* Re: [PATCH v3 11/12] misc: fastrpc: Add dma handle implementation
From: kernel test robot @ 2022-01-26 20:13 UTC (permalink / raw)
To: Srinivas Kandagatla, robh+dt, gregkh
Cc: llvm, kbuild-all, devicetree, ekangupt, bkumar, linux-kernel,
srini, bjorn.andersson, linux-arm-msm, Vamsi Krishna Gattupalli
In-Reply-To: <20220126135304.16340-12-srinivas.kandagatla@linaro.org>
Hi Srinivas,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on char-misc/char-misc-testing]
[also build test WARNING on robh/for-next linux/master linus/master v5.17-rc1 next-20220125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Srinivas-Kandagatla/misc-fastrpc-Add-missing-DSP-FastRPC-features/20220126-215705
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git 515a2f507491e7c3818e74ef4f4e088c1fecb190
config: hexagon-randconfig-r041-20220124 (https://download.01.org/0day-ci/archive/20220127/202201270440.GvskN5kg-lkp@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 2a1b7aa016c0f4b5598806205bdfbab1ea2d92c4)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/70d5973b9373ab26b6a1ed520ee07b71c7bdba63
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Srinivas-Kandagatla/misc-fastrpc-Add-missing-DSP-FastRPC-features/20220126-215705
git checkout 70d5973b9373ab26b6a1ed520ee07b71c7bdba63
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=hexagon SHELL=/bin/bash drivers/misc/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/misc/fastrpc.c:1862:13: warning: stack frame size (1256) exceeds limit (1024) in 'fastrpc_device_ioctl' [-Wframe-larger-than]
static long fastrpc_device_ioctl(struct file *file, unsigned int cmd,
^
1 warning generated.
vim +/fastrpc_device_ioctl +1862 drivers/misc/fastrpc.c
b1c0b7969aa4918 Jeya R 2022-01-26 1861
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 @1862 static long fastrpc_device_ioctl(struct file *file, unsigned int cmd,
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1863 unsigned long arg)
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1864 {
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1865 struct fastrpc_user *fl = (struct fastrpc_user *)file->private_data;
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1866 char __user *argp = (char __user *)arg;
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1867 int err;
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1868
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1869 switch (cmd) {
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1870 case FASTRPC_IOCTL_INVOKE:
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1871 err = fastrpc_invoke(fl, argp);
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1872 break;
d73f71c7c6ee158 Srinivas Kandagatla 2019-02-08 1873 case FASTRPC_IOCTL_INIT_ATTACH:
6010d9befc8df89 Jonathan Marek 2020-09-08 1874 err = fastrpc_init_attach(fl, AUDIO_PD);
6010d9befc8df89 Jonathan Marek 2020-09-08 1875 break;
6010d9befc8df89 Jonathan Marek 2020-09-08 1876 case FASTRPC_IOCTL_INIT_ATTACH_SNS:
6010d9befc8df89 Jonathan Marek 2020-09-08 1877 err = fastrpc_init_attach(fl, SENSORS_PD);
d73f71c7c6ee158 Srinivas Kandagatla 2019-02-08 1878 break;
d73f71c7c6ee158 Srinivas Kandagatla 2019-02-08 1879 case FASTRPC_IOCTL_INIT_CREATE:
d73f71c7c6ee158 Srinivas Kandagatla 2019-02-08 1880 err = fastrpc_init_create_process(fl, argp);
d73f71c7c6ee158 Srinivas Kandagatla 2019-02-08 1881 break;
6cffd79504ce040 Srinivas Kandagatla 2019-02-08 1882 case FASTRPC_IOCTL_ALLOC_DMA_BUFF:
6cffd79504ce040 Srinivas Kandagatla 2019-02-08 1883 err = fastrpc_dmabuf_alloc(fl, argp);
6cffd79504ce040 Srinivas Kandagatla 2019-02-08 1884 break;
2419e55e532de14 Jorge Ramirez-Ortiz 2019-10-09 1885 case FASTRPC_IOCTL_MMAP:
2419e55e532de14 Jorge Ramirez-Ortiz 2019-10-09 1886 err = fastrpc_req_mmap(fl, argp);
2419e55e532de14 Jorge Ramirez-Ortiz 2019-10-09 1887 break;
2419e55e532de14 Jorge Ramirez-Ortiz 2019-10-09 1888 case FASTRPC_IOCTL_MUNMAP:
2419e55e532de14 Jorge Ramirez-Ortiz 2019-10-09 1889 err = fastrpc_req_munmap(fl, argp);
2419e55e532de14 Jorge Ramirez-Ortiz 2019-10-09 1890 break;
b1c0b7969aa4918 Jeya R 2022-01-26 1891 case FASTRPC_IOCTL_MEM_MAP:
b1c0b7969aa4918 Jeya R 2022-01-26 1892 err = fastrpc_req_mem_map(fl, argp);
b1c0b7969aa4918 Jeya R 2022-01-26 1893 break;
b1c0b7969aa4918 Jeya R 2022-01-26 1894 case FASTRPC_IOCTL_MEM_UNMAP:
b1c0b7969aa4918 Jeya R 2022-01-26 1895 err = fastrpc_req_mem_unmap(fl, argp);
b1c0b7969aa4918 Jeya R 2022-01-26 1896 break;
a22465bb4904fac Jeya R 2022-01-26 1897 case FASTRPC_IOCTL_GET_DSP_INFO:
a22465bb4904fac Jeya R 2022-01-26 1898 err = fastrpc_get_dsp_info(fl, argp);
a22465bb4904fac Jeya R 2022-01-26 1899 break;
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1900 default:
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1901 err = -ENOTTY;
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1902 break;
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1903 }
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1904
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1905 return err;
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1906 }
c68cfb718c8f97b Srinivas Kandagatla 2019-02-08 1907
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* Re: [PATCH v3 11/12] misc: fastrpc: Add dma handle implementation
From: kernel test robot @ 2022-01-26 20:14 UTC (permalink / raw)
To: Srinivas Kandagatla, robh+dt, gregkh
Cc: kbuild-all, devicetree, ekangupt, bkumar, linux-kernel, srini,
bjorn.andersson, linux-arm-msm, Vamsi Krishna Gattupalli
In-Reply-To: <20220126135304.16340-12-srinivas.kandagatla@linaro.org>
Hi Srinivas,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on char-misc/char-misc-testing]
[also build test WARNING on robh/for-next linux/master linus/master v5.17-rc1 next-20220125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Srinivas-Kandagatla/misc-fastrpc-Add-missing-DSP-FastRPC-features/20220126-215705
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git 515a2f507491e7c3818e74ef4f4e088c1fecb190
config: arc-randconfig-r003-20220126 (https://download.01.org/0day-ci/archive/20220127/202201270412.QDMYUTEr-lkp@intel.com/config)
compiler: arc-elf-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/70d5973b9373ab26b6a1ed520ee07b71c7bdba63
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Srinivas-Kandagatla/misc-fastrpc-Add-missing-DSP-FastRPC-features/20220126-215705
git checkout 70d5973b9373ab26b6a1ed520ee07b71c7bdba63
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arc SHELL=/bin/bash drivers/misc/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/misc/fastrpc.c: In function 'fastrpc_req_mem_unmap_impl':
drivers/misc/fastrpc.c:1761:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
1761 | args[0].ptr = (u64) &req_msg;
| ^
drivers/misc/fastrpc.c: In function 'fastrpc_req_mem_map':
drivers/misc/fastrpc.c:1811:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
1811 | map->va = (void *) req.vaddrin;
| ^
drivers/misc/fastrpc.c:1816:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
1816 | args[0].ptr = (u64) &req_msg;
| ^
drivers/misc/fastrpc.c:1822:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
1822 | args[1].ptr = (u64) &pages;
| ^
drivers/misc/fastrpc.c:1825:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
1825 | args[2].ptr = (u64) &pages;
| ^
drivers/misc/fastrpc.c:1828:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
1828 | args[3].ptr = (u64) &rsp_msg;
| ^
drivers/misc/fastrpc.c: In function 'fastrpc_get_info_from_kernel.constprop':
>> drivers/misc/fastrpc.c:1552:1: warning: the frame size of 1076 bytes is larger than 1024 bytes [-Wframe-larger-than=]
1552 | }
| ^
vim +1552 drivers/misc/fastrpc.c
a22465bb4904fac Jeya R 2022-01-26 1515
a22465bb4904fac Jeya R 2022-01-26 1516 static int fastrpc_get_info_from_kernel(struct fastrpc_ioctl_capability *cap,
a22465bb4904fac Jeya R 2022-01-26 1517 struct fastrpc_user *fl)
a22465bb4904fac Jeya R 2022-01-26 1518 {
a22465bb4904fac Jeya R 2022-01-26 1519 struct fastrpc_channel_ctx *cctx = fl->cctx;
a22465bb4904fac Jeya R 2022-01-26 1520 uint32_t attribute_id = cap->attribute_id;
a22465bb4904fac Jeya R 2022-01-26 1521 uint32_t dsp_attributes[FASTRPC_MAX_DSP_ATTRIBUTES];
a22465bb4904fac Jeya R 2022-01-26 1522 unsigned long flags;
a22465bb4904fac Jeya R 2022-01-26 1523 uint32_t domain = cap->domain;
a22465bb4904fac Jeya R 2022-01-26 1524 int err;
a22465bb4904fac Jeya R 2022-01-26 1525
a22465bb4904fac Jeya R 2022-01-26 1526 spin_lock_irqsave(&cctx->lock, flags);
a22465bb4904fac Jeya R 2022-01-26 1527 /* check if we already have queried dsp for attributes */
a22465bb4904fac Jeya R 2022-01-26 1528 if (cctx->valid_attributes) {
a22465bb4904fac Jeya R 2022-01-26 1529 spin_unlock_irqrestore(&cctx->lock, flags);
a22465bb4904fac Jeya R 2022-01-26 1530 goto done;
a22465bb4904fac Jeya R 2022-01-26 1531 }
a22465bb4904fac Jeya R 2022-01-26 1532 spin_unlock_irqrestore(&cctx->lock, flags);
a22465bb4904fac Jeya R 2022-01-26 1533
a22465bb4904fac Jeya R 2022-01-26 1534 err = fastrpc_get_info_from_dsp(fl, &dsp_attributes[0], FASTRPC_MAX_DSP_ATTRIBUTES);
a22465bb4904fac Jeya R 2022-01-26 1535 if (err == DSP_UNSUPPORTED_API) {
a22465bb4904fac Jeya R 2022-01-26 1536 dev_info(&cctx->rpdev->dev,
a22465bb4904fac Jeya R 2022-01-26 1537 "Warning: DSP capabilities not supported on domain: %d\n", domain);
a22465bb4904fac Jeya R 2022-01-26 1538 return -EOPNOTSUPP;
a22465bb4904fac Jeya R 2022-01-26 1539 } else if (err) {
a22465bb4904fac Jeya R 2022-01-26 1540 dev_err(&cctx->rpdev->dev, "Error: dsp information is incorrect err: %d\n", err);
a22465bb4904fac Jeya R 2022-01-26 1541 return err;
a22465bb4904fac Jeya R 2022-01-26 1542 }
a22465bb4904fac Jeya R 2022-01-26 1543
a22465bb4904fac Jeya R 2022-01-26 1544 spin_lock_irqsave(&cctx->lock, flags);
a22465bb4904fac Jeya R 2022-01-26 1545 memcpy(cctx->dsp_attributes, dsp_attributes, sizeof(u32) * FASTRPC_MAX_DSP_ATTRIBUTES);
a22465bb4904fac Jeya R 2022-01-26 1546 cctx->valid_attributes = true;
a22465bb4904fac Jeya R 2022-01-26 1547 spin_unlock_irqrestore(&cctx->lock, flags);
a22465bb4904fac Jeya R 2022-01-26 1548 done:
a22465bb4904fac Jeya R 2022-01-26 1549 cap->capability = cctx->dsp_attributes[attribute_id];
a22465bb4904fac Jeya R 2022-01-26 1550
a22465bb4904fac Jeya R 2022-01-26 1551 return 0;
a22465bb4904fac Jeya R 2022-01-26 @1552 }
a22465bb4904fac Jeya R 2022-01-26 1553
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* Re: [RESEND, third time][PATCH] arm64: dts: intel: socfpga_agilex_socdk: align LED node names with dtschema
From: Dinh Nguyen @ 2022-01-26 20:26 UTC (permalink / raw)
To: Krzysztof Kozlowski, Rob Herring, devicetree, linux-kernel
Cc: Krzysztof Kozlowski
In-Reply-To: <20220126174157.288111-1-krzysztof.kozlowski@canonical.com>
On 1/26/22 11:41, Krzysztof Kozlowski wrote:
> From: Krzysztof Kozlowski <krzk@kernel.org>
>
> Align the LED node names with dtschema to silence dtbs_check warnings
> like:
>
> leds: 'hps0', 'hps1', 'hps2' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> ---
>
> This patch waits for a year. Dinh, you previously acked it but can you
> apply it?
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
> index ea37ba7ccff9..26cd3c121757 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
> @@ -21,17 +21,17 @@ chosen {
>
> leds {
> compatible = "gpio-leds";
> - hps0 {
> + led0 {
> label = "hps_led0";
> gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
> };
>
> - hps1 {
> + led1 {
> label = "hps_led1";
> gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
> };
>
> - hps2 {
> + led2 {
> label = "hps_led2";
> gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
> };
Apologies for missing this the first 2 times.
Applied, thanks!
Dinh
^ permalink raw reply
* Re: [PATCH v3 03/12] misc: fastrpc: Add support to get DSP capabilities
From: kernel test robot @ 2022-01-26 21:04 UTC (permalink / raw)
To: Srinivas Kandagatla, robh+dt, gregkh
Cc: kbuild-all, devicetree, ekangupt, bkumar, linux-kernel, srini,
bjorn.andersson, linux-arm-msm, Jeya R
In-Reply-To: <20220126135304.16340-4-srinivas.kandagatla@linaro.org>
Hi Srinivas,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on char-misc/char-misc-testing]
[also build test WARNING on robh/for-next linux/master linus/master v5.17-rc1 next-20220125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Srinivas-Kandagatla/misc-fastrpc-Add-missing-DSP-FastRPC-features/20220126-215705
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git 515a2f507491e7c3818e74ef4f4e088c1fecb190
config: nds32-randconfig-r014-20220126 (https://download.01.org/0day-ci/archive/20220127/202201270435.PxFnOyYn-lkp@intel.com/config)
compiler: nds32le-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/a22465bb4904facca8fe21d23f74410cf6cb1fd0
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Srinivas-Kandagatla/misc-fastrpc-Add-missing-DSP-FastRPC-features/20220126-215705
git checkout a22465bb4904facca8fe21d23f74410cf6cb1fd0
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=nds32 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/misc/fastrpc.c: In function 'fastrpc_req_mem_unmap_impl':
drivers/misc/fastrpc.c:1646:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
1646 | args[0].ptr = (u64) &req_msg;
| ^
drivers/misc/fastrpc.c: In function 'fastrpc_req_mem_map':
drivers/misc/fastrpc.c:1696:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
1696 | map->va = (void *) req.vaddrin;
| ^
drivers/misc/fastrpc.c:1701:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
1701 | args[0].ptr = (u64) &req_msg;
| ^
drivers/misc/fastrpc.c:1707:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
1707 | args[1].ptr = (u64) &pages;
| ^
drivers/misc/fastrpc.c:1710:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
1710 | args[2].ptr = (u64) &pages;
| ^
drivers/misc/fastrpc.c:1713:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
1713 | args[3].ptr = (u64) &rsp_msg;
| ^
drivers/misc/fastrpc.c: In function 'fastrpc_get_info_from_kernel.constprop':
>> drivers/misc/fastrpc.c:1437:1: warning: the frame size of 1080 bytes is larger than 1024 bytes [-Wframe-larger-than=]
1437 | }
| ^
vim +1437 drivers/misc/fastrpc.c
1400
1401 static int fastrpc_get_info_from_kernel(struct fastrpc_ioctl_capability *cap,
1402 struct fastrpc_user *fl)
1403 {
1404 struct fastrpc_channel_ctx *cctx = fl->cctx;
1405 uint32_t attribute_id = cap->attribute_id;
1406 uint32_t dsp_attributes[FASTRPC_MAX_DSP_ATTRIBUTES];
1407 unsigned long flags;
1408 uint32_t domain = cap->domain;
1409 int err;
1410
1411 spin_lock_irqsave(&cctx->lock, flags);
1412 /* check if we already have queried dsp for attributes */
1413 if (cctx->valid_attributes) {
1414 spin_unlock_irqrestore(&cctx->lock, flags);
1415 goto done;
1416 }
1417 spin_unlock_irqrestore(&cctx->lock, flags);
1418
1419 err = fastrpc_get_info_from_dsp(fl, &dsp_attributes[0], FASTRPC_MAX_DSP_ATTRIBUTES);
1420 if (err == DSP_UNSUPPORTED_API) {
1421 dev_info(&cctx->rpdev->dev,
1422 "Warning: DSP capabilities not supported on domain: %d\n", domain);
1423 return -EOPNOTSUPP;
1424 } else if (err) {
1425 dev_err(&cctx->rpdev->dev, "Error: dsp information is incorrect err: %d\n", err);
1426 return err;
1427 }
1428
1429 spin_lock_irqsave(&cctx->lock, flags);
1430 memcpy(cctx->dsp_attributes, dsp_attributes, sizeof(u32) * FASTRPC_MAX_DSP_ATTRIBUTES);
1431 cctx->valid_attributes = true;
1432 spin_unlock_irqrestore(&cctx->lock, flags);
1433 done:
1434 cap->capability = cctx->dsp_attributes[attribute_id];
1435
1436 return 0;
> 1437 }
1438
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* [PATCH v3] dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
From: Lad Prabhakar @ 2022-01-26 21:10 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, devicetree, linux-renesas-soc, linux-kernel,
Prabhakar, Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module
clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and also
add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
("Register configuration") of the RZ/V2L Hardware User's Manual (Rev.1.00,
Nov.2021).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Hi All,
This patch is from series [0]. Just re-sending this patch as
rest are queued.
v2->v3:
* Added DRP core clocks
* Included RB and ACK
[0] https://patchwork.kernel.org/project/linux-renesas-soc/
cover/20220110134659.30424-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
Cheers,
Prabhakar
---
include/dt-bindings/clock/r9a07g054-cpg.h | 229 ++++++++++++++++++++++
1 file changed, 229 insertions(+)
create mode 100644 include/dt-bindings/clock/r9a07g054-cpg.h
diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h
new file mode 100644
index 000000000000..43f4dbda872c
--- /dev/null
+++ b/include/dt-bindings/clock/r9a07g054-cpg.h
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A07G054 CPG Core Clocks */
+#define R9A07G054_CLK_I 0
+#define R9A07G054_CLK_I2 1
+#define R9A07G054_CLK_G 2
+#define R9A07G054_CLK_S0 3
+#define R9A07G054_CLK_S1 4
+#define R9A07G054_CLK_SPI0 5
+#define R9A07G054_CLK_SPI1 6
+#define R9A07G054_CLK_SD0 7
+#define R9A07G054_CLK_SD1 8
+#define R9A07G054_CLK_M0 9
+#define R9A07G054_CLK_M1 10
+#define R9A07G054_CLK_M2 11
+#define R9A07G054_CLK_M3 12
+#define R9A07G054_CLK_M4 13
+#define R9A07G054_CLK_HP 14
+#define R9A07G054_CLK_TSU 15
+#define R9A07G054_CLK_ZT 16
+#define R9A07G054_CLK_P0 17
+#define R9A07G054_CLK_P1 18
+#define R9A07G054_CLK_P2 19
+#define R9A07G054_CLK_AT 20
+#define R9A07G054_OSCCLK 21
+#define R9A07G054_CLK_P0_DIV2 22
+#define R9A07G054_CLK_DRP_M 23
+#define R9A07G054_CLK_DRP_D 24
+#define R9A07G054_CLK_DRP_A 25
+
+/* R9A07G054 Module Clocks */
+#define R9A07G054_CA55_SCLK 0
+#define R9A07G054_CA55_PCLK 1
+#define R9A07G054_CA55_ATCLK 2
+#define R9A07G054_CA55_GICCLK 3
+#define R9A07G054_CA55_PERICLK 4
+#define R9A07G054_CA55_ACLK 5
+#define R9A07G054_CA55_TSCLK 6
+#define R9A07G054_GIC600_GICCLK 7
+#define R9A07G054_IA55_CLK 8
+#define R9A07G054_IA55_PCLK 9
+#define R9A07G054_MHU_PCLK 10
+#define R9A07G054_SYC_CNT_CLK 11
+#define R9A07G054_DMAC_ACLK 12
+#define R9A07G054_DMAC_PCLK 13
+#define R9A07G054_OSTM0_PCLK 14
+#define R9A07G054_OSTM1_PCLK 15
+#define R9A07G054_OSTM2_PCLK 16
+#define R9A07G054_MTU_X_MCK_MTU3 17
+#define R9A07G054_POE3_CLKM_POE 18
+#define R9A07G054_GPT_PCLK 19
+#define R9A07G054_POEG_A_CLKP 20
+#define R9A07G054_POEG_B_CLKP 21
+#define R9A07G054_POEG_C_CLKP 22
+#define R9A07G054_POEG_D_CLKP 23
+#define R9A07G054_WDT0_PCLK 24
+#define R9A07G054_WDT0_CLK 25
+#define R9A07G054_WDT1_PCLK 26
+#define R9A07G054_WDT1_CLK 27
+#define R9A07G054_WDT2_PCLK 28
+#define R9A07G054_WDT2_CLK 29
+#define R9A07G054_SPI_CLK2 30
+#define R9A07G054_SPI_CLK 31
+#define R9A07G054_SDHI0_IMCLK 32
+#define R9A07G054_SDHI0_IMCLK2 33
+#define R9A07G054_SDHI0_CLK_HS 34
+#define R9A07G054_SDHI0_ACLK 35
+#define R9A07G054_SDHI1_IMCLK 36
+#define R9A07G054_SDHI1_IMCLK2 37
+#define R9A07G054_SDHI1_CLK_HS 38
+#define R9A07G054_SDHI1_ACLK 39
+#define R9A07G054_GPU_CLK 40
+#define R9A07G054_GPU_AXI_CLK 41
+#define R9A07G054_GPU_ACE_CLK 42
+#define R9A07G054_ISU_ACLK 43
+#define R9A07G054_ISU_PCLK 44
+#define R9A07G054_H264_CLK_A 45
+#define R9A07G054_H264_CLK_P 46
+#define R9A07G054_CRU_SYSCLK 47
+#define R9A07G054_CRU_VCLK 48
+#define R9A07G054_CRU_PCLK 49
+#define R9A07G054_CRU_ACLK 50
+#define R9A07G054_MIPI_DSI_PLLCLK 51
+#define R9A07G054_MIPI_DSI_SYSCLK 52
+#define R9A07G054_MIPI_DSI_ACLK 53
+#define R9A07G054_MIPI_DSI_PCLK 54
+#define R9A07G054_MIPI_DSI_VCLK 55
+#define R9A07G054_MIPI_DSI_LPCLK 56
+#define R9A07G054_LCDC_CLK_A 57
+#define R9A07G054_LCDC_CLK_P 58
+#define R9A07G054_LCDC_CLK_D 59
+#define R9A07G054_SSI0_PCLK2 60
+#define R9A07G054_SSI0_PCLK_SFR 61
+#define R9A07G054_SSI1_PCLK2 62
+#define R9A07G054_SSI1_PCLK_SFR 63
+#define R9A07G054_SSI2_PCLK2 64
+#define R9A07G054_SSI2_PCLK_SFR 65
+#define R9A07G054_SSI3_PCLK2 66
+#define R9A07G054_SSI3_PCLK_SFR 67
+#define R9A07G054_SRC_CLKP 68
+#define R9A07G054_USB_U2H0_HCLK 69
+#define R9A07G054_USB_U2H1_HCLK 70
+#define R9A07G054_USB_U2P_EXR_CPUCLK 71
+#define R9A07G054_USB_PCLK 72
+#define R9A07G054_ETH0_CLK_AXI 73
+#define R9A07G054_ETH0_CLK_CHI 74
+#define R9A07G054_ETH1_CLK_AXI 75
+#define R9A07G054_ETH1_CLK_CHI 76
+#define R9A07G054_I2C0_PCLK 77
+#define R9A07G054_I2C1_PCLK 78
+#define R9A07G054_I2C2_PCLK 79
+#define R9A07G054_I2C3_PCLK 80
+#define R9A07G054_SCIF0_CLK_PCK 81
+#define R9A07G054_SCIF1_CLK_PCK 82
+#define R9A07G054_SCIF2_CLK_PCK 83
+#define R9A07G054_SCIF3_CLK_PCK 84
+#define R9A07G054_SCIF4_CLK_PCK 85
+#define R9A07G054_SCI0_CLKP 86
+#define R9A07G054_SCI1_CLKP 87
+#define R9A07G054_IRDA_CLKP 88
+#define R9A07G054_RSPI0_CLKB 89
+#define R9A07G054_RSPI1_CLKB 90
+#define R9A07G054_RSPI2_CLKB 91
+#define R9A07G054_CANFD_PCLK 92
+#define R9A07G054_GPIO_HCLK 93
+#define R9A07G054_ADC_ADCLK 94
+#define R9A07G054_ADC_PCLK 95
+#define R9A07G054_TSU_PCLK 96
+#define R9A07G054_STPAI_INITCLK 97
+#define R9A07G054_STPAI_ACLK 98
+#define R9A07G054_STPAI_MCLK 99
+#define R9A07G054_STPAI_DCLKIN 100
+#define R9A07G054_STPAI_ACLK_DRP 101
+
+/* R9A07G054 Resets */
+#define R9A07G054_CA55_RST_1_0 0
+#define R9A07G054_CA55_RST_1_1 1
+#define R9A07G054_CA55_RST_3_0 2
+#define R9A07G054_CA55_RST_3_1 3
+#define R9A07G054_CA55_RST_4 4
+#define R9A07G054_CA55_RST_5 5
+#define R9A07G054_CA55_RST_6 6
+#define R9A07G054_CA55_RST_7 7
+#define R9A07G054_CA55_RST_8 8
+#define R9A07G054_CA55_RST_9 9
+#define R9A07G054_CA55_RST_10 10
+#define R9A07G054_CA55_RST_11 11
+#define R9A07G054_CA55_RST_12 12
+#define R9A07G054_GIC600_GICRESET_N 13
+#define R9A07G054_GIC600_DBG_GICRESET_N 14
+#define R9A07G054_IA55_RESETN 15
+#define R9A07G054_MHU_RESETN 16
+#define R9A07G054_DMAC_ARESETN 17
+#define R9A07G054_DMAC_RST_ASYNC 18
+#define R9A07G054_SYC_RESETN 19
+#define R9A07G054_OSTM0_PRESETZ 20
+#define R9A07G054_OSTM1_PRESETZ 21
+#define R9A07G054_OSTM2_PRESETZ 22
+#define R9A07G054_MTU_X_PRESET_MTU3 23
+#define R9A07G054_POE3_RST_M_REG 24
+#define R9A07G054_GPT_RST_C 25
+#define R9A07G054_POEG_A_RST 26
+#define R9A07G054_POEG_B_RST 27
+#define R9A07G054_POEG_C_RST 28
+#define R9A07G054_POEG_D_RST 29
+#define R9A07G054_WDT0_PRESETN 30
+#define R9A07G054_WDT1_PRESETN 31
+#define R9A07G054_WDT2_PRESETN 32
+#define R9A07G054_SPI_RST 33
+#define R9A07G054_SDHI0_IXRST 34
+#define R9A07G054_SDHI1_IXRST 35
+#define R9A07G054_GPU_RESETN 36
+#define R9A07G054_GPU_AXI_RESETN 37
+#define R9A07G054_GPU_ACE_RESETN 38
+#define R9A07G054_ISU_ARESETN 39
+#define R9A07G054_ISU_PRESETN 40
+#define R9A07G054_H264_X_RESET_VCP 41
+#define R9A07G054_H264_CP_PRESET_P 42
+#define R9A07G054_CRU_CMN_RSTB 43
+#define R9A07G054_CRU_PRESETN 44
+#define R9A07G054_CRU_ARESETN 45
+#define R9A07G054_MIPI_DSI_CMN_RSTB 46
+#define R9A07G054_MIPI_DSI_ARESET_N 47
+#define R9A07G054_MIPI_DSI_PRESET_N 48
+#define R9A07G054_LCDC_RESET_N 49
+#define R9A07G054_SSI0_RST_M2_REG 50
+#define R9A07G054_SSI1_RST_M2_REG 51
+#define R9A07G054_SSI2_RST_M2_REG 52
+#define R9A07G054_SSI3_RST_M2_REG 53
+#define R9A07G054_SRC_RST 54
+#define R9A07G054_USB_U2H0_HRESETN 55
+#define R9A07G054_USB_U2H1_HRESETN 56
+#define R9A07G054_USB_U2P_EXL_SYSRST 57
+#define R9A07G054_USB_PRESETN 58
+#define R9A07G054_ETH0_RST_HW_N 59
+#define R9A07G054_ETH1_RST_HW_N 60
+#define R9A07G054_I2C0_MRST 61
+#define R9A07G054_I2C1_MRST 62
+#define R9A07G054_I2C2_MRST 63
+#define R9A07G054_I2C3_MRST 64
+#define R9A07G054_SCIF0_RST_SYSTEM_N 65
+#define R9A07G054_SCIF1_RST_SYSTEM_N 66
+#define R9A07G054_SCIF2_RST_SYSTEM_N 67
+#define R9A07G054_SCIF3_RST_SYSTEM_N 68
+#define R9A07G054_SCIF4_RST_SYSTEM_N 69
+#define R9A07G054_SCI0_RST 70
+#define R9A07G054_SCI1_RST 71
+#define R9A07G054_IRDA_RST 72
+#define R9A07G054_RSPI0_RST 73
+#define R9A07G054_RSPI1_RST 74
+#define R9A07G054_RSPI2_RST 75
+#define R9A07G054_CANFD_RSTP_N 76
+#define R9A07G054_CANFD_RSTC_N 77
+#define R9A07G054_GPIO_RSTN 78
+#define R9A07G054_GPIO_PORT_RESETN 79
+#define R9A07G054_GPIO_SPARE_RESETN 80
+#define R9A07G054_ADC_PRESETN 81
+#define R9A07G054_ADC_ADRST_N 82
+#define R9A07G054_TSU_PRESETN 83
+#define R9A07G054_STPAI_ARESETN 84
+
+#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
--
2.17.1
^ permalink raw reply related
* [PATCH] dt-bindings: net: convert net/cortina,gemini-ethernet to yaml
From: Corentin Labbe @ 2022-01-26 21:11 UTC (permalink / raw)
To: davem, kuba, linus.walleij, robh+dt, ulli.kroll
Cc: devicetree, linux-arm-kernel, linux-kernel, netdev,
Corentin Labbe
Converts net/cortina,gemini-ethernet.txt to yaml
This permits to detect some missing properties like interrupts
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
.../bindings/net/cortina,gemini-ethernet.txt | 92 ------------
.../bindings/net/cortina,gemini-ethernet.yaml | 138 ++++++++++++++++++
2 files changed, 138 insertions(+), 92 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
create mode 100644 Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml
diff --git a/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt b/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
deleted file mode 100644
index 6c559981d110..000000000000
--- a/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt
+++ /dev/null
@@ -1,92 +0,0 @@
-Cortina Systems Gemini Ethernet Controller
-==========================================
-
-This ethernet controller is found in the Gemini SoC family:
-StorLink SL3512 and SL3516, also known as Cortina Systems
-CS3512 and CS3516.
-
-Required properties:
-- compatible: must be "cortina,gemini-ethernet"
-- reg: must contain the global registers and the V-bit and A-bit
- memory areas, in total three register sets.
-- syscon: a phandle to the system controller
-- #address-cells: must be specified, must be <1>
-- #size-cells: must be specified, must be <1>
-- ranges: should be state like this giving a 1:1 address translation
- for the subnodes
-
-The subnodes represents the two ethernet ports in this device.
-They are not independent of each other since they share resources
-in the parent node, and are thus children.
-
-Required subnodes:
-- port0: contains the resources for ethernet port 0
-- port1: contains the resources for ethernet port 1
-
-Required subnode properties:
-- compatible: must be "cortina,gemini-ethernet-port"
-- reg: must contain two register areas: the DMA/TOE memory and
- the GMAC memory area of the port
-- interrupts: should contain the interrupt line of the port.
- this is nominally a level interrupt active high.
-- resets: this must provide an SoC-integrated reset line for
- the port.
-- clocks: this should contain a handle to the PCLK clock for
- clocking the silicon in this port
-- clock-names: must be "PCLK"
-
-Optional subnode properties:
-- phy-mode: see ethernet.txt
-- phy-handle: see ethernet.txt
-
-Example:
-
-mdio-bus {
- (...)
- phy0: ethernet-phy@1 {
- reg = <1>;
- device_type = "ethernet-phy";
- };
- phy1: ethernet-phy@3 {
- reg = <3>;
- device_type = "ethernet-phy";
- };
-};
-
-
-ethernet@60000000 {
- compatible = "cortina,gemini-ethernet";
- reg = <0x60000000 0x4000>, /* Global registers, queue */
- <0x60004000 0x2000>, /* V-bit */
- <0x60006000 0x2000>; /* A-bit */
- syscon = <&syscon>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- gmac0: ethernet-port@0 {
- compatible = "cortina,gemini-ethernet-port";
- reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
- <0x6000a000 0x2000>; /* Port 0 GMAC */
- interrupt-parent = <&intcon>;
- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&syscon GEMINI_RESET_GMAC0>;
- clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
- clock-names = "PCLK";
- phy-mode = "rgmii";
- phy-handle = <&phy0>;
- };
-
- gmac1: ethernet-port@1 {
- compatible = "cortina,gemini-ethernet-port";
- reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
- <0x6000e000 0x2000>; /* Port 1 GMAC */
- interrupt-parent = <&intcon>;
- interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&syscon GEMINI_RESET_GMAC1>;
- clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
- clock-names = "PCLK";
- phy-mode = "rgmii";
- phy-handle = <&phy1>;
- };
-};
diff --git a/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml b/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml
new file mode 100644
index 000000000000..294977fd32f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml
@@ -0,0 +1,138 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cortina Systems Gemini Ethernet Controller
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+ This ethernet controller is found in the Gemini SoC family:
+ StorLink SL3512 and SL3516, also known as Cortina Systems
+ CS3512 and CS3516.
+
+properties:
+ compatible:
+ const: cortina,gemini-ethernet
+
+ reg:
+ minItems: 3
+ description: must contain the global registers and the V-bit and A-bit
+ memory areas, in total three register sets.
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+#The subnodes represents the two ethernet ports in this device.
+#They are not independent of each other since they share resources
+#in the parent node, and are thus children.
+patternProperties:
+ "^ethernet-port@[0-9]+$":
+ type: object
+ description: contains the resources for ethernet port
+ allOf:
+ - $ref: ethernet-controller.yaml#
+ properties:
+ compatible:
+ const: cortina,gemini-ethernet-port
+
+ reg:
+ minItems: 2
+ items:
+ - description: DMA/TOE memory
+ - description: GMAC memory area of the port
+
+ interrupts:
+ maxItems: 1
+ description: should contain the interrupt line of the port.
+ this is nominally a level interrupt active high.
+
+ resets:
+ maxItems: 1
+ description: this must provide an SoC-integrated reset line for the port.
+
+ clocks:
+ maxItems: 1
+ description: this should contain a handle to the PCLK clock for
+ clocking the silicon in this port
+
+ clock-names:
+ const: PCLK
+
+ required:
+ - reg
+ - compatible
+ - interrupts
+ - resets
+ - clocks
+ - clock-names
+
+required:
+ - compatible
+ - reg
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/cortina,gemini-clock.h>
+ #include <dt-bindings/reset/cortina,gemini-reset.h>
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ device_type = "ethernet-phy";
+ };
+ phy1: ethernet-phy@3 {
+ reg = <3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+
+ ethernet@60000000 {
+ compatible = "cortina,gemini-ethernet";
+ reg = <0x60000000 0x4000>, /* Global registers, queue */
+ <0x60004000 0x2000>, /* V-bit */
+ <0x60006000 0x2000>; /* A-bit */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gmac0: ethernet-port@0 {
+ compatible = "cortina,gemini-ethernet-port";
+ reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
+ <0x6000a000 0x2000>; /* Port 0 GMAC */
+ interrupt-parent = <&intcon>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&syscon GEMINI_RESET_GMAC0>;
+ clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
+ clock-names = "PCLK";
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+ };
+
+ gmac1: ethernet-port@1 {
+ compatible = "cortina,gemini-ethernet-port";
+ reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
+ <0x6000e000 0x2000>; /* Port 1 GMAC */
+ interrupt-parent = <&intcon>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&syscon GEMINI_RESET_GMAC1>;
+ clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
+ clock-names = "PCLK";
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ };
+ };
--
2.34.1
^ permalink raw reply related
* Re: [RFC PATCH 0/2] Multicolor PWM LED support
From: Jacek Anaszewski @ 2022-01-26 21:26 UTC (permalink / raw)
To: Sven Schwermer, linux-leds, devicetree, linux-pwm
Cc: Sven Schwermer, pavel, robh+dt, thierry.reding, u.kleine-koenig,
lee.jones
In-Reply-To: <70bfabe5-7f53-5c80-e1de-dc73e85232de@svenschwermer.de>
Hi Sven,
On 1/26/22 8:51 AM, Sven Schwermer wrote:
> Hi Jacek,
>
> Thank you for your feedback!
>
> On 1/25/22 23:31, Jacek Anaszewski wrote:
>
>>> 1. Currently, the max-brightness property is expected as a
>>> property to
>>> the multi-led node. That seems consistent with the existing
>>> multicolor class code, but I'm wondering whether it would make
>>> sense to have a max-brigthness for the individual LEDs as well?
>>
>> For the proper mixed color calculation all sub-leds should have
>> the same max_brightness as the global max_brightness.
>>
>> Look at how sub-led intensities are calculated in
>> led_mc_calc_color_components().
>>
>> See also [0] and [1].
>
> OK, thanks. That makes sense.
>
>>> 2. The current multi-led node definition calls for a node index which
>>> would in turn require the reg property to be set within the node.
>>> In this context, that doesn't seem to make sense. Should this
>>> requirement be lifted from leds-class-multicolor.yaml?
>>
>> reg is required for all DT nodes with address unit in the name.
>> If you skipped the address unit, then reg would be also not required.
>
> Yes, I realize this. However, leds-class-multicolor.yaml [0] requires
> the address unit: "^multi-led@([0-9a-f])$"
This is only an example and nothing prevents you from dropping address
unit in leds-pwm-multicolor DT bindings. We don't have common DT parser
for multicolor LEDs and it will be hard to come up with something that
will fit neatly for all possible LED controllers anyway.
Dropping address unit from leds-class-multicolor.yaml would be too much
since it is useful in some cases, see e.g. [2].
[2] Documentation/devicetree/bindings/leds/leds-lp50xx.yaml
--
Best regards,
Jacek Anaszewski
^ permalink raw reply
* Re: [PATCH] dt-bindings: watchdog: brcm,bcm7038: add more compatible strings
From: Rob Herring @ 2022-01-26 22:10 UTC (permalink / raw)
To: Rafał Miłecki
Cc: linux-arm-kernel, devicetree, Florian Fainelli, Rob Herring,
bcm-kernel-feedback-list, Rafał Miłecki,
Wim Van Sebroeck, Guenter Roeck, Justin Chen, linux-watchdog
In-Reply-To: <20220126132116.11070-1-zajec5@gmail.com>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 1904 bytes --]
On Wed, 26 Jan 2022 14:21:16 +0100, Rafał Miłecki wrote:
> From: Rafał Miłecki <rafal@milecki.pl>
>
> This hardware block is used on almost all BCM63xx family chipsets and
> BCM4908 which reuses a lot of BCM63xx parts. Add relevant compatible
> strings and also include a generic one.
>
> The only SoC with a different block I found is BCM6838 (thus not included
> in this change).
>
> It may be worth noting that BCM6338, BCM6345, BCM6348 and BCM63268 don't
> include "SoftRst" register but that can be handled by drivers based on
> precise compatible string.
>
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
> ---
> .../bindings/watchdog/brcm,bcm7038-wdt.yaml | 21 +++++++++++++++----
> 1 file changed, 17 insertions(+), 4 deletions(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mfd/brcm,twd.example.dt.yaml: timer-mfd@ff800400: watchdog@28:compatible: ['brcm,bcm7038-wdt'] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mfd/brcm,twd.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mfd/brcm,twd.example.dt.yaml: watchdog@28: compatible: ['brcm,bcm7038-wdt'] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1584464
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply
* Re: [PATCH v19 1/3] dt-bindings: input: Add bindings for Mediatek matrix keypad
From: Rob Herring @ 2022-01-26 22:10 UTC (permalink / raw)
To: Mattijs Korpershoek
Cc: linux-arm-kernel, Yingjoe Chen, Fengping Yu, Matthias Brugger,
devicetree, Dmitry Torokhov, linux-kernel, Fabien Parent,
Kevin Hilman, Marco Felsch, linux-mediatek, linux-input,
Rob Herring, Andy Shevchenko
In-Reply-To: <20220126153519.3637496-2-mkorpershoek@baylibre.com>
On Wed, 26 Jan 2022 16:35:17 +0100, Mattijs Korpershoek wrote:
> From: "fengping.yu" <fengping.yu@mediatek.com>
>
> This patch add devicetree bindings for Mediatek matrix keypad driver.
>
> Signed-off-by: fengping.yu <fengping.yu@mediatek.com>
> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
> Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
> ---
> .../input/mediatek,mt6779-keypad.yaml | 80 +++++++++++++++++++
> 1 file changed, 80 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml:28:13: [warning] wrong indentation: expected 14 but found 12 (indentation)
./Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml:43:8: [warning] wrong indentation: expected 6 but found 7 (indentation)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1584526
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: timer: Convert faraday,fttmr010 to yaml
From: Rob Herring @ 2022-01-26 22:10 UTC (permalink / raw)
To: Corentin Labbe; +Cc: linux-kernel, daniel.lezcano, robh+dt, devicetree, tglx
In-Reply-To: <20220126160021.3537591-1-clabbe@baylibre.com>
On Wed, 26 Jan 2022 16:00:21 +0000, Corentin Labbe wrote:
> Converts timer/faraday,fttmr010.txt to yaml.
>
> Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
> ---
> Changes since v1:
> - added moxart example
> - relaxed some contraints as driver only support one clock and one
> interrupt (as used by moxa,moxart-timer)
>
> .../bindings/timer/faraday,fttmr010.txt | 38 --------
> .../bindings/timer/faraday,fttmr010.yaml | 88 +++++++++++++++++++
> 2 files changed, 88 insertions(+), 38 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/timer/faraday,fttmr010.txt
> create mode 100644 Documentation/devicetree/bindings/timer/faraday,fttmr010.yaml
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1584531
timer@1e782000: interrupts-extended: [[1, 0, 16, 4], [1, 0, 17, 4], [1, 0, 18, 4], [1, 0, 19, 4], [1, 0, 20, 4], [1, 0, 21, 4], [1, 0, 22, 4], [1, 0, 23, 4]] is too long
arch/arm/boot/dts/aspeed-ast2600-evb-a1.dt.yaml
arch/arm/boot/dts/aspeed-ast2600-evb.dt.yaml
arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dt.yaml
arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dt.yaml
arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dt.yaml
arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dt.yaml
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dt.yaml
arch/arm/boot/dts/aspeed-bmc-ibm-rainier-1s4u.dt.yaml
arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dt.yaml
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dt.yaml
arch/arm/boot/dts/aspeed-bmc-inventec-transformers.dt.yaml
arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dt.yaml
timer@1e782000: '#pwm-cells', 'fttmr010,pwm-outputs' do not match any of the regexes: 'pinctrl-[0-9]+'
arch/arm/boot/dts/aspeed-bmc-vegman-n110.dt.yaml
arch/arm/boot/dts/aspeed-bmc-vegman-rx20.dt.yaml
arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dt.yaml
^ permalink raw reply
* Re: [PATCH 17/27] dt-bindings: display: rockchip: Add binding for VOP2
From: Rob Herring @ 2022-01-26 22:10 UTC (permalink / raw)
To: Sascha Hauer
Cc: Michael Riesch, Sandy Huang, Heiko Stübner, kernel,
dri-devel, Andy Yan, linux-arm-kernel, devicetree,
Benjamin Gaignard, linux-rockchip, Peter Geis
In-Reply-To: <20220126145549.617165-18-s.hauer@pengutronix.de>
On Wed, 26 Jan 2022 15:55:39 +0100, Sascha Hauer wrote:
> The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566.
> The binding differs slightly from the existing VOP binding, so add a new
> binding file for it.
>
> Changes since v3:
> - drop redundant _vop suffix from clock names
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> .../display/rockchip/rockchip-vop2.yaml | 146 ++++++++++++++++++
> 1 file changed, 146 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.example.dt.yaml: vop@fe040000: clock-names:0: 'aclk' was expected
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.example.dt.yaml: vop@fe040000: clock-names:1: 'hclk' was expected
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1584511
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply
* Re: [PATCH] dt-bindings: hwmon: gpio-fan: convert to YAML
From: Rob Herring @ 2022-01-26 22:10 UTC (permalink / raw)
To: Corentin Labbe
Cc: linux-kernel, linux, linux-hwmon, devicetree, robh+dt, jdelvare
In-Reply-To: <20220126200350.3633576-1-clabbe@baylibre.com>
On Wed, 26 Jan 2022 20:03:50 +0000, Corentin Labbe wrote:
> Converts hwmon/gpio-fan.txt to YAML
>
> Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
> ---
>
> I didnt found any clear maintainer and since DT yaml mandates a
> maintainer section, I set devicetree@vger.kernel.org.
>
> .../devicetree/bindings/hwmon/gpio-fan.txt | 41 --------
> .../devicetree/bindings/hwmon/gpio-fan.yaml | 96 +++++++++++++++++++
> 2 files changed, 96 insertions(+), 41 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/hwmon/gpio-fan.txt
> create mode 100644 Documentation/devicetree/bindings/hwmon/gpio-fan.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/hwmon/gpio-fan.example.dt.yaml:0:0: /example-0/gpio@4d000000: failed to match any schema with compatible: ['cortina,gemini-gpio', 'faraday,ftgpio010']
Documentation/devicetree/bindings/hwmon/gpio-fan.example.dt.yaml:0:0: /example-0/gpio@4d000000: failed to match any schema with compatible: ['cortina,gemini-gpio', 'faraday,ftgpio010']
Documentation/devicetree/bindings/hwmon/gpio-fan.example.dt.yaml:0:0: /example-1/gpio@4d000000: failed to match any schema with compatible: ['cortina,gemini-gpio', 'faraday,ftgpio010']
Documentation/devicetree/bindings/hwmon/gpio-fan.example.dt.yaml:0:0: /example-1/gpio@4d000000: failed to match any schema with compatible: ['cortina,gemini-gpio', 'faraday,ftgpio010']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1584654
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply
* Re: [PATCH v4 2/4] dt-bindings: usb: dwc3-imx8mp: Add imx8mp specific flags
From: Rob Herring @ 2022-01-26 22:10 UTC (permalink / raw)
To: Alexander Stein
Cc: Greg Kroah-Hartman, Shawn Guo, devicetree, Sascha Hauer,
linux-usb, NXP Linux Team, linux-arm-kernel, Li Jun, Rob Herring,
Fabio Estevam
In-Reply-To: <20220126141340.234125-3-alexander.stein@ew.tq-group.com>
On Wed, 26 Jan 2022 15:13:38 +0100, Alexander Stein wrote:
> This adds bindings for features in the USB glue block. They allow
> setting polarity of PWR and OC as well as disabling port power control.
> Also permanently attached can be annotated as well.
> Additional IO address and clock are needed.
>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
> .../bindings/usb/fsl,imx8mp-dwc3.yaml | 31 ++++++++++++++++---
> 1 file changed, 27 insertions(+), 4 deletions(-)
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1584490
usb@32f10100: reg: [[854655232, 8]] is too short
arch/arm64/boot/dts/freescale/imx8mp-evk.dt.yaml
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dt.yaml
usb@32f10108: reg: [[854655240, 8]] is too short
arch/arm64/boot/dts/freescale/imx8mp-evk.dt.yaml
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dt.yaml
^ permalink raw reply
* Re: [PATCH v4 3/5] dt-bindings: bus: add device tree bindings for qcom,ssc-block-bus
From: Rob Herring @ 2022-01-26 22:10 UTC (permalink / raw)
To: michael.srba
Cc: Andy Gross, Stephen Boyd, Michael Srba, Arnd Bergmann,
Saravana Kannan, Bjorn Andersson, Philipp Zabel, Linus Walleij,
linux-arm-msm, Florian Fainelli, Rob Herring, Greg Kroah-Hartman,
devicetree, linux-clk
In-Reply-To: <20220126183250.11924-3-michael.srba@seznam.cz>
On Wed, 26 Jan 2022 19:32:48 +0100, michael.srba@seznam.cz wrote:
> From: Michael Srba <Michael.Srba@seznam.cz>
>
> This patch adds bindings for the AHB bus which exposes the SCC block in
> the global address space. This bus (and the SSC block itself) is present
> on certain qcom SoCs.
>
> In typical configuration, this bus (as some of the clocks and registers
> that we need to manipulate) is not accessible to the OS, and the
> resources on this bus are indirectly accessed by communicating with a
> hexagon CPU core residing in the SSC block. In this configuration, the
> hypervisor is the one performing the bus initialization for the purposes
> of bringing the haxagon CPU core out of reset.
>
> However, it is possible to change the configuration, in which case this
> binding serves to allow the OS to initialize the bus.
>
> Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
> ---
> CHANGES:
> - v2: fix issues caught by by dt-schema
> - v3: none
> - v4: address the issues pointed out in the review
> ---
> .../bindings/bus/qcom,ssc-block-bus.yaml | 150 ++++++++++++++++++
> 1 file changed, 150 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml:86:9: [warning] wrong indentation: expected 10 but found 8 (indentation)
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.example.dt.yaml:0:0: /example-0/soc/bus@10ac008/pinctrl@5e10000: failed to match any schema with compatible: ['qcom,msm8998-ssc-tlmm-pinctrl']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1584622
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply
* [PATCH 0/8] Add ethernet support for Qualcomm SA8155p-ADP board
From: Bhupesh Sharma @ 2022-01-26 22:17 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
agross, sboyd, tdas, mturquette, linux-clk, bjorn.andersson,
davem, netdev
The SA8155p-ADP board supports on-board ethernet (Gibabit Interface),
with support for both RGMII and RMII buses.
This patchset adds the support for the same.
Note that this patchset is based on an earlier sent patchset
for adding PDC controller support on SM8150 (see [1]).
[1]. https://lore.kernel.org/linux-arm-msm/20220119203133.467264-1-bhupesh.sharma@linaro.org/T
Bhupesh Sharma (3):
clk: qcom: gcc: Add PCIe, EMAC and UFS GDSCs for SM8150
clk: qcom: gcc-sm8150: use runtime PM for the clock controller
clk: qcom: gcc-sm8150: Use PWRSTS_ON (only) as a workaround for emac
gdsc
Bjorn Andersson (1):
net: stmmac: dwmac-qcom-ethqos: Adjust rgmii loopback_en per platform
Vinod Koul (4):
dt-bindings: net: qcom,ethqos: Document SM8150 SoC compatible
net: stmmac: Add support for SM8150
arm64: dts: qcom: sm8150: add ethernet node
arm64: dts: qcom: sa8155p-adp: Enable ethernet node
.../devicetree/bindings/net/qcom,ethqos.txt | 4 +-
arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 144 ++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 27 ++++
drivers/clk/qcom/gcc-sm8150.c | 105 +++++++++++--
.../stmicro/stmmac/dwmac-qcom-ethqos.c | 37 ++++-
include/dt-bindings/clock/qcom,gcc-sm8150.h | 9 +-
6 files changed, 305 insertions(+), 21 deletions(-)
--
2.34.1
^ permalink raw reply
* [PATCH 1/8] dt-bindings: net: qcom,ethqos: Document SM8150 SoC compatible
From: Bhupesh Sharma @ 2022-01-26 22:17 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
agross, sboyd, tdas, mturquette, linux-clk, bjorn.andersson,
davem, netdev, Vinod Koul, Rob Herring
In-Reply-To: <20220126221725.710167-1-bhupesh.sharma@linaro.org>
From: Vinod Koul <vkoul@kernel.org>
SM8150 has a ethernet controller and needs a different configuration so
add a new compatible for this
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
Documentation/devicetree/bindings/net/qcom,ethqos.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/qcom,ethqos.txt b/Documentation/devicetree/bindings/net/qcom,ethqos.txt
index fcf5035810b5..1f5746849a71 100644
--- a/Documentation/devicetree/bindings/net/qcom,ethqos.txt
+++ b/Documentation/devicetree/bindings/net/qcom,ethqos.txt
@@ -7,7 +7,9 @@ This device has following properties:
Required properties:
-- compatible: Should be qcom,qcs404-ethqos"
+- compatible: Should be one of:
+ "qcom,qcs404-ethqos"
+ "qcom,sm8150-ethqos"
- reg: Address and length of the register set for the device
--
2.34.1
^ permalink raw reply related
* [PATCH 2/8] net: stmmac: Add support for SM8150
From: Bhupesh Sharma @ 2022-01-26 22:17 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
agross, sboyd, tdas, mturquette, linux-clk, bjorn.andersson,
davem, netdev, Vinod Koul
In-Reply-To: <20220126221725.710167-1-bhupesh.sharma@linaro.org>
From: Vinod Koul <vkoul@kernel.org>
This adds compatible, POR config & driver data for ethernet controller
found in SM8150 SoC.
Cc: David S. Miller <davem@davemloft.net>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
[bhsharma: Massage the commit log and other cosmetic changes]
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
.../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 2ffa0a11eea5..8cdba9d521ec 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -183,6 +183,20 @@ static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
.num_por = ARRAY_SIZE(emac_v2_3_0_por),
};
+static const struct ethqos_emac_por emac_v2_1_0_por[] = {
+ { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 },
+ { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
+ { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
+ { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
+ { .offset = SDCC_USR_CTL, .value = 0x00010800 },
+ { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
+};
+
+static const struct ethqos_emac_driver_data emac_v2_1_0_data = {
+ .por = emac_v2_1_0_por,
+ .num_por = ARRAY_SIZE(emac_v2_1_0_por),
+};
+
static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
{
unsigned int val;
@@ -558,6 +572,7 @@ static int qcom_ethqos_remove(struct platform_device *pdev)
static const struct of_device_id qcom_ethqos_match[] = {
{ .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
+ { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
{ }
};
MODULE_DEVICE_TABLE(of, qcom_ethqos_match);
--
2.34.1
^ permalink raw reply related
* [PATCH 3/8] clk: qcom: gcc: Add PCIe, EMAC and UFS GDSCs for SM8150
From: Bhupesh Sharma @ 2022-01-26 22:17 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
agross, sboyd, tdas, mturquette, linux-clk, bjorn.andersson,
davem, netdev
In-Reply-To: <20220126221725.710167-1-bhupesh.sharma@linaro.org>
This adds the PCIe, EMAC and UFS GDSC structures for
SM8150. The GDSC will allow the respective system to be
brought out of reset.
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
drivers/clk/qcom/gcc-sm8150.c | 74 +++++++++++++++++----
include/dt-bindings/clock/qcom,gcc-sm8150.h | 9 ++-
2 files changed, 69 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index 245794485719..ada755ad55f7 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -3448,22 +3448,67 @@ static struct clk_branch gcc_video_xo_clk = {
},
};
+static struct gdsc emac_gdsc = {
+ .gdscr = 0x6004,
+ .pd = {
+ .name = "emac_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc pcie_0_gdsc = {
+ .gdscr = 0x6b004,
+ .pd = {
+ .name = "pcie_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc pcie_1_gdsc = {
+ .gdscr = 0x8d004,
+ .pd = {
+ .name = "pcie_1_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc ufs_card_gdsc = {
+ .gdscr = 0x75004,
+ .pd = {
+ .name = "ufs_card_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc ufs_phy_gdsc = {
+ .gdscr = 0x77004,
+ .pd = {
+ .name = "ufs_phy_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR,
+};
+
static struct gdsc usb30_prim_gdsc = {
- .gdscr = 0xf004,
- .pd = {
- .name = "usb30_prim_gdsc",
- },
- .pwrsts = PWRSTS_OFF_ON,
- .flags = POLL_CFG_GDSCR,
+ .gdscr = 0xf004,
+ .pd = {
+ .name = "usb30_prim_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR,
};
static struct gdsc usb30_sec_gdsc = {
- .gdscr = 0x10004,
- .pd = {
- .name = "usb30_sec_gdsc",
- },
- .pwrsts = PWRSTS_OFF_ON,
- .flags = POLL_CFG_GDSCR,
+ .gdscr = 0x10004,
+ .pd = {
+ .name = "usb30_sec_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR,
};
static struct clk_regmap *gcc_sm8150_clocks[] = {
@@ -3714,6 +3759,11 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = {
};
static struct gdsc *gcc_sm8150_gdscs[] = {
+ [EMAC_GDSC] = &emac_gdsc,
+ [PCIE_0_GDSC] = &pcie_0_gdsc,
+ [PCIE_1_GDSC] = &pcie_1_gdsc,
+ [UFS_CARD_GDSC] = &ufs_card_gdsc,
+ [UFS_PHY_GDSC] = &ufs_phy_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
};
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
index 3e1a91876610..35d80ae411a0 100644
--- a/include/dt-bindings/clock/qcom,gcc-sm8150.h
+++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
@@ -241,7 +241,12 @@
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
/* GCC GDSCRs */
-#define USB30_PRIM_GDSC 4
-#define USB30_SEC_GDSC 5
+#define EMAC_GDSC 0
+#define PCIE_0_GDSC 1
+#define PCIE_1_GDSC 2
+#define UFS_CARD_GDSC 3
+#define UFS_PHY_GDSC 4
+#define USB30_PRIM_GDSC 5
+#define USB30_SEC_GDSC 6
#endif
--
2.34.1
^ permalink raw reply related
* [PATCH 4/8] arm64: dts: qcom: sm8150: add ethernet node
From: Bhupesh Sharma @ 2022-01-26 22:17 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
agross, sboyd, tdas, mturquette, linux-clk, bjorn.andersson,
davem, netdev, Vinod Koul
In-Reply-To: <20220126221725.710167-1-bhupesh.sharma@linaro.org>
From: Vinod Koul <vkoul@kernel.org>
SM8150 SoC supports ethqos ethernet controller so add the node for it
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
[bhsharma: Correct ethernet interrupt numbers and add power-domain]
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 463732bcfc07..70cf4651598a 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -915,6 +915,33 @@ gpi_dma0: dma-controller@800000 {
status = "disabled";
};
+ ethernet: ethernet@20000 {
+ compatible = "qcom,sm8150-ethqos";
+ reg = <0x0 0x00020000 0x0 0x10000>,
+ <0x0 0x00036000 0x0 0x100>;
+ reg-names = "stmmaceth", "rgmii";
+ clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
+ clocks = <&gcc GCC_EMAC_AXI_CLK>,
+ <&gcc GCC_EMAC_SLV_AHB_CLK>,
+ <&gcc GCC_EMAC_PTP_CLK>,
+ <&gcc GCC_EMAC_RGMII_CLK>;
+ interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
+
+ power-domains = <&gcc EMAC_GDSC>;
+ resets = <&gcc GCC_EMAC_BCR>;
+
+ iommus = <&apps_smmu 0x3C0 0x0>;
+
+ snps,tso;
+ rx-fifo-depth = <4096>;
+ tx-fifo-depth = <4096>;
+
+ status = "disabled";
+ };
+
+
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
--
2.34.1
^ permalink raw reply related
* [PATCH 5/8] arm64: dts: qcom: sa8155p-adp: Enable ethernet node
From: Bhupesh Sharma @ 2022-01-26 22:17 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
agross, sboyd, tdas, mturquette, linux-clk, bjorn.andersson,
davem, netdev, Vinod Koul
In-Reply-To: <20220126221725.710167-1-bhupesh.sharma@linaro.org>
From: Vinod Koul <vkoul@kernel.org>
Enable the etheret node, add the phy node and pinctrl for ethernet.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
[bhsharma: Correct ethernet/rgmii related pinmuxs, specify multi-queues and
plug in the PHY interrupt for WOL]
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 144 +++++++++++++++++++++++
1 file changed, 144 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
index 8756c2b25c7e..474f688f14a2 100644
--- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
@@ -47,6 +47,65 @@ vreg_s4a_1p8: smps4 {
vin-supply = <&vreg_3p3>;
};
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <4>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ snps,route-up;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ snps,route-ptp;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ snps,route-avcp;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ snps,priority = <0xC>;
+ };
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+ snps,tx-sched-wrr;
+
+ queue0 {
+ snps,weight = <0x10>;
+ snps,dcb-algorithm;
+ snps,priority = <0x0>;
+ };
+
+ queue1 {
+ snps,weight = <0x11>;
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ };
+
+ queue2 {
+ snps,weight = <0x12>;
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ };
+
+ queue3 {
+ snps,weight = <0x13>;
+ snps,dcb-algorithm;
+ snps,priority = <0x3>;
+ };
+ };
};
&apps_rsc {
@@ -317,6 +376,42 @@ &remoteproc_cdsp {
firmware-name = "qcom/sa8155p/cdsp.mdt";
};
+ðernet {
+ status = "okay";
+
+ snps,reset-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 11000 70000>;
+
+ snps,ptp-ref-clk-rate = <250000000>;
+ snps,ptp-req-clk-rate = <96000000>;
+
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet_defaults>;
+
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii";
+ mdio {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ compatible = "snps,dwmac-mdio";
+
+ /* Micrel KSZ9031RNZ PHY */
+ rgmii_phy: phy@7 {
+ reg = <0x7>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */
+ device_type = "ethernet-phy";
+ compatible = "ethernet-phy-ieee802.3-c22";
+ };
+ };
+};
+
&uart2 {
status = "okay";
};
@@ -407,4 +502,53 @@ mux {
drive-strength = <2>;
};
};
+
+ ethernet_defaults: ethernet-defaults {
+ mdc {
+ pins = "gpio7";
+ function = "rgmii";
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio59";
+ function = "rgmii";
+ bias-pull-up;
+ };
+
+ rgmii-rx {
+ pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116";
+ function = "rgmii";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ rgmii-tx {
+ pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121";
+ function = "rgmii";
+ bias-pull-up;
+ drive-strength = <16>;
+ };
+
+ phy-intr {
+ pins = "gpio124";
+ function = "emac_phy";
+ bias-disable;
+ drive-strength = <8>;
+ };
+
+ pps {
+ pins = "gpio81";
+ function = "emac_pps";
+ bias-disable;
+ drive-strength = <8>;
+ };
+
+ phy-reset {
+ pins = "gpio79";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <16>;
+ };
+ };
};
--
2.34.1
^ permalink raw reply related
* [PATCH 6/8] net: stmmac: dwmac-qcom-ethqos: Adjust rgmii loopback_en per platform
From: Bhupesh Sharma @ 2022-01-26 22:17 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
agross, sboyd, tdas, mturquette, linux-clk, bjorn.andersson,
davem, netdev
In-Reply-To: <20220126221725.710167-1-bhupesh.sharma@linaro.org>
From: Bjorn Andersson <bjorn.andersson@linaro.org>
Not all platforms should have RGMII_CONFIG_LOOPBACK_EN and the result it
about 50% packet loss on incoming messages. So make it possile to
configure this per compatible and enable it for QCS404.
Cc: David S. Miller <davem@davemloft.net>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
.../stmicro/stmmac/dwmac-qcom-ethqos.c | 22 +++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 8cdba9d521ec..0cc28c79cc61 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -78,6 +78,7 @@ struct ethqos_emac_por {
struct ethqos_emac_driver_data {
const struct ethqos_emac_por *por;
unsigned int num_por;
+ bool rgmii_config_looback_en;
};
struct qcom_ethqos {
@@ -90,6 +91,7 @@ struct qcom_ethqos {
const struct ethqos_emac_por *por;
unsigned int num_por;
+ bool rgmii_config_looback_en;
};
static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
@@ -181,6 +183,7 @@ static const struct ethqos_emac_por emac_v2_3_0_por[] = {
static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
.por = emac_v2_3_0_por,
.num_por = ARRAY_SIZE(emac_v2_3_0_por),
+ .rgmii_config_looback_en = true,
};
static const struct ethqos_emac_por emac_v2_1_0_por[] = {
@@ -195,6 +198,7 @@ static const struct ethqos_emac_por emac_v2_1_0_por[] = {
static const struct ethqos_emac_driver_data emac_v2_1_0_data = {
.por = emac_v2_1_0_por,
.num_por = ARRAY_SIZE(emac_v2_1_0_por),
+ .rgmii_config_looback_en = false,
};
static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
@@ -311,8 +315,12 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
SDCC_DDR_CONFIG_PRG_DLY_EN,
SDCC_HC_REG_DDR_CONFIG);
- rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
- RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
+ if (ethqos->rgmii_config_looback_en)
+ rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
+ RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
+ else
+ rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
+ 0, RGMII_IO_MACRO_CONFIG);
break;
case SPEED_100:
@@ -345,8 +353,13 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
SDCC_HC_REG_DDR_CONFIG);
- rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
- RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
+ if (ethqos->rgmii_config_looback_en)
+ rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
+ RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
+ else
+ rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
+ 0, RGMII_IO_MACRO_CONFIG);
+
break;
case SPEED_10:
@@ -518,6 +531,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
data = of_device_get_match_data(&pdev->dev);
ethqos->por = data->por;
ethqos->num_por = data->num_por;
+ ethqos->rgmii_config_looback_en = data->rgmii_config_looback_en;
ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii");
if (IS_ERR(ethqos->rgmii_clk)) {
--
2.34.1
^ permalink raw reply related
* [PATCH 8/8] clk: qcom: gcc-sm8150: Use PWRSTS_ON (only) as a workaround for emac gdsc
From: Bhupesh Sharma @ 2022-01-26 22:17 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
agross, sboyd, tdas, mturquette, linux-clk, bjorn.andersson,
davem, netdev
In-Reply-To: <20220126221725.710167-1-bhupesh.sharma@linaro.org>
EMAC GDSC currently has issues (seen on SA8155p-ADP) when its
turn'ed ON, once its already in OFF state. So, use PWRSTS_ON
state (only) as a workaround for now.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
drivers/clk/qcom/gcc-sm8150.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index 2e71afed81fd..fd7e931d3c09 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -3449,12 +3449,16 @@ static struct clk_branch gcc_video_xo_clk = {
},
};
+/* To Do: EMAC GDSC currently has issues when its turn'ed ON, once
+ * its already in OFF state. So use PWRSTS_ON state (only) as a
+ * workaround for now.
+ */
static struct gdsc emac_gdsc = {
.gdscr = 0x6004,
.pd = {
.name = "emac_gdsc",
},
- .pwrsts = PWRSTS_OFF_ON,
+ .pwrsts = PWRSTS_ON,
.flags = POLL_CFG_GDSCR,
};
--
2.34.1
^ permalink raw reply related
* [PATCH 7/8] clk: qcom: gcc-sm8150: use runtime PM for the clock controller
From: Bhupesh Sharma @ 2022-01-26 22:17 UTC (permalink / raw)
To: linux-arm-msm
Cc: bhupesh.sharma, bhupesh.linux, linux-kernel, devicetree, robh+dt,
agross, sboyd, tdas, mturquette, linux-clk, bjorn.andersson,
davem, netdev
In-Reply-To: <20220126221725.710167-1-bhupesh.sharma@linaro.org>
On sm8150 emac clk registers are powered up by the GDSC power
domain. Use runtime PM calls to make sure that required power domain is
powered on while we access clock controller's registers.
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
drivers/clk/qcom/gcc-sm8150.c | 27 +++++++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index ada755ad55f7..2e71afed81fd 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -5,6 +5,7 @@
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
@@ -3792,19 +3793,41 @@ static const struct of_device_id gcc_sm8150_match_table[] = {
};
MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
+static void gcc_sm8150_pm_runtime_disable(void *data)
+{
+ pm_runtime_disable(data);
+}
+
static int gcc_sm8150_probe(struct platform_device *pdev)
{
struct regmap *regmap;
+ int ret;
+
+ pm_runtime_enable(&pdev->dev);
+
+ ret = devm_add_action_or_reset(&pdev->dev, gcc_sm8150_pm_runtime_disable, &pdev->dev);
+ if (ret)
+ return ret;
+
+ ret = pm_runtime_resume_and_get(&pdev->dev);
+ if (ret)
+ return ret;
regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
- if (IS_ERR(regmap))
+ if (IS_ERR(regmap)) {
+ pm_runtime_put(&pdev->dev);
return PTR_ERR(regmap);
+ }
/* Disable the GPLL0 active input to NPU and GPU via MISC registers */
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
- return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
+ ret = qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
+
+ pm_runtime_put(&pdev->dev);
+
+ return ret;
}
static struct platform_driver gcc_sm8150_driver = {
--
2.34.1
^ permalink raw reply related
* [PATCH V2] dt-bindings: watchdog: brcm,bcm7038: add more compatible strings
From: Rafał Miłecki @ 2022-01-26 22:20 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Florian Fainelli,
Justin Chen
Cc: linux-watchdog, devicetree, linux-arm-kernel,
bcm-kernel-feedback-list, Rafał Miłecki
In-Reply-To: <20220126132116.11070-1-zajec5@gmail.com>
From: Rafał Miłecki <rafal@milecki.pl>
This hardware block is used on almost all BCM63xx family chipsets and
BCM4908 which reuses a lot of BCM63xx parts. Add relevant compatible
strings and also include a generic one.
The only SoC with a different block I found is BCM6838 (thus not included
in this change).
It may be worth noting that BCM6338, BCM6345, BCM6348 and BCM63268 don't
include "SoftRst" register but that can be handled by drivers based on
precise compatible string.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---
V2: Sort enum entries & update brcm,twd.yaml
---
.../devicetree/bindings/mfd/brcm,twd.yaml | 2 +-
.../bindings/watchdog/brcm,bcm7038-wdt.yaml | 21 +++++++++++++++----
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/brcm,twd.yaml b/Documentation/devicetree/bindings/mfd/brcm,twd.yaml
index 634526f790b8..3f5db1990aba 100644
--- a/Documentation/devicetree/bindings/mfd/brcm,twd.yaml
+++ b/Documentation/devicetree/bindings/mfd/brcm,twd.yaml
@@ -55,7 +55,7 @@ examples:
#size-cells = <1>;
watchdog@28 {
- compatible = "brcm,bcm7038-wdt";
+ compatible = "brcm,bcm4908-wdt", "brcm,bcm63xx-wdt";
reg = <0x28 0x8>;
};
};
diff --git a/Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.yaml b/Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.yaml
index a926809352b8..4d848442913c 100644
--- a/Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.yaml
@@ -16,9 +16,22 @@ maintainers:
properties:
compatible:
- enum:
- - brcm,bcm6345-wdt
- - brcm,bcm7038-wdt
+ items:
+ - enum:
+ - brcm,bcm4908-wdt
+ - brcm,bcm6338-wdt
+ - brcm,bcm6345-wdt
+ - brcm,bcm6348-wdt
+ - brcm,bcm6848-wdt
+ - brcm,bcm6858-wdt
+ - brcm,bcm7038-wdt
+ - brcm,bcm60333-wdt
+ - brcm,bcm63138-wdt
+ - brcm,bcm63148-wdt
+ - brcm,bcm63268-wdt
+ - brcm,bcm63381-wdt
+ - brcm,bcm68360-wdt
+ - const: brcm,bcm63xx-wdt
reg:
maxItems: 1
@@ -37,7 +50,7 @@ required:
examples:
- |
watchdog@f040a7e8 {
- compatible = "brcm,bcm7038-wdt";
+ compatible = "brcm,bcm7038-wdt", "brcm,bcm63xx-wdt";
reg = <0xf040a7e8 0x16>;
clocks = <&upg_fixed>;
};
--
2.31.1
^ permalink raw reply related
* Re: [PATCH 7/8] clk: qcom: gcc-sm8150: use runtime PM for the clock controller
From: Dmitry Baryshkov @ 2022-01-26 22:34 UTC (permalink / raw)
To: Bhupesh Sharma
Cc: linux-arm-msm, bhupesh.linux, linux-kernel, devicetree, robh+dt,
agross, sboyd, tdas, mturquette, linux-clk, bjorn.andersson,
davem, netdev
In-Reply-To: <20220126221725.710167-8-bhupesh.sharma@linaro.org>
On Thu, 27 Jan 2022 at 01:19, Bhupesh Sharma <bhupesh.sharma@linaro.org> wrote:
>
> On sm8150 emac clk registers are powered up by the GDSC power
> domain. Use runtime PM calls to make sure that required power domain is
> powered on while we access clock controller's registers.
>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
> drivers/clk/qcom/gcc-sm8150.c | 27 +++++++++++++++++++++++++--
> 1 file changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> index ada755ad55f7..2e71afed81fd 100644
> --- a/drivers/clk/qcom/gcc-sm8150.c
> +++ b/drivers/clk/qcom/gcc-sm8150.c
> @@ -5,6 +5,7 @@
> #include <linux/bitops.h>
> #include <linux/err.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> @@ -3792,19 +3793,41 @@ static const struct of_device_id gcc_sm8150_match_table[] = {
> };
> MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
>
> +static void gcc_sm8150_pm_runtime_disable(void *data)
> +{
> + pm_runtime_disable(data);
> +}
> +
> static int gcc_sm8150_probe(struct platform_device *pdev)
> {
> struct regmap *regmap;
> + int ret;
> +
> + pm_runtime_enable(&pdev->dev);
> +
> + ret = devm_add_action_or_reset(&pdev->dev, gcc_sm8150_pm_runtime_disable, &pdev->dev);
> + if (ret)
> + return ret;
Please use devm_pm_runtime_enable() instead.
> +
> + ret = pm_runtime_resume_and_get(&pdev->dev);
> + if (ret)
> + return ret;
>
> regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
> - if (IS_ERR(regmap))
> + if (IS_ERR(regmap)) {
> + pm_runtime_put(&pdev->dev);
> return PTR_ERR(regmap);
> + }
>
> /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
> regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
> regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
>
> - return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
> + ret = qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
> +
> + pm_runtime_put(&pdev->dev);
> +
> + return ret;
> }
>
> static struct platform_driver gcc_sm8150_driver = {
> --
> 2.34.1
>
--
With best wishes
Dmitry
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