* [PATCH net-next v3 0/3] Cadence MACB/GEM support for ZynqMP SGMII
From: Robert Hancock @ 2022-01-27 0:27 UTC (permalink / raw)
To: netdev
Cc: davem, kuba, robh+dt, michal.simek, nicolas.ferre, claudiu.beznea,
devicetree, Robert Hancock
Changes to allow SGMII mode to work properly in the GEM driver on the
Xilinx ZynqMP platform.
Changes since v2:
-fixed missing includes in DT binding example
-fixed phy_init and phy_power_on error handling/cleanup, moved
phy_power_on to open rather than probe
Changes since v1:
-changed order of controller reset and PHY init as per suggestion
-switched device reset to be optional
-updated bindings doc patch for switch to YAML
Robert Hancock (3):
dt-bindings: net: cdns,macb: added generic PHY and reset mappings for
ZynqMP
net: macb: Added ZynqMP-specific initialization
arm64: dts: zynqmp: Added GEM reset definitions
.../devicetree/bindings/net/cdns,macb.yaml | 56 +++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 +++
drivers/net/ethernet/cadence/macb.h | 5 ++
drivers/net/ethernet/cadence/macb_main.c | 53 +++++++++++++++++-
4 files changed, 120 insertions(+), 2 deletions(-)
--
2.31.1
^ permalink raw reply
* [PATCH net-next v3 3/3] arm64: dts: zynqmp: Added GEM reset definitions
From: Robert Hancock @ 2022-01-27 0:27 UTC (permalink / raw)
To: netdev
Cc: davem, kuba, robh+dt, michal.simek, nicolas.ferre, claudiu.beznea,
devicetree, Robert Hancock
In-Reply-To: <20220127002711.3632101-1-robert.hancock@calian.com>
The Cadence GEM/MACB driver now utilizes the platform-level reset on the
ZynqMP platform. Add reset definitions to the ZynqMP platform device
tree to allow this to be used.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 74e66443e4ce..9bec3ba20c69 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -512,6 +512,8 @@ gem0: ethernet@ff0b0000 {
#stream-id-cells = <1>;
iommus = <&smmu 0x874>;
power-domains = <&zynqmp_firmware PD_ETH_0>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
+ reset-names = "gem0_rst";
};
gem1: ethernet@ff0c0000 {
@@ -526,6 +528,8 @@ gem1: ethernet@ff0c0000 {
#stream-id-cells = <1>;
iommus = <&smmu 0x875>;
power-domains = <&zynqmp_firmware PD_ETH_1>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
+ reset-names = "gem1_rst";
};
gem2: ethernet@ff0d0000 {
@@ -540,6 +544,8 @@ gem2: ethernet@ff0d0000 {
#stream-id-cells = <1>;
iommus = <&smmu 0x876>;
power-domains = <&zynqmp_firmware PD_ETH_2>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
+ reset-names = "gem2_rst";
};
gem3: ethernet@ff0e0000 {
@@ -554,6 +560,8 @@ gem3: ethernet@ff0e0000 {
#stream-id-cells = <1>;
iommus = <&smmu 0x877>;
power-domains = <&zynqmp_firmware PD_ETH_3>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
+ reset-names = "gem3_rst";
};
gpio: gpio@ff0a0000 {
--
2.31.1
^ permalink raw reply related
* Re: [PATCH 6/8] dt-bindings: vendor-prefixes: add LG Electronics
From: Petr Vorel @ 2022-01-27 0:20 UTC (permalink / raw)
To: Luca Weiss, linux-arm-msm, Krzysztof Kozlowski, Rob Herring
Cc: Shawn Guo, Oleksij Rempel, Sam Ravnborg, Linus Walleij,
Daniel Palmer, Max Merchel, Hao Fang, devicetree, linux-kernel,
Jean THOMAS
In-Reply-To: <4f415ca1-6527-5667-01f2-9676f565d670@canonical.com>
Hi all,
> > Hi Krzysztof,
> > On Montag, 13. September 2021 10:49:43 CEST Krzysztof Kozlowski wrote:
> >> On 12/09/2021 01:27, Luca Weiss wrote:
> >>> LG Electronics is a part of the LG Corporation and produces, amongst
> >>> other things, consumer electronics such as phones and smartwatches.
> >> Hi,
> >> Thanks for the patches.
> >> I think "lge" it's the same prefix as "lg". There is no sense in having
> >> multiple vendor prefixes just because company splits inside business
> >> units or subsidiaries. The same as with other conglomerates, e.g.
> >> Samsung - if we wanted to be specific, there will be 4-5 Samsung
> >> vendors... Not mentioning that company organisation is not always
> >> disclosed and can change.
> > I was mostly following qcom-msm8974-lge-nexus5-hammerhead as it's the other LG
> > device tree I am aware of so I've picked lge instead of lg. Also worth noting
> > that Google uses "LGE" in the Android device tree[1] or in the model name in
> > the LG G Watch R kernel sources ("LGE APQ 8026v2 LENOK rev-1.0")
> [1] Does not point to kernel tree. Downstream user could be a good
> argument to switch to lge, but then I would expect correcting other "lg"
> devices which are in fact made by LGE.
> > I don't have a strong opinion either way so I'm fine with either.
> > If we decide to go with "lg" do we want to change the Nexus 5 devicetree
> > (hammerhead) also, that one has the lge name in at least compatible and
> > filename (I don't know how much of a breaking change that would be considered
> > as).
> We would have to add a new one and mark the old compatible as deprecated.
Have we sorted this lg- vs. lge- ?
There are both:
arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
vs
arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts
+ patch flying for msm8992-lg-bullhead-rev-101.dtb
original:
https://lore.kernel.org/linux-arm-msm/20211201231832.188634-1-virgule@jeanthomas.me/
rebased by me:
https://lore.kernel.org/linux-arm-msm/20220113233358.17972-2-petr.vorel@gmail.com/
Kind regards,
Petr
> >> We already have lg for several components, also made by LG Electronics.
> >> What about these?
> >> There is only one device with "lge", added back in 2016 without adding
> >> vendor prefix. I would propose to fix that one, instead of keeping
> >> duplicated "lg".
> >> Best regards,
> >> Krzysztof
> > Regards
> > Luca
> > [1] https://android.googlesource.com/device/lge/hammerhead/
> Best regards,
> Krzysztof
^ permalink raw reply
* Re: [PATCH] ARM: dts: suniv: Add MMC and clock macros.
From: Jesse Taube @ 2022-01-27 0:12 UTC (permalink / raw)
To: Andre Przywara
Cc: devicetree, robh+dt, Mesih Kilinc, Maxime Ripard, Chen-Yu Tsai,
Jernej Skrabec, linux-arm-kernel, linux-sunxi, Chris Morgan
In-Reply-To: <20220126235726.03abdab4@slackpad.fritz.box>
On 1/26/22 18:57, Andre Przywara wrote:
> On Mon, 24 Jan 2022 20:13:52 -0500
> Jesse Taube <mr.bossman075@gmail.com> wrote:
>
> Hi Jesse,
>
> I understand that get_maintainers.pl suggested this CC: list, but you
> should add sunxi people and linux-arm kernel ML. Doing that now.
Uh yeah that makes sense in hind sight.
>> Include clock and reset macros and replace magic numbers.
>> Add MMC node.
>
> This patch itself does not do much, does it? You would at least need to
> enable that in the board dts.
True it doesn't do much just so that its in both u-boot and linux.
> And this should be multiple patches:
> 1) replace numbers with macros (part of this patch)
> 2) Add the MMC compatible string combo to the the bindings doc
> 3) Add the *two* MMC nodes and at least the pinctrl node for MMC0 to the
> SoC .dtsi (partly in this patch)
> 4) Enable the MMC and the card detect pin in the Nano board .dts
>
> I checked that the macros names match the numbers they replace, so
> you can add my R-b: on that patch 1 (if you follow my suggestion).
> The MMC node also seems to look sane.
That seems okay.
>>
>> Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
>
> It is not evident why Mesih's S-o-b: is in here? The patch seems to be
> authored and sent by you? Either you make him the author if that is his
> patch originally, or you put him just as Cc: or in Suggested-by:, maybe.
I did write the patch after I wrote it I was looking at his github and
he had almost the same patch.
> Cheers,
> Andre
>
>> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
>> ---
>> arch/arm/boot/dts/suniv-f1c100s.dtsi | 41 +++++++++++++++++++++++-----
>> 1 file changed, 34 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
>> index 6100d3b75f61..32872bb29917 100644
>> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
>> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
>> @@ -4,6 +4,9 @@
>> * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
>> */
>>
>> +#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
>> +#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
>> +
>> / {
>> #address-cells = <1>;
>> #size-cells = <1>;
>> @@ -82,7 +85,7 @@ pio: pinctrl@1c20800 {
>> compatible = "allwinner,suniv-f1c100s-pinctrl";
>> reg = <0x01c20800 0x400>;
>> interrupts = <38>, <39>, <40>;
>> - clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
>> + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
>> clock-names = "apb", "hosc", "losc";
>> gpio-controller;
>> interrupt-controller;
>> @@ -93,6 +96,11 @@ uart0_pe_pins: uart0-pe-pins {
>> pins = "PE0", "PE1";
>> function = "uart0";
>> };
>> +
>> + mmc0_pins: mmc0-pins {
>> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
>> + function = "mmc0";
>> + };
>> };
>>
>> timer@1c20c00 {
>> @@ -108,14 +116,33 @@ wdt: watchdog@1c20ca0 {
>> reg = <0x01c20ca0 0x20>;
>> };
>>
>> + mmc0: mmc@1c0f000 {
>> + compatible = "allwinner,suniv-f1c100s-mmc",
>> + "allwinner,sun7i-a20-mmc";
>> + reg = <0x01c0f000 0x1000>;
>> + clocks = <&ccu CLK_BUS_MMC0>,
>> + <&ccu CLK_MMC0>,
>> + <&ccu CLK_MMC0_OUTPUT>,
>> + <&ccu CLK_MMC0_SAMPLE>;
>> + clock-names = "ahb", "mmc", "output", "sample";
>> + resets = <&ccu RST_BUS_MMC0>;
>> + reset-names = "ahb";
>> + interrupts = <23>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&mmc0_pins>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> uart0: serial@1c25000 {
>> compatible = "snps,dw-apb-uart";
>> reg = <0x01c25000 0x400>;
>> interrupts = <1>;
>> reg-shift = <2>;
>> reg-io-width = <4>;
>> - clocks = <&ccu 38>;
>> - resets = <&ccu 24>;
>> + clocks = <&ccu CLK_BUS_UART0>;
>> + resets = <&ccu RST_BUS_UART0>;
>> status = "disabled";
>> };
>>
>> @@ -125,8 +152,8 @@ uart1: serial@1c25400 {
>> interrupts = <2>;
>> reg-shift = <2>;
>> reg-io-width = <4>;
>> - clocks = <&ccu 39>;
>> - resets = <&ccu 25>;
>> + clocks = <&ccu CLK_BUS_UART1>;
>> + resets = <&ccu RST_BUS_UART1>;
>> status = "disabled";
>> };
>>
>> @@ -136,8 +163,8 @@ uart2: serial@1c25800 {
>> interrupts = <3>;
>> reg-shift = <2>;
>> reg-io-width = <4>;
>> - clocks = <&ccu 40>;
>> - resets = <&ccu 26>;
>> + clocks = <&ccu CLK_BUS_UART2>;
>> + resets = <&ccu RST_BUS_UART2>;
>> status = "disabled";
>> };
>> };
>
^ permalink raw reply
* Re: [PATCH 5/8] arm64: dts: qcom: sa8155p-adp: Enable ethernet node
From: Andrew Lunn @ 2022-01-27 0:07 UTC (permalink / raw)
To: Bhupesh Sharma
Cc: linux-arm-msm, bhupesh.linux, linux-kernel, devicetree, robh+dt,
agross, sboyd, tdas, mturquette, linux-clk, bjorn.andersson,
davem, netdev, Vinod Koul
In-Reply-To: <20220126221725.710167-6-bhupesh.sharma@linaro.org>
> +ðernet {
> + status = "okay";
> +
> + snps,reset-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
> + snps,reset-active-low;
> + snps,reset-delays-us = <0 11000 70000>;
> +
> + snps,ptp-ref-clk-rate = <250000000>;
> + snps,ptp-req-clk-rate = <96000000>;
> +
> + snps,mtl-rx-config = <&mtl_rx_setup>;
> + snps,mtl-tx-config = <&mtl_tx_setup>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <ðernet_defaults>;
> +
> + phy-handle = <&rgmii_phy>;
> + phy-mode = "rgmii";
Where are the rgmii delays being added for this board?
Andrew
^ permalink raw reply
* Re: [PATCH] ARM: dts: suniv: Add MMC and clock macros.
From: Andre Przywara @ 2022-01-26 23:57 UTC (permalink / raw)
To: Jesse Taube
Cc: devicetree, robh+dt, Mesih Kilinc, Maxime Ripard, Chen-Yu Tsai,
Jernej Skrabec, linux-arm-kernel, linux-sunxi, Chris Morgan
In-Reply-To: <20220125011352.2691365-1-Mr.Bossman075@gmail.com>
On Mon, 24 Jan 2022 20:13:52 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
Hi Jesse,
I understand that get_maintainers.pl suggested this CC: list, but you
should add sunxi people and linux-arm kernel ML. Doing that now.
> Include clock and reset macros and replace magic numbers.
> Add MMC node.
This patch itself does not do much, does it? You would at least need to
enable that in the board dts.
And this should be multiple patches:
1) replace numbers with macros (part of this patch)
2) Add the MMC compatible string combo to the the bindings doc
3) Add the *two* MMC nodes and at least the pinctrl node for MMC0 to the
SoC .dtsi (partly in this patch)
4) Enable the MMC and the card detect pin in the Nano board .dts
I checked that the macros names match the numbers they replace, so
you can add my R-b: on that patch 1 (if you follow my suggestion).
The MMC node also seems to look sane.
>
> Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
It is not evident why Mesih's S-o-b: is in here? The patch seems to be
authored and sent by you? Either you make him the author if that is his
patch originally, or you put him just as Cc: or in Suggested-by:, maybe.
Cheers,
Andre
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> ---
> arch/arm/boot/dts/suniv-f1c100s.dtsi | 41 +++++++++++++++++++++++-----
> 1 file changed, 34 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> index 6100d3b75f61..32872bb29917 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -4,6 +4,9 @@
> * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
> */
>
> +#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
> +#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
> +
> / {
> #address-cells = <1>;
> #size-cells = <1>;
> @@ -82,7 +85,7 @@ pio: pinctrl@1c20800 {
> compatible = "allwinner,suniv-f1c100s-pinctrl";
> reg = <0x01c20800 0x400>;
> interrupts = <38>, <39>, <40>;
> - clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
> + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
> clock-names = "apb", "hosc", "losc";
> gpio-controller;
> interrupt-controller;
> @@ -93,6 +96,11 @@ uart0_pe_pins: uart0-pe-pins {
> pins = "PE0", "PE1";
> function = "uart0";
> };
> +
> + mmc0_pins: mmc0-pins {
> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
> + function = "mmc0";
> + };
> };
>
> timer@1c20c00 {
> @@ -108,14 +116,33 @@ wdt: watchdog@1c20ca0 {
> reg = <0x01c20ca0 0x20>;
> };
>
> + mmc0: mmc@1c0f000 {
> + compatible = "allwinner,suniv-f1c100s-mmc",
> + "allwinner,sun7i-a20-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC0>,
> + <&ccu CLK_MMC0>,
> + <&ccu CLK_MMC0_OUTPUT>,
> + <&ccu CLK_MMC0_SAMPLE>;
> + clock-names = "ahb", "mmc", "output", "sample";
> + resets = <&ccu RST_BUS_MMC0>;
> + reset-names = "ahb";
> + interrupts = <23>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> uart0: serial@1c25000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x01c25000 0x400>;
> interrupts = <1>;
> reg-shift = <2>;
> reg-io-width = <4>;
> - clocks = <&ccu 38>;
> - resets = <&ccu 24>;
> + clocks = <&ccu CLK_BUS_UART0>;
> + resets = <&ccu RST_BUS_UART0>;
> status = "disabled";
> };
>
> @@ -125,8 +152,8 @@ uart1: serial@1c25400 {
> interrupts = <2>;
> reg-shift = <2>;
> reg-io-width = <4>;
> - clocks = <&ccu 39>;
> - resets = <&ccu 25>;
> + clocks = <&ccu CLK_BUS_UART1>;
> + resets = <&ccu RST_BUS_UART1>;
> status = "disabled";
> };
>
> @@ -136,8 +163,8 @@ uart2: serial@1c25800 {
> interrupts = <3>;
> reg-shift = <2>;
> reg-io-width = <4>;
> - clocks = <&ccu 40>;
> - resets = <&ccu 26>;
> + clocks = <&ccu CLK_BUS_UART2>;
> + resets = <&ccu RST_BUS_UART2>;
> status = "disabled";
> };
> };
^ permalink raw reply
* Re: [PATCH v2 1/3] arm64: dts: renesas: Prepare AA1024XD12 panel .dtsi for overlay support
From: Laurent Pinchart @ 2022-01-26 23:57 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rob Herring, Kieran Bingham, Geert Uytterhoeven, Magnus Damm,
Chris Paterson
In-Reply-To: <CAMuHMdW1DwsMTVog4oBa_=ozH=aEeAdK+wS1SbwbZYz22JAL=w@mail.gmail.com>
Hi Geert,
On Wed, Jan 26, 2022 at 08:15:26PM +0100, Geert Uytterhoeven wrote:
> On Wed, Jan 26, 2022 at 7:58 PM Laurent Pinchart wrote:
> > On Wed, Jan 26, 2022 at 01:18:56PM +0100, Geert Uytterhoeven wrote:
> > > On Wed, Dec 29, 2021 at 8:31 PM Laurent Pinchart wrote:
> > > > The Mitsubishi AA1024XD12 panel can be used for R-Car Gen2 and Gen3
> > > > boards as an optional external panel. It is described in the
> > > > arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi file as a direct child of the
> > > > DT root node. This allows including r8a77xx-aa104xd12-panel.dtsi in
> > > > board device trees, with other minor modifications, to enable the panel.
> > > >
> > > > This is however not how external components should be modelled. Instead
> > > > of modifying the board device tree to enable the panel, it should be
> > > > compiled as a DT overlay, to be loaded by the boot loader.
> > > >
> > > > Prepare the r8a77xx-aa104xd12-panel.dtsi file for this usage by
> > > > declaring a panel node only, without hardcoding its path. Overlay
> > > > sources can then include r8a77xx-aa104xd12-panel.dtsi where appropriate.
> > > >
> > > > This change doesn't cause any regression as r8a77xx-aa104xd12-panel.dtsi
> > > > is currently unused. As overlay support for this panel has only been
> > > > tested with Gen3 hardware, and Gen2 support will require more
> > > > development, move the file to arch/arm64/boot/dts/renesas/.
> > > >
> > > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>
> > I see you've reviewed the whole series. Can you pick it up ?
>
> I believe it depends on the removal of the empty endpoints, for which
> we're waiting for feedback from Rob, IIRC?
You're right. Let's wait some more time then.
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH] arm64: dts: meson-sm1-odroid: use correct enable-gpio pin for tf-io regulator
From: Lutz Koschorreck @ 2022-01-26 23:43 UTC (permalink / raw)
To: Rob Herring, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl
Cc: devicetree, linux-arm-kernel, linux-amlogic, linux-kernel
The interrupt pin of the external ethernet phy is used, instead of the
enable-gpio pin of the tf-io regulator. The GPIOE_2 pin is located in
the gpio_ao bank.
Using open drain prevents reboot issues.
This causes phy interrupt problems at system startup.
[ 76.645190] irq 36: nobody cared (try booting with the "irqpoll" option)
[ 76.649617] CPU: 0 PID: 1416 Comm: irq/36-0.0:00 Not tainted 5.16.0 #2
[ 76.649629] Hardware name: Hardkernel ODROID-HC4 (DT)
[ 76.649635] Call trace:
[ 76.649638] dump_backtrace+0x0/0x1c8
[ 76.649658] show_stack+0x14/0x60
[ 76.649667] dump_stack_lvl+0x64/0x7c
[ 76.649676] dump_stack+0x14/0x2c
[ 76.649683] __report_bad_irq+0x38/0xe8
[ 76.649695] note_interrupt+0x220/0x3a0
[ 76.649704] handle_irq_event_percpu+0x58/0x88
[ 76.649713] handle_irq_event+0x44/0xd8
[ 76.649721] handle_fasteoi_irq+0xa8/0x130
[ 76.649730] generic_handle_domain_irq+0x38/0x58
[ 76.649738] gic_handle_irq+0x9c/0xb8
[ 76.649747] call_on_irq_stack+0x28/0x38
[ 76.649755] do_interrupt_handler+0x7c/0x80
[ 76.649763] el1_interrupt+0x34/0x80
[ 76.649772] el1h_64_irq_handler+0x14/0x20
[ 76.649781] el1h_64_irq+0x74/0x78
[ 76.649788] irq_finalize_oneshot.part.56+0x68/0xf8
[ 76.649796] irq_thread_fn+0x5c/0x98
[ 76.649804] irq_thread+0x13c/0x260
[ 76.649812] kthread+0x144/0x178
[ 76.649822] ret_from_fork+0x10/0x20
[ 76.649830] handlers:
[ 76.653170] [<0000000025a6cd31>] irq_default_primary_handler threaded [<0000000093580eb7>] phy_interrupt
[ 76.661256] Disabling IRQ #36
Fixes: 1f80a5cf74a6 ("arm64: dts: meson-sm1-odroid: add missing enable gpio and supply for tf_io regulator")
Signed-off-by: Lutz Koschorreck <theleks@ko-hh.de>
---
arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
index 0bd1e98a0eef..ddb1b345397f 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
@@ -48,7 +48,7 @@ tf_io: gpio-regulator-tf_io {
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_5v>;
- enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
+ enable-gpio = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>;
enable-active-high;
regulator-always-on;
--
2.25.1
^ permalink raw reply related
* [PATCH v8 1/3] usb: dwc3: xilinx: fix uninitialized return value
From: Robert Hancock @ 2022-01-26 23:40 UTC (permalink / raw)
To: linux-usb
Cc: balbi, gregkh, michal.simek, manish.narani, sean.anderson,
robh+dt, devicetree, piyush.mehta, Robert Hancock
In-Reply-To: <20220126234017.3619108-1-robert.hancock@calian.com>
A previous patch to skip part of the initialization when a USB3 PHY was
not present could result in the return value being uninitialized in that
case, causing spurious probe failures. Initialize ret to 0 to avoid this.
Fixes: 9678f3361afc ("usb: dwc3: xilinx: Skip resets and USB3 register settings for USB2.0 mode")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
drivers/usb/dwc3/dwc3-xilinx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
index e14ac15e24c3..a6f3a9b38789 100644
--- a/drivers/usb/dwc3/dwc3-xilinx.c
+++ b/drivers/usb/dwc3/dwc3-xilinx.c
@@ -99,7 +99,7 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
struct device *dev = priv_data->dev;
struct reset_control *crst, *hibrst, *apbrst;
struct phy *usb3_phy;
- int ret;
+ int ret = 0;
u32 reg;
usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
--
2.31.1
^ permalink raw reply related
* [PATCH v8 3/3] usb: dwc3: xilinx: Add ULPI PHY reset handling
From: Robert Hancock @ 2022-01-26 23:40 UTC (permalink / raw)
To: linux-usb
Cc: balbi, gregkh, michal.simek, manish.narani, sean.anderson,
robh+dt, devicetree, piyush.mehta, Robert Hancock
In-Reply-To: <20220126234017.3619108-1-robert.hancock@calian.com>
Hook up an optional GPIO-based reset for the connected USB ULPI PHY
device. This is typically already done by the first-stage boot loader,
however it can be more robust to ensure this reset is done prior to
loading the driver in Linux.
Based on a patch "usb: dwc3: xilinx: Add gpio-reset support" in the
Xilinx kernel tree by Piyush Mehta <piyush.mehta@xilinx.com>.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
drivers/usb/dwc3/dwc3-xilinx.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
index a6f3a9b38789..1ee6011ada44 100644
--- a/drivers/usb/dwc3/dwc3-xilinx.c
+++ b/drivers/usb/dwc3/dwc3-xilinx.c
@@ -11,6 +11,7 @@
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/of.h>
+#include <linux/gpio/consumer.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/of_platform.h>
@@ -101,6 +102,7 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
struct phy *usb3_phy;
int ret = 0;
u32 reg;
+ struct gpio_desc *reset_gpio;
usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
if (IS_ERR(usb3_phy)) {
@@ -110,6 +112,14 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
goto err;
}
+ reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(reset_gpio)) {
+ ret = PTR_ERR(reset_gpio);
+ dev_err_probe(dev, ret,
+ "Failed to get reset gpio\n");
+ goto err;
+ }
+
/*
* The following core resets are not required unless a USB3 PHY
* is used, and the subsequent register settings are not required
@@ -201,6 +211,15 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
}
skip_usb3_phy:
+ /* ulpi reset via gpio-modepin or gpio-framework driver */
+ if (reset_gpio) {
+ /* Toggle ulpi to reset the phy. */
+ gpiod_set_value(reset_gpio, 0);
+ usleep_range(5000, 10000); /* delay */
+ gpiod_set_value(reset_gpio, 1);
+ usleep_range(5000, 10000); /* delay */
+ }
+
/*
* This routes the USB DMA traffic to go through FPD path instead
* of reaching DDR directly. This traffic routing is needed to
--
2.31.1
^ permalink raw reply related
* [PATCH v8 2/3] dt-bindings: usb: dwc3-xilinx: Added reset-gpios
From: Robert Hancock @ 2022-01-26 23:40 UTC (permalink / raw)
To: linux-usb
Cc: balbi, gregkh, michal.simek, manish.narani, sean.anderson,
robh+dt, devicetree, piyush.mehta, Robert Hancock
In-Reply-To: <20220126234017.3619108-1-robert.hancock@calian.com>
Update DT binding to reflect new reset-gpios property.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
index f77c16e203d5..823ce731e95f 100644
--- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
@@ -59,6 +59,10 @@ properties:
- const: usb_hibrst
- const: usb_apbrst
+ reset-gpios:
+ description: Optional GPIO connected to ULPI PHY reset line.
+ maxItems: 1
+
phys:
minItems: 1
maxItems: 2
--
2.31.1
^ permalink raw reply related
* [PATCH v8 0/3] Xilinx ZynqMP USB fixes
From: Robert Hancock @ 2022-01-26 23:40 UTC (permalink / raw)
To: linux-usb
Cc: balbi, gregkh, michal.simek, manish.narani, sean.anderson,
robh+dt, devicetree, piyush.mehta, Robert Hancock
Some fixes related to the Xilinx ZynqMP DWC3 wrapper driver.
Changes since v7:
-Drop patches already merged. Add a patch to fix a bug found in one
of those previous patches.
-Fixed error handling for reset GPIO
Changes since v6:
-skip USB core resets and register settings which are not necessary
when USB3 PHY is not specified
-added patches to implement ULPI PHY reset in driver
Changes since v5:
-code formatting fixes, no functional change
Changes since v4:
-dropped DWC3 core patches as they are superseded by Sean Anderson's
patchset "usb: dwc3: Calculate REFCLKPER et. al. from reference clock",
ZynqMP-specific patches unchanged
Changes since v3:
-fixed DT schema dt-doc-validate error
Changes since v2:
-additional kerneldoc fixes
Changes since v1:
-added DT binding documentation for new attribute
-kerneldoc formatting and reworded comments
*** BLURB HERE ***
Robert Hancock (3):
usb: dwc3: xilinx: fix uninitialized return value
dt-bindings: usb: dwc3-xilinx: Added reset-gpios
usb: dwc3: xilinx: Add ULPI PHY reset handling
.../devicetree/bindings/usb/dwc3-xilinx.yaml | 4 ++++
drivers/usb/dwc3/dwc3-xilinx.c | 21 ++++++++++++++++++-
2 files changed, 24 insertions(+), 1 deletion(-)
--
2.31.1
^ permalink raw reply
* Re: [PATCH v7 1/2] dt-bindings: reserved-memory: Open Profile for DICE
From: David Brazdil @ 2022-01-26 23:19 UTC (permalink / raw)
To: Rob Herring
Cc: Rob Herring, Arnd Bergmann, Frank Rowand, Will Deacon,
Andrew Scull, Wedson Almeida Filho, devicetree, linux-kernel,
Greg Kroah-Hartman
In-Reply-To: <20220126231237.529308-2-dbrazdil@google.com>
Hi Rob,
On Wed, Jan 26, 2022 at 11:12:36PM +0000, David Brazdil wrote:
> Add DeviceTree bindings for Open Profile for DICE, an open protocol for
> measured boot. Firmware uses DICE to measure the hardware/software
> combination and generates Compound Device Identifier (CDI) certificates.
> These are stored in memory and the buffer is described in the DT as
> a reserved memory region compatible with 'google,open-dice'.
>
> 'no-map' is required to ensure the memory region is never treated by
> the kernel as system memory.
>
> Signed-off-by: David Brazdil <dbrazdil@google.com>
> ---
> .../reserved-memory/google,open-dice.yaml | 46 +++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reserved-memory/google,open-dice.yaml
>
> diff --git a/Documentation/devicetree/bindings/reserved-memory/google,open-dice.yaml b/Documentation/devicetree/bindings/reserved-memory/google,open-dice.yaml
> new file mode 100644
> index 000000000000..257a0b51994a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reserved-memory/google,open-dice.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reserved-memory/google,open-dice.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Open Profile for DICE Device Tree Bindings
> +
> +description: |
> + This binding represents a reserved memory region containing data
> + generated by the Open Profile for DICE protocol.
> +
> + See https://pigweed.googlesource.com/open-dice/
> +
> +maintainers:
> + - David Brazdil <dbrazdil@google.com>
> +
> +allOf:
> + - $ref: "reserved-memory.yaml"
> +
> +properties:
> + compatible:
> + const: google,open-dice
> +
> + reg:
> + description: page-aligned region of memory containing DICE data
> +
> +required:
> + - compatible
> + - reg
> + - no-map
You already gave this a Reviewed-by in v6. Just want to mention that I
didn't pick it up because I added a required no-map here. It was always
included in our DTs but I made it required because the kernel should
never treat that region as system memory. The kernel will warn when the
driver tries to wipe the memory otherwise.
David
^ permalink raw reply
* [PATCH] ASoC: dt-bindings: Centralize the 'sound-dai' definition
From: Rob Herring @ 2022-01-26 23:14 UTC (permalink / raw)
To: Jerome Brunet, Liam Girdwood, Mark Brown, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Andy Gross, Bjorn Andersson, Krzysztof Kozlowski,
Sylwester Nawrocki, Rohit kumar, Cheng-Yi Chiang, Shengjiu Wang,
Srinivas Kandagatla, Jonathan Bakker
Cc: Krzysztof Kozlowski, alsa-devel, devicetree, linux-kernel,
linux-arm-kernel, linux-arm-msm
'sound-dai' is a common property, but has duplicate type definitions.
Create a new common definition to define the type and then update all
the other occurrences to just define how many entries there are just
like other phandle+arg properties.
The constraints on the number of entries is based on the examples and
could be wrong.
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
Please ack, this depends on commit abf0fee97313 ("dt-bindings: Improve
phandle-array schemas") in my tree.
---
.../bindings/sound/amlogic,gx-sound-card.yaml | 4 ++--
.../bindings/sound/google,sc7180-trogdor.yaml | 6 ++++--
.../bindings/sound/imx-audio-card.yaml | 7 +++++--
.../bindings/sound/qcom,sm8250.yaml | 10 +++++++---
.../bindings/sound/samsung,aries-wm8994.yaml | 5 +----
.../bindings/sound/samsung,midas-audio.yaml | 2 --
.../bindings/sound/samsung,odroid.yaml | 9 +++------
.../devicetree/bindings/sound/sound-dai.yaml | 20 +++++++++++++++++++
8 files changed, 42 insertions(+), 21 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/sound-dai.yaml
diff --git a/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml b/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml
index 2e35aeaa8781..8b5be4b92f35 100644
--- a/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml
+++ b/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml
@@ -57,7 +57,7 @@ patternProperties:
rate
sound-dai:
- $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
description: phandle of the CPU DAI
patternProperties:
@@ -71,7 +71,7 @@ patternProperties:
properties:
sound-dai:
- $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
description: phandle of the codec DAI
required:
diff --git a/Documentation/devicetree/bindings/sound/google,sc7180-trogdor.yaml b/Documentation/devicetree/bindings/sound/google,sc7180-trogdor.yaml
index 837e3faa63a9..233caa0ade87 100644
--- a/Documentation/devicetree/bindings/sound/google,sc7180-trogdor.yaml
+++ b/Documentation/devicetree/bindings/sound/google,sc7180-trogdor.yaml
@@ -62,13 +62,15 @@ patternProperties:
description: Holds subnode which indicates cpu dai.
type: object
properties:
- sound-dai: true
+ sound-dai:
+ maxItems: 1
codec:
description: Holds subnode which indicates codec dai.
type: object
properties:
- sound-dai: true
+ sound-dai:
+ maxItems: 1
required:
- link-name
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-card.yaml b/Documentation/devicetree/bindings/sound/imx-audio-card.yaml
index d1816dd061cf..bb3a435722c7 100644
--- a/Documentation/devicetree/bindings/sound/imx-audio-card.yaml
+++ b/Documentation/devicetree/bindings/sound/imx-audio-card.yaml
@@ -59,13 +59,16 @@ patternProperties:
description: Holds subnode which indicates cpu dai.
type: object
properties:
- sound-dai: true
+ sound-dai:
+ maxItems: 1
codec:
description: Holds subnode which indicates codec dai.
type: object
properties:
- sound-dai: true
+ sound-dai:
+ minItems: 1
+ maxItems: 2
fsl,mclk-equal-bclk:
description: Indicates mclk can be equal to bclk, especially for sai interface
diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
index 4bfda04b4608..4ecd4080bb96 100644
--- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
+++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml
@@ -69,19 +69,23 @@ patternProperties:
description: Holds subnode which indicates cpu dai.
type: object
properties:
- sound-dai: true
+ sound-dai:
+ maxItems: 1
platform:
description: Holds subnode which indicates platform dai.
type: object
properties:
- sound-dai: true
+ sound-dai:
+ maxItems: 1
codec:
description: Holds subnode which indicates codec dai.
type: object
properties:
- sound-dai: true
+ sound-dai:
+ minItems: 1
+ maxItems: 4
required:
- link-name
diff --git a/Documentation/devicetree/bindings/sound/samsung,aries-wm8994.yaml b/Documentation/devicetree/bindings/sound/samsung,aries-wm8994.yaml
index eb487ed3ca3b..4ffa275b3c49 100644
--- a/Documentation/devicetree/bindings/sound/samsung,aries-wm8994.yaml
+++ b/Documentation/devicetree/bindings/sound/samsung,aries-wm8994.yaml
@@ -27,9 +27,6 @@ properties:
sound-dai:
minItems: 2
maxItems: 2
- items:
- maxItems: 1
- $ref: /schemas/types.yaml#/definitions/phandle-array
description: |
phandles to the I2S controller and bluetooth codec,
in that order
@@ -38,7 +35,7 @@ properties:
type: object
properties:
sound-dai:
- $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
description: phandle to the WM8994 CODEC
samsung,audio-routing:
diff --git a/Documentation/devicetree/bindings/sound/samsung,midas-audio.yaml b/Documentation/devicetree/bindings/sound/samsung,midas-audio.yaml
index 095775c598fa..ec50bcb4af5f 100644
--- a/Documentation/devicetree/bindings/sound/samsung,midas-audio.yaml
+++ b/Documentation/devicetree/bindings/sound/samsung,midas-audio.yaml
@@ -21,7 +21,6 @@ properties:
type: object
properties:
sound-dai:
- $ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
description: phandle to the I2S controller
required:
@@ -31,7 +30,6 @@ properties:
type: object
properties:
sound-dai:
- $ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
description: phandle to the WM1811 CODEC
required:
diff --git a/Documentation/devicetree/bindings/sound/samsung,odroid.yaml b/Documentation/devicetree/bindings/sound/samsung,odroid.yaml
index e8122bc87362..db2513f3e168 100644
--- a/Documentation/devicetree/bindings/sound/samsung,odroid.yaml
+++ b/Documentation/devicetree/bindings/sound/samsung,odroid.yaml
@@ -37,18 +37,15 @@ properties:
type: object
properties:
sound-dai:
- $ref: /schemas/types.yaml#/definitions/phandle-array
description: phandles to the I2S controllers
codec:
type: object
properties:
sound-dai:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- description: |
- List of phandles to the CODEC nodes,
- first entry must be corresponding to the MAX98090 CODEC and
- the second entry must be the phandle of the HDMI IP block node.
+ items:
+ - description: phandle of the MAX98090 CODEC
+ - description: phandle of the HDMI IP block node
samsung,audio-routing:
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
diff --git a/Documentation/devicetree/bindings/sound/sound-dai.yaml b/Documentation/devicetree/bindings/sound/sound-dai.yaml
new file mode 100644
index 000000000000..61c6f7abc4e7
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/sound-dai.yaml
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/sound-dai.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Digital Audio Interface consumer Device Tree Bindings
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+select: true
+
+properties:
+ sound-dai:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: A phandle plus args to digital audio interface provider(s)
+
+additionalProperties: true
+...
--
2.32.0
^ permalink raw reply related
* [PATCH] ASoC: dt-bindings: realtek,rt5682s: Drop Tegra specifics from example
From: Rob Herring @ 2022-01-26 23:13 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Derek Fang
Cc: alsa-devel, devicetree, linux-kernel
There's no need to complicate examples with a platform specific macro.
It also complicates example parsing to figure out the number of interrupt
cells in examples (based on bracketing).
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/sound/realtek,rt5682s.yaml | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/realtek,rt5682s.yaml b/Documentation/devicetree/bindings/sound/realtek,rt5682s.yaml
index d65c0ed5060c..ca5b8987b749 100644
--- a/Documentation/devicetree/bindings/sound/realtek,rt5682s.yaml
+++ b/Documentation/devicetree/bindings/sound/realtek,rt5682s.yaml
@@ -21,6 +21,7 @@ properties:
description: I2C address of the device.
interrupts:
+ maxItems: 1
description: The CODEC's interrupt output.
realtek,dmic1-data-pin:
@@ -94,7 +95,7 @@ required:
examples:
- |
- #include <dt-bindings/gpio/tegra-gpio.h>
+ #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
@@ -104,10 +105,9 @@ examples:
codec@1a {
compatible = "realtek,rt5682s";
reg = <0x1a>;
- interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
realtek,ldo1-en-gpios =
- <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ <&gpio 2 GPIO_ACTIVE_HIGH>;
realtek,dmic1-data-pin = <1>;
realtek,dmic1-clk-pin = <1>;
realtek,jd-src = <1>;
--
2.32.0
^ permalink raw reply related
* [PATCH] spi: dt-bindings: Fix 'reg' child node schema
From: Rob Herring @ 2022-01-26 23:13 UTC (permalink / raw)
To: Mark Brown, Pratyush Yadav; +Cc: linux-spi, devicetree, linux-kernel
The schema for SPI child nodes' 'reg' property is not complete. 'reg' is
a matrix of cells. The schema needs to define both the number of 'reg'
entries and constraints on each entry.
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/spi/spi-peripheral-props.yaml | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
index 5dd209206e88..3ec2d7b83775 100644
--- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
@@ -23,8 +23,9 @@ properties:
minItems: 1
maxItems: 256
items:
- minimum: 0
- maximum: 256
+ items:
+ - minimum: 0
+ maximum: 256
description:
Chip select used by the device.
--
2.32.0
^ permalink raw reply related
* [PATCH] dt-bindings: regulator: maxim,max8973: Drop Tegra specifics from example
From: Rob Herring @ 2022-01-26 23:12 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Krzysztof Kozlowski; +Cc: linux-kernel, devicetree
There's no need to complicate examples with a platform specific macro.
It also complicates example parsing to figure out the number of interrupt
cells in examples (based on the bracketing).
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/regulator/maxim,max8973.yaml | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/regulator/maxim,max8973.yaml b/Documentation/devicetree/bindings/regulator/maxim,max8973.yaml
index 35c53e27f78c..5898dcf10f06 100644
--- a/Documentation/devicetree/bindings/regulator/maxim,max8973.yaml
+++ b/Documentation/devicetree/bindings/regulator/maxim,max8973.yaml
@@ -113,7 +113,7 @@ examples:
};
- |
- #include <dt-bindings/gpio/tegra-gpio.h>
+ #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
@@ -123,8 +123,7 @@ examples:
regulator@1b {
compatible = "maxim,max77621";
reg = <0x1b>;
- interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(Y, 1) IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
regulator-always-on;
regulator-boot-on;
--
2.32.0
^ permalink raw reply related
* [PATCH v7 2/2] misc: open-dice: Add driver to expose DICE data to userspace
From: David Brazdil @ 2022-01-26 23:12 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Rob Herring, Arnd Bergmann, Frank Rowand, David Brazdil,
Will Deacon, Andrew Scull, Wedson Almeida Filho, devicetree,
linux-kernel, Rob Herring
In-Reply-To: <20220126231237.529308-1-dbrazdil@google.com>
Open Profile for DICE is an open protocol for measured boot compatible
with the Trusted Computing Group's Device Identifier Composition
Engine (DICE) specification. The generated Compound Device Identifier
(CDI) certificates represent the hardware/software combination measured
by DICE, and can be used for remote attestation and sealing.
Add a driver that exposes reserved memory regions populated by firmware
with DICE CDIs and exposes them to userspace via a character device.
Userspace obtains the memory region's size from read() and calls mmap()
to create a mapping of the memory region in its address space. The
mapping is not allowed to be write+shared, giving userspace a guarantee
that the data were not overwritten by another process.
Userspace can also call write(), which triggers a wipe of the DICE data
by the driver. Because both the kernel and userspace mappings use
write-combine semantics, all clients observe the memory as zeroed after
the syscall has returned.
Acked-by: Rob Herring <robh@kernel.org>
Cc: Andrew Scull <ascull@google.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: David Brazdil <dbrazdil@google.com>
---
drivers/misc/Kconfig | 12 +++
drivers/misc/Makefile | 1 +
drivers/misc/open-dice.c | 208 +++++++++++++++++++++++++++++++++++++++
drivers/of/platform.c | 1 +
4 files changed, 222 insertions(+)
create mode 100644 drivers/misc/open-dice.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 0f5a49fc7c9e..a2b26426efba 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -470,6 +470,18 @@ config HISI_HIKEY_USB
switching between the dual-role USB-C port and the USB-A host ports
using only one USB controller.
+config OPEN_DICE
+ tristate "Open Profile for DICE driver"
+ depends on OF_RESERVED_MEM
+ help
+ This driver exposes a DICE reserved memory region to userspace via
+ a character device. The memory region contains Compound Device
+ Identifiers (CDIs) generated by firmware as an output of DICE
+ measured boot flow. Userspace can use CDIs for remote attestation
+ and sealing.
+
+ If unsure, say N.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index a086197af544..70e800e9127f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -59,3 +59,4 @@ obj-$(CONFIG_UACCE) += uacce/
obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
obj-$(CONFIG_HI6421V600_IRQ) += hi6421v600-irq.o
+obj-$(CONFIG_OPEN_DICE) += open-dice.o
diff --git a/drivers/misc/open-dice.c b/drivers/misc/open-dice.c
new file mode 100644
index 000000000000..c61be3404c6f
--- /dev/null
+++ b/drivers/misc/open-dice.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021 - Google LLC
+ * Author: David Brazdil <dbrazdil@google.com>
+ *
+ * Driver for Open Profile for DICE.
+ *
+ * This driver takes ownership of a reserved memory region containing data
+ * generated by the Open Profile for DICE measured boot protocol. The memory
+ * contents are not interpreted by the kernel but can be mapped into a userspace
+ * process via a misc device. Userspace can also request a wipe of the memory.
+ *
+ * Userspace can access the data with (w/o error handling):
+ *
+ * fd = open("/dev/open-dice0", O_RDWR);
+ * read(fd, &size, sizeof(unsigned long));
+ * data = mmap(NULL, size, PROT_READ, MAP_PRIVATE, fd, 0);
+ * write(fd, NULL, 0); // wipe
+ * close(fd);
+ */
+
+#include <linux/io.h>
+#include <linux/miscdevice.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/platform_device.h>
+
+#define DRIVER_NAME "open-dice"
+
+struct open_dice_drvdata {
+ struct mutex lock;
+ char name[16];
+ struct reserved_mem *rmem;
+ struct miscdevice misc;
+};
+
+static inline struct open_dice_drvdata *to_open_dice_drvdata(struct file *filp)
+{
+ return container_of(filp->private_data, struct open_dice_drvdata, misc);
+}
+
+static int open_dice_wipe(struct open_dice_drvdata *drvdata)
+{
+ void *kaddr;
+
+ mutex_lock(&drvdata->lock);
+ kaddr = devm_memremap(drvdata->misc.this_device, drvdata->rmem->base,
+ drvdata->rmem->size, MEMREMAP_WC);
+ if (IS_ERR(kaddr)) {
+ mutex_unlock(&drvdata->lock);
+ return PTR_ERR(kaddr);
+ }
+
+ memset(kaddr, 0, drvdata->rmem->size);
+ devm_memunmap(drvdata->misc.this_device, kaddr);
+ mutex_unlock(&drvdata->lock);
+ return 0;
+}
+
+/*
+ * Copies the size of the reserved memory region to the user-provided buffer.
+ */
+static ssize_t open_dice_read(struct file *filp, char __user *ptr, size_t len,
+ loff_t *off)
+{
+ unsigned long val = to_open_dice_drvdata(filp)->rmem->size;
+
+ return simple_read_from_buffer(ptr, len, off, &val, sizeof(val));
+}
+
+/*
+ * Triggers a wipe of the reserved memory region. The user-provided pointer
+ * is never dereferenced.
+ */
+static ssize_t open_dice_write(struct file *filp, const char __user *ptr,
+ size_t len, loff_t *off)
+{
+ if (open_dice_wipe(to_open_dice_drvdata(filp)))
+ return -EIO;
+
+ /* Consume the input buffer. */
+ return len;
+}
+
+/*
+ * Creates a mapping of the reserved memory region in user address space.
+ */
+static int open_dice_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+ struct open_dice_drvdata *drvdata = to_open_dice_drvdata(filp);
+
+ /* Do not allow userspace to modify the underlying data. */
+ if ((vma->vm_flags & VM_WRITE) && (vma->vm_flags & VM_SHARED))
+ return -EPERM;
+
+ /* Ensure userspace cannot acquire VM_WRITE + VM_SHARED later. */
+ if (vma->vm_flags & VM_WRITE)
+ vma->vm_flags &= ~VM_MAYSHARE;
+ else if (vma->vm_flags & VM_SHARED)
+ vma->vm_flags &= ~VM_MAYWRITE;
+
+ /* Create write-combine mapping so all clients observe a wipe. */
+ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+ vma->vm_flags |= VM_DONTCOPY | VM_DONTDUMP;
+ return vm_iomap_memory(vma, drvdata->rmem->base, drvdata->rmem->size);
+}
+
+static const struct file_operations open_dice_fops = {
+ .owner = THIS_MODULE,
+ .read = open_dice_read,
+ .write = open_dice_write,
+ .mmap = open_dice_mmap,
+};
+
+static int __init open_dice_probe(struct platform_device *pdev)
+{
+ static unsigned int dev_idx;
+ struct device *dev = &pdev->dev;
+ struct reserved_mem *rmem;
+ struct open_dice_drvdata *drvdata;
+ int ret;
+
+ rmem = of_reserved_mem_lookup(dev->of_node);
+ if (!rmem) {
+ dev_err(dev, "failed to lookup reserved memory\n");
+ return -EINVAL;
+ }
+
+ if (!rmem->size || (rmem->size > ULONG_MAX)) {
+ dev_err(dev, "invalid memory region size\n");
+ return -EINVAL;
+ }
+
+ if (!PAGE_ALIGNED(rmem->base) || !PAGE_ALIGNED(rmem->size)) {
+ dev_err(dev, "memory region must be page-aligned\n");
+ return -EINVAL;
+ }
+
+ drvdata = devm_kmalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+ if (!drvdata)
+ return -ENOMEM;
+
+ *drvdata = (struct open_dice_drvdata){
+ .lock = __MUTEX_INITIALIZER(drvdata->lock),
+ .rmem = rmem,
+ .misc = (struct miscdevice){
+ .parent = dev,
+ .name = drvdata->name,
+ .minor = MISC_DYNAMIC_MINOR,
+ .fops = &open_dice_fops,
+ .mode = 0600,
+ },
+ };
+
+ /* Index overflow check not needed, misc_register() will fail. */
+ snprintf(drvdata->name, sizeof(drvdata->name), DRIVER_NAME"%u", dev_idx++);
+
+ ret = misc_register(&drvdata->misc);
+ if (ret) {
+ dev_err(dev, "failed to register misc device '%s': %d\n",
+ drvdata->name, ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, drvdata);
+ return 0;
+}
+
+static int open_dice_remove(struct platform_device *pdev)
+{
+ struct open_dice_drvdata *drvdata = platform_get_drvdata(pdev);
+
+ misc_deregister(&drvdata->misc);
+ return 0;
+}
+
+static const struct of_device_id open_dice_of_match[] = {
+ { .compatible = "google,open-dice" },
+ {},
+};
+
+static struct platform_driver open_dice_driver = {
+ .remove = open_dice_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = open_dice_of_match,
+ },
+};
+
+static int __init open_dice_init(void)
+{
+ int ret = platform_driver_probe(&open_dice_driver, open_dice_probe);
+
+ /* DICE regions are optional. Succeed even with zero instances. */
+ return (ret == -ENODEV) ? 0 : ret;
+}
+
+static void __exit open_dice_exit(void)
+{
+ platform_driver_unregister(&open_dice_driver);
+}
+
+module_init(open_dice_init);
+module_exit(open_dice_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("David Brazdil <dbrazdil@google.com>");
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index 793350028906..a16b74f32aa9 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -514,6 +514,7 @@ static const struct of_device_id reserved_mem_matches[] = {
{ .compatible = "qcom,smem" },
{ .compatible = "ramoops" },
{ .compatible = "nvmem-rmem" },
+ { .compatible = "google,open-dice" },
{}
};
--
2.35.0.rc0.227.g00780c9af4-goog
^ permalink raw reply related
* [PATCH v7 1/2] dt-bindings: reserved-memory: Open Profile for DICE
From: David Brazdil @ 2022-01-26 23:12 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Rob Herring, Arnd Bergmann, Frank Rowand, David Brazdil,
Will Deacon, Andrew Scull, Wedson Almeida Filho, devicetree,
linux-kernel
In-Reply-To: <20220126231237.529308-1-dbrazdil@google.com>
Add DeviceTree bindings for Open Profile for DICE, an open protocol for
measured boot. Firmware uses DICE to measure the hardware/software
combination and generates Compound Device Identifier (CDI) certificates.
These are stored in memory and the buffer is described in the DT as
a reserved memory region compatible with 'google,open-dice'.
'no-map' is required to ensure the memory region is never treated by
the kernel as system memory.
Signed-off-by: David Brazdil <dbrazdil@google.com>
---
.../reserved-memory/google,open-dice.yaml | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reserved-memory/google,open-dice.yaml
diff --git a/Documentation/devicetree/bindings/reserved-memory/google,open-dice.yaml b/Documentation/devicetree/bindings/reserved-memory/google,open-dice.yaml
new file mode 100644
index 000000000000..257a0b51994a
--- /dev/null
+++ b/Documentation/devicetree/bindings/reserved-memory/google,open-dice.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reserved-memory/google,open-dice.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Open Profile for DICE Device Tree Bindings
+
+description: |
+ This binding represents a reserved memory region containing data
+ generated by the Open Profile for DICE protocol.
+
+ See https://pigweed.googlesource.com/open-dice/
+
+maintainers:
+ - David Brazdil <dbrazdil@google.com>
+
+allOf:
+ - $ref: "reserved-memory.yaml"
+
+properties:
+ compatible:
+ const: google,open-dice
+
+ reg:
+ description: page-aligned region of memory containing DICE data
+
+required:
+ - compatible
+ - reg
+ - no-map
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ dice: dice@12340000 {
+ compatible = "google,open-dice";
+ reg = <0x00 0x12340000 0x2000>;
+ no-map;
+ };
+ };
--
2.35.0.rc0.227.g00780c9af4-goog
^ permalink raw reply related
* [PATCH v7 0/2] Driver for Open Profile for DICE
From: David Brazdil @ 2022-01-26 23:12 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Rob Herring, Arnd Bergmann, Frank Rowand, David Brazdil,
Will Deacon, Andrew Scull, Wedson Almeida Filho, devicetree,
linux-kernel
Open Profile for DICE is an open protocol for measured boot compatible
with the Trusted Computing Group's Device Identifier Composition
Engine (DICE) specification. The generated Compound Device Identifier
(CDI) certificates represent the measured hardware/software combination
and can be used by userspace for remote attestation and sealing.
This patchset adds DeviceTree bindings for the DICE device referencing
a reserved memory region containing the CDIs, and a driver that exposes
the memory region to userspace via a misc device.
See https://pigweed.googlesource.com/open-dice for more details.
The patches are based on top of v5.17-rc1 and can also be found here:
https://android-kvm.googlesource.com/linux topic/dice_v7
Changes since v6:
* replace spinlock with mutex because devm_memremap can sleep
* prevent write+shared mapping via mprotect/mremap
* fail gracefully when no instances found
* no-map required in DT bindings to ensure mem region not treated as RAM
Changes since v5:
* replaced 'additionalProperties' with 'unevaluatedProperties' in DT YAML
Changes since v4:
* registered compatible in 'reserved_mem_matches'
* removed unnecessary DT node, only reserved-memory
* fixed typos in comments
Changes since v3:
* align with semantics of read/write
* fix kerneldoc warnings
* fix printf format warnings
Changes since v2:
* renamed from 'dice' to 'open-dice'
* replaced ioctls with read/write
* replaced memzero_explicit with memset
* allowed multiple instances
* expanded Kconfig description
Changes since v1:
* converted to miscdevice
* all mappings now write-combine to simplify semantics
* removed atomic state, any attempt at exclusive access
* simplified wipe, applied on ioctl, not on release
* fixed ioctl return value
David Brazdil (2):
dt-bindings: reserved-memory: Open Profile for DICE
misc: open-dice: Add driver to expose DICE data to userspace
.../reserved-memory/google,open-dice.yaml | 46 ++++
drivers/misc/Kconfig | 12 +
drivers/misc/Makefile | 1 +
drivers/misc/open-dice.c | 208 ++++++++++++++++++
drivers/of/platform.c | 1 +
5 files changed, 268 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reserved-memory/google,open-dice.yaml
create mode 100644 drivers/misc/open-dice.c
--
2.35.0.rc0.227.g00780c9af4-goog
^ permalink raw reply
* [PATCH] dt-bindings: iio/adc: qcom,spmi-iadc: Fix 'reg' property in example
From: Rob Herring @ 2022-01-26 23:12 UTC (permalink / raw)
To: Jonathan Cameron, Lars-Peter Clausen; +Cc: linux-iio, devicetree, linux-kernel
The QCom SPMI PMIC child nodes are defined to have a single address cell,
but the example has an erroneous size cell. Remove it.
Signed-off-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml
index 27e3108661c0..2a94db688830 100644
--- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml
@@ -51,7 +51,7 @@ examples:
#size-cells = <0>;
pmic_iadc: adc@3600 {
compatible = "qcom,spmi-iadc";
- reg = <0x3600 0x100>;
+ reg = <0x3600>;
interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>;
qcom,external-resistor-micro-ohms = <10000>;
#io-channel-cells = <1>;
--
2.32.0
^ permalink raw reply related
* [PATCH] dt-bindings: arm,cci-400: Add interrupt controller to example
From: Rob Herring @ 2022-01-26 23:11 UTC (permalink / raw)
To: Lorenzo Pieralisi; +Cc: linux-arm-kernel, devicetree, linux-kernel
In order to parse the 'interrupts' an interrupt provider node is needed.
That is because the example is a full example (starting with root node)
and on those we don't guess and generate a fake provider.
Signed-off-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/arm,cci-400.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/arm,cci-400.yaml b/Documentation/devicetree/bindings/arm/arm,cci-400.yaml
index f8530a50863a..1706134b75a3 100644
--- a/Documentation/devicetree/bindings/arm/arm,cci-400.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,cci-400.yaml
@@ -119,6 +119,11 @@ examples:
arm,hbi = <0x249>;
interrupt-parent = <&gic>;
+ gic: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
/*
* This CCI node corresponds to a CCI component whose control
* registers sits at address 0x000000002c090000.
--
2.32.0
^ permalink raw reply related
* Re: [PATCH v7 4/4] usb: dwc3: xilinx: Add ULPI PHY reset handling
From: Robert Hancock @ 2022-01-26 23:01 UTC (permalink / raw)
To: linux-usb@vger.kernel.org
Cc: robh+dt@kernel.org, sean.anderson@seco.com,
devicetree@vger.kernel.org, michal.simek@xilinx.com,
manish.narani@xilinx.com, balbi@kernel.org,
gregkh@linuxfoundation.org, piyush.mehta@xilinx.com
In-Reply-To: <20220126000253.1586760-5-robert.hancock@calian.com>
On Tue, 2022-01-25 at 18:02 -0600, Robert Hancock wrote:
> Hook up an optional GPIO-based reset for the connected USB ULPI PHY
> device. This is typically already done by the first-stage boot loader,
> however it can be more robust to ensure this reset is done prior to
> loading the driver in Linux.
>
> Based on a patch "usb: dwc3: xilinx: Add gpio-reset support" in the
> Xilinx kernel tree by Piyush Mehta <piyush.mehta@xilinx.com>.
>
> Signed-off-by: Robert Hancock <robert.hancock@calian.com>
> ---
> drivers/usb/dwc3/dwc3-xilinx.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
> index e14ac15e24c3..0778236509bf 100644
> --- a/drivers/usb/dwc3/dwc3-xilinx.c
> +++ b/drivers/usb/dwc3/dwc3-xilinx.c
> @@ -11,6 +11,7 @@
> #include <linux/slab.h>
> #include <linux/clk.h>
> #include <linux/of.h>
> +#include <linux/gpio/consumer.h>
> #include <linux/platform_device.h>
> #include <linux/dma-mapping.h>
> #include <linux/of_platform.h>
> @@ -101,6 +102,7 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx
> *priv_data)
> struct phy *usb3_phy;
> int ret;
> u32 reg;
> + struct gpio_desc *reset_gpio;
>
> usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
> if (IS_ERR(usb3_phy)) {
> @@ -201,6 +203,22 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx
> *priv_data)
> }
>
> skip_usb3_phy:
> + /* ulpi reset via gpio-modepin or gpio-framework driver */
> + reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
> + if (IS_ERR(reset_gpio)) {
> + dev_err_probe(dev, PTR_ERR(reset_gpio),
> + "Failed to bind reset gpio\n");
> + goto err;
>
Just noticed this forgets to set the error code to PTR_ERR(reset_gpio) and
breaks in the deferred probe case. Also, this should be done earlier to avoid
bailing out too late in that case. Will resubmit a new patchset with this fix
for the remaining two patches (first 2 in this series were already merged).
> + }
> +
> + if (reset_gpio) {
> + /* Toggle ulpi to reset the phy. */
> + gpiod_set_value(reset_gpio, 0);
> + usleep_range(5000, 10000); /* delay */
> + gpiod_set_value(reset_gpio, 1);
> + usleep_range(5000, 10000); /* delay */
> + }
> +
> /*
> * This routes the USB DMA traffic to go through FPD path instead
> * of reaching DDR directly. This traffic routing is needed to
--
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
www.calian.com
^ permalink raw reply
* Re: [PATCH v19 1/3] dt-bindings: input: Add bindings for Mediatek matrix keypad
From: Rob Herring @ 2022-01-26 22:44 UTC (permalink / raw)
To: Mattijs Korpershoek
Cc: Dmitry Torokhov, Andy Shevchenko, Marco Felsch, Matthias Brugger,
Fengping Yu, Yingjoe Chen, Fabien Parent, Kevin Hilman,
Linux Input, devicetree, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support,
linux-kernel@vger.kernel.org
In-Reply-To: <20220126153519.3637496-2-mkorpershoek@baylibre.com>
On Wed, Jan 26, 2022 at 9:35 AM Mattijs Korpershoek
<mkorpershoek@baylibre.com> wrote:
>
> From: "fengping.yu" <fengping.yu@mediatek.com>
>
> This patch add devicetree bindings for Mediatek matrix keypad driver.
>
> Signed-off-by: fengping.yu <fengping.yu@mediatek.com>
> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
> Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
> ---
> .../input/mediatek,mt6779-keypad.yaml | 80 +++++++++++++++++++
> 1 file changed, 80 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml
>
> diff --git a/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml b/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml
> new file mode 100644
> index 000000000000..2c76029224a0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml
> @@ -0,0 +1,80 @@
> +# SPDX-License-Identifier: GPL-2.0
dual license new bindings
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/input/mediatek,mt6779-keypad.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek's Keypad Controller device tree bindings
> +
> +maintainers:
> + - Fengping Yu <fengping.yu@mediatek.com>
> +
> +allOf:
> + - $ref: "/schemas/input/matrix-keymap.yaml#"
> +
> +description: |
> + Mediatek's Keypad controller is used to interface a SoC with a matrix-type
> + keypad device. The keypad controller supports multiple row and column lines.
> + A key can be placed at each intersection of a unique row and a unique column.
> + The keypad controller can sense a key-press and key-release and report the
> + event using a interrupt to the cpu.
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: mediatek,mt6779-keypad
> + - items:
> + - enum:
> + - mediatek,mt6873-keypad
> + - const: mediatek,mt6779-keypad
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + description: Names of the clocks listed in clocks property in the same order
Drop generic descriptions.
> + items:
> + - const: kpd
> +
> + wakeup-source:
> + description: use any event on keypad as wakeup event
> + type: boolean
> +
> + mediatek,debounce-us:
We already a somewhat common property: debounce-delay-ms
> + description: |
> + Debounce interval in microseconds, if not specified, the default
> + value is 16000
> + maximum: 256000
default: 16000
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/input/input.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + kp@10010000 {
Use a standard node name: keyboard@... or keys@...
> + compatible = "mediatek,mt6779-keypad";
> + reg = <0 0x10010000 0 0x1000>;
> + interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_FALLING>;
> + clocks = <&clk26m>;
> + clock-names = "kpd";
> + };
> + };
> --
> 2.32.0
>
^ permalink raw reply
* Re: [PATCH 2/2] clk: qcom: Add MSM8226 Multimedia Clock Controller support
From: Luca Weiss @ 2022-01-26 22:40 UTC (permalink / raw)
To: Bartosz Dudziak, ~postmarketos/upstreaming
Cc: Andy Gross, Michael Turquette, Stephen Boyd, Rob Herring,
Jeffrey Hugo, Taniya Das, linux-arm-msm, linux-clk, devicetree,
linux-kernel, ~postmarketos/upstreaming, Bjorn Andersson
In-Reply-To: <Ya42ZAKupwKiWpJf@builder.lan>
Hi Bartosz,
are you planning to work on this? If not I can pick it up and make a v2.
Please let me know!
Regards
Luca
On Montag, 6. Dezember 2021 17:12:20 CET Bjorn Andersson wrote:
> On Fri 12 Nov 19:58 CST 2021, Bartosz Dudziak wrote:
> > diff --git a/drivers/clk/qcom/mmcc-msm8974.c
> > b/drivers/clk/qcom/mmcc-msm8974.c
> [..]
>
> > static int mmcc_msm8974_probe(struct platform_device *pdev)
> > {
> >
> > struct regmap *regmap;
> >
> > + const struct of_device_id *match;
> > +
> > + match = of_match_device(mmcc_msm8974_match_table, &pdev->dev);
>
> Could you please use of_device_get_match_data() instead?
>
> > + if (!match)
>
> As a general suggestion; I don't see how we would end up here with
> !match, but if we somehow do it would be during development and you
> would have an easier time debugging this by hitting a NULL pointer
> dereference with a callstack, than tracking down why your clocks are
> missing...
>
> Thanks,
> Bjorn
>
> > + return -ENODEV;
> >
> > - regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc);
> > + regmap = qcom_cc_map(pdev, match->data);
> >
> > if (IS_ERR(regmap))
> >
> > return PTR_ERR(regmap);
> >
> > - clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
> > - clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
> > + if (match->data == &mmcc_msm8974_desc) {
> > + clk_pll_configure_sr_hpm_lp(&mmpll1, regmap,
&mmpll1_config, true);
> > + clk_pll_configure_sr_hpm_lp(&mmpll3, regmap,
&mmpll3_config, false);
> > + } else {
> > + msm8226_clock_override();
> > + }
> >
> > - return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap);
> > + return qcom_cc_really_probe(pdev, match->data, regmap);
> >
> > }
> >
> > static struct platform_driver mmcc_msm8974_driver = {
^ permalink raw reply
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