* [PATCH net-next v2 8/9] net: ethernet: mtk-star-emac: add support for MII interface
From: Biao Huang @ 2022-01-27 1:58 UTC (permalink / raw)
To: David Miller, Rob Herring, Bartosz Golaszewski, Fabien Parent
Cc: Jakub Kicinski, Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Matthias Brugger, netdev, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Biao Huang, Yinghua Pan,
srv_heupstream, Macpaul Lin
In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com>
Add support for MII interface.
If user wants to use MII, assign "MII" to "phy-mode" property in dts.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
---
drivers/net/ethernet/mediatek/mtk_star_emac.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c
index d5e974e0db6d..167a019fd8f5 100644
--- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
+++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
@@ -193,6 +193,7 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" };
#define MTK_PERICFG_REG_NIC_CFG1_CON 0x03c8
#define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10
#define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0)
+#define MTK_PERICFG_BIT_NIC_CFG_CON_MII 0
#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1
#define MTK_PERICFG_BIT_NIC_CFG_CON_CLK BIT(0)
#define MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2 BIT(8)
@@ -1463,6 +1464,7 @@ static int mtk_star_set_timing(struct mtk_star_priv *priv)
unsigned int delay_val = 0;
switch (priv->phy_intf) {
+ case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_RMII:
delay_val |= FIELD_PREP(MTK_STAR_BIT_INV_RX_CLK, priv->rx_inv);
delay_val |= FIELD_PREP(MTK_STAR_BIT_INV_TX_CLK, priv->tx_inv);
@@ -1545,7 +1547,8 @@ static int mtk_star_probe(struct platform_device *pdev)
ret = of_get_phy_mode(of_node, &priv->phy_intf);
if (ret) {
return ret;
- } else if (priv->phy_intf != PHY_INTERFACE_MODE_RMII) {
+ } else if (priv->phy_intf != PHY_INTERFACE_MODE_RMII &&
+ priv->phy_intf != PHY_INTERFACE_MODE_MII) {
dev_err(dev, "unsupported phy mode: %s\n",
phy_modes(priv->phy_intf));
return -EINVAL;
@@ -1610,9 +1613,12 @@ static int mt8516_set_interface_mode(struct net_device *ndev)
{
struct mtk_star_priv *priv = netdev_priv(ndev);
struct device *dev = mtk_star_get_dev(priv);
- unsigned int intf_val, ret, rmii_rxc;
+ unsigned int intf_val, ret, rmii_rxc = 0;
switch (priv->phy_intf) {
+ case PHY_INTERFACE_MODE_MII:
+ intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_MII;
+ break;
case PHY_INTERFACE_MODE_RMII:
intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII;
rmii_rxc = priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK;
@@ -1642,6 +1648,9 @@ static int mt8365_set_interface_mode(struct net_device *ndev)
unsigned int intf_val;
switch (priv->phy_intf) {
+ case PHY_INTERFACE_MODE_MII:
+ intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_MII;
+ break;
case PHY_INTERFACE_MODE_RMII:
intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII;
intf_val |= priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2;
--
2.25.1
^ permalink raw reply related
* [PATCH net-next v2 6/9] net: ethernet: mtk-star-emac: add timing adjustment support
From: Biao Huang @ 2022-01-27 1:58 UTC (permalink / raw)
To: David Miller, Rob Herring, Bartosz Golaszewski, Fabien Parent
Cc: Jakub Kicinski, Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Matthias Brugger, netdev, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Biao Huang, Yinghua Pan,
srv_heupstream, Macpaul Lin
In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com>
Add simple clock inversion for timing adjustment in driver.
Add property "mediatek,txc-inverse" or "mediatek,rxc-inverse" to
device node when necessary.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
---
drivers/net/ethernet/mediatek/mtk_star_emac.c | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c
index d69f75661e75..d5e974e0db6d 100644
--- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
+++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
@@ -131,6 +131,11 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" };
#define MTK_STAR_REG_INT_MASK 0x0054
#define MTK_STAR_BIT_INT_MASK_FNRC BIT(6)
+/* Delay-Macro Register */
+#define MTK_STAR_REG_TEST0 0x0058
+#define MTK_STAR_BIT_INV_RX_CLK BIT(30)
+#define MTK_STAR_BIT_INV_TX_CLK BIT(31)
+
/* Misc. Config Register */
#define MTK_STAR_REG_TEST1 0x005c
#define MTK_STAR_BIT_TEST1_RST_HASH_MBIST BIT(31)
@@ -268,6 +273,8 @@ struct mtk_star_priv {
int duplex;
int pause;
bool rmii_rxc;
+ bool rx_inv;
+ bool tx_inv;
const struct mtk_star_compat *compat_data;
@@ -1450,6 +1457,25 @@ static void mtk_star_clk_disable_unprepare(void *data)
clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks);
}
+static int mtk_star_set_timing(struct mtk_star_priv *priv)
+{
+ struct device *dev = mtk_star_get_dev(priv);
+ unsigned int delay_val = 0;
+
+ switch (priv->phy_intf) {
+ case PHY_INTERFACE_MODE_RMII:
+ delay_val |= FIELD_PREP(MTK_STAR_BIT_INV_RX_CLK, priv->rx_inv);
+ delay_val |= FIELD_PREP(MTK_STAR_BIT_INV_TX_CLK, priv->tx_inv);
+ break;
+ default:
+ dev_err(dev, "This interface not supported\n");
+ return -EINVAL;
+ }
+
+ regmap_write(priv->regs, MTK_STAR_REG_TEST0, delay_val);
+
+ return 0;
+}
static int mtk_star_probe(struct platform_device *pdev)
{
struct device_node *of_node;
@@ -1532,6 +1558,8 @@ static int mtk_star_probe(struct platform_device *pdev)
}
priv->rmii_rxc = of_property_read_bool(of_node, "mediatek,rmii-rxc");
+ priv->rx_inv = of_property_read_bool(of_node, "mediatek,rxc-inverse");
+ priv->tx_inv = of_property_read_bool(of_node, "mediatek,txc-inverse");
if (priv->compat_data->set_interface_mode) {
ret = priv->compat_data->set_interface_mode(ndev);
@@ -1541,6 +1569,12 @@ static int mtk_star_probe(struct platform_device *pdev)
}
}
+ ret = mtk_star_set_timing(priv);
+ if (ret) {
+ dev_err(dev, "Failed to set timing, err = %d\n", ret);
+ return -EINVAL;
+ }
+
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
if (ret) {
dev_err(dev, "unsupported DMA mask\n");
--
2.25.1
^ permalink raw reply related
* [PATCH net-next v2 4/9] dt-bindings: net: mtk-star-emac: add support for MT8365
From: Biao Huang @ 2022-01-27 1:58 UTC (permalink / raw)
To: David Miller, Rob Herring, Bartosz Golaszewski, Fabien Parent
Cc: Jakub Kicinski, Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Matthias Brugger, netdev, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Biao Huang, Yinghua Pan,
srv_heupstream, Macpaul Lin
In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com>
Add binding document for Ethernet on MT8365.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Reviewed-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
Documentation/devicetree/bindings/net/mediatek,star-emac.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
index e6a5ff208253..87a8b25b03a6 100644
--- a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
+++ b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
@@ -23,6 +23,7 @@ properties:
- mediatek,mt8516-eth
- mediatek,mt8518-eth
- mediatek,mt8175-eth
+ - mediatek,mt8365-eth
reg:
maxItems: 1
--
2.25.1
^ permalink raw reply related
* [PATCH net-next v2 5/9] net: ethernet: mtk-star-emac: add clock pad selection for RMII
From: Biao Huang @ 2022-01-27 1:58 UTC (permalink / raw)
To: David Miller, Rob Herring, Bartosz Golaszewski, Fabien Parent
Cc: Jakub Kicinski, Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Matthias Brugger, netdev, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Biao Huang, Yinghua Pan,
srv_heupstream, Macpaul Lin
In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com>
This patch add a new dts property named "mediatek,rmii-rxc" parsing
in driver, which will configure MAC to select which pin the RMII reference
clock is connected to, TXC or RXC.
TXC pad is the default reference clock pin. If user wants to use RXC pad
instead, add "mediatek,rmii-rxc" to corresponding device node.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
---
drivers/net/ethernet/mediatek/mtk_star_emac.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c
index a3884beaa3fe..d69f75661e75 100644
--- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
+++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
@@ -189,6 +189,8 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" };
#define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10
#define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0)
#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1
+#define MTK_PERICFG_BIT_NIC_CFG_CON_CLK BIT(0)
+#define MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2 BIT(8)
/* Represents the actual structure of descriptors used by the MAC. We can
* reuse the same structure for both TX and RX - the layout is the same, only
@@ -265,6 +267,7 @@ struct mtk_star_priv {
int speed;
int duplex;
int pause;
+ bool rmii_rxc;
const struct mtk_star_compat *compat_data;
@@ -1528,6 +1531,8 @@ static int mtk_star_probe(struct platform_device *pdev)
return -ENODEV;
}
+ priv->rmii_rxc = of_property_read_bool(of_node, "mediatek,rmii-rxc");
+
if (priv->compat_data->set_interface_mode) {
ret = priv->compat_data->set_interface_mode(ndev);
if (ret) {
@@ -1571,17 +1576,25 @@ static int mt8516_set_interface_mode(struct net_device *ndev)
{
struct mtk_star_priv *priv = netdev_priv(ndev);
struct device *dev = mtk_star_get_dev(priv);
- unsigned int intf_val;
+ unsigned int intf_val, ret, rmii_rxc;
switch (priv->phy_intf) {
case PHY_INTERFACE_MODE_RMII:
intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII;
+ rmii_rxc = priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK;
break;
default:
dev_err(dev, "This interface not supported\n");
return -EINVAL;
}
+ ret = regmap_update_bits(priv->pericfg,
+ MTK_PERICFG_REG_NIC_CFG1_CON,
+ MTK_PERICFG_BIT_NIC_CFG_CON_CLK,
+ rmii_rxc);
+ if (ret)
+ return ret;
+
return regmap_update_bits(priv->pericfg,
MTK_PERICFG_REG_NIC_CFG0_CON,
MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF,
@@ -1597,6 +1610,7 @@ static int mt8365_set_interface_mode(struct net_device *ndev)
switch (priv->phy_intf) {
case PHY_INTERFACE_MODE_RMII:
intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII;
+ intf_val |= priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2;
break;
default:
dev_err(dev, "This interface not supported\n");
@@ -1605,7 +1619,8 @@ static int mt8365_set_interface_mode(struct net_device *ndev)
return regmap_update_bits(priv->pericfg,
MTK_PERICFG_REG_NIC_CFG_CON_V2,
- MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF,
+ MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF |
+ MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2,
intf_val);
}
--
2.25.1
^ permalink raw reply related
* [PATCH net-next v2 3/9] net: ethernet: mtk-star-emac: add support for MT8365 SoC
From: Biao Huang @ 2022-01-27 1:58 UTC (permalink / raw)
To: David Miller, Rob Herring, Bartosz Golaszewski, Fabien Parent
Cc: Jakub Kicinski, Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Matthias Brugger, netdev, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Biao Huang, Yinghua Pan,
srv_heupstream, Macpaul Lin
In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com>
Add Ethernet driver support for MT8365 SoC.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
drivers/net/ethernet/mediatek/mtk_star_emac.c | 75 ++++++++++++++++---
1 file changed, 64 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c
index a8fbbbcd185b..a3884beaa3fe 100644
--- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
+++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
@@ -151,6 +151,7 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" };
#define MTK_STAR_REG_MAC_CLK_CONF 0x00ac
#define MTK_STAR_MSK_MAC_CLK_CONF GENMASK(7, 0)
#define MTK_STAR_BIT_CLK_DIV_10 0x0a
+#define MTK_STAR_BIT_CLK_DIV_50 0x32
/* Counter registers. */
#define MTK_STAR_REG_C_RXOKPKT 0x0100
@@ -183,9 +184,11 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" };
#define MTK_STAR_REG_C_RX_TWIST 0x0218
/* Ethernet CFG Control */
-#define MTK_PERICFG_REG_NIC_CFG_CON 0x03c4
-#define MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII GENMASK(3, 0)
-#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII BIT(0)
+#define MTK_PERICFG_REG_NIC_CFG0_CON 0x03c4
+#define MTK_PERICFG_REG_NIC_CFG1_CON 0x03c8
+#define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10
+#define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0)
+#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1
/* Represents the actual structure of descriptors used by the MAC. We can
* reuse the same structure for both TX and RX - the layout is the same, only
@@ -234,6 +237,7 @@ struct mtk_star_ring {
};
struct mtk_star_compat {
+ int (*set_interface_mode)(struct net_device *ndev);
unsigned char bit_clk_div;
};
@@ -909,13 +913,6 @@ static void mtk_star_init_config(struct mtk_star_priv *priv)
priv->compat_data->bit_clk_div);
}
-static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv)
-{
- regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON,
- MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII,
- MTK_PERICFG_BIT_NIC_CFG_CON_RMII);
-}
-
static int mtk_star_enable(struct net_device *ndev)
{
struct mtk_star_priv *priv = netdev_priv(ndev);
@@ -1531,7 +1528,13 @@ static int mtk_star_probe(struct platform_device *pdev)
return -ENODEV;
}
- mtk_star_set_mode_rmii(priv);
+ if (priv->compat_data->set_interface_mode) {
+ ret = priv->compat_data->set_interface_mode(ndev);
+ if (ret) {
+ dev_err(dev, "Failed to set phy interface, err = %d\n", ret);
+ return -EINVAL;
+ }
+ }
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
if (ret) {
@@ -1564,10 +1567,58 @@ static int mtk_star_probe(struct platform_device *pdev)
return devm_register_netdev(dev, ndev);
}
+static int mt8516_set_interface_mode(struct net_device *ndev)
+{
+ struct mtk_star_priv *priv = netdev_priv(ndev);
+ struct device *dev = mtk_star_get_dev(priv);
+ unsigned int intf_val;
+
+ switch (priv->phy_intf) {
+ case PHY_INTERFACE_MODE_RMII:
+ intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII;
+ break;
+ default:
+ dev_err(dev, "This interface not supported\n");
+ return -EINVAL;
+ }
+
+ return regmap_update_bits(priv->pericfg,
+ MTK_PERICFG_REG_NIC_CFG0_CON,
+ MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF,
+ intf_val);
+}
+
+static int mt8365_set_interface_mode(struct net_device *ndev)
+{
+ struct mtk_star_priv *priv = netdev_priv(ndev);
+ struct device *dev = mtk_star_get_dev(priv);
+ unsigned int intf_val;
+
+ switch (priv->phy_intf) {
+ case PHY_INTERFACE_MODE_RMII:
+ intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII;
+ break;
+ default:
+ dev_err(dev, "This interface not supported\n");
+ return -EINVAL;
+ }
+
+ return regmap_update_bits(priv->pericfg,
+ MTK_PERICFG_REG_NIC_CFG_CON_V2,
+ MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF,
+ intf_val);
+}
+
static const struct mtk_star_compat mtk_star_mt8516_compat = {
+ .set_interface_mode = mt8516_set_interface_mode,
.bit_clk_div = MTK_STAR_BIT_CLK_DIV_10,
};
+static const struct mtk_star_compat mtk_star_mt8365_compat = {
+ .set_interface_mode = mt8365_set_interface_mode,
+ .bit_clk_div = MTK_STAR_BIT_CLK_DIV_50,
+};
+
static const struct of_device_id mtk_star_of_match[] = {
{ .compatible = "mediatek,mt8516-eth",
.data = &mtk_star_mt8516_compat },
@@ -1575,6 +1626,8 @@ static const struct of_device_id mtk_star_of_match[] = {
.data = &mtk_star_mt8516_compat },
{ .compatible = "mediatek,mt8175-eth",
.data = &mtk_star_mt8516_compat },
+ { .compatible = "mediatek,mt8365-eth",
+ .data = &mtk_star_mt8365_compat },
{ }
};
MODULE_DEVICE_TABLE(of, mtk_star_of_match);
--
2.25.1
^ permalink raw reply related
* [PATCH net-next v2 1/9] net: ethernet: mtk-star-emac: store bit_clk_div in compat structure
From: Biao Huang @ 2022-01-27 1:58 UTC (permalink / raw)
To: David Miller, Rob Herring, Bartosz Golaszewski, Fabien Parent
Cc: Jakub Kicinski, Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Matthias Brugger, netdev, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Biao Huang, Yinghua Pan,
srv_heupstream, Macpaul Lin
In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com>
From: Fabien Parent <fparent@baylibre.com>
Not all the SoC are using the same clock divider. Move the divider into
a compat structure specific to the SoCs.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
drivers/net/ethernet/mediatek/mtk_star_emac.c | 23 +++++++++++++++----
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c
index 1d5dd2015453..7fd8ec0fc636 100644
--- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
+++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
@@ -17,6 +17,7 @@
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include <linux/platform_device.h>
@@ -232,6 +233,10 @@ struct mtk_star_ring {
unsigned int tail;
};
+struct mtk_star_compat {
+ unsigned char bit_clk_div;
+};
+
struct mtk_star_priv {
struct net_device *ndev;
@@ -257,6 +262,8 @@ struct mtk_star_priv {
int duplex;
int pause;
+ const struct mtk_star_compat *compat_data;
+
/* Protects against concurrent descriptor access. */
spinlock_t lock;
@@ -899,7 +906,7 @@ static void mtk_star_init_config(struct mtk_star_priv *priv)
regmap_write(priv->regs, MTK_STAR_REG_SYS_CONF, val);
regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CLK_CONF,
MTK_STAR_MSK_MAC_CLK_CONF,
- MTK_STAR_BIT_CLK_DIV_10);
+ priv->compat_data->bit_clk_div);
}
static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv)
@@ -1461,6 +1468,7 @@ static int mtk_star_probe(struct platform_device *pdev)
priv = netdev_priv(ndev);
priv->ndev = ndev;
+ priv->compat_data = of_device_get_match_data(&pdev->dev);
SET_NETDEV_DEV(ndev, dev);
platform_set_drvdata(pdev, ndev);
@@ -1556,10 +1564,17 @@ static int mtk_star_probe(struct platform_device *pdev)
return devm_register_netdev(dev, ndev);
}
+static const struct mtk_star_compat mtk_star_mt8516_compat = {
+ .bit_clk_div = MTK_STAR_BIT_CLK_DIV_10,
+};
+
static const struct of_device_id mtk_star_of_match[] = {
- { .compatible = "mediatek,mt8516-eth", },
- { .compatible = "mediatek,mt8518-eth", },
- { .compatible = "mediatek,mt8175-eth", },
+ { .compatible = "mediatek,mt8516-eth",
+ .data = &mtk_star_mt8516_compat },
+ { .compatible = "mediatek,mt8518-eth",
+ .data = &mtk_star_mt8516_compat },
+ { .compatible = "mediatek,mt8175-eth",
+ .data = &mtk_star_mt8516_compat },
{ }
};
MODULE_DEVICE_TABLE(of, mtk_star_of_match);
--
2.25.1
^ permalink raw reply related
* [PATCH net-next v2 2/9] net: ethernet: mtk-star-emac: modify IRQ trigger flags
From: Biao Huang @ 2022-01-27 1:58 UTC (permalink / raw)
To: David Miller, Rob Herring, Bartosz Golaszewski, Fabien Parent
Cc: Jakub Kicinski, Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Matthias Brugger, netdev, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Biao Huang, Yinghua Pan,
srv_heupstream, Macpaul Lin
In-Reply-To: <20220127015857.9868-1-biao.huang@mediatek.com>
If the flags in request_irq() is IRQF_TRIGGER_NONE, the trigger method
is determined by "interrupt" property in dts.
So, modify the flag from IRQF_TRIGGER_FALLING to IRQF_TRIGGER_NONE.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
Reviewed-by: Bartosz Golaszewski <brgl@bgdev.pl>
---
drivers/net/ethernet/mediatek/mtk_star_emac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c
index 7fd8ec0fc636..a8fbbbcd185b 100644
--- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
+++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
@@ -959,7 +959,7 @@ static int mtk_star_enable(struct net_device *ndev)
/* Request the interrupt */
ret = request_irq(ndev->irq, mtk_star_handle_irq,
- IRQF_TRIGGER_FALLING, ndev->name, ndev);
+ IRQF_TRIGGER_NONE, ndev->name, ndev);
if (ret)
goto err_free_skbs;
--
2.25.1
^ permalink raw reply related
* [PATCH net-next v2 0/9] add more features for mtk-star-emac
From: Biao Huang @ 2022-01-27 1:58 UTC (permalink / raw)
To: David Miller, Rob Herring, Bartosz Golaszewski, Fabien Parent
Cc: Jakub Kicinski, Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Matthias Brugger, netdev, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, Biao Huang, Yinghua Pan,
srv_heupstream, Macpaul Lin
Changes in v2:
1. fix coding style as Bartosz's comments.
2. add reviewed-by as Bartosz's comments.
This series add more features for mtk-star-emac:
1. add reference clock pad selection for RMII;
2. add simple timing adjustment for RMII;
3. add support for MII;
4. add support for new IC MT8365;
5. separate tx/rx interrupt handling.
Biao Huang (8):
net: ethernet: mtk-star-emac: modify IRQ trigger flags
net: ethernet: mtk-star-emac: add support for MT8365 SoC
dt-bindings: net: mtk-star-emac: add support for MT8365
net: ethernet: mtk-star-emac: add clock pad selection for RMII
net: ethernet: mtk-star-emac: add timing adjustment support
dt-bindings: net: mtk-star-emac: add description for new properties
net: ethernet: mtk-star-emac: add support for MII interface
net: ethernet: mtk-star-emac: separate tx/rx handling with two NAPIs
Fabien Parent (1):
net: ethernet: mtk-star-emac: store bit_clk_div in compat structure
.../bindings/net/mediatek,star-emac.yaml | 17 +
drivers/net/ethernet/mediatek/mtk_star_emac.c | 477 ++++++++++++------
2 files changed, 341 insertions(+), 153 deletions(-)
--
2.25.1
^ permalink raw reply
* Re: [PATCH net-next v1 2/9] net: ethernet: mtk-star-emac: modify IRQ trigger flags
From: Biao Huang @ 2022-01-27 1:13 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: David Miller, Rob Herring, Fabien Parent, Jakub Kicinski,
Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Matthias Brugger, netdev, devicetree, Linux Kernel Mailing List,
Linux ARM, moderated list:ARM/Mediatek SoC..., Yinghua Pan,
srv_heupstream, Macpaul Lin
In-Reply-To: <CAMRc=McZTped08HwbM+pr-xtsDyddTLjpsCc_f7ucoDM2DNXaw@mail.gmail.com>
Dear Bartosz,
Thanks for your comments!
On Tue, 2022-01-25 at 11:22 +0100, Bartosz Golaszewski wrote:
> On Thu, Jan 20, 2022 at 8:02 AM Biao Huang <biao.huang@mediatek.com>
> wrote:
> >
> > If the flags in request_irq() is IRQF_TRIGGER_NONE, the trigger
> > method
> > is determined by "interrupt" property in dts.
> > So, modify the flag from IRQF_TRIGGER_FALLING to IRQF_TRIGGER_NONE.
> >
> > Signed-off-by: Biao Huang <biao.huang@mediatek.com>
> > Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
> > ---
> > drivers/net/ethernet/mediatek/mtk_star_emac.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c
> > b/drivers/net/ethernet/mediatek/mtk_star_emac.c
> > index 26f5020f2e9c..7c2af775d601 100644
> > --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
> > +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
> > @@ -959,7 +959,7 @@ static int mtk_star_enable(struct net_device
> > *ndev)
> >
> > /* Request the interrupt */
> > ret = request_irq(ndev->irq, mtk_star_handle_irq,
> > - IRQF_TRIGGER_FALLING, ndev->name, ndev);
> > + IRQF_TRIGGER_NONE, ndev->name, ndev);
> > if (ret)
> > goto err_free_skbs;
> >
> > --
> > 2.25.1
> >
>
> Reviewed-by: Bartosz Golaszewski <brgl@bgdev.pl>
I'll add reviewd-by in next send.
^ permalink raw reply
* Re: [PATCH net-next v1 4/9] dt-bindings: net: mtk-star-emac: add support for MT8365
From: Biao Huang @ 2022-01-27 1:13 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: David Miller, Rob Herring, Fabien Parent, Jakub Kicinski,
Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Matthias Brugger, netdev, devicetree, Linux Kernel Mailing List,
Linux ARM, moderated list:ARM/Mediatek SoC..., Yinghua Pan,
srv_heupstream, Macpaul Lin
In-Reply-To: <CAMRc=MdVKdXcK0gdBSpaaSm5fx1o5Sy_0-JJBPK0=Xp7UmQnqQ@mail.gmail.com>
Dear Bartosz,
Thanks for your comments~
On Tue, 2022-01-25 at 11:23 +0100, Bartosz Golaszewski wrote:
> On Thu, Jan 20, 2022 at 8:02 AM Biao Huang <biao.huang@mediatek.com>
> wrote:
> >
> > Add binding document for Ethernet on MT8365.
> >
> > Signed-off-by: Biao Huang <biao.huang@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/net/mediatek,star-emac.yaml | 1
> > +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/net/mediatek,star-
> > emac.yaml b/Documentation/devicetree/bindings/net/mediatek,star-
> > emac.yaml
> > index e6a5ff208253..87a8b25b03a6 100644
> > --- a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
> > +++ b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
> > @@ -23,6 +23,7 @@ properties:
> > - mediatek,mt8516-eth
> > - mediatek,mt8518-eth
> > - mediatek,mt8175-eth
> > + - mediatek,mt8365-eth
> >
> > reg:
> > maxItems: 1
> > --
> > 2.25.1
> >
>
> Reviewed-by: Bartosz Golaszewski <brgl@bgdev.pl>
I'll add revieed-by in next send.
^ permalink raw reply
* Re: [PATCH v3 6/6] RISC-V: Do not use cpumask data structure for hartid bitmap
From: Atish Patra @ 2022-01-27 1:01 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Jessica Clarke, Atish Patra, Linux Kernel Mailing List,
Anup Patel, Albert Ou, Damien Le Moal, devicetree, Jisheng Zhang,
Krzysztof Kozlowski, linux-riscv, Palmer Dabbelt, Paul Walmsley,
Rob Herring
In-Reply-To: <CAMuHMdXq7OQJL6H7=JRnDTR6p+AD0o2Ctjn806XZQZ9PYjvepg@mail.gmail.com>
On Wed, Jan 26, 2022 at 1:10 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Atish,
>
> On Wed, Jan 26, 2022 at 9:28 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Wed, Jan 26, 2022 at 3:21 AM Atish Patra <atishp@atishpatra.org> wrote:
> > > On Tue, Jan 25, 2022 at 2:26 PM Jessica Clarke <jrtc27@jrtc27.com> wrote:
> > > > On 20 Jan 2022, at 09:09, Atish Patra <atishp@rivosinc.com> wrote:
> > > > > Currently, SBI APIs accept a hartmask that is generated from struct
> > > > > cpumask. Cpumask data structure can hold upto NR_CPUs value. Thus, it
> > > > > is not the correct data structure for hartids as it can be higher
> > > > > than NR_CPUs for platforms with sparse or discontguous hartids.
> > > > >
> > > > > Remove all association between hartid mask and struct cpumask.
> > > > >
> > > > > Reviewed-by: Anup Patel <anup@brainfault.org> (For Linux RISC-V changes)
> > > > > Acked-by: Anup Patel <anup@brainfault.org> (For KVM RISC-V changes)
> > > > > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> >
> > > I am yet to reproduce it on my end.
> > > @Geert Uytterhoeven: can you please try the below diff on your end.
> >
> > Unfortunately it doesn't fix the issue for me.
> >
> > /me debugging...
>
> Found it: after this commit, the SBI_EXT_RFENCE_REMOTE_FENCE_I and
> SBI_EXT_RFENCE_REMOTE_SFENCE_VMA ecalls are now called with
> hmask = 0x8000000000000001 and hbase = 1 instead of hmask = 3 and
> hbase = 0.
>
> cpuid 1 maps to hartid 0
> cpuid 0 maps to hartid 1
>
> __sbi_rfence_v02:364: cpuid 1 hartid 0
> __sbi_rfence_v02:377: hartid 0 hbase 1
> hmask |= 1UL << (hartid - hbase);
>
> oops
>
> __sbi_rfence_v02_call:303: SBI_EXT_RFENCE_REMOTE_FENCE_I hmask
> 8000000000000001 hbase 1
>
Ahh yes. hmask will be incorrect if the bootcpu(cpu 0) is a higher
hartid and it is trying to do a remote tlb flush/IPI
to lower the hartid. We should generate the hartid array before the loop.
Can you try this diff ? It seems to work for me during multiple boot
cycle on the unleashed.
You can find the patch here as well
https://github.com/atishp04/linux/commits/v5.17-rc1
--------------------------------------------------------------------------------------------------------------------------------
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index f72527fcb347..4ebeb5813edc 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -8,6 +8,8 @@
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/reboot.h>
+#include <linux/sort.h>
+
#include <asm/sbi.h>
#include <asm/smp.h>
@@ -85,7 +87,7 @@ static unsigned long
__sbi_v01_cpumask_to_hartmask(const struct cpumask *cpu_mas
pr_warn("Unable to send any request to hartid > BITS_PER_LONG for
SBI v0.1\n");
break;
}
- hmask |= 1 << hartid;
+ hmask |= 1UL << hartid;
}
return hmask;
@@ -160,7 +162,7 @@ static int __sbi_send_ipi_v01(const struct cpumask
*cpu_mask)
{
unsigned long hart_mask;
- if (!cpu_mask)
+ if (!cpu_mask || cpumask_empty(cpu_mask))
cpu_mask = cpu_online_mask;
hart_mask = __sbi_v01_cpumask_to_hartmask(cpu_mask);
@@ -176,7 +178,7 @@ static int __sbi_rfence_v01(int fid, const struct
cpumask *cpu_mask,
int result = 0;
unsigned long hart_mask;
- if (!cpu_mask)
+ if (!cpu_mask || cpumask_empty(cpu_mask))
cpu_mask = cpu_online_mask;
hart_mask = __sbi_v01_cpumask_to_hartmask(cpu_mask);
@@ -236,6 +238,18 @@ static int __sbi_rfence_v01(int fid, const struct
cpumask *cpu_mask,
static void sbi_set_power_off(void) {}
#endif /* CONFIG_RISCV_SBI_V01 */
+static int cmp_ulong(const void *A, const void *B)
+{
+ const unsigned long *a = A, *b = B;
+
+ if (*a < *b)
+ return -1;
+ else if (*a > *b)
+ return 1;
+ else
+ return 0;
+}
+
static void __sbi_set_timer_v02(uint64_t stime_value)
{
#if __riscv_xlen == 32
@@ -251,13 +265,22 @@ static int __sbi_send_ipi_v02(const struct
cpumask *cpu_mask)
{
unsigned long hartid, cpuid, hmask = 0, hbase = 0;
struct sbiret ret = {0};
- int result;
+ int result, index = 0, max_index = 0;
+ unsigned long hartid_arr[NR_CPUS] = {0};
- if (!cpu_mask)
+ if (!cpu_mask || cpumask_empty(cpu_mask))
cpu_mask = cpu_online_mask;
for_each_cpu(cpuid, cpu_mask) {
hartid = cpuid_to_hartid_map(cpuid);
+ hartid_arr[index] = hartid;
+ index++;
+ }
+
+ max_index = index;
+ sort(hartid_arr, max_index, sizeof(unsigned long), cmp_ulong, NULL);
+ for (index = 0; index < max_index; index++) {
+ hartid = hartid_arr[index];
if (hmask && ((hbase + BITS_PER_LONG) <= hartid)) {
ret = sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI,
hmask, hbase, 0, 0, 0, 0);
@@ -345,13 +368,21 @@ static int __sbi_rfence_v02(int fid, const
struct cpumask *cpu_mask,
unsigned long arg4, unsigned long arg5)
{
unsigned long hartid, cpuid, hmask = 0, hbase = 0;
- int result;
+ int result, index = 0, max_index = 0;
+ unsigned long hartid_arr[NR_CPUS] = {0};
- if (!cpu_mask)
+ if (!cpu_mask || cpumask_empty(cpu_mask))
cpu_mask = cpu_online_mask;
for_each_cpu(cpuid, cpu_mask) {
hartid = cpuid_to_hartid_map(cpuid);
+ hartid_arr[index] = hartid;
+ index++;
+ }
+ max_index = index;
+ sort(hartid_arr, max_index, sizeof(unsigned long), cmp_ulong, NULL);
+ for (index = 0; index < max_index; index++) {
+ hartid = hartid_arr[index];
if (hmask && ((hbase + BITS_PER_LONG) <= hartid)) {
result = __sbi_rfence_v02_call(fid, hmask, hbase,
start, size, arg4, arg5);
--------------------------------------------------------------------------------------------------------------------------------
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Regards,
Atish
^ permalink raw reply related
* [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node
From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw)
To: Rob Herring, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20220127010023.3169415-1-pgwipeout@gmail.com>
The sdmmc1 node on Quartz64-A supports the optional wifi module from
Pine64.
Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on
the Quartz64-A.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 33c2c18caaa9..1d73ac6557c5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -91,6 +91,18 @@ simple-audio-card,codec {
};
};
+ sdio_pwrseq: sdio-pwrseq {
+ status = "okay";
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk817 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <5000000>;
+ };
+
vcc12v_dcin: vcc12v_dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@@ -147,6 +159,17 @@ vcc_sys: vcc_sys {
regulator-max-microvolt = <4400000>;
vin-supply = <&vbus>;
};
+
+ /* sourced from vcc_sys, sdio module operates internally at 3.3v */
+ vcc_wl: vcc_wl {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_wl";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sys>;
+ };
};
&cpu0 {
@@ -475,6 +498,12 @@ pmic_int_l: pmic-int-l {
};
};
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
vcc_sd {
vcc_sd_h: vcc-sd-h {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -516,6 +545,22 @@ &sdmmc0 {
status = "okay";
};
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_wl>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
&spdif {
status = "okay";
};
--
2.25.1
^ permalink raw reply related
* [PATCH 1/3] arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage
From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw)
To: Rob Herring, Heiko Stuebner, Peter Geis
Cc: Rob Herring, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20220127010023.3169415-1-pgwipeout@gmail.com>
The Quartz64 Model A uses a voltage divider to ensure ddr voltage is
within specification from the default regulator configuration.
Adjusting this voltage is detrimental, and currently causes the ddr
voltage to be about 0.8v.
Remove the min and max voltage setpoints for the ddr regulator.
Fixes: b33a22a1e7c4 ("arm64: dts: rockchip: add basic dts for Pine64
Quartz64-A")
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 166399b7f13f..d9eb92d59099 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -285,8 +285,6 @@ regulator-state-mem {
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_ddr";
regulator-state-mem {
--
2.25.1
^ permalink raw reply related
* [PATCH 2/3] arm64: dts: rockchip: add Quartz64-A pmu_io_domains
From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw)
To: Rob Herring, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20220127010023.3169415-1-pgwipeout@gmail.com>
Several io power domains on the Quartz64-A operate at 1.8v.
Add the pmu_io_domains definition to enable support for this.
This permits the enablement of the following features:
sdio - wifi support
sdhci - mmc-hs200-1_8v
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index d9eb92d59099..33c2c18caaa9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -482,6 +482,19 @@ vcc_sd_h: vcc-sd-h {
};
};
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc1v8_dvp>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
--
2.25.1
^ permalink raw reply related
* [PATCH 0/3] Quartz64-A fixes and enablement from 5.17-rc1
From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw)
Cc: Peter Geis, Rob Herring, Heiko Stuebner, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
Good Evening,
This is the first of several patch series for further expanding
Quartz64-A support.
This series has the following patches:
Fix the ddr regulator voltage.
Add pmu_io_domains to permit sdio and high speed emmc support.
Add sdmmc1 node for wifi support.
Please review and apply.
Very Respectfully,
Peter Geis
Peter Geis (3):
arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage
arm64: dts: rockchip: add Quartz64-A pmu_io_domains
arm64: dts: rockchip: add Quartz64-A sdmmc1 node
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 60 ++++++++++++++++++-
1 file changed, 58 insertions(+), 2 deletions(-)
--
2.25.1
^ permalink raw reply
* Re: [PATCH] ARM: dts: suniv: Add MMC and clock macros.
From: Andre Przywara @ 2022-01-27 0:53 UTC (permalink / raw)
To: Jesse Taube
Cc: devicetree, robh+dt, Mesih Kilinc, Maxime Ripard, Chen-Yu Tsai,
Jernej Skrabec, linux-arm-kernel, linux-sunxi, Chris Morgan
In-Reply-To: <d69233d8-4e3d-56db-d4d3-1b39fe84ee30@gmail.com>
On Wed, 26 Jan 2022 19:12:05 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
> On 1/26/22 18:57, Andre Przywara wrote:
> > On Mon, 24 Jan 2022 20:13:52 -0500
> > Jesse Taube <mr.bossman075@gmail.com> wrote:
> >
> > Hi Jesse,
> >
> > I understand that get_maintainers.pl suggested this CC: list, but you
> > should add sunxi people and linux-arm kernel ML. Doing that now.
> Uh yeah that makes sense in hind sight.
> >> Include clock and reset macros and replace magic numbers.
> >> Add MMC node.
> >
> > This patch itself does not do much, does it? You would at least need to
> > enable that in the board dts.
> True it doesn't do much just so that its in both u-boot and linux.
> > And this should be multiple patches:
> > 1) replace numbers with macros (part of this patch)
> > 2) Add the MMC compatible string combo to the the bindings doc
> > 3) Add the *two* MMC nodes and at least the pinctrl node for MMC0 to the
> > SoC .dtsi (partly in this patch)
> > 4) Enable the MMC and the card detect pin in the Nano board .dts
> >
> > I checked that the macros names match the numbers they replace, so
> > you can add my R-b: on that patch 1 (if you follow my suggestion).
> > The MMC node also seems to look sane.
> That seems okay.
> >>
> >> Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
> >
> > It is not evident why Mesih's S-o-b: is in here? The patch seems to be
> > authored and sent by you? Either you make him the author if that is his
> > patch originally, or you put him just as Cc: or in Suggested-by:, maybe.
> I did write the patch after I wrote it I was looking at his github and
> he had almost the same patch.
Yeah, not really surprising, there are only so many ways to write a DT.
I guess he never sent it, and since you wrote it, it's yours, so just
add him in Cc:, since he was involved in the F1C100s upstreaming.
Cheers,
Andre
> > Cheers,
> > Andre
> >
> >> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> >> ---
> >> arch/arm/boot/dts/suniv-f1c100s.dtsi | 41 +++++++++++++++++++++++-----
> >> 1 file changed, 34 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> >> index 6100d3b75f61..32872bb29917 100644
> >> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> >> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> >> @@ -4,6 +4,9 @@
> >> * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
> >> */
> >>
> >> +#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
> >> +#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
> >> +
> >> / {
> >> #address-cells = <1>;
> >> #size-cells = <1>;
> >> @@ -82,7 +85,7 @@ pio: pinctrl@1c20800 {
> >> compatible = "allwinner,suniv-f1c100s-pinctrl";
> >> reg = <0x01c20800 0x400>;
> >> interrupts = <38>, <39>, <40>;
> >> - clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
> >> + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
> >> clock-names = "apb", "hosc", "losc";
> >> gpio-controller;
> >> interrupt-controller;
> >> @@ -93,6 +96,11 @@ uart0_pe_pins: uart0-pe-pins {
> >> pins = "PE0", "PE1";
> >> function = "uart0";
> >> };
> >> +
> >> + mmc0_pins: mmc0-pins {
> >> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
> >> + function = "mmc0";
> >> + };
> >> };
> >>
> >> timer@1c20c00 {
> >> @@ -108,14 +116,33 @@ wdt: watchdog@1c20ca0 {
> >> reg = <0x01c20ca0 0x20>;
> >> };
> >>
> >> + mmc0: mmc@1c0f000 {
> >> + compatible = "allwinner,suniv-f1c100s-mmc",
> >> + "allwinner,sun7i-a20-mmc";
> >> + reg = <0x01c0f000 0x1000>;
> >> + clocks = <&ccu CLK_BUS_MMC0>,
> >> + <&ccu CLK_MMC0>,
> >> + <&ccu CLK_MMC0_OUTPUT>,
> >> + <&ccu CLK_MMC0_SAMPLE>;
> >> + clock-names = "ahb", "mmc", "output", "sample";
> >> + resets = <&ccu RST_BUS_MMC0>;
> >> + reset-names = "ahb";
> >> + interrupts = <23>;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&mmc0_pins>;
> >> + status = "disabled";
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + };
> >> +
> >> uart0: serial@1c25000 {
> >> compatible = "snps,dw-apb-uart";
> >> reg = <0x01c25000 0x400>;
> >> interrupts = <1>;
> >> reg-shift = <2>;
> >> reg-io-width = <4>;
> >> - clocks = <&ccu 38>;
> >> - resets = <&ccu 24>;
> >> + clocks = <&ccu CLK_BUS_UART0>;
> >> + resets = <&ccu RST_BUS_UART0>;
> >> status = "disabled";
> >> };
> >>
> >> @@ -125,8 +152,8 @@ uart1: serial@1c25400 {
> >> interrupts = <2>;
> >> reg-shift = <2>;
> >> reg-io-width = <4>;
> >> - clocks = <&ccu 39>;
> >> - resets = <&ccu 25>;
> >> + clocks = <&ccu CLK_BUS_UART1>;
> >> + resets = <&ccu RST_BUS_UART1>;
> >> status = "disabled";
> >> };
> >>
> >> @@ -136,8 +163,8 @@ uart2: serial@1c25800 {
> >> interrupts = <3>;
> >> reg-shift = <2>;
> >> reg-io-width = <4>;
> >> - clocks = <&ccu 40>;
> >> - resets = <&ccu 26>;
> >> + clocks = <&ccu CLK_BUS_UART2>;
> >> + resets = <&ccu RST_BUS_UART2>;
> >> status = "disabled";
> >> };
> >> };
> >
^ permalink raw reply
* Re: [PATCH net-next v1 3/9] net: ethernet: mtk-star-emac: add support for MT8365 SoC
From: Biao Huang @ 2022-01-27 0:51 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: David Miller, Rob Herring, Fabien Parent, Jakub Kicinski,
Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Matthias Brugger, netdev, devicetree, Linux Kernel Mailing List,
Linux ARM, moderated list:ARM/Mediatek SoC..., Yinghua Pan,
srv_heupstream, Macpaul Lin
In-Reply-To: <CAMRc=MefKOmdKbm5KT=zQLORwm7oYe1oUy_XW3heqAqFqbE5NQ@mail.gmail.com>
Dear Bartosz,
Thanks for your comments!
On Tue, 2022-01-25 at 11:21 +0100, Bartosz Golaszewski wrote:
> On Thu, Jan 20, 2022 at 8:02 AM Biao Huang <biao.huang@mediatek.com>
> wrote:
> >
> > Add Ethernet driver support for MT8365 SoC.
> >
> > Signed-off-by: Biao Huang <biao.huang@mediatek.com>
> > Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> > drivers/net/ethernet/mediatek/mtk_star_emac.c | 75
> > ++++++++++++++++---
> > 1 file changed, 64 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c
> > b/drivers/net/ethernet/mediatek/mtk_star_emac.c
> > index 7c2af775d601..403439782db9 100644
> > --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
> > +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
> > @@ -151,6 +151,7 @@ static const char *const mtk_star_clk_names[] =
> > { "core", "reg", "trans" };
> > #define MTK_STAR_REG_MAC_CLK_CONF 0x00ac
> > #define MTK_STAR_MSK_MAC_CLK_CONF GENMASK(7, 0)
> > #define MTK_STAR_BIT_CLK_DIV_10 0x0a
> > +#define MTK_STAR_BIT_CLK_DIV_50 0x32
> >
> > /* Counter registers. */
> > #define MTK_STAR_REG_C_RXOKPKT 0x0100
> > @@ -183,9 +184,11 @@ static const char *const mtk_star_clk_names[]
> > = { "core", "reg", "trans" };
> > #define MTK_STAR_REG_C_RX_TWIST 0x0218
> >
> > /* Ethernet CFG Control */
> > -#define MTK_PERICFG_REG_NIC_CFG_CON 0x03c4
> > -#define MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII GENMASK(3, 0)
> > -#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII BIT(0)
> > +#define MTK_PERICFG_REG_NIC_CFG0_CON 0x03c4
> > +#define MTK_PERICFG_REG_NIC_CFG1_CON 0x03c8
> > +#define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10
> > +#define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0)
> > +#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1
> >
> > /* Represents the actual structure of descriptors used by the MAC.
> > We can
> > * reuse the same structure for both TX and RX - the layout is the
> > same, only
> > @@ -234,6 +237,7 @@ struct mtk_star_ring {
> > };
> >
> > struct mtk_star_compat {
> > + int (*set_interface_mode)(struct net_device *ndev);
> > unsigned char bit_clk_div;
> > };
> >
> > @@ -909,13 +913,6 @@ static void mtk_star_init_config(struct
> > mtk_star_priv *priv)
> > priv->compat_data->bit_clk_div);
> > }
> >
> > -static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv)
> > -{
> > - regmap_update_bits(priv->pericfg,
> > MTK_PERICFG_REG_NIC_CFG_CON,
> > - MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII,
> > - MTK_PERICFG_BIT_NIC_CFG_CON_RMII);
> > -}
> > -
> > static int mtk_star_enable(struct net_device *ndev)
> > {
> > struct mtk_star_priv *priv = netdev_priv(ndev);
> > @@ -1531,7 +1528,13 @@ static int mtk_star_probe(struct
> > platform_device *pdev)
> > return -ENODEV;
> > }
> >
> > - mtk_star_set_mode_rmii(priv);
> > + if (priv->compat_data->set_interface_mode) {
> > + ret = priv->compat_data->set_interface_mode(ndev);
> > + if (ret) {
> > + dev_err(dev, "Failed to set phy interface,
> > err = %d\n", ret);
> > + return -EINVAL;
> > + }
> > + }
>
> Shouldn't you still call mtk_star_set_mode_rmii(priv) if there's no
> callback?
mtk_star_set_mode_rmii is replaced by priv->compat_data-
>set_interface_mode,
all the interface settings are moved to set_interface_mode,
and we'll implement it for every IC.
so, mtk_star_set_mode_rmii is no longer used.
>
> >
> > ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
> > if (ret) {
> > @@ -1564,10 +1567,58 @@ static int mtk_star_probe(struct
> > platform_device *pdev)
> > return devm_register_netdev(dev, ndev);
> > }
> >
> > +static int mt8516_set_interface_mode(struct net_device *ndev)
> > +{
> > + struct mtk_star_priv *priv = netdev_priv(ndev);
> > + struct device *dev = mtk_star_get_dev(priv);
> > + unsigned int intf_val = 0;
>
> No need to initialize.
OK, will fix it in next send.
>
> > +
> > + switch (priv->phy_intf) {
> > + case PHY_INTERFACE_MODE_RMII:
> > + intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII;
> > + break;
> > + default:
> > + dev_err(dev, "This interface not supported\n");
> > + return -EINVAL;
> > + }
> > +
> > + regmap_update_bits(priv->pericfg,
> > MTK_PERICFG_REG_NIC_CFG0_CON,
> > + MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF,
> > + intf_val);
> > + return 0;
>
> You can directly return regmap_update_bits().
OK, will fix it in next send.
>
> > +}
> > +
> > +static int mt8365_set_interface_mode(struct net_device *ndev)
> > +{
> > + struct mtk_star_priv *priv = netdev_priv(ndev);
> > + struct device *dev = mtk_star_get_dev(priv);
> > + unsigned int intf_val = 0;
> > +
> > + switch (priv->phy_intf) {
> > + case PHY_INTERFACE_MODE_RMII:
> > + intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII;
> > + break;
> > + default:
> > + dev_err(dev, "This interface not supported\n");
> > + return -EINVAL;
> > + }
> > +
> > + regmap_update_bits(priv->pericfg,
> > MTK_PERICFG_REG_NIC_CFG_CON_V2,
> > + MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF,
> > + intf_val);
> > + return 0;
> > +}
>
> Same as above.
OK, will fix it in next send.
>
> > +
> > static struct mtk_star_compat mtk_star_mt8516_compat = {
> > + .set_interface_mode = mt8516_set_interface_mode,
> > .bit_clk_div = MTK_STAR_BIT_CLK_DIV_10,
> > };
> >
> > +static struct mtk_star_compat mtk_star_mt8365_compat = {
> > + .set_interface_mode = mt8365_set_interface_mode,
> > + .bit_clk_div = MTK_STAR_BIT_CLK_DIV_50,
> > +};
> > +
> > static const struct of_device_id mtk_star_of_match[] = {
> > { .compatible = "mediatek,mt8516-eth",
> > .data = &mtk_star_mt8516_compat },
> > @@ -1575,6 +1626,8 @@ static const struct of_device_id
> > mtk_star_of_match[] = {
> > .data = &mtk_star_mt8516_compat },
> > { .compatible = "mediatek,mt8175-eth",
> > .data = &mtk_star_mt8516_compat },
> > + { .compatible = "mediatek,mt8365-eth",
> > + .data = &mtk_star_mt8365_compat },
> > { }
> > };
> > MODULE_DEVICE_TABLE(of, mtk_star_of_match);
> > --
> > 2.25.1
> >
>
> Bart
^ permalink raw reply
* Re: [PATCH net-next v1 1/9] net: ethernet: mtk-star-emac: store bit_clk_div in compat structure
From: Biao Huang @ 2022-01-27 0:47 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: David Miller, Rob Herring, Fabien Parent, Jakub Kicinski,
Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Matthias Brugger, netdev, devicetree, Linux Kernel Mailing List,
Linux ARM, moderated list:ARM/Mediatek SoC..., Yinghua Pan,
srv_heupstream, Macpaul Lin
In-Reply-To: <CAMRc=Mc+DqcQFGqxoYXYG-VCuaKkJusoVGSHb0G-MtYsiVCxVw@mail.gmail.com>
Dear Bartosz,
Thanks for your comments!
On Tue, 2022-01-25 at 10:50 +0100, Bartosz Golaszewski wrote:
> On Thu, Jan 20, 2022 at 8:02 AM Biao Huang <biao.huang@mediatek.com>
> wrote:
> >
> > From: Fabien Parent <fparent@baylibre.com>
> >
> > Not all the SoC are using the same clock divider. Move the divider
> > into
> > a compat structure specific to the SoCs.
> >
> > Signed-off-by: Biao Huang <biao.huang@mediatek.com>
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> > drivers/net/ethernet/mediatek/mtk_star_emac.c | 23
> > +++++++++++++++----
> > 1 file changed, 19 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c
> > b/drivers/net/ethernet/mediatek/mtk_star_emac.c
> > index 1d5dd2015453..26f5020f2e9c 100644
> > --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
> > +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
> > @@ -17,6 +17,7 @@
> > #include <linux/module.h>
> > #include <linux/netdevice.h>
> > #include <linux/of.h>
> > +#include <linux/of_device.h>
> > #include <linux/of_mdio.h>
> > #include <linux/of_net.h>
> > #include <linux/platform_device.h>
> > @@ -232,6 +233,10 @@ struct mtk_star_ring {
> > unsigned int tail;
> > };
> >
> > +struct mtk_star_compat {
> > + unsigned char bit_clk_div;
> > +};
> > +
> > struct mtk_star_priv {
> > struct net_device *ndev;
> >
> > @@ -257,6 +262,8 @@ struct mtk_star_priv {
> > int duplex;
> > int pause;
> >
> > + const struct mtk_star_compat *compat_data;
> > +
> > /* Protects against concurrent descriptor access. */
> > spinlock_t lock;
> >
> > @@ -899,7 +906,7 @@ static void mtk_star_init_config(struct
> > mtk_star_priv *priv)
> > regmap_write(priv->regs, MTK_STAR_REG_SYS_CONF, val);
> > regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CLK_CONF,
> > MTK_STAR_MSK_MAC_CLK_CONF,
> > - MTK_STAR_BIT_CLK_DIV_10);
> > + priv->compat_data->bit_clk_div);
> > }
> >
> > static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv)
> > @@ -1461,6 +1468,7 @@ static int mtk_star_probe(struct
> > platform_device *pdev)
> >
> > priv = netdev_priv(ndev);
> > priv->ndev = ndev;
> > + priv->compat_data = of_device_get_match_data(&pdev->dev);
> > SET_NETDEV_DEV(ndev, dev);
> > platform_set_drvdata(pdev, ndev);
> >
> > @@ -1556,10 +1564,17 @@ static int mtk_star_probe(struct
> > platform_device *pdev)
> > return devm_register_netdev(dev, ndev);
> > }
> >
> > +static struct mtk_star_compat mtk_star_mt8516_compat = {
>
> static const ... ?
Yes, will fix it in next send.
>
> > + .bit_clk_div = MTK_STAR_BIT_CLK_DIV_10,
> > +};
> > +
> > static const struct of_device_id mtk_star_of_match[] = {
> > - { .compatible = "mediatek,mt8516-eth", },
> > - { .compatible = "mediatek,mt8518-eth", },
> > - { .compatible = "mediatek,mt8175-eth", },
> > + { .compatible = "mediatek,mt8516-eth",
> > + .data = &mtk_star_mt8516_compat },
> > + { .compatible = "mediatek,mt8518-eth",
> > + .data = &mtk_star_mt8516_compat },
> > + { .compatible = "mediatek,mt8175-eth",
> > + .data = &mtk_star_mt8516_compat },
> > { }
> > };
> > MODULE_DEVICE_TABLE(of, mtk_star_of_match);
> > --
> > 2.25.1
> >
^ permalink raw reply
* Re: [PATCH net-next v3 2/2] net: dsa: microchip: Add property to disable reference clock
From: Florian Fainelli @ 2022-01-27 0:42 UTC (permalink / raw)
To: Robert Hancock, netdev
Cc: woojung.huh, UNGLinuxDriver, andrew, vivien.didelot, olteanv,
davem, kuba, robh+dt, marex, devicetree
In-Reply-To: <20220127003318.3633212-3-robert.hancock@calian.com>
On 1/26/2022 4:33 PM, Robert Hancock wrote:
> Add a new microchip,synclko-disable property which can be specified
> to disable the reference clock output from the device if not required
> by the board design.
>
> Signed-off-by: Robert Hancock <robert.hancock@calian.com>
This looks good, I would just have done the hunk below a bit differently:
> ---
> drivers/net/dsa/microchip/ksz9477.c | 7 ++++++-
> drivers/net/dsa/microchip/ksz_common.c | 6 ++++++
> drivers/net/dsa/microchip/ksz_common.h | 1 +
> 3 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/dsa/microchip/ksz9477.c b/drivers/net/dsa/microchip/ksz9477.c
> index 353b5f981740..33d52050cd68 100644
> --- a/drivers/net/dsa/microchip/ksz9477.c
> +++ b/drivers/net/dsa/microchip/ksz9477.c
> @@ -222,9 +222,14 @@ static int ksz9477_reset_switch(struct ksz_device *dev)
> (BROADCAST_STORM_VALUE *
> BROADCAST_STORM_PROT_RATE) / 100);
>
> - if (dev->synclko_125)
> + if (dev->synclko_disable)
> + ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, 0);
> + else if (dev->synclko_125)
> ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
> SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ);
> + else
> + ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
> + SW_ENABLE_REFCLKO);
Since you write to the same register in all of these branches, why not
do this:
u32 tmp = SW_ENABLE_REFCLKO;
if (dev->synclko_disable)
tmp = 0
else if (dev->synclko_125)
tmp = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ;
ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, tmp);
even though the compiler may just do that for you under the hood.
--
Florian
^ permalink raw reply
* [PATCH net-next v3 0/2] Allow disabling KSZ switch refclock
From: Robert Hancock @ 2022-01-27 0:33 UTC (permalink / raw)
To: netdev
Cc: woojung.huh, UNGLinuxDriver, andrew, vivien.didelot, f.fainelli,
olteanv, davem, kuba, robh+dt, marex, devicetree, Robert Hancock
The reference clock output from the KSZ9477 and related Microchip
switch devices is not required on all board designs. Add a device
tree property to disable it for power and EMI reasons.
Changes since v2:
-check for conflicting options in DT, added note in bindings doc
Changes since v1:
-added Acked-by on patch 1, rebase to net-next
Robert Hancock (2):
net: dsa: microchip: Document property to disable reference clock
net: dsa: microchip: Add property to disable reference clock
.../devicetree/bindings/net/dsa/microchip,ksz.yaml | 6 ++++++
drivers/net/dsa/microchip/ksz9477.c | 7 ++++++-
drivers/net/dsa/microchip/ksz_common.c | 6 ++++++
drivers/net/dsa/microchip/ksz_common.h | 1 +
4 files changed, 19 insertions(+), 1 deletion(-)
--
2.31.1
^ permalink raw reply
* [PATCH net-next v3 1/2] net: dsa: microchip: Document property to disable reference clock
From: Robert Hancock @ 2022-01-27 0:33 UTC (permalink / raw)
To: netdev
Cc: woojung.huh, UNGLinuxDriver, andrew, vivien.didelot, f.fainelli,
olteanv, davem, kuba, robh+dt, marex, devicetree, Robert Hancock,
Rob Herring
In-Reply-To: <20220127003318.3633212-1-robert.hancock@calian.com>
Document the new microchip,synclko-disable property which can be
specified to disable the reference clock output from the device if not
required by the board design.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/net/dsa/microchip,ksz.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml
index 84985f53bffd..184152087b60 100644
--- a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml
+++ b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml
@@ -42,6 +42,12 @@ properties:
description:
Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
+ microchip,synclko-disable:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Set if the output SYNCLKO clock should be disabled. Do not mix with
+ microchip,synclko-125.
+
required:
- compatible
- reg
--
2.31.1
^ permalink raw reply related
* [PATCH net-next v3 2/2] net: dsa: microchip: Add property to disable reference clock
From: Robert Hancock @ 2022-01-27 0:33 UTC (permalink / raw)
To: netdev
Cc: woojung.huh, UNGLinuxDriver, andrew, vivien.didelot, f.fainelli,
olteanv, davem, kuba, robh+dt, marex, devicetree, Robert Hancock
In-Reply-To: <20220127003318.3633212-1-robert.hancock@calian.com>
Add a new microchip,synclko-disable property which can be specified
to disable the reference clock output from the device if not required
by the board design.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
drivers/net/dsa/microchip/ksz9477.c | 7 ++++++-
drivers/net/dsa/microchip/ksz_common.c | 6 ++++++
drivers/net/dsa/microchip/ksz_common.h | 1 +
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/microchip/ksz9477.c b/drivers/net/dsa/microchip/ksz9477.c
index 353b5f981740..33d52050cd68 100644
--- a/drivers/net/dsa/microchip/ksz9477.c
+++ b/drivers/net/dsa/microchip/ksz9477.c
@@ -222,9 +222,14 @@ static int ksz9477_reset_switch(struct ksz_device *dev)
(BROADCAST_STORM_VALUE *
BROADCAST_STORM_PROT_RATE) / 100);
- if (dev->synclko_125)
+ if (dev->synclko_disable)
+ ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, 0);
+ else if (dev->synclko_125)
ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ);
+ else
+ ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
+ SW_ENABLE_REFCLKO);
return 0;
}
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 55dbda04ea62..7e33ec73f803 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -434,6 +434,12 @@ int ksz_switch_register(struct ksz_device *dev,
}
dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
"microchip,synclko-125");
+ dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
+ "microchip,synclko-disable");
+ if (dev->synclko_125 && dev->synclko_disable) {
+ dev_err(dev->dev, "inconsistent synclko settings\n");
+ return -EINVAL;
+ }
}
ret = dsa_register_switch(dev->ds);
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index df8ae59c8525..3db63f62f0a1 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -75,6 +75,7 @@ struct ksz_device {
u32 regs_size;
bool phy_errata_9477;
bool synclko_125;
+ bool synclko_disable;
struct vlan_table *vlan_cache;
--
2.31.1
^ permalink raw reply related
* [PATCH net-next v3 1/3] dt-bindings: net: cdns,macb: added generic PHY and reset mappings for ZynqMP
From: Robert Hancock @ 2022-01-27 0:27 UTC (permalink / raw)
To: netdev
Cc: davem, kuba, robh+dt, michal.simek, nicolas.ferre, claudiu.beznea,
devicetree, Robert Hancock
In-Reply-To: <20220127002711.3632101-1-robert.hancock@calian.com>
Updated macb DT binding documentation to reflect the phy-names, phys,
resets, reset-names properties which are now used with ZynqMP GEM
devices, and added a ZynqMP-specific DT example.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
.../devicetree/bindings/net/cdns,macb.yaml | 56 +++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml
index 8dd06db34169..6cd3d853dcba 100644
--- a/Documentation/devicetree/bindings/net/cdns,macb.yaml
+++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml
@@ -81,6 +81,25 @@ properties:
phy-handle: true
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: sgmii-phy
+ description:
+ Required with ZynqMP SoC when in SGMII mode.
+ Should reference PS-GTR generic PHY device for this controller
+ instance. See ZynqMP example.
+
+ resets:
+ maxItems: 1
+ description:
+ Recommended with ZynqMP, specify reset control for this
+ controller instance with zynqmp-reset driver.
+
+ reset-names:
+ maxItems: 1
+
fixed-link: true
iommus:
@@ -157,3 +176,40 @@ examples:
reset-gpios = <&pioE 6 1>;
};
};
+
+ - |
+ #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
+ #include <dt-bindings/power/xlnx-zynqmp-power.h>
+ #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
+ #include <dt-bindings/phy/phy.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ gem1: ethernet@ff0c0000 {
+ compatible = "cdns,zynqmp-gem", "cdns,gem";
+ interrupt-parent = <&gic>;
+ interrupts = <0 59 4>, <0 59 4>;
+ reg = <0x0 0xff0c0000 0x0 0x1000>;
+ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
+ <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
+ <&zynqmp_clk GEM_TSU>;
+ clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #stream-id-cells = <1>;
+ iommus = <&smmu 0x875>;
+ power-domains = <&zynqmp_firmware PD_ETH_1>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
+ reset-names = "gem1_rst";
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-names = "sgmii-phy";
+ phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
--
2.31.1
^ permalink raw reply related
* [PATCH net-next v3 2/3] net: macb: Added ZynqMP-specific initialization
From: Robert Hancock @ 2022-01-27 0:27 UTC (permalink / raw)
To: netdev
Cc: davem, kuba, robh+dt, michal.simek, nicolas.ferre, claudiu.beznea,
devicetree, Robert Hancock
In-Reply-To: <20220127002711.3632101-1-robert.hancock@calian.com>
The GEM controllers on ZynqMP were missing some initialization steps which
are required in some cases when using SGMII mode, which uses the PS-GTR
transceivers managed by the phy-zynqmp driver.
The GEM core appears to need a hardware-level reset in order to work
properly in SGMII mode in cases where the GT reference clock was not
present at initial power-on. This can be done using a reset mapped to
the zynqmp-reset driver in the device tree.
Also, when in SGMII mode, the GEM driver needs to ensure the PHY is
initialized and powered on.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
drivers/net/ethernet/cadence/macb.h | 5 +++
drivers/net/ethernet/cadence/macb_main.c | 53 +++++++++++++++++++++++-
2 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index 9ddbee7de72b..584336b7cdaf 100644
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -12,6 +12,7 @@
#include <linux/ptp_clock_kernel.h>
#include <linux/net_tstamp.h>
#include <linux/interrupt.h>
+#include <linux/phy/phy.h>
#if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
#define MACB_EXT_DESC
@@ -1291,6 +1292,9 @@ struct macb {
u32 wol;
struct macb_ptp_info *ptp_info; /* macb-ptp interface */
+
+ struct phy *sgmii_phy; /* for ZynqMP SGMII mode */
+
#ifdef MACB_EXT_DESC
uint8_t hw_dma_cap;
#endif
@@ -1315,6 +1319,7 @@ struct macb {
struct macb_pm_data pm_data;
const struct macb_usrio_config *usrio;
+
};
#ifdef CONFIG_MACB_USE_HWSTAMP
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index a363da928e8b..4787196e0980 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -34,7 +34,9 @@
#include <linux/udp.h>
#include <linux/tcp.h>
#include <linux/iopoll.h>
+#include <linux/phy/phy.h>
#include <linux/pm_runtime.h>
+#include <linux/reset.h>
#include "macb.h"
/* This structure is only used for MACB on SiFive FU540 devices */
@@ -2739,6 +2741,10 @@ static int macb_open(struct net_device *dev)
macb_init_hw(bp);
+ err = phy_power_on(bp->sgmii_phy);
+ if (err)
+ goto reset_hw;
+
err = macb_phylink_connect(bp);
if (err)
goto reset_hw;
@@ -2775,6 +2781,8 @@ static int macb_close(struct net_device *dev)
phylink_stop(bp->phylink);
phylink_disconnect_phy(bp->phylink);
+ phy_power_off(bp->sgmii_phy);
+
spin_lock_irqsave(&bp->lock, flags);
macb_reset_hw(bp);
netif_carrier_off(dev);
@@ -4544,13 +4552,50 @@ static const struct macb_config np4_config = {
.usrio = &macb_default_usrio,
};
+static int zynqmp_init(struct platform_device *pdev)
+{
+ struct net_device *dev = platform_get_drvdata(pdev);
+ struct macb *bp = netdev_priv(dev);
+ int ret;
+
+ if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ /* Ensure PS-GTR PHY device used in SGMII mode is ready */
+ bp->sgmii_phy = devm_phy_get(&pdev->dev, "sgmii-phy");
+
+ if (IS_ERR(bp->sgmii_phy)) {
+ ret = PTR_ERR(bp->sgmii_phy);
+ dev_err_probe(&pdev->dev, ret,
+ "failed to get PS-GTR PHY\n");
+ return ret;
+ }
+
+ ret = phy_init(bp->sgmii_phy);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to init PS-GTR PHY: %d\n",
+ ret);
+ return ret;
+ }
+ }
+
+ /* Fully reset GEM controller at hardware level using zynqmp-reset driver,
+ * if mapped in device tree.
+ */
+ ret = device_reset_optional(&pdev->dev);
+ if (ret) {
+ dev_err_probe(&pdev->dev, ret, "failed to reset controller");
+ return ret;
+ }
+
+ return macb_init(pdev);
+}
+
static const struct macb_config zynqmp_config = {
.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
MACB_CAPS_JUMBO |
MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
.dma_burst_length = 16,
.clk_init = macb_clk_init,
- .init = macb_init,
+ .init = zynqmp_init,
.jumbo_max_len = 10240,
.usrio = &macb_default_usrio,
};
@@ -4767,7 +4812,7 @@ static int macb_probe(struct platform_device *pdev)
err = macb_mii_init(bp);
if (err)
- goto err_out_free_netdev;
+ goto err_out_phy_exit;
netif_carrier_off(dev);
@@ -4792,6 +4837,9 @@ static int macb_probe(struct platform_device *pdev)
mdiobus_unregister(bp->mii_bus);
mdiobus_free(bp->mii_bus);
+err_out_phy_exit:
+ phy_exit(bp->sgmii_phy);
+
err_out_free_netdev:
free_netdev(dev);
@@ -4813,6 +4861,7 @@ static int macb_remove(struct platform_device *pdev)
if (dev) {
bp = netdev_priv(dev);
+ phy_exit(bp->sgmii_phy);
mdiobus_unregister(bp->mii_bus);
mdiobus_free(bp->mii_bus);
--
2.31.1
^ permalink raw reply related
* [PATCH net-next v3 0/3] Cadence MACB/GEM support for ZynqMP SGMII
From: Robert Hancock @ 2022-01-27 0:27 UTC (permalink / raw)
To: netdev
Cc: davem, kuba, robh+dt, michal.simek, nicolas.ferre, claudiu.beznea,
devicetree, Robert Hancock
Changes to allow SGMII mode to work properly in the GEM driver on the
Xilinx ZynqMP platform.
Changes since v2:
-fixed missing includes in DT binding example
-fixed phy_init and phy_power_on error handling/cleanup, moved
phy_power_on to open rather than probe
Changes since v1:
-changed order of controller reset and PHY init as per suggestion
-switched device reset to be optional
-updated bindings doc patch for switch to YAML
Robert Hancock (3):
dt-bindings: net: cdns,macb: added generic PHY and reset mappings for
ZynqMP
net: macb: Added ZynqMP-specific initialization
arm64: dts: zynqmp: Added GEM reset definitions
.../devicetree/bindings/net/cdns,macb.yaml | 56 +++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 +++
drivers/net/ethernet/cadence/macb.h | 5 ++
drivers/net/ethernet/cadence/macb_main.c | 53 +++++++++++++++++-
4 files changed, 120 insertions(+), 2 deletions(-)
--
2.31.1
^ permalink raw reply
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