* [PATCH v4 3/4] arm64: dts: imx8dxl: update cm40 irq number information
From: Frank Li @ 2024-03-29 16:37 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li
In-Reply-To: <20240329-m4_lpuart-v4-0-c11d9ca2a317@nxp.com>
Update cm40 irq number for imx8dxl chip.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
index 9d49c75a26222..b9d137d69f5a7 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -243,3 +243,14 @@ xtal24m: clock-xtal24m {
#include "imx8dxl-ss-conn.dtsi"
#include "imx8dxl-ss-lsio.dtsi"
#include "imx8dxl-ss-ddr.dtsi"
+
+&cm40_intmux {
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+};
--
2.34.1
^ permalink raw reply related
* [PATCH v4 2/4] arm64: dts: imx8dxl: add lpuart device in cm40 subsystem
From: Frank Li @ 2024-03-29 16:37 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li,
Alice Guo, Peng Fan, Alexander Stein
In-Reply-To: <20240329-m4_lpuart-v4-0-c11d9ca2a317@nxp.com>
From: Alice Guo <alice.guo@nxp.com>
Add lpuart device in cm40 subsystem.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
index 10a05db06ade9..5cff052b95d18 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
@@ -20,6 +20,18 @@ cm40_subsys: bus@34000000 {
ranges = <0x34000000 0x0 0x34000000 0x4000000>;
interrupt-parent = <&cm40_intmux>;
+ cm40_lpuart: serial@37220000 {
+ compatible = "fsl,imx8qxp-lpuart";
+ reg = <0x37220000 0x1000>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cm40_uart_lpcg IMX_LPCG_CLK_1>, <&cm40_uart_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "ipg", "baud";
+ assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_M4_0_UART>;
+ status = "disabled";
+ };
+
cm40_i2c: i2c@37230000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x37230000 0x1000>;
@@ -53,6 +65,18 @@ cm40_intmux: intmux@37400000 {
status = "disabled";
};
+ cm40_uart_lpcg: clock-controller@37620000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x37620000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>,
+ <&cm40_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>;
+ clock-output-names = "cm40_lpcg_uart_clk",
+ "cm40_lpcg_uart_ipg_clk";
+ power-domains = <&pd IMX_SC_R_M4_0_UART>;
+ };
+
cm40_i2c_lpcg: clock-controller@37630000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x37630000 0x1000>;
--
2.34.1
^ permalink raw reply related
* [PATCH v4 1/4] arm64: dts: imx8: add cm40 subsystem dtsi
From: Frank Li @ 2024-03-29 16:37 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li,
Dong Aisheng, Alexander Stein
In-Reply-To: <20240329-m4_lpuart-v4-0-c11d9ca2a317@nxp.com>
From: Dong Aisheng <aisheng.dong@nxp.com>
Add cm40 subsystem dtsi.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 67 +++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 +
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
3 files changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
new file mode 100644
index 0000000000000..10a05db06ade9
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+cm40_ipg_clk: clock-cm40-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <132000000>;
+ clock-output-names = "cm40_ipg_clk";
+};
+
+cm40_subsys: bus@34000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x34000000 0x0 0x34000000 0x4000000>;
+ interrupt-parent = <&cm40_intmux>;
+
+ cm40_i2c: i2c@37230000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x37230000 0x1000>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cm40_i2c_lpcg IMX_LPCG_CLK_0>,
+ <&cm40_i2c_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_M4_0_I2C>;
+ status = "disabled";
+ };
+
+ cm40_intmux: intmux@37400000 {
+ compatible = "fsl,imx-intmux";
+ reg = <0x37400000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&cm40_ipg_clk>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
+ status = "disabled";
+ };
+
+ cm40_i2c_lpcg: clock-controller@37630000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x37630000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
+ <&cm40_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "cm40_lpcg_i2c_clk",
+ "cm40_lpcg_i2c_ipg_clk";
+ power-domains = <&pd IMX_SC_R_M4_0_I2C>;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
index a0674c5c55766..9d49c75a26222 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/dma/fsl-edma.h>
+#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -231,6 +232,7 @@ xtal24m: clock-xtal24m {
};
/* sorted in register address */
+ #include "imx8-ss-cm40.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-ddr.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 10e16d84c0c3b..0313f295de2e9 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -317,6 +317,7 @@ map0 {
/* sorted in register address */
#include "imx8-ss-img.dtsi"
#include "imx8-ss-vpu.dtsi"
+ #include "imx8-ss-cm40.dtsi"
#include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
--
2.34.1
^ permalink raw reply related
* [PATCH v4 0/4] arm64: dts: imx8: add cm40 and cm40_uart
From: Frank Li @ 2024-03-29 16:37 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Frank Li,
Dong Aisheng, Alexander Stein, Alice Guo, Peng Fan
Add cm40 subsystem.
Add cm40_lpuart and lpurt1 for 8dxl evk boards.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Changes in v4:
- fixed lpcg index.
- fixed typo 'informaiton'.
- fixed fixregulator name
- Link to v3: https://lore.kernel.org/r/20240305-m4_lpuart-v3-0-592463ef1d22@nxp.com
Changes in v3:
- Add Alexander review tags
- move interrupt-parent below range.
- move interrupt-parent before interrutps at intmux node
- Link to v2: https://lore.kernel.org/r/20240302-m4_lpuart-v2-0-89a5952043b6@nxp.com
Changes in v2:
- commit message "Adding" to Add
- fixed regulator@101 warning
- remove 'modem reset'
- order nodes by access
- move interrupt-parent under top bus
- clean up other dtb check warning
- Link to v1: https://lore.kernel.org/r/20240228-m4_lpuart-v1-0-9e6947be15e7@nxp.com
---
Alice Guo (1):
arm64: dts: imx8dxl: add lpuart device in cm40 subsystem
Dong Aisheng (1):
arm64: dts: imx8: add cm40 subsystem dtsi
Frank Li (2):
arm64: dts: imx8dxl: update cm40 irq number information
dts: arm64: imx8dxl-evk: add lpuart1 and cm40 uart
arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 91 +++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 37 ++++++++++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 13 ++++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
4 files changed, 142 insertions(+)
---
base-commit: 9acc053fc8f256959e849cb6588a054074daebcd
change-id: 20240228-m4_lpuart-30791c032f2a
Best regards,
---
Frank Li <Frank.Li@nxp.com>
^ permalink raw reply
* Re: [PATCH RESEND v6 3/5] spmi: pmic-arb: Make the APID init a version operation
From: Abel Vesa @ 2024-03-29 16:32 UTC (permalink / raw)
To: Neil Armstrong
Cc: Stephen Boyd, Matthias Brugger, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Srini Kandagatla, Johan Hovold,
linux-kernel, linux-arm-kernel, linux-arm-msm, linux-mediatek,
devicetree
In-Reply-To: <9af9cfd1-38c7-4f38-a652-fd046f427f98@linaro.org>
On 24-03-28 09:51:49, Neil Armstrong wrote:
> On 26/03/2024 17:28, Abel Vesa wrote:
> > Rather than using conditionals in probe function, add the APID init
> > as a version specific operation. Due to v7, which supports multiple
> > buses, pass on the bus index to be used for sorting out the apid base
> > and count.
> >
> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > ---
> > drivers/spmi/spmi-pmic-arb.c | 199 +++++++++++++++++++++++++++----------------
> > 1 file changed, 124 insertions(+), 75 deletions(-)
> >
> > diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c
> > index 9ed1180fe31f..38fed8a585fe 100644
> > --- a/drivers/spmi/spmi-pmic-arb.c
> > +++ b/drivers/spmi/spmi-pmic-arb.c
> > @@ -183,6 +183,7 @@ struct spmi_pmic_arb {
> > * struct pmic_arb_ver_ops - version dependent functionality.
> > *
> > * @ver_str: version string.
> > + * @init_apid: finds the apid base and count
> > * @ppid_to_apid: finds the apid for a given ppid.
> > * @non_data_cmd: on v1 issues an spmi non-data command.
> > * on v2 no HW support, returns -EOPNOTSUPP.
> > @@ -202,6 +203,7 @@ struct spmi_pmic_arb {
> > */
> > struct pmic_arb_ver_ops {
> > const char *ver_str;
> > + int (*init_apid)(struct spmi_pmic_arb *pmic_arb, int index);
> > int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
> > /* spmi commands (read_cmd, write_cmd, cmd) functionality */
> > int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
> > @@ -942,6 +944,38 @@ static int qpnpint_irq_domain_alloc(struct irq_domain *domain,
> > return 0;
> > }
> > +static int pmic_arb_init_apid_min_max(struct spmi_pmic_arb *pmic_arb)
> > +{
> > + /*
> > + * Initialize max_apid/min_apid to the opposite bounds, during
> > + * the irq domain translation, we are sure to update these
> > + */
> > + pmic_arb->max_apid = 0;
> > + pmic_arb->min_apid = pmic_arb->max_periphs - 1;
> > +
> > + return 0;
> > +}
> > +
> > +static int pmic_arb_init_apid_v1(struct spmi_pmic_arb *pmic_arb, int index)
> > +{
> > + u32 *mapping_table;
> > +
> > + if (index) {
> > + dev_err(&pmic_arb->spmic->dev, "Unsupported buses count %d detected\n",
> > + index);
> > + return -EINVAL;
> > + }
> > +
> > + mapping_table = devm_kcalloc(&pmic_arb->spmic->dev, pmic_arb->max_periphs,
> > + sizeof(*mapping_table), GFP_KERNEL);
> > + if (!mapping_table)
> > + return -ENOMEM;
> > +
> > + pmic_arb->mapping_table = mapping_table;
>
> Can you specify in the spmi_pmic_arb->mapping_table struct documentation the mapping_table
> is only used in v1 ? or even better rename it to mapping_table_v1
>
Actually the mapping_table is used on version 1 through 3.
^ permalink raw reply
* [PATCH 1/2] iio: imu: inv_icm42600: add support of ICM-42688-P
From: inv.git-commit @ 2024-03-29 15:15 UTC (permalink / raw)
To: jic23, robh, krzysztof.kozlowski+dt, conor+dt
Cc: lars, linux-iio, devicetree, Jean-Baptiste Maneyrol
In-Reply-To: <20240329151535.712827-1-inv.git-commit@tdk.com>
From: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
Signed-off-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
---
drivers/iio/imu/inv_icm42600/inv_icm42600.h | 2 ++
drivers/iio/imu/inv_icm42600/inv_icm42600_core.c | 5 +++++
drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c | 3 +++
drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c | 3 +++
4 files changed, 13 insertions(+)
diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600.h b/drivers/iio/imu/inv_icm42600/inv_icm42600.h
index 0e290c807b0f..0566340b2660 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600.h
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600.h
@@ -22,6 +22,7 @@ enum inv_icm42600_chip {
INV_CHIP_ICM42602,
INV_CHIP_ICM42605,
INV_CHIP_ICM42622,
+ INV_CHIP_ICM42688,
INV_CHIP_ICM42631,
INV_CHIP_NB,
};
@@ -304,6 +305,7 @@ struct inv_icm42600_state {
#define INV_ICM42600_WHOAMI_ICM42602 0x41
#define INV_ICM42600_WHOAMI_ICM42605 0x42
#define INV_ICM42600_WHOAMI_ICM42622 0x46
+#define INV_ICM42600_WHOAMI_ICM42688 0x47
#define INV_ICM42600_WHOAMI_ICM42631 0x5C
/* User bank 1 (MSB 0x10) */
diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c
index a5e81906e37e..82e0a2e2ad70 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c
@@ -87,6 +87,11 @@ static const struct inv_icm42600_hw inv_icm42600_hw[INV_CHIP_NB] = {
.name = "icm42622",
.conf = &inv_icm42600_default_conf,
},
+ [INV_CHIP_ICM42688] = {
+ .whoami = INV_ICM42600_WHOAMI_ICM42688,
+ .name = "icm42688",
+ .conf = &inv_icm42600_default_conf,
+ },
[INV_CHIP_ICM42631] = {
.whoami = INV_ICM42600_WHOAMI_ICM42631,
.name = "icm42631",
diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c
index 1af559403ba6..ebb28f84ba98 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c
@@ -84,6 +84,9 @@ static const struct of_device_id inv_icm42600_of_matches[] = {
}, {
.compatible = "invensense,icm42622",
.data = (void *)INV_CHIP_ICM42622,
+ }, {
+ .compatible = "invensense,icm42688",
+ .data = (void *)INV_CHIP_ICM42688,
}, {
.compatible = "invensense,icm42631",
.data = (void *)INV_CHIP_ICM42631,
diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c
index 6be4ac794937..50217a10e0bb 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c
@@ -80,6 +80,9 @@ static const struct of_device_id inv_icm42600_of_matches[] = {
}, {
.compatible = "invensense,icm42622",
.data = (void *)INV_CHIP_ICM42622,
+ }, {
+ .compatible = "invensense,icm42688",
+ .data = (void *)INV_CHIP_ICM42688,
}, {
.compatible = "invensense,icm42631",
.data = (void *)INV_CHIP_ICM42631,
--
2.34.1
^ permalink raw reply related
* [PATCH 2/2] dt-bindings: iio: imu: add icm42688 inside inv_icm42600
From: inv.git-commit @ 2024-03-29 15:15 UTC (permalink / raw)
To: jic23, robh, krzysztof.kozlowski+dt, conor+dt
Cc: lars, linux-iio, devicetree, Jean-Baptiste Maneyrol
In-Reply-To: <20240329151535.712827-1-inv.git-commit@tdk.com>
From: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
Add bindings for ICM-42688-P chip.
Signed-off-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
---
.../devicetree/bindings/iio/imu/invensense,icm42600.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
index 7cd05bcbee31..152aec8d82ff 100644
--- a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
+++ b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
@@ -31,6 +31,7 @@ properties:
- invensense,icm42602
- invensense,icm42605
- invensense,icm42622
+ - invensense,icm42688
- invensense,icm42631
reg:
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v11 2/7] clk: meson: add vclk driver
From: Neil Armstrong @ 2024-03-29 16:07 UTC (permalink / raw)
To: Jerome Brunet
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Kevin Hilman,
Michael Turquette, Stephen Boyd, Martin Blumenstingl,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Daniel Vetter, Nicolas Belin, Jagan Teki, devicetree,
linux-kernel, linux-amlogic, linux-clk, linux-arm-kernel,
dri-devel
In-Reply-To: <1jzfuh8bd7.fsf@starbuckisacylon.baylibre.com>
On 29/03/2024 13:33, Jerome Brunet wrote:
>
> On Mon 25 Mar 2024 at 12:09, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
>> The VCLK and VCLK_DIV clocks have supplementary bits.
>>
>> The VCLK gate has a "SOFT RESET" bit to toggle after the whole
>> VCLK sub-tree rate has been set, this is implemented in
>> the gate enable callback.
>>
>> The VCLK_DIV clocks as enable and reset bits used to disable
>> and reset the divider, associated with CLK_SET_RATE_GATE it ensures
>> the rate is set while the divider is disabled and in reset mode.
>>
>> The VCLK_DIV enable bit isn't implemented as a gate since it's part
>> of the divider logic and vendor does this exact sequence to ensure
>> the divider is correctly set.
>
> checkpatch reports a few easy CHECKs and one WARNING.
> Could you please fix these ?
>
> Other than that, It looks OK.
Ack
thx
Neil
>
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> drivers/clk/meson/Kconfig | 4 ++
>> drivers/clk/meson/Makefile | 1 +
>> drivers/clk/meson/vclk.c | 141 +++++++++++++++++++++++++++++++++++++++++++++
>> drivers/clk/meson/vclk.h | 51 ++++++++++++++++
>> 4 files changed, 197 insertions(+)
>>
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index 29ffd14d267b..8a9823789fa3 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -30,6 +30,10 @@ config COMMON_CLK_MESON_VID_PLL_DIV
>> tristate
>> select COMMON_CLK_MESON_REGMAP
>>
>> +config COMMON_CLK_MESON_VCLK
>> + tristate
>> + select COMMON_CLK_MESON_REGMAP
>> +
>> config COMMON_CLK_MESON_CLKC_UTILS
>> tristate
>>
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index 9ee4b954c896..9ba43fe7a07a 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
>> obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
>> obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
>> obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
>> +obj-$(CONFIG_COMMON_CLK_MESON_VCLK) += vclk.o
>>
>> # Amlogic Clock controllers
>>
>> diff --git a/drivers/clk/meson/vclk.c b/drivers/clk/meson/vclk.c
>> new file mode 100644
>> index 000000000000..3ea813a0a995
>> --- /dev/null
>> +++ b/drivers/clk/meson/vclk.c
>> @@ -0,0 +1,141 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
>> + */
>> +
>> +#include <linux/module.h>
>> +#include "vclk.h"
>> +
>> +/* The VCLK gate has a supplementary reset bit to pulse after ungating */
>> +
>> +static inline struct meson_vclk_gate_data *
>> +clk_get_meson_vclk_gate_data(struct clk_regmap *clk)
>> +{
>> + return (struct meson_vclk_gate_data *)clk->data;
>> +}
>> +
>> +static int meson_vclk_gate_enable(struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
>> +
>> + meson_parm_write(clk->map, &vclk->enable, 1);
>> +
>> + /* Do a reset pulse */
>> + meson_parm_write(clk->map, &vclk->reset, 1);
>> + meson_parm_write(clk->map, &vclk->reset, 0);
>> +
>> + return 0;
>> +}
>> +
>> +static void meson_vclk_gate_disable(struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
>> +
>> + meson_parm_write(clk->map, &vclk->enable, 0);
>> +}
>> +
>> +static int meson_vclk_gate_is_enabled(struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_gate_data *vclk = clk_get_meson_vclk_gate_data(clk);
>> +
>> + return meson_parm_read(clk->map, &vclk->enable);
>> +}
>> +
>> +const struct clk_ops meson_vclk_gate_ops = {
>> + .enable = meson_vclk_gate_enable,
>> + .disable = meson_vclk_gate_disable,
>> + .is_enabled = meson_vclk_gate_is_enabled,
>> +};
>> +EXPORT_SYMBOL_GPL(meson_vclk_gate_ops);
>> +
>> +/* The VCLK Divider has supplementary reset & enable bits */
>> +
>> +static inline struct meson_vclk_div_data *
>> +clk_get_meson_vclk_div_data(struct clk_regmap *clk)
>> +{
>> + return (struct meson_vclk_div_data *)clk->data;
>> +}
>> +
>> +static unsigned long meson_vclk_div_recalc_rate(struct clk_hw *hw,
>> + unsigned long prate)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>> +
>> + return divider_recalc_rate(hw, prate, meson_parm_read(clk->map, &vclk->div),
>> + vclk->table, vclk->flags, vclk->div.width);
>> +}
>> +
>> +static int meson_vclk_div_determine_rate(struct clk_hw *hw,
>> + struct clk_rate_request *req)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>> +
>> + return divider_determine_rate(hw, req, vclk->table, vclk->div.width,
>> + vclk->flags);
>> +}
>> +
>> +static int meson_vclk_div_set_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long parent_rate)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>> + int ret;
>> +
>> + ret = divider_get_val(rate, parent_rate, vclk->table, vclk->div.width,
>> + vclk->flags);
>> + if (ret < 0)
>> + return ret;
>> +
>> + meson_parm_write(clk->map, &vclk->div, ret);
>> +
>> + return 0;
>> +};
>> +
>> +static int meson_vclk_div_enable(struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>> +
>> + /* Unreset the divider when ungating */
>> + meson_parm_write(clk->map, &vclk->reset, 0);
>> + meson_parm_write(clk->map, &vclk->enable, 1);
>> +
>> + return 0;
>> +}
>> +
>> +static void meson_vclk_div_disable(struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>> +
>> + /* Reset the divider when gating */
>> + meson_parm_write(clk->map, &vclk->enable, 0);
>> + meson_parm_write(clk->map, &vclk->reset, 1);
>> +}
>> +
>> +static int meson_vclk_div_is_enabled(struct clk_hw *hw)
>> +{
>> + struct clk_regmap *clk = to_clk_regmap(hw);
>> + struct meson_vclk_div_data *vclk = clk_get_meson_vclk_div_data(clk);
>> +
>> + return meson_parm_read(clk->map, &vclk->enable);
>> +}
>> +
>> +const struct clk_ops meson_vclk_div_ops = {
>> + .recalc_rate = meson_vclk_div_recalc_rate,
>> + .determine_rate = meson_vclk_div_determine_rate,
>> + .set_rate = meson_vclk_div_set_rate,
>> + .enable = meson_vclk_div_enable,
>> + .disable = meson_vclk_div_disable,
>> + .is_enabled = meson_vclk_div_is_enabled,
>> +};
>> +EXPORT_SYMBOL_GPL(meson_vclk_div_ops);
>> +
>> +MODULE_DESCRIPTION("Amlogic vclk clock driver");
>> +MODULE_AUTHOR("Neil Armstrong <neil.armstrong@linaro.org>");
>> +MODULE_LICENSE("GPL v2");
>> diff --git a/drivers/clk/meson/vclk.h b/drivers/clk/meson/vclk.h
>> new file mode 100644
>> index 000000000000..20b0b181db09
>> --- /dev/null
>> +++ b/drivers/clk/meson/vclk.h
>> @@ -0,0 +1,51 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
>> + */
>> +
>> +#ifndef __VCLK_H
>> +#define __VCLK_H
>> +
>> +#include "clk-regmap.h"
>> +#include "parm.h"
>> +
>> +/**
>> + * struct meson_vclk_gate_data - vclk_gate regmap backed specific data
>> + *
>> + * @enable: vclk enable field
>> + * @reset: vclk reset field
>> + * @flags: hardware-specific flags
>> + *
>> + * Flags:
>> + * Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored
>> + */
>> +struct meson_vclk_gate_data {
>> + struct parm enable;
>> + struct parm reset;
>> + u8 flags;
>> +};
>> +
>> +extern const struct clk_ops meson_vclk_gate_ops;
>> +
>> +/**
>> + * struct meson_vclk_div_data - vclk_div regmap back specific data
>> + *
>> + * @div: divider field
>> + * @enable: vclk divider enable field
>> + * @reset: vclk divider reset field
>> + * @table: array of value/divider pairs, last entry should have div = 0
>> + *
>> + * Flags:
>> + * Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored
>> + */
>> +struct meson_vclk_div_data {
>> + struct parm div;
>> + struct parm enable;
>> + struct parm reset;
>> + const struct clk_div_table *table;
>> + u8 flags;
>> +};
>> +
>> +extern const struct clk_ops meson_vclk_div_ops;
>> +
>> +#endif /* __VCLK_H */
>
>
^ permalink raw reply
* Re: [PATCH v11 3/7] clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF
From: Neil Armstrong @ 2024-03-29 16:06 UTC (permalink / raw)
To: Jerome Brunet
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Kevin Hilman,
Michael Turquette, Stephen Boyd, Martin Blumenstingl,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Daniel Vetter, Nicolas Belin, Jagan Teki, devicetree,
linux-kernel, linux-amlogic, linux-clk, linux-arm-kernel,
dri-devel
In-Reply-To: <1jv8558b11.fsf@starbuckisacylon.baylibre.com>
On 29/03/2024 13:35, Jerome Brunet wrote:
>
> On Mon 25 Mar 2024 at 12:09, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
>> In order to setup the DSI clock, let's make the unused VCLK2 clock path
>> configuration via CCF.
>>
>> The nocache option is removed from following clocks:
>> - vclk2_sel
>> - vclk2_input
>> - vclk2_div
>> - vclk2
>> - vclk_div1
>> - vclk2_div2_en
>> - vclk2_div4_en
>> - vclk2_div6_en
>> - vclk2_div12_en
>> - vclk2_div2
>> - vclk2_div4
>> - vclk2_div6
>> - vclk2_div12
>> - cts_encl_sel
>>
>> vclk2 and vclk2_div uses the newly introduced vclk regmap driver
>> to handle the enable and reset bits.
>>
>> In order to set a rate on cts_encl via the vclk2 clock path,
>> the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order
>> to keep CCF from selection a parent.
>> The parents of cts_encl_sel & vclk2_sel are expected to be defined
>> in DT or manually set by the display driver at some point.
>>
>> The following clock scheme is to be used for DSI:
>>
>> xtal
>> \_ gp0_pll_dco
>> \_ gp0_pll
>> |- vclk2_sel
>> | \_ vclk2_input
>> | \_ vclk2_div
>> | \_ vclk2
>> | \_ vclk2_div1
>> | \_ cts_encl_sel
>> | \_ cts_encl -> to VPU LCD Encoder
>> |- mipi_dsi_pxclk_sel
>> \_ mipi_dsi_pxclk_div
>> \_ mipi_dsi_pxclk -> to DSI controller
>>
>> The mipi_dsi_pxclk_div is set as bypass with a single /1 entry in div_table
>> in order to use the same GP0 for mipi_dsi_pxclk and vclk2_input.
>>
>> The SET_RATE_PARENT is only set on the mipi_dsi_pxclk_sel clock so the
>> DSI bitclock is the reference base clock to calculate the vclk2_div value
>> when pixel clock is set on the cts_encl endpoint.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> drivers/clk/meson/Kconfig | 1 +
>> drivers/clk/meson/g12a.c | 72 ++++++++++++++++++++++++++++++++++-------------
>> 2 files changed, 53 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index 8a9823789fa3..59a40a49f8e1 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -144,6 +144,7 @@ config COMMON_CLK_G12A
>> select COMMON_CLK_MESON_EE_CLKC
>> select COMMON_CLK_MESON_CPU_DYNDIV
>> select COMMON_CLK_MESON_VID_PLL_DIV
>> + select COMMON_CLK_MESON_VCLK
>> select MFD_SYSCON
>> help
>> Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
>> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
>> index 90f4c6103014..083882e53b65 100644
>> --- a/drivers/clk/meson/g12a.c
>> +++ b/drivers/clk/meson/g12a.c
>> @@ -22,6 +22,7 @@
>> #include "clk-regmap.h"
>> #include "clk-cpu-dyndiv.h"
>> #include "vid-pll-div.h"
>> +#include "vclk.h"
>> #include "meson-eeclk.h"
>> #include "g12a.h"
>>
>> @@ -3165,7 +3166,7 @@ static struct clk_regmap g12a_vclk2_sel = {
>> .ops = &clk_regmap_mux_ops,
>> .parent_hws = g12a_vclk_parent_hws,
>> .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
>> - .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
>> + .flags = CLK_SET_RATE_NO_REPARENT,
>> },
>> };
>>
>> @@ -3193,7 +3194,6 @@ static struct clk_regmap g12a_vclk2_input = {
>> .ops = &clk_regmap_gate_ops,
>> .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
>> .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> },
>> };
>>
>> @@ -3215,19 +3215,32 @@ static struct clk_regmap g12a_vclk_div = {
>> };
>>
>> static struct clk_regmap g12a_vclk2_div = {
>> - .data = &(struct clk_regmap_div_data){
>> - .offset = HHI_VIID_CLK_DIV,
>> - .shift = 0,
>> - .width = 8,
>> + .data = &(struct meson_vclk_div_data){
>> + .div = {
>> + .reg_off = HHI_VIID_CLK_DIV,
>> + .shift = 0,
>> + .width = 8,
>> + },
>> + .enable = {
>> + .reg_off = HHI_VIID_CLK_DIV,
>> + .shift = 16,
>> + .width = 1,
>> + },
>> + .reset = {
>> + .reg_off = HHI_VIID_CLK_DIV,
>> + .shift = 17,
>> + .width = 1,
>> + },
>> + .flags = CLK_DIVIDER_ROUND_CLOSEST,
>> },
>> .hw.init = &(struct clk_init_data){
>> .name = "vclk2_div",
>> - .ops = &clk_regmap_divider_ops,
>> + .ops = &meson_vclk_div_ops,
>> .parent_hws = (const struct clk_hw *[]) {
>> &g12a_vclk2_input.hw
>> },
>> .num_parents = 1,
>> - .flags = CLK_GET_RATE_NOCACHE,
>> + .flags = CLK_SET_RATE_GATE,
>> },
>> };
>>
>> @@ -3246,16 +3259,24 @@ static struct clk_regmap g12a_vclk = {
>> };
>>
>> static struct clk_regmap g12a_vclk2 = {
>> - .data = &(struct clk_regmap_gate_data){
>> - .offset = HHI_VIID_CLK_CNTL,
>> - .bit_idx = 19,
>> + .data = &(struct meson_vclk_gate_data){
>> + .enable = {
>> + .reg_off = HHI_VIID_CLK_CNTL,
>> + .shift = 19,
>> + .width = 1,
>> + },
>> + .reset = {
>> + .reg_off = HHI_VIID_CLK_CNTL,
>> + .shift = 15,
>> + .width = 1,
>> + },
>> },
>> .hw.init = &(struct clk_init_data) {
>> .name = "vclk2",
>> - .ops = &clk_regmap_gate_ops,
>> + .ops = &meson_vclk_gate_ops,
>> .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
>> .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3339,7 +3360,7 @@ static struct clk_regmap g12a_vclk2_div1 = {
>> .ops = &clk_regmap_gate_ops,
>> .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>> .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3353,7 +3374,7 @@ static struct clk_regmap g12a_vclk2_div2_en = {
>> .ops = &clk_regmap_gate_ops,
>> .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>> .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3367,7 +3388,7 @@ static struct clk_regmap g12a_vclk2_div4_en = {
>> .ops = &clk_regmap_gate_ops,
>> .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>> .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3381,7 +3402,7 @@ static struct clk_regmap g12a_vclk2_div6_en = {
>> .ops = &clk_regmap_gate_ops,
>> .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>> .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3395,7 +3416,7 @@ static struct clk_regmap g12a_vclk2_div12_en = {
>> .ops = &clk_regmap_gate_ops,
>> .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
>> .num_parents = 1,
>> - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3461,6 +3482,7 @@ static struct clk_fixed_factor g12a_vclk2_div2 = {
>> &g12a_vclk2_div2_en.hw
>> },
>> .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3474,6 +3496,7 @@ static struct clk_fixed_factor g12a_vclk2_div4 = {
>> &g12a_vclk2_div4_en.hw
>> },
>> .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3487,6 +3510,7 @@ static struct clk_fixed_factor g12a_vclk2_div6 = {
>> &g12a_vclk2_div6_en.hw
>> },
>> .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3500,6 +3524,7 @@ static struct clk_fixed_factor g12a_vclk2_div12 = {
>> &g12a_vclk2_div12_en.hw
>> },
>> .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> @@ -3561,7 +3586,7 @@ static struct clk_regmap g12a_cts_encl_sel = {
>> .ops = &clk_regmap_mux_ops,
>> .parent_hws = g12a_cts_parent_hws,
>> .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
>> - .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
>> + .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
>> },
>> };
>>
>> @@ -3717,15 +3742,22 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_sel = {
>> .ops = &clk_regmap_mux_ops,
>> .parent_hws = g12a_mipi_dsi_pxclk_parent_hws,
>> .num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws),
>> - .flags = CLK_SET_RATE_NO_REPARENT,
>> + .flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
>> },
>> };
>>
>> +/* Force as bypass by forcing a single /1 table entry, and not rely of boot value */
>
> The comment here is not entirely accurate.
>
> The table below will actually force to only use a 1 divider on
> .set_rate(), not on boot, AFAICT.
>
> The boot value will stay in the register until the first call to set_rate().
>
> Considering this is quite fragile as it is, It would be nice to prefix
> the updated comment with "FIXME"
Ack
>
>> +static const struct clk_div_table g12a_mipi_dsi_pxclk_div_table[] = {
>> + { .val = 0, .div = 1 },
>> + { /* sentinel */ },
>> +};
>> +
>> static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
>> .data = &(struct clk_regmap_div_data){
>> .offset = HHI_MIPIDSI_PHY_CLK_CNTL,
>> .shift = 0,
>> .width = 7,
>> + .table = g12a_mipi_dsi_pxclk_div_table,
>> },
>> .hw.init = &(struct clk_init_data){
>> .name = "mipi_dsi_pxclk_div",
>
>
^ permalink raw reply
* Re: 回复: [PATCH v2 1/2] ASoC: dt-bindings: Add bindings for Cadence I2S-MC controller
From: Krzysztof Kozlowski @ 2024-03-29 16:01 UTC (permalink / raw)
To: Mark Brown
Cc: Xingyu Wu, Liam Girdwood, Claudiu Beznea, Jaroslav Kysela,
Takashi Iwai, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
alsa-devel@alsa-project.org, linux-sound@vger.kernel.org
In-Reply-To: <ZgbDx6oD+mMUIvH1@finisterre.sirena.org.uk>
On 29/03/2024 14:36, Mark Brown wrote:
> On Fri, Mar 29, 2024 at 12:42:22PM +0100, Krzysztof Kozlowski wrote:
>
>> I stated and I keep my statement that such block is usually not usable
>> on its own and always needs some sort of quirks or SoC-specific
>> implementation. At least this is what I saw in other similar cases, but
>> not exactly I2S.
>
> I wouldn't be so pessimistic, especially not for I2S - a good portion of
> quirks there are extra features rather than things needed for basic
> operation, a lot of things that might in the past have been quirks for
> basic operation are these days hidden behind the DT bindings.
OK, I trust your judgement, so cdns as fallback seems okay, but I don't
think it warrants cdns as used alone. Not particularly because cdns is
different, but because we expect specific SoC compatible always.
Thus if cdns,i2s-mc stays, then:
items:
- enum:
- starfive,jh8100-i2s
- cdns,i2s-mc
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 0/2] iio: imu: inv_icm42600: add support of ICM-42688-P
From: inv.git-commit @ 2024-03-29 15:15 UTC (permalink / raw)
To: jic23, robh, krzysztof.kozlowski+dt, conor+dt
Cc: lars, linux-iio, devicetree, Jean-Baptiste Maneyrol
From: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
This series is for adding support of high-end specs ICM-42688-P chip.
Jean-Baptiste Maneyrol (2):
iio: imu: inv_icm42600: add support of ICM-42688-P
dt-bindings: iio: imu: add icm42688 inside inv_icm42600
.../devicetree/bindings/iio/imu/invensense,icm42600.yaml | 1 +
drivers/iio/imu/inv_icm42600/inv_icm42600.h | 2 ++
drivers/iio/imu/inv_icm42600/inv_icm42600_core.c | 5 +++++
drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c | 3 +++
drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c | 3 +++
5 files changed, 14 insertions(+)
--
2.34.1
^ permalink raw reply
* Re: [PATCH 2/2] dt-bindings: iio: imu: add icm42688 inside inv_icm42600
From: Conor Dooley @ 2024-03-29 15:49 UTC (permalink / raw)
To: inv.git-commit
Cc: jic23, robh, krzysztof.kozlowski+dt, conor+dt, lars, linux-iio,
devicetree, Jean-Baptiste Maneyrol
In-Reply-To: <20240329151535.712827-3-inv.git-commit@tdk.com>
[-- Attachment #1: Type: text/plain, Size: 1232 bytes --]
On Fri, Mar 29, 2024 at 03:15:35PM +0000, inv.git-commit@tdk.com wrote:
> From: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
>
> Add bindings for ICM-42688-P chip.
>
> Signed-off-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
My initial thought was that you're missing a sign-off, but is
"inv.git-commit@tdk.com" some system you have to bypass corporate email
garbage?
> ---
> .../devicetree/bindings/iio/imu/invensense,icm42600.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
> index 7cd05bcbee31..152aec8d82ff 100644
> --- a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
> +++ b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
> @@ -31,6 +31,7 @@ properties:
> - invensense,icm42602
> - invensense,icm42605
> - invensense,icm42622
> + - invensense,icm42688
Can you add this in alphanumerical order please?
Also, this patch should be the first in the series.
Thanks,
Conor.
> - invensense,icm42631
>
> reg:
> --
> 2.34.1
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v3 8/9] dt-bindings: xlnx: Add VTC and TPG bindings
From: Conor Dooley @ 2024-03-29 15:46 UTC (permalink / raw)
To: Klymenko, Anatoliy
Cc: Krzysztof Kozlowski, Laurent Pinchart, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Daniel Vetter,
Simek, Michal, Andrzej Hajda, Neil Armstrong, Robert Foss,
Jonas Karlman, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mauro Carvalho Chehab, Tomi Valkeinen,
dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-media@vger.kernel.org
In-Reply-To: <MW4PR12MB716570A3676218F0C6375E37E63A2@MW4PR12MB7165.namprd12.prod.outlook.com>
[-- Attachment #1: Type: text/plain, Size: 2943 bytes --]
On Fri, Mar 29, 2024 at 12:38:33AM +0000, Klymenko, Anatoliy wrote:
> Thank you for the feedback.
> > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > Subject: Re: [PATCH v3 8/9] dt-bindings: xlnx: Add VTC and TPG bindings
> > On 22/03/2024 20:12, Klymenko, Anatoliy wrote:
> > >> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > >> On 21/03/2024 21:43, Anatoliy Klymenko wrote:
> > >>> diff --git a/include/dt-bindings/media/media-bus-format.h
> > >>> b/include/dt-
> > >> bindings/media/media-bus-format.h
> > >>> new file mode 100644
> > >>> index 000000000000..60fc6e11dabc
> > >>> --- /dev/null
> > >>> +++ b/include/dt-bindings/media/media-bus-format.h
> > >>> @@ -0,0 +1,177 @@
> > >>> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> > >>> +/*
> > >>> + * Media Bus API header
> > >>> + *
> > >>> + * Copyright (C) 2009, Guennadi Liakhovetski
> > >>> +<g.liakhovetski@gmx.de>
> > >>> + *
> > >>> + * This program is free software; you can redistribute it and/or
> > >>> +modify
> > >>> + * it under the terms of the GNU General Public License version 2
> > >>> +as
> > >>> + * published by the Free Software Foundation.
> > >>
> > >> That's not true. Your SPDX tells something entirely different.
> > >>
> > >
> > > Thank you - I'll see how to fix it.
> > >
> > >> Anyway, you did not explain why you need to copy anything anywhere.
> > >>
> > >> Specifically, random hex values *are not bindings*.
> > >>
> > >
> > > The same media bus format values are being used by the reference
> > > driver in patch #9. And, as far as I know, we cannot use headers from
> > > Linux API headers directly (at least I
> >
> > I don't understand what does it mean. You can use in your driver whatever
> > headers you wish, I don't care about them.
> >
> >
> > noticed the same pattern in ../dt-bindings/sdtv-standarts.h for instance).
> > What would be the best approach to reusing the same defines on DT and
> > driver sides from your point of view? Symlink maybe?
> > >
> >
> > Wrap your messages to match mailing list discussion style. There are no
> > defines used in DT. If there are, show me them in *THIS* or other
> > *upstreamed* (being upstreamed) patchset.
> >
>
> Sorry, I didn't explain properly what I'm trying to achieve. I need to
> create a DT node property that represents video signal format, one of
> MEDIA_BUS_FMT_* from include/uapi/linux/media-bus-format.h. It would be
> nice to reuse the same symbolic values in the device tree. What is the
> best approach here? Should I create a separate header in
> include/dt-bindings with the same or similar (to avoid multiple
> definition errors) defines, or is it better to create a symlink to
> media-bus-format.h like include/dt-bindings/linux-event-codes.h?
Isn't there already a property for this, described in
Documentation/devicetree/bindings/media/xilinx/video.txt
?
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v7 1/2] dt-bindings: dma: Add Loongson-1 APB DMA
From: Conor Dooley @ 2024-03-29 15:40 UTC (permalink / raw)
To: keguang.zhang
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Huacai Chen, linux-mips, dmaengine, devicetree, linux-kernel
In-Reply-To: <20240329-loongson1-dma-v7-1-37db58608de5@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2251 bytes --]
On Fri, Mar 29, 2024 at 07:26:57PM +0800, Keguang Zhang via B4 Relay wrote:
> From: Keguang Zhang <keguang.zhang@gmail.com>
>
> Add devicetree binding document for Loongson-1 APB DMA.
>
> Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com>
> ---
> Changes in v7:
> - Change the comptible to 'loongson,ls1*-apbdma' (suggested by Huacai Chen)
> - Update the title and description part accordingly
> - Rename the file to loongson,ls1b-apbdma.yaml
> - Add a compatible string for LS1A
> - Delete minItems of 'interrupts'
> - Change patterns of 'interrupt-names' to const
>
> Changes in v6:
> - Change the compatible to the fallback
> - Some minor fixes
>
> Changes in v5:
> - A newly added patch
> ---
> .../bindings/dma/loongson,ls1b-apbdma.yaml | 65 ++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/loongson,ls1b-apbdma.yaml b/Documentation/devicetree/bindings/dma/loongson,ls1b-apbdma.yaml
> new file mode 100644
> index 000000000000..449da9fc2de1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/loongson,ls1b-apbdma.yaml
> @@ -0,0 +1,65 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/loongson,ls1b-apbdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson-1 APB DMA Controller
> +
> +maintainers:
> + - Keguang Zhang <keguang.zhang@gmail.com>
> +
> +description:
> + Loongson-1 APB DMA controller provides 3 independent channels for
> + peripherals such as NAND, audio playback and capture.
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: loongson,ls1b-apbdma
> + - items:
> + - enum:
> + - loongson,ls1a-apbdma
> + - loongson,ls1c-apbdma
> + - const: loongson,ls1b-apbdma
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + description: Each channel has a dedicated interrupt line.
If there's a respin, make this an items list. If you do, you can then
drop the maxItems and description. Ideally with that change made,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [RFC PATCH 1/2] dt-bindings: connector: Add gpio-usb-c-connector compatible
From: Conor Dooley @ 2024-03-29 15:37 UTC (permalink / raw)
To: Krishna Kurapati
Cc: Krzysztof Kozlowski, Rob Herring, Greg Kroah-Hartman,
Conor Dooley, Dmitry Baryshkov, Miquel Raynal, Guenter Roeck,
Bjorn Helgaas, Kyle Tso, Fabrice Gasnier, Heikki Krogerus,
u.kleine-koenig, AngeloGioacchino Del Regno, devicetree,
linux-usb, linux-kernel, quic_ppratap, quic_jackp
In-Reply-To: <20240329071948.3101882-2-quic_kriskura@quicinc.com>
[-- Attachment #1: Type: text/plain, Size: 1594 bytes --]
On Fri, Mar 29, 2024 at 12:49:47PM +0530, Krishna Kurapati wrote:
> QDU1000 IDP [1] has a Type-c connector and supports USB 3.0.
> However it relies on usb-conn-gpio driver to read the vbus and id
> gpio's and provide role switch. However the driver currently has
> only gpio-b-connector compatible present in ID table. Adding that
> in DT would mean that the device supports Type-B connector and not
> Type-c connector.
>
> Add gpio-usb-c-connector compatible to the driver to support such
> cases.
This is not a driver. Bindings commit messages should talk about the
hardware they're supporting, not about drivers.
>
> [1]: https://lore.kernel.org/all/20240319091020.15137-3-quic_kbajaj@quicinc.com/
>
> Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
> ---
> Documentation/devicetree/bindings/connector/usb-connector.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml b/Documentation/devicetree/bindings/connector/usb-connector.yaml
> index fb216ce68bb3..2af27793c639 100644
> --- a/Documentation/devicetree/bindings/connector/usb-connector.yaml
> +++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml
> @@ -30,6 +30,9 @@ properties:
> - const: samsung,usb-connector-11pin
> - const: usb-b-connector
>
> + - items:
> + - const: gpio-usb-c-connector
This is over complicated, just needs to be "- const: gpio-usb-c-connector"
Thanks,
Conor.
> +
> reg:
> maxItems: 1
>
> --
> 2.34.1
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v1 1/3] dt-bindings: phy: Add i.MX8Q HSIO SerDes PHY binding
From: Conor Dooley @ 2024-03-29 15:34 UTC (permalink / raw)
To: Richard Zhu
Cc: vkoul, kishon, robh+dt, krzysztof.kozlowski+dt, conor+dt,
frank.li, linux-phy, devicetree, linux-arm-kernel, linux-kernel,
kernel, linux-imx
In-Reply-To: <1711699790-16494-2-git-send-email-hongxing.zhu@nxp.com>
[-- Attachment #1: Type: text/plain, Size: 5724 bytes --]
On Fri, Mar 29, 2024 at 04:09:48PM +0800, Richard Zhu wrote:
> Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding.
> - Use the controller ID to specify which controller is binded to the
> PHY.
> - Introduce one HSIO configuration, mandatory required to set
> "PCIE_AB_SELECT" and "PHY_X1_EPCS_SEL" during the initialization.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
> .../bindings/phy/fsl,imx8q-hsio.yaml | 143 ++++++++++++++++++
> 1 file changed, 143 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8q-hsio.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8q-hsio.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8q-hsio.yaml
> new file mode 100644
> index 000000000000..506551d4d94a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/fsl,imx8q-hsio.yaml
> @@ -0,0 +1,143 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/fsl,imx8q-hsio.yaml#
Why doesn't the filename match a compatible?
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8Q SoC series HSIO SERDES PHY
> +
> +maintainers:
> + - Richard Zhu <hongxing.zhu@nxp.com>
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx8qxp-serdes
> + - fsl,imx8qm-serdes
> + reg:
> + minItems: 4
> + maxItems: 4
> +
> + "#phy-cells":
> + const: 3
> + description: |
> + The first number defines the ID of the PHY contained in the HSIO macro.
> + The second defines controller ID binded to the PHY. The third defines the
> + HSIO configuratons refer to the different use cases. They are defined in
> + dt-bindings/phy/phy-imx8-pcie.h
> +
> + reg-names:
> + items:
> + - const: reg
> + - const: phy
> + - const: ctrl
> + - const: misc
> +
> + clocks:
> + minItems: 5
> + maxItems: 14
> +
> + clock-names:
> + minItems: 5
> + maxItems: 14
> +
> + fsl,refclk-pad-mode:
> + description: |
> + Specifies the mode of the refclk pad used. It can be UNUSED(PHY
> + refclock is derived from SoC internal source), INPUT(PHY refclock
> + is provided externally via the refclk pad) or OUTPUT(PHY refclock
> + is derived from SoC internal source and provided on the refclk pad).
> + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants
> + to be used.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [ 0, 1, 2 ]
Why do we need numbers and a header here at all? The enum should be an
enum of strings input, output & unused. Oh and "unused" can just be
dropped, and not having the property at all would mean "unused".
> +
> + power-domains:
> + description: |
> + i.MX8Q HSIO SerDes power domains. i.MX8QXP has one SerDes power domains.
> + And i.MX8QM has two.
The text description here can go, your constrains communicate this.
> + minItems: 1
> + maxItems: 2
> +
> +required:
> + - compatible
> + - reg
> + - "#phy-cells"
> + - clocks
> + - clock-names
> + - fsl,refclk-pad-mode
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8qxp-serdes
> + then:
> + properties:
> + clock-names:
> + items:
> + - const: apb_pclk0
> + - const: pclk0
Why would you have different ordering for the two devices?
> + - const: phy0_crr
> + - const: ctl0_crr
> + - const: misc_crr
> + power-domains:
> + minItems: 1
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8qm-serdes
> + then:
> + properties:
> + clock-names:
> + items:
> + - const: pclk0
> + - const: pclk1
> + - const: apb_pclk0
> + - const: apb_pclk1
> + - const: pclk2
> + - const: epcs_tx
> + - const: epcs_rx
> + - const: apb_pclk2
> + - const: phy0_crr
> + - const: phy1_crr
> + - const: ctl0_crr
> + - const: ctl1_crr
> + - const: ctl2_crr
> + - const: misc_crr
> + power-domains:
> + minItems: 2
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8-clock.h>
> + #include <dt-bindings/clock/imx8-lpcg.h>
> + #include <dt-bindings/firmware/imx/rsrc.h>
> + #include <dt-bindings/phy/phy-imx8-pcie.h>
> +
> + serdes: phy@5f1a0000 {
Drop the unused label please.
> + compatible = "fsl,imx8qxp-serdes";
> + reg = <0x5f1a0000 0x10000>,
> + <0x5f120000 0x10000>,
> + <0x5f140000 0x10000>,
> + <0x5f160000 0x10000>;
> + reg-names = "reg", "phy", "ctrl", "misc";
> + clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>,
> + <&phyx1_lpcg IMX_LPCG_CLK_4>,
> + <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,
> + <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,
> + <&misc_crr5_lpcg IMX_LPCG_CLK_4>;
> + clock-names = "apb_pclk0", "pclk0", "phy0_crr", "ctl0_crr",
> + "misc_crr";
> + power-domains = <&pd IMX_SC_R_SERDES_1>;
> + #phy-cells = <3>;
> + status = "disabled";
Drop this status.
Cheers,
Conor.
> + };
> +...
> --
> 2.37.1
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* [PATCH v10 1/3] dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC
From: Mrinmay Sarkar @ 2024-03-29 15:21 UTC (permalink / raw)
To: andersson, krzysztof.kozlowski+dt, conor+dt, konrad.dybcio,
manivannan.sadhasivam
Cc: quic_shazhuss, quic_nitegupt, quic_ramkri, quic_nayiluri,
quic_krichai, quic_vbadigan, quic_schintav, Mrinmay Sarkar,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Rob Herring, linux-pci, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <1711725718-6362-1-git-send-email-quic_msarkar@quicinc.com>
Add devicetree bindings support for SA8775P SoC. It has DMA register
space and dma interrupt to support HDMA.
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../devicetree/bindings/pci/qcom,pcie-ep.yaml | 64 +++++++++++++++++++++-
1 file changed, 62 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index a223ce0..46802f7 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -13,6 +13,7 @@ properties:
compatible:
oneOf:
- enum:
+ - qcom,sa8775p-pcie-ep
- qcom,sdx55-pcie-ep
- qcom,sm8450-pcie-ep
- items:
@@ -20,6 +21,7 @@ properties:
- const: qcom,sdx55-pcie-ep
reg:
+ minItems: 6
items:
- description: Qualcomm-specific PARF configuration registers
- description: DesignWare PCIe registers
@@ -27,8 +29,10 @@ properties:
- description: Address Translation Unit (ATU) registers
- description: Memory region used to map remote RC address space
- description: BAR memory region
+ - description: DMA register space
reg-names:
+ minItems: 6
items:
- const: parf
- const: dbi
@@ -36,13 +40,14 @@ properties:
- const: atu
- const: addr_space
- const: mmio
+ - const: dma
clocks:
- minItems: 7
+ minItems: 5
maxItems: 8
clock-names:
- minItems: 7
+ minItems: 5
maxItems: 8
qcom,perst-regs:
@@ -57,14 +62,18 @@ properties:
- description: Perst separation enable offset
interrupts:
+ minItems: 2
items:
- description: PCIe Global interrupt
- description: PCIe Doorbell interrupt
+ - description: DMA interrupt
interrupt-names:
+ minItems: 2
items:
- const: global
- const: doorbell
+ - const: dma
reset-gpios:
description: GPIO used as PERST# input signal
@@ -125,6 +134,10 @@ allOf:
- qcom,sdx55-pcie-ep
then:
properties:
+ reg:
+ maxItems: 6
+ reg-names:
+ maxItems: 6
clocks:
items:
- description: PCIe Auxiliary clock
@@ -143,6 +156,10 @@ allOf:
- const: slave_q2a
- const: sleep
- const: ref
+ interrupts:
+ maxItems: 2
+ interrupt-names:
+ maxItems: 2
- if:
properties:
@@ -152,6 +169,10 @@ allOf:
- qcom,sm8450-pcie-ep
then:
properties:
+ reg:
+ maxItems: 6
+ reg-names:
+ maxItems: 6
clocks:
items:
- description: PCIe Auxiliary clock
@@ -172,6 +193,45 @@ allOf:
- const: ref
- const: ddrss_sf_tbu
- const: aggre_noc_axi
+ interrupts:
+ maxItems: 2
+ interrupt-names:
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sa8775p-pcie-ep
+ then:
+ properties:
+ reg:
+ minItems: 7
+ maxItems: 7
+ reg-names:
+ minItems: 7
+ maxItems: 7
+ clocks:
+ items:
+ - description: PCIe Auxiliary clock
+ - description: PCIe CFG AHB clock
+ - description: PCIe Master AXI clock
+ - description: PCIe Slave AXI clock
+ - description: PCIe Slave Q2A AXI clock
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg
+ - const: bus_master
+ - const: bus_slave
+ - const: slave_q2a
+ interrupts:
+ minItems: 3
+ maxItems: 3
+ interrupt-names:
+ minItems: 3
+ maxItems: 3
unevaluatedProperties: false
--
2.7.4
^ permalink raw reply related
* [PATCH v10 0/3] arm64: qcom: sa8775p: add support for EP PCIe
From: Mrinmay Sarkar @ 2024-03-29 15:21 UTC (permalink / raw)
To: andersson, krzysztof.kozlowski+dt, conor+dt, konrad.dybcio,
manivannan.sadhasivam
Cc: quic_shazhuss, quic_nitegupt, quic_ramkri, quic_nayiluri,
quic_krichai, quic_vbadigan, quic_schintav, Mrinmay Sarkar,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Bjorn Helgaas, linux-pci, linux-arm-msm, devicetree, linux-kernel
This series adds the relavent DT bindings, new compatible string,
and add EP PCIe node in dtsi file for ep pcie0 controller.
v9 -> v10:
- rebased on top of 6.9-rc1
- dropped MHI EPF driver patches as those are applied
- v9 link: https://lore.kernel.org/all/1701432377-16899-1-git-send-email-quic_msarkar@quicinc.com/
v8 -> v9:
- update author in "Add pci_epf_mhi_ prefix to the function" patch.
- add ack by and reviewed by tag in commit message.
v7 -> v8:
- Add new patch PCI: epf-mhi: Add "pci_epf_mhi_" prefix to the function
names
- Update PCI: epf-mhi: Add support for SA8775P patch on top of the new
patch and update commit message.
v6 -> v7:
- add reviewed by tag in commit message in all patches.
- update commit message in patch 2 as per comment.
- update reason for reusing PID in commit message.
v5 -> v6:
- update cover letter
v4 -> v5:
- add maxItems to the respective field to constrain io space and
interrupt in all variants.
v3 -> v4:
- add maxItems field in dt bindings
- update comment in patch2
- dropped PHY driver patch as it is already applied [1]
- update comment in EPF driver patch
- update commect in dtsi and add iommus instead of iommu-map
[1] https://lore.kernel.org/all/169804254205.383714.18423881810869732517.b4-ty@kernel.org/
v2 -> v3:
- removed if/then schemas, added minItems for reg,
reg-bnames, interrupt and interrupt-names instead.
- adding qcom,sa8775p-pcie-ep compitable for sa8775p
as we have some specific change to add.
- reusing sm8450's pcs_misc num table as it is same as sa8775p.
used appropriate namespace for pcs.
- remove const from sa8775p_header as kernel test robot
throwing some warnings due to this.
- remove fallback compatiable as we are adding compatiable for sa8775p.
v1 -> v2:
- update description for dma
- Reusing qcom,sdx55-pcie-ep compatibe so remove compaitable
for sa8775p
- sort the defines in phy header file and remove extra defines
- add const in return type pci_epf_header and remove MHI_EPF_USE_DMA
flag as hdma patch is not ready
- add fallback compatiable as qcom,sdx55-pcie-ep, add iommu property
Mrinmay Sarkar (3):
dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC
PCI: qcom-ep: Add support for SA8775P SOC
arm64: dts: qcom: sa8775p: Add ep pcie0 controller node
.../devicetree/bindings/pci/qcom,pcie-ep.yaml | 64 +++++++++++++++++++++-
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 46 ++++++++++++++++
drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
3 files changed, 109 insertions(+), 2 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH v10 3/3] arm64: dts: qcom: sa8775p: Add ep pcie0 controller node
From: Mrinmay Sarkar @ 2024-03-29 15:21 UTC (permalink / raw)
To: andersson, krzysztof.kozlowski+dt, conor+dt, konrad.dybcio,
manivannan.sadhasivam
Cc: quic_shazhuss, quic_nitegupt, quic_ramkri, quic_nayiluri,
quic_krichai, quic_vbadigan, quic_schintav, Mrinmay Sarkar,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Rob Herring, linux-pci, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <1711725718-6362-1-git-send-email-quic_msarkar@quicinc.com>
Add ep pcie dtsi node for pcie0 controller found on sa8775p platform.
It supports gen4 and x2 link width. Limiting the speed to Gen3 due to
stability issues.
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 46 +++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 231cea1..d9802027 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -3679,6 +3679,52 @@
status = "disabled";
};
+ pcie0_ep: pcie-ep@1c00000 {
+ compatible = "qcom,sa8775p-pcie-ep";
+ reg = <0x0 0x01c00000 0x0 0x3000>,
+ <0x0 0x40000000 0x0 0xf20>,
+ <0x0 0x40000f20 0x0 0xa8>,
+ <0x0 0x40001000 0x0 0x4000>,
+ <0x0 0x40200000 0x0 0x100000>,
+ <0x0 0x01c03000 0x0 0x1000>,
+ <0x0 0x40005000 0x0 0x2000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
+ "mmio", "dma";
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
+
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a";
+
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "global", "doorbell", "dma";
+
+ interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ iommus = <&pcie_smmu 0x0000 0x7f>;
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "core";
+ power-domains = <&gcc PCIE_0_GDSC>;
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+ max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
+ num-lanes = <2>;
+
+ status = "disabled";
+ };
+
pcie0_phy: phy@1c04000 {
compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
reg = <0x0 0x1c04000 0x0 0x2000>;
--
2.7.4
^ permalink raw reply related
* [PATCH v10 2/3] PCI: qcom-ep: Add support for SA8775P SOC
From: Mrinmay Sarkar @ 2024-03-29 15:21 UTC (permalink / raw)
To: andersson, krzysztof.kozlowski+dt, conor+dt, konrad.dybcio,
manivannan.sadhasivam
Cc: quic_shazhuss, quic_nitegupt, quic_ramkri, quic_nayiluri,
quic_krichai, quic_vbadigan, quic_schintav, Mrinmay Sarkar,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Rob Herring, linux-arm-msm, linux-pci, devicetree, linux-kernel
In-Reply-To: <1711725718-6362-1-git-send-email-quic_msarkar@quicinc.com>
Add support for SA8775P SoC to the Qualcomm PCIe Endpoint Controller
driver. Adding new compatible string as it has different set of clocks
compared to other SoCs.
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 36e5e80..45008e0 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -875,6 +875,7 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev)
}
static const struct of_device_id qcom_pcie_ep_match[] = {
+ { .compatible = "qcom,sa8775p-pcie-ep", },
{ .compatible = "qcom,sdx55-pcie-ep", },
{ .compatible = "qcom,sm8450-pcie-ep", },
{ }
--
2.7.4
^ permalink raw reply related
* Re: [PATCH net-next v6 13/17] net: pse-pd: Use regulator framework within PSE framework
From: Kory Maincent @ 2024-03-29 15:04 UTC (permalink / raw)
To: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Jonathan Corbet, Luis Chamberlain, Russ Weight,
Greg Kroah-Hartman, Rafael J. Wysocki, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Oleksij Rempel, Mark Brown,
Frank Rowand, Andrew Lunn, Heiner Kallweit, Russell King
Cc: Thomas Petazzoni, netdev, linux-kernel, linux-doc, devicetree,
Dent Project
In-Reply-To: <20240326-feature_poe-v6-13-c1011b6ea1cb@bootlin.com>
On Tue, 26 Mar 2024 15:04:50 +0100
Kory Maincent <kory.maincent@bootlin.com> wrote:
> From: Kory Maincent (Dent Project) <kory.maincent@bootlin.com>
>
> Integrate the regulator framework to the PSE framework for enhanced
> access to features such as voltage, power measurement, and limits, which
> are akin to regulators. Additionally, PSE features like port priorities
> could potentially enhance the regulator framework. Note that this
> integration introduces some implementation complexity, including wrapper
> callbacks, but the potential benefits make it worthwhile.
>
> Regulator are using enable counter with specific behavior.
> Two calls to regulator_disable will trigger kernel warnings.
> If the counter exceeds one, regulator_disable call won't disable the
> PSE PI. These behavior isn't suitable for PSE control.
> Added a boolean 'enabled' state to prevent multiple calls to
> regulator_enable/disable. These calls will only be called from PSE
> framework as it won't have any regulator children, therefore no mutex are
> needed to safeguards this boolean.
>
> regulator_get needs the consumer device pointer. Use PSE as regulator
> provider and consumer device until we have RJ45 ports represented in
> the Kernel.
Oleksij, could you verify this patch does not break pse_regulator driver?
Regards,
--
Köry Maincent, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH v3 0/4] dt-bindings: rtc: convert multiple devices to dtschema
From: Alexandre Belloni @ 2024-03-29 14:59 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Baruch Siach,
Javier Carrasco
Cc: linux-rtc, devicetree, linux-kernel, linux-arm-kernel,
Krzysztof Kozlowski
In-Reply-To: <20240326-rtc-yaml-v3-0-caa430ecace7@gmail.com>
On Tue, 26 Mar 2024 14:03:22 +0100, Javier Carrasco wrote:
> This series converts the following existing bindings to dtschema:
>
> - armada-380-rtc
> - alphascale,asm9260-rtc
> - digicolor-rtc (moved to trivial-rtc)
> - nxp,lpc1788-rtc
>
> [...]
Applied, thanks!
[1/4] dt-bindings: rtc: armada-380-rtc: convert to dtschema
https://git.kernel.org/abelloni/c/c3c50e7df39b
[2/4] dt-bindings: rtc: alphascale,asm9260-rtc: convert to dtschema
https://git.kernel.org/abelloni/c/432008d2f766
[3/4] dt-bindings: rtc: digicolor-rtc: move to trivial-rtc
https://git.kernel.org/abelloni/c/971e7303f472
[4/4] dt-bindings: rtc: nxp,lpc1788-rtc: convert to dtschema
https://git.kernel.org/abelloni/c/7918a220d210
Best regards,
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH net-next v6 17/17] net: pse-pd: Add TI TPS23881 PSE controller driver
From: Kory Maincent @ 2024-03-29 14:56 UTC (permalink / raw)
To: Andrew Lunn
Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Jonathan Corbet, Luis Chamberlain, Russ Weight,
Greg Kroah-Hartman, Rafael J. Wysocki, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Oleksij Rempel, Mark Brown,
Frank Rowand, Heiner Kallweit, Russell King, Thomas Petazzoni,
netdev, linux-kernel, linux-doc, devicetree, Dent Project
In-Reply-To: <6bbc6b86-3947-4679-ac0b-fde50129d0f6@lunn.ch>
On Thu, 28 Mar 2024 17:24:17 +0100
Andrew Lunn <andrew@lunn.ch> wrote:
> > +static int tps23881_flash_fw_part(struct i2c_client *client,
> > + const char *fw_name,
> > + const struct tps23881_fw_conf *fw_conf)
>
> Does the device actually have flash? Or is this just downloading to
> SRAM?
It is downloading to SRAM.
>
> > +{
> > + const struct firmware *fw = NULL;
> > + int i, ret;
> > +
> > + ret = request_firmware(&fw, fw_name, &client->dev);
> > + if (ret)
> > + return ret;
> > +
> > + dev_info(&client->dev, "Flashing %s\n", fw_name);
>
> If this is a one-time thing whenever there is a new firmware version
> dropped into /lib/firmware, this would be O.K. However, if this
> happens every boot, i would use dev_dbg().
Ok I will change to dev_dbg then.
Thanks!
Regards,
--
Köry Maincent, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH net-next v6 17/17] net: pse-pd: Add TI TPS23881 PSE controller driver
From: Kory Maincent @ 2024-03-29 14:55 UTC (permalink / raw)
To: Andrew Lunn
Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Jonathan Corbet, Luis Chamberlain, Russ Weight,
Greg Kroah-Hartman, Rafael J. Wysocki, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Oleksij Rempel, Mark Brown,
Frank Rowand, Heiner Kallweit, Russell King, Thomas Petazzoni,
netdev, linux-kernel, linux-doc, devicetree, Dent Project
In-Reply-To: <0cc9923f-2907-471e-81b0-2ca01a6e8c79@lunn.ch>
On Thu, 28 Mar 2024 17:17:43 +0100
Andrew Lunn <andrew@lunn.ch> wrote:
> > +
> > + /* Set operating mode */
> > + ret = i2c_smbus_write_word_data(client, TPS23881_REG_OP_MODE,
> > 0xaaaa);
>
> Could you add some #defines here? This is semiauto i think?
Yes
> > + /* Enable detection and classification */
> > + val = 0;
> > + for (i = 0; i < TPS23881_MAX_CHANS; i++) {
> > + if (!port_matrix[i].exist)
> > + continue;
> > +
> > + val |= BIT(port_matrix[i].lgcl_chan[0]) |
> > + BIT(port_matrix[i].lgcl_chan[0] + 4);
> > + if (port_matrix[i].is_4p)
> > + val |= BIT(port_matrix[i].lgcl_chan[1]) |
> > + BIT(port_matrix[i].lgcl_chan[1] + 4);
> > + }
> > + ret = i2c_smbus_write_word_data(client, TPS23881_REG_DET_CLA_EN,
> > 0xffff);
>
> This looks odd. You calculate val, and then don't use it?
Oh indeed, you are right! Thanks for spotting the issue.
Regards,
--
Köry Maincent, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH v4 5/5] dmaengine: imx-sdma: Add i2c dma support
From: Frank Li @ 2024-03-29 14:34 UTC (permalink / raw)
To: Vinod Koul, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Joy Zou
Cc: dmaengine, linux-arm-kernel, linux-kernel, devicetree, imx,
Frank Li, Robin Gong, Clark Wang, Daniel Baluta
In-Reply-To: <20240329-sdma_upstream-v4-0-daeb3067dea7@nxp.com>
From: Robin Gong <yibin.gong@nxp.com>
New sdma script (sdma-6q: v3.6, sdma-7d: v4.6) support i2c at imx8mp and
imx6ull. So add I2C dma support.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Acked-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Joy Zou <joy.zou@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/imx-sdma.c | 7 +++++++
include/linux/dma/imx-dma.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index f68ab34a3c880..1ab8a7d3a50dc 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -251,6 +251,8 @@ struct sdma_script_start_addrs {
s32 sai_2_mcu_addr;
s32 uart_2_mcu_rom_addr;
s32 uartsh_2_mcu_rom_addr;
+ s32 i2c_2_mcu_addr;
+ s32 mcu_2_i2c_addr;
/* End of v3 array */
s32 mcu_2_zqspi_addr;
/* End of v4 array */
@@ -1081,6 +1083,11 @@ static int sdma_get_pc(struct sdma_channel *sdmac,
per_2_emi = sdma->script_addrs->sai_2_mcu_addr;
emi_2_per = sdma->script_addrs->mcu_2_sai_addr;
break;
+ case IMX_DMATYPE_I2C:
+ per_2_emi = sdma->script_addrs->i2c_2_mcu_addr;
+ emi_2_per = sdma->script_addrs->mcu_2_i2c_addr;
+ sdmac->is_ram_script = true;
+ break;
case IMX_DMATYPE_HDMI:
emi_2_per = sdma->script_addrs->hdmi_dma_addr;
sdmac->is_ram_script = true;
diff --git a/include/linux/dma/imx-dma.h b/include/linux/dma/imx-dma.h
index cfec5f946e237..76a8de9ae1517 100644
--- a/include/linux/dma/imx-dma.h
+++ b/include/linux/dma/imx-dma.h
@@ -41,6 +41,7 @@ enum sdma_peripheral_type {
IMX_DMATYPE_SAI, /* SAI */
IMX_DMATYPE_MULTI_SAI, /* MULTI FIFOs For Audio */
IMX_DMATYPE_HDMI, /* HDMI Audio */
+ IMX_DMATYPE_I2C, /* I2C */
};
enum imx_dma_prio {
--
2.34.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox