* [PATCH v7 4/4] ASoc: dt-bindings: PCM6240: Add initial DT binding
From: Shenghao Ding @ 2024-03-31 2:18 UTC (permalink / raw)
To: linux-kernel
Cc: lgirdwood, broonie, robh+dt, krzysztof.kozlowski+dt, conor+dt,
linux-sound, devicetree, perex, tiwai, 13916275206, mohit.chawla,
soyer, jkhuang3, tiwai, pdjuandi, manisha.agrawal, s-hari, aviel,
hnagalla, praneeth, Baojun.Xu, Shenghao Ding, Rob Herring
In-Reply-To: <20240331021835.1470-1-shenghao-ding@ti.com>
PCM6240 family chips are popular among audio customers, in spite of only a
portion of the functionality of codec, such as ADC or DAC, and so on, for
different Specifications, range from Personal Electric to Automotive
Electric, even some professional fields. Yet their audio performance is far
superior to the codec's, and cost is lower than codec, and much easier to
program than codec.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shenghao Ding <shenghao-ding@ti.com>
---
Change in v7:
- Rewrite the subject to match something similar to other commits.
- And none of them are compatible with something.
- minItems, then maxItems.
- Drop reset-gpios description
- Remove the repeated reg descriptions and reg constraints.
- Drop redundant spaces.
- Add missing line breaks between blocks and additionalProperties.
- Correct compatibility issue on adc6120 and pcm6240.
- All these chips have only a portion of the functionality of codec,
such as ADC or DAC, and so on, but their audio performance is far
superior to the codec's, and cost is lower than codec, and much easier
to program than codec. Simply one or two register settings can enable
them to work. Init for these chips are hardware reset or software reset.
As to some audio filter params for internal filters, it is up to the
special user cases, which can be saved into the bin file. The default
value also can work well.
- Add blank line before reg.
- remove unneeded items and if branches.
- Add missing compatible devices, such as adc6120, etc.
- Add necessary people into the list for DTS review
- correct misaligned.
- simplify the compatibility
- remove sound-name-prefix and revert back
- Add review information
---
.../devicetree/bindings/sound/ti,pcm6240.yaml | 177 ++++++++++++++++++
1 file changed, 177 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/ti,pcm6240.yaml
diff --git a/Documentation/devicetree/bindings/sound/ti,pcm6240.yaml b/Documentation/devicetree/bindings/sound/ti,pcm6240.yaml
new file mode 100644
index 000000000000..dd5b08e3d7a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ti,pcm6240.yaml
@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022 - 2024 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ti,pcm6240.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments PCM6240 Family Audio ADC/DAC
+
+maintainers:
+ - Shenghao Ding <shenghao-ding@ti.com>
+
+description: |
+ The PCM6240 Family is a big family of Audio ADC/DAC for
+ different Specifications, range from Personal Electric
+ to Automotive Electric, even some professional fields.
+
+ Specifications about the audio chip can be found at:
+ https://www.ti.com/lit/gpn/tlv320adc3120
+ https://www.ti.com/lit/gpn/tlv320adc5120
+ https://www.ti.com/lit/gpn/tlv320adc6120
+ https://www.ti.com/lit/gpn/dix4192
+ https://www.ti.com/lit/gpn/pcm1690
+ https://www.ti.com/lit/gpn/pcm3120-q1
+ https://www.ti.com/lit/gpn/pcm3140-q1
+ https://www.ti.com/lit/gpn/pcm5120-q1
+ https://www.ti.com/lit/gpn/pcm6120-q1
+ https://www.ti.com/lit/gpn/pcm6260-q1
+ https://www.ti.com/lit/gpn/pcm9211
+ https://www.ti.com/lit/gpn/pcmd3140
+ https://www.ti.com/lit/gpn/pcmd3180
+ https://www.ti.com/lit/gpn/taa5212
+ https://www.ti.com/lit/gpn/tad5212
+
+properties:
+ compatible:
+ description: |
+ ti,adc3120: Stereo-channel, 768-kHz, Burr-Brown™ audio analog-to-
+ digital converter (ADC) with 106-dB SNR.
+
+ ti,adc5120: 2-Channel, 768-kHz, Burr-Brown™ Audio ADC with 120-dB SNR.
+
+ ti,adc6120: Stereo-channel, 768-kHz, Burr-Brown™ audio analog-to-
+ digital converter (ADC) with 123-dB SNR.
+
+ ti,dix4192: 216-kHz digital audio converter with Quad-Channel In
+ and One-Channel Out.
+
+ ti,pcm1690: Automotive Catalog 113dB SNR 8-Channel Audio DAC with
+ Differential Outputs.
+
+ ti,pcm3120: Automotive, stereo, 106-dB SNR, 768-kHz, low-power
+ software-controlled audio ADC.
+
+ ti,pcm3140: Automotive, Quad-Channel, 768-kHz, Burr-Brown™ Audio ADC
+ with 106-dB SNR.
+
+ ti,pcm5120: Automotive, stereo, 120-dB SNR, 768-kHz, low-power
+ software-controlled audio ADC.
+
+ ti,pcm5140: Automotive, Quad-Channel, 768-kHz, Burr-Brown™ Audio ADC
+ with 120-dB SNR.
+
+ ti,pcm6120: Automotive, stereo, 123-dB SNR, 768-kHz, low-power
+ software-controlled audio ADC.
+
+ ti,pcm6140: Automotive, Quad-Channel, 768-kHz, Burr-Brown™ Audio ADC
+ with 123-dB SNR.
+
+ ti,pcm6240: Automotive 4-ch audio ADC with integrated programmable mic
+ bias, boost and input diagnostics.
+
+ ti,pcm6260: Automotive 6-ch audio ADC with integrated programmable mic
+ bias, boost and input diagnostics.
+
+ ti,pcm9211: 216-kHz digital audio converter With Stereo ADC and
+ Routing.
+
+ ti,pcmd3140: Four-channel PDM-input to TDM or I2S output converter.
+
+ ti,pcmd3180: Eight-channel pulse-density-modulation input to TDM or
+ I2S output converter.
+
+ ti,taa5212: Low-power high-performance stereo audio ADC with 118-dB
+ dynamic range.
+
+ ti,tad5212: Low-power stereo audio DAC with 120-dB dynamic range.
+ oneOf:
+ - items:
+ - enum:
+ - ti,adc3120
+ - ti,adc5120
+ - ti,pcm3120
+ - ti,pcm5120
+ - ti,pcm6120
+ - const: ti,adc6120
+ - items:
+ - enum:
+ - ti,pcmd512x
+ - ti,pcm9211
+ - ti,taa5212
+ - ti,tad5212
+ - const: ti,adc6120
+ - items:
+ - enum:
+ - ti,pcm3140
+ - ti,pcm5140
+ - ti,dix4192
+ - ti,pcm6140
+ - ti,pcm6260
+ - const: ti,pcm6240
+ - items:
+ - enum:
+ - ti,pcmd3140
+ - ti,pcmd3180
+ - ti,pcm1690
+ - ti,taa5412
+ - ti,tad5412
+ - const: ti,pcm6240
+ - enum:
+ - ti,adc6120
+ - ti,pcm6240
+
+ reg:
+ description:
+ I2C address, in multiple pcmdevices case, all the i2c address
+ aggregate as one Audio Device to support multiple audio slots.
+ minItems: 1
+ maxItems: 4
+
+ reset-gpios:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description:
+ Invalid only for ti,pcm1690 because of no INT pin.
+
+ '#sound-dai-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: dai-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,pcm1690
+ then:
+ properties:
+ interrupts: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ /* example for two devices with interrupt support */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pcm6240: audio-codec@48 {
+ compatible = "ti,pcm6240";
+ reg = <0x48>, /* primary-device */
+ <0x4b>; /* secondary-device */
+ #sound-dai-cells = <0>;
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <15>;
+ };
+ };
+...
--
2.34.1
^ permalink raw reply related
* [PATCH v7 3/4] ASoc: PCM6240: Add compile item for PCM6240 Family driver
From: Shenghao Ding @ 2024-03-31 2:18 UTC (permalink / raw)
To: linux-kernel
Cc: lgirdwood, broonie, robh+dt, krzysztof.kozlowski+dt, conor+dt,
linux-sound, devicetree, perex, tiwai, 13916275206, mohit.chawla,
soyer, jkhuang3, tiwai, pdjuandi, manisha.agrawal, s-hari, aviel,
hnagalla, praneeth, Baojun.Xu, Shenghao Ding
In-Reply-To: <20240331021835.1470-1-shenghao-ding@ti.com>
PCM6240 driver implements a flexible and configurable setting for register
and filter coefficients, to one, two or even multiple PCM6240 Family Audio
chips.
Signed-off-by: Shenghao Ding <shenghao-ding@ti.com>
---
Change in v7:
- All these chips have only a portion of the codec's functionality, such
as ADC or DAC, and so on, but their audio performance is far superior
to the codec's, and cost is lower than codec, and much easier to
program than codec.
---
sound/soc/codecs/Kconfig | 10 ++++++++++
sound/soc/codecs/Makefile | 2 ++
2 files changed, 12 insertions(+)
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index f78ea2f86fa6..0c35cdfd4a47 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -179,6 +179,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_PCM5102A
imply SND_SOC_PCM512x_I2C
imply SND_SOC_PCM512x_SPI
+ imply SND_SOC_PCM6240
imply SND_SOC_PEB2466
imply SND_SOC_RK3328
imply SND_SOC_RK817
@@ -1422,6 +1423,15 @@ config SND_SOC_PCM512x_SPI
select SND_SOC_PCM512x
select REGMAP_SPI
+config SND_SOC_PCM6240
+ tristate "Texas Instruments PCM6240 Family Audio chips based on I2C"
+ depends on I2C
+ help
+ Enable support for Texas Instruments PCM6240 Family Audio chips.
+ Note the PCM6240 driver implements a flexible and configurable
+ setting for register and filter coefficients, to one, two or
+ even multiple PCM6240 Family Audio chips.
+
config SND_SOC_PEB2466
tristate "Infineon PEB2466 quad PCM codec"
depends on SPI
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 7c075539dc47..5553155b843b 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -204,6 +204,7 @@ snd-soc-pcm5102a-objs := pcm5102a.o
snd-soc-pcm512x-objs := pcm512x.o
snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o
snd-soc-pcm512x-spi-objs := pcm512x-spi.o
+snd-soc-pcm6240-objs := pcm6240.o
snd-soc-peb2466-objs := peb2466.o
snd-soc-rk3328-objs := rk3328_codec.o
snd-soc-rk817-objs := rk817_codec.o
@@ -594,6 +595,7 @@ obj-$(CONFIG_SND_SOC_PCM5102A) += snd-soc-pcm5102a.o
obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o
obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o
obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o
+obj-$(CONFIG_SND_SOC_PCM6240) += snd-soc-pcm6240.o
obj-$(CONFIG_SND_SOC_PEB2466) += snd-soc-peb2466.o
obj-$(CONFIG_SND_SOC_RK3328) += snd-soc-rk3328.o
obj-$(CONFIG_SND_SOC_RK817) += snd-soc-rk817.o
--
2.34.1
^ permalink raw reply related
* Re: [PATCH 5/5] cadence-xspi: Add xfer capabilities
From: kernel test robot @ 2024-03-31 3:25 UTC (permalink / raw)
To: Witold Sadowski, linux-kernel, linux-spi, devicetree
Cc: oe-kbuild-all, broonie, robh, krzysztof.kozlowski+dt, conor+dt,
pthombar, Witold Sadowski
In-Reply-To: <20240329194849.25554-6-wsadowski@marvell.com>
Hi Witold,
kernel test robot noticed the following build warnings:
[auto build test WARNING on broonie-spi/for-next]
[also build test WARNING on linus/master v6.9-rc1 next-20240328]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Witold-Sadowski/spi-cadence-Add-new-bindings-documentation-for-Cadence-XSPI/20240330-035124
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
patch link: https://lore.kernel.org/r/20240329194849.25554-6-wsadowski%40marvell.com
patch subject: [PATCH 5/5] cadence-xspi: Add xfer capabilities
config: x86_64-randconfig-123-20240331 (https://download.01.org/0day-ci/archive/20240331/202403311133.jOI5kbg4-lkp@intel.com/config)
compiler: gcc-7 (Ubuntu 7.5.0-6ubuntu2) 7.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240331/202403311133.jOI5kbg4-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202403311133.jOI5kbg4-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/spi/spi-cadence-xspi.c: In function 'cdns_xspi_setup':
drivers/spi/spi-cadence-xspi.c:892:36: error: implicit declaration of function 'spi_master_get_devdata'; did you mean 'spi_mem_get_drvdata'? [-Werror=implicit-function-declaration]
struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(spi_dev->master);
^~~~~~~~~~~~~~~~~~~~~~
spi_mem_get_drvdata
drivers/spi/spi-cadence-xspi.c:892:66: error: 'struct spi_device' has no member named 'master'
struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(spi_dev->master);
^~
drivers/spi/spi-cadence-xspi.c: In function 'cdns_xspi_transfer_one_message_b0':
>> drivers/spi/spi-cadence-xspi.c:1029:36: warning: initialization makes pointer from integer without a cast [-Wint-conversion]
struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(master);
^~~~~~~~~~~~~~~~~~~~~~
>> drivers/spi/spi-cadence-xspi.c:1035:11: warning: initialization makes integer from pointer without a cast [-Wint-conversion]
int cs = spi->chip_select;
^~~
drivers/spi/spi-cadence-xspi.c: At top level:
drivers/spi/spi-cadence-xspi.c:1242:0: error: unterminated #ifdef
#ifdef CONFIG_OF
cc1: some warnings being treated as errors
vim +1029 drivers/spi/spi-cadence-xspi.c
1025
1026 int cdns_xspi_transfer_one_message_b0(struct spi_controller *master,
1027 struct spi_message *m)
1028 {
> 1029 struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(master);
1030 struct spi_device *spi = m->spi;
1031 struct spi_transfer *t = NULL;
1032
1033 const int max_len = XFER_QWORD_BYTECOUNT * XFER_QWORD_COUNT;
1034 int current_cycle_count;
> 1035 int cs = spi->chip_select;
1036 int cs_change = 0;
1037
1038 /* Enable xfer state machine */
1039 if (!cdns_xspi->xfer_in_progress) {
1040 u32 xfer_control = readl(cdns_xspi->xferbase + SPIX_XFER_FUNC_CTRL);
1041
1042 cdns_xspi->current_xfer_qword = 0;
1043 cdns_xspi->xfer_in_progress = true;
1044 xfer_control |= (XFER_RECEIVE_ENABLE |
1045 XFER_CLK_CAPTURE_POL |
1046 XFER_FUNC_START |
1047 XFER_SOFT_RESET |
1048 FIELD_PREP(XFER_CS_N_HOLD, (1 << cs)));
1049 xfer_control &= ~(XFER_FUNC_ENABLE | XFER_CLK_DRIVE_POL);
1050 writel(xfer_control, cdns_xspi->xferbase + SPIX_XFER_FUNC_CTRL);
1051 }
1052
1053 list_for_each_entry(t, &m->transfers, transfer_list) {
1054 u8 *txd = (u8 *) t->tx_buf;
1055 u8 *rxd = (u8 *) t->rx_buf;
1056 u8 data[10];
1057 u32 cmd_regs[6];
1058
1059 if (!txd)
1060 txd = data;
1061
1062 cdns_xspi->in_buffer = txd + 1;
1063 cdns_xspi->out_buffer = txd + 1;
1064
1065 while (t->len) {
1066
1067 current_cycle_count = t->len > max_len ? max_len : t->len;
1068
1069 if (current_cycle_count < 10) {
1070 cdns_xspi_prepare_generic(cs, txd, current_cycle_count,
1071 false, cmd_regs);
1072 cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
1073 if (cdns_xspi_stig_ready(cdns_xspi, true))
1074 return -EIO;
1075 } else {
1076 cdns_xspi_prepare_generic(cs, txd, 1, true, cmd_regs);
1077 cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
1078 cdns_xspi_prepare_transfer(cs, 1, current_cycle_count - 1,
1079 cmd_regs);
1080 cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
1081 if (cdns_xspi_sdma_ready(cdns_xspi, true))
1082 return -EIO;
1083 cdns_xspi_sdma_handle(cdns_xspi);
1084 if (cdns_xspi_stig_ready(cdns_xspi, true))
1085 return -EIO;
1086
1087 cdns_xspi->in_buffer += current_cycle_count;
1088 cdns_xspi->out_buffer += current_cycle_count;
1089 }
1090
1091 if (rxd) {
1092 int j;
1093
1094 for (j = 0; j < current_cycle_count / 8; j++)
1095 cdns_xspi_read_single_qword(cdns_xspi, &rxd);
1096 cdns_xspi_finish_read(cdns_xspi, &rxd, current_cycle_count);
1097 } else {
1098 cdns_xspi->current_xfer_qword += current_cycle_count /
1099 XFER_QWORD_BYTECOUNT;
1100 if (current_cycle_count % XFER_QWORD_BYTECOUNT)
1101 cdns_xspi->current_xfer_qword++;
1102
1103 cdns_xspi->current_xfer_qword %= XFER_QWORD_COUNT;
1104 }
1105 cs_change = t->cs_change;
1106 t->len -= current_cycle_count;
1107 }
1108 }
1109
1110 if (!cs_change) {
1111 u32 xfer_control = readl(cdns_xspi->xferbase + SPIX_XFER_FUNC_CTRL);
1112
1113 xfer_control &= ~(XFER_RECEIVE_ENABLE |
1114 XFER_SOFT_RESET);
1115 writel(xfer_control, cdns_xspi->xferbase + SPIX_XFER_FUNC_CTRL);
1116 cdns_xspi->xfer_in_progress = false;
1117 }
1118
1119 m->status = 0;
1120 spi_finalize_current_message(master);
1121
1122 return 0;
1123 }
1124
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* [PATCH v2 0/7] arm64: dts: qcom: fix description of the Type-C signals
From: Dmitry Baryshkov @ 2024-03-31 3:48 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
Rename the HS link between usb-c-connector and the DWC3 USB controller.
Add missing graph connection between the QMP PHY and DWC3 USB
controller.
Reported-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Changes in v2:
- Fixed other platforms in addition to sm8250 (Bryan)
- Link to v1: https://lore.kernel.org/r/20240322-typec-fix-sm8250-v1-0-1ac22b333ea9@linaro.org
---
Dmitry Baryshkov (7):
arm64: dts: qcom: sm8250: describe HS signals properly
arm64: dts: qcom: sm8250: add a link between DWC3 and QMP PHY
arm64: dts: qcom: sc8180x: switch USB+DP QMP PHYs to new bindings
arm64: dts: qcom: sc8180x: describe USB signals properly
arm64: dts: qcom: sc8280xp: describe USB signals properly
arm64: dts: qcom: x1e80100: describe USB signals properly
arm64: dts: qcom: sm8150-hdk: rename Type-C HS endpoints
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 8 +-
.../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 16 +-
arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 20 +--
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 164 ++++++++++-----------
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 20 +--
.../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 20 +--
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 54 ++++++-
arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 4 +-
.../boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 8 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++-
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 149 ++++++++++++++++++-
11 files changed, 340 insertions(+), 147 deletions(-)
---
base-commit: 13ee4a7161b6fd938aef6688ff43b163f6d83e37
change-id: 20240322-typec-fix-sm8250-33c47a03a056
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
^ permalink raw reply
* [PATCH v2 1/7] arm64: dts: qcom: sm8250: describe HS signals properly
From: Dmitry Baryshkov @ 2024-03-31 3:48 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240331-typec-fix-sm8250-v2-0-857acb6bd88e@linaro.org>
The OF graph should describe physical signals. There is no 'role switch'
signal between Type-C connector and the DWC3 USB controller. Instead
there is a HighSpeed signal lane between DWC3 controller and the USB-C
connector. Rename endpoints in accordance to that (this follows the
example lead by other plaforms, including QRB2210 RB1, QRB4210 RB2 and
all PMIC GLINK platforms).
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 8 ++++----
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index cd0db4f31d4a..44239d1e57e9 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -1356,8 +1356,8 @@ &usb_1_dwc3 {
usb-role-switch;
};
-&usb_1_role_switch_out {
- remote-endpoint = <&pm8150b_role_switch_in>;
+&usb_1_dwc3_hs_out {
+ remote-endpoint = <&pm8150b_hs_in>;
};
&usb_1_hsphy {
@@ -1465,8 +1465,8 @@ ports {
port@0 {
reg = <0>;
- pm8150b_role_switch_in: endpoint {
- remote-endpoint = <&usb_1_role_switch_out>;
+ pm8150b_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs_out>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi
index 2042020eb0dd..6cc0bcb40f1f 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi
@@ -659,8 +659,8 @@ ports {
port@0 {
reg = <0>;
- pm8150b_role_switch_in: endpoint {
- remote-endpoint = <&usb_1_role_switch_out>;
+ pm8150b_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs_out>;
};
};
};
@@ -723,8 +723,8 @@ &usb_1_hsphy {
status = "okay";
};
-&usb_1_role_switch_out {
- remote-endpoint = <&pm8150b_role_switch_in>;
+&usb_1_dwc3_hs_out {
+ remote-endpoint = <&pm8150b_hs_in>;
};
&ufs_mem_hc {
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 7f2333c9d17d..440bbb89bf8a 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -4196,7 +4196,7 @@ usb_1_dwc3: usb@a600000 {
phy-names = "usb2-phy", "usb3-phy";
port {
- usb_1_role_switch_out: endpoint {};
+ usb_1_dwc3_hs_out: endpoint {};
};
};
};
--
2.39.2
^ permalink raw reply related
* [PATCH v2 2/7] arm64: dts: qcom: sm8250: add a link between DWC3 and QMP PHY
From: Dmitry Baryshkov @ 2024-03-31 3:48 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240331-typec-fix-sm8250-v2-0-857acb6bd88e@linaro.org>
The SuperSpeed signals originate from the DWC3 host controller and then
are routed through the Combo QMP PHY, where they are multiplexed with
the DisplayPort signals. Add corresponding OF graph link.
Reported-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 440bbb89bf8a..cfc07dd9d0ec 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3917,6 +3917,10 @@ port@0 {
port@1 {
reg = <1>;
+
+ usb_1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss_out>;
+ };
};
port@2 {
@@ -4195,8 +4199,24 @@ usb_1_dwc3: usb@a600000 {
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
- port {
- usb_1_dwc3_hs_out: endpoint {};
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss_out: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+ };
+ };
};
};
};
--
2.39.2
^ permalink raw reply related
* [PATCH v2 3/7] arm64: dts: qcom: sc8180x: switch USB+DP QMP PHYs to new bindings
From: Dmitry Baryshkov @ 2024-03-31 3:48 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240331-typec-fix-sm8250-v2-0-857acb6bd88e@linaro.org>
To follow other Qualcomm platforms, update QMP USB+DP PHYs to use newer
bindings rather than old bindings which had PHYs as subdevices.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 122 ++++++++++++----------------------
1 file changed, 41 insertions(+), 81 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 32afc78d5b76..a4931b5ee86c 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8180x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
@@ -2472,28 +2473,25 @@ usb_sec_hsphy: phy@88e3000 {
status = "disabled";
};
- usb_prim_qmpphy: phy@88e9000 {
+ usb_prim_qmpphy: phy@88e8000 {
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
- reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x38>,
- <0 0x088ea000 0 0x40>;
- reg-names = "reg-base", "dp_com";
+ reg = <0 0x088e8000 0 0x3000>;
+
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "aux",
- "ref_clk_src",
"ref",
- "com_aux";
+ "com_aux",
+ "usb3_pipe";
+
resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>,
<&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
reset-names = "phy", "common";
#clock-cells = <1>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #phy-cells = <1>;
status = "disabled";
@@ -2507,59 +2505,38 @@ port@0 {
usb_prim_qmpphy_out: endpoint {};
};
+ port@1 {
+ reg = <1>;
+
+ usb_prim_qmpphy_usb_ss_in: endpoint {};
+ };
+
port@2 {
reg = <2>;
usb_prim_qmpphy_dp_in: endpoint {};
};
};
-
- usb_prim_ssphy: usb3-phy@88e9200 {
- reg = <0 0x088e9200 0 0x200>,
- <0 0x088e9400 0 0x200>,
- <0 0x088e9c00 0 0x218>,
- <0 0x088e9600 0 0x200>,
- <0 0x088e9800 0 0x200>,
- <0 0x088e9a00 0 0x100>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_prim_phy_pipe_clk_src";
- };
-
- usb_prim_dpphy: dp-phy@88ea200 {
- reg = <0 0x088ea200 0 0x200>,
- <0 0x088ea400 0 0x200>,
- <0 0x088eaa00 0 0x200>,
- <0 0x088ea600 0 0x200>,
- <0 0x088ea800 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
};
usb_sec_qmpphy: phy@88ee000 {
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
- reg = <0 0x088ee000 0 0x18c>,
- <0 0x088ed000 0 0x10>,
- <0 0x088ef000 0 0x40>;
- reg-names = "reg-base", "dp_com";
+ reg = <0 0x088ed000 0 0x3000>;
+
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "aux",
- "ref_clk_src",
"ref",
- "com_aux";
+ "com_aux",
+ "usb3_pipe";
resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>,
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
#clock-cells = <1>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #phy-cells = <1>;
status = "disabled";
@@ -2573,37 +2550,18 @@ port@0 {
usb_sec_qmpphy_out: endpoint {};
};
+ port@1 {
+ reg = <1>;
+
+ usb_sec_qmpphy_usb_ss_in: endpoint {};
+ };
+
port@2 {
reg = <2>;
usb_sec_qmpphy_dp_in: endpoint {};
};
};
-
- usb_sec_ssphy: usb3-phy@88e9200 {
- reg = <0 0x088ee200 0 0x200>,
- <0 0x088ee400 0 0x200>,
- <0 0x088eec00 0 0x218>,
- <0 0x088ee600 0 0x200>,
- <0 0x088ee800 0 0x200>,
- <0 0x088eea00 0 0x100>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_sec_phy_pipe_clk_src";
- };
-
- usb_sec_dpphy: dp-phy@88ef200 {
- reg = <0 0x088ef200 0 0x200>,
- <0 0x088ef400 0 0x200>,
- <0 0x088efa00 0 0x200>,
- <0 0x088ef600 0 0x200>,
- <0 0x088ef800 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- clock-output-names = "qmp_dptx1_phy_pll_link_clk",
- "qmp_dptx1_phy_pll_vco_div_clk";
- };
};
system-cache-controller@9200000 {
@@ -2672,7 +2630,7 @@ usb_prim_dwc3: usb@a600000 {
iommus = <&apps_smmu 0x140 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>;
+ phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
port {
@@ -2729,7 +2687,7 @@ usb_sec_dwc3: usb@a800000 {
iommus = <&apps_smmu 0x160 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>;
+ phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
port {
@@ -3046,9 +3004,10 @@ mdss_dp0: displayport-controller@ae90000 {
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
- assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>;
+ assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
- phys = <&usb_prim_dpphy>;
+ phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
#sound-dai-cells = <0>;
@@ -3122,9 +3081,10 @@ mdss_dp1: displayport-controller@ae98000 {
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
- assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>;
+ assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
- phys = <&usb_sec_dpphy>;
+ phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
#sound-dai-cells = <0>;
@@ -3268,10 +3228,10 @@ dispcc: clock-controller@af00000 {
reg = <0 0x0af00000 0 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
- <&usb_prim_dpphy 0>,
- <&usb_prim_dpphy 1>,
- <&usb_sec_dpphy 0>,
- <&usb_sec_dpphy 1>,
+ <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
+ <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&edp_phy 0>,
<&edp_phy 1>;
clock-names = "bi_tcxo",
--
2.39.2
^ permalink raw reply related
* [PATCH v2 4/7] arm64: dts: qcom: sc8180x: describe USB signals properly
From: Dmitry Baryshkov @ 2024-03-31 3:48 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240331-typec-fix-sm8250-v2-0-857acb6bd88e@linaro.org>
Follow example of other platforms. Rename HS graph nodes to contain
'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 16 ++++----
arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 20 +++++-----
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 46 +++++++++++++++++++---
3 files changed, 58 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
index 6f2e1c732ed3..93846ff42606 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
@@ -66,7 +66,7 @@ port@0 {
reg = <0>;
pmic_glink_con0_hs: endpoint {
- remote-endpoint = <&usb_prim_role_switch>;
+ remote-endpoint = <&usb_prim_dwc3_hs>;
};
};
@@ -101,7 +101,7 @@ port@0 {
reg = <0>;
pmic_glink_con1_hs: endpoint {
- remote-endpoint = <&usb_sec_role_switch>;
+ remote-endpoint = <&usb_sec_dwc3_hs>;
};
};
@@ -580,6 +580,10 @@ &usb_prim_dwc3 {
dr_mode = "host";
};
+&usb_prim_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con0_hs>;
+};
+
&usb_prim_qmpphy_dp_in {
remote-endpoint = <&mdss_dp0_out>;
};
@@ -588,8 +592,8 @@ &usb_prim_qmpphy_out {
remote-endpoint = <&pmic_glink_con0_ss>;
};
-&usb_prim_role_switch {
- remote-endpoint = <&pmic_glink_con0_hs>;
+&usb_sec_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con1_hs>;
};
&usb_sec_hsphy {
@@ -617,10 +621,6 @@ &usb_sec_qmpphy_out {
remote-endpoint = <&pmic_glink_con1_ss>;
};
-&usb_sec_role_switch {
- remote-endpoint = <&pmic_glink_con1_hs>;
-};
-
&usb_sec {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
index bfee60c93ccc..65d923497a05 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
@@ -71,7 +71,7 @@ port@0 {
reg = <0>;
pmic_glink_con0_hs: endpoint {
- remote-endpoint = <&usb_prim_role_switch>;
+ remote-endpoint = <&usb_prim_dwc3_hs>;
};
};
@@ -106,7 +106,7 @@ port@0 {
reg = <0>;
pmic_glink_con1_hs: endpoint {
- remote-endpoint = <&usb_sec_role_switch>;
+ remote-endpoint = <&usb_sec_dwc3_hs>;
};
};
@@ -648,6 +648,10 @@ &usb_prim_dwc3 {
dr_mode = "host";
};
+&usb_prim_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con0_hs>;
+};
+
&usb_prim_qmpphy_dp_in {
remote-endpoint = <&mdss_dp0_out>;
};
@@ -656,10 +660,6 @@ &usb_prim_qmpphy_out {
remote-endpoint = <&pmic_glink_con0_ss>;
};
-&usb_prim_role_switch {
- remote-endpoint = <&pmic_glink_con0_hs>;
-};
-
&usb_sec_hsphy {
vdda-pll-supply = <&vreg_l5e_0p88>;
vdda18-supply = <&vreg_l12a_1p8>;
@@ -685,10 +685,6 @@ &usb_sec_qmpphy_out {
remote-endpoint = <&pmic_glink_con1_ss>;
};
-&usb_sec_role_switch {
- remote-endpoint = <&pmic_glink_con1_hs>;
-};
-
&usb_sec {
status = "okay";
};
@@ -697,6 +693,10 @@ &usb_sec_dwc3 {
dr_mode = "host";
};
+&usb_sec_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con1_hs>;
+};
+
&wifi {
memory-region = <&wlan_mem>;
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index a4931b5ee86c..59bb844ed432 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -2508,7 +2508,9 @@ port@0 {
port@1 {
reg = <1>;
- usb_prim_qmpphy_usb_ss_in: endpoint {};
+ usb_prim_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_prim_dwc3_ss>;
+ };
};
port@2 {
@@ -2553,7 +2555,9 @@ port@0 {
port@1 {
reg = <1>;
- usb_sec_qmpphy_usb_ss_in: endpoint {};
+ usb_sec_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_sec_dwc3_ss>;
+ };
};
port@2 {
@@ -2633,8 +2637,23 @@ usb_prim_dwc3: usb@a600000 {
phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
- port {
- usb_prim_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_prim_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_prim_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -2690,8 +2709,23 @@ usb_sec_dwc3: usb@a800000 {
phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
- port {
- usb_sec_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_sec_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_sec_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>;
+ };
};
};
};
--
2.39.2
^ permalink raw reply related
* [PATCH v2 5/7] arm64: dts: qcom: sc8280xp: describe USB signals properly
From: Dmitry Baryshkov @ 2024-03-31 3:48 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240331-typec-fix-sm8250-v2-0-857acb6bd88e@linaro.org>
Follow example of other platforms. Rename HS graph nodes to contain
'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 20 ++++----
.../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 20 ++++----
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 54 ++++++++++++++++++++--
3 files changed, 70 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index 41215567b3ae..a2627ab4db9a 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -56,7 +56,7 @@ port@0 {
reg = <0>;
pmic_glink_con0_hs: endpoint {
- remote-endpoint = <&usb_0_role_switch>;
+ remote-endpoint = <&usb_0_dwc3_hs>;
};
};
@@ -91,7 +91,7 @@ port@0 {
reg = <0>;
pmic_glink_con1_hs: endpoint {
- remote-endpoint = <&usb_1_role_switch>;
+ remote-endpoint = <&usb_1_dwc3_hs>;
};
};
@@ -675,6 +675,10 @@ &usb_0_dwc3 {
dr_mode = "host";
};
+&usb_0_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con0_hs>;
+};
+
&usb_0_hsphy {
vdda-pll-supply = <&vreg_l9d>;
vdda18-supply = <&vreg_l1c>;
@@ -700,10 +704,6 @@ &usb_0_qmpphy_out {
remote-endpoint = <&pmic_glink_con0_ss>;
};
-&usb_0_role_switch {
- remote-endpoint = <&pmic_glink_con0_hs>;
-};
-
&usb_1 {
status = "okay";
};
@@ -712,6 +712,10 @@ &usb_1_dwc3 {
dr_mode = "host";
};
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con1_hs>;
+};
+
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l4b>;
vdda18-supply = <&vreg_l1c>;
@@ -737,10 +741,6 @@ &usb_1_qmpphy_out {
remote-endpoint = <&pmic_glink_con1_ss>;
};
-&usb_1_role_switch {
- remote-endpoint = <&pmic_glink_con1_hs>;
-};
-
&xo_board_clk {
clock-frequency = <38400000>;
};
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 15ae94c1602d..53252bb93d9e 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -115,7 +115,7 @@ port@0 {
reg = <0>;
pmic_glink_con0_hs: endpoint {
- remote-endpoint = <&usb_0_role_switch>;
+ remote-endpoint = <&usb_0_dwc3_hs>;
};
};
@@ -150,7 +150,7 @@ port@0 {
reg = <0>;
pmic_glink_con1_hs: endpoint {
- remote-endpoint = <&usb_1_role_switch>;
+ remote-endpoint = <&usb_1_dwc3_hs>;
};
};
@@ -1102,6 +1102,10 @@ &usb_0_dwc3 {
dr_mode = "host";
};
+&usb_0_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con0_hs>;
+};
+
&usb_0_hsphy {
vdda-pll-supply = <&vreg_l9d>;
vdda18-supply = <&vreg_l1c>;
@@ -1127,10 +1131,6 @@ &usb_0_qmpphy_out {
remote-endpoint = <&pmic_glink_con0_ss>;
};
-&usb_0_role_switch {
- remote-endpoint = <&pmic_glink_con0_hs>;
-};
-
&usb_1 {
status = "okay";
};
@@ -1139,6 +1139,10 @@ &usb_1_dwc3 {
dr_mode = "host";
};
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_con1_hs>;
+};
+
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l4b>;
vdda18-supply = <&vreg_l1c>;
@@ -1164,10 +1168,6 @@ &usb_1_qmpphy_out {
remote-endpoint = <&pmic_glink_con1_ss>;
};
-&usb_1_role_switch {
- remote-endpoint = <&pmic_glink_con1_hs>;
-};
-
&vamacro {
pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 9f6d98fbc28e..41caa8713cfd 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3164,6 +3164,14 @@ port@0 {
usb_0_qmpphy_out: endpoint {};
};
+ port@1 {
+ reg = <1>;
+
+ usb_0_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_0_dwc3_ss>;
+ };
+ };
+
port@2 {
reg = <2>;
@@ -3217,6 +3225,14 @@ port@0 {
usb_1_qmpphy_out: endpoint {};
};
+ port@1 {
+ reg = <1>;
+
+ usb_1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+ };
+ };
+
port@2 {
reg = <2>;
@@ -3420,8 +3436,23 @@ usb_0_dwc3: usb@a600000 {
phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
- port {
- usb_0_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_0_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_0_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_0_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -3482,8 +3513,23 @@ usb_1_dwc3: usb@a800000 {
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
- port {
- usb_1_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+ };
};
};
};
--
2.39.2
^ permalink raw reply related
* [PATCH v2 6/7] arm64: dts: qcom: x1e80100: describe USB signals properly
From: Dmitry Baryshkov @ 2024-03-31 3:48 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240331-typec-fix-sm8250-v2-0-857acb6bd88e@linaro.org>
Follow example of other platforms. Rename HS graph nodes to contain
'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 149 +++++++++++++++++++++++++++++++--
1 file changed, 141 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index f5a3b39ae70e..3213eccc3a3a 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -2543,6 +2543,33 @@ usb_1_ss0_qmpphy: phy@fd5000 {
#phy-cells = <1>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss0_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss0_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss0_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_ss0_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
};
usb_1_ss1_hsphy: phy@fd9000 {
@@ -2583,6 +2610,33 @@ usb_1_ss1_qmpphy: phy@fda000 {
#phy-cells = <1>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss1_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss1_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_ss1_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
};
usb_1_ss2_hsphy: phy@fde000 {
@@ -2623,6 +2677,33 @@ usb_1_ss2_qmpphy: phy@fdf000 {
#phy-cells = <1>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss2_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss2_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_ss2_dwc3_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_ss2_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
};
cnoc_main: interconnect@1500000 {
@@ -3445,8 +3526,23 @@ usb_1_ss2_dwc3: usb@a000000 {
dma-coherent;
- port {
- usb_1_ss2_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss2_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss2_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -3514,8 +3610,15 @@ usb_2_dwc3: usb@a200000 {
phy-names = "usb2-phy";
maximum-speed = "high-speed";
- port {
- usb_2_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_2_dwc3_hs: endpoint {
+ };
};
};
};
@@ -3590,8 +3693,23 @@ usb_1_ss0_dwc3: usb@a600000 {
dma-coherent;
- port {
- usb_1_ss0_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss0_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss0_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
+ };
};
};
};
@@ -3673,8 +3791,23 @@ usb_1_ss1_dwc3: usb@a800000 {
dma-coherent;
- port {
- usb_1_ss1_role_switch: endpoint {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_ss1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_ss1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
+ };
};
};
};
--
2.39.2
^ permalink raw reply related
* [PATCH v2 7/7] arm64: dts: qcom: sm8150-hdk: rename Type-C HS endpoints
From: Dmitry Baryshkov @ 2024-03-31 3:48 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss,
Dmitry Baryshkov
In-Reply-To: <20240331-typec-fix-sm8250-v2-0-857acb6bd88e@linaro.org>
Follow other Qualcomm platforms and rename pm8150b_role_switch_in to
pm8150_hs_in. Corresponding port is described as HS port rather than
role switching.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
index de670b407ef1..857ccc5de085 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
@@ -556,7 +556,7 @@ ports {
port@0 {
reg = <0>;
- pm8150b_role_switch_in: endpoint {
+ pm8150b_hs_in: endpoint {
remote-endpoint = <&usb_1_dwc3_hs>;
};
};
@@ -703,7 +703,7 @@ &usb_1_dwc3 {
};
&usb_1_dwc3_hs {
- remote-endpoint = <&pm8150b_role_switch_in>;
+ remote-endpoint = <&pm8150b_hs_in>;
};
&usb_1_dwc3_ss {
--
2.39.2
^ permalink raw reply related
* Re: [PATCH v2] dt-bindings: usb: qcom,pmic-typec: update example to follow connector schema
From: Greg Kroah-Hartman @ 2024-03-31 7:17 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Bryan O'Donoghue, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, linux-usb,
devicetree, linux-kernel, Luca Weiss
In-Reply-To: <20240331-typec-fix-example-v2-1-f56fffe4f37c@linaro.org>
On Sun, Mar 31, 2024 at 12:21:15AM +0200, Dmitry Baryshkov wrote:
> Update Qualcomm PMIC Type-C examples to follow the USB-C connector
> schema. The USB-C connector should have three ports (USB HS @0,
> SSTX/RX @1 and SBU @2 lanes). Reorder ports accordingly and add SBU port
> connected to the SBU mux (e.g. FSA4480).
>
> Fixes: 00bb478b829e ("dt-bindings: usb: Add Qualcomm PMIC Type-C")
> Reported-by: Luca Weiss <luca.weiss@fairphone.com>
> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> Update examples to follow usb-c-connector schema wrt. ports definitions.
> ---
Hi,
This is the friendly patch-bot of Greg Kroah-Hartman. You have sent him
a patch that has triggered this response. He used to manually respond
to these common problems, but in order to save his sanity (he kept
writing the same thing over and over, yet to different people), I was
created. Hopefully you will not take offence and will fix the problem
in your patch and resubmit it so that it can be accepted into the Linux
kernel tree.
You are receiving this message because of the following common error(s)
as indicated below:
- You have marked a patch with a "Fixes:" tag for a commit that is in an
older released kernel, yet you do not have a cc: stable line in the
signed-off-by area at all, which means that the patch will not be
applied to any older kernel releases. To properly fix this, please
follow the documented rules in the
Documentation/process/stable-kernel-rules.rst file for how to resolve
this.
If you wish to discuss this problem further, or you have questions about
how to resolve this issue, please feel free to respond to this email and
Greg will reply once he has dug out from the pending patches received
from other developers.
thanks,
greg k-h's patch email bot
^ permalink raw reply
* Re: [PATCH 4/5] driver: spi: cadence: Add ACPI support
From: kernel test robot @ 2024-03-31 7:35 UTC (permalink / raw)
To: Witold Sadowski, linux-kernel, linux-spi, devicetree
Cc: oe-kbuild-all, broonie, robh, krzysztof.kozlowski+dt, conor+dt,
pthombar, Piyush Malgujar, Witold Sadowski
In-Reply-To: <20240329194849.25554-5-wsadowski@marvell.com>
Hi Witold,
kernel test robot noticed the following build errors:
[auto build test ERROR on broonie-spi/for-next]
[also build test ERROR on linus/master v6.9-rc1 next-20240328]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Witold-Sadowski/spi-cadence-Add-new-bindings-documentation-for-Cadence-XSPI/20240330-035124
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
patch link: https://lore.kernel.org/r/20240329194849.25554-5-wsadowski%40marvell.com
patch subject: [PATCH 4/5] driver: spi: cadence: Add ACPI support
config: m68k-allmodconfig (https://download.01.org/0day-ci/archive/20240331/202403311503.5rYNyUzp-lkp@intel.com/config)
compiler: m68k-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240331/202403311503.5rYNyUzp-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202403311503.5rYNyUzp-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/spi/spi-cadence-xspi.c: In function 'mrvl_ioreadq':
drivers/spi/spi-cadence-xspi.c:535:14: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
535 | if (((uint64_t)buf % 8) == 0) {
| ^
drivers/spi/spi-cadence-xspi.c:537:36: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Werror=implicit-function-declaration]
537 | *buf64++ = readq(addr);
| ^~~~~
| readb
drivers/spi/spi-cadence-xspi.c: In function 'mrvl_iowriteq':
drivers/spi/spi-cadence-xspi.c:559:14: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
559 | if (((uint64_t)buf % 8) == 0) {
| ^
drivers/spi/spi-cadence-xspi.c:561:25: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration]
561 | writeq(*buf64++, addr);
| ^~~~~~
| writel
drivers/spi/spi-cadence-xspi.c: In function 'cdns_xspi_setup':
drivers/spi/spi-cadence-xspi.c:869:43: error: implicit declaration of function 'spi_master_get_devdata'; did you mean 'spi_mem_get_drvdata'? [-Werror=implicit-function-declaration]
869 | struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(spi_dev->master);
| ^~~~~~~~~~~~~~~~~~~~~~
| spi_mem_get_drvdata
drivers/spi/spi-cadence-xspi.c:869:73: error: 'struct spi_device' has no member named 'master'
869 | struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(spi_dev->master);
| ^~
drivers/spi/spi-cadence-xspi.c: At top level:
>> drivers/spi/spi-cadence-xspi.c:993: error: unterminated #ifdef
993 | #ifdef CONFIG_OF
|
cc1: some warnings being treated as errors
vim +993 drivers/spi/spi-cadence-xspi.c
986
987 static const struct acpi_device_id cdns_xspi_acpi_match[] = {
988 {"cdns,xspi-nor", 0},
989 {"mrvl,xspi-nor", 0},
990 {},
991 };
992 MODULE_DEVICE_TABLE(acpi, cdns_xspi_acpi_match);
> 993 #ifdef CONFIG_OF
994 static const struct of_device_id cdns_xspi_of_match[] = {
995 {
996 .compatible = "cdns,xspi-nor",
997 },
998 {
999 .compatible = "mrvl,xspi-nor",
1000 },
1001 { /* end of table */}
1002 };
1003 MODULE_DEVICE_TABLE(of, cdns_xspi_of_match);
1004
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH 2/5] spi: cadence: Add Marvell IP modification changes
From: kernel test robot @ 2024-03-31 7:46 UTC (permalink / raw)
To: Witold Sadowski, linux-kernel, linux-spi, devicetree
Cc: oe-kbuild-all, broonie, robh, krzysztof.kozlowski+dt, conor+dt,
pthombar, Witold Sadowski
In-Reply-To: <20240329194849.25554-3-wsadowski@marvell.com>
Hi Witold,
kernel test robot noticed the following build errors:
[auto build test ERROR on broonie-spi/for-next]
[also build test ERROR on linus/master v6.9-rc1 next-20240328]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Witold-Sadowski/spi-cadence-Add-new-bindings-documentation-for-Cadence-XSPI/20240330-035124
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
patch link: https://lore.kernel.org/r/20240329194849.25554-3-wsadowski%40marvell.com
patch subject: [PATCH 2/5] spi: cadence: Add Marvell IP modification changes
config: i386-randconfig-141-20240330 (https://download.01.org/0day-ci/archive/20240331/202403311540.oe0vVEdr-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240331/202403311540.oe0vVEdr-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202403311540.oe0vVEdr-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/spi/spi-cadence-xspi.c:531:15: error: call to undeclared function 'readq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
531 | *buf64++ = readq(addr);
| ^
drivers/spi/spi-cadence-xspi.c:534:10: error: call to undeclared function 'readq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
534 | tmp = readq(addr);
| ^
drivers/spi/spi-cadence-xspi.c:540:9: error: call to undeclared function 'readq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
540 | tmp = readq(addr);
| ^
>> drivers/spi/spi-cadence-xspi.c:555:4: error: call to undeclared function 'writeq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
555 | writeq(*buf64++, addr);
| ^
drivers/spi/spi-cadence-xspi.c:559:4: error: call to undeclared function 'writeq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
559 | writeq(tmp, addr);
| ^
drivers/spi/spi-cadence-xspi.c:565:3: error: call to undeclared function 'writeq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
565 | writeq(tmp, addr);
| ^
>> drivers/spi/spi-cadence-xspi.c:794:36: error: call to undeclared function 'spi_master_get_devdata'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
794 | struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(spi_dev->master);
| ^
drivers/spi/spi-cadence-xspi.c:794:36: note: did you mean 'spi_mem_get_drvdata'?
include/linux/spi/spi-mem.h:224:21: note: 'spi_mem_get_drvdata' declared here
224 | static inline void *spi_mem_get_drvdata(struct spi_mem *mem)
| ^
>> drivers/spi/spi-cadence-xspi.c:794:68: error: no member named 'master' in 'struct spi_device'
794 | struct cdns_xspi_dev *cdns_xspi = spi_master_get_devdata(spi_dev->master);
| ~~~~~~~ ^
8 errors generated.
vim +/readq +531 drivers/spi/spi-cadence-xspi.c
520
521 static void mrvl_ioreadq(void __iomem *addr, void *buf, int len)
522 {
523 int i = 0;
524 int rcount = len / 8;
525 int rcount_nf = len % 8;
526 uint64_t tmp;
527 uint64_t *buf64 = (uint64_t *)buf;
528
529 if (((uint64_t)buf % 8) == 0) {
530 for (i = 0; i < rcount; i++)
> 531 *buf64++ = readq(addr);
532 } else {
533 for (i = 0; i < rcount; i++) {
534 tmp = readq(addr);
535 memcpy(buf+(i*8), &tmp, 8);
536 }
537 }
538
539 if (rcount_nf != 0) {
540 tmp = readq(addr);
541 memcpy(buf+(i*8), &tmp, rcount_nf);
542 }
543 }
544
545 static void mrvl_iowriteq(void __iomem *addr, const void *buf, int len)
546 {
547 int i = 0;
548 int rcount = len / 8;
549 int rcount_nf = len % 8;
550 uint64_t tmp;
551 uint64_t *buf64 = (uint64_t *)buf;
552
553 if (((uint64_t)buf % 8) == 0) {
554 for (i = 0; i < rcount; i++)
> 555 writeq(*buf64++, addr);
556 } else {
557 for (i = 0; i < rcount; i++) {
558 memcpy(&tmp, buf+(i*8), 8);
559 writeq(tmp, addr);
560 }
561 }
562
563 if (rcount_nf != 0) {
564 memcpy(&tmp, buf+(i*8), rcount_nf);
565 writeq(tmp, addr);
566 }
567 }
568
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v7 4/4] ASoc: dt-bindings: PCM6240: Add initial DT binding
From: Krzysztof Kozlowski @ 2024-03-31 8:15 UTC (permalink / raw)
To: Shenghao Ding, linux-kernel
Cc: lgirdwood, broonie, robh+dt, krzysztof.kozlowski+dt, conor+dt,
linux-sound, devicetree, perex, tiwai, 13916275206, mohit.chawla,
soyer, jkhuang3, tiwai, pdjuandi, manisha.agrawal, s-hari, aviel,
hnagalla, praneeth, Baojun.Xu, Rob Herring
In-Reply-To: <20240331021835.1470-5-shenghao-ding@ti.com>
On 31/03/2024 04:18, Shenghao Ding wrote:
> PCM6240 family chips are popular among audio customers, in spite of only a
> portion of the functionality of codec, such as ADC or DAC, and so on, for
> different Specifications, range from Personal Electric to Automotive
> Electric, even some professional fields. Yet their audio performance is far
> superior to the codec's, and cost is lower than codec, and much easier to
> program than codec.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
>
> Signed-off-by: Shenghao Ding <shenghao-ding@ti.com>
>
> ---
> Change in v7:
> - Rewrite the subject to match something similar to other commits.
> - And none of them are compatible with something.
> - minItems, then maxItems.
> - Drop reset-gpios description
> - Remove the repeated reg descriptions and reg constraints.
> - Drop redundant spaces.
> - Add missing line breaks between blocks and additionalProperties.
> - Correct compatibility issue on adc6120 and pcm6240.
> - All these chips have only a portion of the functionality of codec,
> such as ADC or DAC, and so on, but their audio performance is far
> superior to the codec's, and cost is lower than codec, and much easier
> to program than codec. Simply one or two register settings can enable
> them to work. Init for these chips are hardware reset or software reset.
> As to some audio filter params for internal filters, it is up to the
> special user cases, which can be saved into the bin file. The default
> value also can work well.
> - Add blank line before reg.
> - remove unneeded items and if branches.
> - Add missing compatible devices, such as adc6120, etc.
> - Add necessary people into the list for DTS review
> - correct misaligned.
> - simplify the compatibility
> - remove sound-name-prefix and revert back
> - Add review information
All these changes in v7 and you still kept Rob's review? I think either
review was not given or your changelog is just incorrect.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v1 2/2] dt-bindings: clock: rockchip: Add support for clk input / output switch
From: Krzysztof Kozlowski @ 2024-03-31 8:24 UTC (permalink / raw)
To: Sugar Zhang, heiko
Cc: linux-rockchip, Conor Dooley, Krzysztof Kozlowski,
Michael Turquette, Rob Herring, Stephen Boyd, devicetree,
linux-arm-kernel, linux-clk, linux-kernel
In-Reply-To: <1711340191-69588-2-git-send-email-sugar.zhang@rock-chips.com>
On 25/03/2024 05:16, Sugar Zhang wrote:
> This patch add support switch for clk-bidirection which located
Please do not use "This commit/patch/change", but imperative mood. See
longer explanation here:
https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95
> at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
> and these config maybe located in many pieces of GRF,
> which hard to addressed in one single clk driver. so, we add
> this simple helper driver to address this situation.
>
> In order to simplify implement and usage, and also for safety
> clk usage (avoid high freq glitch), we set all clk out as disabled
> (which means Input default for clk-bidrection) in the pre-stage,
> such boot-loader or init by HW default. And then set a safety freq
> before enable clk-out, such as "assign-clock-rates" or clk_set_rate
> in drivers.
>
> e.g.
>
> 1. mclk{out,in}_sai0 define:
>
> mclkin_sai0: mclkin-sai0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <12288000>;
> clock-output-names = "mclk_sai0_from_io";
> };
>
> mclkout_sai0: mclkout-sai0@ff040070 {
> compatible = "rockchip,clk-out";
> reg = <0 0xff040070 0 0x4>;
> clocks = <&cru MCLK_SAI0_OUT2IO>;
> #clock-cells = <0>;
> clock-output-names = "mclk_sai0_to_io";
> rockchip,bit-shift = <4>;
> //example with PD if reg access needed
> power-domains = <&power RK3562_PD_VO>;
> };
>
> Note:
>
> clock-output-names of mclkin_sai0 should equal to strings in drivers. such as:
>
> drivers/clk/rockchip/clk-rk3562.c:
> PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" };
>
> 2. mclkout_sai0 usage:
>
> &ext_codec {
> clocks = <&mclkout_sai0>;
> clock-names = "mclk";
> assigned-clocks = <&mclkout_sai0>;
> assigned-clock-rates = <12288000>;
> pinctrl-names = "default";
> pinctrl-0 = <&i2s0m0_mclk>;
> };
>
> clk_summary on sai0 work:
>
> cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"
>
> clk_sai0_src 1 1 0 1188000000 0 0 50000
> clk_sai0_frac 1 1 0 12288000 0 0 50000
> clk_sai0 1 1 0 12288000 0 0 50000
> mclk_sai0 1 1 0 12288000 0 0 50000
> mclk_sai0_out2io 1 1 0 12288000 0 0 50000
> mclk_sai0_to_io 1 1 0 12288000 0 0 50000
>
> example with PD if reg access needed:
>
> * PD status when mclk_sai0_to_io on:
>
> cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
>
> domain status children
> /device runtime status
> ----------------------------------------------------------------------
> ...
>
> vo on
> /devices/platform/clocks/ff040070.mclkout-sai0 active
> ...
>
> * PD status when mclk_sai0_to_io off:
>
> cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
>
> domain status children
> /device runtime status
> ----------------------------------------------------------------------
> ...
>
> vo off-0
> /devices/platform/clocks/ff040070.mclkout-sai0 suspended
> ...
>
> 3. mclkin_sai0 usage:
>
> please override freq of mclkin as the real external clkin, such as:
>
> &mclkin_sai0 {
> clock-frequency = <24576000>;
> }
>
> &ext_codec {
> clocks = <&mclkin_sai0>;
> clock-names = "mclk";
> assigned-clocks = <&cru CLK_SAI0>;
> assigned-clock-parents = <&mclkin_sai0>;
> pinctrl-names = "default";
> pinctrl-0 = <&i2s0m0_mclk>;
> };
>
> clk_summary on sai0 work:
>
> cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"
>
> mclk_sai0_from_io 1 1 0 12288000 0 0 50000
> clk_sai0 1 1 0 12288000 0 0 50000
> mclk_sai0 1 1 0 12288000 0 0 50000
> mclk_sai0_out2io 0 0 0 12288000 0 0 50000
> mclk_sai0_to_io 0 0 0 12288000 0 0 50000
None of this long commit msg is a description of hardware. Please remove
all unnecessary information and instead describe the problem you are
solving or the hardware.
>
> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
> ---
>
> .../bindings/clock/rockchip,clk-out.yaml | 107 +++++++++++++++++++++
> 1 file changed, 107 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml b/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
> new file mode 100644
> index 0000000..6582605
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
> @@ -0,0 +1,107 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip Clock Out Control Module Binding
It does not look like you tested the bindings, at least after quick
look. Please run `make dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
Maybe you need to update your dtschema and yamllint.
> +
> +maintainers:
> + - Sugar Zhang <sugar.zhang@rock-chips.com>
> +
> +description: |
> + This add support switch for clk-bidirection which located
No, "this does not add". This is description of hardware, thus describe
hardware.
> + at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
> + and these config maybe located in many pieces of GRF,
> + which hard to addressed in one single clk driver. so, we add
> + this simple helper driver to address this situation.
Bindings are for hardware, not drivers. Rephrase EVERYTHING to focus on
hardware, not driver. Otherwise it looks like you wrote it for drivers,
which is a NAK.
> +
> + In order to simplify implement and usage, and also for safety
> + clk usage (avoid high freq glitch), we set all clk out as disabled
> + (which means Input default for clk-bidrection) in the pre-stage,
> + such boot-loader or init by HW default. And then set a safety freq
> + before enable clk-out, such as "assign-clock-rates" or clk_set_rate
> + in drivers.
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,clk-out
Missing SoC compatible. See writing bindings.
> +
> + reg:
> + maxItems: 1
> +
> + "#clock-cells":
> + const: 1
> +
> + clocks:
> + maxItems: 1
> + description: parent clocks.
Drop useless description.
> +
> + power-domains:
> + maxItems: 1
> +
> + clock-output-names:
> + maxItems: 1
> +
> + rockchip,bit-shift:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Defines the bit shift of clk out enable.
No, this is deduced from compatible.
> +
> + rockchip,bit-set-to-disable:
> + type: boolean
> + description: |
> + By default this clock sets the bit at bit-shift to enable the clock.
> + Setting this property does the opposite: setting the bit disable
> + the clock and clearing it enables the clock.
No, this is deduced from compatible.
Binding looks really poor, like written for some debug driver.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - "#clock-cells"
> + - clock-output-names
> + - rockchip,bit-shift
> +
> +additionalProperties: false
> +
> +examples:
> + # Clock Provider node:
> + - |
> + mclkin_sai0: mclkin-sai0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12288000>;
> + clock-output-names = "mclk_sai0_from_io";
> + };
Drop, unrelated.
> +
> + mclkout_sai0: mclkout-sai0@ff040070 {
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "rockchip,clk-out";
> + reg = <0 0xff040070 0 0x4>;
> + clocks = <&cru MCLK_SAI0_OUT2IO>;
> + #clock-cells = <0>;
> + clock-output-names = "mclk_sai0_to_io";
> + rockchip,bit-shift = <4>;
> + };
> +
> + # Clock mclkout Consumer node:
> + - |
> + ext_codec {
Drop, not related, incorrect name.
> + clocks = <&mclkout_sai0>;
> + clock-names = "mclk";
> + assigned-clocks = <&mclkout_sai0>;
> + assigned-clock-rates = <12288000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2s0m0_mclk>;
> + };
> +
> + # Clock mclkin Consumer node:
> + - |
> + ext_codec {
Drop.
Don't upstream poor quality downstream code, but fix it first to match
upstream style. Read carefully writing bindings and DTS coding style.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 0/2] Set PHY address of MT7531 switch to 0x1f on MediaTek arm64 boards
From: arinc.unal @ 2024-03-31 9:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: mithat.guner, erkin.bozoglu, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
In-Reply-To: <20240314-for-mediatek-mt7531-phy-address-v1-0-52f58db01acd@arinc9.com>
On 14.03.2024 15:20, Arınç ÜNAL via B4 Relay wrote:
> Hello.
>
> This is a small patch series setting the PHY address of MT7531 to 0x1f
> on
> all boards that have the switch.
>
> Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
> ---
> Arınç ÜNAL (2):
> arm64: dts: mediatek: mt7622: set PHY address of MT7531 switch
> to 0x1f
> arm64: dts: mediatek: mt7986: set PHY address of MT7531 switch
> to 0x1f
>
> arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 ++--
> arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 4 ++--
> arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 4 ++--
> arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 4 ++--
> arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 4 ++--
> 5 files changed, 10 insertions(+), 10 deletions(-)
> ---
> base-commit: ba90af39ba57b3fe3ecfdba0c87a80d20c7b788d
> change-id: 20240314-for-mediatek-mt7531-phy-address-9d0b4cfeca21
>
> Best regards,
Reminder that this patch series is waiting.
Arınç
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: ti: k3-am62p5-sk: minor whitespace cleanup
From: Krzysztof Kozlowski @ 2024-03-31 10:26 UTC (permalink / raw)
To: Benoît Cousson, Tony Lindgren, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Nishanth Menon,
Vignesh Raghavendra, Tero Kristo, linux-omap, devicetree,
linux-kernel, linux-arm-kernel, Krzysztof Kozlowski
In-Reply-To: <20240208105146.128645-1-krzysztof.kozlowski@linaro.org>
On Thu, 08 Feb 2024 11:51:45 +0100, Krzysztof Kozlowski wrote:
> The DTS code coding style expects exactly one space before '{'
> character.
>
>
This is waiting on the lists for almost two months, so I just picked it up. Let
me know if anyone prefers to take it instead.
Applied, thanks!
[1/2] arm64: dts: ti: k3-am62p5-sk: minor whitespace cleanup
https://git.kernel.org/krzk/linux-dt/c/9d0ee097b3e5873e4e98770b94f11481f485e7c9
[2/2] ARM: dts: ti: omap: minor whitespace cleanup
https://git.kernel.org/krzk/linux-dt/c/021bc7094e8c8ac1380527d3f53561c9a234a190
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
^ permalink raw reply
* Re: [PATCH] arm64: dts: sprd: minor whitespace cleanup
From: Krzysztof Kozlowski @ 2024-03-31 10:26 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Orson Zhai,
Baolin Wang, Chunyan Zhang, devicetree, linux-kernel,
Krzysztof Kozlowski
In-Reply-To: <20240208105137.128601-1-krzysztof.kozlowski@linaro.org>
On Thu, 08 Feb 2024 11:51:37 +0100, Krzysztof Kozlowski wrote:
> The DTS code coding style expects exactly one space before '{'
> character.
>
>
This is waiting on the lists for almost two months, so I just picked it up. Let
me know if anyone prefers to take it instead.
Applied, thanks!
[1/1] arm64: dts: sprd: minor whitespace cleanup
https://git.kernel.org/krzk/linux-dt/c/6ff7ac1c4c93b686ebc132d46975d9e8608befb1
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
^ permalink raw reply
* Re: [PATCH 1/5] spi: cadence: Add new bindings documentation for Cadence XSPI
From: kernel test robot @ 2024-03-31 10:43 UTC (permalink / raw)
To: Witold Sadowski, linux-kernel, linux-spi, devicetree
Cc: oe-kbuild-all, broonie, robh, krzysztof.kozlowski+dt, conor+dt,
pthombar, Witold Sadowski
In-Reply-To: <20240329194849.25554-2-wsadowski@marvell.com>
Hi Witold,
kernel test robot noticed the following build warnings:
[auto build test WARNING on broonie-spi/for-next]
[also build test WARNING on linus/master v6.9-rc1 next-20240328]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Witold-Sadowski/spi-cadence-Add-new-bindings-documentation-for-Cadence-XSPI/20240330-035124
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
patch link: https://lore.kernel.org/r/20240329194849.25554-2-wsadowski%40marvell.com
patch subject: [PATCH 1/5] spi: cadence: Add new bindings documentation for Cadence XSPI
compiler: loongarch64-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240331/202403311827.DCvAFLcu-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202403311827.DCvAFLcu-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
>> Documentation/devicetree/bindings/spi/cdns,xspi.yaml: properties:compatible: [{'const': 'cdns,xspi-nor'}, {'const': 'mrvl,xspi-nor'}] is not of type 'object', 'boolean'
from schema $id: http://json-schema.org/draft-07/schema#
>> Documentation/devicetree/bindings/spi/cdns,xspi.yaml: properties:compatible: [{'const': 'cdns,xspi-nor'}, {'const': 'mrvl,xspi-nor'}] is not of type 'object', 'boolean'
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
--
>> Documentation/devicetree/bindings/spi/cdns,xspi.yaml: ignoring, error in schema: properties: compatible
Documentation/devicetree/bindings/net/snps,dwmac.yaml: mac-mode: missing type definition
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH 2/5] spi: cadence: Add Marvell IP modification changes
From: Krzysztof Kozlowski @ 2024-03-31 10:50 UTC (permalink / raw)
To: Witold Sadowski, linux-kernel, linux-spi, devicetree
Cc: broonie, robh, krzysztof.kozlowski+dt, conor+dt, pthombar
In-Reply-To: <20240329194849.25554-3-wsadowski@marvell.com>
On 29/03/2024 20:48, Witold Sadowski wrote:
> Add support for Marvell IP modification - clock divider,
> and PHY config, and IRQ clearing.
> Clock divider block is build into Cadence XSPI controller
> and is connected directly to 800MHz clock.
> As PHY config is not set directly in IP block, driver can
> load custom PHY configuration values.
> To correctly clear interrupt in Marvell implementation
> MSI-X must be cleared too.
>
> Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
> ---
> drivers/spi/spi-cadence-xspi.c | 311 ++++++++++++++++++++++++++++++++-
You already sent this patchset, so this is not v1. Please version your
patches correctly. b4 does it automatically.
You also received last time feedback which it seems you just ignored.
You did not respond to any of the feedback and I do not see it being
addressed here.
That's not how collaboration in upstream projects work. Don't just
ignore reviews you receive. Please carefully read:
https://elixir.bootlin.com/linux/v6.9-rc1/source/Documentation/process/submitting-patches.rst
There is also entire section about this particular issue - responding to
reviewers.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v3 0/2] Samsung Galaxy Z Fold5 initial support
From: Alexandru Marc Serdeliuc via B4 Relay @ 2024-03-31 10:56 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Alexandru Marc Serdeliuc
This documents and add intial dts support for Samsung Galaxy Z Fold5 (samsung,q5q)
which is a foldable phone by Samsung based on the sm8550 SoC.
Currently working features:
- Framebuffer
- UFS
- i2c
- Buttons
Signed-off-by: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
---
Alexandru Marc Serdeliuc (2):
dt-bindings: arm: qcom: Document the Samsung Galaxy Z Fold5
arm64: dts: qcom: sm8550: Add support for Samsung Galaxy Z Fold5
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 582 ++++++++++++++++++++++++
3 files changed, 584 insertions(+)
---
base-commit: 4cece764965020c22cff7665b18a012006359095
change-id: 20240331-samsung-galaxy-zfold5-q5q-e3f348f64757
Best regards,
--
Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
^ permalink raw reply
* [PATCH v3 1/2] dt-bindings: arm: qcom: Document the Samsung Galaxy Z Fold5
From: Alexandru Marc Serdeliuc via B4 Relay @ 2024-03-31 10:56 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Alexandru Marc Serdeliuc
In-Reply-To: <20240331-samsung-galaxy-zfold5-q5q-v3-0-17ae8d0a9fba@yahoo.com>
From: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
This documents Samsung Galaxy Z Fold5 (samsung,q5q)
which is a foldable phone by Samsung based on the sm8550 SoC.
Signed-off-by: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 66beaac60e1d..dea2a23b8fc2 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -1003,6 +1003,7 @@ properties:
- qcom,sm8550-hdk
- qcom,sm8550-mtp
- qcom,sm8550-qrd
+ - samsung,q5q
- const: qcom,sm8550
- items:
--
2.34.1
^ permalink raw reply related
* [PATCH v3 2/2] arm64: dts: qcom: sm8550: Add support for Samsung Galaxy Z Fold5
From: Alexandru Marc Serdeliuc via B4 Relay @ 2024-03-31 10:56 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Alexandru Marc Serdeliuc
In-Reply-To: <20240331-samsung-galaxy-zfold5-q5q-v3-0-17ae8d0a9fba@yahoo.com>
From: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
Add support for Samsung Galaxy Z Fold5 (q5q) foldable phone based on sm8550
Currently working features:
- Framebuffer
- UFS
- i2c
- Buttons
Signed-off-by: Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 582 ++++++++++++++++++++++++
2 files changed, 583 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 7d40ec5e7d21..a7503fd35b6c 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -241,6 +241,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8550-samsung-q5q.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
new file mode 100644
index 000000000000..6619ed00c350
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
@@ -0,0 +1,582 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Alexandru Marc Serdeliuc <serdeliuk@yahoo.com>
+ * Copyright (c) 2024, David Wronek <david@mainlining.org>
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8550.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+
+/ {
+ model = "Samsung Galaxy Z Fold5";
+ compatible = "samsung,q5q", "qcom,sm8550";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer: framebuffer@b8000000 {
+ compatible = "simple-framebuffer";
+ reg = <0x0 0xb8000000 0x0 0x2b00000>;
+ width = <2176>;
+ height = <1812>;
+ stride = <(2176 * 4)>;
+ format = "a8r8g8b8";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reserved-memory {
+ /*
+ * The bootloader will only keep display hardware enabled
+ * if this memory region is named exactly 'splash_region'
+ */
+ splash_region@b8000000 {
+ reg = <0x0 0xb8000000 0x0 0x2b00000>;
+ no-map;
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vreg_l3c_0p91: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vreg_s4e_0p9: smps4 {
+ regulator-name = "vreg_s4e_0p9";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <984000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p1: smps5 {
+ regulator-name = "vreg_s5e_1p1";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <904000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p91: ldo3 {
+ regulator-name = "vreg_l3f_0p91";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "g";
+
+ vreg_s1g_1p2: smps1 {
+ regulator-name = "vreg_s1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p8: smps2 {
+ regulator-name = "vreg_s2g_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p7: smps3 {
+ regulator-name = "vreg_s3g_0p7";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p3: smps4 {
+ regulator-name = "vreg_s4g_1p3";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5g_0p8: smps5 {
+ regulator-name = "vreg_s5g_0p8";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p8: smps6 {
+ regulator-name = "vreg_s6g_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2g_1p2: ldo2 {
+ regulator-name = "vreg_l2g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "m";
+
+ vreg_l1m_1p056: ldo1 {
+ regulator-name = "vreg_l1m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_1p8: ldo6 {
+ regulator-name = "vreg_l6m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p9: ldo7 {
+ regulator-name = "vreg_l7m_2p9";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "n";
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p1: ldo2 {
+ regulator-name = "vreg_l2n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_2p8: ldo3 {
+ regulator-name = "vreg_l3n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_2p8: ldo4 {
+ regulator-name = "vreg_l4n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_1p8: ldo5 {
+ regulator-name = "vreg_l5n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_3p3: ldo6 {
+ regulator-name = "vreg_l6n_3p3";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_2p96: ldo7 {
+ regulator-name = "vreg_l7n_2p96";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+
+&dispcc {
+ status = "disabled";
+};
+
+&i2c_master_hub_0 {
+ status = "okay";
+};
+
+&pcie_1_phy_aux_clk {
+ clock-frequency = <1000>;
+};
+
+&pcie0 {
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+};
+
+&pcie1 {
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l3c_0p91>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ vdda-qref-supply = <&vreg_l1e_0p88>;
+ status = "okay";
+};
+
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8550/adsp.mbn",
+ "qcom/sm8550/adsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8550/cdsp.mbn",
+ "qcom/sm8550/cdsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/sm8550/modem.mbn",
+ "qcom/sm8550/modem_dtb.mbn";
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&tlmm {
+ gpio-reserved-ranges = <36 4>, <50 2>;
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
--
2.34.1
^ permalink raw reply related
* [PATCH 1/5] dt-bindings: mfd: add entry for Marvell 88PM886 PMIC
From: Karel Balej @ 2024-03-31 10:46 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Dmitry Torokhov, Liam Girdwood, Mark Brown, devicetree,
linux-kernel, linux-input
Cc: Duje Mihanović, ~postmarketos/upstreaming, phone-devel
In-Reply-To: <20240331105608.7338-2-balejk@matfyz.cz>
Marvell 88PM886 is a PMIC with several subdevices such as onkey,
regulators or battery and charger. It comes in at least two revisions,
A0 and A1 -- only A1 is described here at the moment.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Karel Balej <balejk@matfyz.cz>
---
Notes:
RFC v4:
- Address Krzysztof's comments:
- Fix regulators indentation.
- Add Krzysztof's trailer.
RFC v3:
- Add wakeup-source property.
- Address Rob's feedback:
- Move regulators into the MFD file.
- Remove interrupt-controller and #interrupt-cells properties.
RFC v2:
- Address Rob's feedback:
- Drop mention of 88PM880.
- Make sure the file passes bindings check (add the necessary header
and fix `interrupt-cells`).
- Other small changes.
- Add regulators. Changes with respect to the regulator RFC series:
- Address Krzysztof's comments:
- Drop unused compatible.
- Fix sub-node pattern.
.../bindings/mfd/marvell,88pm886-a1.yaml | 76 +++++++++++++++++++
1 file changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/marvell,88pm886-a1.yaml
diff --git a/Documentation/devicetree/bindings/mfd/marvell,88pm886-a1.yaml b/Documentation/devicetree/bindings/mfd/marvell,88pm886-a1.yaml
new file mode 100644
index 000000000000..d6a71c912b76
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/marvell,88pm886-a1.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/marvell,88pm886-a1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell 88PM886 PMIC core
+
+maintainers:
+ - Karel Balej <balejk@matfyz.cz>
+
+description:
+ Marvell 88PM886 is a PMIC providing several functions such as onkey,
+ regulators or battery and charger.
+
+properties:
+ compatible:
+ const: marvell,88pm886-a1
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ wakeup-source: true
+
+ regulators:
+ type: object
+ additionalProperties: false
+ patternProperties:
+ "^(ldo(1[0-6]|[1-9])|buck[1-5])$":
+ type: object
+ $ref: /schemas/regulator/regulator.yaml#
+ description: LDO or buck regulator.
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic@30 {
+ compatible = "marvell,88pm886-a1";
+ reg = <0x30>;
+ interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ wakeup-source;
+
+ regulators {
+ ldo2: ldo2 {
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo15: ldo15 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ buck2: buck2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+ };
+...
--
2.44.0
^ permalink raw reply related
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