* Re: [RFC PATCH 1/2] spi: dt-bindings: add Siflower Quad SPI controller
From: Qingfang Deng @ 2024-04-01 3:36 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Qingfang Deng, linux-spi, devicetree, linux-kernel
In-Reply-To: <261f2995-b279-48bc-b9d4-023a8a705857@linaro.org>
Hi Krzysztof,
On Sun, Mar 31, 2024 at 1:42 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 29/03/2024 02:51, Qingfang Deng wrote:
> > Add YAML devicetree bindings for Siflower Quad SPI controller.
>
> Describe the hardware. What is this Siflower?
It's a new RISC-V SoC which hasn't been upstreamed yet.
> > +properties:
> > + compatible:
> > + const: siflower,qspi
>
> Except that this was not tested, aren't you adding it for some SoC? If
> so, then you miss here SoC part.
I should add the "siflower" prefix to
Documentation/devicetree/bindings/vendor-prefixes.yaml, right?
Regards,
Qingfang
^ permalink raw reply
* Re: [PATCH v6 0/2] ASoC: nau8325: Modify driver code and dtschema.
From: WTLI @ 2024-04-01 3:59 UTC (permalink / raw)
To: Mark Brown
Cc: lgirdwood, alsa-devel, devicetree, linux-sound,
krzysztof.kozlowski+dt, linux-kernel, robh+dt, conor+dt, perex,
tiwai, YHCHuang, KCHSU0, CTLIN0, SJLIN0, scott6986,
supercraig0719, dardar923
In-Reply-To: <ZgbFv+c3fjME+x+Y@finisterre.sirena.org.uk>
Mark Brown 於 3/29/2024 9:44 PM 寫道:
> On Fri, Mar 29, 2024 at 04:54:00PM +0800, Seven Lee wrote:
>> Revise properties description and use standard units in dtschema.
>> The unit conversion driver based on the attribute must also be
>> changed accordingly.
> My applying the prior version raced with you sending this new one, could
> you please send incremental patches with the changes from your v6?
Sorry, I misunderstood. I will send incremental patches with my v6.
________________________________
________________________________
The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.
^ permalink raw reply
* [PATCH] ASoC: dt-bindings: mt2701-wm8960: Convert to dtschema
From: Kartik Agarwala @ 2024-04-01 4:35 UTC (permalink / raw)
To: lgirdwood, broonie, robh, krzysztof.kozlowski+dt, conor+dt,
matthias.bgg, angelogioacchino.delregno
Cc: Kartik Agarwala, linux-sound, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Convert mt2701-wm890 bindings from text to dtschema. This is used by MediaTek mt77623a/n SoC.
Signed-off-by: Kartik Agarwala <agarwala.kartik@gmail.com>
---
.../sound/mediatek,mt2701-wm8960.yaml | 59 +++++++++++++++++++
.../bindings/sound/mt2701-wm8960.txt | 24 --------
2 files changed, 59 insertions(+), 24 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt2701-wm8960.yaml
delete mode 100644 Documentation/devicetree/bindings/sound/mt2701-wm8960.txt
diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt2701-wm8960.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt2701-wm8960.yaml
new file mode 100644
index 000000000..771f14a59
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mediatek,mt2701-wm8960.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/mediatek,mt2701-wm8960.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT2701 with WM8960 CODEC
+
+maintainers:
+ - Kartik Agarwala <agarwala.kartik@gmail.com>
+
+properties:
+ compatible:
+ const: mediatek,mt2701-wm8960-machine
+
+ mediatek,platform:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of MT2701 ASoC platform.
+
+ audio-routing:
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ description: |
+ A list of the connections between audio components. Each entry is a
+ pair of strings, the first being the connection's sink, the second
+ being the connection's source.
+
+ mediatek,audio-codec:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of the WM8960 audio codec.
+
+ pinctrl-names:
+ const: default
+
+ pinctrl-0: true
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - mediatek,platform
+ - audio-routing
+ - mediatek,audio-codec
+ - pinctrl-names
+ - pinctrl-0
+
+examples:
+ - |
+ sound {
+ compatible = "mediatek,mt2701-wm8960-machine";
+ mediatek,platform = <&afe>;
+ audio-routing =
+ "Headphone", "HP_L",
+ "Headphone", "HP_R",
+ "LINPUT1", "AMIC",
+ "RINPUT1", "AMIC";
+ mediatek,audio-codec = <&wm8960>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&aud_pins_default>;
+ };
diff --git a/Documentation/devicetree/bindings/sound/mt2701-wm8960.txt b/Documentation/devicetree/bindings/sound/mt2701-wm8960.txt
deleted file mode 100644
index 809b609ea..000000000
--- a/Documentation/devicetree/bindings/sound/mt2701-wm8960.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-MT2701 with WM8960 CODEC
-
-Required properties:
-- compatible: "mediatek,mt2701-wm8960-machine"
-- mediatek,platform: the phandle of MT2701 ASoC platform
-- audio-routing: a list of the connections between audio
-- mediatek,audio-codec: the phandles of wm8960 codec
-- pinctrl-names: Should contain only one value - "default"
-- pinctrl-0: Should specify pin control groups used for this controller.
-
-Example:
-
- sound:sound {
- compatible = "mediatek,mt2701-wm8960-machine";
- mediatek,platform = <&afe>;
- audio-routing =
- "Headphone", "HP_L",
- "Headphone", "HP_R",
- "LINPUT1", "AMIC",
- "RINPUT1", "AMIC";
- mediatek,audio-codec = <&wm8960>;
- pinctrl-names = "default";
- pinctrl-0 = <&aud_pins_default>;
- };
--
2.34.1
^ permalink raw reply related
* Re: [PATCH] ASoC: dt-bindings: mt2701-wm8960: Convert to dtschema
From: Kartik Agarwala @ 2024-04-01 4:49 UTC (permalink / raw)
To: lgirdwood, broonie, robh, krzysztof.kozlowski+dt, conor+dt,
matthias.bgg, angelogioacchino.delregno
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek
In-Reply-To: <20240401043505.40972-1-agarwala.kartik@gmail.com>
On 4/1/24 10:05 AM, Kartik Agarwala wrote:
> Convert mt2701-wm890 bindings from text to dtschema. This is used by MediaTek mt77623a/n SoC.
Apologies for the typo, it should be mt7623a/n instead of mt77623a/n.
Regards,
Kartik Agarwala
^ permalink raw reply
* Re: [PATCH v5 1/2] dt-bindings: hwmon: Add NCT7363Y documentation
From: Ban Feng @ 2024-04-01 6:20 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Guenter Roeck, Rob Herring, linux-hwmon, krzysztof.kozlowski+dt,
robh+dt, conor+dt, corbet, jdelvare, kwliu, kcfeng0, Paul Menzel,
linux-kernel, devicetree, Bonnie_Lo, linux-doc, DELPHINE_CHIU,
openbmc
In-Reply-To: <e1102a00-0c94-4d35-8de2-1173ee417bdc@linaro.org>
Hi Krzysztof,
Thanks for your support.
Best regards,
Ban
On Tue, Mar 26, 2024 at 2:29 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 25/03/2024 18:09, Guenter Roeck wrote:
> > On 3/22/24 02:26, Rob Herring wrote:
> >>
> >> On Fri, 22 Mar 2024 16:11:57 +0800, baneric926@gmail.com wrote:
> >>> From: Ban Feng <kcfeng0@nuvoton.com>
> >>>
> >>> Add bindings for the Nuvoton NCT7363Y Fan Controller
> >>>
> >>> Reviewed-by: Rob Herring <robh@kernel.org>
> >>> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
> >>> Signed-off-by: Ban Feng <kcfeng0@nuvoton.com>
> >>> ---
> >>> .../bindings/hwmon/nuvoton,nct7363.yaml | 66 +++++++++++++++++++
> >>> MAINTAINERS | 6 ++
> >>> 2 files changed, 72 insertions(+)
> >>> create mode 100644 Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.yaml
> >>>
> >>
> >> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> >> on your patch (DT_CHECKER_FLAGS is new in v5.13):
> >>
> >> yamllint warnings/errors:
> >>
> >> dtschema/dtc warnings/errors:
> >> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.yaml:
> >> Error in referenced schema matching $id: http://devicetree.org/schemas/hwmon/fan-common.yaml
> >> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.example.dtb: hwmon@22: fan-0: False schema does not allow {'pwms': [[1, 0, 50000]], 'tach-ch': ['']}
> >> from schema $id: http://devicetree.org/schemas/hwmon/nuvoton,nct7363.yaml#
> >> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.example.dtb: hwmon@22: fan-0: Unevaluated properties are not allowed ('pwms', 'tach-ch' were unexpected)
> >> from schema $id: http://devicetree.org/schemas/hwmon/nuvoton,nct7363.yaml#
> >> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.example.dtb: hwmon@22: fan-1: False schema does not allow {'pwms': [[1, 1, 50000]], 'tach-ch': b'\x01'}
> >> from schema $id: http://devicetree.org/schemas/hwmon/nuvoton,nct7363.yaml#
> >> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.example.dtb: hwmon@22: fan-1: Unevaluated properties are not allowed ('pwms', 'tach-ch' were unexpected)
> >> from schema $id: http://devicetree.org/schemas/hwmon/nuvoton,nct7363.yaml#
> >> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/hwmon/nuvoton,nct7363.example.dtb: fan-1: tach-ch: b'\x01' is not of type 'object', 'array', 'boolean', 'null'
> >> from schema $id: http://devicetree.org/schemas/dt-core.yaml#
> >>
> >> doc reference errors (make refcheckdocs):
> >>
> >> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240322081158.4106326-2-kcfeng0@nuvoton.com
> >>
> >> The base for the series is generally the latest rc1. A different dependency
> >> should be noted in *this* patch.
> >>
> >> If you already ran 'make dt_binding_check' and didn't see the above
> >> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> >> date:
> >>
> >> pip3 install dtschema --upgrade
> >>
> >> Please check and re-submit after running the above command yourself. Note
> >> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> >> your schema. However, it must be unset to test all examples with your schema.
> >>
> >
> > I am a bit puzzled by this one. The patch has a Reviewed-by: tag from Rob,
> > but then Rob's bot complains about errors. hat am I missing ?
>
> The warning is a result of missing fan-common.yaml in the tree used as a
> base.
>
> I checked now and I don't see warnings on next or v6.9-rc1, so it is
> safe for you to apply it.
>
> For the record:
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply
* RE: 回复: [PATCH v2 1/2] ASoC: dt-bindings: Add bindings for Cadence I2S-MC controller
From: Xingyu Wu @ 2024-04-01 6:32 UTC (permalink / raw)
To: Krzysztof Kozlowski, Mark Brown
Cc: Liam Girdwood, Claudiu Beznea, Jaroslav Kysela, Takashi Iwai,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
alsa-devel@alsa-project.org, linux-sound@vger.kernel.org
In-Reply-To: <7297bd78-4f74-4d23-afb3-9b7aecbe451d@linaro.org>
On 30/03/2024 0:02, Krzysztof Kozlowski wrote:
>
> On 29/03/2024 14:36, Mark Brown wrote:
> > On Fri, Mar 29, 2024 at 12:42:22PM +0100, Krzysztof Kozlowski wrote:
> >
> >> I stated and I keep my statement that such block is usually not
> >> usable on its own and always needs some sort of quirks or
> >> SoC-specific implementation. At least this is what I saw in other
> >> similar cases, but not exactly I2S.
> >
> > I wouldn't be so pessimistic, especially not for I2S - a good portion
> > of quirks there are extra features rather than things needed for basic
> > operation, a lot of things that might in the past have been quirks for
> > basic operation are these days hidden behind the DT bindings.
>
> OK, I trust your judgement, so cdns as fallback seems okay, but I don't think it
> warrants cdns as used alone. Not particularly because cdns is different, but
> because we expect specific SoC compatible always.
>
> Thus if cdns,i2s-mc stays, then:
>
> items:
> - enum:
> - starfive,jh8100-i2s
> - cdns,i2s-mc
>
OK, thanks Krzysztof and Mark. I will modify it in next patch.
Best regards,
Xingyu Wu
^ permalink raw reply
* RE: [PATCH v5 3/4] dt-bindings: clock: add i.MX95 clock header
From: Peng Fan @ 2024-04-01 7:26 UTC (permalink / raw)
To: Krzysztof Kozlowski, Peng Fan (OSS), Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Abel Vesa
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <31b493d1-ad74-48c7-8585-9df323418ae3@linaro.org>
> Subject: Re: [PATCH v5 3/4] dt-bindings: clock: add i.MX95 clock header
>
> On 24/03/2024 08:52, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > Add clock header for i.MX95 BLK CTL modules
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> > include/dt-bindings/clock/nxp,imx95-clock.h | 32
> +++++++++++++++++++++++++++++
> > 1 file changed, 32 insertions(+)
> >
> > diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h b/include/dt-
> bindings/clock/nxp,imx95-clock.h
> > new file mode 100644
> > index 000000000000..83fa3ffe78a8
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/nxp,imx95-clock.h
> > @@ -0,0 +1,32 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#ifndef __DT_BINDINGS_CLOCK_IMX95_H
> > +#define __DT_BINDINGS_CLOCK_IMX95_H
> > +
> > +#define IMX95_CLK_VPUBLK_WAVE 0
> > +#define IMX95_CLK_VPUBLK_JPEG_ENC 1
> > +#define IMX95_CLK_VPUBLK_JPEG_DEC 2
> > +#define IMX95_CLK_VPUBLK_END 3
>
> No improvements, so again: drop counting.
Could you please give more details on what you think needs
to be addressed here? I may overlook your comments before,
but I search v1-v4, not find comments on the headers,
except the one file name align with binding if 1:1 match.
Thanks,
Peng.
>
> Same in other places.
>
> Best regards,
> Krzysztof
^ permalink raw reply
* [PATCH V3] schemas: pci: Extend the meaning of 'linux,pci-probe-only'
From: Vidya Sagar @ 2024-04-01 7:49 UTC (permalink / raw)
To: robh, bhelgaas
Cc: devicetree, linux-kernel, treding, jonathanh, kthota, mmaddireddy,
vidyas, sagar.tv
Extend the meaning of 'linux,pci-probe-only' to cover the cases where
it is applicable only to a specific PCI host bridge if defined in a
PCI node instead of chosen node. Add the documentation for the same
in schemas/pci/pci-host-bridge.yaml
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V3:
* Addressed Rob's review comments
V2:
* Addressed Bjorn's review comments
dtschema/schemas/chosen.yaml | 7 +++++--
dtschema/schemas/pci/pci-host-bridge.yaml | 11 +++++++++++
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/dtschema/schemas/chosen.yaml b/dtschema/schemas/chosen.yaml
index 6d5c3f1..f806646 100644
--- a/dtschema/schemas/chosen.yaml
+++ b/dtschema/schemas/chosen.yaml
@@ -142,8 +142,11 @@ properties:
enum: [ 0, 1 ]
description:
Optional property which takes a single-cell argument. If '0', then Linux
- will assign devices in its usual manner, otherwise it will not try to
- assign devices and instead use them as they are configured already.
+ will reassign BARs and bridge windows in its usual manner, otherwise it will
+ not try to reassign BARs and bridge windows, instead use them as they are
+ configured already by the platform firmware.
+ NOTE:- To restrict the applicability of this property to a specific PCI
+ host bridge, please refer to /schemas/pci/pci-host-bridge.yaml
stdout-path:
$ref: types.yaml#/definitions/string
diff --git a/dtschema/schemas/pci/pci-host-bridge.yaml b/dtschema/schemas/pci/pci-host-bridge.yaml
index fbbb829..e6665e7 100644
--- a/dtschema/schemas/pci/pci-host-bridge.yaml
+++ b/dtschema/schemas/pci/pci-host-bridge.yaml
@@ -31,6 +31,17 @@ properties:
number for each host bridge in the system must be unique.
$ref: /schemas/types.yaml#/definitions/uint32
+ linux,pci-probe-only:
+ $ref: types.yaml#/definitions/uint32
+ enum: [ 0, 1 ]
+ description:
+ Optional property which takes a single-cell argument. If '0', then Linux
+ will reassign BARs and bridge windows in its usual manner, otherwise it will
+ not try to reassign BARs and bridge windows, instead use them as they are
+ configured already by the platform firmware.
+ NOTE:- If defined in chosen node, this property has system wide applicability.
+ Please refer to /schemas/chosen.yaml for more info.
+
msi-map:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
--
2.25.1
^ permalink raw reply related
* [PATCH V5] PCI: Add support for preserving boot configuration
From: Vidya Sagar @ 2024-04-01 7:50 UTC (permalink / raw)
To: bhelgaas, rafael, lenb, will, lpieralisi, kw, robh, frowand.list
Cc: linux-pci, linux-acpi, linux-kernel, linux-arm-kernel, devicetree,
treding, jonathanh, kthota, mmaddireddy, vidyas, sagar.tv
In-Reply-To: <20240223080021.1692996-1-vidyas@nvidia.com>
Add support for preserving the boot configuration done by the
platform firmware per host bridge basis, based on the presence of
'linux,pci-probe-only' property in the respective PCI host bridge
device-tree node. It also unifies the ACPI and DT based boot flows
in this regard.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V5:
* Addressed Rob's review comments
V4:
* Addressed Bjorn's review comments
V3:
* Unified ACPI and DT flows as part of addressing Bjorn's review comments
V2:
* Addressed issues reported by kernel test robot <lkp@intel.com>
drivers/acpi/pci_root.c | 12 -----
drivers/pci/controller/pci-host-common.c | 4 --
drivers/pci/of.c | 57 +++++++++++++++++++-----
drivers/pci/probe.c | 46 ++++++++++++++-----
include/linux/of_pci.h | 6 +++
5 files changed, 88 insertions(+), 37 deletions(-)
diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index 84030804a763..ddc2b3e89111 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -1008,7 +1008,6 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
int node = acpi_get_node(device->handle);
struct pci_bus *bus;
struct pci_host_bridge *host_bridge;
- union acpi_object *obj;
info->root = root;
info->bridge = device;
@@ -1050,17 +1049,6 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL))
host_bridge->native_cxl_error = 0;
- /*
- * Evaluate the "PCI Boot Configuration" _DSM Function. If it
- * exists and returns 0, we must preserve any PCI resource
- * assignments made by firmware for this host bridge.
- */
- obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 1,
- DSM_PCI_PRESERVE_BOOT_CONFIG, NULL);
- if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0)
- host_bridge->preserve_config = 1;
- ACPI_FREE(obj);
-
acpi_dev_power_up_children_with_adr(device);
pci_scan_child_bus(bus);
diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/controller/pci-host-common.c
index 6be3266cd7b5..e2602e38ae45 100644
--- a/drivers/pci/controller/pci-host-common.c
+++ b/drivers/pci/controller/pci-host-common.c
@@ -73,10 +73,6 @@ int pci_host_common_probe(struct platform_device *pdev)
if (IS_ERR(cfg))
return PTR_ERR(cfg);
- /* Do not reassign resources if probe only */
- if (!pci_has_flag(PCI_PROBE_ONLY))
- pci_add_flags(PCI_REASSIGN_ALL_BUS);
-
bridge->sysdata = cfg;
bridge->ops = (struct pci_ops *)&ops->pci_ops;
bridge->msi_domain = true;
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index 51e3dd0ea5ab..e6da3654f9ac 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -239,24 +239,61 @@ EXPORT_SYMBOL_GPL(of_get_pci_domain_nr);
*/
void of_pci_check_probe_only(void)
{
- u32 val;
+ bool is_preserve_config = of_pci_bridge_preserve_resources(of_chosen);
+
+ if (is_preserve_config)
+ pci_add_flags(PCI_PROBE_ONLY);
+ else
+ pci_clear_flags(PCI_PROBE_ONLY);
+
+ pr_info("PROBE_ONLY %s\n", is_preserve_config ? "enabled" : "disabled");
+}
+EXPORT_SYMBOL_GPL(of_pci_check_probe_only);
+
+/**
+ * of_pci_bridge_preserve_resources - Return true if the boot configuration
+ * needs to be preserved
+ * @node: Device tree node.
+ *
+ * This function looks for "linux,pci-probe-only" property for a given
+ * PCI controller's node and returns true if found. It will also look in the
+ * chosen node if the property is not found in the given controller's node.
+ * Having this property ensures that the kernel doesn't reconfigure the
+ * BARs and bridge windows that are already done by the platform firmware.
+ *
+ * Return: true if the property exists false otherwise.
+ */
+bool of_pci_bridge_preserve_resources(struct device_node *node)
+{
+ u32 val = 0;
int ret;
- ret = of_property_read_u32(of_chosen, "linux,pci-probe-only", &val);
+ if (!node) {
+ pr_warn("device node is NULL, trying with of_chosen\n");
+ node = of_chosen;
+ }
+
+retry:
+ ret = of_property_read_u32(node, "linux,pci-probe-only", &val);
if (ret) {
- if (ret == -ENODATA || ret == -EOVERFLOW)
- pr_warn("linux,pci-probe-only without valid value, ignoring\n");
- return;
+ if (ret == -ENODATA || ret == -EOVERFLOW) {
+ pr_warn("Incorrect value for linux,pci-probe-only in %pOF, ignoring\n", node);
+ return false;
+ }
+ if (ret == -EINVAL) {
+ if (node == of_chosen)
+ return false;
+
+ node = of_chosen;
+ goto retry;
+ }
}
if (val)
- pci_add_flags(PCI_PROBE_ONLY);
+ return true;
else
- pci_clear_flags(PCI_PROBE_ONLY);
-
- pr_info("PROBE_ONLY %s\n", val ? "enabled" : "disabled");
+ return false;
}
-EXPORT_SYMBOL_GPL(of_pci_check_probe_only);
/**
* devm_of_pci_get_host_bridge_resources() - Resource-managed parsing of PCI
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 795534589b98..b0e0226a8da8 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -15,6 +15,7 @@
#include <linux/cpumask.h>
#include <linux/aer.h>
#include <linux/acpi.h>
+#include <linux/pci-acpi.h>
#include <linux/hypervisor.h>
#include <linux/irqdomain.h>
#include <linux/pm_runtime.h>
@@ -877,6 +878,28 @@ static void pci_set_bus_msi_domain(struct pci_bus *bus)
dev_set_msi_domain(&bus->dev, d);
}
+static void pci_check_config_preserve(struct pci_host_bridge *host_bridge)
+{
+ if (ACPI_HANDLE(&host_bridge->dev)) {
+ union acpi_object *obj;
+
+ /*
+ * Evaluate the "PCI Boot Configuration" _DSM Function. If it
+ * exists and returns 0, we must preserve any PCI resource
+ * assignments made by firmware for this host bridge.
+ */
+ obj = acpi_evaluate_dsm(ACPI_HANDLE(&host_bridge->dev), &pci_acpi_dsm_guid, 1,
+ DSM_PCI_PRESERVE_BOOT_CONFIG, NULL);
+ if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0)
+ host_bridge->preserve_config = 1;
+ ACPI_FREE(obj);
+ }
+
+ if (host_bridge->dev.parent && host_bridge->dev.parent->of_node)
+ host_bridge->preserve_config =
+ of_pci_bridge_preserve_resources(host_bridge->dev.parent->of_node);
+}
+
static int pci_register_host_bridge(struct pci_host_bridge *bridge)
{
struct device *parent = bridge->dev.parent;
@@ -971,6 +994,9 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
+ /* Check if the boot configuration by FW needs to be preserved */
+ pci_check_config_preserve(bridge);
+
/* Coalesce contiguous windows */
resource_list_for_each_entry_safe(window, n, &resources) {
if (list_is_last(&window->node, &resources))
@@ -3080,20 +3106,18 @@ int pci_host_probe(struct pci_host_bridge *bridge)
bus = bridge->bus;
+ /* If we must preserve the resource configuration, claim now */
+ if (bridge->preserve_config)
+ pci_bus_claim_resources(bus);
+
/*
- * We insert PCI resources into the iomem_resource and
- * ioport_resource trees in either pci_bus_claim_resources()
- * or pci_bus_assign_resources().
+ * Assign whatever was left unassigned. If we didn't claim above,
+ * this will reassign everything.
*/
- if (pci_has_flag(PCI_PROBE_ONLY)) {
- pci_bus_claim_resources(bus);
- } else {
- pci_bus_size_bridges(bus);
- pci_bus_assign_resources(bus);
+ pci_assign_unassigned_root_bus_resources(bus);
- list_for_each_entry(child, &bus->children, node)
- pcie_bus_configure_settings(child);
- }
+ list_for_each_entry(child, &bus->children, node)
+ pcie_bus_configure_settings(child);
pci_bus_add_devices(bus);
return 0;
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
index 29658c0ee71f..3f3909a5d55d 100644
--- a/include/linux/of_pci.h
+++ b/include/linux/of_pci.h
@@ -13,6 +13,7 @@ struct device_node *of_pci_find_child_device(struct device_node *parent,
unsigned int devfn);
int of_pci_get_devfn(struct device_node *np);
void of_pci_check_probe_only(void);
+bool of_pci_bridge_preserve_resources(struct device_node *node);
#else
static inline struct device_node *of_pci_find_child_device(struct device_node *parent,
unsigned int devfn)
@@ -26,6 +27,11 @@ static inline int of_pci_get_devfn(struct device_node *np)
}
static inline void of_pci_check_probe_only(void) { }
+
+static inline bool of_pci_bridge_preserve_resources(struct device_node *node)
+{
+ return false;
+}
#endif
#if IS_ENABLED(CONFIG_OF_IRQ)
--
2.25.1
^ permalink raw reply related
* [PATCH] arm64: dts: rockchip: remove startup-delay-us from vcc3v3_pcie2x1l0 on rock-5b
From: Jianfeng Liu @ 2024-04-01 8:13 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
Cc: robh, krzysztof.kozlowski+dt, conor+dt, heiko, sfr,
liujianfeng1994
Property startup-delay-us is copied from vendor dts and it will
make kernel not detect pcie wifi device. If I run command:
"echo 1 > /sys/bus/pci/rescan", pcie wifi device is detected, but
my wifi device RTL8822CE failed to load driver. Another device
RTL8723BE can load driver but no wifi signal is detected.
Removing this property will fix issues above.
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
index d6bf2ee07..a9af654a0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -76,7 +76,6 @@ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- startup-delay-us = <50000>;
vin-supply = <&vcc5v0_sys>;
};
--
2.34.1
^ permalink raw reply related
* Re: [PATCH] iio: industrialio-core: look for aliases to request device index
From: Dominique Martinet @ 2024-04-01 8:18 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Jonathan Cameron, David Lechner, Krzysztof Kozlowski,
Syunya Ohshio, Guido Günther, Lars-Peter Clausen,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-iio,
devicetree, linux-kernel
In-Reply-To: <20240331152042.394b4289@jic23-huawei>
Jonathan Cameron wrote on Sun, Mar 31, 2024 at 03:20:42PM +0100:
> Hi, got back to this finally...
Thank you for taking the time to express your thoughts!
> So the problems compared to other 'alias' users is that IIO is a bit more
> complex than for example LEDs. A single DT node/compatible (or equivalent) can
> result in a 1+ IIO devices and 1+ triggers.
Right. I'm no longer really arguing for it at this point, but for
comparison in the patch I sent, the alias sets the start of the idr for
the device index, so if you have a driver that creates two IIO devices
you could just "reserve" two for this DT node and assuming the order
within this node is constant you'd still get constant numbering, so I
think it still somewhat holds up here.
For triggers though the numbers are separate and it wouldn't make sense
to use the same alias, if we wanted a coherent design with this we'd
need to add a second alias (such as iio_trigger = ..), but that makes
much less sense to me given they're also likely to be dynamically
instancied via configfs from what I've seen; I wouldn't want to do this
kind of mapping, so I agree with you.
> So I've messed around a bit and can think of various possible options to make
> this simpler.
> 1) Use a tmpfs mount and link from that.
> Now we 'could' put an alias directory somewhere under /sys/bus/iio/ that
> is a mount point created via sysfs_create_mount_point() - I abused the
> /sys/kernel/debug directory to test this (unmounted debugfs and mounted
> a tmpfs). That would provide somewhere in sysfs that allows suitable
> links. However, this is unusual so likely to be controversial.
Agreed that's probably not something we want to put our hands into.
> 2) Alternatively the relevant platform could create one of these somewhere
> outside of sysfs and use udev rules to create the links.
I'm not sure I understood this one, something akin to the udev rules
I've showed that made links to the /sys iio device in /dev?
"relevant platform" here would be vendors?
> 3) Stick to the oddity of doing it under /dev/
> 4) Access the things in the first place via more stable paths?
> /sys/bus/i2c/devices/i2c-0/0-0008/iio\:device?/ etc
> Relying on the alias support for i2c bus numbering to make that stable should work
> and if you are sure there will only be one entry (most devices) that matches
> the wild card, should be easy enough to use in scripts.
>
> My personal preference is this last option. Basically if you want stable paths
> don't use /sys/bus/iio/devices/ to get them.
Hmm, I wouldn't call that path stable given the '?' portion can change,
but at least that certainly is a single glob away so it's definitely
simpler than checking every labels all the time.
My second nitpick with this is that while these paths are stable for a
given kernel version, but we've had some paths changes over many years
(not sure if it was 3.14 or 4.9 but one of these perhaps didn't have
/sys/devices/platform yet? and things got moved there at some point with
some subtle name changes, breaking a couple of scripts).
OTOH /sys/bus/iio/devices feels less likely to change, but I guess this
is something that'd come up on tests when preparing a new kernel anyway,
so this is probably acceptable; I'm just thinking out loud.
With that said I can't think of anything that'd work everywhere either,
so I guess we can stick to the status-quo and I'll rediscuss what we
want to do with coworkers.
Thanks,
--
Dominique
^ permalink raw reply
* [PATCH v3] dt-bindings: mfd: twl: Convert trivial subdevices to json-schema
From: Andreas Kemnade @ 2024-04-01 8:18 UTC (permalink / raw)
To: dmitry.torokhov, robh, krzysztof.kozlowski+dt, conor+dt, lee,
alexandre.belloni, wim, linux, andreas, linux-input, devicetree,
linux-kernel, linux-rtc, linux-watchdog, sre
Convert subdevices with just an interrupt and compatbile to
json-schema and wire up already converted subdevices.
RTC is available in all variants, so allow it unconditionally.
GPADC binding for TWL603X uses two different compatibles, so
specify just the compatible and do not include it.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Acked-by: Guenter Roeck <linux@roeck-us.net>
---
Changes in v3:
- added Ack
(apparantly many recipients did not receive the V2 patch,
so there is a need for a resend)
Changes in v2:
- style cleanup
- absolute paths
- unevalutedProperties instead of additionalProperties
due to not accepting things in if: clauses without it
.../bindings/input/twl4030-pwrbutton.txt | 21 ------
.../devicetree/bindings/mfd/ti,twl.yaml | 72 ++++++++++++++++++-
.../devicetree/bindings/rtc/twl-rtc.txt | 11 ---
.../bindings/watchdog/twl4030-wdt.txt | 10 ---
4 files changed, 71 insertions(+), 43 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/input/twl4030-pwrbutton.txt
delete mode 100644 Documentation/devicetree/bindings/rtc/twl-rtc.txt
delete mode 100644 Documentation/devicetree/bindings/watchdog/twl4030-wdt.txt
diff --git a/Documentation/devicetree/bindings/input/twl4030-pwrbutton.txt b/Documentation/devicetree/bindings/input/twl4030-pwrbutton.txt
deleted file mode 100644
index 6c201a2ba8acf..0000000000000
--- a/Documentation/devicetree/bindings/input/twl4030-pwrbutton.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Texas Instruments TWL family (twl4030) pwrbutton module
-
-This module is part of the TWL4030. For more details about the whole
-chip see Documentation/devicetree/bindings/mfd/ti,twl.yaml.
-
-This module provides a simple power button event via an Interrupt.
-
-Required properties:
-- compatible: should be one of the following
- - "ti,twl4030-pwrbutton": For controllers compatible with twl4030
-- interrupts: should be one of the following
- - <8>: For controllers compatible with twl4030
-
-Example:
-
-&twl {
- twl_pwrbutton: pwrbutton {
- compatible = "ti,twl4030-pwrbutton";
- interrupts = <8>;
- };
-};
diff --git a/Documentation/devicetree/bindings/mfd/ti,twl.yaml b/Documentation/devicetree/bindings/mfd/ti,twl.yaml
index 52ed228fb1e7e..c2357fecb56cc 100644
--- a/Documentation/devicetree/bindings/mfd/ti,twl.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,twl.yaml
@@ -15,6 +15,67 @@ description: |
USB transceiver or Audio amplifier.
These chips are connected to an i2c bus.
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,twl4030
+ then:
+ properties:
+ madc:
+ type: object
+ $ref: /schemas/iio/adc/ti,twl4030-madc.yaml
+ unevaluatedProperties: false
+
+ bci:
+ type: object
+ $ref: /schemas/power/supply/twl4030-charger.yaml
+ unevaluatedProperties: false
+
+ pwrbutton:
+ type: object
+ additionalProperties: false
+ properties:
+ compatible:
+ const: ti,twl4030-pwrbutton
+ interrupts:
+ items:
+ - items:
+ const: 8
+
+ watchdog:
+ type: object
+ additionalProperties: false
+ properties:
+ compatible:
+ const: ti,twl4030-wdt
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,twl6030
+ then:
+ properties:
+ gpadc:
+ type: object
+ properties:
+ compatible:
+ const: ti,twl6030-gpadc
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,twl6032
+ then:
+ properties:
+ gpadc:
+ type: object
+ properties:
+ compatible:
+ const: ti,twl6032-gpadc
+
properties:
compatible:
description:
@@ -42,7 +103,16 @@ properties:
"#clock-cells":
const: 1
-additionalProperties: false
+ rtc:
+ type: object
+ additionalProperties: false
+ properties:
+ compatible:
+ const: ti,twl4030-rtc
+ interrupts:
+ maxItems: 1
+
+unevaluatedProperties: false
required:
- compatible
diff --git a/Documentation/devicetree/bindings/rtc/twl-rtc.txt b/Documentation/devicetree/bindings/rtc/twl-rtc.txt
deleted file mode 100644
index 8f9a94f2f8969..0000000000000
--- a/Documentation/devicetree/bindings/rtc/twl-rtc.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-* Texas Instruments TWL4030/6030 RTC
-
-Required properties:
-- compatible : Should be "ti,twl4030-rtc"
-- interrupts : Should be the interrupt number.
-
-Example:
- rtc {
- compatible = "ti,twl4030-rtc";
- interrupts = <11>;
- };
diff --git a/Documentation/devicetree/bindings/watchdog/twl4030-wdt.txt b/Documentation/devicetree/bindings/watchdog/twl4030-wdt.txt
deleted file mode 100644
index 80a37193c0b86..0000000000000
--- a/Documentation/devicetree/bindings/watchdog/twl4030-wdt.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-Device tree bindings for twl4030-wdt driver (TWL4030 watchdog)
-
-Required properties:
- compatible = "ti,twl4030-wdt";
-
-Example:
-
-watchdog {
- compatible = "ti,twl4030-wdt";
-};
--
2.39.2
^ permalink raw reply related
* [PATCH v2 0/8] Add Loongson-2k0500 and Loongson-2k2000 clock support
From: Binbin Zhou @ 2024-04-01 8:23 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
Hi all:
As we know, the Loongson-2K family of SoCs (ls2k0500/ls2k1000/ls2k2000)
have a similar clock structure, and I support them to be configured with
different parameters (e.g., register offsets, etc.).
To make it easier to add support for different SoCs, I refactored the
original driver to make the whole driver as understandable as possible.
Briefly, I have divided all clocks into three categories according to
their properties and their parent clocks: Independent PLLs, clocks based
on frequency scales, and clock dividers.
Thanks.
----
V2:
patch(1/8):
- Drop LOONGSON2_CLK_END, for it is not a binding.
patch(1/8)(3/8)(5/8):
- Add Acked-by tag from Conor, Thanks.
Link to V1:
https://lore.kernel.org/all/cover.1710926402.git.zhoubinbin@loongson.cn/
Binbin Zhou (8):
dt-bindings: clock: add Loongson-2K expand clock index
clk: clk-loongson2: Refactor driver for adding new platforms
dt-bindings: clock: loongson2: add Loongson-2K0500 compatible
clk: clk-loongson2: Add Loongson-2K0500 clock support
dt-bindings: clock: loongson2: add Loongson-2K2000 compatible
clk: clk-loongson2: Add Loongson-2K2000 clock support
LoongArch: dts: Add clock support to Loongson-2K0500
LoongArch: dts: Add clock support to Loongson-2K2000
.../bindings/clock/loongson,ls2k-clk.yaml | 4 +-
.../boot/dts/loongson-2k0500-ref.dts | 4 +
arch/loongarch/boot/dts/loongson-2k0500.dtsi | 57 +-
.../boot/dts/loongson-2k2000-ref.dts | 4 +
arch/loongarch/boot/dts/loongson-2k2000.dtsi | 19 +-
drivers/clk/clk-loongson2.c | 549 ++++++++++--------
include/dt-bindings/clock/loongson,ls2k-clk.h | 56 +-
7 files changed, 408 insertions(+), 285 deletions(-)
--
2.43.0
^ permalink raw reply
* [PATCH v2 2/8] clk: clk-loongson2: Refactor driver for adding new platforms
From: Binbin Zhou @ 2024-04-01 8:23 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
In-Reply-To: <cover.1711504700.git.zhoubinbin@loongson.cn>
The driver only supported loongson-2K1000 at first, but the clock
structure of loongson-2K0500 and loongson-2K2000 are actually similar,
and I tried to refactor the whole driver to adjust to the addition of
the new platform.
Briefly, I have divided all clocks into three categories according to
their properties and their parent clocks: Independent PLLs, clocks based
on frequency scales, and clock dividers.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
drivers/clk/clk-loongson2.c | 459 ++++++++++++++++--------------------
1 file changed, 199 insertions(+), 260 deletions(-)
diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
index bacdcbb287ac..ff2ade6a471a 100644
--- a/drivers/clk/clk-loongson2.c
+++ b/drivers/clk/clk-loongson2.c
@@ -6,6 +6,7 @@
#include <linux/err.h>
#include <linux/init.h>
+#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/module.h>
@@ -13,317 +14,254 @@
#include <linux/io-64-nonatomic-lo-hi.h>
#include <dt-bindings/clock/loongson,ls2k-clk.h>
-#define LOONGSON2_PLL_MULT_SHIFT 32
-#define LOONGSON2_PLL_MULT_WIDTH 10
-#define LOONGSON2_PLL_DIV_SHIFT 26
-#define LOONGSON2_PLL_DIV_WIDTH 6
-#define LOONGSON2_APB_FREQSCALE_SHIFT 20
-#define LOONGSON2_APB_FREQSCALE_WIDTH 3
-#define LOONGSON2_USB_FREQSCALE_SHIFT 16
-#define LOONGSON2_USB_FREQSCALE_WIDTH 3
-#define LOONGSON2_SATA_FREQSCALE_SHIFT 12
-#define LOONGSON2_SATA_FREQSCALE_WIDTH 3
-#define LOONGSON2_BOOT_FREQSCALE_SHIFT 8
-#define LOONGSON2_BOOT_FREQSCALE_WIDTH 3
-
-static void __iomem *loongson2_pll_base;
-
static const struct clk_parent_data pdata[] = {
- { .fw_name = "ref_100m",},
+ { .fw_name = "ref_100m", },
};
-static struct clk_hw *loongson2_clk_register(struct device *dev,
- const char *name,
- const char *parent_name,
- const struct clk_ops *ops,
- unsigned long flags)
-{
- int ret;
- struct clk_hw *hw;
- struct clk_init_data init = { };
-
- hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
- if (!hw)
- return ERR_PTR(-ENOMEM);
-
- init.name = name;
- init.ops = ops;
- init.flags = flags;
- init.num_parents = 1;
-
- if (!parent_name)
- init.parent_data = pdata;
- else
- init.parent_names = &parent_name;
-
- hw->init = &init;
-
- ret = devm_clk_hw_register(dev, hw);
- if (ret)
- hw = ERR_PTR(ret);
-
- return hw;
-}
-
-static unsigned long loongson2_calc_pll_rate(int offset, unsigned long rate)
-{
- u64 val;
- u32 mult, div;
-
- val = readq(loongson2_pll_base + offset);
-
- mult = (val >> LOONGSON2_PLL_MULT_SHIFT) &
- clk_div_mask(LOONGSON2_PLL_MULT_WIDTH);
- div = (val >> LOONGSON2_PLL_DIV_SHIFT) &
- clk_div_mask(LOONGSON2_PLL_DIV_WIDTH);
-
- return div_u64((u64)rate * mult, div);
-}
-
-static unsigned long loongson2_node_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return loongson2_calc_pll_rate(0x0, parent_rate);
-}
-
-static const struct clk_ops loongson2_node_clk_ops = {
- .recalc_rate = loongson2_node_recalc_rate,
+enum loongson2_clk_type {
+ CLK_TYPE_PLL,
+ CLK_TYPE_SCALE,
+ CLK_TYPE_DIVIDER,
+ CLK_TYPE_NONE,
};
-static unsigned long loongson2_ddr_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return loongson2_calc_pll_rate(0x10, parent_rate);
-}
+struct loongson2_clk_provider {
+ void __iomem *base;
+ struct device *dev;
+ struct clk_hw_onecell_data clk_data;
+ spinlock_t clk_lock; /* protect access to DIV registers */
+};
-static const struct clk_ops loongson2_ddr_clk_ops = {
- .recalc_rate = loongson2_ddr_recalc_rate,
+struct loongson2_clk_data {
+ struct clk_hw hw;
+ void __iomem *reg;
+ u8 div_shift;
+ u8 div_width;
+ u8 mult_shift;
+ u8 mult_width;
};
-static unsigned long loongson2_dc_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return loongson2_calc_pll_rate(0x20, parent_rate);
-}
+struct loongson2_clk_board_info {
+ u8 id;
+ enum loongson2_clk_type type;
+ const char *name;
+ const char *parent_name;
+ u8 reg_offset;
+ u8 div_shift;
+ u8 div_width;
+ u8 mult_shift;
+ u8 mult_width;
+};
-static const struct clk_ops loongson2_dc_clk_ops = {
- .recalc_rate = loongson2_dc_recalc_rate,
+#define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \
+ { \
+ .id = _id, \
+ .type = CLK_TYPE_DIVIDER, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .reg_offset = _offset, \
+ .div_shift = _dshift, \
+ .div_width = _dwidth, \
+ }
+
+#define CLK_PLL(_id, _name, _offset, _mshift, _mwidth, \
+ _dshift, _dwidth) \
+ { \
+ .id = _id, \
+ .type = CLK_TYPE_PLL, \
+ .name = _name, \
+ .parent_name = NULL, \
+ .reg_offset = _offset, \
+ .mult_shift = _mshift, \
+ .mult_width = _mwidth, \
+ .div_shift = _dshift, \
+ .div_width = _dwidth, \
+ }
+
+#define CLK_SCALE(_id, _name, _pname, _offset, \
+ _dshift, _dwidth) \
+ { \
+ .id = _id, \
+ .type = CLK_TYPE_SCALE, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .reg_offset = _offset, \
+ .div_shift = _dshift, \
+ .div_width = _dwidth, \
+ }
+
+static const struct loongson2_clk_board_info ls2k1000_clks[] = {
+ CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 32, 10, 26, 6),
+ CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x10, 32, 10, 26, 6),
+ CLK_PLL(LOONGSON2_DC_PLL, "pll_dc", 0x20, 32, 10, 26, 6),
+ CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x30, 32, 10, 26, 6),
+ CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x40, 32, 10, 26, 6),
+ CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "pll_node", 0x8, 0, 6),
+ CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "pll_ddr", 0x18, 0, 6),
+ CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "pll_ddr", 0x18, 22, 6),
+ /*
+ * The hda clk divisor in the upper 32bits and the clk-prodiver
+ * layer code doesn't support 64bit io operation thus a conversion
+ * is required that subtract shift by 32 and add 4byte to the hda
+ * address
+ */
+ CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "pll_ddr", 0x22, 12, 7),
+ CLK_DIV(LOONGSON2_DC_CLK, "clk_dc", "pll_dc", 0x28, 0, 6),
+ CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "pll_dc", 0x28, 22, 6),
+ CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x38, 0, 6),
+ CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x38, 0, 6),
+ CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", NULL, 0x50, 8, 3),
+ CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_gmac", 0x50, 12, 3),
+ CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_gmac", 0x50, 16, 3),
+ CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_gmac", 0x50, 20, 3),
+ { /* Sentinel */ },
};
-static unsigned long loongson2_pix0_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
+static inline struct loongson2_clk_data *to_loongson2_clk(struct clk_hw *hw)
{
- return loongson2_calc_pll_rate(0x30, parent_rate);
+ return container_of(hw, struct loongson2_clk_data, hw);
}
-static const struct clk_ops loongson2_pix0_clk_ops = {
- .recalc_rate = loongson2_pix0_recalc_rate,
-};
-
-static unsigned long loongson2_pix1_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
+static inline unsigned long loongson2_rate_part(u64 val, u8 shift, u8 width)
{
- return loongson2_calc_pll_rate(0x40, parent_rate);
+ return (val & GENMASK(shift + width - 1, shift)) >> shift;
}
-static const struct clk_ops loongson2_pix1_clk_ops = {
- .recalc_rate = loongson2_pix1_recalc_rate,
-};
-
-static unsigned long loongson2_calc_rate(unsigned long rate,
- int shift, int width)
+static unsigned long loongson2_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
{
- u64 val;
- u32 mult;
-
- val = readq(loongson2_pll_base + 0x50);
+ u64 val, mult, div;
+ struct loongson2_clk_data *clk = to_loongson2_clk(hw);
- mult = (val >> shift) & clk_div_mask(width);
+ val = readq(clk->reg);
+ mult = loongson2_rate_part(val, clk->mult_shift, clk->mult_width);
+ div = loongson2_rate_part(val, clk->div_shift, clk->div_width);
- return div_u64((u64)rate * (mult + 1), 8);
-}
-
-static unsigned long loongson2_boot_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return loongson2_calc_rate(parent_rate,
- LOONGSON2_BOOT_FREQSCALE_SHIFT,
- LOONGSON2_BOOT_FREQSCALE_WIDTH);
+ return div_u64((u64)parent_rate * mult, div);
}
-static const struct clk_ops loongson2_boot_clk_ops = {
- .recalc_rate = loongson2_boot_recalc_rate,
+static const struct clk_ops loongson2_pll_recalc_ops = {
+ .recalc_rate = loongson2_pll_recalc_rate,
};
-static unsigned long loongson2_apb_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
+static unsigned long loongson2_freqscale_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
{
- return loongson2_calc_rate(parent_rate,
- LOONGSON2_APB_FREQSCALE_SHIFT,
- LOONGSON2_APB_FREQSCALE_WIDTH);
-}
+ u64 val, mult;
+ struct loongson2_clk_data *clk = to_loongson2_clk(hw);
-static const struct clk_ops loongson2_apb_clk_ops = {
- .recalc_rate = loongson2_apb_recalc_rate,
-};
+ val = readq(clk->reg);
+ mult = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;
-static unsigned long loongson2_usb_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return loongson2_calc_rate(parent_rate,
- LOONGSON2_USB_FREQSCALE_SHIFT,
- LOONGSON2_USB_FREQSCALE_WIDTH);
+ return div_u64((u64)parent_rate * mult, 8);
}
-static const struct clk_ops loongson2_usb_clk_ops = {
- .recalc_rate = loongson2_usb_recalc_rate,
+static const struct clk_ops loongson2_freqscale_recalc_ops = {
+ .recalc_rate = loongson2_freqscale_recalc_rate,
};
-static unsigned long loongson2_sata_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
+static struct clk_hw *loongson2_clk_register(struct loongson2_clk_provider *clp,
+ const struct loongson2_clk_board_info *cld,
+ const struct clk_ops *ops)
{
- return loongson2_calc_rate(parent_rate,
- LOONGSON2_SATA_FREQSCALE_SHIFT,
- LOONGSON2_SATA_FREQSCALE_WIDTH);
-}
+ int ret;
+ struct clk_hw *hw;
+ struct loongson2_clk_data *clk;
+ struct clk_init_data init = { };
-static const struct clk_ops loongson2_sata_clk_ops = {
- .recalc_rate = loongson2_sata_recalc_rate,
-};
+ clk = devm_kzalloc(clp->dev, sizeof(*clk), GFP_KERNEL);
+ if (!clk)
+ return ERR_PTR(-ENOMEM);
-static inline int loongson2_check_clk_hws(struct clk_hw *clks[], unsigned int count)
-{
- unsigned int i;
+ init.name = cld->name;
+ init.ops = ops;
+ init.flags = 0;
+ init.num_parents = 1;
- for (i = 0; i < count; i++)
- if (IS_ERR(clks[i])) {
- pr_err("Loongson2 clk %u: register failed with %ld\n",
- i, PTR_ERR(clks[i]));
- return PTR_ERR(clks[i]);
- }
+ if (!cld->parent_name)
+ init.parent_data = pdata;
+ else
+ init.parent_names = &cld->parent_name;
+
+ clk->reg = clp->base + cld->reg_offset;
+ clk->div_shift = cld->div_shift;
+ clk->div_width = cld->div_width;
+ clk->mult_shift = cld->mult_shift;
+ clk->mult_width = cld->mult_width;
+ clk->hw.init = &init;
- return 0;
+ hw = &clk->hw;
+ ret = devm_clk_hw_register(clp->dev, hw);
+ if (ret)
+ clk = ERR_PTR(ret);
+
+ return hw;
}
static int loongson2_clk_probe(struct platform_device *pdev)
{
- int ret;
- struct clk_hw **hws;
- struct clk_hw_onecell_data *clk_hw_data;
- spinlock_t loongson2_clk_lock;
+ int i, clks_num = 0;
+ struct clk_hw *hw;
struct device *dev = &pdev->dev;
+ struct loongson2_clk_provider *clp;
+ const struct loongson2_clk_board_info *p, *data;
- loongson2_pll_base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(loongson2_pll_base))
- return PTR_ERR(loongson2_pll_base);
-
- clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, LOONGSON2_CLK_END),
- GFP_KERNEL);
- if (WARN_ON(!clk_hw_data))
- return -ENOMEM;
-
- clk_hw_data->num = LOONGSON2_CLK_END;
- hws = clk_hw_data->hws;
-
- hws[LOONGSON2_NODE_PLL] = loongson2_clk_register(dev, "node_pll",
- NULL,
- &loongson2_node_clk_ops, 0);
-
- hws[LOONGSON2_DDR_PLL] = loongson2_clk_register(dev, "ddr_pll",
- NULL,
- &loongson2_ddr_clk_ops, 0);
+ data = device_get_match_data(dev);
+ if (!data)
+ return -EINVAL;
- hws[LOONGSON2_DC_PLL] = loongson2_clk_register(dev, "dc_pll",
- NULL,
- &loongson2_dc_clk_ops, 0);
+ for (p = data; p->name; p++)
+ clks_num++;
- hws[LOONGSON2_PIX0_PLL] = loongson2_clk_register(dev, "pix0_pll",
- NULL,
- &loongson2_pix0_clk_ops, 0);
-
- hws[LOONGSON2_PIX1_PLL] = loongson2_clk_register(dev, "pix1_pll",
- NULL,
- &loongson2_pix1_clk_ops, 0);
+ clp = devm_kzalloc(dev, struct_size(clp, clk_data.hws, clks_num),
+ GFP_KERNEL);
+ if (!clp)
+ return -ENOMEM;
- hws[LOONGSON2_BOOT_CLK] = loongson2_clk_register(dev, "boot",
- NULL,
- &loongson2_boot_clk_ops, 0);
+ clp->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(clp->base))
+ return PTR_ERR(clp->base);
+
+ spin_lock_init(&clp->clk_lock);
+ clp->clk_data.num = clks_num + 1;
+ clp->dev = dev;
+
+ for (i = 0; i < clks_num; i++) {
+ p = &data[i];
+ switch (p->type) {
+ case CLK_TYPE_PLL:
+ hw = loongson2_clk_register(clp, p,
+ &loongson2_pll_recalc_ops);
+ break;
+ case CLK_TYPE_SCALE:
+ hw = loongson2_clk_register(clp, p,
+ &loongson2_freqscale_recalc_ops);
+ break;
+ case CLK_TYPE_DIVIDER:
+ hw = devm_clk_hw_register_divider(dev, p->name,
+ p->parent_name, 0,
+ clp->base + p->reg_offset,
+ p->div_shift, p->div_width,
+ CLK_DIVIDER_ONE_BASED,
+ &clp->clk_lock);
+ break;
+ default:
+ return dev_err_probe(dev, -EINVAL, "Invalid clk type\n");
+ }
- hws[LOONGSON2_NODE_CLK] = devm_clk_hw_register_divider(dev, "node",
- "node_pll", 0,
- loongson2_pll_base + 0x8, 0,
- 6, CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
+ if (IS_ERR(hw))
+ return dev_err_probe(dev, PTR_ERR(hw),
+ "Register clk: %s, type: %u failed!\n",
+ p->name, p->type);
- /*
- * The hda clk divisor in the upper 32bits and the clk-prodiver
- * layer code doesn't support 64bit io operation thus a conversion
- * is required that subtract shift by 32 and add 4byte to the hda
- * address
- */
- hws[LOONGSON2_HDA_CLK] = devm_clk_hw_register_divider(dev, "hda",
- "ddr_pll", 0,
- loongson2_pll_base + 0x22, 12,
- 7, CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
-
- hws[LOONGSON2_GPU_CLK] = devm_clk_hw_register_divider(dev, "gpu",
- "ddr_pll", 0,
- loongson2_pll_base + 0x18, 22,
- 6, CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
-
- hws[LOONGSON2_DDR_CLK] = devm_clk_hw_register_divider(dev, "ddr",
- "ddr_pll", 0,
- loongson2_pll_base + 0x18, 0,
- 6, CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
-
- hws[LOONGSON2_GMAC_CLK] = devm_clk_hw_register_divider(dev, "gmac",
- "dc_pll", 0,
- loongson2_pll_base + 0x28, 22,
- 6, CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
-
- hws[LOONGSON2_DC_CLK] = devm_clk_hw_register_divider(dev, "dc",
- "dc_pll", 0,
- loongson2_pll_base + 0x28, 0,
- 6, CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
-
- hws[LOONGSON2_APB_CLK] = loongson2_clk_register(dev, "apb",
- "gmac",
- &loongson2_apb_clk_ops, 0);
-
- hws[LOONGSON2_USB_CLK] = loongson2_clk_register(dev, "usb",
- "gmac",
- &loongson2_usb_clk_ops, 0);
-
- hws[LOONGSON2_SATA_CLK] = loongson2_clk_register(dev, "sata",
- "gmac",
- &loongson2_sata_clk_ops, 0);
-
- hws[LOONGSON2_PIX0_CLK] = clk_hw_register_divider(NULL, "pix0",
- "pix0_pll", 0,
- loongson2_pll_base + 0x38, 0, 6,
- CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
-
- hws[LOONGSON2_PIX1_CLK] = clk_hw_register_divider(NULL, "pix1",
- "pix1_pll", 0,
- loongson2_pll_base + 0x48, 0, 6,
- CLK_DIVIDER_ONE_BASED,
- &loongson2_clk_lock);
-
- ret = loongson2_check_clk_hws(hws, LOONGSON2_CLK_END);
- if (ret)
- return ret;
+ clp->clk_data.hws[p->id] = hw;
+ }
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data);
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clp->clk_data);
}
static const struct of_device_id loongson2_clk_match_table[] = {
- { .compatible = "loongson,ls2k-clk" },
+ { .compatible = "loongson,ls2k-clk", .data = &ls2k1000_clks },
{ }
};
MODULE_DEVICE_TABLE(of, loongson2_clk_match_table);
@@ -338,4 +276,5 @@ static struct platform_driver loongson2_clk_driver = {
module_platform_driver(loongson2_clk_driver);
MODULE_DESCRIPTION("Loongson2 clock driver");
+MODULE_AUTHOR("Loongson Technology Corporation Limited");
MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply related
* [PATCH v2 1/8] dt-bindings: clock: add Loongson-2K expand clock index
From: Binbin Zhou @ 2024-04-01 8:23 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou, Conor Dooley
In-Reply-To: <cover.1711504700.git.zhoubinbin@loongson.cn>
In the new Loongson-2K family of SoCs, more clock indexes are needed,
such as clock gates.
The patch adds these clock indexes
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
include/dt-bindings/clock/loongson,ls2k-clk.h | 56 ++++++++++++-------
1 file changed, 37 insertions(+), 19 deletions(-)
diff --git a/include/dt-bindings/clock/loongson,ls2k-clk.h b/include/dt-bindings/clock/loongson,ls2k-clk.h
index 3bc4dfc193c2..4e6811eca8c6 100644
--- a/include/dt-bindings/clock/loongson,ls2k-clk.h
+++ b/include/dt-bindings/clock/loongson,ls2k-clk.h
@@ -7,24 +7,42 @@
#ifndef __DT_BINDINGS_CLOCK_LOONGSON2_H
#define __DT_BINDINGS_CLOCK_LOONGSON2_H
-#define LOONGSON2_REF_100M 0
-#define LOONGSON2_NODE_PLL 1
-#define LOONGSON2_DDR_PLL 2
-#define LOONGSON2_DC_PLL 3
-#define LOONGSON2_PIX0_PLL 4
-#define LOONGSON2_PIX1_PLL 5
-#define LOONGSON2_NODE_CLK 6
-#define LOONGSON2_HDA_CLK 7
-#define LOONGSON2_GPU_CLK 8
-#define LOONGSON2_DDR_CLK 9
-#define LOONGSON2_GMAC_CLK 10
-#define LOONGSON2_DC_CLK 11
-#define LOONGSON2_APB_CLK 12
-#define LOONGSON2_USB_CLK 13
-#define LOONGSON2_SATA_CLK 14
-#define LOONGSON2_PIX0_CLK 15
-#define LOONGSON2_PIX1_CLK 16
-#define LOONGSON2_BOOT_CLK 17
-#define LOONGSON2_CLK_END 18
+#define LOONGSON2_REF_100M 0
+#define LOONGSON2_NODE_PLL 1
+#define LOONGSON2_DDR_PLL 2
+#define LOONGSON2_DC_PLL 3
+#define LOONGSON2_PIX0_PLL 4
+#define LOONGSON2_PIX1_PLL 5
+#define LOONGSON2_NODE_CLK 6
+#define LOONGSON2_HDA_CLK 7
+#define LOONGSON2_GPU_CLK 8
+#define LOONGSON2_DDR_CLK 9
+#define LOONGSON2_GMAC_CLK 10
+#define LOONGSON2_DC_CLK 11
+#define LOONGSON2_APB_CLK 12
+#define LOONGSON2_USB_CLK 13
+#define LOONGSON2_SATA_CLK 14
+#define LOONGSON2_PIX0_CLK 15
+#define LOONGSON2_PIX1_CLK 16
+#define LOONGSON2_BOOT_CLK 17
+
+/* Loongson-2K2000 */
+#define LOONGSON2_OUT0_GATE 18
+#define LOONGSON2_GMAC_GATE 19
+#define LOONGSON2_RIO_GATE 20
+#define LOONGSON2_DC_GATE 21
+#define LOONGSON2_GPU_GATE 22
+#define LOONGSON2_DDR_GATE 23
+#define LOONGSON2_HDA_GATE 24
+#define LOONGSON2_NODE_GATE 25
+#define LOONGSON2_EMMC_GATE 26
+#define LOONGSON2_PIX0_GATE 27
+#define LOONGSON2_PIX1_GATE 28
+#define LOONGSON2_OUT0_CLK 29
+#define LOONGSON2_RIO_CLK 30
+#define LOONGSON2_EMMC_CLK 31
+#define LOONGSON2_DES_CLK 32
+#define LOONGSON2_I2S_CLK 33
+#define LOONGSON2_MISC_CLK 34
#endif
--
2.43.0
^ permalink raw reply related
* [PATCH v2 3/8] dt-bindings: clock: loongson2: add Loongson-2K0500 compatible
From: Binbin Zhou @ 2024-04-01 8:23 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou, Conor Dooley
In-Reply-To: <cover.1711504700.git.zhoubinbin@loongson.cn>
Add the devicetree compatible for Loongson-2K0500 clocks.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
index 63a59015987e..83baee40e200 100644
--- a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
@@ -16,7 +16,8 @@ description: |
properties:
compatible:
enum:
- - loongson,ls2k-clk
+ - loongson,ls2k0500-clk
+ - loongson,ls2k-clk # This is for Loongson-2K1000
reg:
maxItems: 1
--
2.43.0
^ permalink raw reply related
* [PATCH v2 4/8] clk: clk-loongson2: Add Loongson-2K0500 clock support
From: Binbin Zhou @ 2024-04-01 8:24 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
In-Reply-To: <cover.1711504700.git.zhoubinbin@loongson.cn>
The Loongson-2K0500 and Loongson-2K1000 clock is similar, we add its
support by different configurations.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
drivers/clk/clk-loongson2.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
index ff2ade6a471a..b5dd9d028826 100644
--- a/drivers/clk/clk-loongson2.c
+++ b/drivers/clk/clk-loongson2.c
@@ -90,6 +90,27 @@ struct loongson2_clk_board_info {
.div_width = _dwidth, \
}
+static const struct loongson2_clk_board_info ls2k0500_clks[] = {
+ CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6),
+ CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x8, 16, 8, 8, 6),
+ CLK_PLL(LOONGSON2_DC_PLL, "pll_soc", 0x10, 16, 8, 8, 6),
+ CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x18, 16, 8, 8, 6),
+ CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x20, 16, 8, 8, 6),
+ CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "pll_node", 0, 24, 6),
+ CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "pll_ddr", 0x8, 24, 6),
+ CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "pll_ddr", 0xc, 8, 6),
+ CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "pll_soc", 0x10, 24, 6),
+ CLK_DIV(LOONGSON2_DC_CLK, "clk_sb", "pll_soc", 0x14, 0, 6),
+ CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "pll_soc", 0x14, 8, 6),
+ CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x18, 24, 6),
+ CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x20, 24, 6),
+ CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", "clk_sb", 0x28, 8, 3),
+ CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_sb", 0x28, 12, 3),
+ CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_sb", 0x28, 16, 3),
+ CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_sb", 0x28, 20, 3),
+ { /* Sentinel */ },
+};
+
static const struct loongson2_clk_board_info ls2k1000_clks[] = {
CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 32, 10, 26, 6),
CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x10, 32, 10, 26, 6),
@@ -261,6 +282,7 @@ static int loongson2_clk_probe(struct platform_device *pdev)
}
static const struct of_device_id loongson2_clk_match_table[] = {
+ { .compatible = "loongson,ls2k0500-clk", .data = &ls2k0500_clks },
{ .compatible = "loongson,ls2k-clk", .data = &ls2k1000_clks },
{ }
};
--
2.43.0
^ permalink raw reply related
* [PATCH v2 5/8] dt-bindings: clock: loongson2: add Loongson-2K2000 compatible
From: Binbin Zhou @ 2024-04-01 8:24 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou, Conor Dooley
In-Reply-To: <cover.1711504700.git.zhoubinbin@loongson.cn>
Add the devicetree compatible for Loongson-2K2000 clocks.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
index 83baee40e200..4f79cdb417ab 100644
--- a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml
@@ -18,6 +18,7 @@ properties:
enum:
- loongson,ls2k0500-clk
- loongson,ls2k-clk # This is for Loongson-2K1000
+ - loongson,ls2k2000-clk
reg:
maxItems: 1
--
2.43.0
^ permalink raw reply related
* [PATCH v2 6/8] clk: clk-loongson2: Add Loongson-2K2000 clock support
From: Binbin Zhou @ 2024-04-01 8:24 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
In-Reply-To: <cover.1711504700.git.zhoubinbin@loongson.cn>
The Loongson-2K2000 and Loongson-2K1000 clock is similar, we add its
support by different configurations.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
drivers/clk/clk-loongson2.c | 72 +++++++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
index b5dd9d028826..0d82aeeadb45 100644
--- a/drivers/clk/clk-loongson2.c
+++ b/drivers/clk/clk-loongson2.c
@@ -22,6 +22,8 @@ enum loongson2_clk_type {
CLK_TYPE_PLL,
CLK_TYPE_SCALE,
CLK_TYPE_DIVIDER,
+ CLK_TYPE_GATE,
+ CLK_TYPE_FIXED,
CLK_TYPE_NONE,
};
@@ -46,11 +48,13 @@ struct loongson2_clk_board_info {
enum loongson2_clk_type type;
const char *name;
const char *parent_name;
+ unsigned long fixed_rate;
u8 reg_offset;
u8 div_shift;
u8 div_width;
u8 mult_shift;
u8 mult_width;
+ u8 bit_idx;
};
#define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \
@@ -90,6 +94,25 @@ struct loongson2_clk_board_info {
.div_width = _dwidth, \
}
+#define CLK_GATE(_id, _name, _pname, _offset, _bidx) \
+ { \
+ .id = _id, \
+ .type = CLK_TYPE_GATE, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .reg_offset = _offset, \
+ .bit_idx = _bidx, \
+ }
+
+#define CLK_FIXED(_id, _name, _pname, _rate) \
+ { \
+ .id = _id, \
+ .type = CLK_TYPE_FIXED, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .fixed_rate = _rate, \
+ }
+
static const struct loongson2_clk_board_info ls2k0500_clks[] = {
CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6),
CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x8, 16, 8, 8, 6),
@@ -138,6 +161,44 @@ static const struct loongson2_clk_board_info ls2k1000_clks[] = {
{ /* Sentinel */ },
};
+static const struct loongson2_clk_board_info ls2k2000_clks[] = {
+ CLK_PLL(LOONGSON2_DC_PLL, "pll_0", 0, 21, 9, 32, 6),
+ CLK_PLL(LOONGSON2_DDR_PLL, "pll_1", 0x10, 21, 9, 32, 6),
+ CLK_PLL(LOONGSON2_NODE_PLL, "pll_2", 0x20, 21, 9, 32, 6),
+ CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x30, 21, 9, 32, 6),
+ CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x40, 21, 9, 32, 6),
+ CLK_GATE(LOONGSON2_OUT0_GATE, "out0_gate", "pll_0", 0, 40),
+ CLK_GATE(LOONGSON2_GMAC_GATE, "gmac_gate", "pll_0", 0, 41),
+ CLK_GATE(LOONGSON2_RIO_GATE, "rio_gate", "pll_0", 0, 42),
+ CLK_GATE(LOONGSON2_DC_GATE, "dc_gate", "pll_1", 0x10, 40),
+ CLK_GATE(LOONGSON2_DDR_GATE, "ddr_gate", "pll_1", 0x10, 41),
+ CLK_GATE(LOONGSON2_GPU_GATE, "gpu_gate", "pll_1", 0x10, 42),
+ CLK_GATE(LOONGSON2_HDA_GATE, "hda_gate", "pll_2", 0x20, 40),
+ CLK_GATE(LOONGSON2_NODE_GATE, "node_gate", "pll_2", 0x20, 41),
+ CLK_GATE(LOONGSON2_EMMC_GATE, "emmc_gate", "pll_2", 0x20, 42),
+ CLK_GATE(LOONGSON2_PIX0_GATE, "pix0_gate", "pll_pix0", 0x30, 40),
+ CLK_GATE(LOONGSON2_PIX1_GATE, "pix1_gate", "pll_pix1", 0x40, 40),
+ CLK_DIV(LOONGSON2_OUT0_CLK, "clk_out0", "out0_gate", 0, 0, 6),
+ CLK_DIV(LOONGSON2_GMAC_CLK, "clk_gmac", "gmac_gate", 0, 7, 6),
+ CLK_DIV(LOONGSON2_RIO_CLK, "clk_rio", "rio_gate", 0, 14, 6),
+ CLK_DIV(LOONGSON2_DC_CLK, "clk_dc", "dc_gate", 0x10, 0, 6),
+ CLK_DIV(LOONGSON2_GPU_CLK, "clk_gpu", "gpu_gate", 0x10, 7, 6),
+ CLK_DIV(LOONGSON2_DDR_CLK, "clk_ddr", "ddr_gate", 0x10, 14, 6),
+ CLK_DIV(LOONGSON2_HDA_CLK, "clk_hda", "hda_gate", 0x20, 0, 6),
+ CLK_DIV(LOONGSON2_NODE_CLK, "clk_node", "node_gate", 0x20, 7, 6),
+ CLK_DIV(LOONGSON2_EMMC_CLK, "clk_emmc", "emmc_gate", 0x20, 14, 6),
+ CLK_DIV(LOONGSON2_PIX0_CLK, "clk_pix0", "pll_pix0", 0x30, 0, 6),
+ CLK_DIV(LOONGSON2_PIX1_CLK, "clk_pix1", "pll_pix1", 0x40, 0, 6),
+ CLK_SCALE(LOONGSON2_SATA_CLK, "clk_sata", "clk_out0", 0x50, 12, 3),
+ CLK_SCALE(LOONGSON2_USB_CLK, "clk_usb", "clk_out0", 0x50, 16, 3),
+ CLK_SCALE(LOONGSON2_APB_CLK, "clk_apb", "clk_node", 0x50, 20, 3),
+ CLK_SCALE(LOONGSON2_BOOT_CLK, "clk_boot", NULL, 0x50, 23, 3),
+ CLK_SCALE(LOONGSON2_DES_CLK, "clk_des", "clk_node", 0x50, 40, 3),
+ CLK_SCALE(LOONGSON2_I2S_CLK, "clk_i2s", "clk_node", 0x50, 44, 3),
+ CLK_FIXED(LOONGSON2_MISC_CLK, "clk_misc", NULL, 50000000),
+ { /* Sentinel */ },
+};
+
static inline struct loongson2_clk_data *to_loongson2_clk(struct clk_hw *hw)
{
return container_of(hw, struct loongson2_clk_data, hw);
@@ -266,6 +327,16 @@ static int loongson2_clk_probe(struct platform_device *pdev)
CLK_DIVIDER_ONE_BASED,
&clp->clk_lock);
break;
+ case CLK_TYPE_GATE:
+ hw = devm_clk_hw_register_gate(dev, p->name, p->parent_name, 0,
+ clp->base + p->reg_offset,
+ p->bit_idx, 0,
+ &clp->clk_lock);
+ break;
+ case CLK_TYPE_FIXED:
+ hw = clk_hw_register_fixed_rate_parent_data(dev, p->name, pdata,
+ 0, p->fixed_rate);
+ break;
default:
return dev_err_probe(dev, -EINVAL, "Invalid clk type\n");
}
@@ -284,6 +355,7 @@ static int loongson2_clk_probe(struct platform_device *pdev)
static const struct of_device_id loongson2_clk_match_table[] = {
{ .compatible = "loongson,ls2k0500-clk", .data = &ls2k0500_clks },
{ .compatible = "loongson,ls2k-clk", .data = &ls2k1000_clks },
+ { .compatible = "loongson,ls2k2000-clk", .data = &ls2k2000_clks },
{ }
};
MODULE_DEVICE_TABLE(of, loongson2_clk_match_table);
--
2.43.0
^ permalink raw reply related
* [PATCH v2 7/8] LoongArch: dts: Add clock support to Loongson-2K0500
From: Binbin Zhou @ 2024-04-01 8:24 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
In-Reply-To: <cover.1711504700.git.zhoubinbin@loongson.cn>
The module is supported, enable it.
Also, add the dma node associated with it.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
.../boot/dts/loongson-2k0500-ref.dts | 4 ++
arch/loongarch/boot/dts/loongson-2k0500.dtsi | 57 ++++++++++++++++++-
2 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/arch/loongarch/boot/dts/loongson-2k0500-ref.dts b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
index 8aefb0c12672..62dad6297e82 100644
--- a/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
+++ b/arch/loongarch/boot/dts/loongson-2k0500-ref.dts
@@ -41,6 +41,10 @@ linux,cma {
};
};
+&clk {
+ status = "okay";
+};
+
&gmac0 {
status = "okay";
diff --git a/arch/loongarch/boot/dts/loongson-2k0500.dtsi b/arch/loongarch/boot/dts/loongson-2k0500.dtsi
index 444779c21034..413b83366367 100644
--- a/arch/loongarch/boot/dts/loongson-2k0500.dtsi
+++ b/arch/loongarch/boot/dts/loongson-2k0500.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/loongson,ls2k-clk.h>
/ {
#address-cells = <2>;
@@ -19,14 +20,15 @@ cpu0: cpu@0 {
compatible = "loongson,la264";
device_type = "cpu";
reg = <0x0>;
- clocks = <&cpu_clk>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
};
};
- cpu_clk: cpu-clk {
+ ref_100m: clock-ref-100m {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <500000000>;
+ clock-frequency = <100000000>;
+ clock-output-names = "ref_100m";
};
cpuintc: interrupt-controller {
@@ -52,6 +54,55 @@ isa@16400000 {
ranges = <1 0x0 0x0 0x16400000 0x4000>;
};
+ clk: clock-controller@1fe10400 {
+ compatible = "loongson,ls2k0500-clk";
+ reg = <0x0 0x1fe10400 0x0 0x2c>;
+ #clock-cells = <1>;
+ clocks = <&ref_100m>;
+ clock-names = "ref_100m";
+ status = "disabled";
+ };
+
+ dma-controller@1fe10c00 {
+ compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
+ reg = <0 0x1fe10c00 0 0x8>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <67>;
+ clocks = <&clk LOONGSON2_APB_CLK>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
+ dma-controller@1fe10c10 {
+ compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
+ reg = <0 0x1fe10c10 0 0x8>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <68>;
+ clocks = <&clk LOONGSON2_APB_CLK>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
+ dma-controller@1fe10c20 {
+ compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
+ reg = <0 0x1fe10c20 0 0x8>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <69>;
+ clocks = <&clk LOONGSON2_APB_CLK>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
+ dma-controller@1fe10c30 {
+ compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
+ reg = <0 0x1fe10c30 0 0x8>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <70>;
+ clocks = <&clk LOONGSON2_APB_CLK>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
liointc0: interrupt-controller@1fe11400 {
compatible = "loongson,liointc-2.0";
reg = <0x0 0x1fe11400 0x0 0x40>,
--
2.43.0
^ permalink raw reply related
* [PATCH v2 8/8] LoongArch: dts: Add clock support to Loongson-2K2000
From: Binbin Zhou @ 2024-04-01 8:24 UTC (permalink / raw)
To: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu
Cc: Huacai Chen, loongson-kernel, linux-clk, devicetree, Xuerui Wang,
loongarch, Binbin Zhou
In-Reply-To: <cover.1711504700.git.zhoubinbin@loongson.cn>
The module is supported, enable it.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
.../boot/dts/loongson-2k2000-ref.dts | 4 ++++
arch/loongarch/boot/dts/loongson-2k2000.dtsi | 19 +++++++++++++++----
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/loongarch/boot/dts/loongson-2k2000-ref.dts b/arch/loongarch/boot/dts/loongson-2k2000-ref.dts
index dca91caf895e..a7af345b30ea 100644
--- a/arch/loongarch/boot/dts/loongson-2k2000-ref.dts
+++ b/arch/loongarch/boot/dts/loongson-2k2000-ref.dts
@@ -39,6 +39,10 @@ linux,cma {
};
};
+&clk {
+ status = "okay";
+};
+
&sata {
status = "okay";
};
diff --git a/arch/loongarch/boot/dts/loongson-2k2000.dtsi b/arch/loongarch/boot/dts/loongson-2k2000.dtsi
index a231949b5f55..605efaba7292 100644
--- a/arch/loongarch/boot/dts/loongson-2k2000.dtsi
+++ b/arch/loongarch/boot/dts/loongson-2k2000.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/loongson,ls2k-clk.h>
/ {
#address-cells = <2>;
@@ -19,21 +20,22 @@ cpu0: cpu@1 {
compatible = "loongson,la364";
device_type = "cpu";
reg = <0x0>;
- clocks = <&cpu_clk>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
};
cpu1: cpu@2 {
compatible = "loongson,la364";
device_type = "cpu";
reg = <0x1>;
- clocks = <&cpu_clk>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
};
};
- cpu_clk: cpu-clk {
+ ref_100m: clock-ref-100m {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <1400000000>;
+ clock-frequency = <100000000>;
+ clock-output-names = "ref_100m";
};
cpuintc: interrupt-controller {
@@ -51,6 +53,15 @@ bus@10000000 {
#address-cells = <2>;
#size-cells = <2>;
+ clk: clock-controller@10010480 {
+ compatible = "loongson,ls2k2000-clk";
+ reg = <0x0 0x10010480 0x0 0x100>;
+ #clock-cells = <1>;
+ clocks = <&ref_100m>;
+ clock-names = "ref_100m";
+ status = "disabled";
+ };
+
pmc: power-management@100d0000 {
compatible = "loongson,ls2k2000-pmc", "loongson,ls2k0500-pmc", "syscon";
reg = <0x0 0x100d0000 0x0 0x58>;
--
2.43.0
^ permalink raw reply related
* [PATCH v8 2/3] dt-bindings: input: qcom,pm8xxx-vib: add new SPMI vibrator module
From: Fenglin Wu via B4 Relay @ 2024-04-01 8:38 UTC (permalink / raw)
To: kernel, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Dmitry Torokhov, Rob Herring, Krzysztof Kozlowski,
Dmitry Baryshkov
Cc: linux-arm-msm, linux-input, linux-kernel, devicetree, Fenglin Wu,
Krzysztof Kozlowski
In-Reply-To: <20240401-pm8xxx-vibrator-new-design-v8-0-6f2b8b03b4c7@quicinc.com>
From: Fenglin Wu <quic_fenglinw@quicinc.com>
Add compatible strings to support vibrator module inside PMI632,
PMI7250B, PM7325B, PM7550BA.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Fenglin Wu <quic_fenglinw@quicinc.com>
---
.../devicetree/bindings/input/qcom,pm8xxx-vib.yaml | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/input/qcom,pm8xxx-vib.yaml b/Documentation/devicetree/bindings/input/qcom,pm8xxx-vib.yaml
index c8832cd0d7da..2025d6a5423e 100644
--- a/Documentation/devicetree/bindings/input/qcom,pm8xxx-vib.yaml
+++ b/Documentation/devicetree/bindings/input/qcom,pm8xxx-vib.yaml
@@ -11,10 +11,18 @@ maintainers:
properties:
compatible:
- enum:
- - qcom,pm8058-vib
- - qcom,pm8916-vib
- - qcom,pm8921-vib
+ oneOf:
+ - enum:
+ - qcom,pm8058-vib
+ - qcom,pm8916-vib
+ - qcom,pm8921-vib
+ - qcom,pmi632-vib
+ - items:
+ - enum:
+ - qcom,pm7250b-vib
+ - qcom,pm7325b-vib
+ - qcom,pm7550ba-vib
+ - const: qcom,pmi632-vib
reg:
maxItems: 1
--
2.25.1
^ permalink raw reply related
* [PATCH v8 1/3] input: pm8xxx-vibrator: refactor to support new SPMI vibrator
From: Fenglin Wu via B4 Relay @ 2024-04-01 8:38 UTC (permalink / raw)
To: kernel, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Dmitry Torokhov, Rob Herring, Krzysztof Kozlowski,
Dmitry Baryshkov
Cc: linux-arm-msm, linux-input, linux-kernel, devicetree, Fenglin Wu
In-Reply-To: <20240401-pm8xxx-vibrator-new-design-v8-0-6f2b8b03b4c7@quicinc.com>
From: Fenglin Wu <quic_fenglinw@quicinc.com>
Currently, vibrator control register addresses are hard coded,
including the base address and offsets, it's not flexible to
support new SPMI vibrator module which is usually included in
different PMICs with different base address. Refactor it by using
the base address defined in devicetree.
Signed-off-by: Fenglin Wu <quic_fenglinw@quicinc.com>
---
drivers/input/misc/pm8xxx-vibrator.c | 40 ++++++++++++++++++++++++------------
1 file changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/input/misc/pm8xxx-vibrator.c b/drivers/input/misc/pm8xxx-vibrator.c
index 04cb87efd799..3b6a2e949f30 100644
--- a/drivers/input/misc/pm8xxx-vibrator.c
+++ b/drivers/input/misc/pm8xxx-vibrator.c
@@ -19,26 +19,26 @@
#define MAX_FF_SPEED 0xff
struct pm8xxx_regs {
- unsigned int enable_addr;
+ unsigned int enable_offset;
unsigned int enable_mask;
- unsigned int drv_addr;
+ unsigned int drv_offset;
unsigned int drv_mask;
unsigned int drv_shift;
unsigned int drv_en_manual_mask;
};
static const struct pm8xxx_regs pm8058_regs = {
- .drv_addr = 0x4A,
+ .drv_offset = 0x4A,
.drv_mask = 0xf8,
.drv_shift = 3,
.drv_en_manual_mask = 0xfc,
};
static struct pm8xxx_regs pm8916_regs = {
- .enable_addr = 0xc046,
+ .enable_offset = 0x46,
.enable_mask = BIT(7),
- .drv_addr = 0xc041,
+ .drv_offset = 0x41,
.drv_mask = 0x1F,
.drv_shift = 0,
.drv_en_manual_mask = 0,
@@ -50,6 +50,8 @@ static struct pm8xxx_regs pm8916_regs = {
* @work: work structure to set the vibration parameters
* @regmap: regmap for register read/write
* @regs: registers' info
+ * @enable_addr: vibrator enable register
+ * @drv_addr: vibrator drive strength register
* @speed: speed of vibration set from userland
* @active: state of vibrator
* @level: level of vibration to set in the chip
@@ -60,6 +62,8 @@ struct pm8xxx_vib {
struct work_struct work;
struct regmap *regmap;
const struct pm8xxx_regs *regs;
+ unsigned int enable_addr;
+ unsigned int drv_addr;
int speed;
int level;
bool active;
@@ -82,14 +86,14 @@ static int pm8xxx_vib_set(struct pm8xxx_vib *vib, bool on)
else
val &= ~regs->drv_mask;
- rc = regmap_write(vib->regmap, regs->drv_addr, val);
+ rc = regmap_write(vib->regmap, vib->drv_addr, val);
if (rc < 0)
return rc;
vib->reg_vib_drv = val;
if (regs->enable_mask)
- rc = regmap_update_bits(vib->regmap, regs->enable_addr,
+ rc = regmap_update_bits(vib->regmap, vib->enable_addr,
regs->enable_mask, on ? ~0 : 0);
return rc;
@@ -102,11 +106,10 @@ static int pm8xxx_vib_set(struct pm8xxx_vib *vib, bool on)
static void pm8xxx_work_handler(struct work_struct *work)
{
struct pm8xxx_vib *vib = container_of(work, struct pm8xxx_vib, work);
- const struct pm8xxx_regs *regs = vib->regs;
- int rc;
unsigned int val;
+ int rc;
- rc = regmap_read(vib->regmap, regs->drv_addr, &val);
+ rc = regmap_read(vib->regmap, vib->drv_addr, &val);
if (rc < 0)
return;
@@ -169,7 +172,7 @@ static int pm8xxx_vib_probe(struct platform_device *pdev)
struct pm8xxx_vib *vib;
struct input_dev *input_dev;
int error;
- unsigned int val;
+ unsigned int val, reg_base = 0;
const struct pm8xxx_regs *regs;
vib = devm_kzalloc(&pdev->dev, sizeof(*vib), GFP_KERNEL);
@@ -189,13 +192,24 @@ static int pm8xxx_vib_probe(struct platform_device *pdev)
regs = of_device_get_match_data(&pdev->dev);
+ if (regs->enable_offset != 0) {
+ error = fwnode_property_read_u32(pdev->dev.fwnode, "reg", ®_base);
+ if (error < 0) {
+ dev_err(&pdev->dev, "Failed to read reg address, rc=%d\n", error);
+ return error;
+ }
+ }
+
+ vib->enable_addr = reg_base + regs->enable_offset;
+ vib->drv_addr = reg_base + regs->drv_offset;
+
/* operate in manual mode */
- error = regmap_read(vib->regmap, regs->drv_addr, &val);
+ error = regmap_read(vib->regmap, vib->drv_addr, &val);
if (error < 0)
return error;
val &= regs->drv_en_manual_mask;
- error = regmap_write(vib->regmap, regs->drv_addr, val);
+ error = regmap_write(vib->regmap, vib->drv_addr, val);
if (error < 0)
return error;
--
2.25.1
^ permalink raw reply related
* [PATCH v8 3/3] input: pm8xxx-vibrator: add new SPMI vibrator support
From: Fenglin Wu via B4 Relay @ 2024-04-01 8:38 UTC (permalink / raw)
To: kernel, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Dmitry Torokhov, Rob Herring, Krzysztof Kozlowski,
Dmitry Baryshkov
Cc: linux-arm-msm, linux-input, linux-kernel, devicetree, Fenglin Wu
In-Reply-To: <20240401-pm8xxx-vibrator-new-design-v8-0-6f2b8b03b4c7@quicinc.com>
From: Fenglin Wu <quic_fenglinw@quicinc.com>
Add support for a new SPMI vibrator module which is very similar
to the vibrator module inside PM8916 but has a finer drive voltage
step and different output voltage range, its drive level control
is expanded across 2 registers. The vibrator module can be found
in following Qualcomm PMICs: PMI632, PM7250B, PM7325B, PM7550BA.
Signed-off-by: Fenglin Wu <quic_fenglinw@quicinc.com>
---
drivers/input/misc/pm8xxx-vibrator.c | 49 +++++++++++++++++++++++++++++-------
1 file changed, 40 insertions(+), 9 deletions(-)
diff --git a/drivers/input/misc/pm8xxx-vibrator.c b/drivers/input/misc/pm8xxx-vibrator.c
index 3b6a2e949f30..59548cd9331c 100644
--- a/drivers/input/misc/pm8xxx-vibrator.c
+++ b/drivers/input/misc/pm8xxx-vibrator.c
@@ -12,9 +12,9 @@
#include <linux/regmap.h>
#include <linux/slab.h>
-#define VIB_MAX_LEVEL_mV (3100)
-#define VIB_MIN_LEVEL_mV (1200)
-#define VIB_MAX_LEVELS (VIB_MAX_LEVEL_mV - VIB_MIN_LEVEL_mV)
+#define VIB_MAX_LEVEL_mV(vib) (vib->drv2_addr ? (3544) : (3100))
+#define VIB_MIN_LEVEL_mV(vib) (vib->drv2_addr ? (1504) : (1200))
+#define VIB_MAX_LEVELS(vib) (VIB_MAX_LEVEL_mV(vib) - VIB_MIN_LEVEL_mV(vib))
#define MAX_FF_SPEED 0xff
@@ -25,6 +25,9 @@ struct pm8xxx_regs {
unsigned int drv_offset;
unsigned int drv_mask;
unsigned int drv_shift;
+ unsigned int drv2_offset;
+ unsigned int drv2_mask;
+ unsigned int drv2_shift;
unsigned int drv_en_manual_mask;
};
@@ -44,6 +47,18 @@ static struct pm8xxx_regs pm8916_regs = {
.drv_en_manual_mask = 0,
};
+static struct pm8xxx_regs pmi632_regs = {
+ .enable_offset = 0x46,
+ .enable_mask = BIT(7),
+ .drv_offset = 0x40,
+ .drv_mask = 0xFF,
+ .drv_shift = 0,
+ .drv2_offset = 0x41,
+ .drv2_mask = 0x0F,
+ .drv2_shift = 8,
+ .drv_en_manual_mask = 0,
+};
+
/**
* struct pm8xxx_vib - structure to hold vibrator data
* @vib_input_dev: input device supporting force feedback
@@ -52,6 +67,7 @@ static struct pm8xxx_regs pm8916_regs = {
* @regs: registers' info
* @enable_addr: vibrator enable register
* @drv_addr: vibrator drive strength register
+ * @drv2_addr: vibrator drive strength upper byte register
* @speed: speed of vibration set from userland
* @active: state of vibrator
* @level: level of vibration to set in the chip
@@ -64,6 +80,7 @@ struct pm8xxx_vib {
const struct pm8xxx_regs *regs;
unsigned int enable_addr;
unsigned int drv_addr;
+ unsigned int drv2_addr;
int speed;
int level;
bool active;
@@ -92,6 +109,16 @@ static int pm8xxx_vib_set(struct pm8xxx_vib *vib, bool on)
vib->reg_vib_drv = val;
+ if (regs->drv2_mask) {
+ if (on)
+ val = (vib->level << regs->drv2_shift) & regs->drv2_mask;
+ else
+ val = 0;
+ rc = regmap_write(vib->regmap, vib->drv2_addr, val);
+ if (rc < 0)
+ return rc;
+ }
+
if (regs->enable_mask)
rc = regmap_update_bits(vib->regmap, vib->enable_addr,
regs->enable_mask, on ? ~0 : 0);
@@ -114,19 +141,22 @@ static void pm8xxx_work_handler(struct work_struct *work)
return;
/*
- * pmic vibrator supports voltage ranges from 1.2 to 3.1V, so
+ * pmic vibrator supports voltage ranges from MIN_LEVEL to MAX_LEVEL, so
* scale the level to fit into these ranges.
*/
if (vib->speed) {
vib->active = true;
- vib->level = ((VIB_MAX_LEVELS * vib->speed) / MAX_FF_SPEED) +
- VIB_MIN_LEVEL_mV;
- vib->level /= 100;
+ vib->level = ((VIB_MAX_LEVELS(vib) * vib->speed) / MAX_FF_SPEED) +
+ VIB_MIN_LEVEL_mV(vib);
} else {
vib->active = false;
- vib->level = VIB_MIN_LEVEL_mV / 100;
+ vib->level = VIB_MIN_LEVEL_mV(vib);
+
}
+ if (!vib->drv2_addr)
+ vib->level /= 100;
+
pm8xxx_vib_set(vib, vib->active);
}
@@ -202,7 +232,7 @@ static int pm8xxx_vib_probe(struct platform_device *pdev)
vib->enable_addr = reg_base + regs->enable_offset;
vib->drv_addr = reg_base + regs->drv_offset;
-
+ vib->drv2_addr = reg_base + regs->drv2_offset;
/* operate in manual mode */
error = regmap_read(vib->regmap, vib->drv_addr, &val);
if (error < 0)
@@ -256,6 +286,7 @@ static const struct of_device_id pm8xxx_vib_id_table[] = {
{ .compatible = "qcom,pm8058-vib", .data = &pm8058_regs },
{ .compatible = "qcom,pm8921-vib", .data = &pm8058_regs },
{ .compatible = "qcom,pm8916-vib", .data = &pm8916_regs },
+ { .compatible = "qcom,pmi632-vib", .data = &pmi632_regs },
{ }
};
MODULE_DEVICE_TABLE(of, pm8xxx_vib_id_table);
--
2.25.1
^ permalink raw reply related
* [PATCH v8 0/3] Add support for vibrator in multiple PMICs
From: Fenglin Wu via B4 Relay @ 2024-04-01 8:38 UTC (permalink / raw)
To: kernel, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Dmitry Torokhov, Rob Herring, Krzysztof Kozlowski,
Dmitry Baryshkov
Cc: linux-arm-msm, linux-input, linux-kernel, devicetree, Fenglin Wu,
Krzysztof Kozlowski
Add SW support for the vibrator module inside PMI632, PM7250B, PM7325B, PM7550BA.
It is very similar to the vibrator module inside PM8916 which is supported in
pm8xxx-vib driver but just the drive amplitude is controlled with 2 registers,
and the register base offset in each PMIC is different.
Changes in v8:
1. Remove hw_type, and still keep the register info in match data
2. Update to use register offset in pm8xxx_regs, and the base address
defined in DT for SPMI vibrator will be added in register access
3. Update voltage output range for SPMI vibrator which has 2 bytes drive
registers
Changes in v7:
1. Fix a typo: SSBL_VIB_DRV_REG --> SSBI_VIB_DRV_REG
2. Move the hw_type switch case in pm8xxx_vib_set() to the refactoring
change.
Changes in v6:
1. Add "qcom,pmi632-vib" as a standalone compatible string.
Changes in v5:
1. Drop "qcom,spmi-vib-gen2" generic compatible string as requested
and use device specific compatible strings only.
Changes in v4:
1. Update to use the combination of the HW type and register offset
as the constant match data, the register base address defined in
'reg' property will be added when accessing SPMI registers using
regmap APIs.
2. Remove 'qcom,spmi-vib-gen1' generic compatible string.
Changes in v3:
1. Refactor the driver to support different type of the vibrators with
better flexibility by introducing the HW type with corresponding
register fields definitions.
2. Add 'qcom,spmi-vib-gen1' and 'qcom,spmi-vib-gen2' compatible
strings, and add PMI632, PM7250B, PM7325B, PM7550BA as compatbile as
spmi-vib-gen2.
Changes in v2:
Remove the "pm7550ba-vib" compatible string as it's compatible with pm7325b.
Signed-off-by: Fenglin Wu <quic_fenglinw@quicinc.com>
---
Fenglin Wu (3):
input: pm8xxx-vibrator: refactor to support new SPMI vibrator
dt-bindings: input: qcom,pm8xxx-vib: add new SPMI vibrator module
input: pm8xxx-vibrator: add new SPMI vibrator support
.../devicetree/bindings/input/qcom,pm8xxx-vib.yaml | 16 +++-
drivers/input/misc/pm8xxx-vibrator.c | 87 ++++++++++++++++------
2 files changed, 78 insertions(+), 25 deletions(-)
---
base-commit: 650cda2ce25f08e8fae391b3ba6be27e7296c6a5
change-id: 20240328-pm8xxx-vibrator-new-design-e5811ad59e8a
Best regards,
--
Fenglin Wu <quic_fenglinw@quicinc.com>
^ permalink raw reply
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