* Re: [RFC PATCH 1/2] spi: dt-bindings: add Siflower Quad SPI controller
From: Qingfang Deng @ 2024-04-01 3:36 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Mark Brown, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Qingfang Deng, linux-spi, devicetree, linux-kernel
In-Reply-To: <261f2995-b279-48bc-b9d4-023a8a705857@linaro.org>
Hi Krzysztof,
On Sun, Mar 31, 2024 at 1:42 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 29/03/2024 02:51, Qingfang Deng wrote:
> > Add YAML devicetree bindings for Siflower Quad SPI controller.
>
> Describe the hardware. What is this Siflower?
It's a new RISC-V SoC which hasn't been upstreamed yet.
> > +properties:
> > + compatible:
> > + const: siflower,qspi
>
> Except that this was not tested, aren't you adding it for some SoC? If
> so, then you miss here SoC part.
I should add the "siflower" prefix to
Documentation/devicetree/bindings/vendor-prefixes.yaml, right?
Regards,
Qingfang
^ permalink raw reply
* Re: [PATCH v7 2/2] dmaengine: Loongson1: Add Loongson-1 APB DMA driver
From: Keguang Zhang @ 2024-04-01 2:44 UTC (permalink / raw)
To: Huacai Chen
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-mips, dmaengine, devicetree, linux-kernel
In-Reply-To: <CAAhV-H6gG5KGxku+aZPwfmqAVF9zfL-9-nNqCd2Z_swxgCe_HA@mail.gmail.com>
Hi Huacai,
On Sat, Mar 30, 2024 at 9:59 PM Huacai Chen <chenhuacai@kernel.org> wrote:
>
> Hi, Keguang,
>
> On Fri, Mar 29, 2024 at 7:28 PM Keguang Zhang via B4 Relay
> <devnull+keguang.zhang.gmail.com@kernel.org> wrote:
> >
> > From: Keguang Zhang <keguang.zhang@gmail.com>
> >
> > This patch adds APB DMA driver for Loongson-1 SoCs.
> >
> > Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com>
> > ---
> > Changes in v7:
> > - Change the comptible to 'loongson,ls1*-apbdma'
> > - Update Kconfig and Makefile accordingly
> > - Rename the file to loongson1-apb-dma.c to keep the consistency
> >
> > Changes in v6:
> > - Implement .device_prep_dma_cyclic for Loongson1 audio driver,
> > - as well as .device_pause and .device_resume.
> > - Set the limitation LS1X_DMA_MAX_DESC and put all descriptors
> > - into one page to save memory
> > - Move dma_pool_zalloc() into ls1x_dma_alloc_desc()
> > - Drop dma_slave_config structure
> > - Use .remove_new instead of .remove
> > - Use KBUILD_MODNAME for the driver name
> > - Improve the debug information
> >
> > Changes in v5:
> > - Add DT support
> > - Use DT data instead of platform data
> > - Use chan_id of struct dma_chan instead of own id
> > - Use of_dma_xlate_by_chan_id() instead of ls1x_dma_filter()
> > - Update the author information to my official name
> >
> > Changes in v4:
> > - Use dma_slave_map to find the proper channel.
> > - Explicitly call devm_request_irq() and tasklet_kill().
> > - Fix namespace issue.
> > - Some minor fixes and cleanups.
> >
> > Changes in v3:
> > - Rename ls1x_dma_filter_fn to ls1x_dma_filter.
> >
> > Changes in v2:
> > - Change the config from 'DMA_LOONGSON1' to 'LOONGSON1_DMA',
> > - and rearrange it in alphabetical order in Kconfig and Makefile.
> > - Fix comment style.
> > ---
> > drivers/dma/Kconfig | 9 +
> > drivers/dma/Makefile | 1 +
> > drivers/dma/loongson1-apb-dma.c | 665 ++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 675 insertions(+)
> >
> > diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> > index 002a5ec80620..f7b06c4cdf3f 100644
> > --- a/drivers/dma/Kconfig
> > +++ b/drivers/dma/Kconfig
> > @@ -369,6 +369,15 @@ config K3_DMA
> > Support the DMA engine for Hisilicon K3 platform
> > devices.
> >
> > +config LOONGSON1_APB_DMA
> > + tristate "Loongson1 APB DMA support"
> > + depends on MACH_LOONGSON32 || COMPILE_TEST
> > + select DMA_ENGINE
> > + select DMA_VIRTUAL_CHANNELS
> > + help
> > + This selects support for the APB DMA controller in Loongson1 SoCs,
> > + which is required by Loongson1 NAND and audio support.
> Why not rename to LS1X_APB_DMA and put it just before LS2X_APB_DMA
> (and also the driver file name)?
>
So far all Kconfig entries of Loongson-1 drivers are named with the
keyword "LOONGSON1".
The same is true for these file names.
Therefore, I need to keep the consistency.
> Huacai
>
> > +
> > config LPC18XX_DMAMUX
> > bool "NXP LPC18xx/43xx DMA MUX for PL080"
> > depends on ARCH_LPC18XX || COMPILE_TEST
> > diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> > index dfd40d14e408..b26f6677978a 100644
> > --- a/drivers/dma/Makefile
> > +++ b/drivers/dma/Makefile
> > @@ -47,6 +47,7 @@ obj-$(CONFIG_INTEL_IDMA64) += idma64.o
> > obj-$(CONFIG_INTEL_IOATDMA) += ioat/
> > obj-y += idxd/
> > obj-$(CONFIG_K3_DMA) += k3dma.o
> > +obj-$(CONFIG_LOONGSON1_APB_DMA) += loongson1-apb-dma.o
> > obj-$(CONFIG_LPC18XX_DMAMUX) += lpc18xx-dmamux.o
> > obj-$(CONFIG_LS2X_APB_DMA) += ls2x-apb-dma.o
> > obj-$(CONFIG_MILBEAUT_HDMAC) += milbeaut-hdmac.o
> > diff --git a/drivers/dma/loongson1-apb-dma.c b/drivers/dma/loongson1-apb-dma.c
> > new file mode 100644
> > index 000000000000..d474a2601e6e
> > --- /dev/null
> > +++ b/drivers/dma/loongson1-apb-dma.c
> > @@ -0,0 +1,665 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +/*
> > + * Driver for Loongson-1 APB DMA Controller
> > + *
> > + * Copyright (C) 2015-2024 Keguang Zhang <keguang.zhang@gmail.com>
> > + */
> > +
> > +#include <linux/dmapool.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/init.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_dma.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +
> > +#include "dmaengine.h"
> > +#include "virt-dma.h"
> > +
> > +/* Loongson-1 DMA Control Register */
> > +#define DMA_CTRL 0x0
> > +
> > +/* DMA Control Register Bits */
> > +#define DMA_STOP BIT(4)
> > +#define DMA_START BIT(3)
> > +#define DMA_ASK_VALID BIT(2)
> > +
> > +#define DMA_ADDR_MASK GENMASK(31, 6)
> > +
> > +/* DMA Next Field Bits */
> > +#define DMA_NEXT_VALID BIT(0)
> > +
> > +/* DMA Command Field Bits */
> > +#define DMA_RAM2DEV BIT(12)
> > +#define DMA_INT BIT(1)
> > +#define DMA_INT_MASK BIT(0)
> > +
> > +#define LS1X_DMA_MAX_CHANNELS 3
> > +
> > +/* Size of allocations for hardware descriptors */
> > +#define LS1X_DMA_DESCS_SIZE PAGE_SIZE
> > +#define LS1X_DMA_MAX_DESC \
> > + (LS1X_DMA_DESCS_SIZE / sizeof(struct ls1x_dma_hwdesc))
> > +
> > +struct ls1x_dma_hwdesc {
> > + u32 next; /* next descriptor address */
> > + u32 saddr; /* memory DMA address */
> > + u32 daddr; /* device DMA address */
> > + u32 length;
> > + u32 stride;
> > + u32 cycles;
> > + u32 cmd;
> > + u32 stats;
> > +};
> > +
> > +struct ls1x_dma_desc {
> > + struct virt_dma_desc vdesc;
> > + enum dma_transfer_direction dir;
> > + enum dma_transaction_type type;
> > + unsigned int bus_width;
> > +
> > + unsigned int nr_descs; /* number of descriptors */
> > +
> > + struct ls1x_dma_hwdesc *hwdesc;
> > + dma_addr_t hwdesc_phys;
> > +};
> > +
> > +struct ls1x_dma_chan {
> > + struct virt_dma_chan vchan;
> > + struct dma_pool *desc_pool;
> > + phys_addr_t src_addr;
> > + phys_addr_t dst_addr;
> > + enum dma_slave_buswidth src_addr_width;
> > + enum dma_slave_buswidth dst_addr_width;
> > +
> > + void __iomem *reg_base;
> > + int irq;
> > +
> > + struct ls1x_dma_desc *desc;
> > +
> > + struct ls1x_dma_hwdesc *curr_hwdesc;
> > + dma_addr_t curr_hwdesc_phys;
> > +};
> > +
> > +struct ls1x_dma {
> > + struct dma_device ddev;
> > + void __iomem *reg_base;
> > +
> > + unsigned int nr_chans;
> > + struct ls1x_dma_chan chan[];
> > +};
> > +
> > +#define to_ls1x_dma_chan(dchan) \
> > + container_of(dchan, struct ls1x_dma_chan, vchan.chan)
> > +
> > +#define to_ls1x_dma_desc(vd) \
> > + container_of(vd, struct ls1x_dma_desc, vdesc)
> > +
> > +/* macros for registers read/write */
> > +#define chan_readl(chan, off) \
> > + readl((chan)->reg_base + (off))
> > +
> > +#define chan_writel(chan, off, val) \
> > + writel((val), (chan)->reg_base + (off))
> > +
> > +static inline struct device *chan2dev(struct dma_chan *chan)
> > +{
> > + return &chan->dev->device;
> > +}
> > +
> > +static inline int ls1x_dma_query(struct ls1x_dma_chan *chan,
> > + dma_addr_t *hwdesc_phys)
> > +{
> > + struct dma_chan *dchan = &chan->vchan.chan;
> > + int val, ret;
> > +
> > + val = *hwdesc_phys & DMA_ADDR_MASK;
> > + val |= DMA_ASK_VALID;
> > + val |= dchan->chan_id;
> > + chan_writel(chan, DMA_CTRL, val);
> > + ret = readl_poll_timeout_atomic(chan->reg_base + DMA_CTRL, val,
> > + !(val & DMA_ASK_VALID), 0, 3000);
> > + if (ret)
> > + dev_err(chan2dev(dchan), "failed to query DMA\n");
> > +
> > + return ret;
> > +}
> > +
> > +static inline int ls1x_dma_start(struct ls1x_dma_chan *chan,
> > + dma_addr_t *hwdesc_phys)
> > +{
> > + struct dma_chan *dchan = &chan->vchan.chan;
> > + int val, ret;
> > +
> > + dev_dbg(chan2dev(dchan), "cookie=%d, starting hwdesc=%x\n",
> > + dchan->cookie, *hwdesc_phys);
> > +
> > + val = *hwdesc_phys & DMA_ADDR_MASK;
> > + val |= DMA_START;
> > + val |= dchan->chan_id;
> > + chan_writel(chan, DMA_CTRL, val);
> > + ret = readl_poll_timeout(chan->reg_base + DMA_CTRL, val,
> > + !(val & DMA_START), 0, 3000);
> > + if (ret)
> > + dev_err(chan2dev(dchan), "failed to start DMA\n");
> > +
> > + return ret;
> > +}
> > +
> > +static inline void ls1x_dma_stop(struct ls1x_dma_chan *chan)
> > +{
> > + chan_writel(chan, DMA_CTRL, chan_readl(chan, DMA_CTRL) | DMA_STOP);
> > +}
> > +
> > +static void ls1x_dma_free_chan_resources(struct dma_chan *dchan)
> > +{
> > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > +
> > + dma_free_coherent(chan2dev(dchan), sizeof(struct ls1x_dma_hwdesc),
> > + chan->curr_hwdesc, chan->curr_hwdesc_phys);
> > + vchan_free_chan_resources(&chan->vchan);
> > + dma_pool_destroy(chan->desc_pool);
> > + chan->desc_pool = NULL;
> > +}
> > +
> > +static int ls1x_dma_alloc_chan_resources(struct dma_chan *dchan)
> > +{
> > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > +
> > + chan->desc_pool = dma_pool_create(dma_chan_name(dchan),
> > + chan2dev(dchan),
> > + sizeof(struct ls1x_dma_hwdesc),
> > + __alignof__(struct ls1x_dma_hwdesc),
> > + 0);
> > + if (!chan->desc_pool)
> > + return -ENOMEM;
> > +
> > + /* allocate memory for querying current HW descriptor */
> > + dma_set_coherent_mask(chan2dev(dchan), DMA_BIT_MASK(32));
> > + chan->curr_hwdesc = dma_alloc_coherent(chan2dev(dchan),
> > + sizeof(struct ls1x_dma_hwdesc),
> > + &chan->curr_hwdesc_phys,
> > + GFP_KERNEL);
> > + if (!chan->curr_hwdesc)
> > + return -ENOMEM;
> > +
> > + return 0;
> > +}
> > +
> > +static void ls1x_dma_free_desc(struct virt_dma_desc *vdesc)
> > +{
> > + struct ls1x_dma_desc *desc = to_ls1x_dma_desc(vdesc);
> > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(vdesc->tx.chan);
> > +
> > + dma_pool_free(chan->desc_pool, desc->hwdesc, desc->hwdesc_phys);
> > + chan->desc = NULL;
> > + kfree(desc);
> > +}
> > +
> > +static struct ls1x_dma_desc *
> > +ls1x_dma_alloc_desc(struct dma_chan *dchan, int sg_len,
> > + enum dma_transfer_direction direction,
> > + enum dma_transaction_type type)
> > +{
> > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > + struct ls1x_dma_desc *desc;
> > +
> > + if (sg_len > LS1X_DMA_MAX_DESC) {
> > + dev_err(chan2dev(dchan), "sg_len %u exceeds limit %lu",
> > + sg_len, LS1X_DMA_MAX_DESC);
> > + return NULL;
> > + }
> > +
> > + desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
> > + if (!desc)
> > + return NULL;
> > +
> > + /* allocate HW descriptors */
> > + desc->hwdesc = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT,
> > + &desc->hwdesc_phys);
> > + if (!desc->hwdesc) {
> > + dev_err(chan2dev(dchan), "failed to alloc HW descriptors\n");
> > + ls1x_dma_free_desc(&desc->vdesc);
> > + return NULL;
> > + }
> > +
> > + desc->dir = direction;
> > + desc->type = type;
> > + desc->nr_descs = sg_len;
> > +
> > + return desc;
> > +}
> > +
> > +static int ls1x_dma_setup_hwdescs(struct dma_chan *dchan,
> > + struct ls1x_dma_desc *desc,
> > + struct scatterlist *sgl, unsigned int sg_len)
> > +{
> > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > + dma_addr_t next_hwdesc_phys = desc->hwdesc_phys;
> > +
> > + struct scatterlist *sg;
> > + unsigned int dev_addr, cmd, i;
> > +
> > + switch (desc->dir) {
> > + case DMA_MEM_TO_DEV:
> > + dev_addr = chan->dst_addr;
> > + desc->bus_width = chan->dst_addr_width;
> > + cmd = DMA_RAM2DEV | DMA_INT;
> > + break;
> > + case DMA_DEV_TO_MEM:
> > + dev_addr = chan->src_addr;
> > + desc->bus_width = chan->src_addr_width;
> > + cmd = DMA_INT;
> > + break;
> > + default:
> > + dev_err(chan2dev(dchan), "unsupported DMA direction: %s\n",
> > + dmaengine_get_direction_text(desc->dir));
> > + return -EINVAL;
> > + }
> > +
> > + /* setup HW descriptors */
> > + for_each_sg(sgl, sg, sg_len, i) {
> > + dma_addr_t buf_addr = sg_dma_address(sg);
> > + size_t buf_len = sg_dma_len(sg);
> > + struct ls1x_dma_hwdesc *hwdesc = &desc->hwdesc[i];
> > +
> > + if (!is_dma_copy_aligned(dchan->device, buf_addr, 0, buf_len)) {
> > + dev_err(chan2dev(dchan), "buffer is not aligned!\n");
> > + return -EINVAL;
> > + }
> > +
> > + hwdesc->saddr = buf_addr;
> > + hwdesc->daddr = dev_addr;
> > + hwdesc->length = buf_len / desc->bus_width;
> > + hwdesc->stride = 0;
> > + hwdesc->cycles = 1;
> > + hwdesc->cmd = cmd;
> > +
> > + if (i) {
> > + next_hwdesc_phys += sizeof(*hwdesc);
> > + desc->hwdesc[i - 1].next = next_hwdesc_phys
> > + | DMA_NEXT_VALID;
> > + }
> > + }
> > +
> > + if (desc->type == DMA_CYCLIC)
> > + desc->hwdesc[i - 1].next = desc->hwdesc_phys | DMA_NEXT_VALID;
> > +
> > + for_each_sg(sgl, sg, sg_len, i) {
> > + struct ls1x_dma_hwdesc *hwdesc = &desc->hwdesc[i];
> > +
> > + print_hex_dump_debug("HW DESC: ", DUMP_PREFIX_OFFSET, 16, 4,
> > + hwdesc, sizeof(*hwdesc), false);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static struct dma_async_tx_descriptor *
> > +ls1x_dma_prep_slave_sg(struct dma_chan *dchan,
> > + struct scatterlist *sgl, unsigned int sg_len,
> > + enum dma_transfer_direction direction,
> > + unsigned long flags, void *context)
> > +{
> > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > + struct ls1x_dma_desc *desc;
> > +
> > + dev_dbg(chan2dev(dchan), "sg_len=%u flags=0x%lx dir=%s\n",
> > + sg_len, flags, dmaengine_get_direction_text(direction));
> > +
> > + desc = ls1x_dma_alloc_desc(dchan, sg_len, direction, DMA_SLAVE);
> > + if (!desc)
> > + return NULL;
> > +
> > + if (ls1x_dma_setup_hwdescs(dchan, desc, sgl, sg_len)) {
> > + ls1x_dma_free_desc(&desc->vdesc);
> > + return NULL;
> > + }
> > +
> > + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
> > +}
> > +
> > +static struct dma_async_tx_descriptor *
> > +ls1x_dma_prep_dma_cyclic(struct dma_chan *dchan,
> > + dma_addr_t buf_addr, size_t buf_len, size_t period_len,
> > + enum dma_transfer_direction direction,
> > + unsigned long flags)
> > +{
> > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > + struct ls1x_dma_desc *desc;
> > + struct scatterlist *sgl;
> > + unsigned int sg_len;
> > + unsigned int i;
> > +
> > + dev_dbg(chan2dev(dchan),
> > + "buf_len=%d period_len=%zu flags=0x%lx dir=%s\n", buf_len,
> > + period_len, flags, dmaengine_get_direction_text(direction));
> > +
> > + sg_len = buf_len / period_len;
> > + desc = ls1x_dma_alloc_desc(dchan, sg_len, direction, DMA_CYCLIC);
> > + if (!desc)
> > + return NULL;
> > +
> > + /* allocate the scatterlist */
> > + sgl = kmalloc_array(sg_len, sizeof(*sgl), GFP_NOWAIT);
> > + if (!sgl)
> > + return NULL;
> > +
> > + sg_init_table(sgl, sg_len);
> > + for (i = 0; i < sg_len; ++i) {
> > + sg_set_page(&sgl[i], pfn_to_page(PFN_DOWN(buf_addr)),
> > + period_len, offset_in_page(buf_addr));
> > + sg_dma_address(&sgl[i]) = buf_addr;
> > + sg_dma_len(&sgl[i]) = period_len;
> > + buf_addr += period_len;
> > + }
> > +
> > + if (ls1x_dma_setup_hwdescs(dchan, desc, sgl, sg_len)) {
> > + ls1x_dma_free_desc(&desc->vdesc);
> > + return NULL;
> > + }
> > +
> > + kfree(sgl);
> > +
> > + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
> > +}
> > +
> > +static int ls1x_dma_slave_config(struct dma_chan *dchan,
> > + struct dma_slave_config *config)
> > +{
> > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > +
> > + chan->src_addr = config->src_addr;
> > + chan->src_addr_width = config->src_addr_width;
> > + chan->dst_addr = config->dst_addr;
> > + chan->dst_addr_width = config->dst_addr_width;
> > +
> > + return 0;
> > +}
> > +
> > +static int ls1x_dma_pause(struct dma_chan *dchan)
> > +{
> > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > + unsigned long flags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&chan->vchan.lock, flags);
> > + ret = ls1x_dma_query(chan, &chan->curr_hwdesc_phys);
> > + if (!ret)
> > + ls1x_dma_stop(chan);
> > + spin_unlock_irqrestore(&chan->vchan.lock, flags);
> > +
> > + return ret;
> > +}
> > +
> > +static int ls1x_dma_resume(struct dma_chan *dchan)
> > +{
> > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > + unsigned long flags;
> > + int ret;
> > +
> > + spin_lock_irqsave(&chan->vchan.lock, flags);
> > + ret = ls1x_dma_start(chan, &chan->curr_hwdesc_phys);
> > + spin_unlock_irqrestore(&chan->vchan.lock, flags);
> > +
> > + return ret;
> > +}
> > +
> > +static int ls1x_dma_terminate_all(struct dma_chan *dchan)
> > +{
> > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > + unsigned long flags;
> > + LIST_HEAD(head);
> > +
> > + spin_lock_irqsave(&chan->vchan.lock, flags);
> > + ls1x_dma_stop(chan);
> > + vchan_get_all_descriptors(&chan->vchan, &head);
> > + spin_unlock_irqrestore(&chan->vchan.lock, flags);
> > +
> > + vchan_dma_desc_free_list(&chan->vchan, &head);
> > +
> > + return 0;
> > +}
> > +
> > +static enum dma_status ls1x_dma_tx_status(struct dma_chan *dchan,
> > + dma_cookie_t cookie,
> > + struct dma_tx_state *state)
> > +{
> > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > + struct virt_dma_desc *vdesc;
> > + enum dma_status status;
> > + size_t bytes = 0;
> > + unsigned long flags;
> > +
> > + status = dma_cookie_status(dchan, cookie, state);
> > + if (status == DMA_COMPLETE)
> > + return status;
> > +
> > + spin_lock_irqsave(&chan->vchan.lock, flags);
> > + vdesc = vchan_find_desc(&chan->vchan, cookie);
> > + if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) {
> > + struct ls1x_dma_desc *desc = chan->desc;
> > + int i;
> > +
> > + if (ls1x_dma_query(chan, &chan->curr_hwdesc_phys))
> > + return status;
> > +
> > + /* locate the current HW descriptor */
> > + for (i = 0; i < desc->nr_descs; i++)
> > + if (desc->hwdesc[i].next == chan->curr_hwdesc->next)
> > + break;
> > +
> > + /* count the residues */
> > + for (; i < desc->nr_descs; i++)
> > + bytes += desc->hwdesc[i].length * desc->bus_width;
> > +
> > + dma_set_residue(state, bytes);
> > + }
> > + spin_unlock_irqrestore(&chan->vchan.lock, flags);
> > +
> > + return status;
> > +}
> > +
> > +static void ls1x_dma_issue_pending(struct dma_chan *dchan)
> > +{
> > + struct ls1x_dma_chan *chan = to_ls1x_dma_chan(dchan);
> > + struct virt_dma_desc *vdesc;
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&chan->vchan.lock, flags);
> > + if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
> > + vdesc = vchan_next_desc(&chan->vchan);
> > + if (!vdesc) {
> > + chan->desc = NULL;
> > + return;
> > + }
> > + chan->desc = to_ls1x_dma_desc(vdesc);
> > + ls1x_dma_start(chan, &chan->desc->hwdesc_phys);
> > + }
> > + spin_unlock_irqrestore(&chan->vchan.lock, flags);
> > +}
> > +
> > +static irqreturn_t ls1x_dma_irq_handler(int irq, void *data)
> > +{
> > + struct ls1x_dma_chan *chan = data;
> > + struct ls1x_dma_desc *desc = chan->desc;
> > + struct dma_chan *dchan = &chan->vchan.chan;
> > +
> > + if (!desc) {
> > + dev_warn(chan2dev(dchan),
> > + "IRQ %d with no active descriptor on channel %d\n",
> > + irq, dchan->chan_id);
> > + return IRQ_NONE;
> > + }
> > +
> > + dev_dbg(chan2dev(dchan), "DMA IRQ %d on channel %d\n", irq,
> > + dchan->chan_id);
> > +
> > + spin_lock(&chan->vchan.lock);
> > +
> > + if (desc->type == DMA_CYCLIC) {
> > + vchan_cyclic_callback(&desc->vdesc);
> > + } else {
> > + list_del(&desc->vdesc.node);
> > + vchan_cookie_complete(&desc->vdesc);
> > + chan->desc = NULL;
> > + }
> > +
> > + spin_unlock(&chan->vchan.lock);
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static int ls1x_dma_chan_probe(struct platform_device *pdev,
> > + struct ls1x_dma *dma, int chan_id)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct ls1x_dma_chan *chan = &dma->chan[chan_id];
> > + char pdev_irqname[4];
> > + char *irqname;
> > + int ret;
> > +
> > + sprintf(pdev_irqname, "ch%u", chan_id);
> > + chan->irq = platform_get_irq_byname(pdev, pdev_irqname);
> > + if (chan->irq < 0)
> > + return -ENODEV;
> > +
> > + irqname = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
> > + dev_name(dev), pdev_irqname);
> > + if (!irqname)
> > + return -ENOMEM;
> > +
> > + ret = devm_request_irq(dev, chan->irq, ls1x_dma_irq_handler,
> > + IRQF_SHARED, irqname, chan);
> > + if (ret)
> > + return dev_err_probe(dev, ret,
> > + "failed to request IRQ %u!\n", chan->irq);
> > +
> > + chan->reg_base = dma->reg_base;
> > + chan->vchan.desc_free = ls1x_dma_free_desc;
> > + vchan_init(&chan->vchan, &dma->ddev);
> > + dev_info(dev, "%s (irq %d) initialized\n", pdev_irqname, chan->irq);
> > +
> > + return 0;
> > +}
> > +
> > +static void ls1x_dma_chan_remove(struct ls1x_dma *dma, int chan_id)
> > +{
> > + struct device *dev = dma->ddev.dev;
> > + struct ls1x_dma_chan *chan = &dma->chan[chan_id];
> > +
> > + devm_free_irq(dev, chan->irq, chan);
> > + list_del(&chan->vchan.chan.device_node);
> > + tasklet_kill(&chan->vchan.task);
> > +}
> > +
> > +static int ls1x_dma_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct dma_device *ddev;
> > + struct ls1x_dma *dma;
> > + int nr_chans, ret, i;
> > +
> > + nr_chans = platform_irq_count(pdev);
> > + if (nr_chans <= 0)
> > + return nr_chans;
> > + if (nr_chans > LS1X_DMA_MAX_CHANNELS)
> > + return dev_err_probe(dev, -EINVAL,
> > + "nr_chans=%d exceeds the maximum\n",
> > + nr_chans);
> > +
> > + dma = devm_kzalloc(dev, struct_size(dma, chan, nr_chans), GFP_KERNEL);
> > + if (!dma)
> > + return -ENOMEM;
> > +
> > + /* initialize DMA device */
> > + dma->reg_base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(dma->reg_base))
> > + return PTR_ERR(dma->reg_base);
> > +
> > + ddev = &dma->ddev;
> > + ddev->dev = dev;
> > + ddev->copy_align = DMAENGINE_ALIGN_4_BYTES;
> > + ddev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
> > + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
> > + ddev->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
> > + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
> > + ddev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
> > + ddev->max_sg_burst = LS1X_DMA_MAX_DESC;
> > + ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
> > + ddev->device_alloc_chan_resources = ls1x_dma_alloc_chan_resources;
> > + ddev->device_free_chan_resources = ls1x_dma_free_chan_resources;
> > + ddev->device_prep_slave_sg = ls1x_dma_prep_slave_sg;
> > + ddev->device_prep_dma_cyclic = ls1x_dma_prep_dma_cyclic;
> > + ddev->device_config = ls1x_dma_slave_config;
> > + ddev->device_pause = ls1x_dma_pause;
> > + ddev->device_resume = ls1x_dma_resume;
> > + ddev->device_terminate_all = ls1x_dma_terminate_all;
> > + ddev->device_tx_status = ls1x_dma_tx_status;
> > + ddev->device_issue_pending = ls1x_dma_issue_pending;
> > +
> > + dma_cap_set(DMA_SLAVE, ddev->cap_mask);
> > + INIT_LIST_HEAD(&ddev->channels);
> > +
> > + /* initialize DMA channels */
> > + for (i = 0; i < nr_chans; i++) {
> > + ret = ls1x_dma_chan_probe(pdev, dma, i);
> > + if (ret)
> > + return ret;
> > + }
> > + dma->nr_chans = nr_chans;
> > +
> > + ret = dmaenginem_async_device_register(ddev);
> > + if (ret) {
> > + dev_err(dev, "failed to register DMA device! %d\n", ret);
> > + return ret;
> > + }
> > +
> > + ret =
> > + of_dma_controller_register(dev->of_node, of_dma_xlate_by_chan_id,
> > + ddev);
> > + if (ret) {
> > + dev_err(dev, "failed to register DMA controller! %d\n", ret);
> > + return ret;
> > + }
> > +
> > + platform_set_drvdata(pdev, dma);
> > + dev_info(dev, "Loongson1 DMA driver registered\n");
> > +
> > + return 0;
> > +}
> > +
> > +static void ls1x_dma_remove(struct platform_device *pdev)
> > +{
> > + struct ls1x_dma *dma = platform_get_drvdata(pdev);
> > + int i;
> > +
> > + of_dma_controller_free(pdev->dev.of_node);
> > +
> > + for (i = 0; i < dma->nr_chans; i++)
> > + ls1x_dma_chan_remove(dma, i);
> > +}
> > +
> > +static const struct of_device_id ls1x_dma_match[] = {
> > + { .compatible = "loongson,ls1b-apbdma" },
> > + { .compatible = "loongson,ls1c-apbdma" },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, ls1x_dma_match);
> > +
> > +static struct platform_driver ls1x_dma_driver = {
> > + .probe = ls1x_dma_probe,
> > + .remove_new = ls1x_dma_remove,
> > + .driver = {
> > + .name = KBUILD_MODNAME,
> > + .of_match_table = ls1x_dma_match,
> > + },
> > +};
> > +
> > +module_platform_driver(ls1x_dma_driver);
> > +
> > +MODULE_AUTHOR("Keguang Zhang <keguang.zhang@gmail.com>");
> > +MODULE_DESCRIPTION("Loongson-1 APB DMA Controller driver");
> > +MODULE_LICENSE("GPL");
> >
> > --
> > 2.40.1
> >
> >
--
Best regards,
Keguang Zhang
^ permalink raw reply
* [PATCH v3 6/7] PCI: dwc: rcar-gen4: Add support for r8a779g0
From: Yoshihiro Shimoda @ 2024-04-01 2:39 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
In-Reply-To: <20240401023942.134704-1-yoshihiro.shimoda.uh@renesas.com>
This driver previously supported r8a779f0 (R-Car S4-8). Add support
for r8a779g0 (R-Car V4H).
To support r8a779g0, it requires specific firmware.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 201 +++++++++++++++++++-
1 file changed, 200 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index e760bcd30c4e..fdd7a41fae33 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -5,8 +5,10 @@
*/
#include <linux/delay.h>
+#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pci.h>
@@ -20,9 +22,10 @@
/* Renesas-specific */
/* PCIe Mode Setting Register 0 */
#define PCIEMSR0 0x0000
-#define BIFUR_MOD_SET_ON BIT(0)
+#define APP_SRIS_MODE BIT(6)
#define DEVICE_TYPE_EP 0
#define DEVICE_TYPE_RC BIT(4)
+#define BIFUR_MOD_SET_ON BIT(0)
/* PCIe Interrupt Status 0 */
#define PCIEINTSTS0 0x0084
@@ -37,19 +40,47 @@
#define PCIEDMAINTSTSEN 0x0314
#define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)
+/* Port Logic Registers 89 */
+#define PRTLGC89 0x0b70
+
+/* Port Logic Registers 90 */
+#define PRTLGC90 0x0b74
+
/* PCIe Reset Control Register 1 */
#define PCIERSTCTRL1 0x0014
#define APP_HOLD_PHY_RST BIT(16)
#define APP_LTSSM_ENABLE BIT(0)
+/* PCIe Power Management Control */
+#define PCIEPWRMNGCTRL 0x0070
+#define APP_CLK_REQ_N BIT(11)
+#define APP_CLK_PM_EN BIT(10)
+
+/*
+ * The R-Car Gen4 documents don't describe the PHY registers' name.
+ * But, the initialization procedure describes these offsets. So,
+ * this driver makes up own #defines for the offsets.
+ */
+#define RCAR_GEN4_PCIE_PHY_0f8 0x0f8
+#define RCAR_GEN4_PCIE_PHY_148 0x148
+#define RCAR_GEN4_PCIE_PHY_1d4 0x1d4
+#define RCAR_GEN4_PCIE_PHY_514 0x514
+#define RCAR_GEN4_PCIE_PHY_700 0x700
+
#define RCAR_NUM_SPEED_CHANGE_RETRIES 10
#define RCAR_MAX_LINK_SPEED 4
#define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000
#define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800
+#define RCAR_GEN4_PCIE_FIRMWARE_NAME "rcar_gen4_pcie.bin"
+#define RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR 0xc000
+
+MODULE_FIRMWARE(RCAR_GEN4_PCIE_FIRMWARE_NAME);
+
struct rcar_gen4_pcie;
struct rcar_gen4_pcie_platdata {
+ void (*additional_common_init)(struct rcar_gen4_pcie *rcar);
int (*ltssm_enable)(struct rcar_gen4_pcie *rcar);
enum dw_pcie_device_mode mode;
};
@@ -57,12 +88,144 @@ struct rcar_gen4_pcie_platdata {
struct rcar_gen4_pcie {
struct dw_pcie dw;
void __iomem *base;
+ void __iomem *phy_base;
struct platform_device *pdev;
const struct rcar_gen4_pcie_platdata *platdata;
};
#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
/* Common */
+static void rcar_gen4_pcie_phy_reg_update_bits(struct rcar_gen4_pcie *rcar,
+ u32 offset, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ tmp = readl(rcar->phy_base + offset);
+ tmp &= ~mask;
+ tmp |= val;
+ writel(tmp, rcar->phy_base + offset);
+}
+
+static int rcar_gen4_pcie_reg_check_bit(struct rcar_gen4_pcie *rcar,
+ u32 offset, u32 mask)
+{
+ struct dw_pcie *dw = &rcar->dw;
+
+ if (dw_pcie_readl_dbi(dw, offset) & mask)
+ return -EAGAIN;
+
+ return 0;
+}
+
+static int rcar_gen4_pcie_update_phy_firmware(struct rcar_gen4_pcie *rcar)
+{
+ const u32 check_addr[] = { 0x00101018, 0x00101118, 0x00101021, 0x00101121};
+ struct dw_pcie *dw = &rcar->dw;
+ const struct firmware *fw;
+ unsigned int i, timeout;
+ u32 data;
+ int ret;
+
+ ret = request_firmware(&fw, RCAR_GEN4_PCIE_FIRMWARE_NAME, dw->dev);
+ if (ret) {
+ dev_err(dw->dev, "%s: Requesting firmware failed\n", __func__);
+ return ret;
+ }
+
+ for (i = 0; i < (fw->size / 2); i++) {
+ data = fw->data[i * 2] | fw->data[(i * 2) + 1] << 8;
+ timeout = 100;
+retry_data:
+ dw_pcie_writel_dbi(dw, PRTLGC89, RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR + i);
+ dw_pcie_writel_dbi(dw, PRTLGC90, data);
+ if (rcar_gen4_pcie_reg_check_bit(rcar, PRTLGC89, BIT(30)) < 0) {
+ if (!(--timeout)) {
+ ret = -ETIMEDOUT;
+ goto exit;
+ }
+ usleep_range(100, 200);
+ goto retry_data;
+ }
+ }
+
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_0f8, BIT(17), BIT(17));
+
+ for (i = 0; i < ARRAY_SIZE(check_addr); i++) {
+ timeout = 100;
+retry_check:
+ dw_pcie_writel_dbi(dw, PRTLGC89, check_addr[i]);
+ ret = rcar_gen4_pcie_reg_check_bit(rcar, PRTLGC89, BIT(30));
+ ret |= rcar_gen4_pcie_reg_check_bit(rcar, PRTLGC90, BIT(0));
+ if (ret < 0) {
+ if (!(--timeout)) {
+ ret = -ETIMEDOUT;
+ goto exit;
+ }
+ usleep_range(100, 200);
+ goto retry_check;
+ }
+ }
+
+ ret = 0;
+exit:
+ release_firmware(fw);
+
+ return ret;
+}
+
+static int rcar_gen4_pcie_enable_phy(struct rcar_gen4_pcie *rcar)
+{
+ struct dw_pcie *dw = &rcar->dw;
+ u32 val;
+ int ret;
+
+ val = dw_pcie_readl_dbi(dw, PCIE_PORT_FORCE);
+ val |= PORT_FORCE_DO_DESKEW_FOR_SRIS;
+ dw_pcie_writel_dbi(dw, PCIE_PORT_FORCE, val);
+
+ val = readl(rcar->base + PCIEMSR0);
+ val |= APP_SRIS_MODE;
+ writel(val, rcar->base + PCIEMSR0);
+
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_700, BIT(28), 0);
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_700, BIT(20), 0);
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_700, BIT(12), 0);
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_700, BIT(4), 0);
+
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_148,
+ GENMASK(23, 22), BIT(22));
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_148,
+ GENMASK(18, 16), GENMASK(17, 16));
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_148,
+ GENMASK(7, 6), BIT(6));
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_148,
+ GENMASK(2, 0), GENMASK(11, 0));
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_1d4,
+ GENMASK(16, 15), GENMASK(16, 15));
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_514, BIT(26), BIT(26));
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_0f8, BIT(16), 0);
+ rcar_gen4_pcie_phy_reg_update_bits(rcar, RCAR_GEN4_PCIE_PHY_0f8, BIT(19), BIT(19));
+
+ val = readl(rcar->base + PCIERSTCTRL1);
+ val &= ~APP_HOLD_PHY_RST;
+ writel(val, rcar->base + PCIERSTCTRL1);
+
+ ret = readl_poll_timeout(rcar->phy_base + RCAR_GEN4_PCIE_PHY_0f8, val,
+ !(val & BIT(18)), 100, 10000);
+ if (ret < 0)
+ return ret;
+
+ ret = rcar_gen4_pcie_update_phy_firmware(rcar);
+ if (ret)
+ return ret;
+
+ val = readl(rcar->base + PCIERSTCTRL1);
+ val |= APP_LTSSM_ENABLE;
+ writel(val, rcar->base + PCIERSTCTRL1);
+
+ return 0;
+}
+
static void rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar,
bool enable)
{
@@ -200,6 +363,9 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
if (ret)
goto err_unprepare;
+ if (rcar->platdata->additional_common_init)
+ rcar->platdata->additional_common_init(rcar);
+
return 0;
err_unprepare:
@@ -241,6 +407,10 @@ static void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
static int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
{
+ rcar->phy_base = devm_platform_ioremap_resource_byname(rcar->pdev, "phy");
+ if (IS_ERR(rcar->phy_base))
+ return PTR_ERR(rcar->base);
+
/* Renesas-specific registers */
rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");
@@ -517,6 +687,31 @@ static int r8a779f0_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar)
return 0;
}
+static void rcar_gen4_pcie_additional_common_init(struct rcar_gen4_pcie *rcar)
+{
+ struct dw_pcie *dw = &rcar->dw;
+ u32 val;
+
+ /*
+ * The SoC manual said the register setting is required. Otherwise,
+ * linkup failed.
+ */
+ val = dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW);
+ val &= ~PORT_LANE_SKEW_INSERT_MASK;
+ if (dw->num_lanes < 4)
+ val |= BIT(6);
+ dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val);
+
+ val = readl(rcar->base + PCIEPWRMNGCTRL);
+ val |= APP_CLK_REQ_N | APP_CLK_PM_EN;
+ writel(val, rcar->base + PCIEPWRMNGCTRL);
+}
+
+static int rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar)
+{
+ return rcar_gen4_pcie_enable_phy(rcar);
+}
+
static struct rcar_gen4_pcie_platdata platdata_r8a779f0_pcie = {
.ltssm_enable = r8a779f0_pcie_ltssm_enable,
.mode = DW_PCIE_RC_TYPE,
@@ -528,10 +723,14 @@ static struct rcar_gen4_pcie_platdata platdata_r8a779f0_pcie_ep = {
};
static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie = {
+ .additional_common_init = rcar_gen4_pcie_additional_common_init,
+ .ltssm_enable = rcar_gen4_pcie_ltssm_enable,
.mode = DW_PCIE_RC_TYPE,
};
static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie_ep = {
+ .additional_common_init = rcar_gen4_pcie_additional_common_init,
+ .ltssm_enable = rcar_gen4_pcie_ltssm_enable,
.mode = DW_PCIE_EP_TYPE,
};
--
2.25.1
^ permalink raw reply related
* [PATCH v3 7/7] misc: pci_endpoint_test: Document a policy about adding pci_device_id
From: Yoshihiro Shimoda @ 2024-04-01 2:39 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Frank Li
In-Reply-To: <20240401023942.134704-1-yoshihiro.shimoda.uh@renesas.com>
To avoid becoming struct pci_device_id pci_endpoint_test_tbl longer
and longer, document a policy. For example, if PCIe endpoint controller
can configure vendor id and/or product id, you can reuse one of
existing entries to test.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
Cc: Frank Li <Frank.li@nxp.com>
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index c38a6083f0a7..3c8a0afad91d 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -980,6 +980,7 @@ static const struct pci_endpoint_test_data j721e_data = {
.irq_type = IRQ_TYPE_MSI,
};
+/* Don't need to add a new entry if you can use existing entry to test */
static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),
.driver_data = (kernel_ulong_t)&default_data,
--
2.25.1
^ permalink raw reply related
* [PATCH v3 4/7] PCI: dwc: rcar-gen4: Add rcar_gen4_pcie_platdata
From: Yoshihiro Shimoda @ 2024-04-01 2:39 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
In-Reply-To: <20240401023942.134704-1-yoshihiro.shimoda.uh@renesas.com>
This driver supports r8a779f0 now. In the future, add support for
r8a779g0 and r8a779h0. To support these new SoCs, need other
initializing settings. So, at first, add rcar_gen4_pcie_platdata
and have a member with mode. No behavior changes.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 30 ++++++++++++++-------
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index 0be760ed420b..da2821d6efce 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -48,11 +48,15 @@
#define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000
#define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800
+struct rcar_gen4_pcie_platdata {
+ enum dw_pcie_device_mode mode;
+};
+
struct rcar_gen4_pcie {
struct dw_pcie dw;
void __iomem *base;
struct platform_device *pdev;
- enum dw_pcie_device_mode mode;
+ const struct rcar_gen4_pcie_platdata *platdata;
};
#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
@@ -137,7 +141,7 @@ static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
* Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
* So, this needs remaining times for up to PCIe Gen4 if RC mode.
*/
- if (changes && rcar->mode == DW_PCIE_RC_TYPE)
+ if (changes && rcar->platdata->mode == DW_PCIE_RC_TYPE)
changes--;
for (i = 0; i < changes; i++) {
@@ -172,9 +176,9 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
val = readl(rcar->base + PCIEMSR0);
- if (rcar->mode == DW_PCIE_RC_TYPE) {
+ if (rcar->platdata->mode == DW_PCIE_RC_TYPE) {
val |= DEVICE_TYPE_RC;
- } else if (rcar->mode == DW_PCIE_EP_TYPE) {
+ } else if (rcar->platdata->mode == DW_PCIE_EP_TYPE) {
val |= DEVICE_TYPE_EP;
} else {
ret = -EINVAL;
@@ -437,9 +441,9 @@ static void rcar_gen4_remove_dw_pcie_ep(struct rcar_gen4_pcie *rcar)
/* Common */
static int rcar_gen4_add_dw_pcie(struct rcar_gen4_pcie *rcar)
{
- rcar->mode = (uintptr_t)of_device_get_match_data(&rcar->pdev->dev);
+ rcar->platdata = of_device_get_match_data(&rcar->pdev->dev);
- switch (rcar->mode) {
+ switch (rcar->platdata->mode) {
case DW_PCIE_RC_TYPE:
return rcar_gen4_add_dw_pcie_rp(rcar);
case DW_PCIE_EP_TYPE:
@@ -480,7 +484,7 @@ static int rcar_gen4_pcie_probe(struct platform_device *pdev)
static void rcar_gen4_remove_dw_pcie(struct rcar_gen4_pcie *rcar)
{
- switch (rcar->mode) {
+ switch (rcar->platdata->mode) {
case DW_PCIE_RC_TYPE:
rcar_gen4_remove_dw_pcie_rp(rcar);
break;
@@ -500,14 +504,22 @@ static void rcar_gen4_pcie_remove(struct platform_device *pdev)
rcar_gen4_pcie_unprepare(rcar);
}
+static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie = {
+ .mode = DW_PCIE_RC_TYPE,
+};
+
+static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie_ep = {
+ .mode = DW_PCIE_EP_TYPE,
+};
+
static const struct of_device_id rcar_gen4_pcie_of_match[] = {
{
.compatible = "renesas,rcar-gen4-pcie",
- .data = (void *)DW_PCIE_RC_TYPE,
+ .data = &platdata_rcar_gen4_pcie,
},
{
.compatible = "renesas,rcar-gen4-pcie-ep",
- .data = (void *)DW_PCIE_EP_TYPE,
+ .data = &platdata_rcar_gen4_pcie_ep,
},
{},
};
--
2.25.1
^ permalink raw reply related
* [PATCH v3 5/7] PCI: dwc: rcar-gen4: Add .ltssm_enable() for other SoC support
From: Yoshihiro Shimoda @ 2024-04-01 2:39 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
In-Reply-To: <20240401023942.134704-1-yoshihiro.shimoda.uh@renesas.com>
This driver can reuse other R-Car Gen4 SoCs support like r8a779g0 and
r8a779h0. However, r8a779g0 and r8a779h0 require other initializing
settings that differ than r8a779f0. So, add a new function pointer
.ltssm_enable() for it. No behavior changes.
After applied this patch, probing SoCs by rcar_gen4_pcie_of_match[]
will be changed like below:
- r8a779f0 as "renesas,r8a779f0-pcie" and "renesas,r8a779f0-pcie-ep"
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 41 ++++++++++++++++++---
1 file changed, 36 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index da2821d6efce..e760bcd30c4e 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -48,7 +48,9 @@
#define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000
#define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800
+struct rcar_gen4_pcie;
struct rcar_gen4_pcie_platdata {
+ int (*ltssm_enable)(struct rcar_gen4_pcie *rcar);
enum dw_pcie_device_mode mode;
};
@@ -61,8 +63,8 @@ struct rcar_gen4_pcie {
#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
/* Common */
-static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
- bool enable)
+static void rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar,
+ bool enable)
{
u32 val;
@@ -127,9 +129,13 @@ static int rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
{
struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
- int i, changes;
+ int i, changes, ret;
- rcar_gen4_pcie_ltssm_enable(rcar, true);
+ if (rcar->platdata->ltssm_enable) {
+ ret = rcar->platdata->ltssm_enable(rcar);
+ if (ret)
+ return ret;
+ }
/*
* Require direct speed change with retrying here if the link_gen is
@@ -157,7 +163,7 @@ static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
{
struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
- rcar_gen4_pcie_ltssm_enable(rcar, false);
+ rcar_gen4_pcie_ltssm_control(rcar, false);
}
static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
@@ -504,6 +510,23 @@ static void rcar_gen4_pcie_remove(struct platform_device *pdev)
rcar_gen4_pcie_unprepare(rcar);
}
+static int r8a779f0_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar)
+{
+ rcar_gen4_pcie_ltssm_control(rcar, true);
+
+ return 0;
+}
+
+static struct rcar_gen4_pcie_platdata platdata_r8a779f0_pcie = {
+ .ltssm_enable = r8a779f0_pcie_ltssm_enable,
+ .mode = DW_PCIE_RC_TYPE,
+};
+
+static struct rcar_gen4_pcie_platdata platdata_r8a779f0_pcie_ep = {
+ .ltssm_enable = r8a779f0_pcie_ltssm_enable,
+ .mode = DW_PCIE_EP_TYPE,
+};
+
static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie = {
.mode = DW_PCIE_RC_TYPE,
};
@@ -513,6 +536,14 @@ static struct rcar_gen4_pcie_platdata platdata_rcar_gen4_pcie_ep = {
};
static const struct of_device_id rcar_gen4_pcie_of_match[] = {
+ {
+ .compatible = "renesas,r8a779f0-pcie",
+ .data = &platdata_r8a779f0_pcie,
+ },
+ {
+ .compatible = "renesas,r8a779f04-pcie-ep",
+ .data = &platdata_r8a779f0_pcie_ep,
+ },
{
.compatible = "renesas,rcar-gen4-pcie",
.data = &platdata_rcar_gen4_pcie,
--
2.25.1
^ permalink raw reply related
* [PATCH v3 2/7] dt-bindings: PCI: rcar-gen4-pci-ep: Add R-Car V4H compatible
From: Yoshihiro Shimoda @ 2024-04-01 2:39 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Conor Dooley, Geert Uytterhoeven
In-Reply-To: <20240401023942.134704-1-yoshihiro.shimoda.uh@renesas.com>
Document bindings for R-Car V4H (R8A779G0) PCIe endpoint module.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
index fe38f62da066..91b81ac75592 100644
--- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
@@ -16,7 +16,9 @@ allOf:
properties:
compatible:
items:
- - const: renesas,r8a779f0-pcie-ep # R-Car S4-8
+ - enum:
+ - renesas,r8a779f0-pcie-ep # R-Car S4-8
+ - renesas,r8a779g0-pcie-ep # R-Car V4H
- const: renesas,rcar-gen4-pcie-ep # R-Car Gen4
reg:
--
2.25.1
^ permalink raw reply related
* [PATCH v3 3/7] PCI: dwc: Add PCIE_PORT_{FORCE,LANE_SKEW} macros
From: Yoshihiro Shimoda @ 2024-04-01 2:39 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
In-Reply-To: <20240401023942.134704-1-yoshihiro.shimoda.uh@renesas.com>
R-Car Gen4 PCIe controller needs to use the Synopsys-specific PCIe
configuration registers. So, add the macros.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 26dae4837462..aa4db6eaf02a 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -71,6 +71,9 @@
#define LINK_WAIT_IATU 9
/* Synopsys-specific PCIe configuration registers */
+#define PCIE_PORT_FORCE 0x708
+#define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23)
+
#define PCIE_PORT_AFR 0x70C
#define PORT_AFR_N_FTS_MASK GENMASK(15, 8)
#define PORT_AFR_N_FTS(n) FIELD_PREP(PORT_AFR_N_FTS_MASK, n)
@@ -92,6 +95,9 @@
#define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7)
#define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf)
+#define PCIE_PORT_LANE_SKEW 0x714
+#define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0)
+
#define PCIE_PORT_DEBUG0 0x728
#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
#define PORT_LOGIC_LTSSM_STATE_L0 0x11
--
2.25.1
^ permalink raw reply related
* [PATCH v3 0/7] PCI: dwc: rcar-gen4: Add R-Car V4H support
From: Yoshihiro Shimoda @ 2024-04-01 2:39 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
The pcie-rcar-gen4 driver can reuse other R-Car Gen4 support like
r8a779g0 (R-Car V4H) and r8a779h0 (R-Car V4M). However, some
initializing settings differ between R-Car S4-8 (r8a779f0) and
others. The R-Car S4-8 will be minority about the setting way. So,
R-Car V4H will be majority and this is generic initialization way
as "renesas,rcar-gen4-pcie{-ep}" compatible. For now, I tested
both R-Car S4-8 and R-Car V4H on this driver. I'll support one more
other SoC (R-Car V4M) in the future.
Changes from v2:
https://lore.kernel.org/linux-pci/20240326024540.2336155-1-yoshihiro.shimoda.uh@renesas.com/
- Add a new patch which just add a platdata in patch 4/7.
- Modify the subjects in patch [56]/7.
- Modify the description and code about Bjorn's comment in patch [56]/7.
- Add missing MODULE_FIRMWARE(9 in patch 6/7.
- Document a policy aboud adding pci_device_id instead of adding r8a779g0's id
in patch 7/7.
Changes from v1:
https://lore.kernel.org/linux-pci/20240229120719.2553638-1-yoshihiro.shimoda.uh@renesas.com/
- Based on v6.9-rc1.
- Add Acked-by and/or Reviewed-by in patch [126/6].
Yoshihiro Shimoda (7):
dt-bindings: PCI: rcar-gen4-pci-host: Add R-Car V4H compatible
dt-bindings: PCI: rcar-gen4-pci-ep: Add R-Car V4H compatible
PCI: dwc: Add PCIE_PORT_{FORCE,LANE_SKEW} macros
PCI: dwc: rcar-gen4: Add rcar_gen4_pcie_platdata
PCI: dwc: rcar-gen4: Add .ltssm_enable() for other SoC support
PCI: dwc: rcar-gen4: Add support for r8a779g0
misc: pci_endpoint_test: Document a policy about adding pci_device_id
.../bindings/pci/rcar-gen4-pci-ep.yaml | 4 +-
.../bindings/pci/rcar-gen4-pci-host.yaml | 4 +-
drivers/misc/pci_endpoint_test.c | 1 +
drivers/pci/controller/dwc/pcie-designware.h | 6 +
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 272 +++++++++++++++++-
5 files changed, 270 insertions(+), 17 deletions(-)
--
2.25.1
^ permalink raw reply
* [PATCH v3 1/7] dt-bindings: PCI: rcar-gen4-pci-host: Add R-Car V4H compatible
From: Yoshihiro Shimoda @ 2024-04-01 2:39 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Conor Dooley, Geert Uytterhoeven
In-Reply-To: <20240401023942.134704-1-yoshihiro.shimoda.uh@renesas.com>
Document bindings for R-Car V4H (R8A779G0) PCIe host module.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
index ffb34339b637..955c664f1fbb 100644
--- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
@@ -16,7 +16,9 @@ allOf:
properties:
compatible:
items:
- - const: renesas,r8a779f0-pcie # R-Car S4-8
+ - enum:
+ - renesas,r8a779f0-pcie # R-Car S4-8
+ - renesas,r8a779g0-pcie # R-Car V4H
- const: renesas,rcar-gen4-pcie # R-Car Gen4
reg:
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v4 1/2] arm64: dts: qcom: sm8650: add GPU nodes
From: Jun Nie @ 2024-04-01 2:25 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Neil Armstrong, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <3e15fd38-13d1-4b99-aaf0-f422b2dbab59@linaro.org>
Konrad Dybcio <konrad.dybcio@linaro.org> 于2024年3月27日周三 08:24写道：
>
> On 18.03.2024 11:09 AM, Neil Armstrong wrote:
> > Add GPU nodes for the SM8650 platform.
> >
> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> > ---
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
Acked-by: Jun Nie <jun.nie@linaro.org>
^ permalink raw reply
* Re: [PATCH v4 2/2] arm64: dts: qcom: sm8650-qrd: enable GPU
From: Jun Nie @ 2024-04-01 2:23 UTC (permalink / raw)
To: Neil Armstrong
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240318-topic-sm8650-gpu-v4-2-206eb0d31694@linaro.org>
Neil Armstrong <neil.armstrong@linaro.org> 于2024年3月18日周一 18:12写道：
>
> Add path of the GPU firmware for the SM8650-QRD board
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
^ permalink raw reply
* RE: [v1 0/3] Add i.MX8Q HSIO PHY driver support
From: Hongxing Zhu @ 2024-04-01 2:13 UTC (permalink / raw)
To: Krzysztof Kozlowski, vkoul@kernel.org, kishon@kernel.org,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, Frank Li
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de, dl-linux-imx
In-Reply-To: <0b5997e9-97b3-4863-87d0-b70e9d051d42@linaro.org>
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: 2024年3月30日 19:55
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; vkoul@kernel.org;
> kishon@kernel.org; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> conor+dt@kernel.org; Frank Li <frank.li@nxp.com>
> Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [v1 0/3] Add i.MX8Q HSIO PHY driver support
>
> On 29/03/2024 09:09, Richard Zhu wrote:
> > v1 changes:
> > - Rebase to the 6.9-rc1, and constify of_phandle_args in xlate.
> > No other changes.
> >
>
> I found some RFC of this... confusing so:
> 1. v1 is the first version. If you send RFC, that RFC is v1, so anything newer is v2 or
> whatever.
>
> 2. One patchset per 24h. Give people chance to actually review your code.
Okay, got that.
Thanks for your comments and suggests.
Best Regards
Richard Zhu
>
> Best regards,
> Krzysztof
^ permalink raw reply
* RE: [PATCH v1 2/3] dt-bindings: phy: phy-imx8-pcie: Add binding for i.MX8Q HSIO SerDes PHY
From: Hongxing Zhu @ 2024-04-01 2:12 UTC (permalink / raw)
To: Frank Li
Cc: vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de, dl-linux-imx
In-Reply-To: <ZgbOTgtdEBJyg/By@lizhi-Precision-Tower-5810>
> -----Original Message-----
> From: Frank Li <frank.li@nxp.com>
> Sent: 2024年3月29日 22:21
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: vkoul@kernel.org; kishon@kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH v1 2/3] dt-bindings: phy: phy-imx8-pcie: Add binding for
> i.MX8Q HSIO SerDes PHY
>
> On Fri, Mar 29, 2024 at 04:09:49PM +0800, Richard Zhu wrote:
> > Add binding for controller ID and HSIO configuration setting of the
> > i.MX8Q HSIO SerDes PHY.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> > include/dt-bindings/phy/phy-imx8-pcie.h | 26
> > +++++++++++++++++++++++++
> > 1 file changed, 26 insertions(+)
>
> This one should be first patch. (1/3).
>
> After fix small improve
>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
>
Thanks for your review.
> >
> > diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h
> > b/include/dt-bindings/phy/phy-imx8-pcie.h
> > index 8bbe2d6538d8..5cd5580879fa 100644
> > --- a/include/dt-bindings/phy/phy-imx8-pcie.h
> > +++ b/include/dt-bindings/phy/phy-imx8-pcie.h
> > @@ -11,4 +11,30 @@
> > #define IMX8_PCIE_REFCLK_PAD_INPUT 1
> > #define IMX8_PCIE_REFCLK_PAD_OUTPUT 2
> >
> > +/*
> > + * i.MX8QM HSIO subsystem has three lane PHYs and three controllers:
> > + * PCIEA(2 lanes capapble PCIe controller), PCIEB (only support one
> > + * lane) and SATA.
>
> Suggest add empty line between segment.
>
Okay, would be added later. Thanks.
Best Regards
Richard Zhu
> > + * In the different use cases. PCIEA can be binded to PHY lane0,
> > +lane1
> > + * or Lane0 and lane1. PCIEB can be binded to lane1 or lane2 PHY.
> > +SATA
> > + * can only be binded to last lane2 PHY.
> > + * Define i.MX8Q HSIO controller ID here to specify the controller
> > + * binded to the PHY.
> > + * Meanwhile, i.MX8QXP HSIO subsystem has one lane PHY and PCIEB(only
> > + * support one lane) controller.
> > + */
> > +#define IMX8Q_HSIO_PCIEA_ID 0
> > +#define IMX8Q_HSIO_PCIEB_ID 1
> > +#define IMX8Q_HSIO_SATA_ID 2
> > +
> > +/*
> > + * On i.MX8QM, PCIEA is mandatory required if the HSIO is enabled.
> > + * Define configurations beside PCIEA is enabled.
> > + * On i.MX8QXP, HSIO module only has PCIEB and one lane PHY.
> > + * The "IMX8Q_HSIO_CFG_PCIEB" can be used on i.MX8QXP platforms.
> > + */
> > +#define IMX8Q_HSIO_CFG_SATA 1
> > +#define IMX8Q_HSIO_CFG_PCIEB 2
> > +#define IMX8Q_HSIO_CFG_PCIEBSATA 3
> > +
> > #endif /* _DT_BINDINGS_IMX8_PCIE_H */
> > --
> > 2.37.1
> >
^ permalink raw reply
* RE: [v1 0/3] Add i.MX8Q HSIO PHY driver support
From: Hongxing Zhu @ 2024-04-01 2:12 UTC (permalink / raw)
To: Frank Li
Cc: vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de, dl-linux-imx
In-Reply-To: <ZgbM4hpFhYW0QCHm@lizhi-Precision-Tower-5810>
> -----Original Message-----
> From: Frank Li <frank.li@nxp.com>
> Sent: 2024年3月29日 22:15
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: vkoul@kernel.org; kishon@kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [v1 0/3] Add i.MX8Q HSIO PHY driver support
>
> On Fri, Mar 29, 2024 at 04:09:47PM +0800, Richard Zhu wrote:
> > v1 changes:
> > - Rebase to the 6.9-rc1, and constify of_phandle_args in xlate.
> > No other changes.
>
> Next time please send to imx@lists.linux.dev instead of linux-imx@nxp.com.
>
> Frank
Okay, thanks for your review.
Best Regards
Richard Zhu
>
> >
> > i.MX8Q HSIO module has PHY and mix control regions.
> > This patch-set adds i.MX8Q HSIO PHY driver support, and provides
> > standard PHY phandles that can be used by i.MX8Q PCIe or SATA driver
> > later.
> >
> > [PATCH v1 1/3] dt-bindings: phy: Add i.MX8Q HSIO SerDes PHY binding
> > [PATCH v1 2/3] dt-bindings: phy: phy-imx8-pcie: Add binding for [PATCH
> > v1 3/3] phy: freescale: imx8q-hsio: Add i.MX8Q HSIO PHY driver
> >
> > Documentation/devicetree/bindings/phy/fsl,imx8q-hsio.yaml | 143
> ++++++++++++++++++++++++
> > drivers/phy/freescale/Kconfig | 8 ++
> > drivers/phy/freescale/Makefile | 1 +
> > drivers/phy/freescale/phy-fsl-imx8q-hsio.c | 518
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++
> > include/dt-bindings/phy/phy-imx8-pcie.h | 26 +++++
> > 5 files changed, 696 insertions(+)
^ permalink raw reply
* RE: [PATCH v5 0/4] Add support i.MX95 BLK CTL module clock features
From: Peng Fan @ 2024-04-01 1:32 UTC (permalink / raw)
To: Krzysztof Kozlowski, Peng Fan (OSS), Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Abel Vesa
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <e9809695-760e-42d2-a79c-bc2d4debdc32@linaro.org>
> Subject: Re: [PATCH v5 0/4] Add support i.MX95 BLK CTL module clock
> features
>
> On 31/03/2024 14:00, Peng Fan wrote:
> >> Subject: Re: [PATCH v5 0/4] Add support i.MX95 BLK CTL module clock
> >> features
> >>
> >> On 24/03/2024 08:51, Peng Fan (OSS) wrote:
> >>> i.MX95's several MIXes has BLK CTL module which could be used for
> >>> clk settings, QoS settings, Misc settings for a MIX. This patchset
> >>> is to add the clk feature support, including dt-bindings
> >>>
> >>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> >>> ---
> >>> Changes in v5:
> >>> - Merge bindings except the one has mux-controller
> >>> - Separate clock ID headers in a separate patch per Rob's comments
> >>
> >> Where did he suggest it?
> >
> > See
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Fall%2F20240315165422.GA1472059-
> robh%40kernel.org%2F&data
> >
> =05%7C02%7Cpeng.fan%40nxp.com%7C95289dc4bed24c3d125808dc51bc4
> 4e0%7C686
> >
> ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638475116243825697%7
> CUnknown%7
> >
> CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi
> LCJXV
> >
> CI6Mn0%3D%7C0%7C%7C%7C&sdata=Dt6KYhWwp%2B4NSwHJlXwUjyRqYU
> CkN0MvlSOE22w
> > vRE0%3D&reserved=0
> >
>
> He said under specific line about one specific define. There is absolutely
> nothing about splitting the header into new patch.
I misunderstood your point, I will put the header patch(patch 2/4) as the 1st patch
V6.
Thanks,
Peng.
>
> NAK
>
> Best regards,
> Krzysztof
^ permalink raw reply
* Re: [PATCH v4 1/4] arm64: dts: imx8: add cm40 subsystem dtsi
From: Peng Fan @ 2024-04-01 2:02 UTC (permalink / raw)
To: Frank Li
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree,
imx, linux-arm-kernel, linux-kernel, Dong Aisheng,
Alexander Stein
In-Reply-To: <20240329-m4_lpuart-v4-1-c11d9ca2a317@nxp.com>
On Fri, Mar 29, 2024 at 12:37:05PM -0400, Frank Li wrote:
>From: Dong Aisheng <aisheng.dong@nxp.com>
>
>Add cm40 subsystem dtsi.
>
>Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
>Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
>Signed-off-by: Frank Li <Frank.Li@nxp.com>
>---
> arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 67 +++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 +
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
> 3 files changed, 70 insertions(+)
>
>diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
>new file mode 100644
>index 0000000000000..10a05db06ade9
>--- /dev/null
>+++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
>@@ -0,0 +1,67 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * Copyright 2019 NXP
The time needs to be 2024, otherwise LGTM:
Reviewed-by: Peng Fan <peng.fan@nxp.com>
>+ * Dong Aisheng <aisheng.dong@nxp.com>
>+ */
>+
>+#include <dt-bindings/firmware/imx/rsrc.h>
>+
>+cm40_ipg_clk: clock-cm40-ipg {
>+ compatible = "fixed-clock";
>+ #clock-cells = <0>;
>+ clock-frequency = <132000000>;
>+ clock-output-names = "cm40_ipg_clk";
>+};
>+
>+cm40_subsys: bus@34000000 {
>+ compatible = "simple-bus";
>+ #address-cells = <1>;
>+ #size-cells = <1>;
>+ ranges = <0x34000000 0x0 0x34000000 0x4000000>;
>+ interrupt-parent = <&cm40_intmux>;
>+
>+ cm40_i2c: i2c@37230000 {
>+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
>+ reg = <0x37230000 0x1000>;
>+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
>+ clocks = <&cm40_i2c_lpcg IMX_LPCG_CLK_0>,
>+ <&cm40_i2c_lpcg IMX_LPCG_CLK_4>;
>+ clock-names = "per", "ipg";
>+ assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
>+ assigned-clock-rates = <24000000>;
>+ power-domains = <&pd IMX_SC_R_M4_0_I2C>;
>+ status = "disabled";
>+ };
>+
>+ cm40_intmux: intmux@37400000 {
>+ compatible = "fsl,imx-intmux";
>+ reg = <0x37400000 0x1000>;
>+ interrupt-parent = <&gic>;
>+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
>+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
>+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
>+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
>+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
>+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
>+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
>+ interrupt-controller;
>+ #interrupt-cells = <2>;
>+ clocks = <&cm40_ipg_clk>;
>+ clock-names = "ipg";
>+ power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
>+ status = "disabled";
>+ };
>+
>+ cm40_i2c_lpcg: clock-controller@37630000 {
>+ compatible = "fsl,imx8qxp-lpcg";
>+ reg = <0x37630000 0x1000>;
>+ #clock-cells = <1>;
>+ clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
>+ <&cm40_ipg_clk>;
>+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
>+ clock-output-names = "cm40_lpcg_i2c_clk",
>+ "cm40_lpcg_i2c_ipg_clk";
>+ power-domains = <&pd IMX_SC_R_M4_0_I2C>;
>+ };
>+};
>diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
>index a0674c5c55766..9d49c75a26222 100644
>--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
>+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
>@@ -5,6 +5,7 @@
>
> #include <dt-bindings/clock/imx8-clock.h>
> #include <dt-bindings/dma/fsl-edma.h>
>+#include <dt-bindings/clock/imx8-lpcg.h>
> #include <dt-bindings/firmware/imx/rsrc.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>@@ -231,6 +232,7 @@ xtal24m: clock-xtal24m {
> };
>
> /* sorted in register address */
>+ #include "imx8-ss-cm40.dtsi"
> #include "imx8-ss-adma.dtsi"
> #include "imx8-ss-conn.dtsi"
> #include "imx8-ss-ddr.dtsi"
>diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
>index 10e16d84c0c3b..0313f295de2e9 100644
>--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
>+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
>@@ -317,6 +317,7 @@ map0 {
> /* sorted in register address */
> #include "imx8-ss-img.dtsi"
> #include "imx8-ss-vpu.dtsi"
>+ #include "imx8-ss-cm40.dtsi"
> #include "imx8-ss-gpu0.dtsi"
> #include "imx8-ss-adma.dtsi"
> #include "imx8-ss-conn.dtsi"
>
>--
>2.34.1
>
--
^ permalink raw reply
* Re: [PATCH v2 17/18] dt-bindings: pci: rockchip,rk3399-pcie-ep: Add ep-gpios property
From: Damien Le Moal @ 2024-03-31 23:06 UTC (permalink / raw)
To: Krzysztof Kozlowski, Manivannan Sadhasivam, Lorenzo Pieralisi,
Kishon Vijay Abraham I, Shawn Lin, Krzysztof Wilczyński,
Bjorn Helgaas, Heiko Stuebner, linux-pci, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree
Cc: linux-rockchip, linux-arm-kernel, Rick Wertenbroek,
Wilfred Mallawa, Niklas Cassel
In-Reply-To: <b020b74e-8ae1-448a-9d47-6c9bb13735f9@linaro.org>
On 3/30/24 18:16, Krzysztof Kozlowski wrote:
> On 30/03/2024 05:19, Damien Le Moal wrote:
>> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>>
>> Describe the `ep-gpios` property which is used to map the PERST# input
>> signal for endpoint mode.
>>
>> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
>> ---
>> .../devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
>> index 6b62f6f58efe..9331d44d6963 100644
>> --- a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
>> +++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
>> @@ -30,6 +30,9 @@ properties:
>> maximum: 32
>> default: 32
>>
>> + ep-gpios:
>> + description: Input GPIO configured for the PERST# signal.
>
> Missing maxItems. But more important: why existing property perst-gpios,
> which you already have there in common schema, is not correct for this case?
I am confused... Where do you find perst-gpios defined for the rk3399 ?
Under Documentation/devicetree/bindings/pci/, the only schema I see using
perst-gpios property are for the qcom (Qualcomm) controllers.
The RC bindings for the rockchip rk3399 PCIe controller
(pci/rockchip,rk3399-pcie.yaml) already define the ep-gpios property. So if
anything, this patch should be probably be modified to move this property to the
common schema in pci/rockchip,rk3399-pcie-common.yaml.
No ?
>
> Best regards,
> Krzysztof
>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply
* [PATCH] arm64: dts: rockchip: Remove unsupported node from the Pinebook Pro dts
From: Dragan Simic @ 2024-03-31 22:20 UTC (permalink / raw)
To: linux-rockchip
Cc: heiko, linux-arm-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Remove a redundant node from the Pine64 Pinebook Pro dts, which is intended
to provide a value for the delay in PCI Express enumeration, but that isn't
supported without additional out-of-tree kernel patches.
There were already efforts to upstream those kernel patches, because they
reportedly make some PCI Express cards (such as LSI SAS HBAs) usable in
Pine64 RockPro64 (which is also based on the RK3399); otherwise, those PCI
Express cards fail to enumerate. However, providing the required background
and explanations proved to be a tough nut to crack, which is the reason why
those patches remain outside of the kernel mainline for now.
If those out-of-tree patches eventually become upstreamed, the resulting
device-tree changes will almost surely belong to the RK3399 SoC dtsi. Also,
the above-mentioned unusable-without-out-of-tree-patches PCI Express devices
are in all fairness not usable in a Pinebook Pro without some extensive
hardware modifications, which is another reason to delete this redundant
node. When it comes to the Pinebook Pro, only M.2 NVMe SSDs can be installed
out of the box (using an additional passive adapter PCB sold separately by
Pine64), which reportedly works fine with no additional patches.
Fixes: 5a65505a6988 ("arm64: dts: rockchip: Add initial support for Pinebook Pro")
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
---
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
index 054c6a4d1a45..294eb2de263d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
@@ -779,7 +779,6 @@ &pcie_phy {
};
&pcie0 {
- bus-scan-delay-ms = <1000>;
ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
^ permalink raw reply related
* Re: [PATCH v1 6/6] clk: meson: a1: add Amlogic A1 CPU clock controller driver
From: Martin Blumenstingl @ 2024-03-31 21:40 UTC (permalink / raw)
To: Dmitry Rokosov
Cc: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, kernel, rockosov, linux-amlogic,
linux-clk, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20240329205904.25002-7-ddrokosov@salutedevices.com>
Hi Dmitry,
On Fri, Mar 29, 2024 at 9:59 PM Dmitry Rokosov
<ddrokosov@salutedevices.com> wrote:
[...]
> +static struct clk_regmap cpu_fclk = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CPUCTRL_CLK_CTRL0,
> + .mask = 0x1,
> + .shift = 10,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "cpu_fclk",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &cpu_fsel0.hw,
> + &cpu_fsel1.hw,
Have you considered the CLK_SET_RATE_GATE flag for &cpu_fsel0.hw and
&cpu_fsel1.hw and then dropping the clock notifier below?
We use that approach with the Mali GPU clock on other SoCs, see for
example commit 8daeaea99caa ("clk: meson: meson8b: make the CCF use
the glitch-free mali mux").
It may differ from what Amlogic does in their BSP, but I don't think
that there's any harm (if it works in general) because CCF (common
clock framework) will set all clocks in the "inactive" tree and then
as a last step just change the mux (&cpu_fclk.hw). So at no point in
time will we get any other rate than a) the original CPU clock rate
before the rate change b) the new desired CPU clock rate. This is
because we have two symmetric clock trees.
Best regards,
Martin
^ permalink raw reply
* [PATCH 3/3] arm64: dts: msm8996: add fastrpc nodes
From: Dmitry Baryshkov @ 2024-03-31 21:10 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mathieu Poirier, Sibi Sankar
Cc: linux-arm-msm, devicetree, linux-remoteproc, linux-kernel,
Srinivas Kandagatla
In-Reply-To: <20240401-msm8996-remoteproc-v1-0-f02ab47fc728@linaro.org>
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
The ADSP provides fastrpc/compute capabilities. Enable support for the
fastrpc on this DSP.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 57 +++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 7ae499fa7d91..cf7ab01f3af6 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -3545,6 +3545,63 @@ q6routing: routing {
};
};
};
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,smd-channels = "fastrpcsmd-apps-dsp";
+ label = "adsp";
+ qcom,non-secure-domain;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+ iommus = <&lpass_q6_smmu 8>;
+ };
+
+ cb@9 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <9>;
+ iommus = <&lpass_q6_smmu 9>;
+ };
+
+ cb@10 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <10>;
+ iommus = <&lpass_q6_smmu 10>;
+ };
+
+ cb@11 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <11>;
+ iommus = <&lpass_q6_smmu 11>;
+ };
+
+ cb@12 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <12>;
+ iommus = <&lpass_q6_smmu 12>;
+ };
+
+ cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&lpass_q6_smmu 5>;
+ };
+
+ cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&lpass_q6_smmu 6>;
+ };
+
+ cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&lpass_q6_smmu 7>;
+ };
+ };
};
};
--
2.39.2
^ permalink raw reply related
* [PATCH 2/3] arm64: dts: qcom: msm8996: add glink-edge nodes
From: Dmitry Baryshkov @ 2024-03-31 21:10 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mathieu Poirier, Sibi Sankar
Cc: linux-arm-msm, devicetree, linux-remoteproc, linux-kernel
In-Reply-To: <20240401-msm8996-remoteproc-v1-0-f02ab47fc728@linaro.org>
MSM8996 provides limited glink support, so add corresponding device tree
nodes. For example the following interfaces are provided on db820c:
modem:
2080000.remoteproc:glink-edge.LOOPBACK_CTL_MPSS.-1.-1
2080000.remoteproc:glink-edge.glink_ssr.-1.-1
2080000.remoteproc:glink-edge.rpmsg_chrdev.0.0
adsp:
9300000.remoteproc:glink-edge.LOOPBACK_CTL_LPASS.-1.-1
9300000.remoteproc:glink-edge.glink_ssr.-1.-1
9300000.remoteproc:glink-edge.rpmsg_chrdev.0.0
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 1601e46549e7..7ae499fa7d91 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -2453,6 +2453,13 @@ slpi_pil: remoteproc@1c00000 {
status = "disabled";
+ glink-edge {
+ interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
+ label = "dsps";
+ qcom,remote-pid = <3>;
+ mboxes = <&apcs_glb 27>;
+ };
+
smd-edge {
interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
@@ -2522,6 +2529,13 @@ metadata {
memory-region = <&mdata_mem>;
};
+ glink-edge {
+ interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
+ label = "modem";
+ qcom,remote-pid = <1>;
+ mboxes = <&apcs_glb 15>;
+ };
+
smd-edge {
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
@@ -3467,6 +3481,14 @@ adsp_pil: remoteproc@9300000 {
status = "disabled";
+ glink-edge {
+ interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
+ label = "lpass";
+ qcom,remote-pid = <2>;
+ mboxes = <&apcs_glb 9>;
+ };
+
+
smd-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
--
2.39.2
^ permalink raw reply related
* [PATCH 0/3] arm64: dts: qcom: msm8996: enable fastrpc and glink-edge
From: Dmitry Baryshkov @ 2024-03-31 21:10 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mathieu Poirier, Sibi Sankar
Cc: linux-arm-msm, devicetree, linux-remoteproc, linux-kernel,
Srinivas Kandagatla
Enable the FastRPC and glink-edge nodes on MSM8996 platform. Tested on
APQ8096 Dragonboard820c.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Dmitry Baryshkov (2):
dt-bindings: remoteproc: qcom,msm8996-mss-pil: allow glink-edge on msm8996
arm64: dts: qcom: msm8996: add glink-edge nodes
Srinivas Kandagatla (1):
arm64: dts: msm8996: add fastrpc nodes
.../bindings/remoteproc/qcom,msm8996-mss-pil.yaml | 1 -
arch/arm64/boot/dts/qcom/msm8996.dtsi | 79 ++++++++++++++++++++++
2 files changed, 79 insertions(+), 1 deletion(-)
---
base-commit: 13ee4a7161b6fd938aef6688ff43b163f6d83e37
change-id: 20240320-msm8996-remoteproc-fccbc2b54ea1
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
^ permalink raw reply
* [PATCH 1/3] dt-bindings: remoteproc: qcom,msm8996-mss-pil: allow glink-edge on msm8996
From: Dmitry Baryshkov @ 2024-03-31 21:10 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mathieu Poirier, Sibi Sankar
Cc: linux-arm-msm, devicetree, linux-remoteproc, linux-kernel
In-Reply-To: <20240401-msm8996-remoteproc-v1-0-f02ab47fc728@linaro.org>
MSM8996 has limited glink support, allow glink-edge node on MSM8996
platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml
index 971734085d51..4d2055f283ac 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml
@@ -231,7 +231,6 @@ allOf:
- const: snoc_axi
- const: mnoc_axi
- const: qdss
- glink-edge: false
required:
- pll-supply
- smd-edge
--
2.39.2
^ permalink raw reply related
* [PATCH v2 12/12] drm/imx: move imx_drm_connector_destroy to imx-tve
From: Dmitry Baryshkov @ 2024-03-31 20:29 UTC (permalink / raw)
To: Philipp Zabel, David Airlie, Daniel Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam
Cc: Chris Healy, dri-devel, devicetree, imx, linux-arm-kernel,
Dmitry Baryshkov
In-Reply-To: <20240331-drm-imx-cleanup-v2-0-d81c1d1c1026@linaro.org>
The imx-tve driver is the only remaining user of
imx_drm_connector_destroy(). Move the function to imx-tve.c
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/imx/ipuv3/imx-drm-core.c | 7 -------
drivers/gpu/drm/imx/ipuv3/imx-drm.h | 2 --
drivers/gpu/drm/imx/ipuv3/imx-tve.c | 8 +++++++-
3 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c b/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c
index 4cfabcf7375a..189d395349b8 100644
--- a/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c
@@ -34,13 +34,6 @@ module_param(legacyfb_depth, int, 0444);
DEFINE_DRM_GEM_DMA_FOPS(imx_drm_driver_fops);
-void imx_drm_connector_destroy(struct drm_connector *connector)
-{
- drm_connector_unregister(connector);
- drm_connector_cleanup(connector);
-}
-EXPORT_SYMBOL_GPL(imx_drm_connector_destroy);
-
static int imx_drm_atomic_check(struct drm_device *dev,
struct drm_atomic_state *state)
{
diff --git a/drivers/gpu/drm/imx/ipuv3/imx-drm.h b/drivers/gpu/drm/imx/ipuv3/imx-drm.h
index e01f026047de..0c85bf83ffbf 100644
--- a/drivers/gpu/drm/imx/ipuv3/imx-drm.h
+++ b/drivers/gpu/drm/imx/ipuv3/imx-drm.h
@@ -25,8 +25,6 @@ extern struct platform_driver ipu_drm_driver;
int imx_drm_encoder_parse_of(struct drm_device *drm,
struct drm_encoder *encoder, struct device_node *np);
-void imx_drm_connector_destroy(struct drm_connector *connector);
-
int ipu_planes_assign_pre(struct drm_device *dev,
struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/imx/ipuv3/imx-tve.c b/drivers/gpu/drm/imx/ipuv3/imx-tve.c
index b49bddb85535..a5118504b522 100644
--- a/drivers/gpu/drm/imx/ipuv3/imx-tve.c
+++ b/drivers/gpu/drm/imx/ipuv3/imx-tve.c
@@ -307,9 +307,15 @@ static int imx_tve_atomic_check(struct drm_encoder *encoder,
return 0;
}
+static void imx_tve_connector_destroy(struct drm_connector *connector)
+{
+ drm_connector_unregister(connector);
+ drm_connector_cleanup(connector);
+}
+
static const struct drm_connector_funcs imx_tve_connector_funcs = {
.fill_modes = drm_helper_probe_single_connector_modes,
- .destroy = imx_drm_connector_destroy,
+ .destroy = imx_tve_connector_destroy,
.reset = drm_atomic_helper_connector_reset,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
--
2.39.2
^ permalink raw reply related
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