* [PATCH 2/2] ARM: boot: dts: microchip: at91-sama7g54_curiosity: Replace regulator-suspend-voltage with the valid property
From: Andrei Simion @ 2024-04-02 9:12 UTC (permalink / raw)
To: robh, krzysztof.kozlowski+dt, conor+dt, nicolas.ferre,
alexandre.belloni, claudiu.beznea, mihai.sain
Cc: linux-arm-kernel, linux-kernel, devicetree, Andrei Simion
In-Reply-To: <20240402091228.110362-1-andrei.simion@microchip.com>
Replace regulator-suspend-voltage with regulator-suspend-microvolt.
Fixes: ebd6591f8ddb ("ARM: dts: microchip: sama7g54_curiosity: Add initial device tree of the board")
Signed-off-by: Andrei Simion <andrei.simion@microchip.com>
---
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts
index 4f609e9e510e..009d2c832421 100644
--- a/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts
+++ b/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts
@@ -242,7 +242,7 @@ vddcore: VDD_CORE {
regulator-state-standby {
regulator-on-in-suspend;
- regulator-suspend-voltage = <1150000>;
+ regulator-suspend-microvolt = <1150000>;
regulator-mode = <4>;
};
@@ -263,7 +263,7 @@ vddcpu: VDD_OTHER {
regulator-state-standby {
regulator-on-in-suspend;
- regulator-suspend-voltage = <1050000>;
+ regulator-suspend-microvolt = <1050000>;
regulator-mode = <4>;
};
@@ -280,7 +280,7 @@ vldo1: LDO1 {
regulator-always-on;
regulator-state-standby {
- regulator-suspend-voltage = <1800000>;
+ regulator-suspend-microvolt = <1800000>;
regulator-on-in-suspend;
};
@@ -296,7 +296,7 @@ vldo2: LDO2 {
regulator-always-on;
regulator-state-standby {
- regulator-suspend-voltage = <3300000>;
+ regulator-suspend-microvolt = <3300000>;
regulator-on-in-suspend;
};
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v2 1/2] arm64: dts: qcom: qcm6490-idp: Enable various remoteprocs
From: Dmitry Baryshkov @ 2024-04-02 9:16 UTC (permalink / raw)
To: Komal Bajaj
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, quic_tsoni
In-Reply-To: <20240402090349.30172-2-quic_kbajaj@quicinc.com>
On Tue, 2 Apr 2024 at 12:04, Komal Bajaj <quic_kbajaj@quicinc.com> wrote:
>
> Enable the ADSP, CDSP, MPSS and WPSS that are found on the SoC.
>
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 2/2] arm64: dts: qcom: qcs6490-rb3gen2: Enable various remoteprocs
From: Dmitry Baryshkov @ 2024-04-02 9:17 UTC (permalink / raw)
To: Komal Bajaj
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel, quic_tsoni
In-Reply-To: <20240402090349.30172-3-quic_kbajaj@quicinc.com>
On Tue, 2 Apr 2024 at 12:04, Komal Bajaj <quic_kbajaj@quicinc.com> wrote:
>
> Enable the ADSP, CDSP and WPSS that are found on qcs6490-rb3gen2.
No MPSS even for GPS?
Anyway,
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> index 97824c769ba3..a25431ddf922 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> @@ -434,6 +434,21 @@ &qupv3_id_0 {
> status = "okay";
> };
>
> +&remoteproc_adsp {
> + firmware-name = "qcom/qcm6490/adsp.mbn";
> + status = "okay";
> +};
> +
> +&remoteproc_cdsp {
> + firmware-name = "qcom/qcm6490/cdsp.mbn";
> + status = "okay";
> +};
> +
> +&remoteproc_wpss {
> + firmware-name = "qcom/qcm6490/wpss.mbn";
> + status = "okay";
> +};
> +
> &tlmm {
> gpio-reserved-ranges = <32 2>, /* ADSP */
> <48 4>; /* NFC */
> --
> 2.42.0
>
>
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH v2 2/2] iio: imu: inv_icm42600: add support of ICM-42688-P
From: inv.git-commit @ 2024-04-02 9:00 UTC (permalink / raw)
To: jic23, robh, krzysztof.kozlowski+dt, conor+dt
Cc: lars, linux-iio, devicetree, Jean-Baptiste Maneyrol
In-Reply-To: <20240402090046.764572-1-inv.git-commit@tdk.com>
From: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
Signed-off-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
---
drivers/iio/imu/inv_icm42600/inv_icm42600.h | 2 ++
drivers/iio/imu/inv_icm42600/inv_icm42600_core.c | 5 +++++
drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c | 3 +++
drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c | 3 +++
4 files changed, 13 insertions(+)
diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600.h b/drivers/iio/imu/inv_icm42600/inv_icm42600.h
index 0e290c807b0f..0566340b2660 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600.h
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600.h
@@ -22,6 +22,7 @@ enum inv_icm42600_chip {
INV_CHIP_ICM42602,
INV_CHIP_ICM42605,
INV_CHIP_ICM42622,
+ INV_CHIP_ICM42688,
INV_CHIP_ICM42631,
INV_CHIP_NB,
};
@@ -304,6 +305,7 @@ struct inv_icm42600_state {
#define INV_ICM42600_WHOAMI_ICM42602 0x41
#define INV_ICM42600_WHOAMI_ICM42605 0x42
#define INV_ICM42600_WHOAMI_ICM42622 0x46
+#define INV_ICM42600_WHOAMI_ICM42688 0x47
#define INV_ICM42600_WHOAMI_ICM42631 0x5C
/* User bank 1 (MSB 0x10) */
diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c
index a5e81906e37e..82e0a2e2ad70 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c
@@ -87,6 +87,11 @@ static const struct inv_icm42600_hw inv_icm42600_hw[INV_CHIP_NB] = {
.name = "icm42622",
.conf = &inv_icm42600_default_conf,
},
+ [INV_CHIP_ICM42688] = {
+ .whoami = INV_ICM42600_WHOAMI_ICM42688,
+ .name = "icm42688",
+ .conf = &inv_icm42600_default_conf,
+ },
[INV_CHIP_ICM42631] = {
.whoami = INV_ICM42600_WHOAMI_ICM42631,
.name = "icm42631",
diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c
index 1af559403ba6..ebb28f84ba98 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c
@@ -84,6 +84,9 @@ static const struct of_device_id inv_icm42600_of_matches[] = {
}, {
.compatible = "invensense,icm42622",
.data = (void *)INV_CHIP_ICM42622,
+ }, {
+ .compatible = "invensense,icm42688",
+ .data = (void *)INV_CHIP_ICM42688,
}, {
.compatible = "invensense,icm42631",
.data = (void *)INV_CHIP_ICM42631,
diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c
index 6be4ac794937..50217a10e0bb 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c
@@ -80,6 +80,9 @@ static const struct of_device_id inv_icm42600_of_matches[] = {
}, {
.compatible = "invensense,icm42622",
.data = (void *)INV_CHIP_ICM42622,
+ }, {
+ .compatible = "invensense,icm42688",
+ .data = (void *)INV_CHIP_ICM42688,
}, {
.compatible = "invensense,icm42631",
.data = (void *)INV_CHIP_ICM42631,
--
2.34.1
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^ permalink raw reply related
* [PATCH v3] clk: starfive: pll: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz
From: Xingyu Wu @ 2024-04-02 9:09 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Conor Dooley,
Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng, Xingyu Wu,
linux-kernel, linux-clk, linux-riscv, devicetree
CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
But now PLL0 rate is 1GHz and the cpu frequency loads become
333/500/500/1000MHz in fact.
So PLL0 rate should be default set to 1.5GHz. But setting the
PLL0 rate need certain steps:
1. Change the parent of cpu_root clock to OSC clock.
2. Change the divider of cpu_core if PLL0 rate is higher than
1.25GHz before CPUfreq boot.
3. Change the parent of cpu_root clock back to PLL0 clock.
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
Hi Stephen and Emil,
This patch fixes the issue about lower rate of CPUfreq[1] by setting PLL0
rate to 1.5GHz.
In order not to affect the cpu operation, setting the PLL0 rate need
certain steps. The cpu_root's parent clock should be changed first. And
the divider of the cpu_core clock should be set to 2 so they won't crash
when setting 1.5GHz without voltage regulation. Due to PLL driver boot
earlier than SYSCRG driver, cpu_core and cpu_root clocks are using by
ioremap().
[1]: https://github.com/starfive-tech/VisionFive2/issues/55
Previous patch link:
v2: https://lore.kernel.org/all/20230821152915.208366-1-xingyu.wu@starfivetech.com/
v1: https://lore.kernel.org/all/20230811033631.160912-1-xingyu.wu@starfivetech.com/
Thanks,
Xingyu Wu
---
.../jh7110-starfive-visionfive-2.dtsi | 5 +
.../clk/starfive/clk-starfive-jh7110-pll.c | 102 ++++++++++++++++++
2 files changed, 107 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 45b58b6f3df8..0c57d833fb29 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -336,6 +336,11 @@ &pwmdac {
status = "okay";
};
+&pllclk {
+ assigned-clocks = <&pllclk JH7110_PLLCLK_PLL0_OUT>;
+ assigned-clock-rates = <1500000000>;
+};
+
&qspi {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.c b/drivers/clk/starfive/clk-starfive-jh7110-pll.c
index 3598390e8fd0..7a53ded8d526 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-pll.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.c
@@ -24,11 +24,14 @@
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/starfive,jh7110-crg.h>
+#include "clk-starfive-jh7110.h"
+
/* this driver expects a 24MHz input frequency from the oscillator */
#define JH7110_PLL_OSC_RATE 24000000UL
@@ -72,6 +75,9 @@
#define JH7110_PLL_PREDIV_SHIFT 0
#define JH7110_PLL_PREDIV_MASK GENMASK(5, 0)
+#define JH7110_CPU_ROOT_MUX_OSC 0
+#define JH7110_CPU_ROOT_MUX_PLL0 1
+
enum jh7110_pll_mode {
JH7110_PLL_MODE_FRACTION,
JH7110_PLL_MODE_INTEGER,
@@ -140,6 +146,8 @@ struct jh7110_pll_data {
struct jh7110_pll_priv {
struct device *dev;
struct regmap *regmap;
+ void __iomem *syscrg_base;
+ bool is_first_set;
struct jh7110_pll_data pll[JH7110_PLLCLK_END];
};
@@ -275,6 +283,25 @@ static struct jh7110_pll_priv *jh7110_pll_priv_from(struct jh7110_pll_data *pll)
return container_of(pll, struct jh7110_pll_priv, pll[pll->idx]);
}
+static void jh7110_pll_syscrg_update_div(void __iomem *base,
+ unsigned int id,
+ unsigned int div)
+{
+ unsigned int reg = readl(base + id * 4);
+
+ writel((reg & ~JH71X0_CLK_DIV_MASK) | div, (base + id * 4));
+}
+
+static void jh7110_pll_syscrg_update_mux(void __iomem *base,
+ unsigned int id,
+ unsigned int mux)
+{
+ unsigned int reg = readl(base + id * 4);
+
+ writel((reg & ~JH71X0_CLK_MUX_MASK) | (mux << JH71X0_CLK_MUX_SHIFT),
+ (base + id * 4));
+}
+
static void jh7110_pll_regvals_get(struct regmap *regmap,
const struct jh7110_pll_info *info,
struct jh7110_pll_regvals *ret)
@@ -352,6 +379,47 @@ static int jh7110_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request
return 0;
}
+static bool jh7110_pll0_is_assigned_clock(struct device_node *node)
+{
+ struct of_phandle_args clkspec;
+ int ret;
+
+ ret = of_parse_phandle_with_args(node, "assigned-clocks",
+ "#clock-cells", 0, &clkspec);
+ if (ret < 0 || clkspec.np != node)
+ return false;
+
+ if (clkspec.args[0] == JH7110_PLLCLK_PLL0_OUT)
+ return true;
+
+ return false;
+}
+
+/*
+ * In order to not affect the cpu when the PLL0 rate is changing,
+ * we need to switch the parent of cpu_root clock to osc clock first,
+ * and then switch back after setting the PLL0 rate.
+ *
+ * If cpu rate rather than 1.25GHz, PMIC need to be set higher voltage.
+ * But the PMIC is controlled by CPUfreq and I2C, which boot later than
+ * PLL driver when using assigned_clock to set PLL0 rate. So set the
+ * CPU_CORE divider to 2(default 1) first and make sure the cpu rate is
+ * lower than 1.25G when pll0 rate will be set more than 1.25G.
+ */
+static void jh7110_pll0_rate_preset(struct jh7110_pll_priv *priv,
+ unsigned long rate)
+{
+ if (rate > 1250000000 && priv->is_first_set &&
+ jh7110_pll0_is_assigned_clock(priv->dev->of_node))
+ jh7110_pll_syscrg_update_div(priv->syscrg_base,
+ JH7110_SYSCLK_CPU_CORE, 2);
+
+ jh7110_pll_syscrg_update_mux(priv->syscrg_base,
+ JH7110_SYSCLK_CPU_ROOT,
+ JH7110_CPU_ROOT_MUX_OSC);
+ priv->is_first_set = false;
+}
+
static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
@@ -372,6 +440,9 @@ static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate,
return -EINVAL;
found:
+ if (pll->idx == JH7110_PLLCLK_PLL0_OUT)
+ jh7110_pll0_rate_preset(priv, rate);
+
if (val->mode == JH7110_PLL_MODE_FRACTION)
regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_FRAC_MASK,
val->frac << JH7110_PLL_FRAC_SHIFT);
@@ -387,6 +458,12 @@ static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate,
regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_POSTDIV1_MASK,
(u32)val->postdiv1 << JH7110_PLL_POSTDIV1_SHIFT);
+ /* Set parent of cpu_root back to PLL0 */
+ if (pll->idx == JH7110_PLLCLK_PLL0_OUT)
+ jh7110_pll_syscrg_update_mux(priv->syscrg_base,
+ JH7110_SYSCLK_CPU_ROOT,
+ JH7110_CPU_ROOT_MUX_PLL0);
+
return 0;
}
@@ -458,6 +535,8 @@ static int jh7110_pll_probe(struct platform_device *pdev)
struct jh7110_pll_priv *priv;
unsigned int idx;
int ret;
+ struct device_node *np;
+ struct resource res;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -489,6 +568,29 @@ static int jh7110_pll_probe(struct platform_device *pdev)
return ret;
}
+ priv->is_first_set = true;
+ np = of_find_compatible_node(NULL, NULL, "starfive,jh7110-syscrg");
+ if (!np) {
+ ret = PTR_ERR(np);
+ dev_err(priv->dev, "failed to get syscrg node\n");
+ goto np_put;
+ }
+
+ ret = of_address_to_resource(np, 0, &res);
+ if (ret) {
+ dev_err(priv->dev, "failed to get syscrg resource\n");
+ goto np_put;
+ }
+
+ priv->syscrg_base = ioremap(res.start, resource_size(&res));
+ if (!priv->syscrg_base)
+ ret = -ENOMEM;
+
+np_put:
+ of_node_put(np);
+ if (ret)
+ return ret;
+
return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_pll_get, priv);
}
--
2.25.1
^ permalink raw reply related
* Re: [PATCH 3/3] arm64: dts: rockchip: Remove UART2 from RGB30
From: Ahmad Fatoum @ 2024-04-02 9:27 UTC (permalink / raw)
To: Chris Morgan
Cc: Chris Morgan, linux-rockchip, linux-clk, devicetree, sboyd,
mturquette, heiko, conor+dt, krzysztof.kozlowski+dt, robh+dt
In-Reply-To: <DM4PR05MB9229E56DE3F587BD222E1402A5392@DM4PR05MB9229.namprd05.prod.outlook.com>
Hello Chris,
On 30.03.24 16:34, Chris Morgan wrote:
> On Sat, Mar 30, 2024 at 02:13:05PM +0100, Ahmad Fatoum wrote:
>> Hello Chris,
>>
>> On 18.10.23 17:33, Chris Morgan wrote:
>>> From: Chris Morgan <macromorgan@hotmail.com>
>>>
>>> The Powkiddy RGB30 has no onboard UART header, so remove the reference
>>> to it in the device tree. This was left on by mistake in the initial
>>> commit.
>>
>> Do you know if the UART is perhaps available over testpoints?
>
> There is not one as best I can tell on either the RGB30 or RK2023. The
> Powkiddy X55 does have UART, however. I was able to exploit the fact
> that the RGB30 is extremely similar to all of the Anbernic devices
> (such as the RG353 series) for the purposes of low-level development.
> Once I got a network connection I performed the rest of development
> over SSH, but prior to that I just developed on a different device.
Thanks for the info.
AFAICS, it should be possible to get a console by changing the pinmux
setting on the Game TF-Card:
SDMMC1_D0/UART6_RX_M0/GPIO2_A3_u
SDMMC1_D1/UART6_TX_M0/GPIO2_A4_u
SDMMC1_D2/UART7_RX_M0/GPIO2_A5_u
SDMMC1_D3/UART7_TX_M0/GPIO2_A6_u
SDMMC1_CMD/UART9_RX_M0/GPIO2_A7_u
SDMMC1_CLK/UART9_TX_M0/GPIO2_B0_d
I will give that a try.
Cheers,
Ahmad
>
> Thank you,
> Chris.
>
>>
>> If yes, having a DT-overlay upstream enabling it along with documentation could be useful.
>> If not, how do you do low-level debugging on the RBG30 in absence of the serial console?
>>
>> Thanks,
>> Ahmad
>>
>>>
>>> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
>>> ---
>>> arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts | 9 +++++++++
>>> 1 file changed, 9 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts
>>> index 3ebc21608213..1ead3c5c24b3 100644
>>> --- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts
>>> +++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts
>>> @@ -64,6 +64,10 @@ simple-audio-card,cpu {
>>>
>>> /delete-node/ &adc_keys;
>>>
>>> +&chosen {
>>> + /delete-property/ stdout-path;
>>> +};
>>> +
>>> &cru {
>>> assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
>>> <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
>>> @@ -149,4 +153,9 @@ rk817_charger: charger {
>>> };
>>> };
>>>
>>> +/* There is no UART header visible on the board for this device. */
>>> +&uart2 {
>>> + status = "disabled";
>>> +};
>>> +
>>> /delete-node/ &vibrator;
>>
>> --
>> Pengutronix e.K. | |
>> Steuerwalder Str. 21 | http://www.pengutronix.de/ |
>> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
>> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* Re: [PATCH v2 1/8] dt-bindings: clock: add Loongson-2K expand clock index
From: Binbin Zhou @ 2024-04-02 9:34 UTC (permalink / raw)
To: Huacai Chen
Cc: Binbin Zhou, Huacai Chen, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Yinbo Zhu,
loongson-kernel, linux-clk, devicetree, Xuerui Wang, loongarch,
Conor Dooley
In-Reply-To: <CAAhV-H5L=ff8k4a5PA7vaD5W8QRu3zWQa=-99bq4MsjUz3UQJQ@mail.gmail.com>
On Tue, Apr 2, 2024 at 2:58 PM Huacai Chen <chenhuacai@kernel.org> wrote:
>
> Hi, Binbin,
>
> On Mon, Apr 1, 2024 at 4:24 PM Binbin Zhou <zhoubinbin@loongson.cn> wrote:
> >
> > In the new Loongson-2K family of SoCs, more clock indexes are needed,
> > such as clock gates.
> > The patch adds these clock indexes
> >
> > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > include/dt-bindings/clock/loongson,ls2k-clk.h | 56 ++++++++++++-------
> > 1 file changed, 37 insertions(+), 19 deletions(-)
> >
> > diff --git a/include/dt-bindings/clock/loongson,ls2k-clk.h b/include/dt-bindings/clock/loongson,ls2k-clk.h
> > index 3bc4dfc193c2..4e6811eca8c6 100644
> > --- a/include/dt-bindings/clock/loongson,ls2k-clk.h
> > +++ b/include/dt-bindings/clock/loongson,ls2k-clk.h
> > @@ -7,24 +7,42 @@
> > #ifndef __DT_BINDINGS_CLOCK_LOONGSON2_H
> > #define __DT_BINDINGS_CLOCK_LOONGSON2_H
> >
> > -#define LOONGSON2_REF_100M 0
> > -#define LOONGSON2_NODE_PLL 1
> > -#define LOONGSON2_DDR_PLL 2
> > -#define LOONGSON2_DC_PLL 3
> > -#define LOONGSON2_PIX0_PLL 4
> > -#define LOONGSON2_PIX1_PLL 5
> > -#define LOONGSON2_NODE_CLK 6
> > -#define LOONGSON2_HDA_CLK 7
> > -#define LOONGSON2_GPU_CLK 8
> > -#define LOONGSON2_DDR_CLK 9
> > -#define LOONGSON2_GMAC_CLK 10
> > -#define LOONGSON2_DC_CLK 11
> > -#define LOONGSON2_APB_CLK 12
> > -#define LOONGSON2_USB_CLK 13
> > -#define LOONGSON2_SATA_CLK 14
> > -#define LOONGSON2_PIX0_CLK 15
> > -#define LOONGSON2_PIX1_CLK 16
> > -#define LOONGSON2_BOOT_CLK 17
> > -#define LOONGSON2_CLK_END 18
> > +#define LOONGSON2_REF_100M 0
> > +#define LOONGSON2_NODE_PLL 1
> > +#define LOONGSON2_DDR_PLL 2
> > +#define LOONGSON2_DC_PLL 3
> > +#define LOONGSON2_PIX0_PLL 4
> > +#define LOONGSON2_PIX1_PLL 5
> > +#define LOONGSON2_NODE_CLK 6
> > +#define LOONGSON2_HDA_CLK 7
> > +#define LOONGSON2_GPU_CLK 8
> > +#define LOONGSON2_DDR_CLK 9
> > +#define LOONGSON2_GMAC_CLK 10
> > +#define LOONGSON2_DC_CLK 11
> > +#define LOONGSON2_APB_CLK 12
> > +#define LOONGSON2_USB_CLK 13
> > +#define LOONGSON2_SATA_CLK 14
> > +#define LOONGSON2_PIX0_CLK 15
> > +#define LOONGSON2_PIX1_CLK 16
> > +#define LOONGSON2_BOOT_CLK 17
> > +
> > +/* Loongson-2K2000 */
> This line should be removed, because the below definition is not
> specific to Loongson-2K2000.
Yes, it was my mistake, I forgot to drop it.
I will fix it in the next version.
Thanks.
Binbin
>
> Huacai
>
> > +#define LOONGSON2_OUT0_GATE 18
> > +#define LOONGSON2_GMAC_GATE 19
> > +#define LOONGSON2_RIO_GATE 20
> > +#define LOONGSON2_DC_GATE 21
> > +#define LOONGSON2_GPU_GATE 22
> > +#define LOONGSON2_DDR_GATE 23
> > +#define LOONGSON2_HDA_GATE 24
> > +#define LOONGSON2_NODE_GATE 25
> > +#define LOONGSON2_EMMC_GATE 26
> > +#define LOONGSON2_PIX0_GATE 27
> > +#define LOONGSON2_PIX1_GATE 28
> > +#define LOONGSON2_OUT0_CLK 29
> > +#define LOONGSON2_RIO_CLK 30
> > +#define LOONGSON2_EMMC_CLK 31
> > +#define LOONGSON2_DES_CLK 32
> > +#define LOONGSON2_I2S_CLK 33
> > +#define LOONGSON2_MISC_CLK 34
> >
> > #endif
> > --
> > 2.43.0
> >
^ permalink raw reply
* Re: [PATCH v1 6/6] clk: meson: a1: add Amlogic A1 CPU clock controller driver
From: Jerome Brunet @ 2024-04-02 9:27 UTC (permalink / raw)
To: Dmitry Rokosov
Cc: Martin Blumenstingl, neil.armstrong, jbrunet, mturquette, sboyd,
robh+dt, krzysztof.kozlowski+dt, khilman, kernel, rockosov,
linux-amlogic, linux-clk, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20240401171237.qoewp2pgcdrqvc3e@CAB-WSD-L081021>
On Mon 01 Apr 2024 at 20:12, Dmitry Rokosov <ddrokosov@salutedevices.com> wrote:
> Hello Martin,
>
> Thank you for quick response. Please find my thoughts below.
>
> On Sun, Mar 31, 2024 at 11:40:13PM +0200, Martin Blumenstingl wrote:
>> Hi Dmitry,
>>
>> On Fri, Mar 29, 2024 at 9:59 PM Dmitry Rokosov
>> <ddrokosov@salutedevices.com> wrote:
>> [...]
>> > +static struct clk_regmap cpu_fclk = {
>> > + .data = &(struct clk_regmap_mux_data) {
>> > + .offset = CPUCTRL_CLK_CTRL0,
>> > + .mask = 0x1,
>> > + .shift = 10,
>> > + },
>> > + .hw.init = &(struct clk_init_data) {
>> > + .name = "cpu_fclk",
>> > + .ops = &clk_regmap_mux_ops,
>> > + .parent_hws = (const struct clk_hw *[]) {
>> > + &cpu_fsel0.hw,
>> > + &cpu_fsel1.hw,
>> Have you considered the CLK_SET_RATE_GATE flag for &cpu_fsel0.hw and
>> &cpu_fsel1.hw and then dropping the clock notifier below?
>> We use that approach with the Mali GPU clock on other SoCs, see for
>> example commit 8daeaea99caa ("clk: meson: meson8b: make the CCF use
>> the glitch-free mali mux").
>> It may differ from what Amlogic does in their BSP,
>
> Amlogic in their BSP takes a different approach, which is slightly
> different from mine. They cleverly change the parent of cpu_clk directly
> by forking the cpufreq driver to a custom version. I must admit, it's
> quite an "interesting and amazing" idea :) but it's not architecturally
> correct totally.
I disagree. Martin's suggestion is correct for the fsel part which is
symetric.
>
>> but I don't think
>> that there's any harm (if it works in general) because CCF (common
>> clock framework) will set all clocks in the "inactive" tree and then
>> as a last step just change the mux (&cpu_fclk.hw). So at no point in
>> time will we get any other rate than a) the original CPU clock rate
>> before the rate change b) the new desired CPU clock rate. This is
>> because we have two symmetric clock trees.
>
> Now, let's dive into the specifics of the issue we're facing. I've
> examined the CLK_SET_RATE_GATE flag, which, to my understanding, blocks
> rate changes for the entire clock chain. However, in this particular
> situation, it doesn't provide the solution we need.
>
> Here's the problem we're dealing with:
>
> 1) The CPU clock can have the following frequency points:
>
> available frequency steps: 128 MHz, 256 MHz, 512 MHz, 768 MHz, 1.01 GHz, 1.20 GHz
>
> When we run the cpupower, we get the following information:
> # cpupower -c 0,1 frequency-info
> analyzing CPU 0:
> driver: cpufreq-dt
> CPUs which run at the same hardware frequency: 0 1
> CPUs which need to have their frequency coordinated by software: 0 1
> maximum transition latency: 50.0 us
> hardware limits: 128 MHz - 1.20 GHz
> available frequency steps: 128 MHz, 256 MHz, 512 MHz, 768 MHz, 1.01 GHz, 1.20 GHz
> available cpufreq governors: conservative ondemand userspace performance schedutil
> current policy: frequency should be within 128 MHz and 128 MHz.
> The governor "schedutil" may decide which speed to use
> within this range.
> current CPU frequency: 128 MHz (asserted by call to hardware)
> analyzing CPU 1:
> driver: cpufreq-dt
> CPUs which run at the same hardware frequency: 0 1
> CPUs which need to have their frequency coordinated by software: 0 1
> maximum transition latency: 50.0 us
> hardware limits: 128 MHz - 1.20 GHz
> available frequency steps: 128 MHz, 256 MHz, 512 MHz, 768 MHz, 1.01 GHz, 1.20 GHz
> available cpufreq governors: conservative ondemand userspace performance schedutil
> current policy: frequency should be within 128 MHz and 128 MHz.
> The governor "schedutil" may decide which speed to use
> within this range.
> current CPU frequency: 128 MHz (asserted by call to hardware)
>
> 2) For the frequency points 128 MHz, 256 MHz, and 512 MHz, the CPU fixed
> clock should be used.
Apparently, you are relying on the SYS PLL lowest possible rate to
enfore this contraint, which I suppose is 24 * 32 = 768MHz. It would be
nice to clearly say so.
> Fortunately, we don't encounter any freeze
> problems when we attempt to change its rate at these frequencies.
That does not sound very solid ...
>
> 3) However, for the frequency points 768 MHz, 1.01 GHz, and 1.20 GHz,
> the sys_pll is used as the clock source because it's a faster option.
> Now, let's imagine that we want to change the CPU clock from 768 MHz to
> 1.01 GHz. Unfortunately, it's not possible due to the broken sys_pll,
> and any execution attempts will result in a hang.
... Because PLL needs to relock, it is going to be off for a while. That
is not "broken", unless there is something else ?
>
> 4) As you can observe, in this case, we actually don't need to lock the
> rate for the sys_pll chain.
In which case ? I'm lost.
> We want to change the rate instead.
... How are you going to do that without relocking the PLL ?
> Hence,
> I'm not aware of any other method to achieve this except by switching
> the cpu_clk parent to a stable clock using clock notifier block.
> Interestingly, I've noticed a similar approach in the CPU clock drivers
> of Rockchip, Qualcomm, and Mediatek.
There is an example of syspll notifier in the g12 clock controller.
You should have a look at it
--
Jerome
^ permalink raw reply
* Re: [PATCH v3 3/9] arm64: dts: qcom: sm8250: describe HS signals properly
From: Bryan O'Donoghue @ 2024-04-02 9:42 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss
In-Reply-To: <20240401-typec-fix-sm8250-v3-3-604dce3ad103@linaro.org>
On 01/04/2024 21:33, Dmitry Baryshkov wrote:
> Instead
> there is a HighSpeed signal lane between DWC3 controller and the USB-C
> connector.
I still don't think this is an accurate statement. The upstream names
and labels should be followed for consistency but role-switching and the
DP/DN lines on the type-c port are not related.
If you drop that sentence in your commit log, then add.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply
* [PATCH] arm64: dts: ti: k3-am62p-main: use eFuse MAC Address for CPSW3G Port 1
From: Siddharth Vadapalli @ 2024-04-02 9:42 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzysztof.kozlowski+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
Assign the MAC Address programmed in the eFuse registers as the default
MAC Address for CPSW3G MAC Port 1. Utilize the "ti,syscon-efuse"
device-tree property to do so.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
This patch is based on linux-next tagged next-20240402.
Regards,
Siddharth.
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
index 7337a9e13535..eb126f4a04dd 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
@@ -696,6 +696,7 @@ cpsw_port1: port@1 {
label = "port1";
phys = <&phy_gmii_sel 1>;
mac-address = [00 00 00 00 00 00];
+ ti,syscon-efuse = <&wkup_conf 0x200>;
};
cpsw_port2: port@2 {
--
2.40.1
^ permalink raw reply related
* Re: [PATCH 1/3] media: mediatek: vcodec: fix h264 multi statless decoder smatch warning
From: AngeloGioacchino Del Regno @ 2024-04-02 9:50 UTC (permalink / raw)
To: Yunfei Dong, Nícolas F . R . A . Prado, Nicolas Dufresne,
Hans Verkuil, Benjamin Gaignard, Nathan Hebert
Cc: Hsin-Yi Wang, Fritz Koenig, Daniel Vetter, Steve Cho, linux-media,
devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
In-Reply-To: <20240229095611.6698-2-yunfei.dong@mediatek.com>
Il 29/02/24 10:56, Yunfei Dong ha scritto:
> Fix smatch static checker warning for vdec_h264_req_multi_if.c.
> Leading to kernel crash when fb is NULL.
>
> Fixes: 397edc703a10 ("media: mediatek: vcodec: add h264 decoder")
> Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
> ---
> .../vcodec/decoder/vdec/vdec_h264_req_multi_if.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
> index 0e741e0dc8ba..ab8e708e0df1 100644
> --- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
> +++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c
> @@ -724,11 +724,16 @@ static int vdec_h264_slice_single_decode(void *h_vdec, struct mtk_vcodec_mem *bs
> return vpu_dec_reset(vpu);
>
> fb = inst->ctx->dev->vdec_pdata->get_cap_buffer(inst->ctx);
> + if (!fb) {
> + mtk_vdec_err(inst->ctx, "fb buffer is NULL");
> + return -EBUSY;
> + }
> +
> src_buf_info = container_of(bs, struct mtk_video_dec_buf, bs_buffer);
> dst_buf_info = container_of(fb, struct mtk_video_dec_buf, frame_buffer);
>
> - y_fb_dma = fb ? (u64)fb->base_y.dma_addr : 0;
> - c_fb_dma = fb ? (u64)fb->base_c.dma_addr : 0;
You're changing the behavior here, can you please explain why this change is valid
into the commit description?
Thanks,
Angelo
> + y_fb_dma = (u64)fb->base_y.dma_addr;
> + c_fb_dma = (u64)fb->base_c.dma_addr;
> mtk_vdec_debug(inst->ctx, "[h264-dec] [%d] y_dma=%llx c_dma=%llx",
> inst->ctx->decoded_frame_cnt, y_fb_dma, c_fb_dma);
>
^ permalink raw reply
* [PATCH v2 1/2] dt-bindings: iio: imu: add icm42688 inside inv_icm42600
From: inv.git-commit @ 2024-04-02 9:00 UTC (permalink / raw)
To: jic23, robh, krzysztof.kozlowski+dt, conor+dt
Cc: lars, linux-iio, devicetree, Jean-Baptiste Maneyrol
In-Reply-To: <20240402090046.764572-1-inv.git-commit@tdk.com>
From: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
Add bindings for ICM-42688-P chip.
Signed-off-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
---
.../devicetree/bindings/iio/imu/invensense,icm42600.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
index 7cd05bcbee31..5e0bed2c45de 100644
--- a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
+++ b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
@@ -32,6 +32,7 @@ properties:
- invensense,icm42605
- invensense,icm42622
- invensense,icm42631
+ - invensense,icm42688
reg:
maxItems: 1
--
2.34.1
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^ permalink raw reply related
* Re: [PATCH] arm64: dts: ti: k3-am62p-main: use eFuse MAC Address for CPSW3G Port 1
From: Vignesh Raghavendra @ 2024-04-02 9:55 UTC (permalink / raw)
To: Siddharth Vadapalli, nm, kristo, robh, krzysztof.kozlowski+dt,
conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, srk
In-Reply-To: <20240402094200.4036076-1-s-vadapalli@ti.com>
On 02/04/24 15:12, Siddharth Vadapalli wrote:
> Assign the MAC Address programmed in the eFuse registers as the default
> MAC Address for CPSW3G MAC Port 1. Utilize the "ti,syscon-efuse"
> device-tree property to do so.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>
> This patch is based on linux-next tagged next-20240402.
>
> Regards,
> Siddharth.
>
> arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
> index 7337a9e13535..eb126f4a04dd 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
> @@ -696,6 +696,7 @@ cpsw_port1: port@1 {
> label = "port1";
> phys = <&phy_gmii_sel 1>;
> mac-address = [00 00 00 00 00 00];
> + ti,syscon-efuse = <&wkup_conf 0x200>;
Sorry, how does this work? wkup_conf is not marked as "syscon" compatible?
> };
>
> cpsw_port2: port@2 {
--
Regards
Vignesh
^ permalink raw reply
* Re: [PATCH v1 6/6] clk: meson: a1: add Amlogic A1 CPU clock controller driver
From: Jerome Brunet @ 2024-04-02 9:35 UTC (permalink / raw)
To: Dmitry Rokosov
Cc: neil.armstrong, jbrunet, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, khilman, martin.blumenstingl, kernel,
rockosov, linux-amlogic, linux-clk, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20240329205904.25002-7-ddrokosov@salutedevices.com>
On Fri 29 Mar 2024 at 23:58, Dmitry Rokosov <ddrokosov@salutedevices.com> wrote:
> The CPU clock controller plays a general role in the Amlogic A1 SoC
> family by generating CPU clocks. As an APB slave module, it offers the
> capability to inherit the CPU clock from two sources: the internal fixed
> clock known as 'cpu fixed clock' and the external input provided by the
> A1 PLL clock controller, referred to as 'syspll'.
>
> It is important for the driver to handle cpu_clk rate switching
> effectively by transitioning to the CPU fixed clock to avoid any
> potential execution freezes.
>
> Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
> ---
> drivers/clk/meson/Kconfig | 10 ++
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/a1-cpu.c | 324 +++++++++++++++++++++++++++++++++++++
> drivers/clk/meson/a1-cpu.h | 16 ++
> 4 files changed, 351 insertions(+)
> create mode 100644 drivers/clk/meson/a1-cpu.c
> create mode 100644 drivers/clk/meson/a1-cpu.h
>
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index 80c4a18c83d2..148d4495eee3 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -111,6 +111,16 @@ config COMMON_CLK_AXG_AUDIO
> Support for the audio clock controller on AmLogic A113D devices,
> aka axg, Say Y if you want audio subsystem to work.
>
> +config COMMON_CLK_A1_CPU
> + tristate "Amlogic A1 SoC CPU controller support"
> + depends on ARM64
> + select COMMON_CLK_MESON_REGMAP
> + select COMMON_CLK_MESON_CLKC_UTILS
> + help
> + Support for the CPU clock controller on Amlogic A113L based
> + device, A1 SoC Family. Say Y if you want A1 CPU clock controller
> + to work.
> +
> config COMMON_CLK_A1_PLL
> tristate "Amlogic A1 SoC PLL controller support"
> depends on ARM64
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 4968fc7ad555..2a06eb0303d6 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_AUDIO_RSTC) += meson-audio-rstc.o
>
> obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
> obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
> +obj-$(CONFIG_COMMON_CLK_A1_CPU) += a1-cpu.o
> obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
> obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
> obj-$(CONFIG_COMMON_CLK_A1_AUDIO) += a1-audio.o
> diff --git a/drivers/clk/meson/a1-cpu.c b/drivers/clk/meson/a1-cpu.c
> new file mode 100644
> index 000000000000..5f5d8ae112e5
> --- /dev/null
> +++ b/drivers/clk/meson/a1-cpu.c
> @@ -0,0 +1,324 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Amlogic A1 SoC family CPU Clock Controller driver.
> + *
> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
> + * Author: Dmitry Rokosov <ddrokosov@salutedevices.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/platform_device.h>
> +#include "a1-cpu.h"
> +#include "clk-regmap.h"
> +#include "meson-clkc-utils.h"
> +
> +#include <dt-bindings/clock/amlogic,a1-cpu-clkc.h>
> +
> +static u32 cpu_fsource_sel_table[] = { 0, 1, 2 };
> +static const struct clk_parent_data cpu_fsource_sel_parents[] = {
> + { .fw_name = "xtal" },
> + { .fw_name = "fclk_div2" },
> + { .fw_name = "fclk_div3" },
> +};
> +
> +static struct clk_regmap cpu_fsource_sel0 = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CPUCTRL_CLK_CTRL0,
> + .mask = 0x3,
> + .shift = 0,
> + .table = cpu_fsource_sel_table,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "cpu_fsource_sel0",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = cpu_fsource_sel_parents,
> + .num_parents = ARRAY_SIZE(cpu_fsource_sel_parents),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap cpu_fsource_div0 = {
> + .data = &(struct clk_regmap_div_data) {
> + .offset = CPUCTRL_CLK_CTRL0,
> + .shift = 4,
> + .width = 6,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "cpu_fsource_div0",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &cpu_fsource_sel0.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap cpu_fsel0 = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CPUCTRL_CLK_CTRL0,
> + .mask = 0x1,
> + .shift = 2,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "cpu_fsel0",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &cpu_fsource_sel0.hw,
> + &cpu_fsource_div0.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap cpu_fsource_sel1 = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CPUCTRL_CLK_CTRL0,
> + .mask = 0x3,
> + .shift = 16,
> + .table = cpu_fsource_sel_table,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "cpu_fsource_sel1",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = cpu_fsource_sel_parents,
> + .num_parents = ARRAY_SIZE(cpu_fsource_sel_parents),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap cpu_fsource_div1 = {
> + .data = &(struct clk_regmap_div_data) {
> + .offset = CPUCTRL_CLK_CTRL0,
> + .shift = 20,
> + .width = 6,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "cpu_fsource_div1",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &cpu_fsource_sel1.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap cpu_fsel1 = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CPUCTRL_CLK_CTRL0,
> + .mask = 0x1,
> + .shift = 18,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "cpu_fsel1",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &cpu_fsource_sel1.hw,
> + &cpu_fsource_div1.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap cpu_fclk = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CPUCTRL_CLK_CTRL0,
> + .mask = 0x1,
> + .shift = 10,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "cpu_fclk",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &cpu_fsel0.hw,
> + &cpu_fsel1.hw,
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap cpu_clk = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CPUCTRL_CLK_CTRL0,
> + .mask = 0x1,
> + .shift = 11,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "cpu_clk",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .hw = &cpu_fclk.hw },
> + { .fw_name = "sys_pll", },
> + },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> + },
> +};
> +
> +/* Array of all clocks registered by this provider */
> +static struct clk_hw *a1_cpu_hw_clks[] = {
> + [CLKID_CPU_FSOURCE_SEL0] = &cpu_fsource_sel0.hw,
> + [CLKID_CPU_FSOURCE_DIV0] = &cpu_fsource_div0.hw,
> + [CLKID_CPU_FSEL0] = &cpu_fsel0.hw,
> + [CLKID_CPU_FSOURCE_SEL1] = &cpu_fsource_sel1.hw,
> + [CLKID_CPU_FSOURCE_DIV1] = &cpu_fsource_div1.hw,
> + [CLKID_CPU_FSEL1] = &cpu_fsel1.hw,
> + [CLKID_CPU_FCLK] = &cpu_fclk.hw,
> + [CLKID_CPU_CLK] = &cpu_clk.hw,
> +};
> +
> +static struct clk_regmap *const a1_cpu_regmaps[] = {
> + &cpu_fsource_sel0,
> + &cpu_fsource_div0,
> + &cpu_fsel0,
> + &cpu_fsource_sel1,
> + &cpu_fsource_div1,
> + &cpu_fsel1,
> + &cpu_fclk,
> + &cpu_clk,
> +};
> +
> +static struct regmap_config a1_cpu_regmap_cfg = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = CPUCTRL_CLK_CTRL1,
> +};
> +
> +static struct meson_clk_hw_data a1_cpu_clks = {
> + .hws = a1_cpu_hw_clks,
> + .num = ARRAY_SIZE(a1_cpu_hw_clks),
> +};
> +
> +struct a1_cpu_clk_nb_data {
> + const struct clk_ops *mux_ops;
That's fishy ...
> + struct clk_hw *cpu_clk;
> + struct notifier_block nb;
> + u8 parent;
> +};
> +
> +#define MESON_A1_CPU_CLK_GET_PARENT(nbd) \
> + ((nbd)->mux_ops->get_parent((nbd)->cpu_clk))
> +#define MESON_A1_CPU_CLK_SET_PARENT(nbd, index) \
> + ((nbd)->mux_ops->set_parent((nbd)->cpu_clk, index))
... Directly going for the mux ops ??!?? No way !
We have a framework to handle the clocks, the whole point is to use it,
not bypass it !
> +
> +static int meson_a1_cpu_clk_notifier_cb(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct a1_cpu_clk_nb_data *nbd;
> + int ret = 0;
> +
> + nbd = container_of(nb, struct a1_cpu_clk_nb_data, nb);
> +
> + switch (event) {
> + case PRE_RATE_CHANGE:
> + nbd->parent = MESON_A1_CPU_CLK_GET_PARENT(nbd);
> + /* Fallback to the CPU fixed clock */
> + ret = MESON_A1_CPU_CLK_SET_PARENT(nbd, 0);
> + /* Wait for clock propagation */
> + udelay(100);
> + break;
> +
> + case POST_RATE_CHANGE:
> + case ABORT_RATE_CHANGE:
> + /* Back to the original parent clock */
> + ret = MESON_A1_CPU_CLK_SET_PARENT(nbd, nbd->parent);
> + /* Wait for clock propagation */
> + udelay(100);
> + break;
> +
> + default:
> + pr_warn("Unknown event %lu for %s notifier block\n",
> + event, clk_hw_get_name(nbd->cpu_clk));
> + break;
> + }
> +
> + return notifier_from_errno(ret);
> +}
> +
> +static struct a1_cpu_clk_nb_data a1_cpu_clk_nb_data = {
> + .mux_ops = &clk_regmap_mux_ops,
> + .cpu_clk = &cpu_clk.hw,
> + .nb.notifier_call = meson_a1_cpu_clk_notifier_cb,
> +};
> +
> +static int meson_a1_dvfs_setup(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct clk *notifier_clk;
> + int ret;
> +
> + /* Setup clock notifier for cpu_clk */
> + notifier_clk = devm_clk_hw_get_clk(dev, &cpu_clk.hw, "dvfs");
> + if (IS_ERR(notifier_clk))
> + return dev_err_probe(dev, PTR_ERR(notifier_clk),
> + "can't get cpu_clk as notifier clock\n");
> +
> + ret = devm_clk_notifier_register(dev, notifier_clk,
> + &a1_cpu_clk_nb_data.nb);
> + if (ret)
> + return dev_err_probe(dev, ret,
> + "can't register cpu_clk notifier\n");
> +
> + return ret;
> +}
> +
> +static int meson_a1_cpu_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + void __iomem *base;
> + struct regmap *map;
> + int clkid, i, err;
> +
> + base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(base))
> + return dev_err_probe(dev, PTR_ERR(base),
> + "can't ioremap resource\n");
> +
> + map = devm_regmap_init_mmio(dev, base, &a1_cpu_regmap_cfg);
> + if (IS_ERR(map))
> + return dev_err_probe(dev, PTR_ERR(map),
> + "can't init regmap mmio region\n");
> +
> + /* Populate regmap for the regmap backed clocks */
> + for (i = 0; i < ARRAY_SIZE(a1_cpu_regmaps); i++)
> + a1_cpu_regmaps[i]->map = map;
> +
> + for (clkid = 0; clkid < a1_cpu_clks.num; clkid++) {
> + err = devm_clk_hw_register(dev, a1_cpu_clks.hws[clkid]);
> + if (err)
> + return dev_err_probe(dev, err,
> + "clock[%d] registration failed\n",
> + clkid);
> + }
> +
> + err = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_cpu_clks);
> + if (err)
> + return dev_err_probe(dev, err, "can't add clk hw provider\n");
I wonder if there is a window of opportunity to poke the syspll without
your notifier here. That being said, the situation would be similar on g12.
> +
> + return meson_a1_dvfs_setup(pdev);
> +}
> +
> +static const struct of_device_id a1_cpu_clkc_match_table[] = {
> + { .compatible = "amlogic,a1-cpu-clkc", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, a1_cpu_clkc_match_table);
> +
> +static struct platform_driver a1_cpu_clkc_driver = {
> + .probe = meson_a1_cpu_probe,
> + .driver = {
> + .name = "a1-cpu-clkc",
> + .of_match_table = a1_cpu_clkc_match_table,
> + },
> +};
> +
> +module_platform_driver(a1_cpu_clkc_driver);
> +MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@salutedevices.com>");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/meson/a1-cpu.h b/drivers/clk/meson/a1-cpu.h
> new file mode 100644
> index 000000000000..e9af4117e26f
> --- /dev/null
> +++ b/drivers/clk/meson/a1-cpu.h
There is not point putting the definition here in a header
These are clearly not going to be shared with another driver.
Please drop this file
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Amlogic A1 CPU Clock Controller internals
> + *
> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
> + * Author: Dmitry Rokosov <ddrokosov@salutedevices.com>
> + */
> +
> +#ifndef __A1_CPU_H
> +#define __A1_CPU_H
> +
> +/* cpu clock controller register offset */
> +#define CPUCTRL_CLK_CTRL0 0x80
> +#define CPUCTRL_CLK_CTRL1 0x84
You are claiming the registers from 0x00 to 0x84 (included), but only
using these 2 registers ? What is the rest ? Are you sure there is only
clocks in there ?
> +
> +#endif /* __A1_CPU_H */
--
Jerome
^ permalink raw reply
* [PATCH v2 0/2] iio: imu: inv_icm42600: add support of ICM-42688-P
From: inv.git-commit @ 2024-04-02 9:00 UTC (permalink / raw)
To: jic23, robh, krzysztof.kozlowski+dt, conor+dt
Cc: lars, linux-iio, devicetree, Jean-Baptiste Maneyrol
From: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
This series is for adding support of high-end specs ICM-42688-P chip.
Changelog:
* v2: change order of chip definitions and order of patches
Jean-Baptiste Maneyrol (2):
dt-bindings: iio: imu: add icm42688 inside inv_icm42600
iio: imu: inv_icm42600: add support of ICM-42688-P
.../devicetree/bindings/iio/imu/invensense,icm42600.yaml | 1 +
drivers/iio/imu/inv_icm42600/inv_icm42600.h | 2 ++
drivers/iio/imu/inv_icm42600/inv_icm42600_core.c | 5 +++++
drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c | 3 +++
drivers/iio/imu/inv_icm42600/inv_icm42600_spi.c | 3 +++
5 files changed, 14 insertions(+)
--
2.34.1
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^ permalink raw reply
* Re: [PATCH v5 09/11] regulator: tps6594-regulator: Add TI TPS65224 PMIC regulators
From: Dan Carpenter @ 2024-04-02 10:06 UTC (permalink / raw)
To: Bhargav Raviprakash
Cc: linux-kernel, m.nirmaladevi, lee, robh+dt, krzysztof.kozlowski+dt,
conor+dt, jpanis, devicetree, arnd, gregkh, lgirdwood, broonie,
linus.walleij, linux-gpio, linux-arm-kernel, nm, vigneshr, kristo,
eblanc
In-Reply-To: <20240328124016.161959-10-bhargav.r@ltts.com>
On Thu, Mar 28, 2024 at 06:10:14PM +0530, Bhargav Raviprakash wrote:
> static irqreturn_t tps6594_regulator_irq_handler(int irq, void *data)
> {
> struct tps6594_regulator_irq_data *irq_data = data;
> @@ -369,17 +513,23 @@ static irqreturn_t tps6594_regulator_irq_handler(int irq, void *data)
> static int tps6594_request_reg_irqs(struct platform_device *pdev,
^^^^^^^
This function is not beautiful. I think since you're changing it from
being tps6594 specific, maybe you want to rename a bunch of stuff.
> struct regulator_dev *rdev,
> struct tps6594_regulator_irq_data *irq_data,
> - struct tps6594_regulator_irq_type *tps6594_regs_irq_types,
> + struct tps6594_regulator_irq_type *regs_irq_types,
> int *irq_idx)
> {
> struct tps6594_regulator_irq_type *irq_type;
> struct tps6594 *tps = dev_get_drvdata(pdev->dev.parent);
> - int j;
> + size_t j;
> int irq;
> int error;
> + size_t interrupt_cnt;
> +
> + if (tps->chip_id == TPS6594)
> + interrupt_cnt = ARRAY_SIZE(tps6594_buck1_irq_types);
> + else
> + interrupt_cnt = ARRAY_SIZE(tps65224_buck1_irq_types);
Either 1) pass both the array and the size or 2) just use tps->chip_id
to determine both the array and the arrays_size. Passing the array and
then determining which array was passed by looking at the type is ugly.
regards,
dan carpenter
>
> - for (j = 0; j < REGS_INT_NB; j++) {
> - irq_type = &tps6594_regs_irq_types[j];
> + for (j = 0; j < interrupt_cnt; j++) {
> + irq_type = ®s_irq_types[j];
> irq = platform_get_irq_byname(pdev, irq_type->irq_name);
> if (irq < 0)
> return -EINVAL;
^ permalink raw reply
* [PATCH v4 0/2] media: i2c: Add imx283 camera sensor driver
From: Umang Jain @ 2024-04-02 10:07 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Conor Dooley, Shawn Guo,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Sakari Ailus
Cc: Umang Jain, Kieran Bingham, Rob Herring, Krzysztof Kozlowski,
Sascha Hauer, Andy Shevchenko, linux-media, devicetree,
linux-arm-kernel, linux-kernel, Rob Herring, Laurent Pinchart
Add a v4l2 subdevice driver for the Sony IMX283 image sensor.
The IMX283 is a 20MP Diagonal 15.86 mm (Type 1) CMOS Image Sensor with
Square Pixel for Color Cameras.
The following features are supported:
- Manual exposure an gain control support
- vblank/hblank/link freq control support
- Test pattern support control
- Arbitrary horizontal and vertical cropping
- Supported resolution:
- 5472x3648 @ 20fps (SRGGB12)
- 5472x3648 @ 25fps (SRGGB10)
- 2736x1824 @ 50fps (SRGGB12)
The driver is tested on mainline branch v6.8-rc2 on IMX8MP Debix-SOM-A.
Additional testing has been done on RPi5 with the downstream BSP.
Changes in v4:
- fix 32-bit build error around u64 divisions (use do_div)
- Fix hmax default and minimum values
Changes in v3:
- fix headers includes
- Improve #define(s) readability
- Drop __func__ from error logs
- Use HZ_PER_MHZ instead of MEGA
- mdsel* variables should be u8
- Use container_of_const() instead of container_of()
- Use clamp() used of clamp_t variant
- Use streams API imx283_{enable|disable}_streams (**NOTE**)
- Properly fix PM runtime handling
(pm_ptr(), DEFINE_RUNTIME_DEV_PM_OPS,
imx283_runtime_suspend, imx283_runtime_resume)
- Fix format modifiers, signed-ness at various places
changes in v2 (summary):
- Use u32 wherever possible
- Use MEGA macro instead of self defined MHZ() macro
- Properly refine regs using CCI
- Drop tracking of current mode. Shifted to infer from active state directly.
(Laurent's review)
- Cont. from above: Pass the struct imx283_mode to functions whereever required.
- Remove unused comments
- Remove custom mutex. Use control handler one instead.
- Drop imx283_reset_colorspace() and inline
- Set colorspace field properly (drop _DEFAULTS)
- Use __maybe_unused for imx283_power_on() and imx283_power_off()
- Store controls v4l2_ctrl handles for those required, not all.
- Drop imx283_free_controls(). Use v4l2_ctrl_handler_free
- fix reset-gpios handling and add it to DT schema
- fix data-lanes property in DT schema
- fix IMX283 Kconfig
- Remove unused macros
- Alphabetical case consistency
Signed-off-by: Umang Jain <umang.jain@ideasonboard.com>
---
Kieran Bingham (1):
media: i2c: Add imx283 camera sensor driver
Umang Jain (1):
media: dt-bindings: media: Add bindings for IMX283
.../devicetree/bindings/media/i2c/sony,imx283.yaml | 107 ++
MAINTAINERS | 9 +
drivers/media/i2c/Kconfig | 10 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/imx283.c | 1605 ++++++++++++++++++++
5 files changed, 1732 insertions(+)
---
base-commit: 54ee11761885407056f4ca60309739e2db6b02dc
change-id: 20240402-kernel-name-extraversion-2b08d441e08c
Best regards,
--
Umang Jain <umang.jain@ideasonboard.com>
^ permalink raw reply
* [PATCH v4 1/2] media: dt-bindings: media: Add bindings for IMX283
From: Umang Jain @ 2024-04-02 10:07 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Conor Dooley, Shawn Guo,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Sakari Ailus
Cc: Umang Jain, Kieran Bingham, Rob Herring, Krzysztof Kozlowski,
Sascha Hauer, Andy Shevchenko, linux-media, devicetree,
linux-arm-kernel, linux-kernel, Rob Herring, Laurent Pinchart
In-Reply-To: <20240402-kernel-name-extraversion-v4-0-fb776893e4ec@ideasonboard.com>
- Add dt-bindings documentation for Sony IMX283 sensor driver
- Add MAINTAINERS entry for Sony IMX283 binding documentation
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Umang Jain <umang.jain@ideasonboard.com>
---
| 107 +++++++++++++++++++++
MAINTAINERS | 8 ++
2 files changed, 115 insertions(+)
--git a/Documentation/devicetree/bindings/media/i2c/sony,imx283.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx283.yaml
new file mode 100644
index 000000000000..e4f49f1435a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/sony,imx283.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2024 Ideas on Board Oy
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/sony,imx283.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sony IMX283 Sensor
+
+maintainers:
+ - Kieran Bingham <kieran.bingham@ideasonboard.com>
+ - Umang Jain <umang.jain@ideasonboard.com>
+
+description:
+ IMX283 sensor is a Sony CMOS active pixel digital image sensor with an active
+ array size of 5472H x 3648V. It is programmable through I2C interface. The
+ I2C client address is fixed to 0x1a as per sensor data sheet. Image data is
+ sent through MIPI CSI-2.
+
+properties:
+ compatible:
+ const: sony,imx283
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: Clock frequency from 6 to 24 MHz.
+ maxItems: 1
+
+ vadd-supply:
+ description: Analog power supply (2.9V)
+
+ vdd1-supply:
+ description: Interface power supply (1.8V)
+
+ vdd2-supply:
+ description: Digital power supply (1.2V)
+
+ reset-gpios:
+ description: Sensor reset (XCLR) GPIO
+ maxItems: 1
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ anyOf:
+ - items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+
+ link-frequencies: true
+
+ required:
+ - data-lanes
+ - link-frequencies
+
+ required:
+ - endpoint
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@1a {
+ compatible = "sony,imx283";
+ reg = <0x1a>;
+ clocks = <&imx283_clk>;
+
+ assigned-clocks = <&imx283_clk>;
+ assigned-clock-parents = <&imx283_clk_parent>;
+ assigned-clock-rates = <12000000>;
+
+ vadd-supply = <&camera_vadd_2v9>;
+ vdd1-supply = <&camera_vdd1_1v8>;
+ vdd2-supply = <&camera_vdd2_1v2>;
+
+ port {
+ imx283: endpoint {
+ remote-endpoint = <&cam>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <360000000>;
+ };
+ };
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 1a89e0d2ac61..a2e164131650 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20367,6 +20367,14 @@ T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/sony,imx274.yaml
F: drivers/media/i2c/imx274.c
+SONY IMX283 SENSOR DRIVER
+M: Kieran Bingham <kieran.bingham@ideasonboard.com>
+M: Umang Jain <umang.jain@ideasonboard.com>
+L: linux-media@vger.kernel.org
+S: Maintained
+T: git git://linuxtv.org/media_tree.git
+F: Documentation/devicetree/bindings/media/i2c/sony,imx283.yaml
+
SONY IMX290 SENSOR DRIVER
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
L: linux-media@vger.kernel.org
--
2.43.0
^ permalink raw reply related
* [PATCH v4 2/2] media: i2c: Add imx283 camera sensor driver
From: Umang Jain @ 2024-04-02 10:07 UTC (permalink / raw)
To: Mauro Carvalho Chehab, Conor Dooley, Shawn Guo,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Sakari Ailus
Cc: Umang Jain, Kieran Bingham, Rob Herring, Krzysztof Kozlowski,
Sascha Hauer, Andy Shevchenko, linux-media, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <20240402-kernel-name-extraversion-v4-0-fb776893e4ec@ideasonboard.com>
From: Kieran Bingham <kieran.bingham@ideasonboard.com>
Add a v4l2 subdevice driver for the Sony IMX283 image sensor.
The IMX283 is a 20MP Diagonal 15.86 mm (Type 1) CMOS Image Sensor with
Square Pixel for Color Cameras.
The following features are supported:
- Manual exposure an gain control support
- vblank/hblank/link freq control support
- Test pattern support control
- Arbitrary horizontal and vertical cropping
- Supported resolution:
- 5472x3648 @ 20fps (SRGGB12)
- 5472x3648 @ 25fps (SRGGB10)
- 2736x1824 @ 50fps (SRGGB12)
Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
Signed-off-by: Umang Jain <umang.jain@ideasonboard.com>
---
MAINTAINERS | 1 +
| 10 +
| 1 +
| 1605 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 1617 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a2e164131650..64d3780afb99 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20374,6 +20374,7 @@ L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/sony,imx283.yaml
+F: drivers/media/i2c/imx283.c
SONY IMX290 SENSOR DRIVER
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
--git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index e4da68835683..b84d64d37f0e 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -163,6 +163,16 @@ config VIDEO_IMX274
This is a V4L2 sensor driver for the Sony IMX274
CMOS image sensor.
+config VIDEO_IMX283
+ tristate "Sony IMX283 sensor support"
+ select V4L2_CCI_I2C
+ help
+ This is a V4L2 sensor driver for the Sony IMX283
+ CMOS image sensor.
+
+ To compile this driver as a module, choose M here: the
+ module will be called imx283.
+
config VIDEO_IMX290
tristate "Sony IMX290 sensor support"
select REGMAP_I2C
--git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index b82e99ca7578..bbe41e831c76 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_VIDEO_IMX214) += imx214.o
obj-$(CONFIG_VIDEO_IMX219) += imx219.o
obj-$(CONFIG_VIDEO_IMX258) += imx258.o
obj-$(CONFIG_VIDEO_IMX274) += imx274.o
+obj-$(CONFIG_VIDEO_IMX283) += imx283.o
obj-$(CONFIG_VIDEO_IMX290) += imx290.o
obj-$(CONFIG_VIDEO_IMX296) += imx296.o
obj-$(CONFIG_VIDEO_IMX319) += imx319.o
--git a/drivers/media/i2c/imx283.c b/drivers/media/i2c/imx283.c
new file mode 100644
index 000000000000..ace8f65aa6b3
--- /dev/null
+++ b/drivers/media/i2c/imx283.c
@@ -0,0 +1,1605 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * V4L2 Support for the IMX283
+ *
+ * Diagonal 15.86 mm (Type 1) CMOS Image Sensor with Square Pixel for Color
+ * Cameras.
+ *
+ * Copyright (C) 2024 Ideas on Board Oy.
+ *
+ * Based on Sony IMX283 driver prepared by Will Whang
+ *
+ * Based on Sony imx477 camera driver
+ * Copyright (C) 2019-2020 Raspberry Pi (Trading) Ltd
+ */
+
+#include <linux/array_size.h>
+#include <linux/bitops.h>
+#include <linux/container_of.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/minmax.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/pm_runtime.h>
+#include <linux/property.h>
+#include <linux/regulator/consumer.h>
+#include <linux/types.h>
+#include <linux/units.h>
+#include <media/v4l2-cci.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-fwnode.h>
+#include <media/v4l2-mediabus.h>
+
+/* Chip ID */
+#define IMX283_REG_CHIP_ID CCI_REG8(0x3000)
+#define IMX283_CHIP_ID 0x0b // Default power on state
+
+#define IMX283_REG_STANDBY CCI_REG8(0x3000)
+#define IMX283_ACTIVE 0
+#define IMX283_STANDBY BIT(0)
+#define IMX283_STBLOGIC BIT(1)
+#define IMX283_STBMIPI BIT(2)
+#define IMX283_STBDV BIT(3)
+#define IMX283_SLEEP BIT(4)
+
+#define IMX283_REG_CLAMP CCI_REG8(0x3001)
+#define IMX283_CLPSQRST BIT(4)
+
+#define IMX283_REG_PLSTMG08 CCI_REG8(0x3003)
+#define IMX283_PLSTMG08_VAL 0x77
+
+#define IMX283_REG_MDSEL1 CCI_REG8(0x3004)
+#define IMX283_REG_MDSEL2 CCI_REG8(0x3005)
+#define IMX283_REG_MDSEL3 CCI_REG8(0x3006)
+#define IMX283_MDSEL3_VCROP_EN BIT(5)
+#define IMX283_REG_MDSEL4 CCI_REG8(0x3007)
+#define IMX283_MDSEL4_VCROP_EN (BIT(4) | BIT(6))
+
+#define IMX283_REG_SVR CCI_REG16_LE(0x3009)
+
+#define IMX283_REG_HTRIMMING CCI_REG8(0x300b)
+#define IMX283_MDVREV BIT(0) /* VFLIP */
+#define IMX283_HTRIMMING_EN BIT(4)
+
+#define IMX283_REG_VWINPOS CCI_REG16_LE(0x300f)
+#define IMX283_REG_VWIDCUT CCI_REG16_LE(0x3011)
+
+#define IMX283_REG_MDSEL7 CCI_REG16_LE(0x3013)
+
+/* CSI Clock Configuration */
+#define IMX283_REG_TCLKPOST CCI_REG8(0x3018)
+#define IMX283_REG_THSPREPARE CCI_REG8(0x301a)
+#define IMX283_REG_THSZERO CCI_REG8(0x301c)
+#define IMX283_REG_THSTRAIL CCI_REG8(0x301e)
+#define IMX283_REG_TCLKTRAIL CCI_REG8(0x3020)
+#define IMX283_REG_TCLKPREPARE CCI_REG8(0x3022)
+#define IMX283_REG_TCLKZERO CCI_REG16_LE(0x3024)
+#define IMX283_REG_TLPX CCI_REG8(0x3026)
+#define IMX283_REG_THSEXIT CCI_REG8(0x3028)
+#define IMX283_REG_TCLKPRE CCI_REG8(0x302a)
+#define IMX283_REG_SYSMODE CCI_REG8(0x3104)
+
+#define IMX283_REG_Y_OUT_SIZE CCI_REG16_LE(0x302f)
+#define IMX283_REG_WRITE_VSIZE CCI_REG16_LE(0x3031)
+#define IMX283_REG_OB_SIZE_V CCI_REG8(0x3033)
+
+/* HMAX internal HBLANK */
+#define IMX283_REG_HMAX CCI_REG16_LE(0x3036)
+#define IMX283_HMAX_MAX (BIT(16) - 1)
+
+/* VMAX internal VBLANK */
+#define IMX283_REG_VMAX CCI_REG24_LE(0x3038)
+#define IMX283_VMAX_MAX (BIT(16) - 1)
+
+/* SHR internal */
+#define IMX283_REG_SHR CCI_REG16_LE(0x303b)
+#define IMX283_SHR_MIN 11
+
+/*
+ * Analog gain control
+ * Gain [dB] = -20log{(2048 - value [10:0]) /2048}
+ * Range: 0dB to approximately +27dB
+ */
+#define IMX283_REG_ANALOG_GAIN CCI_REG16_LE(0x3042)
+#define IMX283_ANA_GAIN_MIN 0
+#define IMX283_ANA_GAIN_MAX 1957
+#define IMX283_ANA_GAIN_STEP 1
+#define IMX283_ANA_GAIN_DEFAULT 0x0
+
+/*
+ * Digital gain control
+ * Gain [dB] = value * 6
+ * Range: 0dB to +18db
+ */
+#define IMX283_REG_DIGITAL_GAIN CCI_REG8(0x3044)
+#define IMX283_DGTL_GAIN_MIN 0
+#define IMX283_DGTL_GAIN_MAX 3
+#define IMX283_DGTL_GAIN_DEFAULT 0
+#define IMX283_DGTL_GAIN_STEP 1
+
+#define IMX283_REG_HTRIMMING_START CCI_REG16_LE(0x3058)
+#define IMX283_REG_HTRIMMING_END CCI_REG16_LE(0x305a)
+
+#define IMX283_REG_MDSEL18 CCI_REG16_LE(0x30f6)
+
+/* Master Mode Operation Control */
+#define IMX283_REG_XMSTA CCI_REG8(0x3105)
+#define IMX283_XMSTA BIT(0)
+
+#define IMX283_REG_SYNCDRV CCI_REG8(0x3107)
+#define IMX283_SYNCDRV_XHS_XVS (0xa0 | 0x02)
+#define IMX283_SYNCDRV_HIZ (0xa0 | 0x03)
+
+/* PLL Standby */
+#define IMX283_REG_STBPL CCI_REG8(0x320b)
+#define IMX283_STBPL_NORMAL 0x00
+#define IMX283_STBPL_STANDBY 0x03
+
+/* Input Frequency Setting */
+#define IMX283_REG_PLRD1 CCI_REG8(0x36c1)
+#define IMX283_REG_PLRD2 CCI_REG16_LE(0x36c2)
+#define IMX283_REG_PLRD3 CCI_REG8(0x36f7)
+#define IMX283_REG_PLRD4 CCI_REG8(0x36f8)
+
+#define IMX283_REG_PLSTMG02 CCI_REG8(0x36aa)
+#define IMX283_PLSTMG02_VAL 0x00
+
+#define IMX283_REG_EBD_X_OUT_SIZE CCI_REG16_LE(0x3a54)
+
+/* Test pattern generator */
+#define IMX283_REG_TPG_CTRL CCI_REG8(0x3156)
+#define IMX283_TPG_CTRL_CLKEN BIT(0)
+#define IMX283_TPG_CTRL_PATEN BIT(4)
+
+#define IMX283_REG_TPG_PAT CCI_REG8(0x3157)
+#define IMX283_TPG_PAT_ALL_000 0x00
+#define IMX283_TPG_PAT_ALL_FFF 0x01
+#define IMX283_TPG_PAT_ALL_555 0x02
+#define IMX283_TPG_PAT_ALL_AAA 0x03
+#define IMX283_TPG_PAT_H_COLOR_BARS 0x0a
+#define IMX283_TPG_PAT_V_COLOR_BARS 0x0b
+
+/* Exposure control */
+#define IMX283_EXPOSURE_MIN 52
+#define IMX283_EXPOSURE_STEP 1
+#define IMX283_EXPOSURE_DEFAULT 1000
+#define IMX283_EXPOSURE_MAX 49865
+
+#define IMAGE_PAD 0
+
+#define IMX283_XCLR_MIN_DELAY_US (1 * USEC_PER_MSEC)
+#define IMX283_XCLR_DELAY_RANGE_US (1 * USEC_PER_MSEC)
+
+/* IMX283 native and active pixel array size. */
+static const struct v4l2_rect imx283_native_area = {
+ .top = 0,
+ .left = 0,
+ .width = 5592,
+ .height = 3710,
+};
+
+static const struct v4l2_rect imx283_active_area = {
+ .top = 40,
+ .left = 108,
+ .width = 5472,
+ .height = 3648,
+};
+
+struct imx283_reg_list {
+ unsigned int num_of_regs;
+ const struct cci_reg_sequence *regs;
+};
+
+/* Mode : resolution and related config values */
+struct imx283_mode {
+ unsigned int mode;
+
+ /* Bits per pixel */
+ unsigned int bpp;
+
+ /* Frame width */
+ unsigned int width;
+
+ /* Frame height */
+ unsigned int height;
+
+ /*
+ * Minimum horizontal timing in pixel-units
+ *
+ * Note that HMAX is written in 72MHz units, and the datasheet assumes a
+ * 720MHz link frequency. Convert datasheet values with the following:
+ *
+ * For 12 bpp modes (480Mbps) convert with:
+ * hmax = [hmax in 72MHz units] * 480 / 72
+ *
+ * For 10 bpp modes (576Mbps) convert with:
+ * hmax = [hmax in 72MHz units] * 576 / 72
+ */
+ u32 min_hmax;
+
+ /* minimum V-timing in lines */
+ u32 min_vmax;
+
+ /* default H-timing */
+ u32 default_hmax;
+
+ /* default V-timing */
+ u32 default_vmax;
+
+ /* minimum SHR */
+ u32 min_shr;
+
+ /*
+ * Per-mode vertical crop constants used to calculate values
+ * of IMX283REG_WIDCUT and IMX283_REG_VWINPOS.
+ */
+ u32 veff;
+ u32 vst;
+ u32 vct;
+
+ /* Horizontal and vertical binning ratio */
+ u8 hbin_ratio;
+ u8 vbin_ratio;
+
+ /* Optical Blanking */
+ u32 horizontal_ob;
+ u32 vertical_ob;
+
+ /* Analog crop rectangle. */
+ struct v4l2_rect crop;
+};
+
+struct imx283_input_frequency {
+ unsigned int mhz;
+ unsigned int reg_count;
+ struct cci_reg_sequence regs[4];
+};
+
+static const struct imx283_input_frequency imx283_frequencies[] = {
+ {
+ .mhz = 6 * HZ_PER_MHZ,
+ .reg_count = 4,
+ .regs = {
+ { IMX283_REG_PLRD1, 0x00 },
+ { IMX283_REG_PLRD2, 0x00f0 },
+ { IMX283_REG_PLRD3, 0x00 },
+ { IMX283_REG_PLRD4, 0xc0 },
+ },
+ },
+ {
+ .mhz = 12 * HZ_PER_MHZ,
+ .reg_count = 4,
+ .regs = {
+ { IMX283_REG_PLRD1, 0x01 },
+ { IMX283_REG_PLRD2, 0x00f0 },
+ { IMX283_REG_PLRD3, 0x01 },
+ { IMX283_REG_PLRD4, 0xc0 },
+ },
+ },
+ {
+ .mhz = 18 * HZ_PER_MHZ,
+ .reg_count = 4,
+ .regs = {
+ { IMX283_REG_PLRD1, 0x01 },
+ { IMX283_REG_PLRD2, 0x00a0 },
+ { IMX283_REG_PLRD3, 0x01 },
+ { IMX283_REG_PLRD4, 0x80 },
+ },
+ },
+ {
+ .mhz = 24 * HZ_PER_MHZ,
+ .reg_count = 4,
+ .regs = {
+ { IMX283_REG_PLRD1, 0x02 },
+ { IMX283_REG_PLRD2, 0x00f0 },
+ { IMX283_REG_PLRD3, 0x02 },
+ { IMX283_REG_PLRD4, 0xc0 },
+ },
+ },
+};
+
+enum imx283_modes {
+ IMX283_MODE_0,
+ IMX283_MODE_1,
+ IMX283_MODE_1A,
+ IMX283_MODE_1S,
+ IMX283_MODE_2,
+ IMX283_MODE_2A,
+ IMX283_MODE_3,
+ IMX283_MODE_4,
+ IMX283_MODE_5,
+ IMX283_MODE_6,
+};
+
+struct imx283_readout_mode {
+ u8 mdsel1;
+ u8 mdsel2;
+ u8 mdsel3;
+ u8 mdsel4;
+};
+
+static const struct imx283_readout_mode imx283_readout_modes[] = {
+ /* All pixel scan modes */
+ [IMX283_MODE_0] = { 0x04, 0x03, 0x10, 0x00 }, /* 12 bit */
+ [IMX283_MODE_1] = { 0x04, 0x01, 0x00, 0x00 }, /* 10 bit */
+ [IMX283_MODE_1A] = { 0x04, 0x01, 0x20, 0x50 }, /* 10 bit */
+ [IMX283_MODE_1S] = { 0x04, 0x41, 0x20, 0x50 }, /* 10 bit */
+
+ /* Horizontal / Vertical 2/2-line binning */
+ [IMX283_MODE_2] = { 0x0d, 0x11, 0x50, 0x00 }, /* 12 bit */
+ [IMX283_MODE_2A] = { 0x0d, 0x11, 0x70, 0x50 }, /* 12 bit */
+
+ /* Horizontal / Vertical 3/3-line binning */
+ [IMX283_MODE_3] = { 0x1e, 0x18, 0x10, 0x00 }, /* 12 bit */
+
+ /* Vertical 2/9 subsampling, horizontal 3 binning cropping */
+ [IMX283_MODE_4] = { 0x29, 0x18, 0x30, 0x50 }, /* 12 bit */
+
+ /* Vertical 2/19 subsampling binning, horizontal 3 binning */
+ [IMX283_MODE_5] = { 0x2d, 0x18, 0x10, 0x00 }, /* 12 bit */
+
+ /* Vertical 2 binning horizontal 2/4, subsampling 16:9 cropping */
+ [IMX283_MODE_6] = { 0x18, 0x21, 0x00, 0x09 }, /* 10 bit */
+
+ /*
+ * New modes should make sure the offset period is complied.
+ * See imx283_exposure() for reference.
+ */
+};
+
+static const struct cci_reg_sequence mipi_data_rate_1440Mbps[] = {
+ /* The default register settings provide the 1440Mbps rate */
+ { CCI_REG8(0x36c5), 0x00 }, /* Undocumented */
+ { CCI_REG8(0x3ac4), 0x00 }, /* Undocumented */
+
+ { IMX283_REG_STBPL, 0x00 },
+ { IMX283_REG_TCLKPOST, 0xa7 },
+ { IMX283_REG_THSPREPARE, 0x6f },
+ { IMX283_REG_THSZERO, 0x9f },
+ { IMX283_REG_THSTRAIL, 0x5f },
+ { IMX283_REG_TCLKTRAIL, 0x5f },
+ { IMX283_REG_TCLKPREPARE, 0x6f },
+ { IMX283_REG_TCLKZERO, 0x017f },
+ { IMX283_REG_TLPX, 0x4f },
+ { IMX283_REG_THSEXIT, 0x47 },
+ { IMX283_REG_TCLKPRE, 0x07 },
+ { IMX283_REG_SYSMODE, 0x02 },
+};
+
+static const struct cci_reg_sequence mipi_data_rate_720Mbps[] = {
+ /* Undocumented Additions "For 720MBps" Setting */
+ { CCI_REG8(0x36c5), 0x01 }, /* Undocumented */
+ { CCI_REG8(0x3ac4), 0x01 }, /* Undocumented */
+
+ { IMX283_REG_STBPL, 0x00 },
+ { IMX283_REG_TCLKPOST, 0x77 },
+ { IMX283_REG_THSPREPARE, 0x37 },
+ { IMX283_REG_THSZERO, 0x67 },
+ { IMX283_REG_THSTRAIL, 0x37 },
+ { IMX283_REG_TCLKTRAIL, 0x37 },
+ { IMX283_REG_TCLKPREPARE, 0x37 },
+ { IMX283_REG_TCLKZERO, 0xdf },
+ { IMX283_REG_TLPX, 0x2f },
+ { IMX283_REG_THSEXIT, 0x47 },
+ { IMX283_REG_TCLKPRE, 0x0f },
+ { IMX283_REG_SYSMODE, 0x02 },
+};
+
+static const s64 link_frequencies[] = {
+ 720 * HZ_PER_MHZ, /* 1440 Mbps lane data rate */
+ 360 * HZ_PER_MHZ, /* 720 Mbps data lane rate */
+};
+
+static const struct imx283_reg_list link_freq_reglist[] = {
+ { /* 720 MHz */
+ .num_of_regs = ARRAY_SIZE(mipi_data_rate_1440Mbps),
+ .regs = mipi_data_rate_1440Mbps,
+ },
+ { /* 360 MHz */
+ .num_of_regs = ARRAY_SIZE(mipi_data_rate_720Mbps),
+ .regs = mipi_data_rate_720Mbps,
+ },
+};
+
+#define CENTERED_RECTANGLE(rect, _width, _height) \
+ { \
+ .left = rect.left + ((rect.width - (_width)) / 2), \
+ .top = rect.top + ((rect.height - (_height)) / 2), \
+ .width = (_width), \
+ .height = (_height), \
+ }
+
+/* Mode configs */
+static const struct imx283_mode supported_modes_12bit[] = {
+ {
+ /* 20MPix 21.40 fps readout mode 0 */
+ .mode = IMX283_MODE_0,
+ .bpp = 12,
+ .width = 5472,
+ .height = 3648,
+ .min_hmax = 5914, /* 887 @ 480MHz/72MHz */
+ .min_vmax = 3793, /* Lines */
+
+ .veff = 3694,
+ .vst = 0,
+ .vct = 0,
+
+ .hbin_ratio = 1,
+ .vbin_ratio = 1,
+
+ /* 20.00 FPS */
+ .default_hmax = 6000, /* 900 @ 480MHz/72MHz */
+ .default_vmax = 4000,
+
+ .min_shr = 11,
+ .horizontal_ob = 96,
+ .vertical_ob = 16,
+ .crop = CENTERED_RECTANGLE(imx283_active_area, 5472, 3648),
+ },
+ {
+ /*
+ * Readout mode 2 : 2/2 binned mode (2736x1824)
+ */
+ .mode = IMX283_MODE_2,
+ .bpp = 12,
+ .width = 2736,
+ .height = 1824,
+ .min_hmax = 2414, /* Pixels (362 * 480MHz/72MHz + padding) */
+ .min_vmax = 3840, /* Lines */
+
+ /* 50.00 FPS */
+ .default_hmax = 2500, /* 375 @ 480MHz/72Mhz */
+ .default_vmax = 3840,
+
+ .veff = 1824,
+ .vst = 0,
+ .vct = 0,
+
+ .hbin_ratio = 2,
+ .vbin_ratio = 2,
+
+ .min_shr = 12,
+ .horizontal_ob = 48,
+ .vertical_ob = 4,
+
+ .crop = CENTERED_RECTANGLE(imx283_active_area, 5472, 3648),
+ },
+};
+
+static const struct imx283_mode supported_modes_10bit[] = {
+ {
+ /* 20MPix 25.48 fps readout mode 1 */
+ .mode = IMX283_MODE_1,
+ .bpp = 10,
+ .width = 5472,
+ .height = 3648,
+ .min_hmax = 5960, /* 745 @ 576MHz / 72MHz */
+ .min_vmax = 3793,
+
+ /* 25.00 FPS */
+ .default_hmax = 6000, /* 750 @ 576MHz / 72MHz */
+ .default_vmax = 3840,
+
+ .min_shr = 10,
+ .horizontal_ob = 96,
+ .vertical_ob = 16,
+ .crop = CENTERED_RECTANGLE(imx283_active_area, 5472, 3648),
+ },
+};
+
+static const u32 imx283_mbus_codes[] = {
+ MEDIA_BUS_FMT_SRGGB12_1X12,
+ MEDIA_BUS_FMT_SRGGB10_1X10,
+};
+
+/* regulator supplies */
+static const char *const imx283_supply_name[] = {
+ "vadd", /* Analog (2.9V) supply */
+ "vdd1", /* Supply Voltage 2 (1.8V) supply */
+ "vdd2", /* Supply Voltage 3 (1.2V) supply */
+};
+
+struct imx283 {
+ struct device *dev;
+ struct regmap *cci;
+
+ const struct imx283_input_frequency *freq;
+
+ struct v4l2_subdev sd;
+ struct media_pad pad;
+
+ struct clk *xclk;
+
+ struct gpio_desc *reset_gpio;
+ struct regulator_bulk_data supplies[ARRAY_SIZE(imx283_supply_name)];
+
+ /* V4L2 Controls */
+ struct v4l2_ctrl_handler ctrl_handler;
+ struct v4l2_ctrl *exposure;
+ struct v4l2_ctrl *vblank;
+ struct v4l2_ctrl *hblank;
+ struct v4l2_ctrl *vflip;
+
+ unsigned long link_freq_bitmap;
+
+ u16 hmax;
+ u32 vmax;
+};
+
+static inline struct imx283 *to_imx283(struct v4l2_subdev *sd)
+{
+ return container_of_const(sd, struct imx283, sd);
+}
+
+static inline void get_mode_table(unsigned int code,
+ const struct imx283_mode **mode_list,
+ unsigned int *num_modes)
+{
+ switch (code) {
+ case MEDIA_BUS_FMT_SRGGB12_1X12:
+ case MEDIA_BUS_FMT_SGRBG12_1X12:
+ case MEDIA_BUS_FMT_SGBRG12_1X12:
+ case MEDIA_BUS_FMT_SBGGR12_1X12:
+ *mode_list = supported_modes_12bit;
+ *num_modes = ARRAY_SIZE(supported_modes_12bit);
+ break;
+
+ case MEDIA_BUS_FMT_SRGGB10_1X10:
+ case MEDIA_BUS_FMT_SGRBG10_1X10:
+ case MEDIA_BUS_FMT_SGBRG10_1X10:
+ case MEDIA_BUS_FMT_SBGGR10_1X10:
+ *mode_list = supported_modes_10bit;
+ *num_modes = ARRAY_SIZE(supported_modes_10bit);
+ break;
+ default:
+ *mode_list = NULL;
+ *num_modes = 0;
+ break;
+ }
+}
+
+/* Calculate the Pixel Rate based on the current mode */
+static u64 imx283_pixel_rate(struct imx283 *imx283,
+ const struct imx283_mode *mode)
+{
+ u64 link_frequency = link_frequencies[__ffs(imx283->link_freq_bitmap)];
+ unsigned int bpp = mode->bpp;
+ const unsigned int ddr = 2; /* Double Data Rate */
+ const unsigned int lanes = 4; /* Only 4 lane support */
+ u64 numerator = link_frequency * ddr * lanes;
+
+ do_div(numerator, bpp);
+
+ return numerator;
+}
+
+/* Convert from a variable pixel_rate to 72 MHz clock cycles */
+static u64 imx283_internal_clock(unsigned int pixel_rate, unsigned int pixels)
+{
+ /*
+ * Determine the following operation without overflow:
+ * pixels = 72 Mhz / pixel_rate
+ *
+ * The internal clock at 72MHz and Pixel Rate (between 240 and 576MHz)
+ * can easily overflow this calculation, so pre-divide to simplify.
+ */
+ const u32 iclk_pre = 72;
+ const u32 pclk_pre = pixel_rate / HZ_PER_MHZ;
+ u64 numerator = pixels * iclk_pre;
+
+ do_div(numerator, pclk_pre);
+
+ return numerator;
+}
+
+/* Internal clock (72MHz) to Pixel Rate clock (Variable) */
+static u64 imx283_iclk_to_pix(unsigned int pixel_rate, unsigned int cycles)
+{
+ /*
+ * Determine the following operation without overflow:
+ * cycles * pixel_rate / 72 MHz
+ *
+ * The internal clock at 72MHz and Pixel Rate (between 240 and 576MHz)
+ * can easily overflow this calculation, so pre-divide to simplify.
+ */
+ const u32 iclk_pre = 72;
+ const u32 pclk_pre = pixel_rate / HZ_PER_MHZ;
+ u64 numerator = cycles * pclk_pre;
+
+ do_div(numerator, iclk_pre);
+
+ return numerator;
+}
+
+/* Determine the exposure based on current hmax, vmax and a given SHR */
+static u32 imx283_exposure(struct imx283 *imx283,
+ const struct imx283_mode *mode, u64 shr)
+{
+ u32 svr = 0; /* SVR feature is not currently supported */
+ u32 offset;
+ u64 numerator;
+
+ /* Number of clocks per internal offset period */
+ offset = mode->mode == IMX283_MODE_0 ? 209 : 157;
+ numerator = (imx283->vmax * (svr + 1) - shr) * imx283->hmax + offset;
+
+ do_div(numerator, imx283->hmax);
+
+ return clamp(numerator, 0, U32_MAX);
+}
+
+static void imx283_exposure_limits(struct imx283 *imx283,
+ const struct imx283_mode *mode,
+ s64 *min_exposure, s64 *max_exposure)
+{
+ u32 svr = 0; /* SVR feature is not currently supported */
+ u64 min_shr = mode->min_shr;
+ /* Global Shutter is not supported */
+ u64 max_shr = (svr + 1) * imx283->vmax - 4;
+
+ max_shr = min(max_shr, BIT(16) - 1);
+
+ *min_exposure = imx283_exposure(imx283, mode, max_shr);
+ *max_exposure = imx283_exposure(imx283, mode, min_shr);
+}
+
+/*
+ * Integration Time [s] = [ {VMAX x (SVR + 1) – (SHR)} x HMAX + offset ]
+ * / [ 72 x 10^6 ]
+ */
+static u32 imx283_shr(struct imx283 *imx283, const struct imx283_mode *mode,
+ u32 exposure)
+{
+ u32 svr = 0; /* SVR feature is not currently supported */
+ u32 offset;
+ u64 temp;
+
+ /* Number of clocks per internal offset period */
+ offset = mode->mode == IMX283_MODE_0 ? 209 : 157;
+ temp = ((u64)exposure * imx283->hmax - offset);
+ do_div(temp, imx283->hmax);
+
+ return (imx283->vmax * (svr + 1) - temp);
+}
+
+static const char * const imx283_tpg_menu[] = {
+ "Disabled",
+ "All 000h",
+ "All FFFh",
+ "All 555h",
+ "All AAAh",
+ "Horizontal color bars",
+ "Vertical color bars",
+};
+
+static const int imx283_tpg_val[] = {
+ IMX283_TPG_PAT_ALL_000,
+ IMX283_TPG_PAT_ALL_000,
+ IMX283_TPG_PAT_ALL_FFF,
+ IMX283_TPG_PAT_ALL_555,
+ IMX283_TPG_PAT_ALL_AAA,
+ IMX283_TPG_PAT_H_COLOR_BARS,
+ IMX283_TPG_PAT_V_COLOR_BARS,
+};
+
+static int imx283_update_test_pattern(struct imx283 *imx283, u32 pattern_index)
+{
+ int ret;
+
+ if (pattern_index >= ARRAY_SIZE(imx283_tpg_val))
+ return -EINVAL;
+
+ if (!pattern_index)
+ return cci_write(imx283->cci, IMX283_REG_TPG_CTRL, 0x00, NULL);
+
+ ret = cci_write(imx283->cci, IMX283_REG_TPG_PAT,
+ imx283_tpg_val[pattern_index], NULL);
+ if (ret)
+ return ret;
+
+ return cci_write(imx283->cci, IMX283_REG_TPG_CTRL,
+ IMX283_TPG_CTRL_CLKEN | IMX283_TPG_CTRL_PATEN, NULL);
+}
+
+static int imx283_set_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct imx283 *imx283 = container_of(ctrl->handler, struct imx283,
+ ctrl_handler);
+ const struct imx283_mode *mode;
+ struct v4l2_mbus_framefmt *fmt;
+ const struct imx283_mode *mode_list;
+ struct v4l2_subdev_state *state;
+ unsigned int num_modes;
+ u64 shr, pixel_rate;
+ int ret = 0;
+
+ state = v4l2_subdev_get_locked_active_state(&imx283->sd);
+ fmt = v4l2_subdev_state_get_format(state, 0);
+
+ get_mode_table(fmt->code, &mode_list, &num_modes);
+ mode = v4l2_find_nearest_size(mode_list, num_modes, width, height,
+ fmt->width, fmt->height);
+
+ /*
+ * The VBLANK control may change the limits of usable exposure, so check
+ * and adjust if necessary.
+ */
+ if (ctrl->id == V4L2_CID_VBLANK) {
+ /* Honour the VBLANK limits when setting exposure. */
+ s64 current_exposure, max_exposure, min_exposure;
+
+ imx283->vmax = mode->height + ctrl->val;
+
+ imx283_exposure_limits(imx283, mode,
+ &min_exposure, &max_exposure);
+
+ current_exposure = imx283->exposure->val;
+ current_exposure = clamp(current_exposure, min_exposure,
+ max_exposure);
+
+ __v4l2_ctrl_modify_range(imx283->exposure, min_exposure,
+ max_exposure, 1, current_exposure);
+ }
+
+ /*
+ * Applying V4L2 control value only happens
+ * when power is up for streaming
+ */
+ if (!pm_runtime_get_if_active(imx283->dev, true))
+ return 0;
+
+ switch (ctrl->id) {
+ case V4L2_CID_EXPOSURE:
+ shr = imx283_shr(imx283, mode, ctrl->val);
+ dev_dbg(imx283->dev, "V4L2_CID_EXPOSURE : %d - SHR: %lld\n",
+ ctrl->val, shr);
+ ret = cci_write(imx283->cci, IMX283_REG_SHR, shr, NULL);
+ break;
+
+ case V4L2_CID_HBLANK:
+ pixel_rate = imx283_pixel_rate(imx283, mode);
+ imx283->hmax = imx283_internal_clock(pixel_rate, mode->width + ctrl->val);
+ dev_dbg(imx283->dev, "V4L2_CID_HBLANK : %d HMAX : %u\n",
+ ctrl->val, imx283->hmax);
+ ret = cci_write(imx283->cci, IMX283_REG_HMAX, imx283->hmax, NULL);
+ break;
+
+ case V4L2_CID_VBLANK:
+ imx283->vmax = mode->height + ctrl->val;
+ dev_dbg(imx283->dev, "V4L2_CID_VBLANK : %d VMAX : %u\n",
+ ctrl->val, imx283->vmax);
+ ret = cci_write(imx283->cci, IMX283_REG_VMAX, imx283->vmax, NULL);
+ break;
+
+ case V4L2_CID_ANALOGUE_GAIN:
+ ret = cci_write(imx283->cci, IMX283_REG_ANALOG_GAIN, ctrl->val, NULL);
+ break;
+
+ case V4L2_CID_DIGITAL_GAIN:
+ ret = cci_write(imx283->cci, IMX283_REG_DIGITAL_GAIN, ctrl->val, NULL);
+ break;
+
+ case V4L2_CID_VFLIP:
+ /*
+ * VFLIP is managed by BIT(0) of IMX283_REG_HTRIMMING address, hence
+ * both need to be set simultaneously.
+ */
+ if (ctrl->val) {
+ cci_write(imx283->cci, IMX283_REG_HTRIMMING,
+ IMX283_HTRIMMING_EN | IMX283_MDVREV, &ret);
+ } else {
+ cci_write(imx283->cci, IMX283_REG_HTRIMMING,
+ IMX283_HTRIMMING_EN, &ret);
+ }
+ break;
+
+ case V4L2_CID_TEST_PATTERN:
+ ret = imx283_update_test_pattern(imx283, ctrl->val);
+ break;
+
+ default:
+ dev_err(imx283->dev, "ctrl(id:0x%x, val:0x%x) is not handled\n",
+ ctrl->id, ctrl->val);
+ break;
+ }
+
+ pm_runtime_put(imx283->dev);
+
+ return ret;
+}
+
+static const struct v4l2_ctrl_ops imx283_ctrl_ops = {
+ .s_ctrl = imx283_set_ctrl,
+};
+
+static int imx283_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ if (code->index >= ARRAY_SIZE(imx283_mbus_codes))
+ return -EINVAL;
+
+ code->code = imx283_mbus_codes[code->index];
+
+ return 0;
+}
+
+static int imx283_enum_frame_size(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_frame_size_enum *fse)
+{
+ const struct imx283_mode *mode_list;
+ unsigned int num_modes;
+
+ get_mode_table(fse->code, &mode_list, &num_modes);
+
+ if (fse->index >= num_modes)
+ return -EINVAL;
+
+ fse->min_width = mode_list[fse->index].width;
+ fse->max_width = fse->min_width;
+ fse->min_height = mode_list[fse->index].height;
+ fse->max_height = fse->min_height;
+
+ return 0;
+}
+
+static void imx283_update_image_pad_format(struct imx283 *imx283,
+ const struct imx283_mode *mode,
+ struct v4l2_mbus_framefmt *format)
+{
+ format->width = mode->width;
+ format->height = mode->height;
+ format->field = V4L2_FIELD_NONE;
+ format->colorspace = V4L2_COLORSPACE_RAW;
+ format->ycbcr_enc = V4L2_YCBCR_ENC_601;
+ format->quantization = V4L2_QUANTIZATION_FULL_RANGE;
+ format->xfer_func = V4L2_XFER_FUNC_NONE;
+}
+
+static int imx283_init_state(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state)
+{
+ struct imx283 *imx283 = to_imx283(sd);
+ struct v4l2_mbus_framefmt *format;
+ const struct imx283_mode *mode;
+ struct v4l2_rect *crop;
+
+ /* Initialize try_fmt */
+ format = v4l2_subdev_state_get_format(state, IMAGE_PAD);
+
+ mode = &supported_modes_12bit[0];
+ format->code = MEDIA_BUS_FMT_SRGGB12_1X12;
+ imx283_update_image_pad_format(imx283, mode, format);
+
+ /* Initialize crop rectangle to mode default */
+ crop = v4l2_subdev_state_get_crop(state, IMAGE_PAD);
+ *crop = mode->crop;
+
+ return 0;
+}
+
+static void imx283_set_framing_limits(struct imx283 *imx283,
+ const struct imx283_mode *mode)
+{
+ u64 pixel_rate = imx283_pixel_rate(imx283, mode);
+ u64 min_hblank, max_hblank, def_hblank;
+
+ /* Initialise hmax and vmax for exposure calculations */
+ imx283->hmax = imx283_internal_clock(pixel_rate, mode->default_hmax);
+ imx283->vmax = mode->default_vmax;
+
+ /*
+ * Horizontal Blanking
+ * Convert the HMAX_MAX (72MHz) to Pixel rate values for HBLANK_MAX
+ */
+ min_hblank = mode->min_hmax - mode->width;
+ max_hblank = imx283_iclk_to_pix(pixel_rate, IMX283_HMAX_MAX) - mode->width;
+ def_hblank = mode->default_hmax - mode->width;
+ __v4l2_ctrl_modify_range(imx283->hblank, min_hblank, max_hblank, 1,
+ def_hblank);
+ __v4l2_ctrl_s_ctrl(imx283->hblank, def_hblank);
+
+ /* Vertical Blanking */
+ __v4l2_ctrl_modify_range(imx283->vblank, mode->min_vmax - mode->height,
+ IMX283_VMAX_MAX - mode->height, 1,
+ mode->default_vmax - mode->height);
+ __v4l2_ctrl_s_ctrl(imx283->vblank, mode->default_vmax - mode->height);
+}
+
+static int imx283_set_pad_format(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_format *fmt)
+{
+ struct v4l2_mbus_framefmt *format;
+ const struct imx283_mode *mode;
+ struct imx283 *imx283 = to_imx283(sd);
+ const struct imx283_mode *mode_list;
+ unsigned int num_modes;
+
+ get_mode_table(fmt->format.code, &mode_list, &num_modes);
+
+ mode = v4l2_find_nearest_size(mode_list, num_modes, width, height,
+ fmt->format.width, fmt->format.height);
+
+ fmt->format.width = mode->width;
+ fmt->format.height = mode->height;
+ fmt->format.field = V4L2_FIELD_NONE;
+ fmt->format.colorspace = V4L2_COLORSPACE_RAW;
+ fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601;
+ fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE;
+ fmt->format.xfer_func = V4L2_XFER_FUNC_NONE;
+
+ format = v4l2_subdev_state_get_format(sd_state, 0);
+
+ if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
+ imx283_set_framing_limits(imx283, mode);
+
+ *format = fmt->format;
+
+ return 0;
+}
+
+static int imx283_standby_cancel(struct imx283 *imx283)
+{
+ unsigned int link_freq_idx;
+ int ret = 0;
+
+ cci_write(imx283->cci, IMX283_REG_STANDBY,
+ IMX283_STBLOGIC | IMX283_STBDV, &ret);
+
+ /* Configure PLL clocks based on the xclk */
+ cci_multi_reg_write(imx283->cci, imx283->freq->regs,
+ imx283->freq->reg_count, &ret);
+
+ dev_dbg(imx283->dev, "Using clk freq %ld MHz",
+ imx283->freq->mhz / HZ_PER_MHZ);
+
+ /* Initialise communication */
+ cci_write(imx283->cci, IMX283_REG_PLSTMG08, IMX283_PLSTMG08_VAL, &ret);
+ cci_write(imx283->cci, IMX283_REG_PLSTMG02, IMX283_PLSTMG02_VAL, &ret);
+
+ /* Enable PLL */
+ cci_write(imx283->cci, IMX283_REG_STBPL, IMX283_STBPL_NORMAL, &ret);
+
+ /* Configure the MIPI link speed */
+ link_freq_idx = __ffs(imx283->link_freq_bitmap);
+ cci_multi_reg_write(imx283->cci, link_freq_reglist[link_freq_idx].regs,
+ link_freq_reglist[link_freq_idx].num_of_regs,
+ &ret);
+
+ /* 1st Stabilisation period of 1 ms or more */
+ usleep_range(1000, 2000);
+
+ /* Activate */
+ cci_write(imx283->cci, IMX283_REG_STANDBY, IMX283_ACTIVE, &ret);
+
+ /* 2nd Stabilisation period of 19ms or more */
+ usleep_range(19000, 20000);
+
+ cci_write(imx283->cci, IMX283_REG_CLAMP, IMX283_CLPSQRST, &ret);
+ cci_write(imx283->cci, IMX283_REG_XMSTA, 0, &ret);
+ cci_write(imx283->cci, IMX283_REG_SYNCDRV, IMX283_SYNCDRV_XHS_XVS, &ret);
+
+ return ret;
+}
+
+/* Start streaming */
+static int imx283_start_streaming(struct imx283 *imx283,
+ struct v4l2_subdev_state *state)
+{
+ const struct imx283_readout_mode *readout;
+ const struct imx283_mode *mode;
+ const struct v4l2_mbus_framefmt *fmt;
+ const struct imx283_mode *mode_list;
+ unsigned int num_modes;
+ u32 v_widcut;
+ s32 v_pos;
+ u32 write_v_size;
+ u32 y_out_size;
+ int ret = 0;
+
+ fmt = v4l2_subdev_state_get_format(state, 0);
+ get_mode_table(fmt->code, &mode_list, &num_modes);
+ mode = v4l2_find_nearest_size(mode_list, num_modes, width, height,
+ fmt->width, fmt->height);
+
+ ret = imx283_standby_cancel(imx283);
+ if (ret) {
+ dev_err(imx283->dev, "failed to cancel standby\n");
+ return ret;
+ }
+
+ /*
+ * Set the readout mode registers.
+ * MDSEL3 and MDSEL4 are updated to enable Arbitrary Vertical Cropping.
+ */
+ readout = &imx283_readout_modes[mode->mode];
+ cci_write(imx283->cci, IMX283_REG_MDSEL1, readout->mdsel1, &ret);
+ cci_write(imx283->cci, IMX283_REG_MDSEL2, readout->mdsel2, &ret);
+ cci_write(imx283->cci, IMX283_REG_MDSEL3,
+ readout->mdsel3 | IMX283_MDSEL3_VCROP_EN, &ret);
+ cci_write(imx283->cci, IMX283_REG_MDSEL4,
+ readout->mdsel4 | IMX283_MDSEL4_VCROP_EN, &ret);
+
+ /* Mode 1S specific entries from the Readout Drive Mode Tables */
+ if (mode->mode == IMX283_MODE_1S) {
+ cci_write(imx283->cci, IMX283_REG_MDSEL7, 0x01, &ret);
+ cci_write(imx283->cci, IMX283_REG_MDSEL18, 0x1098, &ret);
+ }
+
+ if (ret) {
+ dev_err(imx283->dev, "failed to set readout\n");
+ return ret;
+ }
+
+ /* Initialise SVR. Unsupported for now - Always 0 */
+ cci_write(imx283->cci, IMX283_REG_SVR, 0x00, &ret);
+
+ dev_dbg(imx283->dev, "Mode: Size %d x %d\n", mode->width, mode->height);
+ dev_dbg(imx283->dev, "Analogue Crop (in the mode) %d,%d %dx%d\n",
+ mode->crop.left,
+ mode->crop.top,
+ mode->crop.width,
+ mode->crop.height);
+
+ y_out_size = mode->crop.height / mode->vbin_ratio;
+ write_v_size = y_out_size + mode->vertical_ob;
+ /*
+ * cropping start position = (VWINPOS – Vst) × 2
+ * cropping width = Veff – (VWIDCUT – Vct) × 2
+ */
+ v_pos = imx283->vflip->val ?
+ ((-mode->crop.top / mode->vbin_ratio) / 2) + mode->vst :
+ ((mode->crop.top / mode->vbin_ratio) / 2) + mode->vst;
+ v_widcut = ((mode->veff - y_out_size) / 2) + mode->vct;
+
+ cci_write(imx283->cci, IMX283_REG_Y_OUT_SIZE, y_out_size, &ret);
+ cci_write(imx283->cci, IMX283_REG_WRITE_VSIZE, write_v_size, &ret);
+ cci_write(imx283->cci, IMX283_REG_VWIDCUT, v_widcut, &ret);
+ cci_write(imx283->cci, IMX283_REG_VWINPOS, v_pos, &ret);
+
+ cci_write(imx283->cci, IMX283_REG_OB_SIZE_V, mode->vertical_ob, &ret);
+
+ /* TODO: Validate mode->crop is fully contained within imx283_native_area */
+ cci_write(imx283->cci, IMX283_REG_HTRIMMING_START, mode->crop.left, &ret);
+ cci_write(imx283->cci, IMX283_REG_HTRIMMING_END,
+ mode->crop.left + mode->crop.width, &ret);
+
+ /* Disable embedded data */
+ cci_write(imx283->cci, IMX283_REG_EBD_X_OUT_SIZE, 0, &ret);
+
+ /* Apply customized values from controls (HMAX/VMAX/SHR) */
+ ret = __v4l2_ctrl_handler_setup(imx283->sd.ctrl_handler);
+
+ return ret;
+}
+
+static int imx283_enable_streams(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state, u32 pad,
+ u64 streams_mask)
+{
+ struct imx283 *imx283 = to_imx283(sd);
+ int ret;
+
+ if (pad != IMAGE_PAD)
+ return -EINVAL;
+
+ ret = pm_runtime_get_sync(imx283->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(imx283->dev);
+ return ret;
+ }
+
+ ret = imx283_start_streaming(imx283, state);
+ if (ret)
+ goto err_rpm_put;
+
+ return 0;
+
+err_rpm_put:
+ pm_runtime_mark_last_busy(imx283->dev);
+ pm_runtime_put_autosuspend(imx283->dev);
+
+ return ret;
+}
+
+static int imx283_disable_streams(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state, u32 pad,
+ u64 streams_mask)
+{
+ struct imx283 *imx283 = to_imx283(sd);
+ int ret;
+
+ if (pad != IMAGE_PAD)
+ return -EINVAL;
+
+ ret = cci_write(imx283->cci, IMX283_REG_STANDBY, IMX283_STBLOGIC, NULL);
+ if (ret)
+ dev_err(imx283->dev, "Failed to stop stream\n");
+
+ pm_runtime_mark_last_busy(imx283->dev);
+ pm_runtime_put_autosuspend(imx283->dev);
+
+ return ret;
+}
+
+/* Power/clock management functions */
+static int imx283_power_on(struct imx283 *imx283)
+{
+ int ret;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(imx283_supply_name),
+ imx283->supplies);
+ if (ret) {
+ dev_err(imx283->dev, "failed to enable regulators\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(imx283->xclk);
+ if (ret) {
+ dev_err(imx283->dev, "failed to enable clock\n");
+ goto reg_off;
+ }
+
+ gpiod_set_value_cansleep(imx283->reset_gpio, 0);
+
+ usleep_range(IMX283_XCLR_MIN_DELAY_US,
+ IMX283_XCLR_MIN_DELAY_US + IMX283_XCLR_DELAY_RANGE_US);
+
+ return 0;
+
+reg_off:
+ regulator_bulk_disable(ARRAY_SIZE(imx283_supply_name), imx283->supplies);
+ return ret;
+}
+
+static int imx283_power_off(struct imx283 *imx283)
+{
+ gpiod_set_value_cansleep(imx283->reset_gpio, 1);
+ regulator_bulk_disable(ARRAY_SIZE(imx283_supply_name), imx283->supplies);
+ clk_disable_unprepare(imx283->xclk);
+
+ return 0;
+}
+
+static int imx283_runtime_resume(struct device *dev)
+{
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
+ struct imx283 *imx283 = to_imx283(sd);
+
+ return imx283_power_on(imx283);
+}
+
+static int imx283_runtime_suspend(struct device *dev)
+{
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
+ struct imx283 *imx283 = to_imx283(sd);
+
+ imx283_power_off(imx283);
+
+ return 0;
+}
+
+static int imx283_get_regulators(struct imx283 *imx283)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx283_supply_name); i++)
+ imx283->supplies[i].supply = imx283_supply_name[i];
+
+ return devm_regulator_bulk_get(imx283->dev,
+ ARRAY_SIZE(imx283_supply_name),
+ imx283->supplies);
+}
+
+/* Verify chip ID */
+static int imx283_identify_module(struct imx283 *imx283)
+{
+ int ret;
+ u64 val;
+
+ ret = cci_read(imx283->cci, IMX283_REG_CHIP_ID, &val, NULL);
+ if (ret) {
+ dev_err(imx283->dev, "failed to read chip id %x, with error %d\n",
+ IMX283_CHIP_ID, ret);
+ return ret;
+ }
+
+ if (val != IMX283_CHIP_ID) {
+ dev_err(imx283->dev, "chip id mismatch: %x!=%llx\n",
+ IMX283_CHIP_ID, val);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int imx283_get_selection(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_selection *sel)
+{
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP: {
+ sel->r = *v4l2_subdev_state_get_crop(sd_state, 0);
+ return 0;
+ }
+
+ case V4L2_SEL_TGT_NATIVE_SIZE:
+ sel->r = imx283_native_area;
+ return 0;
+
+ case V4L2_SEL_TGT_CROP_DEFAULT:
+ case V4L2_SEL_TGT_CROP_BOUNDS:
+ sel->r = imx283_active_area;
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct v4l2_subdev_core_ops imx283_core_ops = {
+ .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
+ .unsubscribe_event = v4l2_event_subdev_unsubscribe,
+};
+
+static const struct v4l2_subdev_video_ops imx283_video_ops = {
+ .s_stream = v4l2_subdev_s_stream_helper,
+};
+
+static const struct v4l2_subdev_pad_ops imx283_pad_ops = {
+ .enum_mbus_code = imx283_enum_mbus_code,
+ .get_fmt = v4l2_subdev_get_fmt,
+ .set_fmt = imx283_set_pad_format,
+ .get_selection = imx283_get_selection,
+ .enum_frame_size = imx283_enum_frame_size,
+ .enable_streams = imx283_enable_streams,
+ .disable_streams = imx283_disable_streams,
+};
+
+static const struct v4l2_subdev_internal_ops imx283_internal_ops = {
+ .init_state = imx283_init_state,
+};
+
+static const struct v4l2_subdev_ops imx283_subdev_ops = {
+ .core = &imx283_core_ops,
+ .video = &imx283_video_ops,
+ .pad = &imx283_pad_ops,
+};
+
+/* Initialize control handlers */
+static int imx283_init_controls(struct imx283 *imx283)
+{
+ struct v4l2_ctrl_handler *ctrl_hdlr;
+ struct v4l2_fwnode_device_properties props;
+ struct v4l2_ctrl *link_freq;
+ const struct imx283_mode *mode = &supported_modes_12bit[0];
+ u64 min_hblank, max_hblank, def_hblank;
+ u64 pixel_rate;
+ int ret;
+
+ ctrl_hdlr = &imx283->ctrl_handler;
+ ret = v4l2_ctrl_handler_init(ctrl_hdlr, 16);
+ if (ret)
+ return ret;
+
+ /*
+ * Create the controls here, but mode specific limits are setup
+ * in the imx283_set_framing_limits() call below.
+ */
+
+ /* By default, PIXEL_RATE is read only */
+ pixel_rate = imx283_pixel_rate(imx283, mode);
+ v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops,
+ V4L2_CID_PIXEL_RATE, pixel_rate,
+ pixel_rate, 1, pixel_rate);
+
+ link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx283_ctrl_ops,
+ V4L2_CID_LINK_FREQ,
+ __fls(imx283->link_freq_bitmap),
+ __ffs(imx283->link_freq_bitmap),
+ link_frequencies);
+ if (link_freq)
+ link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
+ /* Initialise vblank/hblank/exposure based on the current mode. */
+ imx283->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops,
+ V4L2_CID_VBLANK,
+ mode->min_vmax - mode->height,
+ IMX283_VMAX_MAX, 1,
+ mode->default_vmax - mode->height);
+
+ min_hblank = mode->min_hmax - mode->width;
+ max_hblank = imx283_iclk_to_pix(pixel_rate, IMX283_HMAX_MAX) - mode->width;
+ def_hblank = mode->default_hmax - mode->width;
+ imx283->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops,
+ V4L2_CID_HBLANK, min_hblank, max_hblank,
+ 1, def_hblank);
+
+ imx283->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops,
+ V4L2_CID_EXPOSURE,
+ IMX283_EXPOSURE_MIN,
+ IMX283_EXPOSURE_MAX,
+ IMX283_EXPOSURE_STEP,
+ IMX283_EXPOSURE_DEFAULT);
+
+ v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
+ IMX283_ANA_GAIN_MIN, IMX283_ANA_GAIN_MAX,
+ IMX283_ANA_GAIN_STEP, IMX283_ANA_GAIN_DEFAULT);
+
+ v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
+ IMX283_DGTL_GAIN_MIN, IMX283_DGTL_GAIN_MAX,
+ IMX283_DGTL_GAIN_STEP, IMX283_DGTL_GAIN_DEFAULT);
+
+ imx283->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_VFLIP,
+ 0, 1, 1, 0);
+ if (imx283->vflip)
+ imx283->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
+
+ v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx283_ctrl_ops,
+ V4L2_CID_TEST_PATTERN,
+ ARRAY_SIZE(imx283_tpg_menu) - 1,
+ 0, 0, imx283_tpg_menu);
+
+ if (ctrl_hdlr->error) {
+ ret = ctrl_hdlr->error;
+ dev_err(imx283->dev, "control init failed (%d)\n", ret);
+ goto error;
+ }
+
+ ret = v4l2_fwnode_device_parse(imx283->dev, &props);
+ if (ret)
+ goto error;
+
+ ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx283_ctrl_ops,
+ &props);
+ if (ret)
+ goto error;
+
+ imx283->sd.ctrl_handler = ctrl_hdlr;
+
+ mutex_lock(imx283->ctrl_handler.lock);
+
+ /* Setup exposure and frame/line length limits. */
+ imx283_set_framing_limits(imx283, mode);
+
+ mutex_unlock(imx283->ctrl_handler.lock);
+
+ return 0;
+
+error:
+ v4l2_ctrl_handler_free(ctrl_hdlr);
+
+ return ret;
+}
+
+static int imx283_parse_endpoint(struct imx283 *imx283)
+{
+ struct fwnode_handle *fwnode;
+ struct v4l2_fwnode_endpoint bus_cfg = {
+ .bus_type = V4L2_MBUS_CSI2_DPHY
+ };
+ struct fwnode_handle *ep;
+ int ret;
+
+ fwnode = dev_fwnode(imx283->dev);
+ ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
+ if (!ep) {
+ dev_err(imx283->dev, "Failed to get next endpoint\n");
+ return -ENXIO;
+ }
+
+ ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
+ fwnode_handle_put(ep);
+ if (ret)
+ return ret;
+
+ if (bus_cfg.bus.mipi_csi2.num_data_lanes != 4) {
+ dev_err(imx283->dev,
+ "number of CSI2 data lanes %d is not supported\n",
+ bus_cfg.bus.mipi_csi2.num_data_lanes);
+ ret = -EINVAL;
+ goto done_endpoint_free;
+ }
+
+ ret = v4l2_link_freq_to_bitmap(imx283->dev, bus_cfg.link_frequencies,
+ bus_cfg.nr_of_link_frequencies,
+ link_frequencies, ARRAY_SIZE(link_frequencies),
+ &imx283->link_freq_bitmap);
+
+done_endpoint_free:
+ v4l2_fwnode_endpoint_free(&bus_cfg);
+
+ return ret;
+};
+
+static int imx283_probe(struct i2c_client *client)
+{
+ struct imx283 *imx283;
+ unsigned int i;
+ unsigned int xclk_freq;
+ int ret;
+
+ imx283 = devm_kzalloc(&client->dev, sizeof(*imx283), GFP_KERNEL);
+ if (!imx283)
+ return -ENOMEM;
+
+ imx283->dev = &client->dev;
+
+ v4l2_i2c_subdev_init(&imx283->sd, client, &imx283_subdev_ops);
+
+ imx283->cci = devm_cci_regmap_init_i2c(client, 16);
+ if (IS_ERR(imx283->cci)) {
+ ret = PTR_ERR(imx283->cci);
+ dev_err(imx283->dev, "failed to initialize CCI: %d\n", ret);
+ return ret;
+ }
+
+ /* Get system clock (xclk) */
+ imx283->xclk = devm_clk_get(imx283->dev, NULL);
+ if (IS_ERR(imx283->xclk)) {
+ return dev_err_probe(imx283->dev, PTR_ERR(imx283->xclk),
+ "failed to get xclk\n");
+ }
+
+ xclk_freq = clk_get_rate(imx283->xclk);
+ for (i = 0; i < ARRAY_SIZE(imx283_frequencies); i++) {
+ if (xclk_freq == imx283_frequencies[i].mhz) {
+ imx283->freq = &imx283_frequencies[i];
+ break;
+ }
+ }
+ if (!imx283->freq) {
+ dev_err(imx283->dev, "xclk frequency unsupported: %d Hz\n", xclk_freq);
+ return -EINVAL;
+ }
+
+ ret = imx283_get_regulators(imx283);
+ if (ret) {
+ return dev_err_probe(imx283->dev, ret,
+ "failed to get regulators\n");
+ }
+
+ ret = imx283_parse_endpoint(imx283);
+ if (ret) {
+ dev_err(imx283->dev, "failed to parse endpoint configuration\n");
+ return ret;
+ }
+
+ /* Request optional enable pin */
+ imx283->reset_gpio = devm_gpiod_get_optional(imx283->dev, "reset",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(imx283->reset_gpio))
+ return dev_err_probe(imx283->dev, PTR_ERR(imx283->reset_gpio),
+ "failed to get reset GPIO\n");
+
+ /*
+ * The sensor must be powered for imx283_identify_module()
+ * to be able to read the CHIP_ID register
+ */
+ ret = imx283_power_on(imx283);
+ if (ret)
+ return ret;
+
+ ret = imx283_identify_module(imx283);
+ if (ret)
+ goto error_power_off;
+
+ /*
+ * Enable runtime PM with autosuspend. As the device has been powered
+ * manually, mark it as active, and increase the usage count without
+ * resuming the device.
+ */
+ pm_runtime_set_active(imx283->dev);
+ pm_runtime_get_noresume(imx283->dev);
+ pm_runtime_enable(imx283->dev);
+ pm_runtime_set_autosuspend_delay(imx283->dev, 1000);
+ pm_runtime_use_autosuspend(imx283->dev);
+
+ /* This needs the pm runtime to be registered. */
+ ret = imx283_init_controls(imx283);
+ if (ret)
+ goto error_pm;
+
+ /* Initialize subdev */
+ imx283->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
+ V4L2_SUBDEV_FL_HAS_EVENTS;
+ imx283->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
+ imx283->sd.internal_ops = &imx283_internal_ops;
+
+ /* Initialize source pads */
+ imx283->pad.flags = MEDIA_PAD_FL_SOURCE;
+
+ ret = media_entity_pads_init(&imx283->sd.entity, 1, &imx283->pad);
+ if (ret) {
+ dev_err(imx283->dev, "failed to init entity pads: %d\n", ret);
+ goto error_handler_free;
+ }
+
+ imx283->sd.state_lock = imx283->ctrl_handler.lock;
+ ret = v4l2_subdev_init_finalize(&imx283->sd);
+ if (ret < 0) {
+ dev_err(imx283->dev, "subdev init error: %d\n", ret);
+ goto error_media_entity;
+ }
+
+ ret = v4l2_async_register_subdev_sensor(&imx283->sd);
+ if (ret < 0) {
+ dev_err(imx283->dev, "failed to register sensor sub-device: %d\n", ret);
+ goto error_subdev_cleanup;
+ }
+
+ /*
+ * Decrease the PM usage count. The device will get suspended after the
+ * autosuspend delay, turning the power off.
+ */
+ pm_runtime_mark_last_busy(imx283->dev);
+ pm_runtime_put_autosuspend(imx283->dev);
+
+ return 0;
+
+error_subdev_cleanup:
+ v4l2_subdev_cleanup(&imx283->sd);
+
+error_media_entity:
+ media_entity_cleanup(&imx283->sd.entity);
+
+error_handler_free:
+ v4l2_ctrl_handler_free(imx283->sd.ctrl_handler);
+
+error_pm:
+ pm_runtime_disable(imx283->dev);
+ pm_runtime_set_suspended(imx283->dev);
+error_power_off:
+ imx283_power_off(imx283);
+
+ return ret;
+}
+
+static void imx283_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct imx283 *imx283 = to_imx283(sd);
+
+ v4l2_async_unregister_subdev(sd);
+ v4l2_subdev_cleanup(&imx283->sd);
+ media_entity_cleanup(&sd->entity);
+ v4l2_ctrl_handler_free(imx283->sd.ctrl_handler);
+
+ pm_runtime_disable(imx283->dev);
+ if (!pm_runtime_status_suspended(imx283->dev))
+ imx283_power_off(imx283);
+ pm_runtime_set_suspended(imx283->dev);
+}
+
+static DEFINE_RUNTIME_DEV_PM_OPS(imx283_pm_ops, imx283_runtime_suspend,
+ imx283_runtime_resume, NULL);
+
+static const struct of_device_id imx283_dt_ids[] = {
+ { .compatible = "sony,imx283" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx283_dt_ids);
+
+static struct i2c_driver imx283_i2c_driver = {
+ .driver = {
+ .name = "imx283",
+ .pm = pm_ptr(&imx283_pm_ops),
+ .of_match_table = imx283_dt_ids,
+ },
+ .probe = imx283_probe,
+ .remove = imx283_remove,
+};
+module_i2c_driver(imx283_i2c_driver);
+
+MODULE_AUTHOR("Will Whang <will@willwhang.com>");
+MODULE_AUTHOR("Kieran Bingham <kieran.bingham@ideasonboard.com>");
+MODULE_AUTHOR("Umang Jain <umang.jain@ideasonboard.com>");
+MODULE_DESCRIPTION("Sony IMX283 Sensor Driver");
+MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v5 7/7] iio: accel: adxl345: Add spi-3wire option
From: Lothar Rubusch @ 2024-04-02 10:11 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Jonathan Cameron, lars, Michael.Hennerich, robh+dt,
krzysztof.kozlowski+dt, conor+dt, linux-iio, devicetree,
linux-kernel, eraretuya
In-Reply-To: <20240401175304.000022ed@Huawei.com>
On Mon, Apr 1, 2024 at 6:53 PM Jonathan Cameron
<Jonathan.Cameron@huawei.com> wrote:
>
> On Mon, 1 Apr 2024 18:06:24 +0200
> Lothar Rubusch <l.rubusch@gmail.com> wrote:
>
> > On Sat, Mar 30, 2024 at 4:24 PM Jonathan Cameron <jic23@kernel.org> wrote:
> > >
> > > On Fri, 29 Mar 2024 01:33:01 +0100
> > > Lothar Rubusch <l.rubusch@gmail.com> wrote:
> > >
> > > > On Thu, Mar 28, 2024 at 2:39 PM Jonathan Cameron <jic23@kernel.org> wrote:
> > > > >
> > > > > On Wed, 27 Mar 2024 22:03:20 +0000
> > > > > Lothar Rubusch <l.rubusch@gmail.com> wrote:
> > > > >
> > > > > > Add a setup function implementation to the spi module to enable spi-3wire
> > > > > > as option when specified in the device-tree.
> > > > > >
> > > > > > Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
> > > > > > ---
> > > > > > drivers/iio/accel/adxl345.h | 2 ++
> > > > > > drivers/iio/accel/adxl345_spi.c | 12 +++++++++++-
> > > > > > 2 files changed, 13 insertions(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h
> > > > > > index 4ea9341d4..e6bc3591c 100644
> > > > > > --- a/drivers/iio/accel/adxl345.h
> > > > > > +++ b/drivers/iio/accel/adxl345.h
> > > > > > @@ -30,6 +30,8 @@
> > > > > > #define ADXL345_POWER_CTL_MEASURE BIT(3)
> > > > > > #define ADXL345_POWER_CTL_STANDBY 0x00
> > > > > >
> > > > > > +#define ADXL345_DATA_FORMAT_SPI_3WIRE BIT(6) /* 3-wire SPI mode */
> > > > > > +
> > > > > > #define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) /* Set the g range */
> > > > > > #define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) /* Left-justified (MSB) mode */
> > > > > > #define ADXL345_DATA_FORMAT_FULL_RES BIT(3) /* Up to 13-bits resolution */
> > > > > > diff --git a/drivers/iio/accel/adxl345_spi.c b/drivers/iio/accel/adxl345_spi.c
> > > > > > index 1c0513bd3..f145d5c1d 100644
> > > > > > --- a/drivers/iio/accel/adxl345_spi.c
> > > > > > +++ b/drivers/iio/accel/adxl345_spi.c
> > > > > > @@ -20,6 +20,16 @@ static const struct regmap_config adxl345_spi_regmap_config = {
> > > > > > .read_flag_mask = BIT(7) | BIT(6),
> > > > > > };
> > > > > >
> > > > > > +static int adxl345_spi_setup(struct device *dev, struct regmap *regmap)
> > > > > > +{
> > > > > > + struct spi_device *spi = container_of(dev, struct spi_device, dev);
> > > > > > +
> > > > > > + if (spi->mode & SPI_3WIRE)
> > > > > > + return regmap_write(regmap, ADXL345_REG_DATA_FORMAT,
> > > > > > + ADXL345_DATA_FORMAT_SPI_3WIRE);
> > > > > Your earlier patch carefully (I think) left one or two fields alone, then
> > > > > this write just comes in and changes them. In particular INT_INVERT.
> > > > >
> > > > Why do you refer here to INT_INVERT? In this code above I try to set
> > > > SPI to 3 lines. Since this is a SPI configuration, i.e. bus specific,
> > > > it happens in adxl345_spi.c. Passing this function to the bus
> > > > independent adxl345_core.c file allows to configure the bus first.
> > > > Therefore, I'm using the update function in core masking out the SPI
> > > > filag.
> > >
> > > Ah. Ok. It was only intended to mask out the SPI3-wire bit, not the
> > > other bits that you also masked out. I thought intent was to leave
> > > them untouched for some reason. Given they don't matter in the driver
> > > at the moment (no interrupt support) then no problem.
> > >
> > > >
> > > > My reason why I try to keep INT_INVERT out is different. There is
> > > > another driver for the same part in the kernel:
> > > > ./drivers/input/misc/adxl34x.c - This is a input driver, using the
> > > > interrupts of the adxl345 for the input device implementation. I
> > > > assumed, that in the iio implementation there won't be interrupt
> > > > handling for the adx345, since it is not an input device. Does this
> > > > make sense?
> > >
> > > No. You can't use these two drivers at the same time. They will almost
> > > certainly trample over each other in actually reading channels etc.
> > >
> > > Their is some legacy of old drivers in input from a long time back.
> > > Given this driver clearly doesn't have full functionality yet in IIO there
> > > and the different userspace ABI, we've just left the input driver alone.
> > >
> > Going by the git history gave this impression, too. But it was still a
> > bit confusing to me.
> >
> > The IIO driver so far does not handle any of the interrupt features.
> > The older driver also seems to support more of the chip's features.
> > Would it make sense to continue implement/port what's missing -
> > feature by feature - for the IIO driver in order to make the input
> > driver obsolete (one day)?
>
> Yes, though it will be challenging because of the ABI differences.
> We do have a few cross subsystem bridge drivers, but the few goes we've
> had at an accel bridge driver haven't made it into the kernel. In particular
> we don't have an in kernel interface for threshold events and similar in IIO.
> It would be easy enough to add one, but no one has ever cared enough to
> do the work. :(
>
Perhaps there are easier things (precision, power saving measures,
etc) of that particular accelerometer to port first. Open issues which
even I could give a try here. Sounds really exciting to me, though,
but before I definitely need a bit more experience with community and
APIs.
What do you mean with cross subsystem bridge drivers, or this accel
bridge driver? I mean, can you provide me with a link to that driver
to have a look into what direction that is going to?
Anyway, I really appreciate already your patience with my patches, the
direct and helpful answers! I appreciate the support. Thinking and
re-thinking over every particular line of code is really an
experience. I don't want to go too much into off-topic discussions
here, if this is not the forum for that, please let me know :)
> Jonathan
>
>
> >
> > > >
> > > > > If it doesn't makes sense to write it there, either write that bit
> > > > > every time here, or leave it alone every time. Not decide on whether
> > > > > to write the bit based on SPI_3WIRE or not. As far as I know they
> > > > > are unconnected features.
> > > > >
> > > > I think I did not understand. Could you please specify a bit more?
> > > > When spi-3wire is configured in the DT it has to be parsed and handled
> > > > in the bus specific part, i.e. the adxl345_spi.c Therefore I configure
> > > > SPI_3WIRE there. I don't want to place SPI specific code in the core
> > > > file.
> > >
> > > My confusion was that you were deliberately not touching the other unused
> > > flags. In reality you are touching the but only if you enable 3wire.
> > > I would write them register to 0 in the !3wire case so all other values
> > > are the same in both paths.
> > >
> > > >
> > > > > > + return 0;
> > > > > > +}
> > > > > > +
> > > > > > static int adxl345_spi_probe(struct spi_device *spi)
> > > > > > {
> > > > > > struct regmap *regmap;
> > > > > > @@ -33,7 +43,7 @@ static int adxl345_spi_probe(struct spi_device *spi)
> > > > > > if (IS_ERR(regmap))
> > > > > > return dev_err_probe(&spi->dev, PTR_ERR(regmap), "Error initializing regmap\n");
> > > > > >
> > > > > > - return adxl345_core_probe(&spi->dev, regmap, NULL);
> > > > > > + return adxl345_core_probe(&spi->dev, regmap, adxl345_spi_setup);
> > > > > > }
> > > > > >
> > > > > > static const struct adxl345_chip_info adxl345_spi_info = {
> > > > >
> > >
> >
>
^ permalink raw reply
* Re: [PATCH AUTOSEL 6.8 36/98] arm64: dts: sc8280xp: correct DMIC2 and DMIC3 pin config node names
From: Krzysztof Kozlowski @ 2024-04-02 10:17 UTC (permalink / raw)
To: Johan Hovold, Sasha Levin
Cc: linux-kernel, stable, Bjorn Andersson, konrad.dybcio, robh,
krzysztof.kozlowski+dt, conor+dt, linux-arm-msm, devicetree
In-Reply-To: <Zguyil0WVwEudPga@hovoldconsulting.com>
On 02/04/2024 09:23, Johan Hovold wrote:
> On Fri, Mar 29, 2024 at 08:37:07AM -0400, Sasha Levin wrote:
>> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>
>> [ Upstream commit 61474b18e762671a69b2df9665f3cec5c87a38af ]
>>
>> Correct the TLMM pin configuration and muxing node names used for DMIC2
>> and DMIC3 (dmic01 -> dmic23). This has no functional impact, but
>> improves code readability and avoids any confusion when reading the DTS.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Link: https://lore.kernel.org/r/20240212172335.124845-1-krzysztof.kozlowski@linaro.org
>> Signed-off-by: Bjorn Andersson <andersson@kernel.org>
>> Signed-off-by: Sasha Levin <sashal@kernel.org>
>
> This is not a bug fix. Please drop from all stable queues (e.g. 6.8 and
> 6.6).
I should just avoid names "fix" and "correct" :)
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v1] arm64: dts: freescale: verdin-imx8mp: enable Verdin I2C_3_HDMI interface
From: Shawn Guo @ 2024-04-02 10:17 UTC (permalink / raw)
To: Vitor Soares
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Vitor Soares, devicetree, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <20240322124620.40250-1-ivitro@gmail.com>
On Fri, Mar 22, 2024 at 12:46:20PM +0000, Vitor Soares wrote:
> From: Vitor Soares <vitor.soares@toradex.com>
>
> Enable Verdin I2C_3_HDMI interface on iMX8MP Toradex Verdin boards.
>
> Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 0/2] Fix the regulator-state-standby definition
From: Nicolas Ferre @ 2024-04-02 10:18 UTC (permalink / raw)
To: Andrei Simion, robh, krzysztof.kozlowski+dt, conor+dt,
alexandre.belloni, claudiu.beznea, mihai.sain
Cc: linux-arm-kernel, linux-kernel, devicetree
In-Reply-To: <20240402091228.110362-1-andrei.simion@microchip.com>
On 02/04/2024 at 11:12, Andrei Simion wrote:
> make dtbs_check DT_SCHEMA_FILES=microchip,mcp16502.yaml
>
> at91-sama7g5ek.dtb: mcp16502@5b: regulators:VDD_(CORE|OTHER)|LDO[1-2]:
> regulator-state-standby 'regulator-suspend-voltage' does not match any of
> the regexes 'pinctrl-[0-9]+' from schema
> $id: http://devicetree.org/schemas/regulator/microchip,mcp16502.yaml#
>
> at91-sama7g54_curiosity.dtb: pmic@5b: regulators:VDD_(CORE|OTHER)|LDO[1-2]:
> regulator-state-standby 'regulator-suspend-voltage' does not match any of
> the regexes 'pinctrl-[0-9]+' from schema
> $id: http://devicetree.org/schemas/regulator/microchip,mcp16502.yaml#
>
> This patch series proposes to correct the typo that was entered by mistake
> into devicetree definition regulator-state-standby by replacing
> regulator-suspend-voltage with regulator-suspend-microvolt.
Sure: as there is no regression for this property never used (because of
the typo, precisely):
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
For the whole series.
Thanks Andrei, best regards,
Nicolas
>
> Andrei Simion (2):
> ARM: boot: dts: microchip: at91-sama7g5ek: Replace
> regulator-suspend-voltage with the valid property
> ARM: boot: dts: microchip: at91-sama7g54_curiosity: Replace
> regulator-suspend-voltage with the valid property
>
> arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts | 8 ++++----
> arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 8 ++++----
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
^ permalink raw reply
* RE: [EXT] Re: [PATCH v10 02/11] arm64: dts: imx8ulp: add usb nodes
From: Xu Yang @ 2024-04-02 10:20 UTC (permalink / raw)
To: Shawn Guo
Cc: gregkh@linuxfoundation.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org,
conor+dt@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, dl-linux-imx,
peter.chen@kernel.org, Jun Li, linux-usb@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
imx@lists.linux.dev, linux-kernel@vger.kernel.org
In-Reply-To: <ZgvCTgB4lp0F83Kn@dragon>
>
> On Thu, Mar 21, 2024 at 04:14:30PM +0800, Xu Yang wrote:
> > Add USB nodes on i.MX8ULP platform which has 2 USB controllers.
> >
> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> >
> > ---
> > Changes in v2:
> > - no changes
> > Changes in v3:
> > - no changes
> > Changes in v4:
> > - no changes
> > Changes in v5:
> > - no changes
> > Changes in v6:
> > - drop usbphy aliases
> > Changes in v7:
> > - no changes
> > Changes in v8:
> > - no changes
> > Changes in v9:
> > - no changes
> > Changes in v10:
> > - no changes
> > ---
> > arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 62 ++++++++++++++++++++++
> > 1 file changed, 62 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > index c4a0082f30d3..7da9461a5745 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > @@ -472,6 +472,68 @@ usdhc2: mmc@298f0000 {
> > status = "disabled";
> > };
> >
> > + usbotg1: usb@29900000 {
> > + compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
> > + reg = <0x29900000 0x200>;
> > + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&pcc4 IMX8ULP_CLK_USB0>;
> > + power-domains = <&scmi_devpd IMX8ULP_PD_USB0>;
> > + phys = <&usbphy1>;
> > + fsl,usbmisc = <&usbmisc1 0>;
> > + ahb-burst-config = <0x0>;
> > + tx-burst-size-dword = <0x8>;
> > + rx-burst-size-dword = <0x8>;
> > + status = "disabled";
> > + };
> > +
> > + usbmisc1: usbmisc@29900200 {
> > + compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",
> > + "fsl,imx6q-usbmisc";
> > + #index-cells = <1>;
> > + reg = <0x29900200 0x200>;
>
> Could you move 'reg' above so that it's after compatible?
Okay.
>
> > + status = "disabled";
> > + };
> > +
> > + usbphy1: usb-phy@29910000 {
> > + compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
> > + reg = <0x29910000 0x10000>;
> > + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>;
> > + #phy-cells = <0>;
> > + status = "disabled";
> > + };
> > +
> > + usbotg2: usb@29920000 {
> > + compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
> > + reg = <0x29920000 0x200>;
> > + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&pcc4 IMX8ULP_CLK_USB1>;
> > + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
> > + phys = <&usbphy2>;
> > + fsl,usbmisc = <&usbmisc2 0>;
> > + ahb-burst-config = <0x0>;
> > + tx-burst-size-dword = <0x8>;
> > + rx-burst-size-dword = <0x8>;
> > + status = "disabled";
> > + };
> > +
> > + usbmisc2: usbmisc@29920200 {
> > + compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",
> > + "fsl,imx6q-usbmisc";
> > + #index-cells = <1>;
> > + reg = <0x29920200 0x200>;
>
> Ditto
Okay.
Thanks,
Xu Yang
>
> Shawn
>
> > + status = "disabled";
> > + };
> > +
> > + usbphy2: usb-phy@29930000 {
> > + compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
> > + reg = <0x29930000 0x10000>;
> > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>;
> > + #phy-cells = <0>;
> > + status = "disabled";
> > + };
> > +
> > fec: ethernet@29950000 {
> > compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
> > reg = <0x29950000 0x10000>;
> > --
> > 2.34.1
> >
^ permalink raw reply
* Re: [PATCH v2 4/4] arm64: dts: qcom: msm8976: Add WCNSS node
From: Bryan O'Donoghue @ 2024-04-02 10:26 UTC (permalink / raw)
To: Adam Skladowski
Cc: phone-devel, ~postmarketos/upstreaming, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240401172153.9231-5-a39.skl@gmail.com>
On 01/04/2024 18:21, Adam Skladowski wrote:
> Add node describing wireless connectivity subsystem.
>
> Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/msm8976.dtsi | 104 ++++++++++++++++++++++++++
> 1 file changed, 104 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> index 77670fce9b8f..41c748c78347 100644
> --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
> @@ -771,6 +771,36 @@ blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
> drive-strength = <2>;
> bias-disable;
> };
> +
> + wcss_wlan_default: wcss-wlan-default-state {
> + wcss-wlan2-pins {
> + pins = "gpio40";
> + function = "wcss_wlan2";
> + drive-strength = <6>;
> + bias-pull-up;
> + };
> +
> + wcss-wlan1-pins {
> + pins = "gpio41";
> + function = "wcss_wlan1";
> + drive-strength = <6>;
> + bias-pull-up;
> + };
> +
> + wcss-wlan0-pins {
> + pins = "gpio42";
> + function = "wcss_wlan0";
> + drive-strength = <6>;
> + bias-pull-up;
> + };
> +
> + wcss-wlan-pins {
> + pins = "gpio43", "gpio44";
> + function = "wcss_wlan";
> + drive-strength = <6>;
> + bias-pull-up;
> + };
> + };
> };
Doesn't look right
arch/arm64/boot/dts/qcom/msm8916.dtsi
arch/arm64/boot/dts/qcom/msm8939.dtsi
wcss_wlan_default: wcss-wlan-default-state {
pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
function = "wcss_wlan";
drive-strength = <6>;
bias-pull-up;
};
>
> gcc: clock-controller@1800000 {
> @@ -1446,6 +1476,80 @@ blsp2_i2c4: i2c@7af8000 {
> status = "disabled";
> };
>
> + wcnss: remoteproc@a204000 {
> + compatible = "qcom,pronto-v3-pil", "qcom,pronto";
> + reg = <0x0a204000 0x2000>,
> + <0x0a202000 0x1000>,
> + <0x0a21b000 0x3000>;
> + reg-names = "ccu",
> + "dxe",
> + "pmu";
> +
> + memory-region = <&wcnss_fw_mem>;
For preference and consistency "wcnss_fw_mem" should be "wcnss_mem"
The ordering of the compatible/reg/interrupt is different to 8916/8939 too.
I'm not sure which is currently the preferred order of declaration but
for V3 of this series would appreciate if you could find out and add the
comment to your cover letter.
Otherwise LGTM.
Please CC me on V3.
---
bod
^ permalink raw reply
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