* Re: [RESEND PATCH v9 2/4] dt-bindings: stm32: update DT bingding for stm32mp25
From: Krzysztof Kozlowski @ 2024-04-05 7:12 UTC (permalink / raw)
To: gabriel.fernandez, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Philipp Zabel
Cc: linux-clk, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel
In-Reply-To: <20240402125312.277052-3-gabriel.fernandez@foss.st.com>
On 02/04/2024 14:53, gabriel.fernandez@foss.st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
>
> Now RCC driver use '.index' of clk_parent_data struct to define a parent.
> The majority of parents are SCMI clocks, then dt-bindings must be fixed.
>
> Fixes: b5be49db3d47 ("dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform")
And except what Rob said, this does not look as a fix. How ABI break
could be a fix and what is even to fix here? Please describe the
observable bug, how it manifests itself and what is exactly the fix for
that bug.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 01/17] dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit
From: André Draszik @ 2024-04-05 7:15 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, saravanak,
willmcvicker
In-Reply-To: <20240404122559.898930-2-peter.griffin@linaro.org>
Hi Pete,
On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> Add dt schema documentation and clock IDs for the High Speed Interface
> 2 (HSI2) clock management unit. This CMU feeds high speed interfaces
> such as PCIe and UFS.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../bindings/clock/google,gs101-clock.yaml | 30 +++++++++++++++++--
> 1 file changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-
> clock.yaml
> index 1d2bcea41c85..a202fd5d1ead 100644
> --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -32,14 +32,15 @@ properties:
> - google,gs101-cmu-misc
> - google,gs101-cmu-peric0
> - google,gs101-cmu-peric1
> + - google,gs101-cmu-hsi2
Can you keep this alphabetical and add hsi before misc please.
>
> clocks:
> minItems: 1
> - maxItems: 3
> + maxItems: 5
>
> clock-names:
> minItems: 1
> - maxItems: 3
> + maxItems: 5
>
> "#clock-cells":
> const: 1
> @@ -112,6 +113,31 @@ allOf:
> - const: bus
> - const: ip
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - google,gs101-cmu-hsi2
this block should also come before misc please.
Once done, feel free to add
Reviewed-by: André Draszik <andre.draszik@linaro.org>
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (24.576 MHz)
> + - description: High Speed Interface bus clock (from CMU_TOP)
> + - description: High Speed Interface pcie clock (from CMU_TOP)
> + - description: High Speed Interface ufs clock (from CMU_TOP)
> + - description: High Speed Interface mmc clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: bus
> + - const: pcie
> + - const: ufs_embd
> + - const: mmc_card
> +
> additionalProperties: false
>
> examples:
^ permalink raw reply
* Re: [PATCH 02/17] dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg compatible
From: André Draszik @ 2024-04-05 7:19 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, saravanak,
willmcvicker
In-Reply-To: <20240404122559.898930-3-peter.griffin@linaro.org>
On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> Update dt schema to include the gs101 hsi2 sysreg compatible.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: André Draszik <andre.draszik@linaro.org>
^ permalink raw reply
* Re: [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2
From: André Draszik @ 2024-04-05 7:23 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, saravanak,
willmcvicker
In-Reply-To: <20240404122559.898930-9-peter.griffin@linaro.org>
Hi Pete,
On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
> index 3dac3577788a..ac239ce6821b 100644
> --- a/include/dt-bindings/clock/google,gs101.h
> +++ b/include/dt-bindings/clock/google,gs101.h
> @@ -518,4 +518,67 @@
> #define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
> #define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46
>
> +/* CMU_HSI2 */
You need to add these defines as part of the patch that is updating the
binding (patch 1 this series).
Cheers,
Andre'
^ permalink raw reply
* Re: [PATCH] dt-bindings: timer: renesas,tmu: Add R-Car V4M support
From: Wolfram Sang @ 2024-04-05 7:28 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Daniel Lezcano, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Laurent Pinchart, devicetree, linux-renesas-soc,
linux-kernel
In-Reply-To: <8a39386b1a33db6e83e852b3b365bc1adeb25242.1712068574.git.geert+renesas@glider.be>
[-- Attachment #1: Type: text/plain, Size: 291 bytes --]
On Tue, Apr 02, 2024 at 04:37:02PM +0200, Geert Uytterhoeven wrote:
> Document support for the Timer Unit (TMU) in the Renesas R-Car V4M
> (R8A779H0) SoC.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH 06/17] arm64: dts: exynos: gs101: Add the hsi2 sysreg node
From: André Draszik @ 2024-04-05 7:33 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, saravanak,
willmcvicker
In-Reply-To: <20240404122559.898930-7-peter.griffin@linaro.org>
Hi Pete,
On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> This has some configuration bits such as sharability that
> are required by UFS.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 38ac4fb1397e..608369cec47b 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 {
> clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> };
>
> + sysreg_hsi2: syscon@14420000 {
> + compatible = "google,gs101-hsi2-sysreg", "syscon";
> + reg = <0x14420000 0x1000>;
Should the length not be 0x10000?
Cheers,
Andre'
^ permalink raw reply
* Re: [PATCH] dt-bindings: timer: renesas,cmt: Add R-Car V4M support
From: Wolfram Sang @ 2024-04-05 7:27 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Daniel Lezcano, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Laurent Pinchart, devicetree, linux-renesas-soc,
linux-kernel
In-Reply-To: <3e8a7a93261d8ad264dec2fa2784fe1bbfc4a23c.1712068536.git.geert+renesas@glider.be>
[-- Attachment #1: Type: text/plain, Size: 324 bytes --]
On Tue, Apr 02, 2024 at 04:36:05PM +0200, Geert Uytterhoeven wrote:
> Document support for the Compare Match Timer Type0 (CMT0) and Type1
> (CMT1) in the Renesas R-Car V4M (R8A779H0) SoC.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH 05/17] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller
From: André Draszik @ 2024-04-05 7:38 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, saravanak,
willmcvicker
In-Reply-To: <20240404122559.898930-6-peter.griffin@linaro.org>
On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> Enable the cmu_hsi2 clock management unit. It feeds some of
> the high speed interfaces such as PCIe and UFS.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index eddb6b326fde..38ac4fb1397e 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 {
> interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
> };
>
> + cmu_hsi2: clock-controller@14400000 {
> + compatible = "google,gs101-cmu-hsi2";
> + reg = <0x14400000 0x4000>;
> + #clock-cells = <1>;
> + clocks = <&ext_24_5m>,
> + <&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
> + <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
> + <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
> + <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
> + clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> + };
This doesn't build because you didn't add the clock ids in the binding patch.
Other than that,
Reviewed-by: André Draszik <andre.draszik@linaro.org>
> +
> pinctrl_hsi2: pinctrl@14440000 {
> compatible = "google,gs101-pinctrl";
> reg = <0x14440000 0x00001000>;
^ permalink raw reply
* [PATCH 0/2] clk: rockchip: clk-rk3568.c: Add missing USB480M_PHY mux
From: Sascha Hauer @ 2024-04-05 7:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-rockchip, Sascha Hauer, David Jander
This series adds a missing clock for the Rockchip RK3568.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
David Jander (1):
clk: rockchip: clk-rk3568.c: Add missing USB480M_PHY mux
Sascha Hauer (1):
dt-bindings: clock: rockchip: add USB480M_PHY mux
drivers/clk/rockchip/clk-rk3568.c | 4 ++++
include/dt-bindings/clock/rk3568-cru.h | 1 +
2 files changed, 5 insertions(+)
---
base-commit: 39cd87c4eb2b893354f3b850f916353f2658ae6f
change-id: 20240405-clk-rk3568-usb480m-phy-mux-ea78af0c1ec5
Best regards,
--
Sascha Hauer <s.hauer@pengutronix.de>
^ permalink raw reply
* [PATCH 1/2] dt-bindings: clock: rockchip: add USB480M_PHY mux
From: Sascha Hauer @ 2024-04-05 7:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-rockchip, Sascha Hauer
In-Reply-To: <20240405-clk-rk3568-usb480m-phy-mux-v1-0-6c89de20a6ff@pengutronix.de>
The USB480M clock can source from a MUX that selects the clock to come
from either of the USB-phy internal 480MHz PLLs. These clocks are
provided by the USB phy driver. This adds the define for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/dt-bindings/clock/rk3568-cru.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h
index d29890865150d..5263085c5b238 100644
--- a/include/dt-bindings/clock/rk3568-cru.h
+++ b/include/dt-bindings/clock/rk3568-cru.h
@@ -78,6 +78,7 @@
#define CPLL_333M 9
#define ARMCLK 10
#define USB480M 11
+#define USB480M_PHY 12
#define ACLK_CORE_NIU2BUS 18
#define CLK_CORE_PVTM 19
#define CLK_CORE_PVTM_CORE 20
--
2.39.2
^ permalink raw reply related
* [PATCH 2/2] clk: rockchip: clk-rk3568.c: Add missing USB480M_PHY mux
From: Sascha Hauer @ 2024-04-05 7:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-rockchip, Sascha Hauer, David Jander
In-Reply-To: <20240405-clk-rk3568-usb480m-phy-mux-v1-0-6c89de20a6ff@pengutronix.de>
From: David Jander <david@protonic.nl>
The USB480M clock can source from a MUX that selects the clock to come
from either of the USB-phy internal 480MHz PLLs. These clocks are
provided by the USB phy driver.
Signed-off-by: David Jander <david@protonic.nl>
Link: https://lore.kernel.org/r/20240404-clk-rockchip-rk3568-add-usb480m-phy-mux-v1-1-e8542afd58b9@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/rockchip/clk-rk3568.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 8cb21d10beca2..2d44bcaef046b 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -215,6 +215,7 @@ static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
PNAME(mux_pll_p) = { "xin24m" };
PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
+PNAME(mux_usb480m_phy_p) = { "clk_usbphy0_480m", "clk_usbphy1_480m"};
PNAME(mux_armclk_p) = { "apll", "gpll" };
PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
@@ -485,6 +486,9 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
RK3568_MODE_CON0, 14, 2, MFLAGS),
+ MUX(USB480M_PHY, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
+ RK3568_MISC_CON2, 15, 1, MFLAGS),
+
/* PD_CORE */
COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
--
2.39.2
^ permalink raw reply related
* Re: [PATCH v8 2/7] arm64: dts: qcom: sm8450: Add interconnect path to PCIe node
From: Manivannan Sadhasivam @ 2024-04-05 7:40 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Krishna chaitanya chundru, Bjorn Andersson, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
Krzysztof Kozlowski, Conor Dooley, Rob Herring, Johan Hovold,
Brian Masney, Georgi Djakov, linux-arm-msm, linux-pci, devicetree,
linux-kernel, vireshk, quic_vbadigan, quic_skananth,
quic_nitegupt, quic_parass
In-Reply-To: <4bd2e661-8e1e-41ff-9b7f-917bb92a196d@linaro.org>
On Wed, Mar 06, 2024 at 05:04:54PM +0100, Konrad Dybcio wrote:
>
>
> On 3/2/24 04:59, Krishna chaitanya chundru wrote:
> > Add pcie-mem & cpu-pcie interconnect path to the PCIe nodes.
> >
> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
> > ---
> > arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > index 01e4dfc4babd..6b1d2e0d9d14 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > @@ -1781,6 +1781,10 @@ pcie0: pcie@1c00000 {
> > <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> > <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> > + interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
>
> Please use QCOM_ICC_TAG_ALWAYS.
>
> > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
>
> And this path could presumably be demoted to QCOM_ICC_TAG_ACTIVE_ONLY?
>
I think it should be fine since there would be no register access done while the
RPMh is put into sleep state. Krishna, can you confirm that by executing the CX
shutdown with QCOM_ICC_TAG_ACTIVE_ONLY vote for cpu-pcie path on any supported
platform?
But if we do such change, then it should also be applied to other SoCs.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply
* Re: [PATCH net-next v6 11/17] dt-bindings: net: pse-pd: Add another way of describing several PSE PIs
From: Oleksij Rempel @ 2024-04-05 7:43 UTC (permalink / raw)
To: Kory Maincent
Cc: Rob Herring, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Jonathan Corbet, Luis Chamberlain, Russ Weight,
Greg Kroah-Hartman, Rafael J. Wysocki, Krzysztof Kozlowski,
Conor Dooley, Mark Brown, Frank Rowand, Andrew Lunn,
Heiner Kallweit, Russell King, Thomas Petazzoni, netdev,
linux-kernel, linux-doc, devicetree, Dent Project
In-Reply-To: <20240404112506.2e155bad@kmaincent-XPS-13-7390>
On Thu, Apr 04, 2024 at 11:25:06AM +0200, Kory Maincent wrote:
> On Wed, 3 Apr 2024 09:31:42 -0500
> Rob Herring <robh@kernel.org> wrote:
>
> > >
> > > > > +
> > > > > + polarity-supported:
> > > > > + $ref: /schemas/types.yaml#/definitions/string-array
> > > > > + description:
> > > > > + Polarity configuration supported by the PSE PI pairsets.
> > > > > + minItems: 1
> > > > > + maxItems: 4
> > > > > + items:
> > > > > + enum:
> > > > > + - MDI-X
> > > > > + - MDI
> > > > > + - X
> > > > > + - S
> > > > > +
> > > > > + vpwr-supply:
> > > > > + description: Regulator power supply for the PSE PI.
> > > >
> > > > I don't see this being used anywhere.
> > >
> > > Right, I forgot to add it to the PD692x0 and TPS23881 binding example!
> >
> > But is this really common/generic? I would think input power rails would
> > be chip specific.
>
> I think as each PSE PI are seen as a regulator we may want it generic to track
> each PI parent. Having the parent regulator described like that would force the
> devicetree to describe where the power come from.
> In contrary, for example, on the pd692x0 controller the regulators are connected
> to the managers (PD69208) and not directly to the PIs. So the devicetree would
> not really fit the hardware. It is indeed chip specific but having described
> like that would be more simple.
>
> If we decided to make it chip specific the core would have a callback to ask
> the driver to fill the regulator_init_data structure for each PI before
> registering the regulators. It is feasible.
>
> Mmh in fact I am still unsure about the solution.
>
> Oleksij as you were the first to push the idea. Have you more argument in mind
> to make it generic?
> https://lore.kernel.org/netdev/ZeObuKHkPN3tiWz_@pengutronix.de/
There can be different, chip specific power consumer, for example the
one which is feeding the PSE controller it self, but also there are common
providers/consumers those which are used to feed PSE PIs. In case of
pd692x0 based setup, the managers are actual regulator responsible to
control power rails connected to PSE PIs, so managers should use this
common provider. Not sure how TI is designed, but it will have same type
of consumer to feed PSE PIs as well.
Regards,
Oleksij
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* Re: [PATCH V2 RESEND 6/6] arm64: dts: qcom: sm8650: Add video and camera clock controllers
From: Dmitry Baryshkov @ 2024-04-05 7:44 UTC (permalink / raw)
To: Jagadeesh Kona
Cc: Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vladimir Zapolskiy, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Taniya Das, Satya Priya Kakitapalli, Ajit Pandey,
Imran Shaik
In-Reply-To: <03f8d2ee-2467-48aa-9b76-06eb13202b8c@quicinc.com>
On Fri, 5 Apr 2024 at 09:01, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
>
>
>
> On 4/4/2024 9:35 PM, Dmitry Baryshkov wrote:
> > On Thu, 4 Apr 2024 at 13:06, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
> >>
> >>
> >>
> >> On 4/4/2024 11:00 AM, Dmitry Baryshkov wrote:
> >>> On Thu, 4 Apr 2024 at 08:13, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
> >>>>
> >>>>
> >>>>
> >>>> On 4/3/2024 9:24 PM, Dmitry Baryshkov wrote:
> >>>>> On Wed, 3 Apr 2024 at 10:16, Jagadeesh Kona <quic_jkona@quicinc.com> wrote:
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>> On 3/25/2024 11:38 AM, Jagadeesh Kona wrote:
> >>>>>>>
> >>>>>>>
> >>>>>>> On 3/21/2024 6:43 PM, Dmitry Baryshkov wrote:
> >>>>>>>> On Thu, 21 Mar 2024 at 11:27, Jagadeesh Kona <quic_jkona@quicinc.com>
> >>>>>>>> wrote:
> >>>>>>>>>
> >>>>>>>>> Add device nodes for video and camera clock controllers on Qualcomm
> >>>>>>>>> SM8650 platform.
> >>>>>>>>>
> >>>>>>>>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> >>>>>>>>> ---
> >>>>>>>>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 28 ++++++++++++++++++++++++++++
> >>>>>>>>> 1 file changed, 28 insertions(+)
> >>>>>>>>>
> >>>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> >>>>>>>>> b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> >>>>>>>>> index 32c0a7b9aded..d862aa6be824 100644
> >>>>>>>>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> >>>>>>>>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> >>>>>>>>> @@ -4,6 +4,8 @@
> >>>>>>>>> */
> >>>>>>>>>
> >>>>>>>>> #include <dt-bindings/clock/qcom,rpmh.h>
> >>>>>>>>> +#include <dt-bindings/clock/qcom,sm8450-videocc.h>
> >>>>>>>>> +#include <dt-bindings/clock/qcom,sm8650-camcc.h>
> >>>>>>>>> #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
> >>>>>>>>> #include <dt-bindings/clock/qcom,sm8650-gcc.h>
> >>>>>>>>> #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
> >>>>>>>>> @@ -3110,6 +3112,32 @@ opp-202000000 {
> >>>>>>>>> };
> >>>>>>>>> };
> >>>>>>>>>
> >>>>>>>>> + videocc: clock-controller@aaf0000 {
> >>>>>>>>> + compatible = "qcom,sm8650-videocc";
> >>>>>>>>> + reg = <0 0x0aaf0000 0 0x10000>;
> >>>>>>>>> + clocks = <&bi_tcxo_div2>,
> >>>>>>>>> + <&gcc GCC_VIDEO_AHB_CLK>;
> >>>>>>>>> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> >>>>>>>>> + required-opps = <&rpmhpd_opp_low_svs>;
> >>>>>>>>
> >>>>>>>> The required-opps should no longer be necessary.
> >>>>>>>>
> >>>>>>>
> >>>>>>> Sure, will check and remove this if not required.
> >>>>>>
> >>>>>>
> >>>>>> I checked further on this and without required-opps, if there is no vote
> >>>>>> on the power-domain & its peer from any other consumers, when runtime
> >>>>>> get is called on device, it enables the power domain just at the minimum
> >>>>>> non-zero level. But in some cases, the minimum non-zero level of
> >>>>>> power-domain could be just retention and is not sufficient for clock
> >>>>>> controller to operate, hence required-opps property is needed to specify
> >>>>>> the minimum level required on power-domain for this clock controller.
> >>>>>
> >>>>> In which cases? If it ends up with the retention vote, it is a bug
> >>>>> which must be fixed.
> >>>>>
> >>>>
> >>>> The minimum non-zero level(configured from bootloaders) of MMCX is
> >>>> retention on few chipsets but it can vary across the chipsets. Hence to
> >>>> be on safer side from our end, it is good to have required-opps in DT to
> >>>> specify the minimum level required for this clock controller.
> >>>
> >>> We are discussing sm8650, not some abstract chipset. Does it list
> >>> retention or low_svs as a minimal level for MMCX?
> >>>
> >>
> >> Actually, the minimum level for MMCX is external to the clock
> >> controllers.
> >
> > Yes, it comes from cmd-db
> >
> >> But the clock controller requires MMCX to be atleast at
> >> lowsvs for it to be functional.
> >
> > Correct
> >
> >> Hence we need to keep required-opps to
> >> ensure the same without relying on the actual minimum level for MMCX.
> >
> > And this is not correct. There is no need for the DT to be redundant.
> > I plan to send patches removing the existing required-opps when they
> > are not required.
> >
> I agree this is not required if cmd-db minimum level is already at
> lowsvs. But since MMCX running at lowsvs is a mandatory requirement for
> clock controller to operate, I believe it is good to have required-opps
> to ensure we meet this requirement in all cases, rather than relying on
> the cmd-db minimum level which we have no control over.
IIf we follow this logic, we should throw cmd-db away and hardcode all
those values in the RPMh drivers.
We have cmd-db. If it is correct, there is no need to duplicate it. If
it is incorrect, it is a bug that should be fixed or worked around.
>
> Thanks,
> Jagadeesh
>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 00/17] HSI2, UFS & UFS phy support for Tensor GS101
From: Krzysztof Kozlowski @ 2024-04-05 7:45 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-1-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> Hi folks,
>
> This series adds support for the High Speed Interface (HSI) 2 clock
> management unit, UFS controller and UFS phy calibration/tuning for GS101.
>
> With this series applied, UFS is now functional! The SKhynix HN8T05BZGKX015
> can be enumerated, partitions mounted etc. This then allows us to move away
> from the initramfs rootfs we have been using for development so far.
>
> The intention is this series will be merged via Krzysztofs Samsung Exynos
> tree(s). This series is rebased on next-20240404.
>
> The series is broadly split into the following parts:
> 1) dt-bindings documentation updates
> 2) gs101 device tree updates
> 3) Prepatory patches for samsung-ufs driver
> 4) GS101 ufs-phy support
> 5) Prepatory patches for ufs-exynos driver
> 6) GS101 ufs-exynos support
UFS phy and host should go through their trees. What is the
reason/need/requirement to put it into this patchset and merge via
Samsung SoC tree?
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 01/17] dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit
From: Krzysztof Kozlowski @ 2024-04-05 7:46 UTC (permalink / raw)
To: André Draszik, Peter Griffin, mturquette, sboyd, robh,
krzk+dt, conor+dt, vkoul, kishon, alim.akhtar, avri.altman,
bvanassche, s.nawrocki, cw00.choi, jejb, martin.petersen,
chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, saravanak,
willmcvicker
In-Reply-To: <d1aaa3a350315b8eb60aaee416fad4382385ca3a.camel@linaro.org>
On 05/04/2024 09:15, André Draszik wrote:
> Hi Pete,
>
> On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
>> Add dt schema documentation and clock IDs for the High Speed Interface
>> 2 (HSI2) clock management unit. This CMU feeds high speed interfaces
>> such as PCIe and UFS.
>>
>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>> ---
>> .../bindings/clock/google,gs101-clock.yaml | 30 +++++++++++++++++--
>> 1 file changed, 28 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-
>> clock.yaml
>> index 1d2bcea41c85..a202fd5d1ead 100644
>> --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>> @@ -32,14 +32,15 @@ properties:
>> - google,gs101-cmu-misc
>> - google,gs101-cmu-peric0
>> - google,gs101-cmu-peric1
>> + - google,gs101-cmu-hsi2
>
> Can you keep this alphabetical and add hsi before misc please.
>>
>> clocks:
>> minItems: 1
>> - maxItems: 3
>> + maxItems: 5
>>
>> clock-names:
>> minItems: 1
>> - maxItems: 3
>> + maxItems: 5
>>
>> "#clock-cells":
>> const: 1
>> @@ -112,6 +113,31 @@ allOf:
>> - const: bus
>> - const: ip
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - google,gs101-cmu-hsi2
>
> this block should also come before misc please.
>
> Once done, feel free to add
Yes, please, ack for both.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 03/17] dt-bindings: ufs: exynos-ufs: Add gs101 compatible
From: Krzysztof Kozlowski @ 2024-04-05 7:49 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-4-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> Add dedicated google,gs101-ufs compatible for Google Tensor gs101
> SoC.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../bindings/ufs/samsung,exynos-ufs.yaml | 51 +++++++++++++++----
> 1 file changed, 42 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> index b2b509b3944d..898da6c0e94f 100644
> --- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> @@ -12,12 +12,10 @@ maintainers:
> description: |
> Each Samsung UFS host controller instance should have its own node.
>
> -allOf:
> - - $ref: ufs-common.yaml
> -
> properties:
> compatible:
> enum:
> + - google,gs101-ufs
> - samsung,exynos7-ufs
> - samsung,exynosautov9-ufs
> - samsung,exynosautov9-ufs-vh
> @@ -38,14 +36,12 @@ properties:
> - const: ufsp
>
> clocks:
> - items:
> - - description: ufs link core clock
> - - description: unipro main clock
> + minItems: 2
> + maxItems: 5
Keep here minItems and:
+ - description: ufs link core clock
+ - description: unipro main clock
+ - description: fmp clock
+ - description: ufs aclk clock
+ - description: ufs pclk clock
>
> clock-names:
> - items:
> - - const: core_clk
> - - const: sclk_unipro_main
> + minItems: 2
> + maxItems: 5
Similarly here
>
> phys:
> maxItems: 1
> @@ -72,6 +68,43 @@ required:
> - clocks
> - clock-names
>
> +allOf:
> + - $ref: ufs-common.yaml
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: google,gs101-ufs
> +
> + then:
> + properties:
> + clocks:
Enough is:
minItems: 5
> + items:
and drop the items since they are defined in top-level.
Your original code is correct, but with my approach we keep the list
synced between variants, at least part of the list. If another variant
appears, then maybe it will go back to your approach, but maybe we can
still have the same clocks and their order.
> + - description: ufs link core clock
> + - description: unipro main clock
> + - description: fmp clock
> + - description: ufs aclk clock
> + - description: ufs pclk clock
> +
> + clock-names:
minItems: 5
> + items:
> + - const: core_clk
> + - const: sclk_unipro_main
> + - const: fmp
> + - const: ufs_aclk
> + - const: ufs_pclk
> + else:
> + properties:
> + clocks:
maxItems: 2
> + items:
> + - description: ufs link core clock
> + - description: unipro main clock
> +
> + clock-names:
maxItems: 2
> + items:
> + - const: core_clk
> + - const: sclk_unipro_main
> +
> unevaluatedProperties: false
>
> examples:
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH] arm64: dts: mediatek: mt2712: fix validation errors
From: AngeloGioacchino Del Regno @ 2024-04-05 7:50 UTC (permalink / raw)
To: Rafał Miłecki, Matthias Brugger, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Rafał Miłecki
In-Reply-To: <20240301074741.8362-1-zajec5@gmail.com>
Il 01/03/24 08:47, Rafał Miłecki ha scritto:
> From: Rafał Miłecki <rafal@milecki.pl>
>
> 1. Fixup infracfg clock controller binding
> It also acts as reset controller so #reset-cells is required.
> 2. Use -pins suffix for pinctrl
>
> This fixes:
> arch/arm64/boot/dts/mediatek/mt2712-evb.dtb: syscon@10001000: '#reset-cells' is a required property
> from schema $id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
> arch/arm64/boot/dts/mediatek/mt2712-evb.dtb: pinctrl@1000b000: 'eth_default', 'eth_sleep', 'usb0_iddig', 'usb1_iddig' do not match any of the regexes: 'pinctrl-[0-9]+', 'pins$'
> from schema $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
>
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply
* Re: [PATCH 04/17] dt-bindings: phy: samsung,ufs-phy: Add dedicated gs101-ufs-phy compatible
From: Krzysztof Kozlowski @ 2024-04-05 7:50 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-5-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> Update dt schema to include the gs101 ufs phy compatible.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 +
> 1 file changed, 1 insertion(+)
This should go via phy tree. DTS should not depend on other subsystems.
If, after resending as separate series, phy does not take patches for
longer time, feel free to ping me, but first let's try to go via phy/UFS.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: crypto: ti,omap-sham: Convert to dtschema
From: Herbert Xu @ 2024-04-05 7:51 UTC (permalink / raw)
To: Animesh Agarwal
Cc: David S. Miller, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-crypto, devicetree, linux-kernel
In-Reply-To: <20240327054911.43093-1-animeshagarwal28@gmail.com>
On Wed, Mar 27, 2024 at 11:19:06AM +0530, Animesh Agarwal wrote:
> Convert the OMAP SoC SHA crypto Module bindings to DT Schema.
>
> Signed-off-by: Animesh Agarwal <animeshagarwal28@gmail.com>
>
> ---
> Changes in v2:
> - Moved vendor specific property below more common properties.
> ---
> .../devicetree/bindings/crypto/omap-sham.txt | 28 ----------
> .../bindings/crypto/ti,omap-sham.yaml | 56 +++++++++++++++++++
> 2 files changed, 56 insertions(+), 28 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/crypto/omap-sham.txt
> create mode 100644 Documentation/devicetree/bindings/crypto/ti,omap-sham.yaml
Patch applied. Thanks.
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH 05/17] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller
From: Krzysztof Kozlowski @ 2024-04-05 7:51 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-6-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> Enable the cmu_hsi2 clock management unit. It feeds some of
> the high speed interfaces such as PCIe and UFS.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
Was it really compiled?
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 07/17] arm64: dts: exynos: gs101: Add ufs, ufs-phy and ufs regulator dt nodes
From: Krzysztof Kozlowski @ 2024-04-05 7:53 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-8-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> Enable the ufs controller, ufs phy and ufs regulator in device tree.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../boot/dts/exynos/google/gs101-oriole.dts | 17 +++++++++
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 35 +++++++++++++++++++
If you wish you can split DTSI and DTS into separate patches. Up to you.
> 2 files changed, 52 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> index 6be15e990b65..986eb5c9898a 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> @@ -53,6 +53,14 @@ button-power {
> wakeup-source;
> };
> };
> +
> + ufs_0_fixed_vcc_reg: regulator-0 {
> + compatible = "regulator-fixed";
> + regulator-name = "ufs-vcc";
> + gpio = <&gpp0 1 0>;
Use defines for GPIO flags, but more important: are you sure this is not
coming from a PMIC? What's the voltage? It looks like a stub for missing
PMIC, because UFS voltages are usually provided by PMIC.
> + regulator-boot-on;
> + enable-active-high;
> + };
> };
>
> &ext_24_5m {
> @@ -106,6 +114,15 @@ &serial_0 {
> status = "okay";
> };
>
> +&ufs_0 {
> + status = "okay";
> + vcc-supply = <&ufs_0_fixed_vcc_reg>;
> +};
> +
> +&ufs_0_phy {
> + status = "okay";
> +};
> +
> &usi_uart {
> samsung,clkreq-on; /* needed for UART mode */
> status = "okay";
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 608369cec47b..9c94829bf14c 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -1277,6 +1277,41 @@ pinctrl_hsi2: pinctrl@14440000 {
> interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
> };
>
> + ufs_0_phy: phy@17e04000 {
> + compatible = "google,gs101-ufs-phy";
> + reg = <0x14704000 0x3000>;
> + reg-names = "phy-pma";
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + #phy-cells = <0>;
> + clocks = <&ext_24_5m>;
> + clock-names = "ref_clk";
> + status = "disabled";
> + };
> +
> + ufs_0: ufs@14700000 {
> + compatible = "google,gs101-ufs";
> +
Drop blank line.
> + reg = <0x14700000 0x200>,
> + <0x14701100 0x200>,
> + <0x14780000 0xa000>,
> + <0x14600000 0x100>;
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 7/7] arm64: dts: qcom: Add SM8550 Xperia 1 V
From: neil.armstrong @ 2024-04-05 7:54 UTC (permalink / raw)
To: Konrad Dybcio, James Schulman, David Rhodes, Richard Fitzgerald,
Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Ricardo Rivera-Matos, Bjorn Andersson, Abel Vesa,
Sai Prakash Ranjan, Kees Cook, Tony Luck, Guilherme G. Piccoli
Cc: Marijn Suijten, alsa-devel, patches, linux-sound, devicetree,
linux-kernel, linux-arm-msm, linux-hardening
In-Reply-To: <8f6236db-0692-44c9-b136-8e0dff714c55@linaro.org>
On 04/04/2024 21:41, Konrad Dybcio wrote:
>
>
> On 2/12/24 18:26, Neil Armstrong wrote:
>> On 12/02/2024 14:10, Konrad Dybcio wrote:
>>> Add support for Sony Xperia 1 V, a.k.a PDX234. This device is a part
>>> of the SoMC SM8550 Yodo platform.
>>>
>
> [...]
>
>>> +/* TODO: Only one SID of PMR735D seems accessible? */
>>
>>
>> What's reported by the cpuinfo pmic array ?
>
> PMK8550 2.1
> PM8550 2.0
> PM8550VS 2.0
> PM8550VS 2.0
> PM8550VS 2.0
> PM8550VE 2.0
> PM8550VS 2.0
> PM8550B 2.0
> PMR735D 2.0
> PM8010 1.1
> PM8010 1.1
>
> Not sure if there's only one or the other one is secure?
>
>>
>> <snip>
>>
>> With the pcie thing fixed:
>> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
>
> It's gonna be fine with the recent aux clock additions. If you
> have no further comments, I'll happily ask for this to be merged ;)
Sure LGTM
>
> Konrad
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: usb: mtk-xhci: add compatible for MT7988
From: AngeloGioacchino Del Regno @ 2024-04-05 7:55 UTC (permalink / raw)
To: Rafał Miłecki, Matthias Brugger, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Chunfeng Yun, Greg Kroah-Hartman, Daniel Golle, linux-usb,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel,
Rafał Miłecki
In-Reply-To: <20240213130044.1976-1-zajec5@gmail.com>
Il 13/02/24 14:00, Rafał Miłecki ha scritto:
> From: Rafał Miłecki <rafal@milecki.pl>
>
> MT7988 SoC contains two on-SoC XHCI controllers. Add proper binding.
>
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply
* Re: [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2
From: Krzysztof Kozlowski @ 2024-04-05 7:55 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-9-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> CMU_HSI2 is the clock management unit used for the hsi2 block.
> HSI stands for High Speed Interface and as such it generates
> clocks for PCIe, UFS and MMC card.
>
> This patch adds support for the muxes, dividers, and gates in
> cmu_hsi2.
>
> CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK is marked as CLK_IS_CRITICAL
> as disabling it leads to an immediate system hang.
>
> CLK_GOUT_HSI2_SYSREG_HSI2_PCLK is also marked CLK_IS_CRITICAL.
> A hang is not observed with fine grained clock control, but
> UFS IP does not function with syscon controlling this clock
> just around hsi2_sysreg register accesses.
>
> CLK_GOUT_HSI2_GPIO_HSI2_PCLK is marked CLK_IGNORE_UNUSED until
> the exynos pinctrl clock patches land then it can be removed.
>
> Some clocks in this unit have very long names. To help with this
> the clock name mangling strategy was updated to include removing
> the following sub-strings.
> - G4X2_DWC_PCIE_CTL_
> - G4X1_DWC_PCIE_CTL_
> - PCIE_SUB_CTRL_
> - INST_0_
> - LN05LPE_
> - TM_WRAPPER_
> - SF_
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>
> ---
> Updated regex for clock name mangling
> sed \
> -e 's|^PLL_LOCKTIME_PLL_\([^_]\+\)|fout_\L\1_pll|' \
> \
> -e 's|^PLL_CON0_MUX_CLKCMU_\([^_]\+\)_\(.*\)|mout_\L\1_\2|' \
> -e 's|^PLL_CON0_PLL_\(.*\)|mout_pll_\L\1|' \
> -e 's|^CLK_CON_MUX_MUX_CLK_\(.*\)|mout_\L\1|' \
> -e '/^PLL_CON[1-4]_[^_]\+_/d' \
> -e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \
> -e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \
> \
> -e 's|_IPCLKPORT||' \
> -e 's|_RSTNSYNC||' \
> -e 's|_G4X2_DWC_PCIE_CTL||' \
> -e 's|_G4X1_DWC_PCIE_CTL||' \
> -e 's|_PCIE_SUB_CTRL||' \
> -e 's|_INST_0||g' \
> -e 's|_LN05LPE||' \
> -e 's|_TM_WRAPPER||' \
> -e 's|_SF||' \
> \
> -e 's|^CLK_CON_DIV_DIV_CLK_\([^_]\+\)_\(.*\)|dout_\L\1_\2|' \
> \
> -e 's|^CLK_CON_BUF_CLKBUF_\([^_]\+\)_\(.*\)|gout_\L\1_\2|' \
> -e 's|^CLK_CON_GAT_CLK_BLK_\([^_]\+\)_UID_\(.*\)|gout_\L\1_\2|' \
> -e 's|^gout_[^_]\+_[^_]\+_cmu_\([^_]\+\)_pclk$|gout_\1_\1_pclk|' \
> -e 's|^CLK_CON_GAT_GOUT_BLK_\([^_]\+\)_UID_\(.*\)|gout_\L\1_\2|' \
> -e 's|^CLK_CON_GAT_CLK_\([^_]\+\)_\(.*\)|gout_\L\1_clk_\L\1_\2|' \
> \
> -e '/^\(DMYQCH\|PCH\|QCH\|QUEUE\)_/d'
> ---
> drivers/clk/samsung/clk-gs101.c | 558 +++++++++++++++++++++++
> include/dt-bindings/clock/google,gs101.h | 63 +++
Bindings are separate patches.
> 2 files changed, 621 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index d065e343a85d..b9f84c7d5c22 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -22,6 +22,7 @@
> #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
> #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
> #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
> +#define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)
>
> /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -3409,6 +3410,560 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
> .clk_name = "bus",
> };
>
> +/* ---- CMU_HSI2 ---------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_HSI2 (0x14400000) */
> +#define PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER 0x0600
> +#define PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER 0x0604
> +#define PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0610
> +#define PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0614
> +#define PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER 0x0620
> +#define PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER 0x0624
> +#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0630
> +#define PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0634
> +#define HSI2_CMU_HSI2_CONTROLLER_OPTION 0x0800
> +#define CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0 0x0810
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2000
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK 0x2008
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK 0x200c
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK 0x2010
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK 0x2014
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK 0x201c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK 0x2020
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK 0x2024
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK 0x2028
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK 0x202c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK 0x2030
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x204c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2050
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2054
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2058
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK 0x205c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x2060
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2064
Is it doable to use shorter register names while still keeping them
close to datasheet/manual? This one is a bit too much... actually most
of them are quite too much. :)
...
> +
> /* ---- platform_driver ----------------------------------------------------- */
>
> static int __init gs101_cmu_probe(struct platform_device *pdev)
> @@ -3432,6 +3987,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
> }, {
> .compatible = "google,gs101-cmu-peric1",
> .data = &peric1_cmu_info,
> + }, {
> + .compatible = "google,gs101-cmu-hsi2",
> + .data = &hsi2_cmu_info,
Keep these also alphabetically ordered by compatible.
Best regards,
Krzysztof
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox