* Re: [PATCH v1 1/4] arm64: dts: freescale: imx8mp-verdin: replace sleep-moci hog with regulator
From: Francesco Dolcini @ 2024-04-05 16:48 UTC (permalink / raw)
To: Stefan Eichenberger
Cc: robh, krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, francesco.dolcini, devicetree, imx, linux-arm-kernel,
linux-kernel, Stefan Eichenberger
In-Reply-To: <20240405160720.5977-2-eichest@gmail.com>
On Fri, Apr 05, 2024 at 06:07:17PM +0200, Stefan Eichenberger wrote:
> From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
>
> The Verdin family has a signal called sleep-moci which can be used to
> turn off peripherals on the carrier board when the SoM goes into
> suspend. So far we have hogged this signal, which means the peripherals
> are always on and it is not possible to add peripherals that depend on
> the sleep-moci to be on. With this change, we replace the hog with a
> regulator so that peripherals can add their own regulators that use the
> same gpio. Carrier boards that allow peripherals to be powered off in
> suspend can disable this regulator and implement their own regulator to
> control the sleep-moci.
>
> Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
^ permalink raw reply
* Re: [PATCH v2 4/6] firmware: arm_scmi: add initial support for i.MX MISC protocol
From: Marco Felsch @ 2024-04-05 16:44 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Sudeep Holla, Cristian Marussi, devicetree, Peng Fan,
linux-kernel, linux-arm-kernel, imx
In-Reply-To: <20240405-imx95-bbm-misc-v2-v2-4-9fc9186856c2@nxp.com>
Hi Peng,
On 24-04-05, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> The i.MX MISC protocol is for misc settings, such as gpio expander
> wakeup.
Can you elaborate a bit more please?
Regards,
Marco
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/firmware/arm_scmi/Kconfig | 10 ++
> drivers/firmware/arm_scmi/Makefile | 1 +
> drivers/firmware/arm_scmi/imx-sm-misc.c | 305 ++++++++++++++++++++++++++++++++
> include/linux/scmi_imx_protocol.h | 17 ++
> 4 files changed, 333 insertions(+)
>
> diff --git a/drivers/firmware/arm_scmi/Kconfig b/drivers/firmware/arm_scmi/Kconfig
> index 56d11c9d9f47..bfeae92f6420 100644
> --- a/drivers/firmware/arm_scmi/Kconfig
> +++ b/drivers/firmware/arm_scmi/Kconfig
> @@ -191,3 +191,13 @@ config IMX_SCMI_BBM_EXT
> and BUTTON.
>
> This driver can also be built as a module.
> +
> +config IMX_SCMI_MISC_EXT
> + tristate "i.MX SCMI MISC EXTENSION"
> + depends on ARM_SCMI_PROTOCOL || (COMPILE_TEST && OF)
> + default y if ARCH_MXC
> + help
> + This enables i.MX System MISC control logic such as gpio expander
> + wakeup
> +
> + This driver can also be built as a module.
> diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile
> index 327687acf857..a23fde721222 100644
> --- a/drivers/firmware/arm_scmi/Makefile
> +++ b/drivers/firmware/arm_scmi/Makefile
> @@ -12,6 +12,7 @@ scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_VIRTIO) += virtio.o
> scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_OPTEE) += optee.o
> scmi-protocols-y = base.o clock.o perf.o power.o reset.o sensors.o system.o voltage.o powercap.o
> scmi-protocols-$(CONFIG_IMX_SCMI_BBM_EXT) += imx-sm-bbm.o
> +scmi-protocols-$(CONFIG_IMX_SCMI_MISC_EXT) += imx-sm-misc.o
> scmi-module-objs := $(scmi-driver-y) $(scmi-protocols-y) $(scmi-transport-y)
>
> obj-$(CONFIG_ARM_SCMI_PROTOCOL) += scmi-core.o
> diff --git a/drivers/firmware/arm_scmi/imx-sm-misc.c b/drivers/firmware/arm_scmi/imx-sm-misc.c
> new file mode 100644
> index 000000000000..1b0ec2281518
> --- /dev/null
> +++ b/drivers/firmware/arm_scmi/imx-sm-misc.c
> @@ -0,0 +1,305 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * System control and Management Interface (SCMI) NXP MISC Protocol
> + *
> + * Copyright 2024 NXP
> + */
> +
> +#define pr_fmt(fmt) "SCMI Notifications MISC - " fmt
> +
> +#include <linux/bits.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/scmi_protocol.h>
> +#include <linux/scmi_imx_protocol.h>
> +
> +#include "protocols.h"
> +#include "notify.h"
> +
> +#define SCMI_PROTOCOL_SUPPORTED_VERSION 0x10000
> +
> +enum scmi_imx_misc_protocol_cmd {
> + SCMI_IMX_MISC_CTRL_SET = 0x3,
> + SCMI_IMX_MISC_CTRL_GET = 0x4,
> + SCMI_IMX_MISC_CTRL_NOTIFY = 0x8,
> +};
> +
> +struct scmi_imx_misc_info {
> + u32 version;
> + u32 nr_dev_ctrl;
> + u32 nr_brd_ctrl;
> + u32 nr_reason;
> +};
> +
> +struct scmi_msg_imx_misc_protocol_attributes {
> + __le32 attributes;
> +};
> +
> +#define GET_BRD_CTRLS_NR(x) le32_get_bits((x), GENMASK(31, 24))
> +#define GET_REASONS_NR(x) le32_get_bits((x), GENMASK(23, 16))
> +#define GET_DEV_CTRLS_NR(x) le32_get_bits((x), GENMASK(15, 0))
> +#define BRD_CTRL_START_ID BIT(15)
> +
> +struct scmi_imx_misc_ctrl_set_in {
> + __le32 id;
> + __le32 num;
> + __le32 value[MISC_MAX_VAL];
> +};
> +
> +struct scmi_imx_misc_ctrl_notify_in {
> + __le32 ctrl_id;
> + __le32 flags;
> +};
> +
> +struct scmi_imx_misc_ctrl_notify_payld {
> + __le32 ctrl_id;
> + __le32 flags;
> +};
> +
> +struct scmi_imx_misc_ctrl_get_out {
> + __le32 num;
> + __le32 *val;
> +};
> +
> +static int scmi_imx_misc_attributes_get(const struct scmi_protocol_handle *ph,
> + struct scmi_imx_misc_info *mi)
> +{
> + int ret;
> + struct scmi_xfer *t;
> + struct scmi_msg_imx_misc_protocol_attributes *attr;
> +
> + ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES, 0,
> + sizeof(*attr), &t);
> + if (ret)
> + return ret;
> +
> + attr = t->rx.buf;
> +
> + ret = ph->xops->do_xfer(ph, t);
> + if (!ret) {
> + mi->nr_dev_ctrl = GET_DEV_CTRLS_NR(attr->attributes);
> + mi->nr_brd_ctrl = GET_BRD_CTRLS_NR(attr->attributes);
> + mi->nr_reason = GET_REASONS_NR(attr->attributes);
> + dev_info(ph->dev, "i.MX MISC NUM DEV CTRL: %d, NUM BRD CTRL: %d,NUM Reason: %d\n",
> + mi->nr_dev_ctrl, mi->nr_brd_ctrl, mi->nr_reason);
> + }
> +
> + ph->xops->xfer_put(ph, t);
> +
> + return ret;
> +}
> +
> +static int scmi_imx_misc_ctrl_validate_id(const struct scmi_protocol_handle *ph,
> + u32 ctrl_id)
> +{
> + struct scmi_imx_misc_info *mi = ph->get_priv(ph);
> +
> + if ((ctrl_id < BRD_CTRL_START_ID) && (ctrl_id > mi->nr_dev_ctrl))
> + return -EINVAL;
> + if (ctrl_id >= BRD_CTRL_START_ID + mi->nr_brd_ctrl)
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +static int scmi_imx_misc_ctrl_notify(const struct scmi_protocol_handle *ph,
> + u32 ctrl_id, u32 flags)
> +{
> + struct scmi_imx_misc_ctrl_notify_in *in;
> + struct scmi_xfer *t;
> + int ret;
> +
> + ret = scmi_imx_misc_ctrl_validate_id(ph, ctrl_id);
> + if (ret)
> + return ret;
> +
> + ret = ph->xops->xfer_get_init(ph, SCMI_IMX_MISC_CTRL_NOTIFY,
> + sizeof(*in), 0, &t);
> + if (ret)
> + return ret;
> +
> + in = t->tx.buf;
> + in->ctrl_id = cpu_to_le32(ctrl_id);
> + in->flags = cpu_to_le32(flags);
> +
> + ret = ph->xops->do_xfer(ph, t);
> +
> + ph->xops->xfer_put(ph, t);
> +
> + return ret;
> +}
> +
> +static int
> +scmi_imx_misc_ctrl_set_notify_enabled(const struct scmi_protocol_handle *ph,
> + u8 evt_id, u32 src_id, bool enable)
> +{
> + int ret;
> +
> + ret = scmi_imx_misc_ctrl_notify(ph, src_id, enable ? evt_id : 0);
> + if (ret)
> + dev_err(ph->dev, "FAIL_ENABLED - evt[%X] src[%d] - ret:%d\n",
> + evt_id, src_id, ret);
> +
> + return ret;
> +}
> +
> +static int scmi_imx_misc_ctrl_get_num_sources(const struct scmi_protocol_handle *ph)
> +{
> + return GENMASK(15, 0);
> +}
> +
> +static void *
> +scmi_imx_misc_ctrl_fill_custom_report(const struct scmi_protocol_handle *ph,
> + u8 evt_id, ktime_t timestamp,
> + const void *payld, size_t payld_sz,
> + void *report, u32 *src_id)
> +{
> + const struct scmi_imx_misc_ctrl_notify_payld *p = payld;
> + struct scmi_imx_misc_ctrl_notify_report *r = report;
> +
> + if (sizeof(*p) != payld_sz)
> + return NULL;
> +
> + r->timestamp = timestamp;
> + r->ctrl_id = p->ctrl_id;
> + r->flags = p->flags;
> + *src_id = r->ctrl_id;
> + dev_dbg(ph->dev, "%s: ctrl_id: %d flags: %d\n", __func__,
> + r->ctrl_id, r->flags);
> +
> + return r;
> +}
> +
> +static const struct scmi_event_ops scmi_imx_misc_event_ops = {
> + .get_num_sources = scmi_imx_misc_ctrl_get_num_sources,
> + .set_notify_enabled = scmi_imx_misc_ctrl_set_notify_enabled,
> + .fill_custom_report = scmi_imx_misc_ctrl_fill_custom_report,
> +};
> +
> +static const struct scmi_event scmi_imx_misc_events[] = {
> + {
> + .id = SCMI_EVENT_IMX_MISC_CONTROL_DISABLED,
> + .max_payld_sz = sizeof(struct scmi_imx_misc_ctrl_notify_payld),
> + .max_report_sz = sizeof(struct scmi_imx_misc_ctrl_notify_report),
> + },
> + {
> + .id = SCMI_EVENT_IMX_MISC_CONTROL_FALLING_EDGE,
> + .max_payld_sz = sizeof(struct scmi_imx_misc_ctrl_notify_payld),
> + .max_report_sz = sizeof(struct scmi_imx_misc_ctrl_notify_report),
> + },
> + {
> + .id = SCMI_EVENT_IMX_MISC_CONTROL_RISING_EDGE,
> + .max_payld_sz = sizeof(struct scmi_imx_misc_ctrl_notify_payld),
> + .max_report_sz = sizeof(struct scmi_imx_misc_ctrl_notify_report),
> + }
> +};
> +
> +static struct scmi_protocol_events scmi_imx_misc_protocol_events = {
> + .queue_sz = SCMI_PROTO_QUEUE_SZ,
> + .ops = &scmi_imx_misc_event_ops,
> + .evts = scmi_imx_misc_events,
> + .num_events = ARRAY_SIZE(scmi_imx_misc_events),
> +};
> +
> +static int scmi_imx_misc_protocol_init(const struct scmi_protocol_handle *ph)
> +{
> + struct scmi_imx_misc_info *minfo;
> + u32 version;
> + int ret;
> +
> + ret = ph->xops->version_get(ph, &version);
> + if (ret)
> + return ret;
> +
> + dev_info(ph->dev, "NXP SM MISC Version %d.%d\n",
> + PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version));
> +
> + minfo = devm_kzalloc(ph->dev, sizeof(*minfo), GFP_KERNEL);
> + if (!minfo)
> + return -ENOMEM;
> +
> + ret = scmi_imx_misc_attributes_get(ph, minfo);
> + if (ret)
> + return ret;
> +
> + return ph->set_priv(ph, minfo, version);
> +}
> +
> +static int scmi_imx_misc_ctrl_get(const struct scmi_protocol_handle *ph,
> + u32 ctrl_id, u32 *num, u32 *val)
> +{
> + struct scmi_imx_misc_ctrl_get_out *out;
> + struct scmi_xfer *t;
> + int ret, i;
> +
> + ret = scmi_imx_misc_ctrl_validate_id(ph, ctrl_id);
> + if (ret)
> + return ret;
> +
> + ret = ph->xops->xfer_get_init(ph, SCMI_IMX_MISC_CTRL_GET, sizeof(u32),
> + 0, &t);
> + if (ret)
> + return ret;
> +
> + put_unaligned_le32(ctrl_id, t->tx.buf);
> + ret = ph->xops->do_xfer(ph, t);
> + if (!ret) {
> + out = t->rx.buf;
> + *num = le32_to_cpu(out->num);
> + for (i = 0; i < *num && i < MISC_MAX_VAL; i++)
> + val[i] = le32_to_cpu(out->val[i]);
> + }
> +
> + ph->xops->xfer_put(ph, t);
> +
> + return ret;
> +}
> +
> +static int scmi_imx_misc_ctrl_set(const struct scmi_protocol_handle *ph,
> + u32 ctrl_id, u32 num, u32 *val)
> +{
> + struct scmi_imx_misc_ctrl_set_in *in;
> + struct scmi_xfer *t;
> + int ret, i;
> +
> + ret = scmi_imx_misc_ctrl_validate_id(ph, ctrl_id);
> + if (ret)
> + return ret;
> +
> + if (num > MISC_MAX_VAL)
> + return -EINVAL;
> +
> + ret = ph->xops->xfer_get_init(ph, SCMI_IMX_MISC_CTRL_SET, sizeof(*in),
> + 0, &t);
> + if (ret)
> + return ret;
> +
> + in = t->tx.buf;
> + in->id = cpu_to_le32(ctrl_id);
> + in->num = cpu_to_le32(num);
> + for (i = 0; i < num; i++)
> + in->value[i] = cpu_to_le32(val[i]);
> +
> + ret = ph->xops->do_xfer(ph, t);
> +
> + ph->xops->xfer_put(ph, t);
> +
> + return ret;
> +}
> +
> +static const struct scmi_imx_misc_proto_ops scmi_imx_misc_proto_ops = {
> + .misc_ctrl_set = scmi_imx_misc_ctrl_set,
> + .misc_ctrl_get = scmi_imx_misc_ctrl_get,
> +};
> +
> +static const struct scmi_protocol scmi_imx_misc = {
> + .id = SCMI_PROTOCOL_IMX_MISC,
> + .owner = THIS_MODULE,
> + .instance_init = &scmi_imx_misc_protocol_init,
> + .ops = &scmi_imx_misc_proto_ops,
> + .events = &scmi_imx_misc_protocol_events,
> + .supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION,
> +};
> +module_scmi_protocol(scmi_imx_misc);
> diff --git a/include/linux/scmi_imx_protocol.h b/include/linux/scmi_imx_protocol.h
> index 90ce011a4429..a69bd4a20f0f 100644
> --- a/include/linux/scmi_imx_protocol.h
> +++ b/include/linux/scmi_imx_protocol.h
> @@ -13,8 +13,14 @@
> #include <linux/notifier.h>
> #include <linux/types.h>
>
> +#define SCMI_PAYLOAD_LEN 100
> +
> +#define SCMI_ARRAY(X, Y) ((SCMI_PAYLOAD_LEN - (X)) / sizeof(Y))
> +#define MISC_MAX_VAL SCMI_ARRAY(8, uint32_t)
> +
> enum scmi_nxp_protocol {
> SCMI_PROTOCOL_IMX_BBM = 0x81,
> + SCMI_PROTOCOL_IMX_MISC = 0x84,
> };
>
> struct scmi_imx_bbm_proto_ops {
> @@ -42,4 +48,15 @@ struct scmi_imx_bbm_notif_report {
> unsigned int rtc_id;
> unsigned int rtc_evt;
> };
> +
> +struct scmi_imx_misc_ctrl_notify_report {
> + ktime_t timestamp;
> + unsigned int ctrl_id;
> + unsigned int flags;
> +};
> +
> +struct scmi_imx_misc_proto_ops {
> + int (*misc_ctrl_set)(const struct scmi_protocol_handle *ph, u32 id, u32 num, u32 *val);
> + int (*misc_ctrl_get)(const struct scmi_protocol_handle *ph, u32 id, u32 *num, u32 *val);
> +};
> #endif
>
> --
> 2.37.1
>
>
>
^ permalink raw reply
* Re: [PATCH v4 2/2] phy: starfive: Add mipi dphy tx support
From: Vinod Koul @ 2024-04-05 16:31 UTC (permalink / raw)
To: Shengyang Chen
Cc: devicetree, linux-phy, kishon, robh+dt, krzysztof.kozlowski+dt,
conor+dt, p.zabel, minda.chen, changhuang.liang, rogerq,
geert+renesas, keith.zhao, linux-kernel
In-Reply-To: <20240301012406.92589-3-shengyang.chen@starfivetech.com>
On 01-03-24, 09:24, Shengyang Chen wrote:
> Add mipi dphy tx support for the StarFive JH7110 SoC.
> It is a module which is used to receive data from DSI
> driver and transfer data to DSI interface like mipi screen.
>
> Signed-off-by: Shengyang Chen <shengyang.chen@starfivetech.com>
> Reviewed-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> MAINTAINERS | 7 +
> drivers/phy/starfive/Kconfig | 10 +
> drivers/phy/starfive/Makefile | 1 +
> drivers/phy/starfive/phy-jh7110-dphy-tx.c | 702 ++++++++++++++++++++++
> 4 files changed, 720 insertions(+)
> create mode 100644 drivers/phy/starfive/phy-jh7110-dphy-tx.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ddbe6c82610f..13219c6504a9 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20871,6 +20871,13 @@ S: Supported
> F: Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml
> F: drivers/phy/starfive/phy-jh7110-dphy-rx.c
>
> +STARFIVE JH7110 DPHY TX DRIVER
> +M: Keith Zhao <keith.zhao@starfivetech.com>
> +M: Shengyang Chen <shengyang.chen@starfivetech.com>
> +S: Supported
> +F: Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml
> +F: drivers/phy/starfive/phy-jh7110-dphy-tx.c
> +
> STARFIVE JH7110 MMC/SD/SDIO DRIVER
> M: William Qiu <william.qiu@starfivetech.com>
> S: Supported
> diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
> index 9508e2143011..d0cdd7cb4a13 100644
> --- a/drivers/phy/starfive/Kconfig
> +++ b/drivers/phy/starfive/Kconfig
> @@ -15,6 +15,16 @@ config PHY_STARFIVE_JH7110_DPHY_RX
> system. If M is selected, the module will be called
> phy-jh7110-dphy-rx.ko.
>
> +config PHY_STARFIVE_JH7110_DPHY_TX
> + tristate "StarFive JH7110 D-PHY TX Support"
> + depends on HAS_IOMEM
> + select GENERIC_PHY
> + select GENERIC_PHY_MIPI_DPHY
> + help
> + Choose this option if you have a StarFive D-PHY TX in your
> + system. If M is selected, the module will be called
> + phy-jh7110-dphy-tx.ko.
> +
> config PHY_STARFIVE_JH7110_PCIE
> tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support"
> depends on HAS_IOMEM
> diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
> index b391018b7c47..eedc4a6fec15 100644
> --- a/drivers/phy/starfive/Makefile
> +++ b/drivers/phy/starfive/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_RX) += phy-jh7110-dphy-rx.o
> +obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_TX) += phy-jh7110-dphy-tx.o
> obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
> obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) += phy-jh7110-usb.o
> diff --git a/drivers/phy/starfive/phy-jh7110-dphy-tx.c b/drivers/phy/starfive/phy-jh7110-dphy-tx.c
> new file mode 100644
> index 000000000000..df30cd424ba7
> --- /dev/null
> +++ b/drivers/phy/starfive/phy-jh7110-dphy-tx.c
> @@ -0,0 +1,702 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * DPHY TX driver for the StarFive JH7110 SoC
> + *
> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> + * Author: Keith Zhao <keith.zhao@starfivetech.com>
> + * Author: Shengyang Chen <shengyang.chen@starfivetech.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/phy/phy-mipi-dphy.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +
> +#define STF_DPHY_APBIFSAIF_SYSCFG(x) (x)
> +
> +#define STF_DPHY_AON_POWER_READY_N_ACTIVE 0
> +#define STF_DPHY_AON_POWER_READY_N_SHIFT 0x0U
> +#define STF_DPHY_AON_POWER_READY_N_MASK BIT(0)
> +#define STF_DPHY_CFG_L0_SWAP_SEL_SHIFT 0xcU
> +#define STF_DPHY_CFG_L0_SWAP_SEL_MASK GENMASK(14, 12)
> +#define STF_DPHY_CFG_L1_SWAP_SEL_SHIFT 0xfU
> +#define STF_DPHY_CFG_L1_SWAP_SEL_MASK GENMASK(17, 15)
> +#define STF_DPHY_CFG_L2_SWAP_SEL_SHIFT 0x12U
> +#define STF_DPHY_CFG_L2_SWAP_SEL_MASK GENMASK(20, 18)
> +#define STF_DPHY_CFG_L3_SWAP_SEL_SHIFT 0x15U
> +#define STF_DPHY_CFG_L3_SWAP_SEL_MASK GENMASK(23, 21)
> +#define STF_DPHY_CFG_L4_SWAP_SEL_SHIFT 0x18U
> +#define STF_DPHY_CFG_L4_SWAP_SEL_MASK GENMASK(26, 24)
> +#define STF_DPHY_RGS_CDTX_PLL_UNLOCK_SHIFT 0x12U
> +#define STF_DPHY_RGS_CDTX_PLL_UNLOCK_MASK BIT(18)
> +#define STF_DPHY_RG_CDTX_L0N_HSTX_RES_SHIFT 0x13U
> +#define STF_DPHY_RG_CDTX_L0N_HSTX_RES_MASK GENMASK(23, 19)
> +#define STF_DPHY_RG_CDTX_L0P_HSTX_RES_SHIFT 0x18U
> +#define STF_DPHY_RG_CDTX_L0P_HSTX_RES_MASK GENMASK(28, 24)
> +
> +#define STF_DPHY_RG_CDTX_L1P_HSTX_RES_SHIFT 0x5U
> +#define STF_DPHY_RG_CDTX_L1P_HSTX_RES_MASK GENMASK(9, 5)
> +#define STF_DPHY_RG_CDTX_L2N_HSTX_RES_SHIFT 0xaU
> +#define STF_DPHY_RG_CDTX_L2N_HSTX_RES_MASK GENMASK(14, 10)
> +#define STF_DPHY_RG_CDTX_L2P_HSTX_RES_SHIFT 0xfU
> +#define STF_DPHY_RG_CDTX_L2P_HSTX_RES_MASK GENMASK(19, 15)
> +#define STF_DPHY_RG_CDTX_L3N_HSTX_RES_SHIFT 0x14U
> +#define STF_DPHY_RG_CDTX_L3N_HSTX_RES_MASK GENMASK(24, 20)
> +#define STF_DPHY_RG_CDTX_L3P_HSTX_RES_SHIFT 0x19U
> +#define STF_DPHY_RG_CDTX_L3P_HSTX_RES_MASK GENMASK(29, 25)
can you get rid of the shift defines. Please use FEILD_PREP and
FIELD_GET which uses the bitmasks you have defined about (you can drop
_MASK from above)
> +
> +#define STF_DPHY_RG_CDTX_L4N_HSTX_RES_SHIFT 0x0U
> +#define STF_DPHY_RG_CDTX_L4N_HSTX_RES_MASK GENMASK(4, 0)
> +#define STF_DPHY_RG_CDTX_L4P_HSTX_RES_SHIFT 0x5U
> +#define STF_DPHY_RG_CDTX_L4P_HSTX_RES_MASK GENMASK(9, 5)
> +#define STF_DPHY_RG_CDTX_PLL_FBK_FRA_SHIFT 0x0U
> +#define STF_DPHY_RG_CDTX_PLL_FBK_FRA_MASK GENMASK(23, 0)
> +
> +#define STF_DPHY_RG_CDTX_PLL_FBK_INT_SHIFT 0x0U
> +#define STF_DPHY_RG_CDTX_PLL_FBK_INT_MASK GENMASK(8, 0)
> +#define STF_DPHY_RG_CDTX_PLL_FM_EN_SHIFT 0x9U
> +#define STF_DPHY_RG_CDTX_PLL_FM_EN_MASK BIT(9)
> +#define STF_DPHY_RG_CDTX_PLL_LDO_STB_X2_EN_SHIFT 0xaU
> +#define STF_DPHY_RG_CDTX_PLL_LDO_STB_X2_EN_MASK BIT(10)
> +#define STF_DPHY_RG_CDTX_PLL_PRE_DIV_SHIFT 0xbU
> +#define STF_DPHY_RG_CDTX_PLL_PRE_DIV_MASK GENMASK(12, 11)
> +
> +#define STF_DPHY_RG_CDTX_PLL_SSC_EN_SHIFT 0x12U
> +#define STF_DPHY_RG_CDTX_PLL_SSC_EN_MASK 0x40000U
> +
> +#define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME_SHIFT 0x0U
> +#define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME_MASK GENMASK(7, 0)
> +#define STF_DPHY_RG_CLANE_HS_CLK_PRE_TIME_SHIFT 0x8U
> +#define STF_DPHY_RG_CLANE_HS_CLK_PRE_TIME_MASK GENMASK(15, 8)
> +#define STF_DPHY_RG_CLANE_HS_PRE_TIME_SHIFT 0x10U
> +#define STF_DPHY_RG_CLANE_HS_PRE_TIME_MASK GENMASK(23, 16)
> +#define STF_DPHY_RG_CLANE_HS_TRAIL_TIME_SHIFT 0x18U
> +#define STF_DPHY_RG_CLANE_HS_TRAIL_TIME_MASK GENMASK(31, 24)
> +
> +#define STF_DPHY_RG_CLANE_HS_ZERO_TIME_SHIFT 0x0U
> +#define STF_DPHY_RG_CLANE_HS_ZERO_TIME_MASK GENMASK(7, 0)
> +#define STF_DPHY_RG_DLANE_HS_PRE_TIME_SHIFT 0x8U
> +#define STF_DPHY_RG_DLANE_HS_PRE_TIME_MASK GENMASK(15, 8)
> +#define STF_DPHY_RG_DLANE_HS_TRAIL_TIME_SHIFT 0x10U
> +#define STF_DPHY_RG_DLANE_HS_TRAIL_TIME_MASK GENMASK(23, 16)
> +#define STF_DPHY_RG_DLANE_HS_ZERO_TIME_SHIFT 0x18U
> +#define STF_DPHY_RG_DLANE_HS_ZERO_TIME_MASK GENMASK(31, 24)
> +
> +#define STF_DPHY_RG_EXTD_CYCLE_SEL_SHIFT 0x0U
> +#define STF_DPHY_RG_EXTD_CYCLE_SEL_MASK GENMASK(2, 0)
> +#define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME_SHIFT 0x0U
> +#define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME_MASK GENMASK(31, 0)
> +
> +#define STF_DPHY_SCFG_DSI_TXREADY_ESC_SEL_SHIFT 0x1U
> +#define STF_DPHY_SCFG_DSI_TXREADY_ESC_SEL_MASK GENMASK(2, 1)
> +#define STF_DPHY_SCFG_PPI_C_READY_SEL_SHIFT 0x3U
> +#define STF_DPHY_SCFG_PPI_C_READY_SEL_MASK GENMASK(4, 3)
> +
> +#define STF_DPHY_REFCLK_IN_SEL_SHIFT 0x1aU
> +#define STF_DPHY_REFCLK_IN_SEL_MASK GENMASK(28, 26)
> +#define STF_DPHY_RESETB_SHIFT 0x1dU
> +#define STF_DPHY_RESETB_MASK BIT(29)
> +
> +#define STF_DPHY_REFCLK_12M 1
> +#define STF_DPHY_BITRATE_ALIGN 10000000
> +
> +#define STF_MAP_LANES_NUM 5
> +
> +#define STF_DPHY_LSHIFT_16(x) ((x) << 16)
> +#define STF_DPHY_LSHIFT_8(x) ((x) << 8)
these two should be dropped
> +
> +struct m31_dphy_config {
> + int ref_clk;
why is this signed?
> + unsigned long bitrate;
> + u32 pll_prev_div;
> + u32 pll_fbk_int;
> + u32 pll_fbk_fra;
> + u32 extd_cycle_sel;
> + u32 dlane_hs_pre_time;
> + u32 dlane_hs_zero_time;
> + u32 dlane_hs_trail_time;
> + u32 clane_hs_pre_time;
> + u32 clane_hs_zero_time;
> + u32 clane_hs_trail_time;
> + u32 clane_hs_clk_pre_time;
> + u32 clane_hs_clk_post_time;
> +};
> +
> +static const struct m31_dphy_config m31_dphy_configs[] = {
> + {12000000, 160000000, 0x0, 0x6a,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d},
you can add this in a single line, that would be more readable...
> + {12000000, 170000000, 0x0, 0x71,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x3, 0xb, 0x18, 0x11, 0x5, 0x2e, 0xd, 0x7, 0x3d},
> + {12000000, 180000000, 0x0, 0x78,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x3, 0xb, 0x19, 0x12, 0x6, 0x30, 0xe, 0x7, 0x3e},
> + {12000000, 190000000, 0x0, 0x7e,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x3, 0xc, 0x1a, 0x12, 0x6, 0x33, 0xe, 0x7, 0x3e},
> + {12000000, 200000000, 0x0, 0x85,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x3, 0xc, 0x1b, 0x13, 0x7, 0x35, 0xf, 0x7, 0x3f},
> + {12000000, 320000000, 0x0, 0x6a,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x2, 0x8, 0x14, 0xf, 0x5, 0x2b, 0xd, 0x3, 0x23},
> + {12000000, 330000000, 0x0, 0x6e,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x2, 0x8, 0x15, 0xf, 0x5, 0x2d, 0xd, 0x3, 0x23},
> + {12000000, 340000000, 0x0, 0x71,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x2, 0x9, 0x15, 0xf, 0x5, 0x2e, 0xd, 0x3, 0x23},
> + {12000000, 350000000, 0x0, 0x74,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x2, 0x9, 0x15, 0x10, 0x6, 0x2f, 0xe, 0x3, 0x24},
> + {12000000, 360000000, 0x0, 0x78,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x2, 0x9, 0x16, 0x10, 0x6, 0x30, 0xe, 0x3, 0x24},
> + {12000000, 370000000, 0x0, 0x7b,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x2, 0x9, 0x17, 0x10, 0x6, 0x32, 0xe, 0x3, 0x24},
> + {12000000, 380000000, 0x0, 0x7e,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x2, 0xa, 0x17, 0x10, 0x6, 0x33, 0xe, 0x3, 0x24},
> + {12000000, 390000000, 0x0, 0x82,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0, 0x2,
> + 0xa, 0x17, 0x11, 0x6, 0x35, 0xf, 0x3, 0x25},
> + {12000000, 400000000, 0x0, 0x85,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x2, 0xa, 0x18, 0x11, 0x7, 0x35, 0xf, 0x3, 0x25},
> + {12000000, 410000000, 0x0, 0x88,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x2, 0xa, 0x19, 0x11, 0x7, 0x37, 0xf, 0x3, 0x25},
> + {12000000, 420000000, 0x0, 0x8c,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x2, 0xa, 0x19, 0x12, 0x7, 0x38, 0x10, 0x3, 0x26},
> + {12000000, 430000000, 0x0, 0x8f,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x2, 0xb, 0x19, 0x12, 0x7, 0x39, 0x10, 0x3, 0x26},
> + {12000000, 440000000, 0x0, 0x92,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x2, 0xb, 0x1a, 0x12, 0x7, 0x3b, 0x10, 0x3, 0x26},
> + {12000000, 450000000, 0x0, 0x96,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x2, 0xb, 0x1b, 0x12, 0x8, 0x3c, 0x10, 0x3, 0x26},
> + {12000000, 460000000, 0x0, 0x99,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x2, 0xb, 0x1b, 0x13, 0x8, 0x3d, 0x11, 0x3, 0x27},
> + {12000000, 470000000, 0x0, 0x9c,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x2, 0xc, 0x1b, 0x13, 0x8, 0x3e, 0x11, 0x3, 0x27},
> + {12000000, 480000000, 0x0, 0xa0,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x2, 0xc, 0x1c, 0x13, 0x8, 0x40, 0x11, 0x3, 0x27},
> + {12000000, 490000000, 0x0, 0xa3,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x2, 0xc, 0x1d, 0x14, 0x8, 0x42, 0x12, 0x3, 0x28},
> + {12000000, 500000000, 0x0, 0xa6,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x2, 0xc, 0x1d, 0x14, 0x9, 0x42, 0x12, 0x3, 0x28},
> + {12000000, 510000000, 0x0, 0xaa,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x2, 0xc, 0x1e, 0x14, 0x9, 0x44, 0x12, 0x3, 0x28},
> + {12000000, 520000000, 0x0, 0xad,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x2, 0xd, 0x1e, 0x15, 0x9, 0x45, 0x13, 0x3, 0x29},
> + {12000000, 530000000, 0x0, 0xb0,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x2, 0xd, 0x1e, 0x15, 0x9, 0x47, 0x13, 0x3, 0x29},
> + {12000000, 540000000, 0x0, 0xb4,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x2, 0xd, 0x1f, 0x15, 0x9, 0x48, 0x13, 0x3, 0x29},
> + {12000000, 550000000, 0x0, 0xb7,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x2, 0xd, 0x20, 0x16, 0x9, 0x4a, 0x14, 0x3, 0x2a},
> + {12000000, 560000000, 0x0, 0xba,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x2, 0xe, 0x20, 0x16, 0xa, 0x4a, 0x14, 0x3, 0x2a},
> + {12000000, 570000000, 0x0, 0xbe,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x2, 0xe, 0x20, 0x16, 0xa, 0x4c, 0x14, 0x3, 0x2a},
> + {12000000, 580000000, 0x0, 0xc1,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x2, 0xe, 0x21, 0x16, 0xa, 0x4d, 0x14, 0x3, 0x2a},
> + {12000000, 590000000, 0x0, 0xc4,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x2, 0xe, 0x22, 0x17, 0xa, 0x4f, 0x15, 0x3, 0x2b},
> + {12000000, 600000000, 0x0, 0xc8,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x2, 0xe, 0x23, 0x17, 0xa, 0x50, 0x15, 0x3, 0x2b},
> + {12000000, 610000000, 0x0, 0xcb,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x2, 0xf, 0x22, 0x17, 0xb, 0x50, 0x15, 0x3, 0x2b},
> + {12000000, 620000000, 0x0, 0xce,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x2, 0xf, 0x23, 0x18, 0xb, 0x52, 0x16, 0x3, 0x2c},
> + {12000000, 630000000, 0x0, 0x69,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x1, 0x7, 0x12, 0xd, 0x5, 0x2a, 0xc, 0x1, 0x15},
> + {12000000, 640000000, 0x0, 0x6a,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x1, 0x7, 0x13, 0xe, 0x5, 0x2b, 0xd, 0x1, 0x16},
> + {12000000, 650000000, 0x0, 0x6c,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x1, 0x7, 0x13, 0xe, 0x5, 0x2c, 0xd, 0x1, 0x16},
> + {12000000, 660000000, 0x0, 0x6e,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x1, 0x7, 0x13, 0xe, 0x5, 0x2d, 0xd, 0x1, 0x16},
> + {12000000, 670000000, 0x0, 0x6f,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x1, 0x8, 0x13, 0xe, 0x5, 0x2d, 0xd, 0x1, 0x16},
> + {12000000, 680000000, 0x0, 0x71,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x1, 0x8, 0x13, 0xe, 0x5, 0x2e, 0xd, 0x1, 0x16},
> + {12000000, 690000000, 0x0, 0x73,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x1, 0x8, 0x14, 0xe, 0x6, 0x2e, 0xd, 0x1, 0x16},
> + {12000000, 700000000, 0x0, 0x74,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x1, 0x8, 0x14, 0xf, 0x6, 0x2f, 0xe, 0x1, 0x16},
> + {12000000, 710000000, 0x0, 0x76,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x1, 0x8, 0x14, 0xf, 0x6, 0x2f, 0xe, 0x1, 0x17},
> + {12000000, 720000000, 0x0, 0x78,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x1, 0x8, 0x15, 0xf, 0x6, 0x30, 0xe, 0x1, 0x17},
> + {12000000, 730000000, 0x0, 0x79,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x1, 0x8, 0x15, 0xf, 0x6, 0x31, 0xe, 0x1, 0x17},
> + {12000000, 740000000, 0x0, 0x7b,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x1, 0x8, 0x15, 0xf, 0x6, 0x32, 0xe, 0x1, 0x17},
> + {12000000, 750000000, 0x0, 0x7d,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x1, 0x8, 0x16, 0xf, 0x6, 0x32, 0xe, 0x1, 0x17},
> + {12000000, 760000000, 0x0, 0x7e,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x1, 0x9, 0x15, 0xf, 0x6, 0x33, 0xe, 0x1, 0x17},
> + {12000000, 770000000, 0x0, 0x80,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x1, 0x9, 0x15, 0x10, 0x6, 0x34, 0xf, 0x1, 0x18},
> + {12000000, 780000000, 0x0, 0x82,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x1, 0x9, 0x16, 0x10, 0x6, 0x35, 0xf, 0x1, 0x18,},
> + {12000000, 790000000, 0x0, 0x83,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x1, 0x9, 0x16, 0x10, 0x7, 0x34, 0xf, 0x1, 0x18},
> + {12000000, 800000000, 0x0, 0x85,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x1, 0x9, 0x17, 0x10, 0x7, 0x35, 0xf, 0x1, 0x18},
> + {12000000, 810000000, 0x0, 0x87,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x1, 0x9, 0x17, 0x10, 0x7, 0x36, 0xf, 0x1, 0x18},
> + {12000000, 820000000, 0x0, 0x88,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x1, 0x9, 0x17, 0x10, 0x7, 0x37, 0xf, 0x1, 0x18},
> + {12000000, 830000000, 0x0, 0x8a,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x1, 0x9, 0x18, 0x10, 0x7, 0x37, 0xf, 0x1, 0x18},
> + {12000000, 840000000, 0x0, 0x8c,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x1, 0x9, 0x18, 0x11, 0x7, 0x38, 0x10, 0x1, 0x19},
> + {12000000, 850000000, 0x0, 0x8d,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x1, 0xa, 0x17, 0x11, 0x7, 0x39, 0x10, 0x1, 0x19},
> + {12000000, 860000000, 0x0, 0x8f,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x1, 0xa, 0x18, 0x11, 0x7, 0x39, 0x10, 0x1, 0x19},
> + {12000000, 870000000, 0x0, 0x91,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x1, 0xa, 0x18, 0x11, 0x7, 0x3a, 0x10, 0x1, 0x19},
> + {12000000, 880000000, 0x0, 0x92,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x1, 0xa, 0x18, 0x11, 0x7, 0x3b, 0x10, 0x1, 0x19},
> + {12000000, 890000000, 0x0, 0x94,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x1, 0xa, 0x19, 0x11, 0x7, 0x3c, 0x10, 0x1, 0x19},
> + {12000000, 900000000, 0x0, 0x96,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x1, 0xa, 0x19, 0x12, 0x8, 0x3c, 0x10, 0x1, 0x19},
> + {12000000, 910000000, 0x0, 0x97,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x1, 0xa, 0x19, 0x12, 0x8, 0x3c, 0x11, 0x1, 0x1a},
> + {12000000, 920000000, 0x0, 0x99,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x1, 0xa, 0x1a, 0x12, 0x8, 0x3d, 0x11, 0x1, 0x1a},
> + {12000000, 930000000, 0x0, 0x9b,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x1, 0xa, 0x1a, 0x12, 0x8, 0x3e, 0x11, 0x1, 0x1a},
> + {12000000, 940000000, 0x0, 0x9c,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x1, 0xb, 0x1a, 0x12, 0x8, 0x3e, 0x11, 0x1, 0x1a},
> + {12000000, 950000000, 0x0, 0x9e,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x1, 0xb, 0x1a, 0x12, 0x8, 0x3f, 0x11, 0x1, 0x1a},
> + {12000000, 960000000, 0x0, 0xa0,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x1, 0xb, 0x1a, 0x12, 0x8, 0x40, 0x11, 0x1, 0x1a},
> + {12000000, 970000000, 0x0, 0xa1,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x1, 0xb, 0x1b, 0x13, 0x8, 0x41, 0x12, 0x1, 0x1b},
> + {12000000, 980000000, 0x0, 0xa3,
> + STF_DPHY_LSHIFT_16(0x55) | STF_DPHY_LSHIFT_8(0x55) | 0x55,
> + 0x1, 0xb, 0x1b, 0x13, 0x8, 0x42, 0x12, 0x1, 0x1b},
> + {12000000, 990000000, 0x0, 0xa5,
> + STF_DPHY_LSHIFT_16(0x0) | STF_DPHY_LSHIFT_8(0x0) | 0x0,
> + 0x1, 0xb, 0x1b, 0x13, 0x8, 0x42, 0x12, 0x1, 0x1b},
> + {12000000, 1000000000, 0x0, 0xa6,
> + STF_DPHY_LSHIFT_16(0xaa) | STF_DPHY_LSHIFT_8(0xaa) | 0xaa,
> + 0x1, 0xb, 0x1c, 0x13, 0x9, 0x42, 0x12, 0x1, 0x1b},
> +};
> +
> +struct stf_dphy_info {
> + /**
> + * @maps:
> + *
> + * Physical lanes and logic lanes mapping table.
> + *
> + * The default order is:
> + * [data lane 0, data lane 1, data lane 2, date lane 3, clk lane]
> + */
> + u8 maps[STF_MAP_LANES_NUM];
> +};
> +
> +struct stf_dphy {
> + struct device *dev;
> + void __iomem *topsys;
> + struct clk *txesc_clk;
> + struct reset_control *sys_rst;
> +
> + struct phy_configure_opts_mipi_dphy config;
> +
> + struct phy *phy;
> + const struct stf_dphy_info *info;
> +};
> +
> +static inline u32 stf_dphy_get_reg(void __iomem *io_addr, u32 addr, u32 shift, u32 mask)
> +{
> + u32 tmp;
> +
> + tmp = readl(io_addr);
> + tmp = (tmp & mask) >> shift;
> + return tmp;
> +}
> +
> +static inline void stf_dphy_set_reg(void __iomem *io_addr, u32 addr, u32 data, u32 shift, u32 mask)
> +{
> + u32 tmp;
> +
> + tmp = readl(io_addr + addr);
> + tmp &= ~mask;
> + tmp |= (data << shift) & mask;
> + writel(tmp, (io_addr + addr));
> +}
> +
> +static int is_pll_locked(struct stf_dphy *dphy)
> +{
> + int tmp = stf_dphy_get_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(8),
> + STF_DPHY_RGS_CDTX_PLL_UNLOCK_SHIFT,
> + STF_DPHY_RGS_CDTX_PLL_UNLOCK_MASK);
> + return !tmp;
why inverted value?
> +}
> +
> +static void stf_dphy_hw_reset(struct stf_dphy *dphy, int assert)
> +{
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(100),
> + !assert, STF_DPHY_RESETB_SHIFT, STF_DPHY_RESETB_MASK);
> +
> + if (!assert) {
> + while ((!is_pll_locked(dphy)))
> + ;
This is infinite, that is not acceptable. Please have a decent timeout
for this...
> + dev_err(dphy->dev, "MIPI dphy-tx # PLL Locked\n");
> + }
> +}
> +
> +static int stf_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
> +{
> + struct stf_dphy *dphy = phy_get_drvdata(phy);
> + const struct stf_dphy_info *info = dphy->info;
> + u32 bitrate = opts->mipi_dphy.hs_clk_rate;
> + const struct m31_dphy_config *p;
> + unsigned long alignment;
> + int i;
> +
> + bitrate = opts->mipi_dphy.hs_clk_rate;
> +
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(8), 0x10,
> + STF_DPHY_RG_CDTX_L0N_HSTX_RES_SHIFT, STF_DPHY_RG_CDTX_L0N_HSTX_RES_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(12), 0x10,
> + STF_DPHY_RG_CDTX_L0N_HSTX_RES_SHIFT, STF_DPHY_RG_CDTX_L0N_HSTX_RES_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(12), 0x10,
> + STF_DPHY_RG_CDTX_L2N_HSTX_RES_SHIFT, STF_DPHY_RG_CDTX_L2N_HSTX_RES_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(12), 0x10,
> + STF_DPHY_RG_CDTX_L3N_HSTX_RES_SHIFT, STF_DPHY_RG_CDTX_L3N_HSTX_RES_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(16), 0x10,
> + STF_DPHY_RG_CDTX_L4N_HSTX_RES_SHIFT, STF_DPHY_RG_CDTX_L4N_HSTX_RES_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(8), 0x10,
> + STF_DPHY_RG_CDTX_L0P_HSTX_RES_SHIFT, STF_DPHY_RG_CDTX_L0P_HSTX_RES_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(12), 0x10,
> + STF_DPHY_RG_CDTX_L1P_HSTX_RES_SHIFT, STF_DPHY_RG_CDTX_L1P_HSTX_RES_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(12), 0x10,
> + STF_DPHY_RG_CDTX_L2P_HSTX_RES_SHIFT, STF_DPHY_RG_CDTX_L2P_HSTX_RES_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(12), 0x10,
> + STF_DPHY_RG_CDTX_L3P_HSTX_RES_SHIFT, STF_DPHY_RG_CDTX_L3P_HSTX_RES_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(16), 0x10,
> + STF_DPHY_RG_CDTX_L4P_HSTX_RES_SHIFT, STF_DPHY_RG_CDTX_L4P_HSTX_RES_MASK);
> +
> + alignment = STF_DPHY_BITRATE_ALIGN;
> + if (bitrate % alignment)
> + bitrate += alignment - (bitrate % alignment);
> +
> + p = m31_dphy_configs;
> + for (i = 0; i < ARRAY_SIZE(m31_dphy_configs); i++, p++) {
> + if (p->bitrate == bitrate) {
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(100),
> + STF_DPHY_REFCLK_12M, STF_DPHY_REFCLK_IN_SEL_SHIFT,
> + STF_DPHY_REFCLK_IN_SEL_MASK);
> +
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(0),
> + STF_DPHY_AON_POWER_READY_N_ACTIVE,
> + STF_DPHY_AON_POWER_READY_N_SHIFT,
> + STF_DPHY_AON_POWER_READY_N_MASK);
> +
> + /*Lane setting*/
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(0), info->maps[0],
> + STF_DPHY_CFG_L0_SWAP_SEL_SHIFT,
> + STF_DPHY_CFG_L0_SWAP_SEL_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(0), info->maps[1],
> + STF_DPHY_CFG_L1_SWAP_SEL_SHIFT,
> + STF_DPHY_CFG_L1_SWAP_SEL_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(0), info->maps[2],
> + STF_DPHY_CFG_L2_SWAP_SEL_SHIFT,
> + STF_DPHY_CFG_L2_SWAP_SEL_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(0), info->maps[3],
> + STF_DPHY_CFG_L3_SWAP_SEL_SHIFT,
> + STF_DPHY_CFG_L3_SWAP_SEL_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(0), info->maps[4],
> + STF_DPHY_CFG_L4_SWAP_SEL_SHIFT,
> + STF_DPHY_CFG_L4_SWAP_SEL_MASK);
> + /*PLL setting*/
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(28), 0x0,
> + STF_DPHY_RG_CDTX_PLL_SSC_EN_SHIFT,
> + STF_DPHY_RG_CDTX_PLL_SSC_EN_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(24), 0x1,
> + STF_DPHY_RG_CDTX_PLL_LDO_STB_X2_EN_SHIFT,
> + STF_DPHY_RG_CDTX_PLL_LDO_STB_X2_EN_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(24), 0x1,
> + STF_DPHY_RG_CDTX_PLL_FM_EN_SHIFT,
> + STF_DPHY_RG_CDTX_PLL_FM_EN_MASK);
> +
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(24),
> + p->pll_prev_div, STF_DPHY_RG_CDTX_PLL_PRE_DIV_SHIFT,
> + STF_DPHY_RG_CDTX_PLL_PRE_DIV_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(24),
> + p->pll_fbk_int, STF_DPHY_RG_CDTX_PLL_FBK_INT_SHIFT,
> + STF_DPHY_RG_CDTX_PLL_FBK_INT_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(20),
> + p->pll_fbk_fra, STF_DPHY_RG_CDTX_PLL_FBK_FRA_SHIFT,
> + STF_DPHY_RG_CDTX_PLL_FBK_FRA_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(40),
> + p->extd_cycle_sel, STF_DPHY_RG_EXTD_CYCLE_SEL_SHIFT,
> + STF_DPHY_RG_EXTD_CYCLE_SEL_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(36),
> + p->dlane_hs_pre_time,
> + STF_DPHY_RG_DLANE_HS_PRE_TIME_SHIFT,
> + STF_DPHY_RG_DLANE_HS_PRE_TIME_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(36),
> + p->dlane_hs_pre_time,
> + STF_DPHY_RG_DLANE_HS_PRE_TIME_SHIFT,
> + STF_DPHY_RG_DLANE_HS_PRE_TIME_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(36),
> + p->dlane_hs_zero_time,
> + STF_DPHY_RG_DLANE_HS_ZERO_TIME_SHIFT,
> + STF_DPHY_RG_DLANE_HS_ZERO_TIME_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(36),
> + p->dlane_hs_trail_time,
> + STF_DPHY_RG_DLANE_HS_TRAIL_TIME_SHIFT,
> + STF_DPHY_RG_DLANE_HS_TRAIL_TIME_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(32),
> + p->clane_hs_pre_time,
> + STF_DPHY_RG_CLANE_HS_PRE_TIME_SHIFT,
> + STF_DPHY_RG_CLANE_HS_PRE_TIME_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(36),
> + p->clane_hs_zero_time,
> + STF_DPHY_RG_CLANE_HS_ZERO_TIME_SHIFT,
> + STF_DPHY_RG_CLANE_HS_ZERO_TIME_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(32),
> + p->clane_hs_trail_time,
> + STF_DPHY_RG_CLANE_HS_TRAIL_TIME_SHIFT,
> + STF_DPHY_RG_CLANE_HS_TRAIL_TIME_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(32),
> + p->clane_hs_clk_pre_time,
> + STF_DPHY_RG_CLANE_HS_CLK_PRE_TIME_SHIFT,
> + STF_DPHY_RG_CLANE_HS_CLK_PRE_TIME_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(32),
> + p->clane_hs_clk_post_time,
> + STF_DPHY_RG_CLANE_HS_CLK_POST_TIME_SHIFT,
> + STF_DPHY_RG_CLANE_HS_CLK_POST_TIME_MASK);
> +
> + break;
> + }
> + }
> +
> + return 0;
this is the only return. It will always return success, consider making
this return void
> +}
> +
> +static int stf_dphy_init(struct phy *phy)
> +{
> + struct stf_dphy *dphy = phy_get_drvdata(phy);
> + int ret;
> +
> + stf_dphy_hw_reset(dphy, 0);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(48), 0,
> + STF_DPHY_SCFG_PPI_C_READY_SEL_SHIFT, STF_DPHY_SCFG_PPI_C_READY_SEL_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(48), 0,
> + STF_DPHY_SCFG_DSI_TXREADY_ESC_SEL_SHIFT,
> + STF_DPHY_SCFG_DSI_TXREADY_ESC_SEL_MASK);
> + stf_dphy_set_reg(dphy->topsys, STF_DPHY_APBIFSAIF_SYSCFG(44), 0x30,
> + STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME_SHIFT,
> + STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME_MASK);
> +
> + ret = clk_prepare_enable(dphy->txesc_clk);
> + if (ret) {
> + dev_err(dphy->dev, "Failed to prepare/enable txesc_clk\n");
> + return ret;
> + }
> +
> + ret = reset_control_deassert(dphy->sys_rst);
> + if (ret) {
> + dev_err(dphy->dev, "Failed to deassert sys_rst\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int stf_dphy_exit(struct phy *phy)
> +{
> + struct stf_dphy *dphy = phy_get_drvdata(phy);
> + int ret;
> +
> + ret = reset_control_assert(dphy->sys_rst);
> + if (ret) {
> + dev_err(dphy->dev, "Failed to assert sys_rst\n");
> + return ret;
> + }
> +
> + clk_disable_unprepare(dphy->txesc_clk);
> +
> + stf_dphy_hw_reset(dphy, 1);
> +
> + return 0;
> +}
> +
> +static int stf_dphy_power_on(struct phy *phy)
> +{
> + struct stf_dphy *dphy = phy_get_drvdata(phy);
> +
> + return pm_runtime_resume_and_get(dphy->dev);
> +}
> +
> +static int stf_dphy_validate(struct phy *phy, enum phy_mode mode, int submode,
> + union phy_configure_opts *opts)
> +{
> + if (mode != PHY_MODE_MIPI_DPHY)
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +static int stf_dphy_power_off(struct phy *phy)
> +{
> + struct stf_dphy *dphy = phy_get_drvdata(phy);
> +
> + return pm_runtime_put_sync(dphy->dev);
> +}
> +
> +static const struct phy_ops stf_dphy_ops = {
> + .power_on = stf_dphy_power_on,
> + .power_off = stf_dphy_power_off,
> + .init = stf_dphy_init,
> + .exit = stf_dphy_exit,
> + .configure = stf_dphy_configure,
> + .validate = stf_dphy_validate,
> + .owner = THIS_MODULE,
> +};
> +
> +static int stf_dphy_probe(struct platform_device *pdev)
> +{
> + struct phy_provider *phy_provider;
> + struct stf_dphy *dphy;
> +
> + dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
> + if (!dphy)
> + return -ENOMEM;
> +
> + dphy->info = of_device_get_match_data(&pdev->dev);
> +
> + dphy->dev = &pdev->dev;
> + dev_set_drvdata(&pdev->dev, dphy);
> +
> + dphy->topsys = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(dphy->topsys))
> + return PTR_ERR(dphy->topsys);
> +
> + pm_runtime_enable(&pdev->dev);
> +
> + dphy->txesc_clk = devm_clk_get(&pdev->dev, "txesc");
> + if (IS_ERR(dphy->txesc_clk))
> + return dev_err_probe(&pdev->dev, PTR_ERR(dphy->txesc_clk),
> + "Failed to get txesc clock\n");
> +
> + dphy->sys_rst = devm_reset_control_get_exclusive(&pdev->dev, "sys");
> + if (IS_ERR(dphy->sys_rst))
> + return dev_err_probe(&pdev->dev, PTR_ERR(dphy->sys_rst),
> + "Failed to get sys reset\n");
> +
> + dphy->phy = devm_phy_create(&pdev->dev, NULL, &stf_dphy_ops);
> + if (IS_ERR(dphy->phy))
> + return dev_err_probe(&pdev->dev, PTR_ERR(dphy->phy),
> + "Failed to create phy\n");
> +
> + phy_set_drvdata(dphy->phy, dphy);
> +
> + phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
> + if (IS_ERR(phy_provider))
> + return dev_err_probe(&pdev->dev, PTR_ERR(phy_provider),
> + "Failed to register phy\n");
> +
> + return 0;
> +}
> +
> +static const struct stf_dphy_info starfive_dphy_info = {
> + .maps = {0, 1, 2, 3, 4},
> +};
> +
> +static const struct of_device_id stf_dphy_dt_ids[] = {
> + {
> + .compatible = "starfive,jh7110-dphy-tx",
> + .data = &starfive_dphy_info,
> + },
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, stf_dphy_dt_ids);
> +
> +static struct platform_driver stf_dphy_driver = {
> + .driver = {
> + .name = "starfive-dphy-tx",
> + .of_match_table = stf_dphy_dt_ids,
> + },
> + .probe = stf_dphy_probe,
> +};
> +module_platform_driver(stf_dphy_driver);
> +
> +MODULE_AUTHOR("Keith Zhao <keith.zhao@starfivetech.com>");
> +MODULE_AUTHOR("Shengyang Chen <shengyang.chen@starfivetech.com>");
> +MODULE_DESCRIPTION("StarFive JH7110 DPHY TX driver");
> +MODULE_LICENSE("GPL");
> --
> 2.17.1
>
>
> --
> linux-phy mailing list
> linux-phy@lists.infradead.org
> https://lists.infradead.org/mailman/listinfo/linux-phy
--
~Vinod
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: omap-mcpdm: Convert to DT schema
From: Mithil @ 2024-04-05 16:29 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, alsa-devel, devicetree, linux-kernel
In-Reply-To: <ec7f77a7-2cf1-4ea6-b9c4-d4fe8a1673ab@linaro.org>
On Fri, Apr 5, 2024 at 9:27 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 05/04/2024 16:48, Mithil wrote:
> > So sorry about the 2nd patch being sent as a new mail, here is a new
> > patch with the changes as suggested
> >
> >> Please use subject prefixes matching the subsystem
> > Changed the patch name to match the folder history.
>
> Nothing improved. What the history tells you?
>
Referred to "ASoC: dt-bindings: rt1015: Convert to dtschema"
Not really sure what else I should change.
> >
> >> Is it your full name?
> > Fixed it, my apologies.
> >
> >> Filename like compatible.
> > Fixed.
>
> Still not, compatible is omap4.
>
Sorry, seems like I was sending the old file again.
Will fix this.
> >
> >> Please open existing bindings and look how it is done there.
> > Changed it, is it fine now?
>
> You mean v2? I have no clue to what you are responding here, but no, v2
> did not improve much.
>
Again, could you guide me to what needs to be done?
Description for reg should be fine as this is how it is done in other
files as well.
Interrupts and hwmods use maxItems now.
Changed nodename to be generic in example as well.
Those were the suggested changes previously.
Best regards,
Mithil
^ permalink raw reply
* Re: [PATCH v2 2/2] Input: edt-ft5x06 - add ft5426
From: Andreas Kemnade @ 2024-04-05 16:28 UTC (permalink / raw)
To: Andy Shevchenko
Cc: dmitry.torokhov, robh+dt, krzysztof.kozlowski+dt, conor+dt,
o.rempel, u.kleine-koenig, hdegoede, ye.xingchen, p.puschmann,
linux-input, devicetree, linux-kernel, caleb.connolly
In-Reply-To: <CAHp75VeZ9U_+1rJQjr4KvvzjYQGzfKtk+BK00vqvKcVn2-yP3g@mail.gmail.com>
On Fri, 5 Apr 2024 18:13:45 +0300
Andy Shevchenko <andy.shevchenko@gmail.com> wrote:
> On Fri, Apr 5, 2024 at 1:20 AM Andreas Kemnade <andreas@kemnade.info> wrote:
> >
> > As ft5426 seems to be compatible with this driver, add it.
> > Debug output during identification: Model "generic ft5x06 (79)", Rev. "
>
> ...
>
> > @@ -1484,6 +1484,7 @@ static const struct of_device_id edt_ft5x06_of_match[] = {
> > { .compatible = "edt,edt-ft5206", .data = &edt_ft5x06_data },
> > { .compatible = "edt,edt-ft5306", .data = &edt_ft5x06_data },
> > { .compatible = "edt,edt-ft5406", .data = &edt_ft5x06_data },
> > + { .compatible = "focaltech,ft5426", .data = &edt_ft5506_data },
>
> Why a different vendor prefix?
> In case you need to use this one, keep the list sorted, currently this
> splits the edt,* ones.
>
How do I know whether to use evervision or edt instead?
I sorted by the numbers. Looking at datasheets for other controllers I see
https://www.displayfuture.com/Display/datasheet/controller/FT5x06.pdf
it only mentions FocalTech Systems Co., Ltd.
So how the vendor prefixes are derived?
Regards,
Andreas
^ permalink raw reply
* Re: [PATCH v3 18/25] dt-bindings: media: imx258: Add alternate compatible strings
From: Conor Dooley @ 2024-04-05 16:24 UTC (permalink / raw)
To: Dave Stevenson
Cc: git, linux-media, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, pavel, phone-devel
In-Reply-To: <20240405-affair-cruelly-a7e9d23b597c@spud>
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On Fri, Apr 05, 2024 at 05:24:11PM +0100, Conor Dooley wrote:
> On Fri, Apr 05, 2024 at 11:25:50AM +0100, Dave Stevenson wrote:
> > Hi Conor
> >
> > On Wed, 3 Apr 2024 at 17:14, Conor Dooley <conor@kernel.org> wrote:
> > >
> > > On Wed, Apr 03, 2024 at 09:03:47AM -0600, git@luigi311.com wrote:
> > > > From: Dave Stevenson <dave.stevenson@raspberrypi.com>
> > > >
> > > > There are a number of variants of the imx258 modules that can not
> > > > be differentiated at runtime, so add compatible strings for the
> > > > PDAF variant.
> > > >
> > > > Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> > > > Signed-off-by: Luis Garcia <git@luigi311.com>
> > > > ---
> > > > .../devicetree/bindings/media/i2c/sony,imx258.yaml | 9 +++++++--
> > > > 1 file changed, 7 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
> > > > index bee61a443b23..c978abc0cdb3 100644
> > > > --- a/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
> > > > +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
> > > > @@ -13,11 +13,16 @@ description: |-
> > > > IMX258 is a diagonal 5.867mm (Type 1/3.06) 13 Mega-pixel CMOS active pixel
> > > > type stacked image sensor with a square pixel array of size 4208 x 3120. It
> > > > is programmable through I2C interface. Image data is sent through MIPI
> > > > - CSI-2.
> > > > + CSI-2. The sensor exists in two different models, a standard variant
> > > > + (IMX258) and a variant with phase detection autofocus (IMX258-PDAF).
> > > > + The camera module does not expose the model through registers, so the
> > > > + exact model needs to be specified.
> > > >
> > > > properties:
> > > > compatible:
> > > > - const: sony,imx258
> > > > + enum:
> > > > + - sony,imx258
> > > > + - sony,imx258-pdaf
> > >
> > > Does the pdaf variant support all of the features/is it register
> > > compatible with the regular variant? If it is, the regular variant
> > > should be a fallback compatible.
> >
> > It has the same register set, but certain registers have to be
> > programmed differently so that the image is corrected for the
> > partially shielded pixels used for phase detect auto focus (PDAF).
> > Either compatible will "work" on either variant of the module, but
> > you'll get weird image artifacts when using the wrong one.
>
> To paraphase, a fallback compatible is not suitable.
Whoops, I forgot this:
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
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^ permalink raw reply
* Re: [PATCH v3 18/25] dt-bindings: media: imx258: Add alternate compatible strings
From: Conor Dooley @ 2024-04-05 16:24 UTC (permalink / raw)
To: Dave Stevenson
Cc: git, linux-media, jacopo.mondi, mchehab, robh,
krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, sakari.ailus, devicetree, imx, linux-arm-kernel,
linux-kernel, pavel, phone-devel
In-Reply-To: <CAPY8ntC9SHJ6Ma17s0Vf2coB-0NUk-xgCLK9KCkxFMuXKHXNwg@mail.gmail.com>
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On Fri, Apr 05, 2024 at 11:25:50AM +0100, Dave Stevenson wrote:
> Hi Conor
>
> On Wed, 3 Apr 2024 at 17:14, Conor Dooley <conor@kernel.org> wrote:
> >
> > On Wed, Apr 03, 2024 at 09:03:47AM -0600, git@luigi311.com wrote:
> > > From: Dave Stevenson <dave.stevenson@raspberrypi.com>
> > >
> > > There are a number of variants of the imx258 modules that can not
> > > be differentiated at runtime, so add compatible strings for the
> > > PDAF variant.
> > >
> > > Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> > > Signed-off-by: Luis Garcia <git@luigi311.com>
> > > ---
> > > .../devicetree/bindings/media/i2c/sony,imx258.yaml | 9 +++++++--
> > > 1 file changed, 7 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
> > > index bee61a443b23..c978abc0cdb3 100644
> > > --- a/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
> > > +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml
> > > @@ -13,11 +13,16 @@ description: |-
> > > IMX258 is a diagonal 5.867mm (Type 1/3.06) 13 Mega-pixel CMOS active pixel
> > > type stacked image sensor with a square pixel array of size 4208 x 3120. It
> > > is programmable through I2C interface. Image data is sent through MIPI
> > > - CSI-2.
> > > + CSI-2. The sensor exists in two different models, a standard variant
> > > + (IMX258) and a variant with phase detection autofocus (IMX258-PDAF).
> > > + The camera module does not expose the model through registers, so the
> > > + exact model needs to be specified.
> > >
> > > properties:
> > > compatible:
> > > - const: sony,imx258
> > > + enum:
> > > + - sony,imx258
> > > + - sony,imx258-pdaf
> >
> > Does the pdaf variant support all of the features/is it register
> > compatible with the regular variant? If it is, the regular variant
> > should be a fallback compatible.
>
> It has the same register set, but certain registers have to be
> programmed differently so that the image is corrected for the
> partially shielded pixels used for phase detect auto focus (PDAF).
> Either compatible will "work" on either variant of the module, but
> you'll get weird image artifacts when using the wrong one.
To paraphase, a fallback compatible is not suitable.
Thanks Dave,
Conor.
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^ permalink raw reply
* Re: [PATCH v5 2/2] iio: adc: adding support for PAC193x
From: Conor Dooley @ 2024-04-05 16:14 UTC (permalink / raw)
To: Marius.Cristea
Cc: jic23, Conor.Dooley, linux, jdelvare, linux-iio, devicetree, lars,
linux-kernel, linux-hwmon, krzysztof.kozlowski+dt, robh+dt,
conor+dt
In-Reply-To: <e432bddc16952d9144ccf6da5a54b88e3171b947.camel@microchip.com>
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On Fri, Apr 05, 2024 at 12:53:38PM +0000, Marius.Cristea@microchip.com wrote:
> Hi Conor,
>
> Thanks for reporting the bug. I have detect it and I'm already
> working on a patch for it.
Oh cool, keep me posted :)
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^ permalink raw reply
* Re: [PATCH v5 02/10] dt-bindings: mailbox: Add mboxes property for CMDQ secure driver
From: Conor Dooley @ 2024-04-05 16:13 UTC (permalink / raw)
To: Jason-JH Lin (林睿祥)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
Houlong Wei (魏厚龙),
devicetree@vger.kernel.org, Shawn Sung (宋孝謙),
CK Hu (胡俊光), conor+dt@kernel.org,
robh@kernel.org, linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
jassisinghbrar@gmail.com, angelogioacchino.delregno@collabora.com
In-Reply-To: <e6a30feb1e4bb41c90df5e0272385d0f47a7dcab.camel@mediatek.com>
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On Fri, Apr 05, 2024 at 02:33:14PM +0000, Jason-JH Lin (林睿祥) wrote:
> On Thu, 2024-04-04 at 15:52 +0100, Conor Dooley wrote:
> > On Thu, Apr 04, 2024 at 04:31:06AM +0000, Jason-JH Lin (林睿祥) wrote:
> > > Hi Conor,
> > >
> > > Thanks for the reviews.
> > >
> > > On Wed, 2024-04-03 at 16:46 +0100, Conor Dooley wrote:
> > > > On Wed, Apr 03, 2024 at 06:25:54PM +0800, Shawn Sung wrote:
> > > > > From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
> > > > >
> > > > > Add mboxes to define a GCE loopping thread as a secure irq
> > > > > handler.
> > > > > This property is only required if CMDQ secure driver is
> > > > > supported.
> > > > >
> > > > > Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> > > > > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > > > > ---
> > > > > .../bindings/mailbox/mediatek,gce-mailbox.yaml | 10
> > > > > ++++++++++
> > > > > 1 file changed, 10 insertions(+)
> > > > >
> > > > > diff --git
> > > > > a/Documentation/devicetree/bindings/mailbox/mediatek,gce-
> > > > > mailbox.yaml
> > > > > b/Documentation/devicetree/bindings/mailbox/mediatek,gce-
> > > > > mailbox.yaml
> > > > > index cef9d76013985..c0d80cc770899 100644
> > > > > --- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-
> > > > > mailbox.yaml
> > > > > +++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-
> > > > > mailbox.yaml
> > > > > @@ -49,6 +49,16 @@ properties:
> > > > > items:
> > > > > - const: gce
> > > > >
> > > > > + mediatek,gce-events:
> > > > > + description:
> > > > > + The event id which is mapping to the specific hardware
> > > > > event
> > > > > signal
> > > > > + to gce. The event id is defined in the gce header
> > > > > + include/dt-bindings/gce/<chip>-gce.h of each chips.
> > > >
> > > > Missing any info here about when this should be used, hint - you
> > > > have
> > > > it
> > > > in the commit message.
> > > >
> > > > > + $ref: /schemas/types.yaml#/definitions/uint32-arrayi
> > > >
> > > > Why is the ID used by the CMDQ service not fixed for each SoC?
> > > >
> > >
> > > I forgot to sync with Shawn about this:
> > > https://lore.kernel.org/all/20240124011459.12204-1-jason-
> > > jh.lin@mediatek.com
> > >
> > > I'll fix it at the next version.
> >
> > When I say "fixed" I don't mean "this is wrong, please fix it", I
> > mean
> > "why is the value not static for a particular SoC". This needs to be
> > explained in the patch (and the description for the event here needs
> > to
> > explain what the gce-mailbox is reserving an event for).
> >
> Oh, I see. Thanks for noticing me.
>
> We do want to reserve a static event ID for gce-mailbox to different
> SoCs. There are 2 mainly reasons to why we set it in DTS:
> 1. There are 1024 events IDs for GCE to use to execute instructions in
> the specific event happened. These events could be signaled by HW or SW
> and their value would be different in different SoC because of HW event
> IDs distribution range from 0 to 1023.
> If we set a static event ID: 855 for mt8188, it might be conflict the
> event ID original set in mt8195.
That's not a problem, we have compatibles for this purpose.
> 2. If we defined the event ID in DTS, we might know how many SW or HW
> event IDs are used.
> If someone wants to use a new event ID for a new feature, they could
> find out the used event IDs in DTS easily and avoid the event ID
> conflicting.
Are the event IDs not documented in the reference manual for the SoC in
question? Or in documentation for the secure world for these devices? A
DTS should not be the authoritive source for this information for
developers.
Additionally, the driver could very easily detect if someone does happen
to put in the reserved ID. That could be generically useful (IOW, check
all of them for re-use) if the ID are to not allowed to be shared.
> The reason why we define a event ID is we want to get a SW signal from
> secure world. We design a GCE looping thread in gce-mailbox driver to
> wait for the GCE execute done event for each cmdq secure packets from
> secure world.
This sort of information needs to be in the commit message, but I don't
think this property is needed at all since it seems to be something
detectable from the compatible.
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^ permalink raw reply
* Re: [PATCH v2 2/2] arm64: dts: rockchip: add Protonic MECSBC device-tree
From: Andrew Lunn @ 2024-04-05 16:12 UTC (permalink / raw)
To: Sascha Hauer
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
David Jander
In-Reply-To: <20240405-protonic-mecsbc-v2-2-0a6fedc78b9f@pengutronix.de>
> +&gmac1 {
> + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
> + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
> + phy-handle = <&rgmii_phy1>;
> + phy-mode = "rgmii-id";
> + clock_in_out = "output";
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac1m1_miim
> + &gmac1m1_tx_bus2
> + &gmac1m1_rx_bus2
> + &gmac1m1_rgmii_clk
> + &gmac1m1_clkinout
> + &gmac1m1_rgmii_bus>;
> + status = "okay";
> +};
Thank for changing it.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* [PATCH v1 4/4] arm64: dts: freescale: imx8mm-verdin-dahlia: support sleep-moci
From: Stefan Eichenberger @ 2024-04-05 16:07 UTC (permalink / raw)
To: robh, krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, francesco.dolcini
Cc: devicetree, imx, linux-arm-kernel, linux-kernel,
Stefan Eichenberger
In-Reply-To: <20240405160720.5977-1-eichest@gmail.com>
From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
Previously, we had the sleep-moci pin set to always on. However, the
Dahlia carrier board supports disabling the sleep-moci when the system
is suspended to power down peripherals that support it. This reduces
overall power consumption. This commit adds support for this feature by
disabling the reg_force_sleep_moci regulator and adding two new
regulators for the USB hub and PCIe that can be turned off when the
system is suspended.
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
---
.../dts/freescale/imx8mm-verdin-dahlia.dtsi | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
index b64dac4f29c2..393fc9e20423 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
@@ -32,6 +32,25 @@ simple-audio-card,cpu {
sound-dai = <&sai2>;
};
};
+
+ reg_usb_hub: regulator-usb-hub {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ regulator-name = "HUB_PWR_EN";
+ };
+
+ reg_pcie: regulator-pcie {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ regulator-name = "PCIE_1_PWR_EN";
+ startup-delay-us = <100000>;
+ };
};
/* Verdin SPI_1 */
@@ -98,6 +117,7 @@ wm8904_1a: audio-codec@1a {
/* Verdin PCIE_1 */
&pcie0 {
+ vpcie-supply = <®_pcie>;
status = "okay";
};
@@ -120,6 +140,11 @@ &pwm3 {
status = "okay";
};
+/* We support turning off sleep moci on Dahlia */
+®_force_sleep_moci {
+ status = "disabled";
+};
+
/* Verdin I2S_1 */
&sai2 {
status = "okay";
@@ -148,8 +173,16 @@ &usbotg1 {
/* Verdin USB_2 */
&usbotg2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
disable-over-current;
status = "okay";
+
+ usb-hub@1 {
+ compatible = "usb424,2744";
+ reg = <1>;
+ vdd-supply = <®_usb_hub>;
+ };
};
/* Verdin SD_1 */
--
2.40.1
^ permalink raw reply related
* [PATCH v1 3/4] arm64: dts: freescale: imx8mm-verdin: replace sleep-moci hog with regulator
From: Stefan Eichenberger @ 2024-04-05 16:07 UTC (permalink / raw)
To: robh, krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, francesco.dolcini
Cc: devicetree, imx, linux-arm-kernel, linux-kernel,
Stefan Eichenberger
In-Reply-To: <20240405160720.5977-1-eichest@gmail.com>
From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
The Verdin family has a signal called sleep-moci which can be used to
turn off peripherals on the carrier board when the SoM goes into
suspend. So far we have hogged this signal, which means the peripherals
are always on and it is not possible to add peripherals that depend on
the sleep-moci to be on. With this change, we replace the hog with a
regulator so that peripherals can add their own regulators that use the
same gpio. Carrier boards that allow peripherals to be powered off in
suspend can disable this regulator and implement their own regulator to
control the sleep-moci.
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
---
.../dts/freescale/imx8mm-verdin-dahlia.dtsi | 5 ++++
.../boot/dts/freescale/imx8mm-verdin-dev.dtsi | 5 ++++
.../dts/freescale/imx8mm-verdin-yavia.dtsi | 5 ++++
.../boot/dts/freescale/imx8mm-verdin.dtsi | 26 ++++++++++++-------
4 files changed, 31 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
index 1cff0b829357..b64dac4f29c2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
@@ -58,6 +58,11 @@ &flexspi {
status = "okay";
};
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+};
+
/* Current measurement into module VCC */
&hwmon {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
index 3c4b8ca125e3..95b7c9a03a23 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
@@ -78,6 +78,11 @@ &i2c3 {
status = "okay";
};
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+};
+
&gpio_expander_21 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi
index 1e28c78e381f..763f069e8405 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi
@@ -81,6 +81,11 @@ &gpio3 {
pinctrl-0 = <&pinctrl_gpios_ext_yavia>;
};
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+};
+
&hwmon_temp {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 6f0811587142..4768b05fd765 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -110,6 +110,22 @@ reg_ethphy: regulator-ethphy {
startup-delay-us = <200000>;
};
+ /*
+ * By default we enable CTRL_SLEEP_MOCI#, this is required to have
+ * peripherals on the carrier board powered.
+ * If more granularity or power saving is required this can be disabled
+ * in the carrier board device tree files.
+ */
+ reg_force_sleep_moci: regulator-force-sleep-moci {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "CTRL_SLEEP_MOCI#";
+ };
+
reg_usb_otg1_vbus: regulator-usb-otg1 {
compatible = "regulator-fixed";
enable-active-high;
@@ -333,16 +349,6 @@ &gpio5 {
"SODIMM_212",
"SODIMM_151",
"SODIMM_153";
-
- ctrl-sleep-moci-hog {
- gpio-hog;
- /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
- gpios = <1 GPIO_ACTIVE_HIGH>;
- line-name = "CTRL_SLEEP_MOCI#";
- output-high;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
- };
};
/* On-module I2C */
--
2.40.1
^ permalink raw reply related
* [PATCH v1 2/4] arm64: dts: freescale: imx8mp-verdin-dahlia: support sleep-moci
From: Stefan Eichenberger @ 2024-04-05 16:07 UTC (permalink / raw)
To: robh, krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, francesco.dolcini
Cc: devicetree, imx, linux-arm-kernel, linux-kernel,
Stefan Eichenberger
In-Reply-To: <20240405160720.5977-1-eichest@gmail.com>
From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
Previously, we had the sleep-moci pin set to always on. However, the
Dahlia carrier board supports disabling the sleep-moci when the system
is suspended to power down peripherals that support it. This reduces
overall power consumption. This commit adds support for this feature by
disabling the reg_force_sleep_moci regulator and adding two new
regulators for the USB hub and PCIe that can be turned off when the
system is suspended.
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
---
.../dts/freescale/imx8mp-verdin-dahlia.dtsi | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
index e68e0e6f21e9..abad1887040a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
@@ -32,6 +32,25 @@ simple-audio-card,cpu {
sound-dai = <&sai1>;
};
};
+
+ reg_usb_hub: regulator-usb-hub {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ regulator-name = "HUB_PWR_EN";
+ };
+
+ reg_pcie: regulator-pcie {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ regulator-name = "PCIE_1_PWR_EN";
+ startup-delay-us = <100000>;
+ };
};
&backlight {
@@ -117,6 +136,7 @@ wm8904_1a: audio-codec@1a {
/* Verdin PCIE_1 */
&pcie {
+ vpcie-supply = <®_pcie>;
status = "okay";
};
@@ -143,6 +163,11 @@ ®_usdhc2_vmmc {
vin-supply = <®_3p3v>;
};
+/* We support turning off sleep moci on Dahlia */
+®_force_sleep_moci {
+ status = "disabled";
+};
+
/* Verdin I2S_1 */
&sai1 {
assigned-clocks = <&clk IMX8MP_CLK_SAI1>;
@@ -186,6 +211,25 @@ &usb3_phy1 {
status = "okay";
};
+&usb_dwc3_1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb_hub_3_0: usb-hub@1 {
+ compatible = "usb424,5744";
+ reg = <1>;
+ peer-hub = <&usb_hub_2_0>;
+ vdd-supply = <®_usb_hub>;
+ };
+
+ usb_hub_2_0: usb-hub@2 {
+ compatible = "usb424,2744";
+ reg = <2>;
+ peer-hub = <&usb_hub_3_0>;
+ vdd-supply = <®_usb_hub>;
+ };
+};
+
/* Verdin SD_1 */
&usdhc2 {
status = "okay";
--
2.40.1
^ permalink raw reply related
* [PATCH v1 1/4] arm64: dts: freescale: imx8mp-verdin: replace sleep-moci hog with regulator
From: Stefan Eichenberger @ 2024-04-05 16:07 UTC (permalink / raw)
To: robh, krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, francesco.dolcini
Cc: devicetree, imx, linux-arm-kernel, linux-kernel,
Stefan Eichenberger
In-Reply-To: <20240405160720.5977-1-eichest@gmail.com>
From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
The Verdin family has a signal called sleep-moci which can be used to
turn off peripherals on the carrier board when the SoM goes into
suspend. So far we have hogged this signal, which means the peripherals
are always on and it is not possible to add peripherals that depend on
the sleep-moci to be on. With this change, we replace the hog with a
regulator so that peripherals can add their own regulators that use the
same gpio. Carrier boards that allow peripherals to be powered off in
suspend can disable this regulator and implement their own regulator to
control the sleep-moci.
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
---
.../dts/freescale/imx8mp-verdin-dahlia.dtsi | 5 ++++
.../boot/dts/freescale/imx8mp-verdin-dev.dtsi | 5 ++++
.../dts/freescale/imx8mp-verdin-yavia.dtsi | 5 ++++
.../boot/dts/freescale/imx8mp-verdin.dtsi | 26 ++++++++++++-------
4 files changed, 31 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
index 7e9e4b13b5c5..e68e0e6f21e9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
@@ -70,6 +70,11 @@ &flexspi {
status = "okay";
};
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+};
+
/* Current measurement into module VCC */
&hwmon {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi
index a509b2b7fa85..1a2520d4d6cf 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi
@@ -93,6 +93,11 @@ &flexspi {
status = "okay";
};
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+};
+
&gpio_expander_21 {
status = "okay";
vcc-supply = <®_1p8v>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi
index db1722f0d80e..27160024d5b5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi
@@ -100,6 +100,11 @@ &flexcan1 {
status = "okay";
};
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+};
+
&hwmon_temp {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
index faa17cbbe2fd..e523762947aa 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
@@ -116,6 +116,22 @@ reg_module_eth1phy: regulator-module-eth1phy {
vin-supply = <®_vdd_3v3>;
};
+ /*
+ * By default we enable CTRL_SLEEP_MOCI#, this is required to have
+ * peripherals on the carrier board powered.
+ * If more granularity or power saving is required this can be disabled
+ * in the carrier board device tree files.
+ */
+ reg_force_sleep_moci: regulator-force-sleep-moci {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "CTRL_SLEEP_MOCI#";
+ };
+
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
enable-active-high;
@@ -439,16 +455,6 @@ &gpio4 {
"SODIMM_256",
"SODIMM_48",
"SODIMM_44";
-
- ctrl-sleep-moci-hog {
- gpio-hog;
- /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
- gpios = <29 GPIO_ACTIVE_HIGH>;
- line-name = "CTRL_SLEEP_MOCI#";
- output-high;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
- };
};
/* On-module I2C */
--
2.40.1
^ permalink raw reply related
* [PATCH v1 0/4] arm64: dts: freescale: verdin-imx8mm/imx8mp: add sleep-moci support
From: Stefan Eichenberger @ 2024-04-05 16:07 UTC (permalink / raw)
To: robh, krzysztof.kozlowski+dt, conor+dt, shawnguo, s.hauer, kernel,
festevam, francesco.dolcini
Cc: devicetree, imx, linux-arm-kernel, linux-kernel,
Stefan Eichenberger
From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
This patch series adds support for sleep-moci to the Verdin iMX8MM and
iMX8MP in combination with the Dahlia carrier board. sleep-moci is a
GPIO that allows the system on module to turn off regulators that are
not needed in suspend mode on the carrier board.
Stefan Eichenberger (4):
arm64: dts: freescale: imx8mp-verdin: replace sleep-moci hog with
regulator
arm64: dts: freescale: imx8mp-verdin-dahlia: support sleep-moci
arm64: dts: freescale: imx8mm-verdin: replace sleep-moci hog with
regulator
arm64: dts: freescale: imx8mm-verdin-dahlia: support sleep-moci
.../dts/freescale/imx8mm-verdin-dahlia.dtsi | 39 +++++++++++++++
.../boot/dts/freescale/imx8mm-verdin-dev.dtsi | 5 ++
.../dts/freescale/imx8mm-verdin-yavia.dtsi | 5 ++
.../boot/dts/freescale/imx8mm-verdin.dtsi | 26 ++++++----
.../dts/freescale/imx8mp-verdin-dahlia.dtsi | 50 +++++++++++++++++++
.../boot/dts/freescale/imx8mp-verdin-dev.dtsi | 5 ++
.../dts/freescale/imx8mp-verdin-yavia.dtsi | 5 ++
.../boot/dts/freescale/imx8mp-verdin.dtsi | 26 ++++++----
8 files changed, 141 insertions(+), 20 deletions(-)
--
2.40.1
^ permalink raw reply
* Re: [PATCH RFC 02/11] dt-bindings: riscv: Add Sdtrig optional CSRs existence on DT
From: Andrew Jones @ 2024-04-05 15:59 UTC (permalink / raw)
To: Conor Dooley
Cc: Max Hsu, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Rafael J. Wysocki,
Pavel Machek, Anup Patel, Atish Patra, Paolo Bonzini, Shuah Khan,
Palmer Dabbelt, linux-riscv, devicetree, linux-kernel, linux-pm,
kvm, kvm-riscv, linux-kselftest
In-Reply-To: <20240329-affidavit-anatomist-1118a12c3e60@wendy>
On Fri, Mar 29, 2024 at 10:31:10AM +0000, Conor Dooley wrote:
> On Fri, Mar 29, 2024 at 05:26:18PM +0800, Max Hsu wrote:
> > The mcontext/hcontext/scontext CSRs are optional in the Sdtrig extension,
> > to prevent RW operations to the missing CSRs, which will cause
> > illegal instructions.
> >
> > As a solution, we have proposed the dt format for these CSRs.
>
> As I mentioned in your other patch, I amn't sure what the actual value
> is in being told about "sdtrig" itself if so many of the CSRs are
> optional. I think we should define pseudo extensions that represent
> usable subsets that are allowed by riscv,isa-extensions, such as
> those you describe here: sdtrig + mcontext, sdtrig + scontext and
> sdtrig + hcontext. Probably also for strig + mscontext. What
> additional value does having a debug child node give us that makes
> it worth having over something like the above?
Yeah, Sdtrig, which doesn't tell you what you get, isn't nice at all.
I wonder if we can start with requiring Sdtrig to be accompanied by
Ssstrict in order to enable the context CSRs, i.e.
Sdtrig - support without optional CSRs
Sdtrig+Ssstrict - probe for optional CSRs, support what's found
If there are platforms with Sdtrig and optional CSRs, but not Ssstrict,
then maybe the optional CSRs can be detected in some vendor-specific way,
where the decision as to whether or not that vendor-specific way is
acceptable is handled case-by-case.
Thanks,
drew
>
> Thanks,
> Conor.
>
> >
> > Signed-off-by: Max Hsu <max.hsu@sifive.com>
> > ---
> > Documentation/devicetree/bindings/riscv/cpus.yaml | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index d87dd50f1a4b..c713a48c5025 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -137,6 +137,24 @@ properties:
> > DMIPS/MHz, relative to highest capacity-dmips-mhz
> > in the system.
> >
> > + debug:
> > + type: object
> > + properties:
> > + compatible:
> > + const: riscv,debug-v1.0.0
> > + trigger-module:
> > + type: object
> > + description: |
> > + An indication set of optional CSR existence from
> > + riscv-debug-spec Sdtrig extension
> > + properties:
> > + mcontext-present:
> > + type: boolean
> > + hcontext-present:
> > + type: boolean
> > + scontext-present:
> > + type: boolean
> > +
> > anyOf:
> > - required:
> > - riscv,isa
> >
> > --
> > 2.43.2
> >
> --
> kvm-riscv mailing list
> kvm-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kvm-riscv
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: omap-mcpdm: Convert to DT schema
From: Krzysztof Kozlowski @ 2024-04-05 15:57 UTC (permalink / raw)
To: Mithil
Cc: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, alsa-devel, devicetree, linux-kernel
In-Reply-To: <CAGzNGRnuG_gLUrH1N57WvpKbpiNtFrcsG6nJcacQNJB_yMYNrA@mail.gmail.com>
On 05/04/2024 16:48, Mithil wrote:
> So sorry about the 2nd patch being sent as a new mail, here is a new
> patch with the changes as suggested
>
>> Please use subject prefixes matching the subsystem
> Changed the patch name to match the folder history.
Nothing improved. What the history tells you?
>
>> Is it your full name?
> Fixed it, my apologies.
>
>> Filename like compatible.
> Fixed.
Still not, compatible is omap4.
>
>> Please open existing bindings and look how it is done there.
> Changed it, is it fine now?
You mean v2? I have no clue to what you are responding here, but no, v2
did not improve much.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 6/6] dts: qcom: sa8775p-ride: remove tx-sched-sp property
From: Krzysztof Kozlowski @ 2024-04-05 15:52 UTC (permalink / raw)
To: Flavio Suligoi, Alexandre Torgue, Jose Abreu, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Maxime Coquelin,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Bjorn Andersson, Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel
In-Reply-To: <20240405152800.638461-7-f.suligoi@asem.it>
On 05/04/2024 17:28, Flavio Suligoi wrote:
> The property "tx-sched-sp" no longer exists, as it was removed from the
> file:
>
> drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
>
> by the commit:
>
> commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
> branch")
>
> Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
Fixes in commit msg needed and patch prefix got mangled: missing arm64.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v6 10/11] riscv: dts: add initial canmv-k230 and k230-evb dts
From: Conor Dooley @ 2024-04-05 15:52 UTC (permalink / raw)
To: Yangyu Chen
Cc: Icenowy Zheng, linux-riscv, Damien Le Moal, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Guo Ren, Michael Turquette, Stephen Boyd, Linus Walleij,
Philipp Zabel, linux-gpio, linux-clk, devicetree, linux-kernel
In-Reply-To: <tencent_1C21558D2A7C7B8251DA4E8E08B82E313C08@qq.com>
[-- Attachment #1: Type: text/plain, Size: 1414 bytes --]
On Mon, Mar 25, 2024 at 11:10:49AM +0800, Yangyu Chen wrote:
> > On Mar 25, 2024, at 00:23, Icenowy Zheng <uwu@icenowy.me> wrote:
> > 在 2024-03-23星期六的 20:12 +0800，Yangyu Chen写道：
> >> - Svpbmt and T-Head MAEE both supported
> >>
> >> T-Head C908 does support both Svpbmt and T-Head MAEE for page-based
> >> memory
> >> attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt
> >> is used
> >> here for mainline kernel support for K230. If the kernel wants to use
> >> Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS
> >> before
> >> entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0
> >> on
> >> T-Head MAEE is NonCachable Memory. Once the kernel switches from bare
> >> metal
> >> to Sv39, It will lose dirty cache line modifications that haven't
> >> been
> >> written back to the memory.
> >
> > As MXSTATUS has a S-mode read-only mirror known as SXSTATUS, maybe the
> > kernel should detect SXSTATUS to decide whether to use Svpbmt or
> > Xtheadpbmt (BTW Svnapot conflicts with Xtheadpbmt too).
> >
>
> Thanks for this hint. I may need to change some code in the T-Head PBMT probe.
For now, I'd rather we just focused on supporting the standard
extensions on this SoC in mainline. I've applied the patches re-doing
the Kconfig options just now, feel free to resend these patches
whenever.
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH 5/6] arm64: dts: qcom: sa8540p-ride: remove tx-sched-sp property
From: Krzysztof Kozlowski @ 2024-04-05 15:51 UTC (permalink / raw)
To: Flavio Suligoi, Alexandre Torgue, Jose Abreu, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Maxime Coquelin,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Bjorn Andersson, Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel
In-Reply-To: <20240405152800.638461-6-f.suligoi@asem.it>
On 05/04/2024 17:27, Flavio Suligoi wrote:
> The property "tx-sched-sp" no longer exists, as it was removed from the
> file:
>
> drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
>
> by the commit:
>
> commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
> branch")
Same problem with commit. BTW, your commit msg does not say what happens
if this property is removed. Instead it could be "Strict priority is by
default in Linux driver and tx-sched-sp was removed in commit sha ("foo
bar")".
With fixed in commit msg.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 1/6] dt-bindings: net: snps,dwmac: remove tx-sched-sp property
From: Krzysztof Kozlowski @ 2024-04-05 15:50 UTC (permalink / raw)
To: Flavio Suligoi, Alexandre Torgue, Jose Abreu, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Maxime Coquelin,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Bjorn Andersson, Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel
In-Reply-To: <20240405152800.638461-2-f.suligoi@asem.it>
On 05/04/2024 17:27, Flavio Suligoi wrote:
> The property "tx-sched-sp" no longer exists, as it was removed from the
> file:
>
> drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
>
> by the commit:
>
> commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
> branch")
>
> Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
> ---
> .../devicetree/bindings/net/snps,dwmac.yaml | 14 --------------
> 1 file changed, 14 deletions(-)
One more thought though:
1. Missing net-next patch annotation,
2. Please split DTS from net. DTS goes via separate trees.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 1/6] dt-bindings: net: snps,dwmac: remove tx-sched-sp property
From: Krzysztof Kozlowski @ 2024-04-05 15:49 UTC (permalink / raw)
To: Flavio Suligoi, Alexandre Torgue, Jose Abreu, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Maxime Coquelin,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Bjorn Andersson, Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel
In-Reply-To: <20240405152800.638461-2-f.suligoi@asem.it>
On 05/04/2024 17:27, Flavio Suligoi wrote:
> The property "tx-sched-sp" no longer exists, as it was removed from the
> file:
>
> drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
>
> by the commit:
Keep syntax as asked by submitting patches, so "by the commit sha ("foo
bar").
>
> commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
> branch")
>
> Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
> ---
> .../devicetree/bindings/net/snps,dwmac.yaml | 14 --------------
> 1 file changed, 14 deletions(-)
This means by default we have tx-sched-sp... I guess it is fine,
assuming there are no other users (projects) of this binding property.
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH RFT 10/10] arm64: dts: microchip: sparx5_pcb135: drop duplicated NOR flash
From: Krzysztof Kozlowski @ 2024-04-05 15:46 UTC (permalink / raw)
To: Steen Hegelund, Conor Dooley, Nicolas Ferre, Claudiu Beznea,
Rob Herring, Krzysztof Kozlowski, Lars Povlsen, Daniel Machon,
UNGLinuxDriver, David S. Miller, Bjarni Jonasson,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <66872c085710223d5bf43cd601cfbc3e54425bbc.camel@microchip.com>
On 05/04/2024 14:11, Steen Hegelund wrote:
>>
>> -&spi0 {
>> - status = "okay";
>> - spi@0 {
>> - compatible = "spi-mux";
>> - mux-controls = <&mux>;
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - reg = <0>; /* CS0 */
>> - flash@9 {
>> - compatible = "jedec,spi-nor";
>> - spi-max-frequency = <8000000>;
>> - reg = <0x9>; /* SPI */
>> - };
>> - };
>> -};
>> -
>
> I also tested this, and no surprise: same comment as for the pcb134 patch...
Thanks, I will send v2.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH RFT 09/10] arm64: dts: microchip: sparx5_pcb134: drop duplicated NOR flash
From: Krzysztof Kozlowski @ 2024-04-05 15:45 UTC (permalink / raw)
To: Steen Hegelund, Conor Dooley, Nicolas Ferre, Claudiu Beznea,
Rob Herring, Krzysztof Kozlowski, Lars Povlsen, Daniel Machon,
UNGLinuxDriver, David S. Miller, Bjarni Jonasson,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <67f29fa86207a68b148b826b71b1349d3552453d.camel@microchip.com>
On 05/04/2024 14:10, Steen Hegelund wrote:
> Hi Krzysztof,
>
> On Mon, 2024-04-01 at 17:37 +0200, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Since beginning the DTS extended the SPI0 in two places adding two SPI
>> muxes, each with same SPI NOR flash. Both used exactly the same
>> chip-selects, so this was clearly buggy code. Without checking in
>> datasheet, assume device has only one SPI NOR flash, so code was
>> duplicated.
>>
>> Fixes dtc W=1 warnings:
>>
>> sparx5_pcb134_board.dtsi:277.10-281.4: Warning (unique_unit_address_if_enabled):
>> /axi@600000000/spi@600104000/flash@0: duplicate unit-address (also used in node
>> /axi@600000000/spi@600104000/spi@0)
>>
>> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
>>
>> ---
>>
>> Not tested on hardware
>> ---
>> .../boot/dts/microchip/sparx5_pcb134_board.dtsi | 16 ----------------
>> 1 file changed, 16 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
>> b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
>> index f165a409bc1d..dc7b59dfcb40 100644
>> --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
>> +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
>> @@ -281,22 +281,6 @@ flash@0 {
>> };
>> };
>>
>> -&spi0 {
>> - status = "okay";
>> - spi@0 {
>> - compatible = "spi-mux";
>> - mux-controls = <&mux>;
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - reg = <0>; /* CS0 */
>> - flash@9 {
>> - compatible = "jedec,spi-nor";
>> - spi-max-frequency = <8000000>;
>> - reg = <0x9>; /* SPI */
>> - };
>> - };
>> -};
>> -
>
> When testing this on actual HW the SPI NOR is no longer accessible.
> The reason is that it sits behind a SPI-MUX and that needs to be present in the Device Tree.
>
> So if you do the "reverse" clean-up it works fine: Remove the simple spi0 node and keep the one that
> has the spi-mux reference.
Aaaa, so we need to do it that way. Thanks for testing! I'll send v2.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: usb: Document the Microchip USB2514 hub
From: Krzysztof Kozlowski @ 2024-04-05 15:45 UTC (permalink / raw)
To: Fabio Estevam, gregkh
Cc: robh, krzk+dt, conor+dt, linux-usb, devicetree, Fabio Estevam
In-Reply-To: <20240405120147.880933-1-festevam@gmail.com>
On 05/04/2024 14:01, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@denx.de>
>
> Document the Microchip USB2412, USB2417, and USB2514 USB hubs.
>
> The existing usb251xb.yaml describes Microchip USB251x hubs that are
> connected under I2C bus. Here, the hub is under the USB bus and use
> the on-board-hub interface instead.
>
> Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply
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