* Re: [PATCH] dt-bindings: timer: renesas,cmt: Add R-Car V4M support
From: Rob Herring @ 2024-04-09 14:11 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Daniel Lezcano, Thomas Gleixner, Krzysztof Kozlowski,
Conor Dooley, Laurent Pinchart, devicetree, linux-renesas-soc,
linux-kernel
In-Reply-To: <3e8a7a93261d8ad264dec2fa2784fe1bbfc4a23c.1712068536.git.geert+renesas@glider.be>
On Tue, Apr 02, 2024 at 04:36:05PM +0200, Geert Uytterhoeven wrote:
> Document support for the Compare Match Timer Type0 (CMT0) and Type1
> (CMT1) in the Renesas R-Car V4M (R8A779H0) SoC.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Documentation/devicetree/bindings/timer/renesas,cmt.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Daniel, please apply this. The timer bindings seem to keep getting
missed.
>
> diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.yaml b/Documentation/devicetree/bindings/timer/renesas,cmt.yaml
> index a0be1755ea28b996..5e09c04da30e47d5 100644
> --- a/Documentation/devicetree/bindings/timer/renesas,cmt.yaml
> +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.yaml
> @@ -103,6 +103,7 @@ properties:
> - renesas,r8a779a0-cmt0 # 32-bit CMT0 on R-Car V3U
> - renesas,r8a779f0-cmt0 # 32-bit CMT0 on R-Car S4-8
> - renesas,r8a779g0-cmt0 # 32-bit CMT0 on R-Car V4H
> + - renesas,r8a779h0-cmt0 # 32-bit CMT0 on R-Car V4M
> - const: renesas,rcar-gen4-cmt0 # 32-bit CMT0 on R-Car Gen4
>
> - items:
> @@ -110,6 +111,7 @@ properties:
> - renesas,r8a779a0-cmt1 # 48-bit CMT on R-Car V3U
> - renesas,r8a779f0-cmt1 # 48-bit CMT on R-Car S4-8
> - renesas,r8a779g0-cmt1 # 48-bit CMT on R-Car V4H
> + - renesas,r8a779h0-cmt1 # 48-bit CMT on R-Car V4M
> - const: renesas,rcar-gen4-cmt1 # 48-bit CMT on R-Car Gen4
>
> reg:
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH v3 18/25] dt-bindings: media: imx258: Add alternate compatible strings
From: Rob Herring @ 2024-04-09 14:12 UTC (permalink / raw)
To: git
Cc: mchehab, devicetree, linux-media, shawnguo, jacopo.mondi,
phone-devel, linux-arm-kernel, krzysztof.kozlowski+dt, festevam,
sakari.ailus, conor+dt, imx, pavel, dave.stevenson, s.hauer,
linux-kernel, kernel
In-Reply-To: <20240403150355.189229-19-git@luigi311.com>
On Wed, 03 Apr 2024 09:03:47 -0600, git@luigi311.com wrote:
> From: Dave Stevenson <dave.stevenson@raspberrypi.com>
>
> There are a number of variants of the imx258 modules that can not
> be differentiated at runtime, so add compatible strings for the
> PDAF variant.
>
> Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
> Signed-off-by: Luis Garcia <git@luigi311.com>
> ---
> .../devicetree/bindings/media/i2c/sony,imx258.yaml | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 1/5] arm64: dts: mediatek: mt8395-nio-12l: Fix MT6360 regulator nodes names
From: AngeloGioacchino Del Regno @ 2024-04-09 14:14 UTC (permalink / raw)
To: linux-mediatek
Cc: robh, krzk+dt, conor+dt, matthias.bgg, devicetree, linux-kernel,
linux-arm-kernel, kernel
In-Reply-To: <20240409114211.310462-2-angelogioacchino.delregno@collabora.com>
Il 09/04/24 13:42, AngeloGioacchino Del Regno ha scritto:
> The regulators' node names for mt6360-regulator are supposed to be
> uppercase. Also, drop "-regulator" from the usb-otg-vbus node name
> to make all vregs to probe correctly.
>
> The alternative would've been to use regulator-compatible, but that's
> a deprecated property.
> Now all regulators are probing fine.
>
> Fixes: 96564b1e2ea4 ("arm64: dts: mediatek: Introduce the MT8395 Radxa NIO 12L board")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
> index e5d9b671a405..18182cf073fb 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
> @@ -216,7 +216,7 @@ charger {
> compatible = "mediatek,mt6360-chg";
> richtek,vinovp-microvolt = <14500000>;
>
> - otg_vbus_regulator: usb-otg-vbus-regulator {
> + otg_vbus_regulator: usb-otg-vbus {
Reviewing and NACK'ing my own patch, I just noticed that everything apart the
usb-otg-vbus renaming is wrong.
The MT6360 regulator node names should not be capitalized as the bindings are
correct in this regard, and there already is one user (genio-1200-evk) apart
from NIO-12L declaring the wrong ones - so, the driver must be fixed, not the
other way around.
This patch will be cleaned up in v2.
Cheers
^ permalink raw reply
* Re: [PATCH 1/5] dt-bindings: riscv: add Zimop ISA extension description
From: Conor Dooley @ 2024-04-09 14:15 UTC (permalink / raw)
To: Clément Léger
Cc: Jonathan Corbet, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Rob Herring, Krzysztof Kozlowski, Anup Patel, Shuah Khan,
Atish Patra, linux-doc, linux-riscv, linux-kernel, devicetree,
kvm, kvm-riscv, linux-kselftest
In-Reply-To: <20240404103254.1752834-2-cleger@rivosinc.com>
[-- Attachment #1: Type: text/plain, Size: 313 bytes --]
On Thu, Apr 04, 2024 at 12:32:47PM +0200, Clément Léger wrote:
> Add description for the Zimop (May-Be-Operations) ISA extension which
> was ratified in commit 58220614a5f of the riscv-isa-manual.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: mtd: amlogic,meson-nand: support fields for boot ROM code
From: Arseniy Krasnov @ 2024-04-09 14:10 UTC (permalink / raw)
To: Rob Herring
Cc: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Krzysztof Kozlowski, Conor Dooley, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl, linux-mtd, devicetree,
linux-arm-kernel, linux-amlogic, linux-kernel, oxffffaa, kernel
In-Reply-To: <20240409134718.GA1050037-robh@kernel.org>
On 09.04.2024 16:47, Rob Herring wrote:
> On Mon, Apr 08, 2024 at 11:59:30AM +0300, Arseniy Krasnov wrote:
>> Boot ROM code on Meson requires that some pages on NAND must be written
>> in special mode: "short" ECC mode where each block is 384 bytes and
>> scrambling mode is on. Such pages located with the specified interval
>> within specified offset. Both interval and offset are located in the
>> device tree and used by driver if 'nand-is-boot-medium' is set for
>> NAND chip.
>>
>> Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com>
>> ---
>> .../bindings/mtd/amlogic,meson-nand.yaml | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml
>> index 57b6957c8415..80ba5003ca70 100644
>> --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml
>> +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml
>> @@ -64,11 +64,25 @@ patternProperties:
>> items:
>> maximum: 0
>>
>> + amlogic,boot-page-last:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + description:
>> + The NFC driver needs this information to select ECC
>> + algorithms supported by the boot ROM.
>> +
>> + amlogic,boot-page-step:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + description:
>> + The NFC driver needs this information to select ECC
>> + algorithms supported by the boot ROM (in pages).
>> +
>> unevaluatedProperties: false
>>
>> dependencies:
>> nand-ecc-strength: [nand-ecc-step-size]
>> nand-ecc-step-size: [nand-ecc-strength]
>> + amlogic,boot-page-last: [nand-is-boot-medium, amlogic,boot-page-step]
>> + amlogic,boot-page-step: [nand-is-boot-medium, amlogic,boot-page-last]
>
> You need quotes if using the inline syntax.
IIUC it must look like this:
amlogic,boot-page-last: [nand-is-boot-medium, "amlogic,boot-page-step"]
etc.
>
> Rob
^ permalink raw reply
* [PATCH v2 0/5] arm64: dts: qcom: add USB-C orientation GPIOs
From: Dmitry Baryshkov @ 2024-04-09 14:28 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Dmitry Baryshkov
Populate orientation GPIOs for some of the PMIC-GLINK-based devices.
This leaves only FairPhone5, RB3Gen2, SC8180X Primus and SC8280XP CRD
without the orientation GPIOs declared.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Changes in v2:
- Relax schema restriction for orientation-gpios property (Luca Weiss)
- Link to v1: https://lore.kernel.org/r/20240408-hdk-orientation-gpios-v1-0-8064ba43e52a@linaro.org
---
Dmitry Baryshkov (5):
dt-bindings: soc: qcom: pmic-glink: allow orientation-gpios
arm64: dts: qcom: sm8350-hdk: add USB-C orientation GPIO
arm64: dts: qcom: sm8450-hdk: add USB-C orientation GPIO
arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: add USB-C orientation GPIOs
arm64: dts: qcom: sc8180x-lenovo-flex-5g: add USB-C orientation GPIOs
.../devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 14 --------------
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 ++
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 ++
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 +
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 +
5 files changed, 6 insertions(+), 14 deletions(-)
---
base-commit: 8568bb2ccc278f344e6ac44af6ed010a90aa88dc
change-id: 20240408-hdk-orientation-gpios-141bc7fd247d
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
^ permalink raw reply
* [PATCH v2 1/5] dt-bindings: soc: qcom: pmic-glink: allow orientation-gpios
From: Dmitry Baryshkov @ 2024-04-09 14:28 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Dmitry Baryshkov
In-Reply-To: <20240409-hdk-orientation-gpios-v2-0-658efd993987@linaro.org>
The orientation GPIOs are not limited to sm8450/sm8550/x1e8000
platforms. Allow corresponding property to be used on all Qualcom
platforms.
Fixes: 65682407f8f4 ("dt-bindings: soc: qcom: qcom,pmic-glink: add a gpio used to determine the Type-C port plug orientation")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 14 --------------
1 file changed, 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml
index 4310bae6c58e..4512390f90f0 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml
@@ -58,20 +58,6 @@ patternProperties:
required:
- compatible
-allOf:
- - if:
- not:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sm8450-pmic-glink
- - qcom,sm8550-pmic-glink
- - qcom,x1e80100-pmic-glink
- then:
- properties:
- orientation-gpios: false
-
additionalProperties: false
examples:
--
2.39.2
^ permalink raw reply related
* [PATCH v2 2/5] arm64: dts: qcom: sm8350-hdk: add USB-C orientation GPIO
From: Dmitry Baryshkov @ 2024-04-09 14:28 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Dmitry Baryshkov
In-Reply-To: <20240409-hdk-orientation-gpios-v2-0-658efd993987@linaro.org>
Define the USB-C orientation GPIO so that the USB-C port orientation is
known without having to resort to the altmode notifications.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index b43d264ed42b..4c25ab2f5670 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -42,6 +42,7 @@ pmic-glink {
compatible = "qcom,sm8350-pmic-glink", "qcom,pmic-glink";
#address-cells = <1>;
#size-cells = <0>;
+ orientation-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
connector@0 {
compatible = "usb-c-connector";
--
2.39.2
^ permalink raw reply related
* [PATCH v2 3/5] arm64: dts: qcom: sm8450-hdk: add USB-C orientation GPIO
From: Dmitry Baryshkov @ 2024-04-09 14:28 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Dmitry Baryshkov
In-Reply-To: <20240409-hdk-orientation-gpios-v2-0-658efd993987@linaro.org>
Define the USB-C orientation GPIO so that the USB-C port orientation is
known without having to resort to the altmode notifications.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
index 0786cff07b89..3be46b56c723 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
@@ -95,6 +95,7 @@ pmic-glink {
compatible = "qcom,sm8450-pmic-glink", "qcom,pmic-glink";
#address-cells = <1>;
#size-cells = <0>;
+ orientation-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>;
connector@0 {
compatible = "usb-c-connector";
--
2.39.2
^ permalink raw reply related
* [PATCH v2 4/5] arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: add USB-C orientation GPIOs
From: Dmitry Baryshkov @ 2024-04-09 14:28 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Dmitry Baryshkov
In-Reply-To: <20240409-hdk-orientation-gpios-v2-0-658efd993987@linaro.org>
Define the USB-C orientation GPIOs so that the USB-C ports orientation
is known without having to resort to the altmode notifications.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 15ae94c1602d..2806aa8ec497 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -100,6 +100,8 @@ pmic-glink {
#address-cells = <1>;
#size-cells = <0>;
+ orientation-gpios = <&tlmm 166 GPIO_ACTIVE_HIGH>,
+ <&tlmm 49 GPIO_ACTIVE_HIGH>;
connector@0 {
compatible = "usb-c-connector";
--
2.39.2
^ permalink raw reply related
* [PATCH v2 5/5] arm64: dts: qcom: sc8180x-lenovo-flex-5g: add USB-C orientation GPIOs
From: Dmitry Baryshkov @ 2024-04-09 14:28 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Dmitry Baryshkov
In-Reply-To: <20240409-hdk-orientation-gpios-v2-0-658efd993987@linaro.org>
Define the USB-C orientation GPIOs so that the USB-C ports orientation
is known without having to resort to the altmode notifications.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
index 6f2e1c732ed3..6af99116c715 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
@@ -51,6 +51,8 @@ pmic-glink {
#address-cells = <1>;
#size-cells = <0>;
+ orientation-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>,
+ <&tlmm 58 GPIO_ACTIVE_HIGH>;
connector@0 {
compatible = "usb-c-connector";
--
2.39.2
^ permalink raw reply related
* Re: [PATCH v1] arm64: dts: imx8mm: fix missing pgc_vpu_* power domain parent
From: Lucas Stach @ 2024-04-09 14:36 UTC (permalink / raw)
To: Vitor Soares, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Vitor Soares, devicetree, imx, linux-arm-kernel, linux-kernel,
stable
In-Reply-To: <e1552a3008a30ef7ed9097b4b80cda23ccb9e840.camel@gmail.com>
Am Dienstag, dem 09.04.2024 um 14:22 +0100 schrieb Vitor Soares:
> Hi Lucas,
>
> Thanks for your feedback.
>
> On Tue, 2024-04-09 at 11:13 +0200, Lucas Stach wrote:
> > Hi Vitor,
> >
> > Am Dienstag, dem 09.04.2024 um 09:58 +0100 schrieb Vitor Soares:
> > > From: Vitor Soares <vitor.soares@toradex.com>
> > >
> > > The pgc_vpu_* nodes miss the reference to the power domain parent,
> > > leading the system to hang during the resume.
> > >
> > This change is not correct. The vpumix domain is controlled through
> > the
> > imx8mm-vpu-blk-ctrl and must not be directly triggered by the child
> > domains in order to guarantee proper power sequencing.
> >
> > If the sequencing is incorrect for resume, it needs to be fixed in
> > the
> > blk-ctrl driver. I'll happily assist if you have any questions about
> > this intricate mix between GPC and blk-ctrl hardware/drivers.
>
> I'm new into the topic, so I tried to follow same approach as in imx8mp
> DT.
>
That's a good hint, the 8MP VPU GPC node additions missed my radar. The
direct dependency there between the GPC domains is equally wrong.
> I also checked the imx8mq DT and it only have one domain for the
> VPU in the GPC. It seem blk-ctrl also dependes on pgc_vpu_* to work
> properly.
>
> The blk-ctrl driver hangs on imx8m_blk_ctrl_power_on() when access the
> ip registers for the soft reset. I tried to power-up the before the
> soft reset, but it didn't work.
>
The runtime_pm_get_sync() at the start of that function should ensure
that bus GPC domain aka vpumix is powered up. Can you check if that is
happening?
Regards,
Lucas
> Do you have an idea how we can address this within blk-ctrl?
>
> Best regards,
> Vitor
>
> >
> > Regards,
> > Lucas
> >
> > > As these PU domains are nested inside the vpumix domain, let's
> > > reference
> > > it accordingly. After this change, the suspend/resume is working.
> > >
> > > Cc: Lucas Stach <l.stach@pengutronix.de>
> > > Cc: <stable@vger.kernel.org>
> > > Closes:
> > > https://lore.kernel.org/all/fccbb040330a706a4f7b34875db1d896a0bf81c8.camel@gmail.com/
> > > Fixes: d39d4bb15310 ("arm64: dts: imx8mm: add GPC node")
> > > Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
> > > ---
> > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > > index 8a1b42b94dce..97d0c6d23ad8 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > > @@ -739,16 +739,19 @@ pgc_vpumix: power-domain@6 {
> > > pgc_vpu_g1: power-domain@7
> > > {
> > > #power-domain-cells
> > > = <0>;
> > > reg =
> > > <IMX8MM_POWER_DOMAIN_VPUG1>;
> > > + power-domains =
> > > <&pgc_vpumix>;
> > > };
> > >
> > > pgc_vpu_g2: power-domain@8
> > > {
> > > #power-domain-cells
> > > = <0>;
> > > reg =
> > > <IMX8MM_POWER_DOMAIN_VPUG2>;
> > > + power-domains =
> > > <&pgc_vpumix>;
> > > };
> > >
> > > pgc_vpu_h1: power-domain@9
> > > {
> > > #power-domain-cells
> > > = <0>;
> > > reg =
> > > <IMX8MM_POWER_DOMAIN_VPUH1>;
> > > + power-domains =
> > > <&pgc_vpumix>;
> > > };
> > >
> > > pgc_dispmix:
> > > power-domain@10 {
> >
>
^ permalink raw reply
* Re: [PATCH v2 00/13] ASoC: ti: davinci-i2s: Add features to McBSP driver
From: Péter Ujfalusi @ 2024-04-09 14:39 UTC (permalink / raw)
To: Bastien Curutchet, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai
Cc: linux-sound, devicetree, linux-kernel, alsa-devel,
Thomas Petazzoni, herve.codina, christophercordahi
In-Reply-To: <20240402071213.11671-1-bastien.curutchet@bootlin.com>
Hi Bastien,
On 02/04/2024 10:12, Bastien Curutchet wrote:
> This series aims to add some features to McBSP driver.
>
> Convert bindings from .txt to .yaml.
> Add possibility to use an external clock as sample rate generator's
> input.
> Add handling of new formats (TDM, S24_LE, BP_FC).
> Enable the detection of unexpected frame pulses.
> Set the clock free-running mode according to SND_SOC_DAIFMT_[GATED/CONT]
> configuration in DAI format.
> Add ti,T1-framing[tx/rx] properties in DT. They allow to set the data
> delay to two bit-clock periods.
>
> This has been tested on a platform designed off of the DAVINCI/OMAP-L138
> connected to 3 daisy-chained AD7767. An external clock drives the
> sample rate generator through the CLKS pin.
> The hardware I have only allowed me to test acquisition side of McBSP.
> It is connected to a 6 channels TDM and acts as Bit clock provider and
> Frame clock consumer.
Nice and clean, thank you for the updates!
Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
PS: sorry for the delay.
>
> Change log v1 -> v2:
> PATCH 1 (bindings):
> * Drop power-domains property's description
> * Drop the unused label 'mcbsp0' in example
> * Add <> around each entry of the 'dmas' property
> * Add 'Reviewed-by: Rob Herring <robh@kernel.org>'
> PATCH 2 (bindings):
> * Drop the 'ti,enable-sync-err' flag
> * Drop the 'ti,disable-free-run' flag
> * Add 'Reviewed-by: Rob Herring <robh@kernel.org>'
> PATCH 4:
> * In probe() use dev_err for fixed error
> PATCH 7 (TDM):
> * set playback.max_channels to 128
> * Add a check on tx_mask as the one done for rx_mask
> * Allow TDM with BP_FP format
> PATCH 9:
> * Detection of unexpected frame pulses is enabled by default
> PATCH 10:
> * Free-running mode is selected by the DAI format through
> SND_SOC_DAIFMT_[CONT/GATED]
> PATCH 12:
> * drop the 'ti,drive-dx' property
> * add 'ti,T1-framing-[rx/tx]' properties
> PATCH 13:
> * Drop the drive_dx part
> * Add support for 'T1 framing' with data delay set to 2 bit-clock
> periods
> Bastien Curutchet (13):
> ASoC: dt-bindings: davinci-mcbsp: convert McBSP bindings to yaml
> schema
> ASoC: dt-bindings: davinci-mcbsp: Add optional clock
> ASoC: ti: davinci-i2s: Remove the unused clk_input_pin attribute
> ASoC: ti: davinci-i2s: Replace dev_err with dev_err_probe
> ASoC: ti: davinci-i2s: Use external clock to drive sample rate
> generator
> ASoC: ti: davinci-i2s: Delete unnecessary assignment
> ASoC: ti: davinci-i2s: Add TDM support
> ASoC: ti: davinci-i2s: Add handling of BP_FC format
> ASoC: ti: davinci-i2s: Enable unexpected frame pulses detection
> ASoC: ti: davinci-i2s: Link free-run mode to
> SND_SOC_DAIFMT_[GATED/CONT]
> ASoC: ti: davinci-i2s: Add S24_LE to supported formats
> ASoC: dt-bindings: davinci-mcbsp: Add the 'ti,T1-framing-{rx/tx}'
> flags
> ASoC: ti: davinci-i2s: Add T1 framing support
>
> .../bindings/sound/davinci-mcbsp.txt | 50 ----
> .../bindings/sound/davinci-mcbsp.yaml | 113 +++++++
> include/linux/platform_data/davinci_asp.h | 15 -
> sound/soc/ti/davinci-i2s.c | 278 ++++++++++++++----
> 4 files changed, 333 insertions(+), 123 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/sound/davinci-mcbsp.txt
> create mode 100644 Documentation/devicetree/bindings/sound/davinci-mcbsp.yaml
>
--
Péter
^ permalink raw reply
* Re: [PATCH v2 1/6] dt-bindings: firmware: arm,scmi: set additionalProperties to true
From: Cristian Marussi @ 2024-04-09 14:56 UTC (permalink / raw)
To: Rob Herring
Cc: Peng Fan, Krzysztof Kozlowski, Peng Fan (OSS),
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Sudeep Holla,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <CAL_Jsq+aVEOPzqddu-X8GLJPex+J6V+_T1qaGHAXgp94+_-ptg@mail.gmail.com>
On Tue, Apr 09, 2024 at 09:09:46AM -0500, Rob Herring wrote:
> On Tue, Apr 9, 2024 at 7:01 AM Cristian Marussi
> <cristian.marussi@arm.com> wrote:
> >
> > On Tue, Apr 09, 2024 at 09:25:10AM +0000, Peng Fan wrote:
> > > Hi Krzysztof,
> > >
> > > > Subject: RE: [PATCH v2 1/6] dt-bindings: firmware: arm,scmi: set
> > > > additionalProperties to true
> > > >
> > > > > Subject: Re: [PATCH v2 1/6] dt-bindings: firmware: arm,scmi: set
> > > > > additionalProperties to true
> > > > >
> > > > > On 08/04/2024 08:08, Peng Fan wrote:
> > > > > >> Subject: Re: [PATCH v2 1/6] dt-bindings: firmware: arm,scmi: set
> > > > > >> additionalProperties to true
> > > > > >>
> > > > > >> On 08/04/2024 01:50, Peng Fan wrote:
> > > > > >>>> Subject: Re: [PATCH v2 1/6] dt-bindings: firmware: arm,scmi: set
> > > > > >>>> additionalProperties to true
> > > > > >>>>
> > > > > >>>> On 07/04/2024 12:04, Peng Fan wrote:
> > > > > >>>>>> Subject: Re: [PATCH v2 1/6] dt-bindings: firmware: arm,scmi:
> > > > > >>>>>> set additionalProperties to true
> > > > > >>>>>>
> > > > > >>>>>> On 07/04/2024 02:37, Peng Fan wrote:
> > > > > >>>>>>>> Subject: Re: [PATCH v2 1/6] dt-bindings: firmware: arm,scmi:
> > > > > >>>>>>>> set additionalProperties to true
> > > > > >>>>>>>>
> > > > > >>>>>>>> On 05/04/2024 14:39, Peng Fan (OSS) wrote:
> > > > > >>>>>>>>> From: Peng Fan <peng.fan@nxp.com>
> > > > > >>>>>>>>>
> > > > > >>>>>>>>> When adding vendor extension protocols, there is dt-schema
> > > > > >> warning:
> > > > > >>>>>>>>> "
> > > > > >>>>>>>>> imx,scmi.example.dtb: scmi: 'protocol@81', 'protocol@84' do
> > > > > >>>>>>>>> not match any of the regexes: 'pinctrl-[0-9]+'
> > > > > >>>>>>>>> "
> > > > > >>>>>>>>>
> > > > > >>>>>>>>> Set additionalProperties to true to address the issue.
> > > > > >>>>>>>>
> > > > > >>>>>>>> I do not see anything addressed here, except making the
> > > > > >>>>>>>> binding accepting anything anywhere...
> > > > > >>>>>>>
> > > > > >>>>>>> I not wanna add vendor protocols in arm,scmi.yaml, so will
> > > > > >>>>>>> introduce a new yaml imx.scmi.yaml which add i.MX SCMI
> > > > > >>>>>>> protocol
> > > > > >> extension.
> > > > > >>>>>>>
> > > > > >>>>>>> With additionalProperties set to false, I not know how, please
> > > > > suggest.
> > > > > >>>>>>
> > > > > >>>>>> First of all, you cannot affect negatively existing devices
> > > > > >>>>>> (their
> > > > > >>>>>> bindings) and your patch does exactly that. This should make
> > > > > >>>>>> you thing what is the correct approach...
> > > > > >>>>>>
> > > > > >>>>>> Rob gave you the comment about missing compatible - you still
> > > > > >>>>>> did not address that.
> > > > > >>>>>
> > > > > >>>>> I added the compatible in patch 2/6 in the examples "compatible
> > > > > >>>>> =
> > > > > >>>> "arm,scmi";"
> > > > > >>>>
> > > > > >>>> So you claim that your vendor extensions are the same or fully
> > > > > >>>> compatible with arm,scmi and you add nothing... Are your
> > > > > >>>> extensions/protocol valid for arm,scmi?
> > > > > >>>
> > > > > >>> Yes. They are valid for arm,scmi.
> > > > > >>>
> > > > > >>> If yes, why is this in separate binding. If no, why you use
> > > > > >>> someone
> > > > > >>>> else's compatible?
> > > > > >>>
> > > > > >>> Per SCMI Spec
> > > > > >>> 0x80-0xFF: Reserved for vendor or platform-specific extensions to
> > > > > >>> this interface
> > > > > >>>
> > > > > >>> i.MX use 0x81 for BBM, 0x84 for MISC. But other vendors will use
> > > > > >>> the id for their own protocol.
> > > > > >>
> > > > > >> So how are they valid for arm,scmi? I don't understand.
> > > > > >
> > > > > > arm,scmi is a firmware compatible string. The protocol node is a sub-node.
> > > > > > I think the arm,scmi is that saying the firmware following SCMI spec
> > > > > > to implement the protocols.
> > > > > >
> > > > > > For vendor reserved ID, firmware also follow the SCMI spec to
> > > > > > implement their own usage, so from firmware level, it is ARM SCMI
> > > > > > spec
> > > > > compatible.
> > > > >
> > > > > That's not the point. It is obvious that your firmware is compatible
> > > > > with arm,scmi, but what you try to say in this and revised patch is
> > > > > that every arm,scmi is compatible with your implementation. What you
> > > > > are saying is that 0x84 is MISC protocol for every firmware, Qualcomm,
> > > > > NXP, Samsung, TI, Mediatek etc.
> > > > >
> > > > > I claim it is not true. 0x84 is not MISC for Qualcomm, for example.
> > > >
> > > > You are right. I am lost now on how to add vendor ID support, using
> > > > arm,scmi.yaml or adding a new imx,scmi.yaml or else.
> > >
> >
> > Hi Peng,
> >
> > I dont think in the following you will find the solution to the problem,
> > it is just to recap the situation and constraints around vendor protocol
> > bindings.
> >
> > Describing SCMI vendors protocols is tricky because while on one side
> > the protocol node has to be rooted under the main scmi fw DT node (like
> > all the standard protocols) and be 'derived' from the arm,scmi.yaml
> > protocol-node definition, the optional additional properties of the a specific
> > vendor protocol nodes can be customized by each single vendor, and since,
> > as you said, you can have multiple protocols from different vendors sharing the
> > same protocol number, you could have multiple disjoint sets of valid properties
> > allowed under that same protocol node number; so on one side you have to stick
> > to some basic protocol-node defs and be rooted under the SCMI node, while on
> > the other side you will have multiple possibly allowed sets of additional
> > properties to check against, so IOW you cannot anyway just set
> > additionalProperties to false since that will result in no checks at all.
> >
> > As a consequence, at runtime, in the final DTB shipped with a specific
> > platform you should have only one of the possible vendor nodes for each
> > of these overlapping protocols, and the SCMI core at probe time will
> > pick the proper protocol implementation based on the vendor/sub_vendor
> > IDs gathered from the running SCMI fw platform at init: this way you
> > can just build the usual "all-inclusive" defconfig without worrying
> > about vendor protocol clashes since the SCMI core can pick the right
> > protocol implementation, you should just had taken care to provide the
> > proper DTB for your protocol; BUT this also means that it is not possible
> > to add multiple DT bindings based on a 'if vendor' condition since the
> > vendor itself is NOT defined and not needed in the bindings since it is
> > discoverable at runtime.
> >
> > So, after all of this blabbing of mine about this, I am wondering if it
> > is not possible that the solution is to handle each and every vendor
> > protocol node that appears with a block of addtional properties that
> > are picked via a oneOf statement from some external vendor specific
> > yaml.
> > (...in a similar way to how pinctrl additional properties are added...)
> >
> >
> > NOTE THAT the following is just an example of what I mean, it is certainly
> > wrong, incomplete annd maybe just not acceptable (and could cause DT
> > maintainers eyes to bleed :P)...
> >
> > ...so it is just fr the sake of explaining what I mean...
> >
> > diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
> > index e9d3f043c4ed..3c38a1e3ffed 100644
> > --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
> > +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
> > @@ -278,6 +278,22 @@ properties:
> > required:
> > - reg
> >
> > + protocol@81:
> > + $ref: '#/$defs/protocol-node'
> > + unevaluatedProperties: false
> > +
> > + properties:
> > + reg:
> > + const: 0x81
> > +
> > + patternProperties:
> > + '$':
> > + type: object
>
> Did you mean to have child nodes under the protocol node rather than in it?
... nope ... it is just as bad as my yaml-fu is :P ... but not sure if
vendors has also this needs or plain props will suffice...
>
> > + oneOf:
> > + - $ref: /schemas/vendor-A/scmi-protos.yaml#
> > + - $ref: /schemas/vendor-B/protos.yaml#
>
> Moved up one level, this would work, but it would have to be an
> 'anyOf' because it is possible that 2 vendors have the exact same set
> of properties.
>
ok
> I can think of 2 other ways to structure this.
>
> First, is a specific vendor protocol discoverable? Not that is 0x81
> protocol present, but that 0x81 is vendor Foo's extra special
> value-add protocol? If not, I think we should require a compatible
> string on vendor protocols. Then the base SCMI schema can require just
> that, and each vendor protocol defines its node with a $ref to
> '#/$defs/protocol-node'.
Basically yes it is discoverable, since at runtime the SCMI core, early on,
normally discovers the vendor_id/sub_vendor_id by querying the platform via
Base protocol and then later only loads/initializes (by closest match) the
vendor protocols that are present in the DT AND that has been 'tagged' at
compile time with the same vendor_id/sub_vendor_id tuple (in the vendor
module code, struct scmi_protocol)
Of course you should take care to put the proper protocol@81 node in your
vendor_A DTB for the vendor_A SCMI driver to make use of the additional
vendor_A properties that you have defined under your node as referred
in your vendor-protos.yaml...if you botch that up I will load a protocol
and call your vendor_A driver with a vendor_X DT node.
DT is currrently vendor-agnostic.
>
> The 2nd way is just a variation of the oneOf above, but do we do 1
> file per vendor protocol or 1 file per vendor. Either should be
> doable, just a matter of where 'protocol@81', etc. are defined.
>
Oh, yes mine was just an ill example...one file per vendor will do just
fine: the important thing is that the list and the yaml itself can be
extended as new vendors appears (in a backward compatble way of course)
Thanks,
Cristian
^ permalink raw reply
* Re: [PATCH v2 0/2] Add support for AD4000 series
From: Marcelo Schmitt @ 2024-04-09 14:59 UTC (permalink / raw)
To: David Lechner
Cc: Marcelo Schmitt, lars, Michael.Hennerich, jic23, robh+dt,
krzysztof.kozlowski+dt, conor+dt, linux-iio, devicetree,
linux-kernel
In-Reply-To: <CAMknhBFoX9mC3F43GSmYZyET9oQvHEB+AAsesZv-aEgFPZPA_w@mail.gmail.com>
On 04/08, David Lechner wrote:
> On Mon, Apr 8, 2024 at 9:31 AM Marcelo Schmitt
> <marcelo.schmitt@analog.com> wrote:
> >
> > This is more like an RFC patch set since configuration read/write is currently
> > buggy.
> >
> > Change log v1 -> v2:
> > - Took device tree provided by David.
> > - Dropped ABI additions in favor of device tree properties.
> > - Set differential IIO channel subtype for differential ADCs.
> > - Set scan_type shift bits to mask out correct real bits from buffer.
> > - Added __aligned(8) to buffer timestamp.
> > - Used union to reduce buffer memory usage for 16-bit devices.
> > - Used SPI transfer functions rather than SPI message.
> > - Used c99 style structure initialization.
> > - Used iio_device_claim_direct_scoped().
> > - Removed unneeded pointer casts.
> > - Added other power supplies (VDD and VIO).
> >
> > Link to v1: https://lore.kernel.org/linux-iio/cover.1711131830.git.marcelo.schmitt@analog.com/
> >
> > Additional topics:
> >
> > - Why there is no different handling for the different SPI wiring modes?
> > It looks like there is no need for different handling of "4-wire" and "3-wire"
> > modes.
> > If in "4-wire" (dt default mode), SDI is connected to SPI controller CS and
> > CNV is active high. We can activate the CNV GPIO then let the SPI controller
> > bring CS (connected to SDI) down when starting the transfer.
> > If in "3-wire" (dt single mode), if we have a CNV (active low) GPIO we activate
> > it and then proceed with with the transfer. If controller CS is connected to
> > CNV it works the same way.
> > I'm thinking it's better if we can support these devices in similar way
> > other SPI ADCs are supported. Does that make sense?
>
> In the AD7944 driver, I handled the "3-wire" mode separately because
> the sample conversion is triggered on the rising edge of the CNV line.
> In "4-wire" mode, since we have a GPIO connected to CNV, we can just
> toggle the GPIO from low to high, wait for the conversion time
> (t_CONV) and then read the sample (SPI xfer) then toggle the CNV line
> low again. In 3-wire mode, the CS line is connected to the CNV pin, so
> in order to get an up-to-date sample, we need to to toggle the CS line
> from low to high to trigger a conversion (spi xfer with no data, only
> delay), then wait for the conversion time, then read the sample (2nd
> spi xfer). So in "4-wire" mode, the CS line is getting toggled once
> per sample, but in "3-wire" mode, it is getting toggled twice per
> sample. I didn't add support for "3-wire" mode where CNV is connected
> to GPIO because we can't get max sample rate that way and it is
> unusual to not have CS connected to something. But if we do that here,
> the timing has to be different from 4-wire mode in order to not get
> stale data.
Yes, that's also the case for ad4000 series. The rising edge of CNV triggers
the conversion which causes a latency/delay of one read if CNV is connected
to a chip select.
I thought it was okay to just accept the latency since it's intrinsic to the
ADC start conversion on CNV rising edge and latency would be less noticeable
when doing continuous sampling.
Although, this indeed causes the timestamps to be disarranged, which is making me
rethink the implementation.
Yet, if we choose to have extra pulse of CNV for the sake of getting correct
timesamps, that might also impact performance for high sample rates (unless
split sample handling into different cases for single-shot and buffered readings).
I'll give it try and do it like ad7944.
>
> > To me, the "3-wire" mode with controller CS to ADC CNV is what most resembles
> > conventional SPI. The only important distinction is that the
> > controller must be able to keep ADC SDI line high during conversions.
> > Although, while the spi-engine implementation provided to me can keep SDI up
> > during conversions, I'm not sure its a thing all SPI controllers can do.
> > I tried a raspberry pi 4 some time ago and it was leaving the SDI line low if
> > no tx buffer was provided. Even with a tx full of 1s the controller would
> > bring SDI down between each 8 bits of transfer.
>
> This is a good point. It sounds like additional bindings are needed to
> describe the various wiring cases of the SDI line.
>
> It sounds like possibilities are:
>
> 1. SDI is hard-wired high -> can't write to registers, CNV is
> connected to SPI controller CS, chip is in "3-wire" mode. Currently
> adi,spi-mode="single"
> 2. SDI is connected to SDO of another chip, SDI of last chip is
> hard-wired low -> can't write to registers, CNV is connected to SPI
> controller CS, chips are in daisy chain mode. Currently
> adi,spi-mode="chain"
> 3. SDI is connected to SPI controller CS -> can't write registers,
> chip can operate in 4-wire mode with CNV connected to GPIO, Currently
> adi,spi-mode omitted.
> 4. SDI is connected to SPI controller SDO -> can write registers, and
> support all writing modes (3-wire, 4-wire, daisy chain) as long as SPI
> controller SDO line can be kept high or low at the appropriate time.
> Currently not handled.
> 5. There could be a pin mux that switches between the one of the first
> three and the 4th option (needed to avoid the issue with SPI
> controller not being able to place the SDI pin in the correct state
> during conversion trigger as described above).
>
> On AD7944, the proposed adi,spi-mode property was sufficient to
> describe what was wired to the SDI pin because we only had the first 3
> options (the AD7944 doesn't have SPI registers to write to).
>
> Also see related comments in my reply to the DT bindings patch.
>
> (From the complete bindings point of view, we should probably also
> consider the possibility of variations of 1. and 2. where CS of the
> SPI controller is not wired and CNV is connected to a GPIO - this can
> be determined by the combination of the adi,spi-mode property and the
> presence or absence of the cnv-gpios property.)
This sounds reasonable to me. I also think the comments on DT patch are good.
Will comment there too.
>
> > Anyway, single-shot and buffered reads work with the spi-engine controller
> > with ADC in "3-wire"/single mode with controller CS line connected to ADC CNV
> > pin which is how I've been testing it.
>
> Technically, yes data can be captured in "3-wire" mode with a single
> CS toggle, but then the data is stale and doesn't correspond to the
> soft timestamp because it is reading the data from the previous
> conversion triggered by the last SPI xfer, whenever that was. Since it
> is trivial to avoid this by adding the extra CS/CNV toggle I describe
> above, I don't see any reason not to.
Okay, will make it do the extra pulse to CNV for "3-wire" mode.
>
> But the way the driver is written now, it is actually only supporting
> the unnamed wiring option 4 from above, so now I understand the
> confusion about 3-wire vs. 4-wire mode in that context.
>
> >
> > - Why did not make vref regulator optional?
> > Other SAR ADCs I've seen needed a voltage reference otherwise they simply
> > could not provide any reasonable readings. Isn't it preferable to fail rather
> > than having a device that can't provide reliable data?
>
> In the device tree bindings, making vref-supply required makes sense
> since there is no internal reference. In the driver, as discussed in
> V1, it will fail if vref-supply in regulator_get_voltage() if
> vref-supply is missing and we use devm_regulator_get() instead of
> devm_regulator_get_optional(). So leaving it as-is is fine. We have a
> plan to clean this up later anyway.
>
Not sure I understand the idea here. Should the driver use
devm_regulator_get_optional() instead of devm_regulator_get() because
the optional call would fail immediately if no vref-supply while the regular
call would only fail at regulator_get_voltage()? Why? This looks very counter
intuitive to me.
> >
> > - Why did not split into AD and ADAQ patches?
> > The main difference between AD and ADAQ is the amplifier in front of the ADC.
> > If only supporting AD, we could probably avoid the scale table since it would
> > only have two possible values per ADC. But then the handling of span compression
> > scale would need refactoring to be in the scale table when adding ADAQ.
> > I'm not excited to implement something knowing it will need rework in the
> > following patch. Will do if required.
>
> If it isn't that much work, it seems worth it to me. If the driver
> work is too much, maybe just split the DT patch?
>
> >
> > - Span compression and offset.
> > For non-differential ADCs, enabling the span compression requires an input offset.
> > Link: https://www.analog.com/media/en/technical-documentation/data-sheets/AD4000-4004-4008.pdf
> > page 18
> > and
> > Link: https://www.analog.com/media/en/technical-documentation/data-sheets/ad4002-4006-4010.pdf
> > page 19
> > I updated the _offset attribute for those ADCs according to span compression
> > being enabled or not. Is it okay to have an attribute update cause an update to
> > another one?
> > Maybe also make the span compression a dt property and have it fixed after probe?
>
> This doesn't sound like something that belongs in DT since it doesn't
> depend on the physical properties of what is wired to the input.
>
> But the fact that offset should not be read until after scale is set
> sounds like a quirk that would be worth documenting in some
> chip-specific docs.
>
> >
> > - Configuration register
> > Despite it doing single-shot and buffered captures, read and writes to the
> > configuration register are currently buggy. It is as if the register was
> > "floating". I tried setting up buffers like ad7768-1, adxl355_core, bma220_spi,
> > bma400_core, and mcp3911.
>
> If the ADC CNV pin is connected to a GPIO and the ADC SDI pin is
> connected to SDO of the SPI controller, then nothing is connected to
> CS of the SPI controller, so that might be the problem.
ADC CNV is connected to controller CS and ADC SDI to controller SDO.
Think it's something to do with buffer alignment.
Will try the changes suggested in reply to driver patch.
>
> >
> >
> > Thanks,
> > Marcelo
> >
> > Marcelo Schmitt (2):
> > dt-bindings: iio: adc: Add AD4000
> > iio: adc: Add support for AD4000
> >
> > .../bindings/iio/adc/adi,ad4000.yaml | 201 ++++++
> > MAINTAINERS | 8 +
> > drivers/iio/adc/Kconfig | 12 +
> > drivers/iio/adc/Makefile | 1 +
> > drivers/iio/adc/ad4000.c | 649 ++++++++++++++++++
> > 5 files changed, 871 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4000.yaml
> > create mode 100644 drivers/iio/adc/ad4000.c
> >
> > --
> > 2.43.0
> >
> >
^ permalink raw reply
* Re: [PATCH v2 2/5] arm64: dts: qcom: sm8350-hdk: add USB-C orientation GPIO
From: Konrad Dybcio @ 2024-04-09 15:00 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240409-hdk-orientation-gpios-v2-2-658efd993987@linaro.org>
On 4/9/24 16:28, Dmitry Baryshkov wrote:
> Define the USB-C orientation GPIO so that the USB-C port orientation is
> known without having to resort to the altmode notifications.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply
* Re: [PATCH v2 3/5] arm64: dts: qcom: sm8450-hdk: add USB-C orientation GPIO
From: Konrad Dybcio @ 2024-04-09 15:00 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240409-hdk-orientation-gpios-v2-3-658efd993987@linaro.org>
On 4/9/24 16:28, Dmitry Baryshkov wrote:
> Define the USB-C orientation GPIO so that the USB-C port orientation is
> known without having to resort to the altmode notifications.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply
* Re: [PATCH v2 4/5] arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: add USB-C orientation GPIOs
From: Konrad Dybcio @ 2024-04-09 15:00 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240409-hdk-orientation-gpios-v2-4-658efd993987@linaro.org>
On 4/9/24 16:28, Dmitry Baryshkov wrote:
> Define the USB-C orientation GPIOs so that the USB-C ports orientation
> is known without having to resort to the altmode notifications.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply
* Re: [PATCH v2 5/5] arm64: dts: qcom: sc8180x-lenovo-flex-5g: add USB-C orientation GPIOs
From: Konrad Dybcio @ 2024-04-09 15:00 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240409-hdk-orientation-gpios-v2-5-658efd993987@linaro.org>
On 4/9/24 16:28, Dmitry Baryshkov wrote:
> Define the USB-C orientation GPIOs so that the USB-C ports orientation
> is known without having to resort to the altmode notifications.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply
* Re: [PATCH v1 0/6] SiFive cache controller PMU drivers
From: Conor Dooley @ 2024-04-09 15:01 UTC (permalink / raw)
To: Conor Dooley
Cc: Samuel Holland, Will Deacon, Mark Rutland, Eric Lin,
Palmer Dabbelt, devicetree, linux-kernel, Paul Walmsley,
linux-riscv, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel
In-Reply-To: <20240216-shopping-unnoticed-e73e72a0e849@wendy>
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On Fri, Feb 16, 2024 at 10:05:04AM +0000, Conor Dooley wrote:
> On Thu, Feb 15, 2024 at 04:08:12PM -0800, Samuel Holland wrote:
>
> > All three of these cache controllers (with PMUs) have been integrated in
> > SoCs by our customers. However, as none of those SoCs have been publicly
> > announced yet, I cannot include SoC-specific compatible strings in this
> > version of the devicetree bindings.
>
> And I don't want to apply any of those dt-binding patches until then.
> Stuff like "sifive,perfmon-counters" seems like a property that would
> go away with a device-specific compatible, at least for the ccache.
Reading the P550 stuff today reminded me that I had not got around to
looking at this series again. You should be able to use that to satisfy
my wish for some soc-specific compatibles, right?
And w.r.r. the perfmon-counters property, looked to me like Rob was
proposing it not even having to be vendor specific.
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^ permalink raw reply
* Re: [PATCH v1 1/6] dt-bindings: cache: Document the sifive,perfmon-counters property
From: Conor Dooley @ 2024-04-09 15:03 UTC (permalink / raw)
To: Samuel Holland
Cc: Will Deacon, Mark Rutland, Eric Lin, Palmer Dabbelt, devicetree,
linux-kernel, Paul Walmsley, linux-riscv, Rob Herring,
Krzysztof Kozlowski, linux-arm-kernel
In-Reply-To: <20240216000837.1868917-2-samuel.holland@sifive.com>
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On Thu, Feb 15, 2024 at 04:08:13PM -0800, Samuel Holland wrote:
> The SiFive Composable Cache controller contains an optional PMU with a
> configurable number of event counters. Document a property which
> describes the number of available counters.
>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
>
> Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> index 7e8cebe21584..100eda4345de 100644
> --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> @@ -81,6 +81,11 @@ properties:
> The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
> The reserved memory node should be defined as per the bindings in reserved-memory.txt.
>
> + sifive,perfmon-counters:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> + description: Number of PMU counter registers
I think this should be restricted to devices that actually have it,
given we've already gone pretty hard in this binding with specific
requirements.
> +
> allOf:
> - $ref: /schemas/cache-controller.yaml#
>
> --
> 2.43.0
>
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^ permalink raw reply
* Re: [PATCH 2/6] soc: qcom: smem: Add pcode/fcode getters
From: Konrad Dybcio @ 2024-04-09 15:04 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, linux-kernel,
dri-devel, freedreno, devicetree, Neil Armstrong
In-Reply-To: <zc5u7ixaser6ekl3sltzxccstu63tpydxybquxz5hcasj4cmfo@csjwfifugeod>
On 4/6/24 04:21, Dmitry Baryshkov wrote:
> On Fri, Apr 05, 2024 at 10:41:30AM +0200, Konrad Dybcio wrote:
>> Introduce getters for SoC product and feature codes and export them.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
[...]
>> + /* Ensure the value makes sense */
>> + if (raw_code >= SOCINFO_FC_INT_RESERVE)
>> + raw_code = SOCINFO_FC_UNKNOWN;
>
> This looks like a c&p from the previous function. Should we be comparing
> the raw_code with a SOCINFO_PC_ constant?
Looks like!
Konrad
^ permalink raw reply
* [PATCH net-next v7 00/17] net: Add support for Power over Ethernet (PoE)
From: Kory Maincent @ 2024-04-09 15:03 UTC (permalink / raw)
To: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Jonathan Corbet, Luis Chamberlain, Russ Weight,
Greg Kroah-Hartman, Rafael J. Wysocki, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Oleksij Rempel, Mark Brown,
Frank Rowand, Andrew Lunn, Heiner Kallweit, Russell King
Cc: Thomas Petazzoni, netdev, linux-kernel, linux-doc, devicetree,
Dent Project, kernel, Maxime Chevallier, Kory Maincent
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 5426 bytes --]
From: Kory Maincent (Dent Project) <kory.maincent@bootlin.com>
This patch series aims at adding support for PoE (Power over Ethernet),
based on the already existing support for PoDL (Power over Data Line)
implementation. In addition, it adds support for two specific PoE
controller, the Microchip PD692x0 and the TI TPS23881.
In detail:
- Patch 1 to 13 prepare net to support PoE devices.
- Patch 14 and 15 add PD692x0 PoE PSE controller driver and its binding.
- Patch 16 and 17 add TI TPS23881 PSE controller driver and its binding.
Changes in v7:
- Fix code, doc and kdoc nit.
- Fix few pd692x0 dt binding issues.
- Rename *flash_fw* functions to *flash_sram_fw* in tps23881 driver.
- Link to v6: https://lore.kernel.org/r/20240326-feature_poe-v6-0-c1011b6ea1cb@bootlin.com
Changes in v6:
- TPS23881 fix firmware management release missing.
- Use pcdev device pointer as regulator consumer and provider.
- Rename of_legacy to no_of_pse_pi.
- Add kdoc, and separate functions for better readability.
- Add vpwr-supply regulator parent.
- Link to v5: https://lore.kernel.org/r/20240227-feature_poe-v5-0-28f0aa48246d@bootlin.com
Changes in v5:
- Fix bindings nit.
- Add supported-polarity parameter to bindings.
- Fix yamllint binding errors.
- Remove the nested lock brought by the use of regulator framework.
- Link to v4: https://lore.kernel.org/r/20240215-feature_poe-v4-0-35bb4c23266c@bootlin.com
Changes in v4:
- Replaced sponsored-by tag by a simple sentence.
- Fix pse_pi node bindings.
- Add pse pi documentation written by Oleksij.
- Link to v3: https://lore.kernel.org/r/20240208-feature_poe-v3-0-531d2674469e@bootlin.com
Changes in v3:
- Add patches to add Oleksij and myself to PSE MAINTAINERS.
- Add patches to add pse devlink.
- Add TI TPS23881 PSE controller driver with its binding.
- Replace pse_get_types helper by pse_has_podl and pse_has_c33
- Changed the PSE core bindings.
- Add a setup_pi_matrix callback.
- Register regulator for each PSE PI (Power Interface).
- Changed the PD692x0 bindings.
- Updated PD692x0 drivers to new bindings and PSE PI description.
- Updated PD692x0 drivers according to the reviews and made fixes.
- Link to v2: https://lore.kernel.org/r/20231201-feature_poe-v2-0-56d8cac607fa@bootlin.com
Changes in v2:
- Extract "firmware_loader: Expand Firmware upload error codes patches" to
send it alone and get it merge in an immutable branch.
- Add "c33" prefix for PoE variables and enums.
- Enhance few comments.
- Add PSE Documentation.
- Make several changes in pd692x0 driver, mainly for readibility.
- Link to v1: https://lore.kernel.org/r/20231116-feature_poe-v1-0-be48044bf249@bootlin.com
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
---
Kory Maincent (17):
MAINTAINERS: net: Add Oleksij to pse-pd maintainers
of: property: Add fw_devlink support for pse parent
net: pse-pd: Rectify and adapt the naming of admin_cotrol member of struct pse_control_config
ethtool: Expand Ethernet Power Equipment with c33 (PoE) alongside PoDL
net: pse-pd: Introduce PSE types enumeration
net: ethtool: pse-pd: Expand pse commands with the PSE PoE interface
netlink: specs: Modify pse attribute prefix
netlink: specs: Expand the pse netlink command with PoE interface
MAINTAINERS: Add myself to pse networking maintainer
net: pse-pd: Add support for PSE PIs
dt-bindings: net: pse-pd: Add another way of describing several PSE PIs
net: pse-pd: Add support for setup_pi_matrix callback
net: pse-pd: Use regulator framework within PSE framework
dt-bindings: net: pse-pd: Add bindings for PD692x0 PSE controller
net: pse-pd: Add PD692x0 PSE controller driver
dt-bindings: net: pse-pd: Add bindings for TPS23881 PSE controller
net: pse-pd: Add TI TPS23881 PSE controller driver
.../bindings/net/pse-pd/microchip,pd692x0.yaml | 169 +++
.../bindings/net/pse-pd/pse-controller.yaml | 101 +-
.../bindings/net/pse-pd/ti,tps23881.yaml | 95 ++
Documentation/netlink/specs/ethtool.yaml | 33 +-
Documentation/networking/ethtool-netlink.rst | 20 +
Documentation/networking/index.rst | 1 +
Documentation/networking/pse-pd/index.rst | 10 +
Documentation/networking/pse-pd/introduction.rst | 73 ++
Documentation/networking/pse-pd/pse-pi.rst | 302 +++++
MAINTAINERS | 8 +
drivers/net/pse-pd/Kconfig | 20 +
drivers/net/pse-pd/Makefile | 2 +
drivers/net/pse-pd/pd692x0.c | 1223 ++++++++++++++++++++
drivers/net/pse-pd/pse_core.c | 513 +++++++-
drivers/net/pse-pd/pse_regulator.c | 49 +-
drivers/net/pse-pd/tps23881.c | 820 +++++++++++++
drivers/of/property.c | 2 +
include/linux/pse-pd/pse.h | 86 +-
include/uapi/linux/ethtool.h | 55 +
include/uapi/linux/ethtool_netlink.h | 3 +
net/ethtool/pse-pd.c | 60 +-
21 files changed, 3543 insertions(+), 102 deletions(-)
---
base-commit: 49ba5d653980157adbd9c6e5fd7d8f7dfe7e39b8
change-id: 20231024-feature_poe-139490e73403
Best regards,
--
Köry Maincent, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH net-next v7 04/17] ethtool: Expand Ethernet Power Equipment with c33 (PoE) alongside PoDL
From: Kory Maincent @ 2024-04-09 15:03 UTC (permalink / raw)
To: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Jonathan Corbet, Luis Chamberlain, Russ Weight,
Greg Kroah-Hartman, Rafael J. Wysocki, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Oleksij Rempel, Mark Brown,
Frank Rowand, Andrew Lunn, Heiner Kallweit, Russell King
Cc: Thomas Petazzoni, netdev, linux-kernel, linux-doc, devicetree,
Dent Project, kernel, Maxime Chevallier, Kory Maincent
In-Reply-To: <20240409-feature_poe-v7-0-11e38efd4dee@bootlin.com>
From: Kory Maincent (Dent Project) <kory.maincent@bootlin.com>
In the current PSE interface for Ethernet Power Equipment, support is
limited to PoDL. This patch extends the interface to accommodate the
objects specified in IEEE 802.3-2022 145.2 for Power sourcing
Equipment (PSE).
The following objects are now supported and considered mandatory:
- IEEE 802.3-2022 30.9.1.1.5 aPSEPowerDetectionStatus
- IEEE 802.3-2022 30.9.1.1.2 aPSEAdminState
- IEEE 802.3-2022 30.9.1.2.1 aPSEAdminControl
To avoid confusion between "PoDL PSE" and "PoE PSE", which have similar
names but distinct values, we have followed the suggestion of Oleksij
Rempel and Andrew Lunn to maintain separate naming schemes for each,
using c33 (clause 33) prefix for "PoE PSE".
You can find more details in the discussion threads here:
https://lore.kernel.org/netdev/20230912110637.GI780075@pengutronix.de/
https://lore.kernel.org/netdev/2539b109-72ad-470a-9dae-9f53de4f64ec@lunn.ch/
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
---
Changes in v2:
- Rename all the PoE variables and enum with a c33 prefix.
- Add documentation, thanks to Oleksij for having written one.
Changes in v3:
- Fix documentation build warning.
---
Documentation/networking/index.rst | 1 +
Documentation/networking/pse-pd/index.rst | 9 +++
Documentation/networking/pse-pd/introduction.rst | 73 ++++++++++++++++++++++++
include/linux/pse-pd/pse.h | 9 +++
include/uapi/linux/ethtool.h | 43 ++++++++++++++
include/uapi/linux/ethtool_netlink.h | 3 +
6 files changed, 138 insertions(+)
diff --git a/Documentation/networking/index.rst b/Documentation/networking/index.rst
index 473d72c36d61..7664c0bfe461 100644
--- a/Documentation/networking/index.rst
+++ b/Documentation/networking/index.rst
@@ -93,6 +93,7 @@ Contents:
plip
ppp_generic
proc_net_tcp
+ pse-pd/index
radiotap-headers
rds
regulatory
diff --git a/Documentation/networking/pse-pd/index.rst b/Documentation/networking/pse-pd/index.rst
new file mode 100644
index 000000000000..18197bc7303d
--- /dev/null
+++ b/Documentation/networking/pse-pd/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Power Sourcing Equipment (PSE) Documentation
+============================================
+
+.. toctree::
+ :maxdepth: 2
+
+ introduction
diff --git a/Documentation/networking/pse-pd/introduction.rst b/Documentation/networking/pse-pd/introduction.rst
new file mode 100644
index 000000000000..e3d3faaef717
--- /dev/null
+++ b/Documentation/networking/pse-pd/introduction.rst
@@ -0,0 +1,73 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Power Sourcing Equipment (PSE) in IEEE 802.3 Standard
+=====================================================
+
+Overview
+--------
+
+Power Sourcing Equipment (PSE) is essential in networks for delivering power
+along with data over Ethernet cables. It usually refers to devices like
+switches and hubs that supply power to Powered Devices (PDs) such as IP
+cameras, VoIP phones, and wireless access points.
+
+PSE vs. PoDL PSE
+----------------
+
+PSE in the IEEE 802.3 standard generally refers to equipment that provides
+power alongside data over Ethernet cables, typically associated with Power over
+Ethernet (PoE).
+
+PoDL PSE, or Power over Data Lines PSE, specifically denotes PSEs operating
+with single balanced twisted-pair PHYs, as per Clause 104 of IEEE 802.3. PoDL
+is significant in contexts like automotive and industrial controls where power
+and data delivery over a single pair is advantageous.
+
+IEEE 802.3-2018 Addendums and Related Clauses
+---------------------------------------------
+
+Key addenda to the IEEE 802.3-2018 standard relevant to power delivery over
+Ethernet are as follows:
+
+- **802.3af (Approved in 2003-06-12)**: Known as PoE in the market, detailed in
+ Clause 33, delivering up to 15.4W of power.
+- **802.3at (Approved in 2009-09-11)**: Marketed as PoE+, enhancing PoE as
+ covered in Clause 33, increasing power delivery to up to 30W.
+- **802.3bt (Approved in 2018-09-27)**: Known as 4PPoE in the market, outlined
+ in Clause 33. Type 3 delivers up to 60W, and Type 4 up to 100W.
+- **802.3bu (Approved in 2016-12-07)**: Formerly referred to as PoDL, detailed
+ in Clause 104. Introduces Classes 0 - 9. Class 9 PoDL PSE delivers up to ~65W
+
+Kernel Naming Convention Recommendations
+----------------------------------------
+
+For clarity and consistency within the Linux kernel's networking subsystem, the
+following naming conventions are recommended:
+
+- For general PSE (PoE) code, use "c33_pse" key words. For example:
+ ``enum ethtool_c33_pse_admin_state c33_admin_control;``.
+ This aligns with Clause 33, encompassing various PoE forms.
+
+- For PoDL PSE - specific code, use "podl_pse". For example:
+ ``enum ethtool_podl_pse_admin_state podl_admin_control;`` to differentiate
+ PoDL PSE settings according to Clause 104.
+
+Summary of Clause 33: Data Terminal Equipment (DTE) Power via Media Dependent Interface (MDI)
+---------------------------------------------------------------------------------------------
+
+Clause 33 of the IEEE 802.3 standard defines the functional and electrical
+characteristics of Powered Device (PD) and Power Sourcing Equipment (PSE).
+These entities enable power delivery using the same generic cabling as for data
+transmission, integrating power with data communication for devices such as
+10BASE-T, 100BASE-TX, or 1000BASE-T.
+
+Summary of Clause 104: Power over Data Lines (PoDL) of Single Balanced Twisted-Pair Ethernet
+--------------------------------------------------------------------------------------------
+
+Clause 104 of the IEEE 802.3 standard delineates the functional and electrical
+characteristics of PoDL Powered Devices (PDs) and PoDL Power Sourcing Equipment
+(PSEs). These are designed for use with single balanced twisted-pair Ethernet
+Physical Layers. In this clause, 'PSE' refers specifically to PoDL PSE, and
+'PD' to PoDL PD. The key intent is to provide devices with a unified interface
+for both data and the power required to process this data over a single
+balanced twisted-pair Ethernet connection.
diff --git a/include/linux/pse-pd/pse.h b/include/linux/pse-pd/pse.h
index 199cf4ae3cf2..be4e5754eb24 100644
--- a/include/linux/pse-pd/pse.h
+++ b/include/linux/pse-pd/pse.h
@@ -17,9 +17,12 @@ struct pse_controller_dev;
*
* @podl_admin_control: set PoDL PSE admin control as described in
* IEEE 802.3-2018 30.15.1.2.1 acPoDLPSEAdminControl
+ * @c33_admin_control: set PSE admin control as described in
+ * IEEE 802.3-2022 30.9.1.2.1 acPSEAdminControl
*/
struct pse_control_config {
enum ethtool_podl_pse_admin_state podl_admin_control;
+ enum ethtool_c33_pse_admin_state c33_admin_control;
};
/**
@@ -29,10 +32,16 @@ struct pse_control_config {
* functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState
* @podl_pw_status: power detection status of the PoDL PSE.
* IEEE 802.3-2018 30.15.1.1.3 aPoDLPSEPowerDetectionStatus:
+ * @c33_admin_state: operational state of the PSE
+ * functions. IEEE 802.3-2022 30.9.1.1.2 aPSEAdminState
+ * @c33_pw_status: power detection status of the PSE.
+ * IEEE 802.3-2022 30.9.1.1.5 aPSEPowerDetectionStatus:
*/
struct pse_control_status {
enum ethtool_podl_pse_admin_state podl_admin_state;
enum ethtool_podl_pse_pw_d_status podl_pw_status;
+ enum ethtool_c33_pse_admin_state c33_admin_state;
+ enum ethtool_c33_pse_pw_d_status c33_pw_status;
};
/**
diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
index 95c2f09f0d0a..29ac06d66228 100644
--- a/include/uapi/linux/ethtool.h
+++ b/include/uapi/linux/ethtool.h
@@ -752,6 +752,49 @@ enum ethtool_module_power_mode {
ETHTOOL_MODULE_POWER_MODE_HIGH,
};
+/**
+ * enum ethtool_c33_pse_admin_state - operational state of the PoDL PSE
+ * functions. IEEE 802.3-2022 30.9.1.1.2 aPSEAdminState
+ * @ETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN: state of PSE functions is unknown
+ * @ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED: PSE functions are disabled
+ * @ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED: PSE functions are enabled
+ */
+enum ethtool_c33_pse_admin_state {
+ ETHTOOL_C33_PSE_ADMIN_STATE_UNKNOWN = 1,
+ ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED,
+ ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED,
+};
+
+/**
+ * enum ethtool_c33_pse_pw_d_status - power detection status of the PSE.
+ * IEEE 802.3-2022 30.9.1.1.3 aPoDLPSEPowerDetectionStatus:
+ * @ETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN: PSE status is unknown
+ * @ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED: "The enumeration \u201cdisabled\u201d
+ * indicates that the PSE State diagram is in the state DISABLED."
+ * @ETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING: "The enumeration \u201csearching\u201d
+ * indicates the PSE State diagram is in a state other than those
+ * listed."
+ * @ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING: "The enumeration
+ * \u201cdeliveringPower\u201d indicates that the PSE State diagram is in the
+ * state POWER_ON."
+ * @ETHTOOL_C33_PSE_PW_D_STATUS_TEST: "The enumeration \u201ctest\u201d indicates that
+ * the PSE State diagram is in the state TEST_MODE."
+ * @ETHTOOL_C33_PSE_PW_D_STATUS_FAULT: "The enumeration \u201cfault\u201d indicates that
+ * the PSE State diagram is in the state TEST_ERROR."
+ * @ETHTOOL_C33_PSE_PW_D_STATUS_OTHERFAULT: "The enumeration \u201cotherFault\u201d
+ * indicates that the PSE State diagram is in the state IDLE due to
+ * the variable error_condition = true."
+ */
+enum ethtool_c33_pse_pw_d_status {
+ ETHTOOL_C33_PSE_PW_D_STATUS_UNKNOWN = 1,
+ ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED,
+ ETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING,
+ ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING,
+ ETHTOOL_C33_PSE_PW_D_STATUS_TEST,
+ ETHTOOL_C33_PSE_PW_D_STATUS_FAULT,
+ ETHTOOL_C33_PSE_PW_D_STATUS_OTHERFAULT,
+};
+
/**
* enum ethtool_podl_pse_admin_state - operational state of the PoDL PSE
* functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState
diff --git a/include/uapi/linux/ethtool_netlink.h b/include/uapi/linux/ethtool_netlink.h
index 23e225f00fb0..75822512faba 100644
--- a/include/uapi/linux/ethtool_netlink.h
+++ b/include/uapi/linux/ethtool_netlink.h
@@ -913,6 +913,9 @@ enum {
ETHTOOL_A_PODL_PSE_ADMIN_STATE, /* u32 */
ETHTOOL_A_PODL_PSE_ADMIN_CONTROL, /* u32 */
ETHTOOL_A_PODL_PSE_PW_D_STATUS, /* u32 */
+ ETHTOOL_A_C33_PSE_ADMIN_STATE, /* u32 */
+ ETHTOOL_A_C33_PSE_ADMIN_CONTROL, /* u32 */
+ ETHTOOL_A_C33_PSE_PW_D_STATUS, /* u32 */
/* add new constants above here */
__ETHTOOL_A_PSE_CNT,
--
2.34.1
^ permalink raw reply related
* [PATCH net-next v7 01/17] MAINTAINERS: net: Add Oleksij to pse-pd maintainers
From: Kory Maincent @ 2024-04-09 15:03 UTC (permalink / raw)
To: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Jonathan Corbet, Luis Chamberlain, Russ Weight,
Greg Kroah-Hartman, Rafael J. Wysocki, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Oleksij Rempel, Mark Brown,
Frank Rowand, Andrew Lunn, Heiner Kallweit, Russell King
Cc: Thomas Petazzoni, netdev, linux-kernel, linux-doc, devicetree,
Dent Project, kernel, Maxime Chevallier, Kory Maincent
In-Reply-To: <20240409-feature_poe-v7-0-11e38efd4dee@bootlin.com>
From: Kory Maincent (Dent Project) <kory.maincent@bootlin.com>
Oleksij was the first to add support for pse-pd net subsystem.
Add himself to the maintainers seems logical.
Acked-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
Changes in v3:
- New patch
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4745ea94d463..e3363e4fc261 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17783,6 +17783,13 @@ F: include/net/psample.h
F: include/uapi/linux/psample.h
F: net/psample
+PSE NETWORK DRIVER
+M: Oleksij Rempel <o.rempel@pengutronix.de>
+L: netdev@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/net/pse-pd/
+F: drivers/net/pse-pd/
+
PSTORE FILESYSTEM
M: Kees Cook <keescook@chromium.org>
R: Tony Luck <tony.luck@intel.com>
--
2.34.1
^ permalink raw reply related
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