* [PATCH 1/1] arm64: dts: imx8mp: Enable HDMI on TQMa8MPxL/MBa8MPxL
From: Alexander Stein @ 2024-04-10 6:37 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Alexander Stein, linux, devicetree, imx, linux-arm-kernel,
linux-kernel
Enable HDMI nodes and add the output connector.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
.../freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 38 +++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
index 86d3da36e4f3e..c51ed7d991d18 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
@@ -135,6 +135,18 @@ led-2 {
};
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "X44";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+ };
+
display: display {
/*
* Display is not fixed, so compatible has to be added from
@@ -470,6 +482,28 @@ &gpio5 {
"", "", "", "";
};
+&hdmi_pvi {
+ status = "okay";
+};
+
+&hdmi_tx {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&hdmi_tx_phy {
+ status = "okay";
+};
+
&i2c2 {
clock-frequency = <384000>;
pinctrl-names = "default", "gpio";
@@ -531,6 +565,10 @@ &i2c6 {
status = "okay";
};
+&lcdif3 {
+ status = "okay";
+};
+
&pcf85063 {
/* RTC_EVENT# is connected on MBa8MPxL */
pinctrl-names = "default";
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v3 1/2] dt-bindings: dma: fsl-edma: remove 'clocks' from required
From: Krzysztof Kozlowski @ 2024-04-10 6:47 UTC (permalink / raw)
To: Frank Li
Cc: conor+dt, devicetree, dmaengine, imx, krzysztof.kozlowski+dt,
linux-kernel, peng.fan, robh, vkoul,
20240409185416.2224609-1-Frank.Li, Xu Yang, Shengjiu Wang,
Pankaj Gupta, Shenwei Wang
In-Reply-To: <383141cd-7f6f-4ed0-945b-7761833ecc35@linaro.org>
On 10/04/2024 08:32, Krzysztof Kozlowski wrote:
> On 10/04/2024 08:30, Krzysztof Kozlowski wrote:
>> On 09/04/2024 23:09, Frank Li wrote:
>>> On Tue, Apr 09, 2024 at 10:02:32PM +0200, Krzysztof Kozlowski wrote:
>>>> On 09/04/2024 20:54, Frank Li wrote:
>>>>> fsl,imx8qm-adma and fsl,imx8qm-edma don't require 'clocks'. Remove it from
>>>>> required and add 'if' block for other compatible string to keep the same
>>>>> restrictions.
>>>>>
>>>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>>> Signed-off-by: Frank Li <Frank.Li@nxp.com>
>>>>> ---
>>>>>
>>>>> Notes:
>>>>> Change from v2 to v3
>>>>> - rebase to dmaengine/next
>>>>
>>>> This fails...
>>>
>>> What's wrong?
>>>
>>> https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git/log/?h=next
>>>
>>>>
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
>>>>> index 825f4715499e5..657a7d3ebf857 100644
>>>>> --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml
>>>>> +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
>>>>> @@ -82,7 +82,6 @@ required:
>>>>> - compatible
>>>>> - reg
>>>>> - interrupts
>>>>> - - clocks
>>>>> - dma-channels
>>>>>
>>>>> allOf:
>>>>> @@ -187,6 +186,22 @@ allOf:
>>>>> "#dma-cells":
>>>>> const: 3
>>>>>
>>>>> + - if:
>>>>> + properties:
>>>>> + compatible:
>>>>> + contains:
>>>>
>>>> It does not look like you tested the bindings, at least after quick
>>>> look. Please run `make dt_binding_check` (see
>>>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>>>> Maybe you need to update your dtschema and yamllint.
>>>
>>> Strange, Test passed
>>>
>>> make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 dt_binding_check DT_SCHEMA_FILES=fsl,edma.yaml
>>> LINT Documentation/devicetree/bindings
>>> DTEX Documentation/devicetree/bindings/dma/fsl,edma.example.dts
>>> CHKDT Documentation/devicetree/bindings/processed-schema.json
>>> SCHEMA Documentation/devicetree/bindings/processed-schema.json
>>> DTC_CHK Documentation/devicetree/bindings/dma/fsl,edma.example.dtb
>>
>> Nope, you tested other patch. Just look at your second patch for this.
>> When reviewer points to errors to your code, please investigate?
>>
>> NAK, fix your patches.
>
> And to prove it, so you will stop wasting my time:
> ../Documentation/devicetree/bindings/dma/fsl,edma.yaml:192:1: found
> character that cannot start any token
>
> ../Documentation/devicetree/bindings/dma/fsl,edma.yaml:192:1: [error]
> syntax error: found character '\t' that cannot start any token (syntax)
>
> ../Documentation/devicetree/bindings/dma/fsl,edma.yaml:192:1: found
> character that cannot start any token
>
> Documentation/devicetree/bindings/dma/fsl,edma.yaml: ignoring, error
> parsing file
Dear NXP,
Quality of patches from NXP is terrible. Several of them are poorly
coded, not following coding style, their submission is not following the
process and requires a lot of effort from reviewers. I was already
complaining about this on mailing lists months ago.
Things did not improve much.
However another trouble is the quality of responses during review. In
many patchsets your responses to reviewers comments were half-baked, not
on actual topic or just with minimal effort to close the topic from your
side. That's not how it works.
If you receive comment, you must investigate. Don't respond immediately
"no, I don't see error" or "but I want something else", but be sure that
you fixed the problem.
Such responses of minimal effort or pushing your own patch is
significant effort on reviewers side. I was complaining about this as
well. This patch here, which does not even build/test yet you claim in
response that you test, is perfect example of it. You got comment from
reviewer and instead really investigating this, you respond that
everything is good on your side. Typical response with minimal effort on
your side, but pushing it to the community.
That's it, that's too much.
NXP, your contributions are poor quality and put too much effort on
community.
Please improve your process, e.g. by training people interacting with
community and using extensive internal review. You can also reach to
experienced community members for help in training and explaining
upstream work, like Denx, Pengutronix, Bootlin, Linaro, Baylibre,
Collabora and others.
Till the situation improves, I will be ignoring all patches from @nxp.com.
Best regards,
Krzysztof
^ permalink raw reply
* RE: [EXT] Re: [PATCH v2 1/1] arm64: dts: imx93-11x11-evk: add rtc PCF2131 support
From: Joy Zou @ 2024-04-10 6:52 UTC (permalink / raw)
To: Krzysztof Kozlowski, Jacky Bai, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
shawnguo@kernel.org, s.hauer@pengutronix.de
Cc: kernel@pengutronix.de, festevam@gmail.com, dl-linux-imx,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <d53ab0fd-cd12-48ec-9a80-6ae17690b726@linaro.org>
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: 2024年4月10日 14:34
> To: Joy Zou <joy.zou@nxp.com>; Jacky Bai <ping.bai@nxp.com>;
> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> conor+dt@kernel.org; shawnguo@kernel.org; s.hauer@pengutronix.de
> Cc: kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx
> <linux-imx@nxp.com>; devicetree@vger.kernel.org; imx@lists.linux.dev;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: [EXT] Re: [PATCH v2 1/1] arm64: dts: imx93-11x11-evk: add rtc
> PCF2131 support
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
> b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
> > index 07e85a30a25f..e66723ed25c2 100644
> > --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
> > @@ -281,6 +281,23 @@ ldo5: LDO5 {
> > };
> > };
> >
> > +&lpi2c3 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + clock-frequency = <400000>;
> > + pinctrl-names = "default", "sleep";
> > + pinctrl-0 = <&pinctrl_lpi2c3>;
> > + pinctrl-1 = <&pinctrl_lpi2c3>;
> > + status = "okay";
> > +
> > + pcf2131: rtc@53 {
> > + compatible = "nxp,pcf2131";
> > + reg = <0x53>;
> > + interrupt-parent = <&pcal6524>;
> > + interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
>
> Fix indentation.
Thanks for your comment.
Yeah, will fix it.
BR
Joy Zou
>
> Best regards,
> Krzysztof
^ permalink raw reply
* [PATCH v3 0/1] Add rtc PCF2131 support
From: Joy Zou @ 2024-04-10 7:01 UTC (permalink / raw)
To: ping.bai, robh+dt, krzysztof.kozlowski+dt, conor+dt, shawnguo,
s.hauer
Cc: kernel, festevam, linux-imx, devicetree, imx, linux-arm-kernel,
linux-kernel
The patchset supports RTC PCF2131 on board dts.
For the details, please check the patch commit log.
Joy Zou (1):
arm64: dts: imx93-11x11-evk: add rtc PCF2131 support
.../boot/dts/freescale/imx93-11x11-evk.dts | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
--
2.37.1
^ permalink raw reply
* [PATCH v3 1/1] arm64: dts: imx93-11x11-evk: add rtc PCF2131 support
From: Joy Zou @ 2024-04-10 7:01 UTC (permalink / raw)
To: ping.bai, robh+dt, krzysztof.kozlowski+dt, conor+dt, shawnguo,
s.hauer
Cc: kernel, festevam, linux-imx, devicetree, imx, linux-arm-kernel,
linux-kernel
In-Reply-To: <20240410070128.1506555-1-joy.zou@nxp.com>
Support rtc PCF2131 on imx93-11x11-evk.
Signed-off-by: Joy Zou <joy.zou@nxp.com>
---
Changes in v3:
1.adjust the indentation.
Changes in v2:
1. remove unnecessary status property.
---
.../boot/dts/freescale/imx93-11x11-evk.dts | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
index 07e85a30a25f..73e0bca36b81 100644
--- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
@@ -281,6 +281,23 @@ ldo5: LDO5 {
};
};
+&lpi2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ pinctrl-1 = <&pinctrl_lpi2c3>;
+ status = "okay";
+
+ pcf2131: rtc@53 {
+ compatible = "nxp,pcf2131";
+ reg = <0x53>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
@@ -343,6 +360,13 @@ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
};
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
+ MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
+ >;
+ };
+
pinctrl_pcal6524: pcal6524grp {
fsl,pins = <
MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
--
2.37.1
^ permalink raw reply related
* Re: [PATCH v2 5/7] dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY
From: Krzysztof Kozlowski @ 2024-04-10 6:59 UTC (permalink / raw)
To: mr.nuke.me, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <33461c22-21a3-023b-4750-c69304471ea8@gmail.com>
On 09/04/2024 22:19, mr.nuke.me@gmail.com wrote:
>>
>>
>>>
>>> clock-names:
>>> items:
>>> - const: aux
>>> - const: cfg_ahb
>>> - const: pipe
>>> + - const: anoc
>>> + - const: snoc
>>
>> OK, you did not test it. Neither this, nor DTS. I stop review, please
>> test first.
>
> I ran both `checkpatch.pl` and `make dt_binding_check`. What in this
> patch makes you say I "did not test it", and what test or tests did I miss?
>
... and no, you did not. If you tested, you would easily see error:
clock-names: ['aux', 'cfg_ahb', 'pipe'] is too short
When you receive comment from reviewer, please investigate thoroughly
what could get wrong. Don't answer just to get rid of reviewer. It's
fine to make mistakes, but if reviewer points to issue and you
immediately respond "no issue", that's waste of my time.
Look at entire code of qcom,pcie how it is organized. Or:
https://elixir.bootlin.com/linux/v6.8/source/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml#L132
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 5/7] dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY
From: Krzysztof Kozlowski @ 2024-04-10 7:02 UTC (permalink / raw)
To: mr.nuke.me, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <2379377e-ca1c-453f-bb74-186ab738ce39@linaro.org>
On 10/04/2024 08:59, Krzysztof Kozlowski wrote:
> On 09/04/2024 22:19, mr.nuke.me@gmail.com wrote:
>>>
>>>
>>>>
>>>> clock-names:
>>>> items:
>>>> - const: aux
>>>> - const: cfg_ahb
>>>> - const: pipe
>>>> + - const: anoc
>>>> + - const: snoc
>>>
>>> OK, you did not test it. Neither this, nor DTS. I stop review, please
>>> test first.
>>
>> I ran both `checkpatch.pl` and `make dt_binding_check`. What in this
>> patch makes you say I "did not test it", and what test or tests did I miss?
>>
>
> ... and no, you did not. If you tested, you would easily see error:
> clock-names: ['aux', 'cfg_ahb', 'pipe'] is too short
>
> When you receive comment from reviewer, please investigate thoroughly
> what could get wrong. Don't answer just to get rid of reviewer. It's
> fine to make mistakes, but if reviewer points to issue and you
> immediately respond "no issue", that's waste of my time.
To clarify: "no issue" response is waste of my time. If you responded
"oh, I see the error, but I don't know how to fix it", it would be ok, I
can clarify and help in this.
Best regards,
Krzysztof
^ permalink raw reply
* RE: [PATCH v8 4/4] pinctrl: Implementation of the generic scmi-pinctrl driver
From: Peng Fan @ 2024-04-10 7:06 UTC (permalink / raw)
To: Peng Fan (OSS), Sudeep Holla, Cristian Marussi, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij, Dan Carpenter
Cc: Andy Shevchenko, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org, Oleksii Moisieiev
In-Reply-To: <DU0PR04MB941754A6D751E80840F9A79888012@DU0PR04MB9417.eurprd04.prod.outlook.com>
Hi Linus,
> Subject: RE: [PATCH v8 4/4] pinctrl: Implementation of the generic scmi-
> pinctrl driver
>
> > Subject: [PATCH v8 4/4] pinctrl: Implementation of the generic
> > scmi-pinctrl driver
> >
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > scmi-pinctrl driver implements pinctrl driver interface and using SCMI
> > protocol to redirect messages from pinctrl subsystem SDK to SCMI
> > platform firmware, which does the changes in HW.
>
> Considering pinctrl expects ENOTSUPP, so I would add this in v9.
>
> diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c index
> 0f55f000a679..accebe3f0706 100644
> --- a/drivers/pinctrl/pinctrl-scmi.c
> +++ b/drivers/pinctrl/pinctrl-scmi.c
> @@ -296,8 +296,12 @@ static int pinctrl_scmi_pinconf_get(struct
> pinctrl_dev *pctldev,
>
> ret = pinctrl_ops->settings_get_one(pmx->ph, pin, PIN_TYPE, type,
> &config_value);
> - if (ret)
> + if (ret) {
> + /* Convert SCMI error code to PINCTRL expected error code */
> + if (ret == -EOPNOTSUPP)
> + ret = -ENOTSUPP;
> return ret;
> + }
>
> *config = pinconf_to_config_packed(config_type, config_value);
>
> @@ -445,8 +449,12 @@ static int pinctrl_scmi_pinconf_group_get(struct
> pinctrl_dev *pctldev,
>
> ret = pinctrl_ops->settings_get_one(pmx->ph, group, GROUP_TYPE, type,
> &config_value);
> - if (ret)
> + if (ret) {
> + /* Convert SCMI error code to PINCTRL expected error code */
> + if (ret == -EOPNOTSUPP)
> + ret = -ENOTSUPP;
> return ret;
> + }
>
> *config = pinconf_to_config_packed(config_type, config_value);
I just rebased to linux-next and found the patch
"pinctrl: pinconf-generic: check error value EOPNOTSUPP" is there, not
removed.
Do I still need to convert the error number from EOPNOTSUPP to
ENOTSUPP in pinctrl-scmi.c?
Thanks,
Peng.
>
> I will collect more comments before post v9. Just post out upper diff to see
> any disagreements.
>
> Thanks,
> Peng.
> >
> > Co-developed-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
> > Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> > MAINTAINERS | 1 +
> > drivers/pinctrl/Kconfig | 11 +
> > drivers/pinctrl/Makefile | 1 +
> > drivers/pinctrl/pinctrl-scmi.c | 564
> > +++++++++++++++++++++++++++++++++++++++++
> > 4 files changed, 577 insertions(+)
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS index
> > 4b511a55101c..d8270ac6651a 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -21457,6 +21457,7 @@ F: drivers/cpufreq/sc[mp]i-cpufreq.c
> > F: drivers/firmware/arm_scmi/
> > F: drivers/firmware/arm_scpi.c
> > F: drivers/hwmon/scmi-hwmon.c
> > +F: drivers/pinctrl/pinctrl-scmi.c
> > F: drivers/pmdomain/arm/
> > F: drivers/powercap/arm_scmi_powercap.c
> > F: drivers/regulator/scmi-regulator.c
> > diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index
> > d45657aa986a..4e6f65cf0e76 100644
> > --- a/drivers/pinctrl/Kconfig
> > +++ b/drivers/pinctrl/Kconfig
> > @@ -450,6 +450,17 @@ config PINCTRL_ROCKCHIP
> > help
> > This support pinctrl and GPIO driver for Rockchip SoCs.
> >
> > +config PINCTRL_SCMI
> > + tristate "Pinctrl driver using SCMI protocol interface"
> > + depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
> > + select PINMUX
> > + select GENERIC_PINCONF
> > + help
> > + This driver provides support for pinctrl which is controlled
> > + by firmware that implements the SCMI interface.
> > + It uses SCMI Message Protocol to interact with the
> > + firmware providing all the pinctrl controls.
> > +
> > config PINCTRL_SINGLE
> > tristate "One-register-per-pin type device tree based pinctrl driver"
> > depends on OF
> > diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index
> > 2152539b53d5..cc809669405a 100644
> > --- a/drivers/pinctrl/Makefile
> > +++ b/drivers/pinctrl/Makefile
> > @@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
> > obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
> > obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
> > obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
> > +obj-$(CONFIG_PINCTRL_SCMI) += pinctrl-scmi.o
> > obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
> > obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
> > obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
> > diff --git a/drivers/pinctrl/pinctrl-scmi.c
> > b/drivers/pinctrl/pinctrl-scmi.c new file mode 100644 index
> > 000000000000..0f55f000a679
> > --- /dev/null
> > +++ b/drivers/pinctrl/pinctrl-scmi.c
> > @@ -0,0 +1,564 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * System Control and Power Interface (SCMI) Protocol based pinctrl
> > +driver
> > + *
> > + * Copyright (C) 2024 EPAM
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#include <linux/device.h>
> > +#include <linux/dev_printk.h>
> > +#include <linux/err.h>
> > +#include <linux/module.h>
> > +#include <linux/scmi_protocol.h>
> > +#include <linux/slab.h>
> > +#include <linux/types.h>
> > +
> > +#include <linux/pinctrl/machine.h>
> > +#include <linux/pinctrl/pinconf.h>
> > +#include <linux/pinctrl/pinconf-generic.h> #include
> > +<linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h>
> > +
> > +#include "pinctrl-utils.h"
> > +#include "core.h"
> > +#include "pinconf.h"
> > +
> > +#define DRV_NAME "scmi-pinctrl"
> > +
> > +/* Define num configs, if not large than 4 use stack, else use kcalloc */
> > +#define SCMI_NUM_CONFIGS 4
> > +
> > +static const struct scmi_pinctrl_proto_ops *pinctrl_ops;
> > +
> > +struct scmi_pinctrl {
> > + struct device *dev;
> > + struct scmi_protocol_handle *ph;
> > + struct pinctrl_dev *pctldev;
> > + struct pinctrl_desc pctl_desc;
> > + struct pinfunction *functions;
> > + unsigned int nr_functions;
> > + struct pinctrl_pin_desc *pins;
> > + unsigned int nr_pins;
> > +};
> > +
> > +static int pinctrl_scmi_get_groups_count(struct pinctrl_dev *pctldev) {
> > + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> > +
> > + return pinctrl_ops->count_get(pmx->ph, GROUP_TYPE); }
> > +
> > +static const char *pinctrl_scmi_get_group_name(struct pinctrl_dev
> *pctldev,
> > + unsigned int selector)
> > +{
> > + int ret;
> > + const char *name;
> > + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> > +
> > + ret = pinctrl_ops->name_get(pmx->ph, selector, GROUP_TYPE,
> > &name);
> > + if (ret) {
> > + dev_err(pmx->dev, "get name failed with err %d", ret);
> > + return NULL;
> > + }
> > +
> > + return name;
> > +}
> > +
> > +static int pinctrl_scmi_get_group_pins(struct pinctrl_dev *pctldev,
> > + unsigned int selector,
> > + const unsigned int **pins,
> > + unsigned int *num_pins)
> > +{
> > + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> > +
> > + return pinctrl_ops->group_pins_get(pmx->ph, selector, pins,
> > num_pins);
> > +}
> > +
> > +static const struct pinctrl_ops pinctrl_scmi_pinctrl_ops = {
> > + .get_groups_count = pinctrl_scmi_get_groups_count,
> > + .get_group_name = pinctrl_scmi_get_group_name,
> > + .get_group_pins = pinctrl_scmi_get_group_pins, #ifdef CONFIG_OF
> > + .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
> > + .dt_free_map = pinconf_generic_dt_free_map, #endif };
> > +
> > +static int pinctrl_scmi_get_functions_count(struct pinctrl_dev
> > +*pctldev) {
> > + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> > +
> > + return pinctrl_ops->count_get(pmx->ph, FUNCTION_TYPE); }
> > +
> > +static const char *pinctrl_scmi_get_function_name(struct pinctrl_dev
> > *pctldev,
> > + unsigned int selector)
> > +{
> > + int ret;
> > + const char *name;
> > + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> > +
> > + ret = pinctrl_ops->name_get(pmx->ph, selector, FUNCTION_TYPE,
> > &name);
> > + if (ret) {
> > + dev_err(pmx->dev, "get name failed with err %d", ret);
> > + return NULL;
> > + }
> > +
> > + return name;
> > +}
> > +
> > +static int pinctrl_scmi_get_function_groups(struct pinctrl_dev *pctldev,
> > + unsigned int selector,
> > + const char * const **p_groups,
> > + unsigned int * const
> > p_num_groups) {
> > + struct pinfunction *func;
> > + const unsigned int *group_ids;
> > + unsigned int num_groups;
> > + const char **groups;
> > + int ret, i;
> > + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> > +
> > + if (!p_groups || !p_num_groups)
> > + return -EINVAL;
> > +
> > + if (selector >= pmx->nr_functions)
> > + return -EINVAL;
> > +
> > + func = &pmx->functions[selector];
> > + if (func->ngroups)
> > + goto done;
> > +
> > + ret = pinctrl_ops->function_groups_get(pmx->ph, selector,
> > &num_groups,
> > + &group_ids);
> > + if (ret) {
> > + dev_err(pmx->dev, "Unable to get function groups, err %d",
> > ret);
> > + return ret;
> > + }
> > + if (!num_groups)
> > + return -EINVAL;
> > +
> > + groups = kcalloc(num_groups, sizeof(*groups), GFP_KERNEL);
> > + if (!groups)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < num_groups; i++) {
> > + groups[i] = pinctrl_scmi_get_group_name(pctldev,
> > group_ids[i]);
> > + if (!groups[i]) {
> > + ret = -EINVAL;
> > + goto err_free;
> > + }
> > + }
> > +
> > + func->ngroups = num_groups;
> > + func->groups = groups;
> > +done:
> > + *p_groups = func->groups;
> > + *p_num_groups = func->ngroups;
> > +
> > + return 0;
> > +
> > +err_free:
> > + kfree(groups);
> > +
> > + return ret;
> > +}
> > +
> > +static int pinctrl_scmi_func_set_mux(struct pinctrl_dev *pctldev,
> > + unsigned int selector, unsigned int group)
> > {
> > + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> > +
> > + return pinctrl_ops->mux_set(pmx->ph, selector, group); }
> > +
> > +static int pinctrl_scmi_request(struct pinctrl_dev *pctldev,
> > + unsigned int offset)
> > +{
> > + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> > +
> > + return pinctrl_ops->pin_request(pmx->ph, offset); }
> > +
> > +static int pinctrl_scmi_free(struct pinctrl_dev *pctldev, unsigned
> > +int
> > +offset) {
> > + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> > +
> > + return pinctrl_ops->pin_free(pmx->ph, offset); }
> > +
> > +static const struct pinmux_ops pinctrl_scmi_pinmux_ops = {
> > + .request = pinctrl_scmi_request,
> > + .free = pinctrl_scmi_free,
> > + .get_functions_count = pinctrl_scmi_get_functions_count,
> > + .get_function_name = pinctrl_scmi_get_function_name,
> > + .get_function_groups = pinctrl_scmi_get_function_groups,
> > + .set_mux = pinctrl_scmi_func_set_mux, };
> > +
> > +static int pinctrl_scmi_map_pinconf_type(enum pin_config_param param,
> > + enum scmi_pinctrl_conf_type
> > *type) {
> > + u32 arg = param;
> > +
> > + switch (arg) {
> > + case PIN_CONFIG_BIAS_BUS_HOLD:
> > + *type = SCMI_PIN_BIAS_BUS_HOLD;
> > + break;
> > + case PIN_CONFIG_BIAS_DISABLE:
> > + *type = SCMI_PIN_BIAS_DISABLE;
> > + break;
> > + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
> > + *type = SCMI_PIN_BIAS_HIGH_IMPEDANCE;
> > + break;
> > + case PIN_CONFIG_BIAS_PULL_DOWN:
> > + *type = SCMI_PIN_BIAS_PULL_DOWN;
> > + break;
> > + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
> > + *type = SCMI_PIN_BIAS_PULL_DEFAULT;
> > + break;
> > + case PIN_CONFIG_BIAS_PULL_UP:
> > + *type = SCMI_PIN_BIAS_PULL_UP;
> > + break;
> > + case PIN_CONFIG_DRIVE_OPEN_DRAIN:
> > + *type = SCMI_PIN_DRIVE_OPEN_DRAIN;
> > + break;
> > + case PIN_CONFIG_DRIVE_OPEN_SOURCE:
> > + *type = SCMI_PIN_DRIVE_OPEN_SOURCE;
> > + break;
> > + case PIN_CONFIG_DRIVE_PUSH_PULL:
> > + *type = SCMI_PIN_DRIVE_PUSH_PULL;
> > + break;
> > + case PIN_CONFIG_DRIVE_STRENGTH:
> > + *type = SCMI_PIN_DRIVE_STRENGTH;
> > + break;
> > + case PIN_CONFIG_DRIVE_STRENGTH_UA:
> > + *type = SCMI_PIN_DRIVE_STRENGTH;
> > + break;
> > + case PIN_CONFIG_INPUT_DEBOUNCE:
> > + *type = SCMI_PIN_INPUT_DEBOUNCE;
> > + break;
> > + case PIN_CONFIG_INPUT_ENABLE:
> > + *type = SCMI_PIN_INPUT_MODE;
> > + break;
> > + case PIN_CONFIG_INPUT_SCHMITT:
> > + *type = SCMI_PIN_INPUT_SCHMITT;
> > + break;
> > + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
> > + *type = SCMI_PIN_INPUT_MODE;
> > + break;
> > + case PIN_CONFIG_MODE_LOW_POWER:
> > + *type = SCMI_PIN_LOW_POWER_MODE;
> > + break;
> > + case PIN_CONFIG_OUTPUT:
> > + *type = SCMI_PIN_OUTPUT_VALUE;
> > + break;
> > + case PIN_CONFIG_OUTPUT_ENABLE:
> > + *type = SCMI_PIN_OUTPUT_MODE;
> > + break;
> > + case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS:
> > + *type = SCMI_PIN_OUTPUT_VALUE;
> > + break;
> > + case PIN_CONFIG_POWER_SOURCE:
> > + *type = SCMI_PIN_POWER_SOURCE;
> > + break;
> > + case PIN_CONFIG_SLEW_RATE:
> > + *type = SCMI_PIN_SLEW_RATE;
> > + break;
> > + case SCMI_PIN_OEM_START ... SCMI_PIN_OEM_END:
> > + *type = arg;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int pinctrl_scmi_pinconf_get(struct pinctrl_dev *pctldev,
> > + unsigned int pin, unsigned long *config) {
> > + int ret;
> > + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> > + enum pin_config_param config_type;
> > + enum scmi_pinctrl_conf_type type;
> > + u32 config_value;
> > +
> > + if (!config)
> > + return -EINVAL;
> > +
> > + config_type = pinconf_to_config_param(*config);
> > +
> > + ret = pinctrl_scmi_map_pinconf_type(config_type, &type);
> > + if (ret)
> > + return ret;
> > +
> > + ret = pinctrl_ops->settings_get_one(pmx->ph, pin, PIN_TYPE, type,
> > + &config_value);
> > + if (ret)
> > + return ret;
> > +
> > + *config = pinconf_to_config_packed(config_type, config_value);
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +pinctrl_scmi_alloc_configs(struct pinctrl_dev *pctldev, u32 num_configs,
> > + u32 **p_config_value,
> > + enum scmi_pinctrl_conf_type **p_config_type) {
> > + if (num_configs <= SCMI_NUM_CONFIGS)
> > + return 0;
> > +
> > + *p_config_value = kcalloc(num_configs, sizeof(**p_config_value),
> > GFP_KERNEL);
> > + if (!*p_config_value)
> > + return -ENOMEM;
> > +
> > + *p_config_type = kcalloc(num_configs, sizeof(**p_config_type),
> > GFP_KERNEL);
> > + if (!*p_config_type) {
> > + kfree(*p_config_value);
> > + return -ENOMEM;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void
> > +pinctrl_scmi_free_configs(struct pinctrl_dev *pctldev, u32 num_configs,
> > + u32 **p_config_value,
> > + enum scmi_pinctrl_conf_type **p_config_type) {
> > + if (num_configs <= SCMI_NUM_CONFIGS)
> > + return;
> > +
> > + kfree(*p_config_value);
> > + kfree(*p_config_type);
> > +}
> > +
> > +static int pinctrl_scmi_pinconf_set(struct pinctrl_dev *pctldev,
> > + unsigned int pin,
> > + unsigned long *configs,
> > + unsigned int num_configs)
> > +{
> > + int i, ret;
> > + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> > + enum scmi_pinctrl_conf_type config_type[SCMI_NUM_CONFIGS];
> > + u32 config_value[SCMI_NUM_CONFIGS];
> > + enum scmi_pinctrl_conf_type *p_config_type = config_type;
> > + u32 *p_config_value = config_value;
> > + enum pin_config_param param;
> > +
> > + if (!configs || !num_configs)
> > + return -EINVAL;
> > +
> > + ret = pinctrl_scmi_alloc_configs(pctldev, num_configs,
> > &p_config_type,
> > + &p_config_value);
> > + if (ret)
> > + return ret;
> > +
> > + for (i = 0; i < num_configs; i++) {
> > + param = pinconf_to_config_param(configs[i]);
> > + ret = pinctrl_scmi_map_pinconf_type(param,
> > &p_config_type[i]);
> > + if (ret) {
> > + dev_err(pmx->dev, "Error map pinconf_type %d\n",
> > ret);
> > + goto free_config;
> > + }
> > + p_config_value[i] = pinconf_to_config_argument(configs[i]);
> > + }
> > +
> > + ret = pinctrl_ops->settings_conf(pmx->ph, pin, PIN_TYPE,
> > num_configs,
> > + p_config_type, p_config_value);
> > + if (ret)
> > + dev_err(pmx->dev, "Error parsing config %d\n", ret);
> > +
> > +free_config:
> > + pinctrl_scmi_free_configs(pctldev, num_configs, &p_config_type,
> > + &p_config_value);
> > + return ret;
> > +}
> > +
> > +static int pinctrl_scmi_pinconf_group_set(struct pinctrl_dev *pctldev,
> > + unsigned int group,
> > + unsigned long *configs,
> > + unsigned int num_configs)
> > +{
> > + int i, ret;
> > + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> > + enum scmi_pinctrl_conf_type config_type[SCMI_NUM_CONFIGS];
> > + u32 config_value[SCMI_NUM_CONFIGS];
> > + enum scmi_pinctrl_conf_type *p_config_type = config_type;
> > + u32 *p_config_value = config_value;
> > + enum pin_config_param param;
> > +
> > + if (!configs || !num_configs)
> > + return -EINVAL;
> > +
> > + ret = pinctrl_scmi_alloc_configs(pctldev, num_configs,
> > &p_config_type,
> > + &p_config_value);
> > + if (ret)
> > + return ret;
> > +
> > + for (i = 0; i < num_configs; i++) {
> > + param = pinconf_to_config_param(configs[i]);
> > + ret = pinctrl_scmi_map_pinconf_type(param,
> > &p_config_type[i]);
> > + if (ret) {
> > + dev_err(pmx->dev, "Error map pinconf_type %d\n",
> > ret);
> > + goto free_config;
> > + }
> > +
> > + p_config_value[i] = pinconf_to_config_argument(configs[i]);
> > + }
> > +
> > + ret = pinctrl_ops->settings_conf(pmx->ph, group, GROUP_TYPE,
> > + num_configs, p_config_type,
> > + p_config_value);
> > + if (ret)
> > + dev_err(pmx->dev, "Error parsing config %d", ret);
> > +
> > +free_config:
> > + pinctrl_scmi_free_configs(pctldev, num_configs, &p_config_type,
> > + &p_config_value);
> > + return ret;
> > +};
> > +
> > +static int pinctrl_scmi_pinconf_group_get(struct pinctrl_dev *pctldev,
> > + unsigned int group,
> > + unsigned long *config)
> > +{
> > + int ret;
> > + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
> > + enum pin_config_param config_type;
> > + enum scmi_pinctrl_conf_type type;
> > + u32 config_value;
> > +
> > + if (!config)
> > + return -EINVAL;
> > +
> > + config_type = pinconf_to_config_param(*config);
> > + ret = pinctrl_scmi_map_pinconf_type(config_type, &type);
> > + if (ret) {
> > + dev_err(pmx->dev, "Error map pinconf_type %d\n", ret);
> > + return ret;
> > + }
> > +
> > + ret = pinctrl_ops->settings_get_one(pmx->ph, group, GROUP_TYPE,
> > type,
> > + &config_value);
> > + if (ret)
> > + return ret;
> > +
> > + *config = pinconf_to_config_packed(config_type, config_value);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct pinconf_ops pinctrl_scmi_pinconf_ops = {
> > + .is_generic = true,
> > + .pin_config_get = pinctrl_scmi_pinconf_get,
> > + .pin_config_set = pinctrl_scmi_pinconf_set,
> > + .pin_config_group_set = pinctrl_scmi_pinconf_group_set,
> > + .pin_config_group_get = pinctrl_scmi_pinconf_group_get,
> > + .pin_config_config_dbg_show = pinconf_generic_dump_config, };
> > +
> > +static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx,
> > + struct pinctrl_desc *desc)
> > +{
> > + struct pinctrl_pin_desc *pins;
> > + unsigned int npins;
> > + int ret, i;
> > +
> > + npins = pinctrl_ops->count_get(pmx->ph, PIN_TYPE);
> > + /*
> > + * npins will never be zero, the scmi pinctrl driver has bailed out
> > + * if npins is zero.
> > + */
> > + pins = devm_kmalloc_array(pmx->dev, npins, sizeof(*pins),
> > GFP_KERNEL);
> > + if (!pins)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < npins; i++) {
> > + pins[i].number = i;
> > + /*
> > + * The memory for name is handled by the scmi firmware
> > driver,
> > + * no need free here
> > + */
> > + ret = pinctrl_ops->name_get(pmx->ph, i, PIN_TYPE,
> > &pins[i].name);
> > + if (ret)
> > + return dev_err_probe(pmx->dev, ret,
> > + "Can't get name for pin %d", i);
> > + }
> > +
> > + desc->npins = npins;
> > + desc->pins = pins;
> > + dev_dbg(pmx->dev, "got pins %u", npins);
> > +
> > + return 0;
> > +}
> > +
> > +static int scmi_pinctrl_probe(struct scmi_device *sdev) {
> > + int ret;
> > + struct device *dev = &sdev->dev;
> > + struct scmi_pinctrl *pmx;
> > + const struct scmi_handle *handle;
> > + struct scmi_protocol_handle *ph;
> > +
> > + if (!sdev->handle)
> > + return -EINVAL;
> > +
> > + handle = sdev->handle;
> > +
> > + pinctrl_ops = handle->devm_protocol_get(sdev,
> > SCMI_PROTOCOL_PINCTRL, &ph);
> > + if (IS_ERR(pinctrl_ops))
> > + return PTR_ERR(pinctrl_ops);
> > +
> > + pmx = devm_kzalloc(dev, sizeof(*pmx), GFP_KERNEL);
> > + if (!pmx)
> > + return -ENOMEM;
> > +
> > + pmx->ph = ph;
> > +
> > + pmx->dev = dev;
> > + pmx->pctl_desc.name = DRV_NAME;
> > + pmx->pctl_desc.owner = THIS_MODULE;
> > + pmx->pctl_desc.pctlops = &pinctrl_scmi_pinctrl_ops;
> > + pmx->pctl_desc.pmxops = &pinctrl_scmi_pinmux_ops;
> > + pmx->pctl_desc.confops = &pinctrl_scmi_pinconf_ops;
> > +
> > + ret = pinctrl_scmi_get_pins(pmx, &pmx->pctl_desc);
> > + if (ret)
> > + return ret;
> > +
> > + ret = devm_pinctrl_register_and_init(dev, &pmx->pctl_desc, pmx,
> > + &pmx->pctldev);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to register pinctrl\n");
> > +
> > + pmx->nr_functions = pinctrl_scmi_get_functions_count(pmx-
> > >pctldev);
> > + pmx->functions = devm_kcalloc(dev, pmx->nr_functions,
> > + sizeof(*pmx->functions), GFP_KERNEL);
> > + if (!pmx->functions)
> > + return -ENOMEM;
> > +
> > + return pinctrl_enable(pmx->pctldev); }
> > +
> > +static const struct scmi_device_id scmi_id_table[] = {
> > + { SCMI_PROTOCOL_PINCTRL, "pinctrl" },
> > + { }
> > +};
> > +MODULE_DEVICE_TABLE(scmi, scmi_id_table);
> > +
> > +static struct scmi_driver scmi_pinctrl_driver = {
> > + .name = DRV_NAME,
> > + .probe = scmi_pinctrl_probe,
> > + .id_table = scmi_id_table,
> > +};
> > +module_scmi_driver(scmi_pinctrl_driver);
> > +
> > +MODULE_AUTHOR("Oleksii Moisieiev <oleksii_moisieiev@epam.com>");
> > +MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
> > MODULE_DESCRIPTION("ARM
> > +SCMI pin controller driver"); MODULE_LICENSE("GPL");
> >
> > --
> > 2.37.1
^ permalink raw reply
* Re: [PATCH v10 2/4] dt-bindings: stm32: update DT bingding for stm32mp25
From: Krzysztof Kozlowski @ 2024-04-10 7:06 UTC (permalink / raw)
To: gabriel.fernandez, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Philipp Zabel
Cc: linux-clk, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel
In-Reply-To: <20240409171241.274600-3-gabriel.fernandez@foss.st.com>
On 09/04/2024 19:12, gabriel.fernandez@foss.st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
>
A nit, subject: drop second/last, redundant "DT bindings". (plus a
typo...) The "dt-bindings" prefix is already stating that these are
bindings.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
Subject: Everything is an update. Be specific.
> RCC driver uses '.index' to define all parent clocks instead '.names'
> because the use of a name to define a parent clock is prohibited.
> This is ABI change, but the RCC driver has not yet merged, unlike all
> others drivers besides Linux.
>
> Fixes: b5be49db3d47 ("dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform")
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
> ---
>
> Changes in v10:
> - cosmetic change (add change blank line)
> - rename USB2 into USBH to be compliant with last Reference Manuel
>
> Changes in v9:
> - Update DT binding documentation according S.Boyd remarks on RCC driver:
> Don't use '.name' to define a parent but use '.index'
> Then:
> - remove 'clock-names' property
> - Add description of all parent clocks used in RCC driver
>
> v9 was Acked-by: Conor Dooley <conor.dooley@microchip.com>
Please avoid putting full acks somewhere in the changelog. You confuse
people's filters and maybe tooling as well. "v9 was Acked-by Conor
Dooley", so a proper sentence, not "fake" ack, would work for everyone.
With fixes in the subject:
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 0/3] arm64: dts: qcom: Fix the msi-map entries
From: Manivannan Sadhasivam @ 2024-04-10 7:13 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, linux-arm-msm, devicetree, linux-kernel, stable
In-Reply-To: <171254262026.648987.5589442883549909128.b4-ty@kernel.org>
On Sun, Apr 07, 2024 at 09:17:20PM -0500, Bjorn Andersson wrote:
>
> On Mon, 18 Mar 2024 12:49:02 +0530, Manivannan Sadhasivam wrote:
> > While adding the GIC ITS MSI support, it was found that the msi-map entries
> > needed to be swapped to receive MSIs from the endpoint.
> >
> > But later it was identified that the swapping was needed due to a bug in
> > the Qualcomm PCIe controller driver. And since the bug is now fixed with
> > commit bf79e33cdd89 ("PCI: qcom: Enable BDF to SID translation properly"),
> > let's fix the msi-map entries also to reflect the actual mapping in the
> > hardware.
> >
> > [...]
>
> Applied, thanks!
>
> [1/3] arm64: dts: qcom: sm8450: Fix the msi-map entries
> commit: d6c0602429490ff90d3f79a431aec1be779650b7
> [2/3] arm64: dts: qcom: sm8550: Fix the msi-map entries
> commit: 398b7c7dda6792c2646a2208a6cbab02da97d6e5
> [3/3] arm64: dts: qcom: sm8650: Fix the msi-map entries
> commit: 3ac680a514b6e63428481b1e6fb069383e5b7add
>
Can this series applied as fix for 6.9 since the driver patch went in during the
merge window?
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply
* [PATCH v1 0/2] Support BOE nv110wum-l60 and IVO t109nw41 MIPI-DSI panel
From: Cong Yang @ 2024-04-10 7:14 UTC (permalink / raw)
To: sam, neil.armstrong, daniel, dianders, airlied, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: dri-devel, devicetree, linux-kernel, Cong Yang
BOE nv110wum-l60 and IVO t109nw41 both 11.0" WUXGA TFT LCD panel,
which fits in nicely with the existing panel-boe-tv101wum-nl6 driver.
Add compatible for BOE nv110wum-l60 and IVO t109nw41
in dt-bindings.
Cong Yang (4):
dt-bindings: display: panel: Add compatible for BOE nv110wum-l60
drm/panel: boe-tv101wum-nl6: Support for BOE nv110wum-l60 MIPI-DSI
panel
dt-bindings: display: panel: Add compatible for IVO t109nw41
drm/panel: boe-tv101wum-nl6: Support for IVO t109nw41 MIPI-DSI panel
.../display/panel/boe,tv101wum-nl6.yaml | 4 +
.../gpu/drm/panel/panel-boe-tv101wum-nl6.c | 213 ++++++++++++++++++
2 files changed, 217 insertions(+)
--
2.25.1
^ permalink raw reply
* [PATCH v1 1/4] dt-bindings: display: panel: Add compatible for BOE nv110wum-l60
From: Cong Yang @ 2024-04-10 7:14 UTC (permalink / raw)
To: sam, neil.armstrong, daniel, dianders, airlied, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: dri-devel, devicetree, linux-kernel, Cong Yang
In-Reply-To: <20240410071439.2152588-1-yangcong5@huaqin.corp-partner.google.com>
The BOE nv110wum-l60 is a 11.0" WUXGA TFT LCD panel, which fits in nicely
with the existing panel-boe-tv101wum-nl6 driver. Hence, we add a new
compatible with panel specific config.
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
---
.../devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml
index 906ef62709b8..50351dd3d6e5 100644
--- a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml
+++ b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml
@@ -36,6 +36,8 @@ properties:
- starry,himax83102-j02
# STARRY ili9882t 10.51" WUXGA TFT LCD panel
- starry,ili9882t
+ # Boe nv110wum-l60 11.0" WUXGA TFT LCD panel
+ - boe,nv110wum-l60
reg:
description: the virtual channel number of a DSI peripheral
--
2.25.1
^ permalink raw reply related
* [PATCH v1 2/4] drm/panel: boe-tv101wum-nl6: Support for BOE nv110wum-l60 MIPI-DSI panel
From: Cong Yang @ 2024-04-10 7:14 UTC (permalink / raw)
To: sam, neil.armstrong, daniel, dianders, airlied, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: dri-devel, devicetree, linux-kernel, Cong Yang
In-Reply-To: <20240410071439.2152588-1-yangcong5@huaqin.corp-partner.google.com>
The BOE nv110wum-l60 is a 11.0" WUXGA TFT LCD panel, which fits in nicely
with the existing panel-boe-tv101wum-nl6 driver. Hence, we add a new
compatible with panel specific config.
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
---
.../gpu/drm/panel/panel-boe-tv101wum-nl6.c | 115 ++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index 0ffe8f8c01de..f91827e1548c 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -1368,6 +1368,91 @@ static const struct panel_init_cmd starry_himax83102_j02_init_cmd[] = {
{},
};
+static const struct panel_init_cmd boe_nv110wum_init_cmd[] = {
+ _INIT_DELAY_CMD(60),
+ _INIT_DCS_CMD(0xB9, 0x83, 0x10, 0x21, 0x55, 0x00),
+ _INIT_DCS_CMD(0xB1, 0x2C, 0xAF, 0xAF, 0x2B, 0xEB, 0x42, 0xE1, 0x4D, 0x36, 0x36, 0x36, 0x36, 0x1A, 0x8B, 0x11, 0x65, 0x00, 0x88, 0xFA, 0xFF, 0xFF, 0x8F, 0xFF, 0x08, 0x9A, 0x33),
+ _INIT_DCS_CMD(0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x12, 0x71, 0x3C, 0xA3, 0x11, 0x00, 0x00, 0x00, 0x88, 0xF5, 0x22, 0x8F),
+ _INIT_DCS_CMD(0xB4, 0x49, 0x49, 0x32, 0x32, 0x14, 0x32, 0x84, 0x6E, 0x84, 0x6E, 0x01, 0x9C),
+ _INIT_DCS_CMD(0xE9, 0xCD),
+ _INIT_DCS_CMD(0xBA, 0x84),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+
+ _INIT_DCS_CMD(0xBC, 0x1B, 0x04),
+ _INIT_DCS_CMD(0xBE, 0x20),
+ _INIT_DCS_CMD(0xBF, 0xFC, 0x84),
+
+ _INIT_DCS_CMD(0xC0, 0x36, 0x36, 0x22, 0x00, 0x00, 0xA0, 0x61, 0x08, 0xF5, 0x03),
+ _INIT_DCS_CMD(0xE9, 0xCC),
+ _INIT_DCS_CMD(0xC7, 0x80),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+ _INIT_DCS_CMD(0xE9, 0xC6),
+ _INIT_DCS_CMD(0xC8, 0x97),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+
+ _INIT_DCS_CMD(0xC9, 0x00, 0x1E, 0x30, 0xD4, 0x01),
+ _INIT_DCS_CMD(0xCB, 0x08, 0x13, 0x07, 0x00, 0x0F, 0x34),
+ _INIT_DCS_CMD(0xCC, 0x02, 0x03, 0x44),
+ _INIT_DCS_CMD(0xE9, 0xC4),
+ _INIT_DCS_CMD(0xD0, 0x03),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+ _INIT_DCS_CMD(0xD1, 0x37, 0x06, 0x00, 0x02, 0x04, 0x0C, 0xFF),
+ _INIT_DCS_CMD(0xD2, 0x1F, 0x11, 0x1F, 0x11),
+
+ _INIT_DCS_CMD(0xD3, 0x06, 0x00, 0x00, 0x00, 0x00, 0x04, 0x08, 0x04, 0x08, 0x37, 0x37, 0x64, 0x4B, 0x11, 0x11, 0x03, 0x03, 0x32, 0x10, 0x0E, 0x00, 0x0E, 0x32, 0x10, 0x0A, 0x00, 0x0A, 0x32,
+ 0x17, 0x98, 0x07, 0x98, 0x00, 0x00),
+ _INIT_DCS_CMD(0xD5, 0x18, 0x18, 0x18, 0x18, 0x1E, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F, 0x1F, 0x24, 0x24, 0x24, 0x24, 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 0x05, 0x04, 0x03, 0x02, 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18),
+ _INIT_DCS_CMD(0xD8, 0xAF, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0xAF, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0),
+
+ _INIT_DCS_CMD(0xE0, 0x00, 0x05, 0x0D, 0x14, 0x1B, 0x2C, 0x44, 0x49, 0x51, 0x4C, 0x67, 0x6C, 0x71, 0x80, 0x7D, 0x84, 0x8D, 0xA0, 0xA0, 0x4F, 0x58, 0x64, 0x73, 0x00, 0x05, 0x0D, 0x14, 0x1B, 0x2C, 0x44, 0x49, 0x51, 0x4C, 0x67, 0x6C, 0x71, 0x80, 0x7D, 0x84, 0x8D, 0xA0, 0xA0, 0x4F, 0x58, 0x64, 0x73),
+ _INIT_DCS_CMD(0xE7, 0x07, 0x10, 0x10, 0x1A, 0x26, 0x9E, 0x00, 0x53, 0x9B, 0x14, 0x14),
+ _INIT_DCS_CMD(0xE1, 0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 0x07, 0x80, 0x02, 0x58, 0x00, 0x14, 0x02, 0x58, 0x02, 0x58, 0x02, 0x00, 0x02, 0x2C, 0x00, 0x20, 0x02, 0x02, 0x00, 0x08, 0x00, 0x0C,
+ 0x05, 0x0E, 0x04, 0x94, 0x18, 0x00, 0x10, 0xF0, 0x03, 0x0C, 0x20, 0x00, 0x06, 0x0B, 0x0B, 0x33, 0x0E),
+ _INIT_DCS_CMD(0xBD, 0x01),
+ _INIT_DCS_CMD(0xD8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xA0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xA0),
+ _INIT_DCS_CMD(0xB1, 0x01, 0xBF, 0x11),
+ _INIT_DCS_CMD(0xCB, 0x86),
+ _INIT_DCS_CMD(0xD2, 0x96),
+ _INIT_DCS_CMD(0xE9, 0xC9),
+ _INIT_DCS_CMD(0xD3, 0x84),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+ _INIT_DCS_CMD(0xE9, 0xD1),
+ _INIT_DCS_CMD(0xE1, 0xF6, 0x2B, 0x34, 0x2B, 0x74, 0x3B, 0x74, 0x6B, 0x74),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+
+ _INIT_DCS_CMD(0xE7, 0x02, 0x00, 0x2B, 0x01, 0x7E, 0x0F, 0x7E, 0x10, 0xA0, 0x00, 0x00),
+ _INIT_DCS_CMD(0xBD, 0x02),
+ _INIT_DCS_CMD(0xB4, 0x02, 0x00, 0xBB, 0x11),
+ _INIT_DCS_CMD(0xD8, 0xFF, 0xAF, 0xFF, 0xFF, 0xFA, 0xA0, 0xFF, 0xAF, 0xFF, 0xFF, 0xFA, 0xA0),
+ _INIT_DCS_CMD(0xE7, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, 0x20, 0x65, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00),
+
+ _INIT_DCS_CMD(0xBD, 0x03),
+ _INIT_DCS_CMD(0xD8, 0xAA, 0xAF, 0xAA, 0xAA, 0xA0, 0x00, 0xAA, 0xAF, 0xAA, 0xAA, 0xA0, 0x00, 0xAA, 0xAF, 0xAA, 0xAA, 0xA0, 0x00, 0xAA, 0xAF, 0xAA, 0xAA, 0xA0, 0x00),
+ _INIT_DCS_CMD(0xE9, 0xC6),
+ _INIT_DCS_CMD(0xB4, 0x03, 0xFF, 0xF8),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+ _INIT_DCS_CMD(0xE1, 0x00),
+
+ _INIT_DCS_CMD(0xBD, 0x00),
+ _INIT_DCS_CMD(0xE9, 0xC4),
+ _INIT_DCS_CMD(0xBA, 0x96),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+
+ _INIT_DCS_CMD(0xBD, 0x01),
+ _INIT_DCS_CMD(0xE9, 0xC5),
+ _INIT_DCS_CMD(0xBA, 0x4F),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+
+ _INIT_DCS_CMD(0xBD, 0x00),
+
+ _INIT_DCS_CMD(0xB9, 0x00, 0x00, 0x00),
+ _INIT_DELAY_CMD(50),
+ _INIT_DCS_CMD(0x11),
+ _INIT_DELAY_CMD(110),
+ _INIT_DCS_CMD(0x29),
+ _INIT_DELAY_CMD(25),
+ {},
+};
static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
{
return container_of(panel, struct boe_panel, base);
@@ -1795,6 +1880,33 @@ static const struct panel_desc starry_himax83102_j02_desc = {
.lp11_before_reset = true,
};
+static const struct drm_display_mode boe_tv110wum_default_mode = {
+ .clock = 166400,
+ .hdisplay = 1200,
+ .hsync_start = 1200 + 65,
+ .hsync_end = 1200 + 65 + 20,
+ .htotal = 1200 + 65 + 20 + 65,
+ .vdisplay = 1920,
+ .vsync_start = 1920 + 115,
+ .vsync_end = 1920 + 115 + 8,
+ .vtotal = 1920 + 115 + 8 + 12,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct panel_desc boe_nv110wum_desc = {
+ .modes = &boe_tv110wum_default_mode,
+ .bpc = 8,
+ .size = {
+ .width_mm = 147,
+ .height_mm = 235,
+ },
+ .lanes = 4,
+ .format = MIPI_DSI_FMT_RGB888,
+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_LPM,
+ .init_cmds = boe_nv110wum_init_cmd,
+ .lp11_before_reset = true,
+};
static int boe_panel_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
@@ -1973,6 +2085,9 @@ static const struct of_device_id boe_of_match[] = {
{ .compatible = "starry,himax83102-j02",
.data = &starry_himax83102_j02_desc
},
+ { .compatible = "boe,nv110wum-l60",
+ .data = &boe_nv110wum_desc
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, boe_of_match);
--
2.25.1
^ permalink raw reply related
* [PATCH v1 3/4] dt-bindings: display: panel: Add compatible for IVO t109nw41
From: Cong Yang @ 2024-04-10 7:14 UTC (permalink / raw)
To: sam, neil.armstrong, daniel, dianders, airlied, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: dri-devel, devicetree, linux-kernel, Cong Yang
In-Reply-To: <20240410071439.2152588-1-yangcong5@huaqin.corp-partner.google.com>
The IVO t109nw41 is a 11.0" WUXGA TFT LCD panel, which fits in nicely with
the existing panel-boe-tv101wum-nl6 driver. Hence, we add a new compatible
with panel specific config.
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
---
.../devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml
index 50351dd3d6e5..f15588a2641c 100644
--- a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml
+++ b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml
@@ -38,6 +38,8 @@ properties:
- starry,ili9882t
# Boe nv110wum-l60 11.0" WUXGA TFT LCD panel
- boe,nv110wum-l60
+ # Ivo t109nw41 11.0" WUXGA TFT LCD panel
+ - ivo,t109nw41
reg:
description: the virtual channel number of a DSI peripheral
--
2.25.1
^ permalink raw reply related
* [PATCH v1 4/4] drm/panel: boe-tv101wum-nl6: Support for IVO t109nw41 MIPI-DSI panel
From: Cong Yang @ 2024-04-10 7:14 UTC (permalink / raw)
To: sam, neil.armstrong, daniel, dianders, airlied, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: dri-devel, devicetree, linux-kernel, Cong Yang
In-Reply-To: <20240410071439.2152588-1-yangcong5@huaqin.corp-partner.google.com>
The IVO t109nw41 is a 11.0" WUXGA TFT LCD panel, which fits in nicely with
the existing panel-boe-tv101wum-nl6 driver. Hence, we add a new compatible
with panel specific config.
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
---
.../gpu/drm/panel/panel-boe-tv101wum-nl6.c | 98 +++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index f91827e1548c..201a82415e1e 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -1453,6 +1453,72 @@ static const struct panel_init_cmd boe_nv110wum_init_cmd[] = {
_INIT_DELAY_CMD(25),
{},
};
+
+static const struct panel_init_cmd ivo_t109nw41_init_cmd[] = {
+ _INIT_DELAY_CMD(60),
+ _INIT_DCS_CMD(0xB9, 0x83, 0x10, 0x21, 0x55, 0x00),
+ _INIT_DCS_CMD(0xB1, 0x2C, 0xED, 0xED, 0x27, 0xE7, 0x42, 0xF5, 0x39, 0x36, 0x36, 0x36, 0x36, 0x32, 0x8B, 0x11, 0x65, 0x00, 0x88, 0xFA, 0xFF, 0xFF, 0x8F, 0xFF, 0x08, 0xD6, 0x33),
+ _INIT_DCS_CMD(0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x12, 0x71, 0x3C, 0xA3, 0x22, 0x20, 0x00, 0x00, 0x88, 0x01),
+ _INIT_DCS_CMD(0xB4, 0x35, 0x35, 0x43, 0x43, 0x35, 0x35, 0x30, 0x7A, 0x30, 0x7A, 0x01, 0x9D),
+ _INIT_DCS_CMD(0xB6, 0x34, 0x34, 0x03),
+ _INIT_DCS_CMD(0xE9, 0xCD),
+ _INIT_DCS_CMD(0xBA, 0x84),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+ _INIT_DCS_CMD(0xBC, 0x1B, 0x04),
+ _INIT_DCS_CMD(0xBE, 0x20),
+ _INIT_DCS_CMD(0xBF, 0xFC, 0xC4),
+ _INIT_DCS_CMD(0xC0, 0x34, 0x34, 0x22, 0x11, 0x22, 0xA0, 0x31, 0x08, 0xF5, 0x03),
+ _INIT_DCS_CMD(0xE9, 0xCC),
+ _INIT_DCS_CMD(0xC7, 0x80),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+ _INIT_DCS_CMD(0xE9, 0xC6),
+ _INIT_DCS_CMD(0xC8, 0x97),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+ _INIT_DCS_CMD(0xC9, 0x00, 0x1E, 0x13, 0x88, 0x01),
+ _INIT_DCS_CMD(0xCB, 0x08, 0x13, 0x07, 0x00, 0x0F, 0x34),
+ _INIT_DCS_CMD(0xCC, 0x02, 0x03, 0x44),
+ _INIT_DCS_CMD(0xE9, 0xC4),
+ _INIT_DCS_CMD(0xD0, 0x03),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+ _INIT_DCS_CMD(0xD1, 0x07, 0x06, 0x00, 0x02, 0x04, 0x2C, 0xFF),
+ _INIT_DCS_CMD(0xD3, 0x06, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x37, 0x07, 0x64, 0x7C, 0x11, 0x11, 0x03, 0x03, 0x32, 0x10, 0x0E, 0x00, 0x0E, 0x32, 0x17, 0x97, 0x07, 0x97, 0x32,
+ 0x00, 0x02, 0x00, 0x02, 0x00, 0x00),
+ _INIT_DCS_CMD(0xD5, 0x25, 0x24, 0x25, 0x24, 0x18, 0x18, 0x18, 0x18, 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 0x05, 0x04, 0x03, 0x02, 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 0xA8, 0xA8, 0xA8, 0xA8, 0x29, 0x29, 0x29, 0x29, 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18),
+ _INIT_DCS_CMD(0xD8, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ _INIT_DCS_CMD(0xE7, 0x07, 0x10, 0x10, 0x1A, 0x26, 0x9E, 0x00, 0x4F, 0xA0, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x0A, 0x02, 0x02, 0x00, 0x33, 0x02, 0x04, 0x18, 0x01),
+ _INIT_DCS_CMD(0xBD, 0x01),
+ _INIT_DCS_CMD(0xB1, 0x01, 0x7F, 0x11, 0xFD),
+ _INIT_DCS_CMD(0xCB, 0x86),
+ _INIT_DCS_CMD(0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ _INIT_DCS_CMD(0xE7, 0x02, 0x00, 0x2B, 0x01, 0x7E, 0x0F, 0x7E, 0x10, 0xA0, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00),
+ _INIT_DCS_CMD(0xBD, 0x02),
+ _INIT_DCS_CMD(0xBF, 0xF2),
+ _INIT_DCS_CMD(0xCB, 0x03, 0x07, 0x00, 0x10, 0x79),
+ _INIT_DCS_CMD(0xD8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xA0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xA0),
+ _INIT_DCS_CMD(0xE7, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0x00, 0x00, 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, 0x20, 0x6E, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ _INIT_DCS_CMD(0xBD, 0x03),
+ _INIT_DCS_CMD(0xD8, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xA0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFA, 0xA0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ _INIT_DCS_CMD(0xE9, 0xC6),
+ _INIT_DCS_CMD(0xB4, 0x03, 0xFF, 0xF8),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+ _INIT_DCS_CMD(0xE1, 0x00),
+ _INIT_DCS_CMD(0xBD, 0x00),
+ _INIT_DCS_CMD(0xE9, 0xC4),
+ _INIT_DCS_CMD(0xBA, 0x96),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+ _INIT_DCS_CMD(0xBD, 0x01),
+ _INIT_DCS_CMD(0xE9, 0xC5),
+ _INIT_DCS_CMD(0xBA, 0x4F),
+ _INIT_DCS_CMD(0xE9, 0x3F),
+ _INIT_DCS_CMD(0xBD, 0x00),
+ _INIT_DELAY_CMD(50),
+ _INIT_DCS_CMD(0x11),
+ _INIT_DELAY_CMD(110),
+ _INIT_DCS_CMD(0x29),
+ _INIT_DELAY_CMD(25),
+ {},
+};
+
static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
{
return container_of(panel, struct boe_panel, base);
@@ -1907,6 +1973,35 @@ static const struct panel_desc boe_nv110wum_desc = {
.init_cmds = boe_nv110wum_init_cmd,
.lp11_before_reset = true,
};
+
+static const struct drm_display_mode ivo_t109nw41_default_mode = {
+ .clock = 166400,
+ .hdisplay = 1200,
+ .hsync_start = 1200 + 75,
+ .hsync_end = 1200 + 75 + 20,
+ .htotal = 1200 + 75 + 20 + 55,
+ .vdisplay = 1920,
+ .vsync_start = 1920 + 115,
+ .vsync_end = 1920 + 115 + 8,
+ .vtotal = 1920 + 115 + 8 + 12,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct panel_desc ivo_t109nw41_desc = {
+ .modes = &ivo_t109nw41_default_mode,
+ .bpc = 8,
+ .size = {
+ .width_mm = 147,
+ .height_mm = 235,
+ },
+ .lanes = 4,
+ .format = MIPI_DSI_FMT_RGB888,
+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_LPM,
+ .init_cmds = ivo_t109nw41_init_cmd,
+ .lp11_before_reset = true,
+};
+
static int boe_panel_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
@@ -2088,6 +2183,9 @@ static const struct of_device_id boe_of_match[] = {
{ .compatible = "boe,nv110wum-l60",
.data = &boe_nv110wum_desc
},
+ { .compatible = "ivo,t109nw41",
+ .data = &ivo_t109nw41_desc
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, boe_of_match);
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v3 1/2] dt-bindings: riscv: add Milk-V Duo S board compatibles
From: Inochi Amaoto @ 2024-04-10 7:19 UTC (permalink / raw)
To: michael.opdenacker, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Chen Wang, Inochi Amaoto, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Chao Wei
Cc: linux-riscv, devicetree, linux-kernel
In-Reply-To: <20240410062254.2955647-2-michael.opdenacker@bootlin.com>
On Wed, Apr 10, 2024 at 08:22:53AM +0200, michael.opdenacker@bootlin.com wrote:
> From: Michael Opdenacker <michael.opdenacker@bootlin.com>
>
> Document the compatible strings for the Milk-V Duo S board[1] which uses
> the SOPHGO SG2000 SoC, compatible with the SOPHGO CV1800B SoC[2].
>
> Link: https://milkv.io/duo-s [1]
> Link: https://en.sophgo.com/product/introduce/cv180xB.html [2]
>
> Signed-off-by: Michael Opdenacker <michael.opdenacker@bootlin.com>
> ---
> Documentation/devicetree/bindings/riscv/sophgo.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> index 9bc813dad098..1837bc550056 100644
> --- a/Documentation/devicetree/bindings/riscv/sophgo.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
> @@ -21,6 +21,7 @@ properties:
> - items:
> - enum:
> - milkv,duo
> + - milkv,duos
> - const: sophgo,cv1800b
Why not adding sg2000 property? They are different series.
IIRC, it at least a cv1813h not cv1800b. I suggest checking
the vendor SDK to get the right board compatibles.
> - items:
> - enum:
> --
> 2.34.1
>
^ permalink raw reply
* RE: [EXT] Re: [PATCH v8 3/8] perf: imx_perf: let the driver manage the counter usage rather the user
From: Xu Yang @ 2024-04-10 7:39 UTC (permalink / raw)
To: Will Deacon
Cc: Frank Li, mark.rutland@arm.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org,
irogers@google.com, mike.leach@linaro.org, peterz@infradead.org,
mingo@redhat.com, acme@kernel.org,
alexander.shishkin@linux.intel.com, adrian.hunter@intel.com,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
imx@lists.linux.dev
In-Reply-To: <20240409152627.GA23621@willie-the-truck>
Hi Will,
>
> On Fri, Mar 22, 2024 at 02:39:25PM +0800, Xu Yang wrote:
> > In current design, the user of perf app needs to input counter ID to count
> > events. However, this is not user-friendly since the user needs to lookup
> > the map table to find the counter. Instead of letting the user to input
> > the counter, let this driver to manage the counters in this patch.
>
> I think we still have to support the old interface so that we don't break
> those existing users (even if the driver just ignores whatever counter ID
> is provided in a backwards-compatible way).
>
> > This will be implemented by:
> > 1. allocate counter 0 for cycle event.
> > 2. find unused counter from 1-10 for reference events.
> > 3. allocate specific counter for counter-specific events.
> >
> > In this patch, counter attribute is removed too. To mark counter-specific
> > events, counter ID will be encoded into perf_pmu_events_attr.id.
> >
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> >
> > ---
> > Changes in v6:
> > - new patch
> > Changes in v7:
> > - no changes
> > Changes in v8:
> > - add Rb tag
> > ---
> > drivers/perf/fsl_imx9_ddr_perf.c | 168 ++++++++++++++++++-------------
> > 1 file changed, 99 insertions(+), 69 deletions(-)
> >
> > diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
> > index 0017f2c9ef91..b728719b494c 100644
> > --- a/drivers/perf/fsl_imx9_ddr_perf.c
> > +++ b/drivers/perf/fsl_imx9_ddr_perf.c
> > @@ -245,14 +249,12 @@ static const struct attribute_group ddr_perf_events_attr_group = {
> > .attrs = ddr_perf_events_attrs,
> > };
> >
> > -PMU_FORMAT_ATTR(event, "config:0-7");
> > -PMU_FORMAT_ATTR(counter, "config:8-15");
> > +PMU_FORMAT_ATTR(event, "config:0-15");
>
> Sadly, this is a user-visible change so I think it will break old tools,
> won't it?
For imx ddr pmu, most of the people will use metrics rather event itself,
and we have speficy the format of event parameters in metrics table.
The parameters is also updated in this patchset.
And to easy use for user, the counter should be hidden (transparent) to
user after I had talk with Frank. Then, the user need't to look up the event
table to find which counter to use.
So this patchset will basically not break the usage of perf tools and will
improve practicality.
Thanks,
Xu Yang
>
> Will
^ permalink raw reply
* Re: [PATCH v3 1/1] arm64: dts: imx93-11x11-evk: add rtc PCF2131 support
From: Marco Felsch @ 2024-04-10 7:40 UTC (permalink / raw)
To: Joy Zou
Cc: ping.bai, robh+dt, krzysztof.kozlowski+dt, conor+dt, shawnguo,
s.hauer, devicetree, imx, linux-kernel, linux-imx, kernel,
festevam, linux-arm-kernel
In-Reply-To: <20240410070128.1506555-2-joy.zou@nxp.com>
On 24-04-10, Joy Zou wrote:
> Support rtc PCF2131 on imx93-11x11-evk.
>
> Signed-off-by: Joy Zou <joy.zou@nxp.com>
> ---
> Changes in v3:
> 1.adjust the indentation.
>
> Changes in v2:
> 1. remove unnecessary status property.
> ---
> .../boot/dts/freescale/imx93-11x11-evk.dts | 24 +++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
> index 07e85a30a25f..73e0bca36b81 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
> @@ -281,6 +281,23 @@ ldo5: LDO5 {
> };
> };
>
> +&lpi2c3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-frequency = <400000>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&pinctrl_lpi2c3>;
> + pinctrl-1 = <&pinctrl_lpi2c3>;
Are both "default" and "sleep" pinctrl's required? It doesn't make any
sense to provde a sleep state which uses the same pinctrl state.
Regards,
Marco
> + status = "okay";
> +
> + pcf2131: rtc@53 {
> + compatible = "nxp,pcf2131";
> + reg = <0x53>;
> + interrupt-parent = <&pcal6524>;
> + interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
> + };
> +};
> +
> &iomuxc {
> pinctrl_eqos: eqosgrp {
> fsl,pins = <
> @@ -343,6 +360,13 @@ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
> >;
> };
>
> + pinctrl_lpi2c3: lpi2c3grp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
> + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
> + >;
> + };
> +
> pinctrl_pcal6524: pcal6524grp {
> fsl,pins = <
> MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
> --
> 2.37.1
>
>
>
^ permalink raw reply
* Re: [PATCH] arm64: dts: mediatek: mt8192: Add missing trip point in thermal zone
From: AngeloGioacchino Del Regno @ 2024-04-10 7:43 UTC (permalink / raw)
To: Hsin-Te Yuan, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Matthias Brugger, Nícolas F. R. A. Prado,
Bernhard Rosenkränzer, Balsam CHIHI, Alexandre Mergnat
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <20240410-upstream-torvalds-master-v1-1-852e903f0cec@chromium.org>
Il 10/04/24 08:20, Hsin-Te Yuan ha scritto:
> Add the missing passive trip point which is expected by kernel.
>
> Fixes: c7a728051f4e ("arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones")
> Signed-off-by: Hsin-Te Yuan <yuanhsinte@chromium.org>
Sorry, I don't understand what you're trying to solve here.
All of the thermal zones in mt8192.dtsi already do have a passive trip point
which is also used in cooling-maps.
Can you please describe the issue?
Thanks,
Angelo
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 40 ++++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 05e401670bced..08d8bccc84669 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1959,6 +1959,11 @@ cpu0-thermal {
> thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU0>;
>
> trips {
> + cpu0_thres: trip-point {
> + temperature = <68000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> cpu0_alert: trip-alert {
> temperature = <85000>;
> hysteresis = <2000>;
> @@ -1989,6 +1994,11 @@ cpu1-thermal {
> thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU1>;
>
> trips {
> + cpu1_thres: trip-point {
> + temperature = <68000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> cpu1_alert: trip-alert {
> temperature = <85000>;
> hysteresis = <2000>;
> @@ -2019,6 +2029,11 @@ cpu2-thermal {
> thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU2>;
>
> trips {
> + cpu2_thres: trip-point {
> + temperature = <68000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> cpu2_alert: trip-alert {
> temperature = <85000>;
> hysteresis = <2000>;
> @@ -2049,6 +2064,11 @@ cpu3-thermal {
> thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU3>;
>
> trips {
> + cpu3_thres: trip-point {
> + temperature = <68000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> cpu3_alert: trip-alert {
> temperature = <85000>;
> hysteresis = <2000>;
> @@ -2079,6 +2099,11 @@ cpu4-thermal {
> thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU0>;
>
> trips {
> + cpu4_thres: trip-point {
> + temperature = <68000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> cpu4_alert: trip-alert {
> temperature = <85000>;
> hysteresis = <2000>;
> @@ -2109,6 +2134,11 @@ cpu5-thermal {
> thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU1>;
>
> trips {
> + cpu5_thres: trip-point {
> + temperature = <68000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> cpu5_alert: trip-alert {
> temperature = <85000>;
> hysteresis = <2000>;
> @@ -2139,6 +2169,11 @@ cpu6-thermal {
> thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU2>;
>
> trips {
> + cpu6_thres: trip-point {
> + temperature = <68000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> cpu6_alert: trip-alert {
> temperature = <85000>;
> hysteresis = <2000>;
> @@ -2169,6 +2204,11 @@ cpu7-thermal {
> thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU3>;
>
> trips {
> + cpu7_thres: trip-point {
> + temperature = <68000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> cpu7_alert: trip-alert {
> temperature = <85000>;
> hysteresis = <2000>;
>
> ---
> base-commit: 20cb38a7af88dc40095da7c2c9094da3873fea23
> change-id: 20240410-upstream-torvalds-master-40aeff5416c7
>
> Best regards,
^ permalink raw reply
* Re: [PATCH V5] PCI: Add support for preserving boot configuration
From: Vidya Sagar @ 2024-04-10 7:44 UTC (permalink / raw)
To: bhelgaas
Cc: lpieralisi, mmaddireddy, linux-kernel, will, jonathanh, kthota,
frowand.list, kw, linux-arm-kernel, lenb, devicetree, sagar.tv,
rafael, linux-pci, treding, linux-acpi, Rob Herring
In-Reply-To: <171207369295.222743.17702844066682854972.robh@kernel.org>
Thanks Rob for the review.
Bjorn, do you have any further comments for this patch?
On 02-04-2024 21:31, Rob Herring wrote:
> External email: Use caution opening links or attachments
>
>
> On Mon, 01 Apr 2024 13:20:31 +0530, Vidya Sagar wrote:
>> Add support for preserving the boot configuration done by the
>> platform firmware per host bridge basis, based on the presence of
>> 'linux,pci-probe-only' property in the respective PCI host bridge
>> device-tree node. It also unifies the ACPI and DT based boot flows
>> in this regard.
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> ---
>> V5:
>> * Addressed Rob's review comments
>>
>> V4:
>> * Addressed Bjorn's review comments
>>
>> V3:
>> * Unified ACPI and DT flows as part of addressing Bjorn's review comments
>>
>> V2:
>> * Addressed issues reported by kernel test robot <lkp@intel.com>
>>
>> drivers/acpi/pci_root.c | 12 -----
>> drivers/pci/controller/pci-host-common.c | 4 --
>> drivers/pci/of.c | 57 +++++++++++++++++++-----
>> drivers/pci/probe.c | 46 ++++++++++++++-----
>> include/linux/of_pci.h | 6 +++
>> 5 files changed, 88 insertions(+), 37 deletions(-)
>>
> Reviewed-by: Rob Herring <robh@kernel.org>
>
^ permalink raw reply
* [PATCH] arm64: dts: qcom: sm8650: add description of CCI controllers
From: Vladimir Zapolskiy @ 2024-04-10 7:49 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Jagadeesh Kona
Cc: Krzysztof Kozlowski, Neil Armstrong, linux-arm-msm, devicetree
Qualcomm SM8650 SoC has three CCI controllers with two I2C busses
connected to each of them.
The CCI controllers on SM8650 are compatible with the ones found on
many other older generations of Qualcomm SoCs.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
---
The change is based and depends on a patch series from Jagadeesh Kona:
https://lore.kernel.org/linux-arm-msm/20240321092529.13362-1-quic_jkona@quicinc.com/
It might be an option to add this change right to the series,
since it anyway requires a respin.
A new compatible value "qcom,sm8650-cci" is NOT added to
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml , because
the controller IP description and selection is covered by a generic
compatible value "qcom,msm8996-cci".
arch/arm64/boot/dts/qcom/sm8650.dtsi | 315 +++++++++++++++++++++++++++
1 file changed, 315 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index b406835b2e71..160b618dff9c 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -3122,6 +3122,114 @@ videocc: clock-controller@aaf0000 {
#power-domain-cells = <1>;
};
+ cci0: cci@ac15000 {
+ compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac15000 0 0x1000>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci";
+ pinctrl-0 = <&cci0_default &cci1_default>;
+ pinctrl-1 = <&cci0_sleep &cci1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ assigned-clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>;
+ assigned-clock-rates = <37500000>;
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac16000 {
+ compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac16000 0 0x1000>;
+ interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci";
+ pinctrl-0 = <&cci2_default &cci3_default>;
+ pinctrl-1 = <&cci2_sleep &cci3_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci2: cci@ac17000 {
+ compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac17000 0 0x1000>;
+ interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_2_CLK>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci";
+ pinctrl-0 = <&cci4_default &cci5_default>;
+ pinctrl-1 = <&cci4_sleep &cci5_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci2_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci2_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
camcc: clock-controller@ade0000 {
compatible = "qcom,sm8650-camcc";
reg = <0 0x0ade0000 0 0x20000>;
@@ -3815,6 +3923,213 @@ tlmm: pinctrl@f100000 {
wakeup-parent = <&pdc>;
+ cci0_default: cci0-default-state {
+ sda-pins {
+ pins = "gpio113";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio114";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci0_sleep: cci0-sleep-state {
+ sda-pins {
+ pins = "gpio113";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio114";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_default: cci1-default-state {
+ sda-pins {
+ pins = "gpio115";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio116";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ mclk-pins {
+ pins = "gpio101";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rst-pins {
+ pins = "gpio15";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cci1_sleep: cci1-sleep-state {
+ sda-pins {
+ pins = "gpio115";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio116";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci2_default: cci2-default-state {
+ sda-pins {
+ pins = "gpio117";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio118";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci2_sleep: cci2-sleep-state {
+ sda-pins {
+ pins = "gpio117";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio118";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci3_default: cci3-default-state {
+ sda-pins {
+ pins = "gpio12";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio13";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci3_sleep: cci3-sleep-state {
+ sda-pins {
+ pins = "gpio12";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio13";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci4_default: cci4-default-state {
+ sda-pins {
+ pins = "gpio112";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio153";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci4_sleep: cci4-sleep-state {
+ sda-pins {
+ pins = "gpio112";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio153";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci5_default: cci5-default-state {
+ sda-pins {
+ pins = "gpio119";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ pins = "gpio120";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
+
+ cci5_sleep: cci5-sleep-state {
+ sda-pins {
+ pins = "gpio119";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio120";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
hub_i2c0_data_clk: hub-i2c0-data-clk-state {
/* SDA, SCL */
pins = "gpio64", "gpio65";
--
2.33.0
^ permalink raw reply related
* Re: [PATCH] arm64: dts: qcom: sm8650: add description of CCI controllers
From: Neil Armstrong @ 2024-04-10 7:52 UTC (permalink / raw)
To: Vladimir Zapolskiy, Bjorn Andersson, Konrad Dybcio,
Jagadeesh Kona
Cc: Krzysztof Kozlowski, linux-arm-msm, devicetree
In-Reply-To: <20240410074951.447898-1-vladimir.zapolskiy@linaro.org>
Hi,
On 10/04/2024 09:49, Vladimir Zapolskiy wrote:
> Qualcomm SM8650 SoC has three CCI controllers with two I2C busses
> connected to each of them.
>
> The CCI controllers on SM8650 are compatible with the ones found on
> many other older generations of Qualcomm SoCs.
>
> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> ---
> The change is based and depends on a patch series from Jagadeesh Kona:
>
> https://lore.kernel.org/linux-arm-msm/20240321092529.13362-1-quic_jkona@quicinc.com/
>
> It might be an option to add this change right to the series,
> since it anyway requires a respin.
>
> A new compatible value "qcom,sm8650-cci" is NOT added to
> Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml , because
> the controller IP description and selection is covered by a generic
> compatible value "qcom,msm8996-cci".
You'll still need to add qcom,sm8650-cci to the "CCI v2" list in qcom,i2c-cci.yaml,
otherwise the DTBS check fail, even if the fallback is already present.
Neil
>
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 315 +++++++++++++++++++++++++++
> 1 file changed, 315 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index b406835b2e71..160b618dff9c 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -3122,6 +3122,114 @@ videocc: clock-controller@aaf0000 {
> #power-domain-cells = <1>;
> };
>
> + cci0: cci@ac15000 {
> + compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
> + reg = <0 0x0ac15000 0 0x1000>;
> + interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
> + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_0_CLK>;
> + clock-names = "camnoc_axi",
> + "slow_ahb_src",
> + "cpas_ahb",
> + "cci";
> + pinctrl-0 = <&cci0_default &cci1_default>;
> + pinctrl-1 = <&cci0_sleep &cci1_sleep>;
> + pinctrl-names = "default", "sleep";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + assigned-clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>;
> + assigned-clock-rates = <37500000>;
> +
> + cci0_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci0_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + cci1: cci@ac16000 {
> + compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
> + reg = <0 0x0ac16000 0 0x1000>;
> + interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
> + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_1_CLK>;
> + clock-names = "camnoc_axi",
> + "slow_ahb_src",
> + "cpas_ahb",
> + "cci";
> + pinctrl-0 = <&cci2_default &cci3_default>;
> + pinctrl-1 = <&cci2_sleep &cci3_sleep>;
> + pinctrl-names = "default", "sleep";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cci1_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci1_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + cci2: cci@ac17000 {
> + compatible = "qcom,sm8650-cci", "qcom,msm8996-cci";
> + reg = <0 0x0ac17000 0 0x1000>;
> + interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
> + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_2_CLK>;
> + clock-names = "camnoc_axi",
> + "slow_ahb_src",
> + "cpas_ahb",
> + "cci";
> + pinctrl-0 = <&cci4_default &cci5_default>;
> + pinctrl-1 = <&cci4_sleep &cci5_sleep>;
> + pinctrl-names = "default", "sleep";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cci2_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci2_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> camcc: clock-controller@ade0000 {
> compatible = "qcom,sm8650-camcc";
> reg = <0 0x0ade0000 0 0x20000>;
> @@ -3815,6 +3923,213 @@ tlmm: pinctrl@f100000 {
>
> wakeup-parent = <&pdc>;
>
> + cci0_default: cci0-default-state {
> + sda-pins {
> + pins = "gpio113";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + scl-pins {
> + pins = "gpio114";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> + };
> +
> + cci0_sleep: cci0-sleep-state {
> + sda-pins {
> + pins = "gpio113";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio114";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci1_default: cci1-default-state {
> + sda-pins {
> + pins = "gpio115";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + scl-pins {
> + pins = "gpio116";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + mclk-pins {
> + pins = "gpio101";
> + function = "cam_mclk";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + rst-pins {
> + pins = "gpio15";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + output-low;
> + };
> + };
> +
> + cci1_sleep: cci1-sleep-state {
> + sda-pins {
> + pins = "gpio115";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio116";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci2_default: cci2-default-state {
> + sda-pins {
> + pins = "gpio117";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + scl-pins {
> + pins = "gpio118";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> + };
> +
> + cci2_sleep: cci2-sleep-state {
> + sda-pins {
> + pins = "gpio117";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio118";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci3_default: cci3-default-state {
> + sda-pins {
> + pins = "gpio12";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + scl-pins {
> + pins = "gpio13";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> + };
> +
> + cci3_sleep: cci3-sleep-state {
> + sda-pins {
> + pins = "gpio12";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio13";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci4_default: cci4-default-state {
> + sda-pins {
> + pins = "gpio112";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + scl-pins {
> + pins = "gpio153";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> + };
> +
> + cci4_sleep: cci4-sleep-state {
> + sda-pins {
> + pins = "gpio112";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio153";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci5_default: cci5-default-state {
> + sda-pins {
> + pins = "gpio119";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + scl-pins {
> + pins = "gpio120";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> + };
> +
> + cci5_sleep: cci5-sleep-state {
> + sda-pins {
> + pins = "gpio119";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio120";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> hub_i2c0_data_clk: hub-i2c0-data-clk-state {
> /* SDA, SCL */
> pins = "gpio64", "gpio65";
^ permalink raw reply
* Re: [PATCH v10 2/4] dt-bindings: stm32: update DT bingding for stm32mp25
From: Gabriel FERNANDEZ @ 2024-04-10 7:51 UTC (permalink / raw)
To: Krzysztof Kozlowski, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue, Philipp Zabel
Cc: linux-clk, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel
In-Reply-To: <0fd8811a-03ea-4471-a72d-7138aeb319f5@linaro.org>
On 4/10/24 09:06, Krzysztof Kozlowski wrote:
> On 09/04/2024 19:12, gabriel.fernandez@foss.st.com wrote:
>> From: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
>>
> A nit, subject: drop second/last, redundant "DT bindings". (plus a
> typo...) The "dt-bindings" prefix is already stating that these are
> bindings.
> See also:
> https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
>
> Subject: Everything is an update. Be specific.
ok
>
>> RCC driver uses '.index' to define all parent clocks instead '.names'
>> because the use of a name to define a parent clock is prohibited.
>> This is ABI change, but the RCC driver has not yet merged, unlike all
>> others drivers besides Linux.
>>
>> Fixes: b5be49db3d47 ("dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform")
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
>> ---
>>
>> Changes in v10:
>> - cosmetic change (add change blank line)
>> - rename USB2 into USBH to be compliant with last Reference Manuel
>>
>> Changes in v9:
>> - Update DT binding documentation according S.Boyd remarks on RCC driver:
>> Don't use '.name' to define a parent but use '.index'
>> Then:
>> - remove 'clock-names' property
>> - Add description of all parent clocks used in RCC driver
>>
>> v9 was Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Please avoid putting full acks somewhere in the changelog. You confuse
> people's filters and maybe tooling as well. "v9 was Acked-by Conor
> Dooley", so a proper sentence, not "fake" ack, would work for everyone.
>
>
> With fixes in the subject:
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Thank's
Best regards
Gabriel
> Best regards,
> Krzysztof
>
^ permalink raw reply
* Re: [PATCH v2 0/5] arm64: dts: qcom: add USB-C orientation GPIOs
From: neil.armstrong @ 2024-04-10 7:53 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20240409-hdk-orientation-gpios-v2-0-658efd993987@linaro.org>
On 09/04/2024 16:28, Dmitry Baryshkov wrote:
> Populate orientation GPIOs for some of the PMIC-GLINK-based devices.
> This leaves only FairPhone5, RB3Gen2, SC8180X Primus and SC8280XP CRD
> without the orientation GPIOs declared.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> Changes in v2:
> - Relax schema restriction for orientation-gpios property (Luca Weiss)
> - Link to v1: https://lore.kernel.org/r/20240408-hdk-orientation-gpios-v1-0-8064ba43e52a@linaro.org
>
> ---
> Dmitry Baryshkov (5):
> dt-bindings: soc: qcom: pmic-glink: allow orientation-gpios
> arm64: dts: qcom: sm8350-hdk: add USB-C orientation GPIO
> arm64: dts: qcom: sm8450-hdk: add USB-C orientation GPIO
> arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: add USB-C orientation GPIOs
> arm64: dts: qcom: sc8180x-lenovo-flex-5g: add USB-C orientation GPIOs
>
> .../devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 14 --------------
> arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 ++
> arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 ++
> arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 +
> arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 +
> 5 files changed, 6 insertions(+), 14 deletions(-)
> ---
> base-commit: 8568bb2ccc278f344e6ac44af6ed010a90aa88dc
> change-id: 20240408-hdk-orientation-gpios-141bc7fd247d
>
> Best regards,
You forgot to pick it on the v1:
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply
* Re: [PATCH v3 1/2] dt-bindings: riscv: add Milk-V Duo S board compatibles
From: Michael Opdenacker @ 2024-04-10 7:55 UTC (permalink / raw)
To: Inochi Amaoto, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
Chen Wang, Paul Walmsley, Palmer Dabbelt, Albert Ou, Chao Wei
Cc: michael.opdenacker, linux-riscv, devicetree, linux-kernel
In-Reply-To: <IA1PR20MB49532EC9B654B5B1C2538851BB062@IA1PR20MB4953.namprd20.prod.outlook.com>
Hi Inochi
Thanks for the reviews!
On 4/10/24 at 09:19, Inochi Amaoto wrote:
> On Wed, Apr 10, 2024 at 08:22:53AM +0200, michael.opdenacker@bootlin.com wrote:
>> From: Michael Opdenacker <michael.opdenacker@bootlin.com>
>>
>> Document the compatible strings for the Milk-V Duo S board[1] which uses
>> the SOPHGO SG2000 SoC, compatible with the SOPHGO CV1800B SoC[2].
>>
>> Link: https://milkv.io/duo-s [1]
>> Link: https://en.sophgo.com/product/introduce/cv180xB.html [2]
>>
>> Signed-off-by: Michael Opdenacker <michael.opdenacker@bootlin.com>
>> ---
>> Documentation/devicetree/bindings/riscv/sophgo.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
>> index 9bc813dad098..1837bc550056 100644
>> --- a/Documentation/devicetree/bindings/riscv/sophgo.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
>> @@ -21,6 +21,7 @@ properties:
>> - items:
>> - enum:
>> - milkv,duo
>> + - milkv,duos
>> - const: sophgo,cv1800b
> Why not adding sg2000 property? They are different series.
> IIRC, it at least a cv1813h not cv1800b. I suggest checking
> the vendor SDK to get the right board compatibles.
Here's what there was in the vendor provided DTB, if I noted it correctly:
compatible = "cvitek,cv181x";
Cheers
Michael
--
Michael Opdenacker, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
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