* Re: [PATCH v2] arm64: dts: mediatek: mt8192: Add missing trip point in thermal zone
From: AngeloGioacchino Del Regno @ 2024-04-10 12:17 UTC (permalink / raw)
To: Hsin-Te Yuan
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
Nícolas F. R. A. Prado, Bernhard Rosenkränzer,
Balsam CHIHI, Alexandre Mergnat, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
In-Reply-To: <CAHc4DNLrU=QVWODOzHXW16Ko1V=W31zkSHOi7rztiJMOMDcKqg@mail.gmail.com>
Il 10/04/24 14:06, Hsin-Te Yuan ha scritto:
> Hi Angelo,
>
> 1. 68°C is provided by MediaTek previously in downstream
> 2. I think sustainable power will be estimated by
> estimate_sustainable_power in drivers/thermal/gov_power_allocator.c,
> but I'll ask MediaTek if they can provide the precise value.
> 3. Sure. I'll do it in v3 after I check 2. with MediaTek
>
Perfect, thanks for the clarification.
Will wait for v3.
Cheers,
Angelo
> Regards,
> Hsin-Te
>
> On Wed, Apr 10, 2024 at 5:50 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Il 10/04/24 10:40, Hsin-Te Yuan ha scritto:
>>> According to Documentation/driver-api/thermal/power_allocator.rst, there
>>> should be two passive trip points. Adding the missing trip point to
>>> ensure that the governor works optimally.
>>>
>>> Fixes: c7a728051f4e ("arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones")
>>> Signed-off-by: Hsin-Te Yuan <yuanhsinte@chromium.org>
>>
>> That's better - but while I can agree about setting a general temperature
>> for that, I still have a few questions and requests:
>>
>> 1. Why is this 68°C? Was that value provided by MediaTek, or was it calculated?
>> 1b. If this was calculated, please, can you explain how?
>>
>> 2. The power allocator documentation also says that the governor works good
>> when a "sustainable dissipatable power" parameter is fed to it through the
>> `sustainable-power` devicetree property (with that being strictly board
>> specific and never SoC-global, as that depends on the form factor and on
>> the cooling method of the machine), can you please also add the right
>> sustainable power indication to the Chromebook devicetrees?
>> In the MT8192 specific case, that's mt8192-asurada.dtsi.
>>
>> 3. I just noticed that MT8192 is not the only one that would be affected by
>> the issue that you're describing in this commit; can you please perform a
>> similar change on the others, if parameters are known?
>>
>> Thanks,
>> Angelo
>>
>>> ---
>>> Changes in v2:
>>> - Clearify the reason of adding another passive trip point
>>> - Link to v1: https://lore.kernel.org/r/20240410-upstream-torvalds-master-v1-1-852e903f0cec@chromium.org
>>> ---
>>> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 40 ++++++++++++++++++++++++++++++++
>>> 1 file changed, 40 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index 05e401670bced..08d8bccc84669 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -1959,6 +1959,11 @@ cpu0-thermal {
>>> thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU0>;
>>>
>>> trips {
>>> + cpu0_thres: trip-point {
>>> + temperature = <68000>;
>>> + hysteresis = <2000>;
>>> + type = "passive";
>>> + };
>>> cpu0_alert: trip-alert {
>>> temperature = <85000>;
>>> hysteresis = <2000>;
>>> @@ -1989,6 +1994,11 @@ cpu1-thermal {
>>> thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU1>;
>>>
>>> trips {
>>> + cpu1_thres: trip-point {
>>> + temperature = <68000>;
>>> + hysteresis = <2000>;
>>> + type = "passive";
>>> + };
>>> cpu1_alert: trip-alert {
>>> temperature = <85000>;
>>> hysteresis = <2000>;
>>> @@ -2019,6 +2029,11 @@ cpu2-thermal {
>>> thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU2>;
>>>
>>> trips {
>>> + cpu2_thres: trip-point {
>>> + temperature = <68000>;
>>> + hysteresis = <2000>;
>>> + type = "passive";
>>> + };
>>> cpu2_alert: trip-alert {
>>> temperature = <85000>;
>>> hysteresis = <2000>;
>>> @@ -2049,6 +2064,11 @@ cpu3-thermal {
>>> thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU3>;
>>>
>>> trips {
>>> + cpu3_thres: trip-point {
>>> + temperature = <68000>;
>>> + hysteresis = <2000>;
>>> + type = "passive";
>>> + };
>>> cpu3_alert: trip-alert {
>>> temperature = <85000>;
>>> hysteresis = <2000>;
>>> @@ -2079,6 +2099,11 @@ cpu4-thermal {
>>> thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU0>;
>>>
>>> trips {
>>> + cpu4_thres: trip-point {
>>> + temperature = <68000>;
>>> + hysteresis = <2000>;
>>> + type = "passive";
>>> + };
>>> cpu4_alert: trip-alert {
>>> temperature = <85000>;
>>> hysteresis = <2000>;
>>> @@ -2109,6 +2134,11 @@ cpu5-thermal {
>>> thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU1>;
>>>
>>> trips {
>>> + cpu5_thres: trip-point {
>>> + temperature = <68000>;
>>> + hysteresis = <2000>;
>>> + type = "passive";
>>> + };
>>> cpu5_alert: trip-alert {
>>> temperature = <85000>;
>>> hysteresis = <2000>;
>>> @@ -2139,6 +2169,11 @@ cpu6-thermal {
>>> thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU2>;
>>>
>>> trips {
>>> + cpu6_thres: trip-point {
>>> + temperature = <68000>;
>>> + hysteresis = <2000>;
>>> + type = "passive";
>>> + };
>>> cpu6_alert: trip-alert {
>>> temperature = <85000>;
>>> hysteresis = <2000>;
>>> @@ -2169,6 +2204,11 @@ cpu7-thermal {
>>> thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU3>;
>>>
>>> trips {
>>> + cpu7_thres: trip-point {
>>> + temperature = <68000>;
>>> + hysteresis = <2000>;
>>> + type = "passive";
>>> + };
>>> cpu7_alert: trip-alert {
>>> temperature = <85000>;
>>> hysteresis = <2000>;
>>>
>>> ---
>>> base-commit: 20cb38a7af88dc40095da7c2c9094da3873fea23
>>> change-id: 20240410-upstream-torvalds-master-40aeff5416c7
>>>
>>> Best regards,
>>
>>
^ permalink raw reply
* Re: [PATCH net-next v2 4/5] net: stmmac: add support for RZ/N1 GMAC
From: Romain Gantois @ 2024-04-10 12:25 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Romain Gantois, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Alexandre Torgue, Jose Abreu,
Maxime Coquelin, Russell King, Clément Léger,
Thomas Petazzoni, netdev, devicetree, linux-kernel,
linux-renesas-soc, linux-stm32, linux-arm-kernel
In-Reply-To: <CAMuHMdX-F8LXWx=Ras4f+Dt_r485HKjRDLydDXZsnZBW8HJzxw@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 810 bytes --]
Hi Geert,
On Tue, 9 Apr 2024, Geert Uytterhoeven wrote:
> > +config DWMAC_RZN1
> > + tristate "Renesas RZ/N1 dwmac support"
> > + default ARCH_RZN1
>
> Why default to enabled?
>
> > + depends on OF && (ARCH_RZN1 || COMPILE_TEST)
The kernel doc states this as one of the possible cases where setting default
y/m makes sense:
```
Sub-driver behavior or similar options for a driver that is “default n”. This
allows you to provide sane defaults.
```
In the case of DWMAC_RZN1, it is a suboption of stmmac which is "default n", and
I think it makes sense to enable the RZN1 ethernet controller driver if both the
stmmac driver and the RZN1 architecture were explicitely selected.
Best Regards,
--
Romain Gantois, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH v3 0/9] clk: renesas: rzg2l: Add support for power domains
From: Claudiu @ 2024-04-10 12:26 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
magnus.damm
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel,
claudiu.beznea, Claudiu Beznea
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Hi,
Series adds support for power domains on rzg2l driver.
RZ/G2L kind of devices support a functionality called MSTOP (module
stop/standby). According to hardware manual the module could be switch
to standby after its clocks are disabled. The reverse order of operation
should be done when enabling a module (get the module out of standby,
enable its clocks etc).
In [1] the MSTOP settings were implemented by adding code in driver
to attach the MSTOP state to the IP clocks. But it has been proposed
to implement it as power domain. The result is this series.
Along with MSTOP functionality there is also module power down
functionality (which is currently available only on RZ/G3S). This has
been also implemented through power domains.
The DT bindings were updated with power domain IDs (plain integers
that matches the DT with driver data structures). The current DT
bindings were updated with module IDs for the modules listed in tables
with name "Registers for Module Standby Mode" (see HW manual) exception
being RZ/G3S where, due to the power down functionality, the DDR,
TZCDDR, OTFDE_DDR were also added, to avoid system being blocked due
to the following lines of code from patch 6/9.
+ /* Prepare for power down the BUSes in power down mode. */
+ if (info->pm_domain_pwrdn_mstop)
+ writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP);
Domain IDs were added to all SoC specific bindings.
Thank you,
Claudiu Beznea
Changes in v3:
- collected tags
- dinamically detect if a SCIF is serial console and populate
pd->suspend_check
- dropped patch 09/10 from v2
Changes in v2:
- addressed review comments
- dropped:
- dt-bindings: clock: r9a09g011-cpg: Add always-on power domain IDs
- clk: renesas: r9a07g043: Add initial support for power domains
- clk: renesas: r9a07g044: Add initial support for power domains
- clk: renesas: r9a09g011: Add initial support for power domains
- clk: renesas: r9a09g011: Add initial support for power domains
- arm64: dts: renesas: r9a07g043: Update #power-domain-cells = <1>
- arm64: dts: renesas: r9a07g044: Update #power-domain-cells = <1>
- arm64: dts: renesas: r9a07g054: Update #power-domain-cells = <1>
- arm64: dts: renesas: r9a09g011: Update #power-domain-cells = <1>
as suggested in the review process
- dropped "arm64: dts: renesas: rzg3s-smarc-som: Guard the ethernet IRQ
GPIOs with proper flags" patch as it was integrated
- added suspend to RAM support
- collected tag
[1] https://lore.kernel.org/all/20231120070024.4079344-4-claudiu.beznea.uj@bp.renesas.com/
Claudiu Beznea (9):
dt-bindings: clock: r9a07g043-cpg: Add power domain IDs
dt-bindings: clock: r9a07g044-cpg: Add power domain IDs
dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
dt-bindings: clock: r9a08g045-cpg: Add power domain IDs
dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells =
<1> for RZ/G3S
clk: renesas: rzg2l: Extend power domain support
clk: renesas: r9a08g045: Add support for power domains
clk: renesas: rzg2l-cpg: Add suspend/resume support for power domains
arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1>
.../bindings/clock/renesas,rzg2l-cpg.yaml | 18 +-
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 20 +-
drivers/clk/renesas/r9a08g045-cpg.c | 61 ++++
drivers/clk/renesas/rzg2l-cpg.c | 269 +++++++++++++++++-
drivers/clk/renesas/rzg2l-cpg.h | 77 +++++
include/dt-bindings/clock/r9a07g043-cpg.h | 52 ++++
include/dt-bindings/clock/r9a07g044-cpg.h | 58 ++++
include/dt-bindings/clock/r9a07g054-cpg.h | 58 ++++
include/dt-bindings/clock/r9a08g045-cpg.h | 70 +++++
9 files changed, 659 insertions(+), 24 deletions(-)
--
2.39.2
^ permalink raw reply
* [PATCH v3 1/9] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs
From: Claudiu @ 2024-04-10 12:26 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
magnus.damm
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel,
claudiu.beznea, Claudiu Beznea
In-Reply-To: <20240410122657.2051132-1-claudiu.beznea.uj@bp.renesas.com>
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v3:
- collected tags
Changes in v2:
- added "RZ/G2UL Only" comments to some defines
- added RZ/Five specific defines
include/dt-bindings/clock/r9a07g043-cpg.h | 52 +++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h
index a64139fec815..131993343777 100644
--- a/include/dt-bindings/clock/r9a07g043-cpg.h
+++ b/include/dt-bindings/clock/r9a07g043-cpg.h
@@ -200,5 +200,57 @@
#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
+/* Power domain IDs. */
+#define R9A07G043_PD_ALWAYS_ON 0
+#define R9A07G043_PD_GIC 1 /* RZ/G2UL Only */
+#define R9A07G043_PD_IA55 2 /* RZ/G2UL Only */
+#define R9A07G043_PD_MHU 3 /* RZ/G2UL Only */
+#define R9A07G043_PD_CORESIGHT 4 /* RZ/G2UL Only */
+#define R9A07G043_PD_SYC 5 /* RZ/G2UL Only */
+#define R9A07G043_PD_DMAC 6
+#define R9A07G043_PD_GTM0 7
+#define R9A07G043_PD_GTM1 8
+#define R9A07G043_PD_GTM2 9
+#define R9A07G043_PD_MTU 10
+#define R9A07G043_PD_POE3 11
+#define R9A07G043_PD_WDT0 12
+#define R9A07G043_PD_SPI 13
+#define R9A07G043_PD_SDHI0 14
+#define R9A07G043_PD_SDHI1 15
+#define R9A07G043_PD_ISU 16 /* RZ/G2UL Only */
+#define R9A07G043_PD_CRU 17 /* RZ/G2UL Only */
+#define R9A07G043_PD_LCDC 18 /* RZ/G2UL Only */
+#define R9A07G043_PD_SSI0 19
+#define R9A07G043_PD_SSI1 20
+#define R9A07G043_PD_SSI2 21
+#define R9A07G043_PD_SSI3 22
+#define R9A07G043_PD_SRC 23
+#define R9A07G043_PD_USB0 24
+#define R9A07G043_PD_USB1 25
+#define R9A07G043_PD_USB_PHY 26
+#define R9A07G043_PD_ETHER0 27
+#define R9A07G043_PD_ETHER1 28
+#define R9A07G043_PD_I2C0 29
+#define R9A07G043_PD_I2C1 30
+#define R9A07G043_PD_I2C2 31
+#define R9A07G043_PD_I2C3 32
+#define R9A07G043_PD_SCIF0 33
+#define R9A07G043_PD_SCIF1 34
+#define R9A07G043_PD_SCIF2 35
+#define R9A07G043_PD_SCIF3 36
+#define R9A07G043_PD_SCIF4 37
+#define R9A07G043_PD_SCI0 38
+#define R9A07G043_PD_SCI1 39
+#define R9A07G043_PD_IRDA 40
+#define R9A07G043_PD_RSPI0 41
+#define R9A07G043_PD_RSPI1 42
+#define R9A07G043_PD_RSPI2 43
+#define R9A07G043_PD_CANFD 44
+#define R9A07G043_PD_ADC 45
+#define R9A07G043_PD_TSU 46
+#define R9A07G043_PD_PLIC 47 /* RZ/Five Only */
+#define R9A07G043_PD_IAX45 48 /* RZ/Five Only */
+#define R9A07G043_PD_NCEPLDM 49 /* RZ/Five Only */
+#define R9A07G043_PD_NCEPLMT 50 /* RZ/Five Only */
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
--
2.39.2
^ permalink raw reply related
* [PATCH v3 2/9] dt-bindings: clock: r9a07g044-cpg: Add power domain IDs
From: Claudiu @ 2024-04-10 12:26 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
magnus.damm
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel,
claudiu.beznea, Claudiu Beznea
In-Reply-To: <20240410122657.2051132-1-claudiu.beznea.uj@bp.renesas.com>
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add power domain IDs for RZ/G2L (R9A07G044) SoC.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v3:
- collected tags
Changes in v2:
- collected tag
include/dt-bindings/clock/r9a07g044-cpg.h | 58 +++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h
index 0bb17ff1a01a..e209f96f92b7 100644
--- a/include/dt-bindings/clock/r9a07g044-cpg.h
+++ b/include/dt-bindings/clock/r9a07g044-cpg.h
@@ -217,4 +217,62 @@
#define R9A07G044_ADC_ADRST_N 82
#define R9A07G044_TSU_PRESETN 83
+/* Power domain IDs. */
+#define R9A07G044_PD_ALWAYS_ON 0
+#define R9A07G044_PD_GIC 1
+#define R9A07G044_PD_IA55 2
+#define R9A07G044_PD_MHU 3
+#define R9A07G044_PD_CORESIGHT 4
+#define R9A07G044_PD_SYC 5
+#define R9A07G044_PD_DMAC 6
+#define R9A07G044_PD_GTM0 7
+#define R9A07G044_PD_GTM1 8
+#define R9A07G044_PD_GTM2 9
+#define R9A07G044_PD_MTU 10
+#define R9A07G044_PD_POE3 11
+#define R9A07G044_PD_GPT 12
+#define R9A07G044_PD_POEGA 13
+#define R9A07G044_PD_POEGB 14
+#define R9A07G044_PD_POEGC 15
+#define R9A07G044_PD_POEGD 16
+#define R9A07G044_PD_WDT0 17
+#define R9A07G044_PD_WDT1 18
+#define R9A07G044_PD_SPI 19
+#define R9A07G044_PD_SDHI0 20
+#define R9A07G044_PD_SDHI1 21
+#define R9A07G044_PD_3DGE 22
+#define R9A07G044_PD_ISU 23
+#define R9A07G044_PD_VCPL4 24
+#define R9A07G044_PD_CRU 25
+#define R9A07G044_PD_MIPI_DSI 26
+#define R9A07G044_PD_LCDC 27
+#define R9A07G044_PD_SSI0 28
+#define R9A07G044_PD_SSI1 29
+#define R9A07G044_PD_SSI2 30
+#define R9A07G044_PD_SSI3 31
+#define R9A07G044_PD_SRC 32
+#define R9A07G044_PD_USB0 33
+#define R9A07G044_PD_USB1 34
+#define R9A07G044_PD_USB_PHY 35
+#define R9A07G044_PD_ETHER0 36
+#define R9A07G044_PD_ETHER1 37
+#define R9A07G044_PD_I2C0 38
+#define R9A07G044_PD_I2C1 39
+#define R9A07G044_PD_I2C2 40
+#define R9A07G044_PD_I2C3 41
+#define R9A07G044_PD_SCIF0 42
+#define R9A07G044_PD_SCIF1 43
+#define R9A07G044_PD_SCIF2 44
+#define R9A07G044_PD_SCIF3 45
+#define R9A07G044_PD_SCIF4 46
+#define R9A07G044_PD_SCI0 47
+#define R9A07G044_PD_SCI1 48
+#define R9A07G044_PD_IRDA 49
+#define R9A07G044_PD_RSPI0 50
+#define R9A07G044_PD_RSPI1 51
+#define R9A07G044_PD_RSPI2 52
+#define R9A07G044_PD_CANFD 53
+#define R9A07G044_PD_ADC 54
+#define R9A07G044_PD_TSU 55
+
#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
--
2.39.2
^ permalink raw reply related
* [PATCH v3 3/9] dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
From: Claudiu @ 2024-04-10 12:26 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
magnus.damm
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel,
claudiu.beznea, Claudiu Beznea
In-Reply-To: <20240410122657.2051132-1-claudiu.beznea.uj@bp.renesas.com>
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add power domain IDs for RZ/V2L (R9A07G054) SoC.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v3:
- collected tags
Changes in v2:
- collected tag
include/dt-bindings/clock/r9a07g054-cpg.h | 58 +++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h
index 43f4dbda872c..2c99f89397c4 100644
--- a/include/dt-bindings/clock/r9a07g054-cpg.h
+++ b/include/dt-bindings/clock/r9a07g054-cpg.h
@@ -226,4 +226,62 @@
#define R9A07G054_TSU_PRESETN 83
#define R9A07G054_STPAI_ARESETN 84
+/* Power domain IDs. */
+#define R9A07G054_PD_ALWAYS_ON 0
+#define R9A07G054_PD_GIC 1
+#define R9A07G054_PD_IA55 2
+#define R9A07G054_PD_MHU 3
+#define R9A07G054_PD_CORESIGHT 4
+#define R9A07G054_PD_SYC 5
+#define R9A07G054_PD_DMAC 6
+#define R9A07G054_PD_GTM0 7
+#define R9A07G054_PD_GTM1 8
+#define R9A07G054_PD_GTM2 9
+#define R9A07G054_PD_MTU 10
+#define R9A07G054_PD_POE3 11
+#define R9A07G054_PD_GPT 12
+#define R9A07G054_PD_POEGA 13
+#define R9A07G054_PD_POEGB 14
+#define R9A07G054_PD_POEGC 15
+#define R9A07G054_PD_POEGD 16
+#define R9A07G054_PD_WDT0 17
+#define R9A07G054_PD_WDT1 18
+#define R9A07G054_PD_SPI 19
+#define R9A07G054_PD_SDHI0 20
+#define R9A07G054_PD_SDHI1 21
+#define R9A07G054_PD_3DGE 22
+#define R9A07G054_PD_ISU 23
+#define R9A07G054_PD_VCPL4 24
+#define R9A07G054_PD_CRU 25
+#define R9A07G054_PD_MIPI_DSI 26
+#define R9A07G054_PD_LCDC 27
+#define R9A07G054_PD_SSI0 28
+#define R9A07G054_PD_SSI1 29
+#define R9A07G054_PD_SSI2 30
+#define R9A07G054_PD_SSI3 31
+#define R9A07G054_PD_SRC 32
+#define R9A07G054_PD_USB0 33
+#define R9A07G054_PD_USB1 34
+#define R9A07G054_PD_USB_PHY 35
+#define R9A07G054_PD_ETHER0 36
+#define R9A07G054_PD_ETHER1 37
+#define R9A07G054_PD_I2C0 38
+#define R9A07G054_PD_I2C1 39
+#define R9A07G054_PD_I2C2 40
+#define R9A07G054_PD_I2C3 41
+#define R9A07G054_PD_SCIF0 42
+#define R9A07G054_PD_SCIF1 43
+#define R9A07G054_PD_SCIF2 44
+#define R9A07G054_PD_SCIF3 45
+#define R9A07G054_PD_SCIF4 46
+#define R9A07G054_PD_SCI0 47
+#define R9A07G054_PD_SCI1 48
+#define R9A07G054_PD_IRDA 49
+#define R9A07G054_PD_RSPI0 50
+#define R9A07G054_PD_RSPI1 51
+#define R9A07G054_PD_RSPI2 52
+#define R9A07G054_PD_CANFD 53
+#define R9A07G054_PD_ADC 54
+#define R9A07G054_PD_TSU 55
+
#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
--
2.39.2
^ permalink raw reply related
* [PATCH v3 4/9] dt-bindings: clock: r9a08g045-cpg: Add power domain IDs
From: Claudiu @ 2024-04-10 12:26 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
magnus.damm
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel,
claudiu.beznea, Claudiu Beznea
In-Reply-To: <20240410122657.2051132-1-claudiu.beznea.uj@bp.renesas.com>
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add power domain IDs for RZ/G3S (R9A08G045) SoC.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v3:
- collected tags
Changes in v2:
- collected tag
include/dt-bindings/clock/r9a08g045-cpg.h | 70 +++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/include/dt-bindings/clock/r9a08g045-cpg.h b/include/dt-bindings/clock/r9a08g045-cpg.h
index 410725b778a8..8281e9caf3a9 100644
--- a/include/dt-bindings/clock/r9a08g045-cpg.h
+++ b/include/dt-bindings/clock/r9a08g045-cpg.h
@@ -239,4 +239,74 @@
#define R9A08G045_I3C_PRESETN 92
#define R9A08G045_VBAT_BRESETN 93
+/* Power domain IDs. */
+#define R9A08G045_PD_ALWAYS_ON 0
+#define R9A08G045_PD_GIC 1
+#define R9A08G045_PD_IA55 2
+#define R9A08G045_PD_MHU 3
+#define R9A08G045_PD_CORESIGHT 4
+#define R9A08G045_PD_SYC 5
+#define R9A08G045_PD_DMAC 6
+#define R9A08G045_PD_GTM0 7
+#define R9A08G045_PD_GTM1 8
+#define R9A08G045_PD_GTM2 9
+#define R9A08G045_PD_GTM3 10
+#define R9A08G045_PD_GTM4 11
+#define R9A08G045_PD_GTM5 12
+#define R9A08G045_PD_GTM6 13
+#define R9A08G045_PD_GTM7 14
+#define R9A08G045_PD_MTU 15
+#define R9A08G045_PD_POE3 16
+#define R9A08G045_PD_GPT 17
+#define R9A08G045_PD_POEGA 18
+#define R9A08G045_PD_POEGB 19
+#define R9A08G045_PD_POEGC 20
+#define R9A08G045_PD_POEGD 21
+#define R9A08G045_PD_WDT0 22
+#define R9A08G045_PD_XSPI 23
+#define R9A08G045_PD_SDHI0 24
+#define R9A08G045_PD_SDHI1 25
+#define R9A08G045_PD_SDHI2 26
+#define R9A08G045_PD_SSI0 27
+#define R9A08G045_PD_SSI1 28
+#define R9A08G045_PD_SSI2 29
+#define R9A08G045_PD_SSI3 30
+#define R9A08G045_PD_SRC 31
+#define R9A08G045_PD_USB0 32
+#define R9A08G045_PD_USB1 33
+#define R9A08G045_PD_USB_PHY 34
+#define R9A08G045_PD_ETHER0 35
+#define R9A08G045_PD_ETHER1 36
+#define R9A08G045_PD_I2C0 37
+#define R9A08G045_PD_I2C1 38
+#define R9A08G045_PD_I2C2 39
+#define R9A08G045_PD_I2C3 40
+#define R9A08G045_PD_SCIF0 41
+#define R9A08G045_PD_SCIF1 42
+#define R9A08G045_PD_SCIF2 43
+#define R9A08G045_PD_SCIF3 44
+#define R9A08G045_PD_SCIF4 45
+#define R9A08G045_PD_SCIF5 46
+#define R9A08G045_PD_SCI0 47
+#define R9A08G045_PD_SCI1 48
+#define R9A08G045_PD_IRDA 49
+#define R9A08G045_PD_RSPI0 50
+#define R9A08G045_PD_RSPI1 51
+#define R9A08G045_PD_RSPI2 52
+#define R9A08G045_PD_RSPI3 53
+#define R9A08G045_PD_RSPI4 54
+#define R9A08G045_PD_CANFD 55
+#define R9A08G045_PD_ADC 56
+#define R9A08G045_PD_TSU 57
+#define R9A08G045_PD_OCTA 58
+#define R9A08G045_PD_PDM 59
+#define R9A08G045_PD_PCI 60
+#define R9A08G045_PD_SPDIF 61
+#define R9A08G045_PD_I3C 62
+#define R9A08G045_PD_VBAT 63
+
+#define R9A08G045_PD_DDR 64
+#define R9A08G045_PD_TZCDDR 65
+#define R9A08G045_PD_OTFDE_DDR 66
+
#endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */
--
2.39.2
^ permalink raw reply related
* [PATCH v3 5/9] dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S
From: Claudiu @ 2024-04-10 12:26 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
magnus.damm
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel,
claudiu.beznea, Claudiu Beznea
In-Reply-To: <20240410122657.2051132-1-claudiu.beznea.uj@bp.renesas.com>
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
The driver will be modified (in the next commits) to be able to specify
individual power domain ID for each IP. The driver will still
support #power-domain-cells = <0>, thus, previous users are not
affected.
The #power-domain-cells = <1> has been instantiated only for RZ/G3S at
the moment as individual platform clock drivers need to be adapted for
this to be supported on the rest of the SoCs.
Also, the description for #power-domain-cells was updated with the links
to per-SoC power domain IDs.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v3:
- collected tags
Changes in v2:
- updated patch title and description
- kept both 0 and 1 for #power-domain-cells as not all the drivers,
device trees are adpated with this series
- added a reference to dt-bindings/clock/r9a0*-cpg.h for power domain
specifiers
- dropped the changes from examples section
.../bindings/clock/renesas,rzg2l-cpg.yaml | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index 80a8c7114c31..4e3b0c45124a 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -57,7 +57,8 @@ properties:
can be power-managed through Module Standby should refer to the CPG device
node in their "power-domains" property, as documented by the generic PM
Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
- const: 0
+ The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could
+ be used to reference individual CPG power domains.
'#reset-cells':
description:
@@ -76,6 +77,21 @@ required:
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a08g045-cpg
+ then:
+ properties:
+ '#power-domain-cells':
+ const: 1
+ else:
+ properties:
+ '#power-domain-cells':
+ const: 0
+
examples:
- |
cpg: clock-controller@11010000 {
--
2.39.2
^ permalink raw reply related
* [PATCH v3 6/9] clk: renesas: rzg2l: Extend power domain support
From: Claudiu @ 2024-04-10 12:26 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
magnus.damm
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel,
claudiu.beznea, Claudiu Beznea
In-Reply-To: <20240410122657.2051132-1-claudiu.beznea.uj@bp.renesas.com>
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra
power when clocks are disabled by activating module standby. This is done
through MSTOP-specific registers that are part of CPG. Each individual
module has one or more bits associated with one MSTOP register (see table
"Registers for Module Standby Mode" from HW manuals). Hardware manual
associates modules' clocks with one or more MSTOP bits. There are 3
mappings available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW
manuals):
case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X})
case 2: N clocks mapped to 1 MSTOP bit (with N={0, ..., X})
case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y})
Case 3 has been currently identified on RZ/V2L for the VCPL4 module.
To cover all three cases, the individual platform drivers will provide to
clock driver MSTOP register offset and associated bits in this register
as a bitmask and the clock driver will apply this bitmask to proper
MSTOP register.
Apart from MSTOP support, RZ/G3S can save more power by powering down the
individual IPs (after MSTOP has been set) if proper bits in
CPG_PWRDN_IP{1,2} registers are set.
The MSTOP and IP power down support were implemented through power
domains. Platform-specific clock drivers will register an array of
type struct rzg2l_cpg_pm_domain_init_data, which will be used to
instantiate properly the power domains.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v3:
- collected tags
Changes in v2:
- called pm_genpd_init() with proper value for is_off argument
- fixed typos
- used flexible array for struct rzg2l_cpg_pm_domains::domains member
- moved genpd member of struct rzg2l_cpg_pd at the beginning of struct
- didn't initialize the parent variable in rzg2l_cpg_add_pm_domains()
as it is already initialized in the for block from
rzg2l_cpg_add_pm_domains() and that initialization should be enough
- dropped RZG2L_PD_F_PARENT flag
- used datasheet naming for all MSTOP registers
- added all MSTOP registers to rzg2l-cpg.h
- reworked the code that initializes the register offset and bits for domains
- dropped MSTOP*(), PWRDN*() macros and introduced struct rzg2l_cpg_reg_conf
and DEF_REG_CONF() for domain description
- constified the 1st argument of rzg2l_cpg_pm_domain_xlate()
- used dev instead of priv->dev where possible
- dropped RZG2L_PD_F_PARENT
- added RZG2L_PD_F_NONE for better description of domains in platform
specific clock drivers
drivers/clk/renesas/rzg2l-cpg.c | 213 +++++++++++++++++++++++++++++---
drivers/clk/renesas/rzg2l-cpg.h | 77 ++++++++++++
2 files changed, 276 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 3d2daa4ba2a4..b36700f4a9f5 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -139,7 +139,6 @@ struct rzg2l_pll5_mux_dsi_div_param {
* @num_resets: Number of Module Resets in info->resets[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @info: Pointer to platform data
- * @genpd: PM domain
* @mux_dsi_div_params: pll5 mux and dsi div parameters
*/
struct rzg2l_cpg_priv {
@@ -156,8 +155,6 @@ struct rzg2l_cpg_priv {
const struct rzg2l_cpg_info *info;
- struct generic_pm_domain genpd;
-
struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
};
@@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
return true;
}
+/**
+ * struct rzg2l_cpg_pm_domains - RZ/G2L PM domains data structure
+ * @onecell_data: cell data
+ * @domains: generic PM domains
+ */
+struct rzg2l_cpg_pm_domains {
+ struct genpd_onecell_data onecell_data;
+ struct generic_pm_domain *domains[];
+};
+
+/**
+ * struct rzg2l_cpg_pd - RZ/G2L power domain data structure
+ * @genpd: generic PM domain
+ * @priv: pointer to CPG private data structure
+ * @conf: CPG PM domain configuration info
+ * @id: RZ/G2L power domain ID
+ */
+struct rzg2l_cpg_pd {
+ struct generic_pm_domain genpd;
+ struct rzg2l_cpg_priv *priv;
+ struct rzg2l_cpg_pm_domain_conf conf;
+ u16 id;
+};
+
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
{
- struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
+ struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
+ struct rzg2l_cpg_priv *priv = pd->priv;
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
bool once = true;
@@ -1617,31 +1639,194 @@ static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device
}
static void rzg2l_cpg_genpd_remove(void *data)
+{
+ struct genpd_onecell_data *celldata = data;
+
+ for (unsigned int i = 0; i < celldata->num_domains; i++)
+ pm_genpd_remove(celldata->domains[i]);
+}
+
+static void rzg2l_cpg_genpd_remove_simple(void *data)
{
pm_genpd_remove(data);
}
+static int rzg2l_cpg_power_on(struct generic_pm_domain *domain)
+{
+ struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
+ struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
+ struct rzg2l_cpg_reg_conf pwrdn = pd->conf.pwrdn;
+ struct rzg2l_cpg_priv *priv = pd->priv;
+
+ /* Set PWRDN. */
+ if (pwrdn.mask)
+ writel(pwrdn.mask << 16, priv->base + pwrdn.off);
+
+ /* Set MSTOP. */
+ if (mstop.mask)
+ writel(mstop.mask << 16, priv->base + mstop.off);
+
+ return 0;
+}
+
+static int rzg2l_cpg_power_off(struct generic_pm_domain *domain)
+{
+ struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
+ struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
+ struct rzg2l_cpg_reg_conf pwrdn = pd->conf.pwrdn;
+ struct rzg2l_cpg_priv *priv = pd->priv;
+
+ /* Set MSTOP. */
+ if (mstop.mask)
+ writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off);
+
+ /* Set PWRDN. */
+ if (pwrdn.mask)
+ writel(pwrdn.mask | (pwrdn.mask << 16), priv->base + pwrdn.off);
+
+ return 0;
+}
+
+static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on)
+{
+ struct dev_power_governor *governor;
+
+ pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
+ pd->genpd.attach_dev = rzg2l_cpg_attach_dev;
+ pd->genpd.detach_dev = rzg2l_cpg_detach_dev;
+ if (always_on) {
+ pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON;
+ governor = &pm_domain_always_on_gov;
+ } else {
+ pd->genpd.power_on = rzg2l_cpg_power_on;
+ pd->genpd.power_off = rzg2l_cpg_power_off;
+ governor = &simple_qos_governor;
+ }
+
+ return pm_genpd_init(&pd->genpd, governor, !always_on);
+}
+
static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
{
struct device *dev = priv->dev;
struct device_node *np = dev->of_node;
- struct generic_pm_domain *genpd = &priv->genpd;
+ struct rzg2l_cpg_pd *pd;
int ret;
- genpd->name = np->name;
- genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
- GENPD_FLAG_ACTIVE_WAKEUP;
- genpd->attach_dev = rzg2l_cpg_attach_dev;
- genpd->detach_dev = rzg2l_cpg_detach_dev;
- ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
+ pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return -ENOMEM;
+
+ pd->genpd.name = np->name;
+ pd->priv = priv;
+ ret = rzg2l_cpg_pd_setup(pd, true);
if (ret)
return ret;
- ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
+ ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove_simple, &pd->genpd);
if (ret)
return ret;
- return of_genpd_add_provider_simple(np, genpd);
+ return of_genpd_add_provider_simple(np, &pd->genpd);
+}
+
+static struct generic_pm_domain *
+rzg2l_cpg_pm_domain_xlate(const struct of_phandle_args *spec, void *data)
+{
+ struct generic_pm_domain *domain = ERR_PTR(-ENOENT);
+ struct genpd_onecell_data *genpd = data;
+
+ if (spec->args_count != 1)
+ return ERR_PTR(-EINVAL);
+
+ for (unsigned int i = 0; i < genpd->num_domains; i++) {
+ struct rzg2l_cpg_pd *pd = container_of(genpd->domains[i], struct rzg2l_cpg_pd,
+ genpd);
+
+ if (pd->id == spec->args[0]) {
+ domain = &pd->genpd;
+ break;
+ }
+ }
+
+ return domain;
+}
+
+static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv)
+{
+ const struct rzg2l_cpg_info *info = priv->info;
+ struct device *dev = priv->dev;
+ struct device_node *np = dev->of_node;
+ struct rzg2l_cpg_pm_domains *domains;
+ struct generic_pm_domain *parent;
+ u32 ncells;
+ int ret;
+
+ ret = of_property_read_u32(np, "#power-domain-cells", &ncells);
+ if (ret)
+ return ret;
+
+ /* For backward compatibility. */
+ if (!ncells)
+ return rzg2l_cpg_add_clk_domain(priv);
+
+ domains = devm_kzalloc(dev, struct_size(domains, domains, info->num_pm_domains),
+ GFP_KERNEL);
+ if (!domains)
+ return -ENOMEM;
+
+ domains->onecell_data.domains = domains->domains;
+ domains->onecell_data.num_domains = info->num_pm_domains;
+ domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate;
+
+ ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data);
+ if (ret)
+ return ret;
+
+ for (unsigned int i = 0; i < info->num_pm_domains; i++) {
+ bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON);
+ struct rzg2l_cpg_pd *pd;
+
+ pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return -ENOMEM;
+
+ pd->genpd.name = info->pm_domains[i].name;
+ pd->conf = info->pm_domains[i].conf;
+ pd->id = info->pm_domains[i].id;
+ pd->priv = priv;
+
+ ret = rzg2l_cpg_pd_setup(pd, always_on);
+ if (ret)
+ return ret;
+
+ if (always_on) {
+ ret = rzg2l_cpg_power_on(&pd->genpd);
+ if (ret)
+ return ret;
+ }
+
+ domains->domains[i] = &pd->genpd;
+ /* Parent should be on the very first entry of info->pm_domains[]. */
+ if (!i) {
+ parent = &pd->genpd;
+ continue;
+ }
+
+ ret = pm_genpd_add_subdomain(parent, &pd->genpd);
+ if (ret)
+ return ret;
+ }
+
+ ret = of_genpd_add_provider_onecell(np, &domains->onecell_data);
+ if (ret)
+ return ret;
+
+ /* Prepare for power down the BUSes in power down mode. */
+ if (info->pm_domain_pwrdn_mstop)
+ writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP);
+
+ return 0;
}
static int __init rzg2l_cpg_probe(struct platform_device *pdev)
@@ -1697,7 +1882,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
if (error)
return error;
- error = rzg2l_cpg_add_clk_domain(priv);
+ error = rzg2l_cpg_add_pm_domains(priv);
if (error)
return error;
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 6e38c8fc888c..d9a7357c4873 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -27,6 +27,21 @@
#define CPG_PL6_ETH_SSEL (0x418)
#define CPG_PL5_SDIV (0x420)
#define CPG_RST_MON (0x680)
+#define CPG_BUS_ACPU_MSTOP (0xB60)
+#define CPG_BUS_MCPU1_MSTOP (0xB64)
+#define CPG_BUS_MCPU2_MSTOP (0xB68)
+#define CPG_BUS_PERI_COM_MSTOP (0xB6C)
+#define CPG_BUS_PERI_CPU_MSTOP (0xB70)
+#define CPG_BUS_PERI_DDR_MSTOP (0xB74)
+#define CPG_BUS_REG0_MSTOP (0xB7C)
+#define CPG_BUS_REG1_MSTOP (0xB80)
+#define CPG_BUS_TZCDDR_MSTOP (0xB84)
+#define CPG_MHU_MSTOP (0xB88)
+#define CPG_BUS_MCPU3_MSTOP (0xB90)
+#define CPG_BUS_PERI_CPU2_MSTOP (0xB94)
+#define CPG_PWRDN_IP1 (0xBB0)
+#define CPG_PWRDN_IP2 (0xBB4)
+#define CPG_PWRDN_MSTOP (0xBC0)
#define CPG_OTHERFUNC1_REG (0xBE8)
#define CPG_SIPLL5_STBY_RESETB BIT(0)
@@ -70,6 +85,8 @@
#define EXTAL_FREQ_IN_MEGA_HZ (24)
+#define CPG_PWRDN_MSTOP_ENABLE (BIT(16) | BIT(0))
+
/**
* Definitions of CPG Core Clocks
*
@@ -234,6 +251,58 @@ struct rzg2l_reset {
#define DEF_RST(_id, _off, _bit) \
DEF_RST_MON(_id, _off, _bit, -1)
+/**
+ * struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure
+ * @off: register offset
+ * @mask: register mask
+ */
+struct rzg2l_cpg_reg_conf {
+ u16 off;
+ u16 mask;
+};
+
+#define DEF_REG_CONF(_off, _mask) ((struct rzg2l_cpg_reg_conf) { .off = (_off), .mask = (_mask) })
+
+/**
+ * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
+ * @mstop: MSTOP register configuration
+ * @pwrdn: PWRDN register configuration
+ */
+struct rzg2l_cpg_pm_domain_conf {
+ struct rzg2l_cpg_reg_conf mstop;
+ struct rzg2l_cpg_reg_conf pwrdn;
+};
+
+/**
+ * struct rzg2l_cpg_pm_domain_init_data - PM domain init data
+ * @name: PM domain name
+ * @conf: PM domain configuration
+ * @flags: RZG2L PM domain flags (see RZG2L_PD_F_*)
+ * @id: PM domain ID (similar to the ones defined in
+ * include/dt-bindings/clock/<soc-id>-cpg.h)
+ */
+struct rzg2l_cpg_pm_domain_init_data {
+ const char * const name;
+ struct rzg2l_cpg_pm_domain_conf conf;
+ u32 flags;
+ u16 id;
+};
+
+#define DEF_PD(_name, _id, _mstop_conf, _pwrdn_conf, _flags) \
+ { \
+ .name = (_name), \
+ .id = (_id), \
+ .conf = { \
+ .mstop = (_mstop_conf), \
+ .pwrdn = (_pwrdn_conf), \
+ }, \
+ .flags = (_flags), \
+ }
+
+/* Power domain flags. */
+#define RZG2L_PD_F_ALWAYS_ON BIT(0)
+#define RZG2L_PD_F_NONE (0)
+
/**
* struct rzg2l_cpg_info - SoC-specific CPG Description
*
@@ -252,6 +321,9 @@ struct rzg2l_reset {
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
* should not be disabled without a knowledgeable driver
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
+ * @pm_domains: PM domains init data array
+ * @num_pm_domains: Number of PM domains
+ * @pm_domain_pwrdn_mstop: Specifies if PWRDN MSTOP is supported
* @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
*/
struct rzg2l_cpg_info {
@@ -278,6 +350,11 @@ struct rzg2l_cpg_info {
const unsigned int *crit_mod_clks;
unsigned int num_crit_mod_clks;
+ /* Power domain. */
+ const struct rzg2l_cpg_pm_domain_init_data *pm_domains;
+ unsigned int num_pm_domains;
+ bool pm_domain_pwrdn_mstop;
+
bool has_clk_mon_regs;
};
--
2.39.2
^ permalink raw reply related
* [PATCH v3 7/9] clk: renesas: r9a08g045: Add support for power domains
From: Claudiu @ 2024-04-10 12:26 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
magnus.damm
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel,
claudiu.beznea, Claudiu Beznea
In-Reply-To: <20240410122657.2051132-1-claudiu.beznea.uj@bp.renesas.com>
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Instantiate power domains for the currently enabled IPs of R9A08G045 SoC.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v3:
- collected tags
Change in v2:
- used DEF_REG_CONF() to describe register offests and bits
- updated MSTOP bitmask for ddr domain
- updated MSTOP config for oftde_ddr
- kept the same description for gic as the CPG_BUS_ACPU_MSTOP register
documentation in the latest HW manual version is wrong and it will be
fixed; proper description for GIC is located in "Registers for Module
Standby Mode" table
- haven't added watchdog domain (was missing in v1, too, by mistake) as
the watchdog restart handler will fail w/o patch [1]; with this pm domain
support the watchdog will fail to probe; not sure what is the best
option until [1] will be integrated
[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20240228083253.2640997-10-claudiu.beznea.uj@bp.renesas.com
drivers/clk/renesas/r9a08g045-cpg.c | 61 +++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index c3e6da2de197..c64769082f5b 100644
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -240,6 +240,62 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
};
+static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
+ /* Keep always-on domain on the first position for proper domains registration. */
+ DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON,
+ DEF_REG_CONF(0, 0),
+ DEF_REG_CONF(0, 0),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("gic", R9A08G045_PD_GIC,
+ DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),
+ DEF_REG_CONF(CPG_PWRDN_IP1, BIT(2)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("ia55", R9A08G045_PD_IA55,
+ DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),
+ DEF_REG_CONF(CPG_PWRDN_IP1, BIT(3)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("dmac", R9A08G045_PD_DMAC,
+ DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),
+ DEF_REG_CONF(0, 0),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("ddr", R9A08G045_PD_DDR,
+ DEF_REG_CONF(CPG_BUS_PERI_DDR_MSTOP, GENMASK(1, 0)),
+ DEF_REG_CONF(CPG_PWRDN_IP2, BIT(0)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("tzcddr", R9A08G045_PD_TZCDDR,
+ DEF_REG_CONF(CPG_BUS_TZCDDR_MSTOP, GENMASK(2, 0)),
+ DEF_REG_CONF(CPG_PWRDN_IP2, BIT(1)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("otfde_ddr", R9A08G045_PD_OTFDE_DDR,
+ DEF_REG_CONF(CPG_BUS_PERI_CPU2_MSTOP, BIT(2)),
+ DEF_REG_CONF(CPG_PWRDN_IP2, BIT(2)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("sdhi0", R9A08G045_PD_SDHI0,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)),
+ DEF_REG_CONF(CPG_PWRDN_IP1, BIT(13)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("sdhi1", R9A08G045_PD_SDHI1,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)),
+ DEF_REG_CONF(CPG_PWRDN_IP1, BIT(14)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("sdhi2", R9A08G045_PD_SDHI2,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)),
+ DEF_REG_CONF(CPG_PWRDN_IP1, BIT(15)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("eth0", R9A08G045_PD_ETHER0,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)),
+ DEF_REG_CONF(CPG_PWRDN_IP1, BIT(11)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("eth1", R9A08G045_PD_ETHER1,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
+ DEF_REG_CONF(CPG_PWRDN_IP1, BIT(12)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("scif0", R9A08G045_PD_SCIF0,
+ DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
+ DEF_REG_CONF(0, 0),
+ RZG2L_PD_F_NONE),
+};
+
const struct rzg2l_cpg_info r9a08g045_cpg_info = {
/* Core Clocks */
.core_clks = r9a08g045_core_clks,
@@ -260,5 +316,10 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = {
.resets = r9a08g045_resets,
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
+ /* Power domains */
+ .pm_domains = r9a08g045_pm_domains,
+ .num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains),
+ .pm_domain_pwrdn_mstop = true,
+
.has_clk_mon_regs = true,
};
--
2.39.2
^ permalink raw reply related
* [PATCH v3 8/9] clk: renesas: rzg2l-cpg: Add suspend/resume support for power domains
From: Claudiu @ 2024-04-10 12:26 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
magnus.damm
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel,
claudiu.beznea, Claudiu Beznea
In-Reply-To: <20240410122657.2051132-1-claudiu.beznea.uj@bp.renesas.com>
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
RZ/G3S supports deep sleep states that it can reach with the help of the
TF-A.
RZ/G3S has a few power domains (e.g. GIC) that need to be always-on while
Linux is running. These domains are initialized (and powered on) when
clock driver is probed.
As the TF-A takes control at the very last(suspend)/first(resume)
phase of configuring the deep sleep state, it can do it's own settings on
power domains.
Thus, to restore the proper Linux state, add rzg2l_cpg_resume() which
powers on the always-on domains and rzg2l_cpg_complete() which activates
the power down mode for the IPs selected through CPG_PWRDN_IP{1, 2}.
Along with it, added the suspend_check member to the RZ/G2L power domain
data structure whose purpose is to checks if a domain can be powered off
while the system is going to suspend. This is necessary for the serial
console domain which needs to be powered on if no_console_suspend is
available in bootargs.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v3:
- populate pd->suspend_check on rzg2l_cpg_attach_dev() for serial
console; due to this the rzg2l_pd_suspend_check_console() was moved
before rzg2l_cpg_attach_dev()
- removed RZG2L_PD_F_CONSOLE define
Changes in v2:
- none; this patch is new
drivers/clk/renesas/rzg2l-cpg.c | 68 ++++++++++++++++++++++++++++++---
1 file changed, 63 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index b36700f4a9f5..baf08a8cc3f0 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -15,6 +15,7 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/renesas.h>
+#include <linux/console.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
@@ -139,6 +140,7 @@ struct rzg2l_pll5_mux_dsi_div_param {
* @num_resets: Number of Module Resets in info->resets[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @info: Pointer to platform data
+ * @domains: generic PM domains
* @mux_dsi_div_params: pll5 mux and dsi div parameters
*/
struct rzg2l_cpg_priv {
@@ -155,6 +157,8 @@ struct rzg2l_cpg_priv {
const struct rzg2l_cpg_info *info;
+ struct generic_pm_domain **domains;
+
struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
};
@@ -1570,16 +1574,23 @@ struct rzg2l_cpg_pm_domains {
* struct rzg2l_cpg_pd - RZ/G2L power domain data structure
* @genpd: generic PM domain
* @priv: pointer to CPG private data structure
+ * @suspend_check: check if domain could be powered off in suspend
* @conf: CPG PM domain configuration info
* @id: RZ/G2L power domain ID
*/
struct rzg2l_cpg_pd {
struct generic_pm_domain genpd;
struct rzg2l_cpg_priv *priv;
+ int (*suspend_check)(void);
struct rzg2l_cpg_pm_domain_conf conf;
u16 id;
};
+static int rzg2l_pd_suspend_check_console(void)
+{
+ return console_suspend_enabled ? 0 : -EBUSY;
+}
+
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
{
struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
@@ -1615,6 +1626,10 @@ static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device
error);
goto fail_put;
}
+
+ /* Add suspend check for console. */
+ if (np == of_stdout)
+ pd->suspend_check = rzg2l_pd_suspend_check_console;
} else {
of_node_put(clkspec.np);
}
@@ -1676,6 +1691,13 @@ static int rzg2l_cpg_power_off(struct generic_pm_domain *domain)
struct rzg2l_cpg_reg_conf pwrdn = pd->conf.pwrdn;
struct rzg2l_cpg_priv *priv = pd->priv;
+ if (pd->suspend_check) {
+ int ret = pd->suspend_check();
+
+ if (ret)
+ return ret;
+ }
+
/* Set MSTOP. */
if (mstop.mask)
writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off);
@@ -1687,8 +1709,9 @@ static int rzg2l_cpg_power_off(struct generic_pm_domain *domain)
return 0;
}
-static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on)
+static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, u32 flags)
{
+ bool always_on = !!(flags & RZG2L_PD_F_ALWAYS_ON);
struct dev_power_governor *governor;
pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
@@ -1719,7 +1742,7 @@ static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
pd->genpd.name = np->name;
pd->priv = priv;
- ret = rzg2l_cpg_pd_setup(pd, true);
+ ret = rzg2l_cpg_pd_setup(pd, RZG2L_PD_F_ALWAYS_ON);
if (ret)
return ret;
@@ -1778,13 +1801,13 @@ static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv)
domains->onecell_data.domains = domains->domains;
domains->onecell_data.num_domains = info->num_pm_domains;
domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate;
+ priv->domains = domains->domains;
ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data);
if (ret)
return ret;
for (unsigned int i = 0; i < info->num_pm_domains; i++) {
- bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON);
struct rzg2l_cpg_pd *pd;
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
@@ -1796,11 +1819,11 @@ static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv)
pd->id = info->pm_domains[i].id;
pd->priv = priv;
- ret = rzg2l_cpg_pd_setup(pd, always_on);
+ ret = rzg2l_cpg_pd_setup(pd, info->pm_domains[i].flags);
if (ret)
return ret;
- if (always_on) {
+ if (info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON) {
ret = rzg2l_cpg_power_on(&pd->genpd);
if (ret)
return ret;
@@ -1890,9 +1913,43 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
if (error)
return error;
+ dev_set_drvdata(dev, priv);
+
+ return 0;
+}
+
+static int rzg2l_cpg_resume(struct device *dev)
+{
+ struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev);
+ const struct rzg2l_cpg_info *info = priv->info;
+
+ /* Power on always ON domains. */
+ for (unsigned int i = 0; i < info->num_pm_domains; i++) {
+ if (info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON) {
+ int ret = rzg2l_cpg_power_on(priv->domains[i]);
+
+ if (ret)
+ return ret;
+ }
+ }
+
return 0;
}
+static void rzg2l_cpg_complete(struct device *dev)
+{
+ struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev);
+
+ /* Prepare for power down the BUSes in power down mode. */
+ if (priv->info->pm_domain_pwrdn_mstop)
+ writel(CPG_PWRDN_MSTOP_ENABLE, priv->base + CPG_PWRDN_MSTOP);
+}
+
+static const struct dev_pm_ops rzg2l_cpg_pm_ops = {
+ NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, rzg2l_cpg_resume)
+ .complete = rzg2l_cpg_complete,
+};
+
static const struct of_device_id rzg2l_cpg_match[] = {
#ifdef CONFIG_CLK_R9A07G043
{
@@ -1931,6 +1988,7 @@ static struct platform_driver rzg2l_cpg_driver = {
.driver = {
.name = "rzg2l-cpg",
.of_match_table = rzg2l_cpg_match,
+ .pm = pm_sleep_ptr(&rzg2l_cpg_pm_ops),
},
};
--
2.39.2
^ permalink raw reply related
* [PATCH v3 9/9] arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1>
From: Claudiu @ 2024-04-10 12:26 UTC (permalink / raw)
To: geert+renesas, mturquette, sboyd, robh, krzk+dt, conor+dt,
magnus.damm
Cc: linux-renesas-soc, linux-clk, devicetree, linux-kernel,
claudiu.beznea, Claudiu Beznea
In-Reply-To: <20240410122657.2051132-1-claudiu.beznea.uj@bp.renesas.com>
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Update CPG #power-domain-cells = <1> and move all the IPs to be part of the
IP specific power domain as the driver has been modified to support
multiple power domains.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v3:
- collected tags
Changes in v2:
- used proper domain ID for IA55 interrupt controller
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index f5f3f4f4c8d6..bdd4f9376fc0 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -67,7 +67,7 @@ scif0: serial@1004b800 {
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
clock-names = "fck";
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SCIF0>;
resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
status = "disabled";
};
@@ -79,7 +79,7 @@ cpg: clock-controller@11010000 {
clock-names = "extal";
#clock-cells = <2>;
#reset-cells = <1>;
- #power-domain-cells = <0>;
+ #power-domain-cells = <1>;
};
sysc: system-controller@11020000 {
@@ -104,7 +104,7 @@ pinctrl: pinctrl@11030000 {
interrupt-parent = <&irqc>;
gpio-ranges = <&pinctrl 0 0 152>;
clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_ALWAYS_ON>;
resets = <&cpg R9A08G045_GPIO_RSTN>,
<&cpg R9A08G045_GPIO_PORT_RESETN>,
<&cpg R9A08G045_GPIO_SPARE_RESETN>;
@@ -177,7 +177,7 @@ irqc: interrupt-controller@11050000 {
clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
<&cpg CPG_MOD R9A08G045_IA55_PCLK>;
clock-names = "clk", "pclk";
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_IA55>;
resets = <&cpg R9A08G045_IA55_RESETN>;
};
@@ -192,7 +192,7 @@ sdhi0: mmc@11c00000 {
<&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A08G045_SDHI0_IXRST>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SDHI0>;
status = "disabled";
};
@@ -207,7 +207,7 @@ sdhi1: mmc@11c10000 {
<&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A08G045_SDHI1_IXRST>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SDHI1>;
status = "disabled";
};
@@ -222,7 +222,7 @@ sdhi2: mmc@11c20000 {
<&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A08G045_SDHI2_IXRST>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SDHI2>;
status = "disabled";
};
@@ -239,7 +239,7 @@ eth0: ethernet@11c30000 {
<&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_ETHER0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -258,7 +258,7 @@ eth1: ethernet@11c40000 {
<&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_ETHER1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -284,7 +284,7 @@ wdt0: watchdog@12800800 {
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A08G045_WDT0_PRESETN>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_WDT0>;
status = "disabled";
};
};
--
2.39.2
^ permalink raw reply related
* Re: [PATCH v3 2/9] arm64: dts: qcom: sc8180x: correct dispcc clocks
From: Konrad Dybcio @ 2024-04-10 12:31 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss
In-Reply-To: <20240401-typec-fix-sm8250-v3-2-604dce3ad103@linaro.org>
On 4/1/24 22:33, Dmitry Baryshkov wrote:
> Correct the clocks being used by the display clock controller on the
> SC8180X platform (to match the schema):
> - Drop the sleep clock
> - Add DSI clocks
> - Reorder eDP / DP clocks
>
> This changes the order of clocks, however it should be noted that the
> clock list was neither correct nor followed the schema beforehand.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply
* Re: [PATCH v3 5/9] arm64: dts: qcom: sc8180x: switch USB+DP QMP PHYs to new bindings
From: Konrad Dybcio @ 2024-04-10 12:33 UTC (permalink / raw)
To: Dmitry Baryshkov, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, Luca Weiss
In-Reply-To: <20240401-typec-fix-sm8250-v3-5-604dce3ad103@linaro.org>
On 4/1/24 22:33, Dmitry Baryshkov wrote:
> To follow other Qualcomm platforms, update QMP USB+DP PHYs to use newer
> bindings rather than old bindings which had PHYs as subdevices.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
[...]
> usb_sec_qmpphy: phy@88ee000 {
This unit address also needs to be updated
LGTM otherwise
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply
* Re: [RFC PATCH v2 0/2] fw_devlink overlay fix
From: Herve Codina @ 2024-04-10 12:35 UTC (permalink / raw)
To: Saravana Kannan
Cc: Geert Uytterhoeven, Rob Herring, kernel-team, linux-kernel, imx,
linux-arm-kernel, linux-i2c, devicetree, linux-spi, linux-acpi,
Luca Ceresoli, Thomas Petazzoni
In-Reply-To: <CAGETcx-Yxtkdfytsota3AciS6M9UeOaKSRtaHfH5pm60KWVmJA@mail.gmail.com>
Hi Saravana,
On Tue, 9 Apr 2024 18:06:33 -0700
Saravana Kannan <saravanak@google.com> wrote:
> On Tue, Apr 9, 2024 at 6:02 AM Herve Codina <herve.codina@bootlin.com> wrote:
> >
> > Hi Saravana,
> >
> > +CC Luca and Thomas
> >
> > On Mon, 8 Apr 2024 22:37:01 -0700
> > Saravana Kannan <saravanak@google.com> wrote:
> >
> > > Don't bother reviewing this patch. It needs to be tested and possibly
> > > refactored first.
> > >
> > > Geert and Herve,
> > >
> > > This patch serious should hopefully fix both of your use cases
> > > [1][2][3]. Can you please check to make sure the device links created
> > > to/from the overlay devices are to/from the right ones?
> > >
> > > I've only compile tested it. If I made some obvious mistake, feel free
> > > to fix it and give it a shot.
> > >
> > > Cc: Rob Herring <robh@kernel.org>
> > >
> > > [1] - https://lore.kernel.org/lkml/CAMuHMdXEnSD4rRJ-o90x4OprUacN_rJgyo8x6=9F9rZ+-KzjOg@mail.gmail.com/
> > > [2] - https://lore.kernel.org/all/20240221095137.616d2aaa@bootlin.com/
> > > [3] - https://lore.kernel.org/lkml/20240312151835.29ef62a0@bootlin.com/
> > >
> >
> > I tested your patches.
> >
> > Concerning my use cases, they fix the issue described in
> > https://lore.kernel.org/all/20240221095137.616d2aaa@bootlin.com/
>
> I went back and looked at the example. I'm not even sure I understand
> that example. In that example at the link above, are you saying
> without any changes to upstream reg_dock_sys_3v3 was listing it's
> supplier as i2c5 instead of tca6424_dock_1? Why wasn't Geert's
> existing changes in of_i2c_notify not sufficient? Looking at it, it
> does:
> rd->dn->fwnode.flags &= ~FWNODE_FLAG_NOT_DEVICE;
>
> Which should clear the flag for tca6424_dock_1. Can you help me
> understand why it's not getting cleared?
I don't really know but I can mke some asumptions.
Maybe the link involved in the issue is created quite early in the overlay
applying process, before the calls to the of notifier of_i2c_notify() that
can clear the FWNODE_FLAG_NOT_DEVICE.
The link is created by of_link_to_phandle(). This functions is triggered
from of_fwnode_add_links() which is the .add_link() operation of the OF
fwnode_operations.
The operation is called by fw_devlink_parse_fwnode(), itself triggered by
fw_devlink_link_device() each time device_add() is called.
If the device_add() related to the reg_dock_sys_3v3 is called before the
of_i2c_notify() related to tca6424_dock_1, the FWNODE_FLAG_NOT_DEVICE flag
in tca6424_dock_1 is not cleared when of_link_to_phandle() is called.
Does this scenario make sense ?
>
> > But not the one described in
> > https://lore.kernel.org/lkml/20240312151835.29ef62a0@bootlin.com/
> > A link is still present between the i2c@600 and the PCI device.
> > instead of the i2c@600 and the pci-ep-bus.
>
> What do you mean by PCI device here? You say the same thing in the
> link, but I don't understand what you mean. Can you clarify what
> exactly gets added by the overlay? Please use the fwnode name in all
> the descriptions, even when talking about device links. That should
> help avoid the confusion.
>
> Also, if you can show what the target node of the overlay looks like,
> that'd help too.
>
> > Adding the patch clearing the FWNODE_FLAG_NOT_DEVICE in device_add() available
> > at [1] on top of your patches fixes the link issue.
> > With this additional patch applied, the link is present between the i2c@600
> > and the pci-ep-bus.
>
> I know the problem with this patch series. But to fix it properly, I
> need to understand the root of the overlay node in your examples and
> the target it's applied to.
This is the Microchip Lan966x PCI device use case.
The Lan966x is a component that can be a "standard" SoC (i.e. core CPUs
and some peripherals) or as a PCI device.
When in PCI device mode, the core CPUs are not available and are replaced
by an endpoint PCI. The PCI host in PCI device mode has to act the code CPUs
in SoC mode. In other word the PCI host has access to peripherals (PCI MMIO
accesses) and has to handle each peripherals.
Drivers for these peripherals are already available in the kernel (reset
controller, i2c controller, network switch, clock controllers, ...) and are
functional when the Lan966x is in SoC mode.
In order to re-use all of these drivers, the solution was to have a Lan966x
PCI driver that is probe() matching the Lan966x PCI Vendor/Device ID.
This driver then load a DT overlay to described the Lan966x internal components.
Basically, the base DT (the DT describing the PCI host board) has the PCI nodes
between the root PCI node and the Lan966x PCI device built at runtime during the
PCI bus scan. At the end of the scan, the Lan966x driver load the overlay and
the final DT looks like the following:
--- 8< ---
soc {
...
pcie@d0070000 {
compatible = "marvell,armada-3700-pcie";
...
/* A bridge, created at runtime during PCI scan */
pci@0,0 {
compatible = "pci11ab,100\0pciclass,060400\0pciclass,0604";
...
/* The Lan966x PCI device, created at runtime during PCI scan */
dev@0,0 {
compatible = "pci1055,9660\0pciclass,020000\0pciclass,0200";
...
/*
* This node is added by the overlay
* during lan966x PCI driver probe()
*/
pci-ep-bus@0 {
compatible = "simple-bus";
...
flx0: flexcom@e0040000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xe0040000 0x100>;
ranges = <0x0 0xe0040000 0x800>;
...
i2c_lan966x: i2c@600 {
compatible = "microchip,lan966x-i2c";
reg = <0x600 0x200>;
...
};
};
...
};
};
};
};
};
--- 8< ---
Without clearing FWNODE_FLAG_NOT_DEVICE, a link is created between
i2c@600 and dev@0,0.
With the FWNODE_FLAG_NOT_DEVICE cleared in device_add(), the link is
created between i2c@600 and pci-ep-bus@0.
flexcom@e0040000 is a MFD device.
In the lan966x PCI driver, the overlay is applied using the following:
--- 8< ---
static int lan966x_pci_load_overlay(struct lan966x_pci *data)
{
u32 dtbo_size = __dtbo_lan966x_pci_end - __dtbo_lan966x_pci_begin;
void *dtbo_start = __dtbo_lan966x_pci_begin;
int ret;
ret = of_overlay_fdt_apply(dtbo_start, dtbo_size, &data->ovcs_id,
data->dev->of_node);
if (ret)
return ret;
return 0;
}
static int lan966x_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct device *dev = &pdev->dev;
struct lan966x_pci *data;
...
data->dev = dev;
...
ret = lan966x_pci_load_overlay(data);
if (ret)
return ret;
...
ret = of_platform_default_populate(dev->of_node, NULL, dev);
if (ret)
goto err_unload_overlay;
return 0;
...
}
--- 8< ---
Hope my explanations were clear enough and answered your question.
Feel free to ask some more details if needed.
I provided only extractions of the full dtso file. If you need some more
information (all nodes, all properties) feel free to ask.
Best regards,
Hervé
^ permalink raw reply
* Re: [PATCH] dt-bindings: firmware: arm,scmi: Update examples for protocol@13
From: Sudeep Holla @ 2024-04-10 12:35 UTC (permalink / raw)
To: Rob Herring
Cc: Ulf Hansson, Cristian Marussi, Krzysztof Kozlowski, devicetree,
linux-arm-kernel
In-Reply-To: <20240410115637.GA4042282-robh@kernel.org>
On Wed, Apr 10, 2024 at 06:56:37AM -0500, Rob Herring wrote:
> On Thu, Apr 04, 2024 at 12:52:08PM +0200, Ulf Hansson wrote:
> > On Wed, 3 Apr 2024 at 15:53, Sudeep Holla <sudeep.holla@arm.com> wrote:
> > >
> > > On Wed, Apr 03, 2024 at 01:11:06PM +0200, Ulf Hansson wrote:
> > > > Recently we extended the binding for protocol@13 to allow it to be modelled
> > > > as a generic performance domain. In a way to promote using the new binding,
> > > > let's update the examples.
> > > >
> > >
> > > Does it make sense to keep one DVFS example with #clock-cells until we
> > > mark it as deprecated ? Otherwise it may be confusing as the binding still
> > > lists. Or leave some comment in the example or something, I am open for
> > > suggestions.
> >
> > I am certainly fine with either way!
> >
> > However, if we intend to make #clock-cells deprecated down the road,
> > maybe it's better to start avoiding the use of it already now. That
> > said, what do you think of following up $subject patch with an update
> > to Juno's dts(i) to move to #power-domains-cells too? That would mean
> > we get a nice reference for how to use this too.
> >
> > >
> > > Other than that,
> > >
> > > Acked-by: Sudeep Holla <sudeep.holla@arm.com>
> >
> > Are you picking this via your scmi tree, or which route is this going?
>
Sorry Ulf, this slipped through the cracks, will queue it.
> Please take via SCMI tree.
>
Sure
> Acked-by: Rob Herring <robh@kernel.org>
Thanks
--
Regards,
Sudeep
^ permalink raw reply
* Re: [PATCH v4 01/18] ASoC: mediatek: Add common machine soundcard driver probe mechanism
From: Alexandre Mergnat @ 2024-04-10 12:42 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, broonie
Cc: wenst, lgirdwood, robh, krzysztof.kozlowski+dt, conor+dt,
matthias.bgg, perex, tiwai, trevor.wu, maso.huang, xiazhengqiao,
arnd, kuninori.morimoto.gx, shraash, nicolas.ferre,
u.kleine-koenig, dianders, frank.li, allen-kh.cheng,
eugen.hristev, claudiu.beznea, jarkko.nikula, jiaxin.yu,
alpernebiyasak, ckeepax, zhourui, nfraprado, alsa-devel,
shane.chien, linux-sound, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, kernel
In-Reply-To: <20240409113310.303261-2-angelogioacchino.delregno@collabora.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
On 09/04/2024 13:32, AngeloGioacchino Del Regno wrote:
> Add a common machine soundcard driver probe function that supports both
> DSP and AFE-direct usecases and also provides a hook for legacy machine
> soundcard driver probe mechanisms.
>
> Note that the hook is there because, even for legacy probe, a lot of the
> actual code can still be commonized, hence still reducing duplication
> for the legacy devicetree retrocompatibility cases.
>
> This common probe function deprecates all of the inconsistent previous
> probe mechanisms and aims to settle all of the MediaTek card drivers on
> consistent and common devicetree properties describing wanted DAIs,
> device specific DAI configuration and DAI links to codecs found on
> each device/board.
--
Regards,
Alexandre
^ permalink raw reply
* Re: [PATCH v4 02/18] ASoC: mediatek: common: Constify struct mtk_sof_priv
From: Alexandre Mergnat @ 2024-04-10 12:46 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, broonie
Cc: wenst, lgirdwood, robh, krzysztof.kozlowski+dt, conor+dt,
matthias.bgg, perex, tiwai, trevor.wu, maso.huang, xiazhengqiao,
arnd, kuninori.morimoto.gx, shraash, nicolas.ferre,
u.kleine-koenig, dianders, frank.li, allen-kh.cheng,
eugen.hristev, claudiu.beznea, jarkko.nikula, jiaxin.yu,
alpernebiyasak, ckeepax, zhourui, nfraprado, alsa-devel,
shane.chien, linux-sound, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, kernel
In-Reply-To: <20240409113310.303261-3-angelogioacchino.delregno@collabora.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
On 09/04/2024 13:32, AngeloGioacchino Del Regno wrote:
> Apart from a dai_link_list variable, the mtk_sof_priv currently holds
> data that never gets modified during runtime.
>
> Constify the mtk_sof_priv structure and move the SOF dai_link_list as
> sof_dai_link_list in struct mtk_soc_card_data, which is a structure
> that already holds the card's machine specific, runtime modified data.
>
> This allows to safely pass the mtk_sof_priv structure as platform data
> for the commonized card probe mechanism.
--
Regards,
Alexandre
^ permalink raw reply
* [PATCH v7 00/16] power: sequencing: implement the subsystem and add first users
From: Bartosz Golaszewski @ 2024-04-10 12:46 UTC (permalink / raw)
To: Marcel Holtmann, Luiz Augusto von Dentz, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kalle Valo, Bjorn Andersson,
Konrad Dybcio, Liam Girdwood, Mark Brown, Catalin Marinas,
Will Deacon, Bjorn Helgaas, Bartosz Golaszewski, Saravana Kannan,
Geert Uytterhoeven, Arnd Bergmann, Neil Armstrong,
Marek Szyprowski, Alex Elder, Srini Kandagatla,
Greg Kroah-Hartman, Abel Vesa, Manivannan Sadhasivam,
Lukas Wunner, Dmitry Baryshkov, Amit Pundir, Xilin Wu
Cc: linux-bluetooth, netdev, devicetree, linux-kernel, linux-wireless,
linux-arm-msm, linux-arm-kernel, linux-pci, linux-pm,
Bartosz Golaszewski
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Problem statement #1: Dynamic bus chicken-and-egg problem.
Certain on-board PCI devices need to be powered up before they are can be
detected but their PCI drivers won't get bound until the device is
powered-up so enabling the relevant resources in the PCI device driver
itself is impossible.
Problem statement #2: Sharing inter-dependent resources between devices.
Certain devices that use separate drivers (often on different busses)
share resources (regulators, clocks, etc.). Typically these resources
are reference-counted but in some cases there are additional interactions
between them to consider, for example specific power-up sequence timings.
===
The reason for tackling both of these problems in a single series is the
fact the the platform I'm working on - Qualcomm RB5 - deals with both and
both need to be addressed in order to enable WLAN and Bluetooth support
upstream.
The on-board WLAN/BT package - QCA6391 - has a Power Management Unit that
takes inputs from the host and exposes LDO outputs consumed by the BT and
WLAN modules which can be powered-up and down independently. However
a delay of 100ms must be respected between enabling the BT- and
WLAN-enable GPIOs.
A similar design with a discreet PMU is also employed in other models of
the WCN family of chips although we can often do without the delays. With
this series we add support for the WCN7850 as well.
===
We introduce a new subsystem here - the power sequencing framework. The
qcom-wcn driver that we add is its first user. It implements the power-up
sequences for QCA6390 and WCN7850 chips. However - we only use it to
power-up the bluetooth module in the former. We use it to driver the WLAN
modules in both. The reason for this is that for WCN7850 we have
comprehensive bindings already upstream together with existing DT users.
Porting them to using the pwrseq subsystem can be done separately and in
an incremental manner once the subsystem itself is upstream. We will also
have to ensure backward DT compatibility. To avoid overcomplicating this
series, let's leave it out for now.
===
This series is logically split into several sections. I'll go
patch-by-patch and explain each step.
Patches 1/16-5/16:
These contain all relevant DT bindings changes. We add new documents for
the QCA6390 & WCN7850 PMUs and ATH12K devices as well as extend the bindings
for the Qualcomm Bluetooth and ATH11K modules with regulators used by them
in QCA6390.
Patches 6/16-8/16:
These contain changes to device-tree sources for the three platforms we
work with in this series. We model the PMUs of the WLAN/BT chips as
top-level platform devices on the device tree. In order to limit the scope
of this series and not introduce an excessive amount of confusion with
deprecating DT bindings, we leave the Bluetooth nodes on sm8650 and sm8550
as is (meaning: they continue to consumer the GPIOs and power inputs from
the host). As the WCN7850 module doesn't require any specific timings, we can
incrementally change that later.
In both cases we add WLAN nodes that consume the power outputs of the PMU.
For QCA6390 we also make the Bluetooth node of the RB5 consume the outputs
of the PMU - we can do it as the bindings for this chip did not define any
supply handles prior to this series meaning we are able to get this correct
right away.
Patches 9/16-12/16:
These contain the bulk of the PCI changes for this series. We introduce
a simple framework for powering up PCI devices before detecting them on
the bus.
The general approach is as follows: PCI devices that need special
treatment before they can be powered up, scanned and bound to their PCI
drivers must be described on the device-tree as child nodes of the PCI
port node. These devices will be instantiated on the platform bus. They
will in fact be generic platform devices with the compatible of the form
used for PCI devices already upstream ("pci<vendor ID>,<device ID">). We
add a new directory under drivers/pci/pwrctl/ that contains PCI pwrctl
drivers. These drivers are platform drivers that will now be matched
against the devices instantiated from port children just like any other
platform pairs.
Both the power control platform device *AND* the associated PCI device
reuse the same OF node and have access to the same properties. The goal
of the platform driver is to request and bring up any required resources
and let the pwrctl framework know that it's now OK to rescan the bus and
detect the devices. When the device is bound, we are notified about it
by the PCI bus notifier event and can establish a device link between the
power control device and the PCI device so that any future extension for
power-management will already be able to work with the correct hierachy.
The reusing of the OF node is the reason for the small changes to the PCI
OF core: as the bootloader can possibly leave the relevant regulators on
before booting linux, the PCI device can be detected before its platform
abstraction is probed. In this case, we find that device first and mark
its OF node as reused. The pwrctl framework handles the opposite case
(when the PCI device is detected only after the platform driver
successfully enabled it).
Patch 13/16 - 14/16:
These add a relatively simple power sequencing subsystem and the first
driver using it: the pwrseq module for the PMUs on the WCN family of chips.
I'm proposing to add a subsystem that allows different devices to use a shared
power sequence split into consumer-specific as well as common "units".
A power sequence provider driver registers a set of units with pwrseq
core. Each unit can be enabled and disabled and contains an optional list
of other units which must be enabled before it itself can be. A unit
represents a discreet chunk of the power sequence.
It also registers a list of targets: a target is an abstraction wrapping
a unit which allows consumers to tell pwrseq which unit they want to
reach. Real-life example is the driver we're adding here: there's a set
of common regulators, two PCIe-specific ones and two enable GPIOs: one
for Bluetooth and one for WLAN.
The Bluetooth driver requests a descriptor to the power sequencer and
names the target it wants to reach:
pwrseq = devm_pwrseq_get(dev, "bluetooth");
The pwrseq core then knows that when the driver calls:
pwrseq_power_on(pwrseq);
It must enable the "bluetooth-enable" unit but it depends on the
"regulators-common" unit so this one is enabled first. The provider
driver is also in charge of assuring an appropriate delay between
enabling the BT and WLAN enable GPIOs. The WLAN-specific resources are
handled by the "wlan-enable" unit and so are not enabled until the WLAN
driver requests the "wlan" target to be powered on.
Another thing worth discussing is the way we associate the consumer with
the relevant power sequencer. DT maintainers have expressed a discontent
with the existing mmc pwrseq bindings and have NAKed an earlier
initiative to introduce global pwrseq bindings to the kernel[1].
In this approach, we model the existing regulators and GPIOs in DT but
the pwrseq subsystem requires each provider to provide a .match()
callback. Whenever a consumer requests a power sequencer handle, we
iterate over the list of pwrseq drivers and call .match() for each. It's
up to the driver to verify in a platform-specific way whether it deals
with its consumer and let the core pwrseq code know.
The advantage of this over reusing the regulator or reset subsystem is
that it's more generalized and can handle resources of all kinds as well
as deal with any kind of power-on sequences: for instance, Qualcomm has
a PCI switch they want a driver for but this switch requires enabling
some resources first (PCI pwrctl) and then configuring the device over
I2C (which can be handled by the pwrseq provider).
Patch 15:
This patch makes the Qualcomm Bluetooth driver get and use the power
sequencer for QCA6390.
Patch 16:
While tiny, this patch is possibly the highlight of the entire series.
It uses the two abstraction layers we introduced before to create an
elegant power sequencing PCI power control driver and supports the ath11k
module on QCA6390 and ath12k on WCN7850.
With this series we can now enable BT and WLAN on several new Qualcomm
boards upstream.
Tested on RB5, sm8650-qrd and sm8550-qrd.
Changelog:
Since v6:
- kernel doc fixes
- drop myself from the DT bindings maintainers list for ath12k
- wait until the PCI bridge device is fully added before creating the
PCI pwrctl platform devices for its sub-nodes, otherwise we may see
sysfs and procfs attribute failures (due to duplication, we're
basically trying to probe the same device twice at the same time)
- I kept the regulators for QCA6390's ath11k as required as they only
apply to this specific Qualcomm package
Since v5:
- unify the approach to modelling the WCN WLAN/BT chips by always exposing
the PMU node on the device tree and making the WLAN and BT nodes become
consumers of its power outputs; this includes a major rework of the DT
sources, bindings and driver code; there's no more a separate PCI
pwrctl driver for WCN7850, instead its power-up sequence was moved
into the pwrseq driver common for all WCN chips
- don't set load_uA from new regulator consumers
- fix reported kerneldoc issues
- drop voltage ranges for PMU outputs from DT
- many minor tweaks and reworks
v1: Original RFC:
https://lore.kernel.org/lkml/20240104130123.37115-1-brgl@bgdev.pl/T/
v2: First real patch series (should have been PATCH v2) adding what I
referred to back then as PCI power sequencing:
https://lore.kernel.org/linux-arm-kernel/2024021413-grumbling-unlivable-c145@gregkh/T/
v3: RFC for the DT representation of the PMU supplying the WLAN and BT
modules inside the QCA6391 package (was largely separate from the
series but probably should have been called PATCH or RFC v3):
https://lore.kernel.org/all/CAMRc=Mc+GNoi57eTQg71DXkQKjdaoAmCpB=h2ndEpGnmdhVV-Q@mail.gmail.com/T/
v4: Second attempt at the full series with changed scope (introduction of
the pwrseq subsystem, should have been RFC v4)
https://lore.kernel.org/lkml/20240201155532.49707-1-brgl@bgdev.pl/T/
v5: Two different ways of handling QCA6390 and WCN7850:
https://lore.kernel.org/lkml/20240216203215.40870-1-brgl@bgdev.pl/
Bartosz Golaszewski (16):
regulator: dt-bindings: describe the PMU module of the QCA6390 package
regulator: dt-bindings: describe the PMU module of the WCN7850 package
dt-bindings: net: bluetooth: qualcomm: describe regulators for QCA6390
dt-bindings: net: wireless: qcom,ath11k: describe the ath11k on
QCA6390
dt-bindings: net: wireless: describe the ath12k PCI module
arm64: dts: qcom: sm8550-qrd: add the Wifi node
arm64: dts: qcom: sm8650-qrd: add the Wifi node
arm64: dts: qcom: qrb5165-rb5: add the Wifi node
PCI: hold the rescan mutex when scanning for the first time
PCI/pwrctl: reuse the OF node for power controlled devices
PCI/pwrctl: create platform devices for child OF nodes of the port
node
PCI/pwrctl: add PCI power control core code
power: sequencing: implement the pwrseq core
power: pwrseq: add a driver for the PMU module on the QCom WCN
chipsets
Bluetooth: qca: use the power sequencer for QCA6390
PCI/pwrctl: add a PCI power control driver for power sequenced devices
.../net/bluetooth/qualcomm-bluetooth.yaml | 17 +
.../net/wireless/qcom,ath11k-pci.yaml | 46 +
.../bindings/net/wireless/qcom,ath12k.yaml | 99 ++
.../bindings/regulator/qcom,qca6390-pmu.yaml | 185 +++
MAINTAINERS | 8 +
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 103 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 +
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 97 ++
arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 +
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 89 ++
arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 +
drivers/bluetooth/hci_qca.c | 74 +-
drivers/pci/Kconfig | 1 +
drivers/pci/Makefile | 1 +
drivers/pci/bus.c | 9 +
drivers/pci/of.c | 14 +-
drivers/pci/probe.c | 2 +
drivers/pci/pwrctl/Kconfig | 17 +
drivers/pci/pwrctl/Makefile | 6 +
drivers/pci/pwrctl/core.c | 137 +++
drivers/pci/pwrctl/pci-pwrctl-pwrseq.c | 89 ++
drivers/pci/remove.c | 2 +
drivers/power/Kconfig | 1 +
drivers/power/Makefile | 1 +
drivers/power/sequencing/Kconfig | 28 +
drivers/power/sequencing/Makefile | 6 +
drivers/power/sequencing/core.c | 1065 +++++++++++++++++
drivers/power/sequencing/pwrseq-qcom-wcn.c | 336 ++++++
include/linux/pci-pwrctl.h | 51 +
include/linux/pwrseq/consumer.h | 56 +
include/linux/pwrseq/provider.h | 75 ++
31 files changed, 2615 insertions(+), 30 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml
create mode 100644 Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml
create mode 100644 drivers/pci/pwrctl/Kconfig
create mode 100644 drivers/pci/pwrctl/Makefile
create mode 100644 drivers/pci/pwrctl/core.c
create mode 100644 drivers/pci/pwrctl/pci-pwrctl-pwrseq.c
create mode 100644 drivers/power/sequencing/Kconfig
create mode 100644 drivers/power/sequencing/Makefile
create mode 100644 drivers/power/sequencing/core.c
create mode 100644 drivers/power/sequencing/pwrseq-qcom-wcn.c
create mode 100644 include/linux/pci-pwrctl.h
create mode 100644 include/linux/pwrseq/consumer.h
create mode 100644 include/linux/pwrseq/provider.h
--
2.40.1
^ permalink raw reply
* [PATCH v7 01/16] regulator: dt-bindings: describe the PMU module of the QCA6390 package
From: Bartosz Golaszewski @ 2024-04-10 12:46 UTC (permalink / raw)
To: Marcel Holtmann, Luiz Augusto von Dentz, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kalle Valo, Bjorn Andersson,
Konrad Dybcio, Liam Girdwood, Mark Brown, Catalin Marinas,
Will Deacon, Bjorn Helgaas, Bartosz Golaszewski, Saravana Kannan,
Geert Uytterhoeven, Arnd Bergmann, Neil Armstrong,
Marek Szyprowski, Alex Elder, Srini Kandagatla,
Greg Kroah-Hartman, Abel Vesa, Manivannan Sadhasivam,
Lukas Wunner, Dmitry Baryshkov, Amit Pundir, Xilin Wu
Cc: linux-bluetooth, netdev, devicetree, linux-kernel, linux-wireless,
linux-arm-msm, linux-arm-kernel, linux-pci, linux-pm,
Bartosz Golaszewski, Krzysztof Kozlowski
In-Reply-To: <20240410124628.171783-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
The QCA6390 package contains discreet modules for WLAN and Bluetooth. They
are powered by the Power Management Unit (PMU) that takes inputs from the
host and provides LDO outputs. This document describes this module.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/regulator/qcom,qca6390-pmu.yaml | 151 ++++++++++++++++++
1 file changed, 151 insertions(+)
create mode 100644 Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml
diff --git a/Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml b/Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml
new file mode 100644
index 000000000000..9d39ff9a75fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml
@@ -0,0 +1,151 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/qcom,qca6390-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. QCA6390 PMU Regulators
+
+maintainers:
+ - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
+
+description:
+ The QCA6390 package contains discreet modules for WLAN and Bluetooth. They
+ are powered by the Power Management Unit (PMU) that takes inputs from the
+ host and provides LDO outputs. This document describes this module.
+
+properties:
+ compatible:
+ const: qcom,qca6390-pmu
+
+ vddaon-supply:
+ description: VDD_AON supply regulator handle
+
+ vddpmu-supply:
+ description: VDD_PMU supply regulator handle
+
+ vddrfa0p95-supply:
+ description: VDD_RFA_0P95 supply regulator handle
+
+ vddrfa1p3-supply:
+ description: VDD_RFA_1P3 supply regulator handle
+
+ vddrfa1p9-supply:
+ description: VDD_RFA_1P9 supply regulator handle
+
+ vddpcie1p3-supply:
+ description: VDD_PCIE_1P3 supply regulator handle<S-Del>
+
+ vddpcie1p9-supply:
+ description: VDD_PCIE_1P9 supply regulator handle
+
+ vddio-supply:
+ description: VDD_IO supply regulator handle
+
+ wlan-enable-gpios:
+ maxItems: 1
+ description: GPIO line enabling the ATH11K WLAN module supplied by the PMU
+
+ bt-enable-gpios:
+ maxItems: 1
+ description: GPIO line enabling the ATH11K Bluetooth module supplied by the PMU
+
+ regulators:
+ type: object
+ description:
+ LDO outputs of the PMU
+
+ patternProperties:
+ "^ldo[0-9]$":
+ $ref: regulator.yaml#
+ type: object
+ unevaluatedProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - regulators
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,qca6390-pmu
+ then:
+ required:
+ - vddaon-supply
+ - vddpmu-supply
+ - vddrfa0p95-supply
+ - vddrfa1p3-supply
+ - vddrfa1p9-supply
+ - vddpcie1p3-supply
+ - vddpcie1p9-supply
+ - vddio-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ pmu {
+ compatible = "qcom,qca6390-pmu";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en_state>, <&wlan_en_state>;
+
+ vddaon-supply = <&vreg_s6a_0p95>;
+ vddpmu-supply = <&vreg_s2f_0p95>;
+ vddrfa0p95-supply = <&vreg_s2f_0p95>;
+ vddrfa1p3-supply = <&vreg_s8c_1p3>;
+ vddrfa1p9-supply = <&vreg_s5a_1p9>;
+ vddpcie1p3-supply = <&vreg_s8c_1p3>;
+ vddpcie1p9-supply = <&vreg_s5a_1p9>;
+ vddio-supply = <&vreg_s4a_1p8>;
+
+ wlan-enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
+ bt-enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p7: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p7";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
--
2.40.1
^ permalink raw reply related
* [PATCH v7 02/16] regulator: dt-bindings: describe the PMU module of the WCN7850 package
From: Bartosz Golaszewski @ 2024-04-10 12:46 UTC (permalink / raw)
To: Marcel Holtmann, Luiz Augusto von Dentz, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kalle Valo, Bjorn Andersson,
Konrad Dybcio, Liam Girdwood, Mark Brown, Catalin Marinas,
Will Deacon, Bjorn Helgaas, Bartosz Golaszewski, Saravana Kannan,
Geert Uytterhoeven, Arnd Bergmann, Neil Armstrong,
Marek Szyprowski, Alex Elder, Srini Kandagatla,
Greg Kroah-Hartman, Abel Vesa, Manivannan Sadhasivam,
Lukas Wunner, Dmitry Baryshkov, Amit Pundir, Xilin Wu
Cc: linux-bluetooth, netdev, devicetree, linux-kernel, linux-wireless,
linux-arm-msm, linux-arm-kernel, linux-pci, linux-pm,
Bartosz Golaszewski, Krzysztof Kozlowski
In-Reply-To: <20240410124628.171783-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
The WCN7850 package contains discreet modules for WLAN and Bluetooth. They
are powered by the Power Management Unit (PMU) that takes inputs from the
host and provides LDO outputs. Extend the bindings for QCA6390 to also
document this model.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/regulator/qcom,qca6390-pmu.yaml | 36 ++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml b/Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml
index 9d39ff9a75fd..2e543661a1e2 100644
--- a/Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml
+++ b/Documentation/devicetree/bindings/regulator/qcom,qca6390-pmu.yaml
@@ -16,20 +16,37 @@ description:
properties:
compatible:
- const: qcom,qca6390-pmu
+ enum:
+ - qcom,qca6390-pmu
+ - qcom,wcn7850-pmu
+
+ vdd-supply:
+ description: VDD supply regulator handle
vddaon-supply:
description: VDD_AON supply regulator handle
+ vdddig-supply:
+ description: VDD_DIG supply regulator handle
+
vddpmu-supply:
description: VDD_PMU supply regulator handle
+ vddio1p2-supply:
+ description: VDD_IO_1P2 supply regulator handle
+
vddrfa0p95-supply:
description: VDD_RFA_0P95 supply regulator handle
+ vddrfa1p2-supply:
+ description: VDD_RFA_1P2 supply regulator handle
+
vddrfa1p3-supply:
description: VDD_RFA_1P3 supply regulator handle
+ vddrfa1p8-supply:
+ description: VDD_RFA_1P8 supply regulator handle
+
vddrfa1p9-supply:
description: VDD_RFA_1P9 supply regulator handle
@@ -50,6 +67,10 @@ properties:
maxItems: 1
description: GPIO line enabling the ATH11K Bluetooth module supplied by the PMU
+ clocks:
+ maxItems: 1
+ description: Reference clock handle
+
regulators:
type: object
description:
@@ -83,6 +104,19 @@ allOf:
- vddpcie1p3-supply
- vddpcie1p9-supply
- vddio-supply
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,wcn7850-pmu
+ then:
+ required:
+ - vdd-supply
+ - vddio-supply
+ - vddaon-supply
+ - vdddig-supply
+ - vddrfa1p2-supply
+ - vddrfa1p8-supply
additionalProperties: false
--
2.40.1
^ permalink raw reply related
* [PATCH v7 03/16] dt-bindings: net: bluetooth: qualcomm: describe regulators for QCA6390
From: Bartosz Golaszewski @ 2024-04-10 12:46 UTC (permalink / raw)
To: Marcel Holtmann, Luiz Augusto von Dentz, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kalle Valo, Bjorn Andersson,
Konrad Dybcio, Liam Girdwood, Mark Brown, Catalin Marinas,
Will Deacon, Bjorn Helgaas, Bartosz Golaszewski, Saravana Kannan,
Geert Uytterhoeven, Arnd Bergmann, Neil Armstrong,
Marek Szyprowski, Alex Elder, Srini Kandagatla,
Greg Kroah-Hartman, Abel Vesa, Manivannan Sadhasivam,
Lukas Wunner, Dmitry Baryshkov, Amit Pundir, Xilin Wu
Cc: linux-bluetooth, netdev, devicetree, linux-kernel, linux-wireless,
linux-arm-msm, linux-arm-kernel, linux-pci, linux-pm,
Bartosz Golaszewski, Krzysztof Kozlowski
In-Reply-To: <20240410124628.171783-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
QCA6390 has a compatible listed in the bindings but is missing the
regulators description. Add the missing supply property and list the
required ones in the allOf section.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../net/bluetooth/qualcomm-bluetooth.yaml | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml b/Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml
index 528ef3572b62..d844acaec1d3 100644
--- a/Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml
+++ b/Documentation/devicetree/bindings/net/bluetooth/qualcomm-bluetooth.yaml
@@ -62,6 +62,9 @@ properties:
vdddig-supply:
description: VDD_DIG supply regulator handle
+ vddbtcmx-supply:
+ description: VDD_BT_CMX supply regulator handle
+
vddbtcxmx-supply:
description: VDD_BT_CXMX supply regulator handle
@@ -180,6 +183,20 @@ allOf:
- vddrfa0p8-supply
- vddrfa1p2-supply
- vddrfa1p9-supply
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qca6390-bt
+ then:
+ required:
+ - vddrfacmn-supply
+ - vddaon-supply
+ - vddbtcmx-supply
+ - vddrfa0p8-supply
+ - vddrfa1p2-supply
+ - vddrfa1p7-supply
examples:
- |
--
2.40.1
^ permalink raw reply related
* [PATCH v7 04/16] dt-bindings: net: wireless: qcom,ath11k: describe the ath11k on QCA6390
From: Bartosz Golaszewski @ 2024-04-10 12:46 UTC (permalink / raw)
To: Marcel Holtmann, Luiz Augusto von Dentz, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kalle Valo, Bjorn Andersson,
Konrad Dybcio, Liam Girdwood, Mark Brown, Catalin Marinas,
Will Deacon, Bjorn Helgaas, Bartosz Golaszewski, Saravana Kannan,
Geert Uytterhoeven, Arnd Bergmann, Neil Armstrong,
Marek Szyprowski, Alex Elder, Srini Kandagatla,
Greg Kroah-Hartman, Abel Vesa, Manivannan Sadhasivam,
Lukas Wunner, Dmitry Baryshkov, Amit Pundir, Xilin Wu
Cc: linux-bluetooth, netdev, devicetree, linux-kernel, linux-wireless,
linux-arm-msm, linux-arm-kernel, linux-pci, linux-pm,
Bartosz Golaszewski
In-Reply-To: <20240410124628.171783-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Add a PCI compatible for the ATH11K module on QCA6390 and describe the
power inputs from the PMU that it consumes.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
.../net/wireless/qcom,ath11k-pci.yaml | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k-pci.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k-pci.yaml
index 41d023797d7d..8675d7d0215c 100644
--- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k-pci.yaml
+++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k-pci.yaml
@@ -17,6 +17,7 @@ description: |
properties:
compatible:
enum:
+ - pci17cb,1101 # QCA6390
- pci17cb,1103 # WCN6855
reg:
@@ -28,10 +29,55 @@ properties:
string to uniquely identify variant of the calibration data for designs
with colliding bus and device ids
+ vddrfacmn-supply:
+ description: VDD_RFA_CMN supply regulator handle
+
+ vddaon-supply:
+ description: VDD_AON supply regulator handle
+
+ vddwlcx-supply:
+ description: VDD_WL_CX supply regulator handle
+
+ vddwlmx-supply:
+ description: VDD_WL_MX supply regulator handle
+
+ vddrfa0p8-supply:
+ description: VDD_RFA_0P8 supply regulator handle
+
+ vddrfa1p2-supply:
+ description: VDD_RFA_1P2 supply regulator handle
+
+ vddrfa1p7-supply:
+ description: VDD_RFA_1P7 supply regulator handle
+
+ vddpcie0p9-supply:
+ description: VDD_PCIE_0P9 supply regulator handle
+
+ vddpcie1p8-supply:
+ description: VDD_PCIE_1P8 supply regulator handle
+
required:
- compatible
- reg
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: pci17cb,1101
+ then:
+ required:
+ - vddrfacmn-supply
+ - vddaon-supply
+ - vddwlcx-supply
+ - vddwlmx-supply
+ - vddrfa0p8-supply
+ - vddrfa1p2-supply
+ - vddrfa1p7-supply
+ - vddpcie0p9-supply
+ - vddpcie1p8-supply
+
additionalProperties: false
examples:
--
2.40.1
^ permalink raw reply related
* [PATCH v7 05/16] dt-bindings: net: wireless: describe the ath12k PCI module
From: Bartosz Golaszewski @ 2024-04-10 12:46 UTC (permalink / raw)
To: Marcel Holtmann, Luiz Augusto von Dentz, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kalle Valo, Bjorn Andersson,
Konrad Dybcio, Liam Girdwood, Mark Brown, Catalin Marinas,
Will Deacon, Bjorn Helgaas, Bartosz Golaszewski, Saravana Kannan,
Geert Uytterhoeven, Arnd Bergmann, Neil Armstrong,
Marek Szyprowski, Alex Elder, Srini Kandagatla,
Greg Kroah-Hartman, Abel Vesa, Manivannan Sadhasivam,
Lukas Wunner, Dmitry Baryshkov, Amit Pundir, Xilin Wu
Cc: linux-bluetooth, netdev, devicetree, linux-kernel, linux-wireless,
linux-arm-msm, linux-arm-kernel, linux-pci, linux-pm,
Bartosz Golaszewski, Krzysztof Kozlowski
In-Reply-To: <20240410124628.171783-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Add device-tree bindings for the ATH12K module found in the WCN7850
package.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/net/wireless/qcom,ath12k.yaml | 99 +++++++++++++++++++
1 file changed, 99 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml
diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml
new file mode 100644
index 000000000000..f04d72d2c88e
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath12k.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 Linaro Limited
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/wireless/qcom,ath12k.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies ath12k wireless devices (PCIe)
+
+maintainers:
+ - Jeff Johnson <quic_jjohnson@quicinc.com>
+ - Kalle Valo <kvalo@kernel.org>
+
+description:
+ Qualcomm Technologies IEEE 802.11ax PCIe devices.
+
+properties:
+ compatible:
+ enum:
+ - pci17cb,1107 # WCN7850
+
+ reg:
+ maxItems: 1
+
+ vddaon-supply:
+ description: VDD_AON supply regulator handle
+
+ vddwlcx-supply:
+ description: VDD_WLCX supply regulator handle
+
+ vddwlmx-supply:
+ description: VDD_WLMX supply regulator handle
+
+ vddrfacmn-supply:
+ description: VDD_RFA_CMN supply regulator handle
+
+ vddrfa0p8-supply:
+ description: VDD_RFA_0P8 supply regulator handle
+
+ vddrfa1p2-supply:
+ description: VDD_RFA_1P2 supply regulator handle
+
+ vddrfa1p8-supply:
+ description: VDD_RFA_1P8 supply regulator handle
+
+ vddpcie0p9-supply:
+ description: VDD_PCIE_0P9 supply regulator handle
+
+ vddpcie1p8-supply:
+ description: VDD_PCIE_1P8 supply regulator handle
+
+required:
+ - compatible
+ - reg
+ - vddaon-supply
+ - vddwlcx-supply
+ - vddwlmx-supply
+ - vddrfacmn-supply
+ - vddrfa0p8-supply
+ - vddrfa1p2-supply
+ - vddrfa1p8-supply
+ - vddpcie0p9-supply
+ - vddpcie1p8-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/gpio/gpio.h>
+ pcie {
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ bus-range = <0x01 0xff>;
+
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+ };
+ };
--
2.40.1
^ permalink raw reply related
* [PATCH v7 06/16] arm64: dts: qcom: sm8550-qrd: add the Wifi node
From: Bartosz Golaszewski @ 2024-04-10 12:46 UTC (permalink / raw)
To: Marcel Holtmann, Luiz Augusto von Dentz, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kalle Valo, Bjorn Andersson,
Konrad Dybcio, Liam Girdwood, Mark Brown, Catalin Marinas,
Will Deacon, Bjorn Helgaas, Bartosz Golaszewski, Saravana Kannan,
Geert Uytterhoeven, Arnd Bergmann, Neil Armstrong,
Marek Szyprowski, Alex Elder, Srini Kandagatla,
Greg Kroah-Hartman, Abel Vesa, Manivannan Sadhasivam,
Lukas Wunner, Dmitry Baryshkov, Amit Pundir, Xilin Wu
Cc: linux-bluetooth, netdev, devicetree, linux-kernel, linux-wireless,
linux-arm-msm, linux-arm-kernel, linux-pci, linux-pm,
Bartosz Golaszewski
In-Reply-To: <20240410124628.171783-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Describe the ath12k WLAN on-board the WCN7850 module present on the
board.
[Neil: authored the initial version of the change]
Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 97 +++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 +++
2 files changed, 107 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 92f015017418..caac40a799a5 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -214,6 +214,68 @@ vph_pwr: vph-pwr-regulator {
regulator-always-on;
regulator-boot-on;
};
+
+ wcn7850-pmu {
+ compatible = "qcom,wcn7850-pmu";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_en>, <&pmk8550_sleep_clk>;
+
+ wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
+ /*
+ * TODO Add bt-enable-gpios once the Bluetooth driver is
+ * converted to using the power sequencer.
+ */
+
+ vdd-supply = <&vreg_s5g_0p85>;
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddaon-supply = <&vreg_s2g_0p85>;
+ vdddig-supply = <&vreg_s4e_0p95>;
+ vddrfa1p2-supply = <&vreg_s4g_1p25>;
+ vddrfa1p8-supply = <&vreg_s6g_1p86>;
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p8: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p8";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
};
&apps_rsc {
@@ -824,6 +886,23 @@ &pcie0 {
status = "okay";
};
+&pcieport0 {
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+};
+
&pcie0_phy {
vdda-phy-supply = <&vreg_l1e_0p88>;
vdda-pll-supply = <&vreg_l3e_1p2>;
@@ -911,6 +990,17 @@ &pcie_1_phy_aux_clk {
clock-frequency = <1000>;
};
+&pmk8550_gpios {
+ pmk8550_sleep_clk: sleep-clk-state {
+ pins = "gpio3";
+ function = "func1";
+ input-disable;
+ output-enable;
+ bias-disable;
+ power-source = <0>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -1084,6 +1174,13 @@ wcd_default: wcd-reset-n-active-state {
bias-disable;
output-low;
};
+
+ wlan_en: wlan-en-state {
+ pins = "gpio80";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
};
&uart7 {
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 5cae8d773cec..f09406fd0ca6 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1770,6 +1770,16 @@ pcie0: pcie@1c00000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcieport0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ bus-range = <0x01 0xff>;
+ };
};
pcie0_phy: phy@1c06000 {
--
2.40.1
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