* [PATCH v3 03/15] firmware: qcom_scm: Migrate to generic PAS service
From: Sumit Garg @ 2026-03-27 13:10 UTC (permalink / raw)
To: linux-arm-msm, devicetree, dri-devel, freedreno, linux-media,
netdev, linux-wireless, ath12k, linux-remoteproc
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
harshal.dev, linux-kernel, Sumit Garg
In-Reply-To: <20260327131043.627120-1-sumit.garg@kernel.org>
From: Sumit Garg <sumit.garg@oss.qualcomm.com>
With the availability of generic PAS service, let's add SCM calls as
a backend to keep supporting legacy QTEE interfaces. The exported
qcom_scm* wrappers will get dropped once all the client drivers get
migrated as part of future patches.
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
---
drivers/firmware/qcom/Kconfig | 1 +
drivers/firmware/qcom/qcom_scm.c | 335 ++++++++++++++-----------------
2 files changed, 155 insertions(+), 181 deletions(-)
diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig
index 8653639d06db..9a12ae2b639d 100644
--- a/drivers/firmware/qcom/Kconfig
+++ b/drivers/firmware/qcom/Kconfig
@@ -15,6 +15,7 @@ config QCOM_PAS
TEE bus based PAS service implementation.
config QCOM_SCM
+ select QCOM_PAS
select QCOM_TZMEM
tristate
diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
index 8fbc96693a55..ab802048a719 100644
--- a/drivers/firmware/qcom/qcom_scm.c
+++ b/drivers/firmware/qcom/qcom_scm.c
@@ -13,6 +13,7 @@
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/export.h>
+#include <linux/firmware/qcom/qcom_pas.h>
#include <linux/firmware/qcom/qcom_scm.h>
#include <linux/firmware/qcom/qcom_tzmem.h>
#include <linux/init.h>
@@ -33,6 +34,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "qcom_pas.h"
#include "qcom_scm.h"
#include "qcom_tzmem.h"
@@ -480,25 +482,6 @@ void qcom_scm_cpu_power_down(u32 flags)
}
EXPORT_SYMBOL_GPL(qcom_scm_cpu_power_down);
-int qcom_scm_set_remote_state(u32 state, u32 id)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_BOOT,
- .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
- .arginfo = QCOM_SCM_ARGS(2),
- .args[0] = state,
- .args[1] = id,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
- int ret;
-
- ret = qcom_scm_call(__scm->dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state);
-
static int qcom_scm_disable_sdi(void)
{
int ret;
@@ -571,26 +554,12 @@ static void qcom_scm_set_download_mode(u32 dload_mode)
dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
}
-/**
- * devm_qcom_scm_pas_context_alloc() - Allocate peripheral authentication service
- * context for a given peripheral
- *
- * PAS context is device-resource managed, so the caller does not need
- * to worry about freeing the context memory.
- *
- * @dev: PAS firmware device
- * @pas_id: peripheral authentication service id
- * @mem_phys: Subsystem reserve memory start address
- * @mem_size: Subsystem reserve memory size
- *
- * Returns: The new PAS context, or ERR_PTR() on failure.
- */
struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device *dev,
u32 pas_id,
phys_addr_t mem_phys,
size_t mem_size)
{
- struct qcom_scm_pas_context *ctx;
+ struct qcom_pas_context *ctx;
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
if (!ctx)
@@ -601,11 +570,12 @@ struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device *dev,
ctx->mem_phys = mem_phys;
ctx->mem_size = mem_size;
- return ctx;
+ return (struct qcom_scm_pas_context *)ctx;
}
EXPORT_SYMBOL_GPL(devm_qcom_scm_pas_context_alloc);
-static int __qcom_scm_pas_init_image(u32 pas_id, dma_addr_t mdata_phys,
+static int __qcom_scm_pas_init_image(struct device *dev, u32 pas_id,
+ dma_addr_t mdata_phys,
struct qcom_scm_res *res)
{
struct qcom_scm_desc desc = {
@@ -627,7 +597,7 @@ static int __qcom_scm_pas_init_image(u32 pas_id, dma_addr_t mdata_phys,
desc.args[1] = mdata_phys;
- ret = qcom_scm_call(__scm->dev, &desc, res);
+ ret = qcom_scm_call(dev, &desc, res);
qcom_scm_bw_disable();
disable_clk:
@@ -636,7 +606,8 @@ static int __qcom_scm_pas_init_image(u32 pas_id, dma_addr_t mdata_phys,
return ret;
}
-static int qcom_scm_pas_prep_and_init_image(struct qcom_scm_pas_context *ctx,
+static int qcom_scm_pas_prep_and_init_image(struct device *dev,
+ struct qcom_pas_context *ctx,
const void *metadata, size_t size)
{
struct qcom_scm_res res;
@@ -651,7 +622,7 @@ static int qcom_scm_pas_prep_and_init_image(struct qcom_scm_pas_context *ctx,
memcpy(mdata_buf, metadata, size);
mdata_phys = qcom_tzmem_to_phys(mdata_buf);
- ret = __qcom_scm_pas_init_image(ctx->pas_id, mdata_phys, &res);
+ ret = __qcom_scm_pas_init_image(dev, ctx->pas_id, mdata_phys, &res);
if (ret < 0)
qcom_tzmem_free(mdata_buf);
else
@@ -660,25 +631,9 @@ static int qcom_scm_pas_prep_and_init_image(struct qcom_scm_pas_context *ctx,
return ret ? : res.result[0];
}
-/**
- * qcom_scm_pas_init_image() - Initialize peripheral authentication service
- * state machine for a given peripheral, using the
- * metadata
- * @pas_id: peripheral authentication service id
- * @metadata: pointer to memory containing ELF header, program header table
- * and optional blob of data used for authenticating the metadata
- * and the rest of the firmware
- * @size: size of the metadata
- * @ctx: optional pas context
- *
- * Return: 0 on success.
- *
- * Upon successful return, the PAS metadata context (@ctx) will be used to
- * track the metadata allocation, this needs to be released by invoking
- * qcom_scm_pas_metadata_release() by the caller.
- */
-int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size,
- struct qcom_scm_pas_context *ctx)
+static int __qcom_scm_pas_init_image2(struct device *dev, u32 pas_id,
+ const void *metadata, size_t size,
+ struct qcom_pas_context *ctx)
{
struct qcom_scm_res res;
dma_addr_t mdata_phys;
@@ -686,7 +641,7 @@ int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size,
int ret;
if (ctx && ctx->use_tzmem)
- return qcom_scm_pas_prep_and_init_image(ctx, metadata, size);
+ return qcom_scm_pas_prep_and_init_image(dev, ctx, metadata, size);
/*
* During the scm call memory protection will be enabled for the meta
@@ -700,16 +655,15 @@ int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size,
* If we pass a buffer that is already part of an SHM Bridge to this
* call, it will fail.
*/
- mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys,
- GFP_KERNEL);
+ mdata_buf = dma_alloc_coherent(dev, size, &mdata_phys, GFP_KERNEL);
if (!mdata_buf)
return -ENOMEM;
memcpy(mdata_buf, metadata, size);
- ret = __qcom_scm_pas_init_image(pas_id, mdata_phys, &res);
+ ret = __qcom_scm_pas_init_image(dev, pas_id, mdata_phys, &res);
if (ret < 0 || !ctx) {
- dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys);
+ dma_free_coherent(dev, size, mdata_buf, mdata_phys);
} else if (ctx) {
ctx->ptr = mdata_buf;
ctx->phys = mdata_phys;
@@ -718,36 +672,35 @@ int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size,
return ret ? : res.result[0];
}
-EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image);
-/**
- * qcom_scm_pas_metadata_release() - release metadata context
- * @ctx: pas context
- */
-void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx)
+int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size,
+ struct qcom_scm_pas_context *ctx)
{
- if (!ctx->ptr)
- return;
+ return __qcom_scm_pas_init_image2(__scm->dev, pas_id, metadata, size,
+ (struct qcom_pas_context *)ctx);
+}
+EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image);
+static void __qcom_scm_pas_metadata_release(struct device *dev,
+ struct qcom_pas_context *ctx)
+{
if (ctx->use_tzmem)
qcom_tzmem_free(ctx->ptr);
else
- dma_free_coherent(__scm->dev, ctx->size, ctx->ptr, ctx->phys);
+ dma_free_coherent(dev, ctx->size, ctx->ptr, ctx->phys);
ctx->ptr = NULL;
}
+
+void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx)
+{
+ __qcom_scm_pas_metadata_release(__scm->dev,
+ (struct qcom_pas_context *)ctx);
+}
EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release);
-/**
- * qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
- * for firmware loading
- * @pas_id: peripheral authentication service id
- * @addr: start address of memory area to prepare
- * @size: size of the memory area to prepare
- *
- * Returns 0 on success.
- */
-int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size)
+static int __qcom_scm_pas_mem_setup(struct device *dev, u32 pas_id,
+ phys_addr_t addr, phys_addr_t size)
{
int ret;
struct qcom_scm_desc desc = {
@@ -769,7 +722,7 @@ int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size)
if (ret)
goto disable_clk;
- ret = qcom_scm_call(__scm->dev, &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);
qcom_scm_bw_disable();
disable_clk:
@@ -777,9 +730,15 @@ int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size)
return ret ? : res.result[0];
}
+
+int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size)
+{
+ return __qcom_scm_pas_mem_setup(__scm->dev, pas_id, addr, size);
+}
EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup);
-static void *__qcom_scm_pas_get_rsc_table(u32 pas_id, void *input_rt_tzm,
+static void *__qcom_scm_pas_get_rsc_table(struct device *dev, u32 pas_id,
+ void *input_rt_tzm,
size_t input_rt_size,
size_t *output_rt_size)
{
@@ -814,7 +773,7 @@ static void *__qcom_scm_pas_get_rsc_table(u32 pas_id, void *input_rt_tzm,
* with output_rt_tzm buffer with res.result[2] size however, It should not
* be of unresonable size.
*/
- ret = qcom_scm_call(__scm->dev, &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);
if (!ret && res.result[2] > SZ_1G) {
ret = -E2BIG;
goto free_output_rt;
@@ -831,51 +790,11 @@ static void *__qcom_scm_pas_get_rsc_table(u32 pas_id, void *input_rt_tzm,
return ret ? ERR_PTR(ret) : output_rt_tzm;
}
-/**
- * qcom_scm_pas_get_rsc_table() - Retrieve the resource table in passed output buffer
- * for a given peripheral.
- *
- * Qualcomm remote processor may rely on both static and dynamic resources for
- * its functionality. Static resources typically refer to memory-mapped addresses
- * required by the subsystem and are often embedded within the firmware binary
- * and dynamic resources, such as shared memory in DDR etc., are determined at
- * runtime during the boot process.
- *
- * On Qualcomm Technologies devices, it's possible that static resources are not
- * embedded in the firmware binary and instead are provided by TrustZone However,
- * dynamic resources are always expected to come from TrustZone. This indicates
- * that for Qualcomm devices, all resources (static and dynamic) will be provided
- * by TrustZone via the SMC call.
- *
- * If the remote processor firmware binary does contain static resources, they
- * should be passed in input_rt. These will be forwarded to TrustZone for
- * authentication. TrustZone will then append the dynamic resources and return
- * the complete resource table in output_rt_tzm.
- *
- * If the remote processor firmware binary does not include a resource table,
- * the caller of this function should set input_rt as NULL and input_rt_size
- * as zero respectively.
- *
- * More about documentation on resource table data structures can be found in
- * include/linux/remoteproc.h
- *
- * @ctx: PAS context
- * @pas_id: peripheral authentication service id
- * @input_rt: resource table buffer which is present in firmware binary
- * @input_rt_size: size of the resource table present in firmware binary
- * @output_rt_size: TrustZone expects caller should pass worst case size for
- * the output_rt_tzm.
- *
- * Return:
- * On success, returns a pointer to the allocated buffer containing the final
- * resource table and output_rt_size will have actual resource table size from
- * TrustZone. The caller is responsible for freeing the buffer. On failure,
- * returns ERR_PTR(-errno).
- */
-struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_context *ctx,
- void *input_rt,
- size_t input_rt_size,
- size_t *output_rt_size)
+static void *__qcom_scm_pas_get_rsc_table2(struct device *dev,
+ struct qcom_pas_context *ctx,
+ void *input_rt,
+ size_t input_rt_size,
+ size_t *output_rt_size)
{
struct resource_table empty_rsc = {};
size_t size = SZ_16K;
@@ -910,11 +829,12 @@ struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_context *c
memcpy(input_rt_tzm, input_rt, input_rt_size);
- output_rt_tzm = __qcom_scm_pas_get_rsc_table(ctx->pas_id, input_rt_tzm,
+ output_rt_tzm = __qcom_scm_pas_get_rsc_table(dev, ctx->pas_id,
+ input_rt_tzm,
input_rt_size, &size);
if (PTR_ERR(output_rt_tzm) == -EOVERFLOW)
/* Try again with the size requested by the TZ */
- output_rt_tzm = __qcom_scm_pas_get_rsc_table(ctx->pas_id,
+ output_rt_tzm = __qcom_scm_pas_get_rsc_table(dev, ctx->pas_id,
input_rt_tzm,
input_rt_size,
&size);
@@ -945,16 +865,20 @@ struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_context *c
return ret ? ERR_PTR(ret) : tbl_ptr;
}
+
+struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_context *ctx,
+ void *input_rt,
+ size_t input_rt_size,
+ size_t *output_rt_size)
+{
+ return __qcom_scm_pas_get_rsc_table2(__scm->dev,
+ (struct qcom_pas_context *)ctx,
+ input_rt, input_rt_size,
+ output_rt_size);
+}
EXPORT_SYMBOL_GPL(qcom_scm_pas_get_rsc_table);
-/**
- * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
- * and reset the remote processor
- * @pas_id: peripheral authentication service id
- *
- * Return 0 on success.
- */
-int qcom_scm_pas_auth_and_reset(u32 pas_id)
+static int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 pas_id)
{
int ret;
struct qcom_scm_desc desc = {
@@ -974,7 +898,7 @@ int qcom_scm_pas_auth_and_reset(u32 pas_id)
if (ret)
goto disable_clk;
- ret = qcom_scm_call(__scm->dev, &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);
qcom_scm_bw_disable();
disable_clk:
@@ -982,28 +906,15 @@ int qcom_scm_pas_auth_and_reset(u32 pas_id)
return ret ? : res.result[0];
}
+
+int qcom_scm_pas_auth_and_reset(u32 pas_id)
+{
+ return __qcom_scm_pas_auth_and_reset(__scm->dev, pas_id);
+}
EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset);
-/**
- * qcom_scm_pas_prepare_and_auth_reset() - Prepare, authenticate, and reset the
- * remote processor
- *
- * @ctx: Context saved during call to qcom_scm_pas_context_init()
- *
- * This function performs the necessary steps to prepare a PAS subsystem,
- * authenticate it using the provided metadata, and initiate a reset sequence.
- *
- * It should be used when Linux is in control setting up the IOMMU hardware
- * for remote subsystem during secure firmware loading processes. The preparation
- * step sets up a shmbridge over the firmware memory before TrustZone accesses the
- * firmware memory region for authentication. The authentication step verifies
- * the integrity and authenticity of the firmware or configuration using secure
- * metadata. Finally, the reset step ensures the subsystem starts in a clean and
- * sane state.
- *
- * Return: 0 on success, negative errno on failure.
- */
-int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx)
+static int __qcom_scm_pas_prepare_and_auth_reset(struct device *dev,
+ struct qcom_pas_context *ctx)
{
u64 handle;
int ret;
@@ -1014,7 +925,7 @@ int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx)
* memory region and then invokes a call to TrustZone to authenticate.
*/
if (!ctx->use_tzmem)
- return qcom_scm_pas_auth_and_reset(ctx->pas_id);
+ return __qcom_scm_pas_auth_and_reset(dev, ctx->pas_id);
/*
* When Linux runs @ EL2 Linux must create the shmbridge itself and then
@@ -1024,20 +935,45 @@ int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx)
if (ret)
return ret;
- ret = qcom_scm_pas_auth_and_reset(ctx->pas_id);
+ ret = __qcom_scm_pas_auth_and_reset(dev, ctx->pas_id);
qcom_tzmem_shm_bridge_delete(handle);
return ret;
}
+
+int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx)
+{
+ return __qcom_scm_pas_prepare_and_auth_reset(__scm->dev,
+ (struct qcom_pas_context *)ctx);
+}
EXPORT_SYMBOL_GPL(qcom_scm_pas_prepare_and_auth_reset);
-/**
- * qcom_scm_pas_shutdown() - Shut down the remote processor
- * @pas_id: peripheral authentication service id
- *
- * Returns 0 on success.
- */
-int qcom_scm_pas_shutdown(u32 pas_id)
+static int __qcom_scm_pas_set_remote_state(struct device *dev, u32 state,
+ u32 pas_id)
+{
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
+ .arginfo = QCOM_SCM_ARGS(2),
+ .args[0] = state,
+ .args[1] = pas_id,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;
+ int ret;
+
+ ret = qcom_scm_call(dev, &desc, &res);
+
+ return ret ? : res.result[0];
+}
+
+int qcom_scm_set_remote_state(u32 state, u32 id)
+{
+ return __qcom_scm_pas_set_remote_state(__scm->dev, state, id);
+}
+EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state);
+
+static int __qcom_scm_pas_shutdown(struct device *dev, u32 pas_id)
{
int ret;
struct qcom_scm_desc desc = {
@@ -1057,7 +993,7 @@ int qcom_scm_pas_shutdown(u32 pas_id)
if (ret)
goto disable_clk;
- ret = qcom_scm_call(__scm->dev, &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);
qcom_scm_bw_disable();
disable_clk:
@@ -1065,16 +1001,14 @@ int qcom_scm_pas_shutdown(u32 pas_id)
return ret ? : res.result[0];
}
+
+int qcom_scm_pas_shutdown(u32 pas_id)
+{
+ return __qcom_scm_pas_shutdown(__scm->dev, pas_id);
+}
EXPORT_SYMBOL_GPL(qcom_scm_pas_shutdown);
-/**
- * qcom_scm_pas_supported() - Check if the peripheral authentication service is
- * available for the given peripherial
- * @pas_id: peripheral authentication service id
- *
- * Returns true if PAS is supported for this peripheral, otherwise false.
- */
-bool qcom_scm_pas_supported(u32 pas_id)
+static bool __qcom_scm_pas_supported(struct device *dev, u32 pas_id)
{
int ret;
struct qcom_scm_desc desc = {
@@ -1086,16 +1020,49 @@ bool qcom_scm_pas_supported(u32 pas_id)
};
struct qcom_scm_res res;
- if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
+ if (!__qcom_scm_is_call_available(dev, QCOM_SCM_SVC_PIL,
QCOM_SCM_PIL_PAS_IS_SUPPORTED))
return false;
- ret = qcom_scm_call(__scm->dev, &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);
return ret ? false : !!res.result[0];
}
+
+bool qcom_scm_pas_supported(u32 pas_id)
+{
+ return __qcom_scm_pas_supported(__scm->dev, pas_id);
+}
EXPORT_SYMBOL_GPL(qcom_scm_pas_supported);
+static struct qcom_pas_ops qcom_pas_ops_scm = {
+ .drv_name = "qcom_scm",
+ .supported = __qcom_scm_pas_supported,
+ .init_image = __qcom_scm_pas_init_image2,
+ .mem_setup = __qcom_scm_pas_mem_setup,
+ .get_rsc_table = __qcom_scm_pas_get_rsc_table2,
+ .auth_and_reset = __qcom_scm_pas_auth_and_reset,
+ .prepare_and_auth_reset = __qcom_scm_pas_prepare_and_auth_reset,
+ .set_remote_state = __qcom_scm_pas_set_remote_state,
+ .shutdown = __qcom_scm_pas_shutdown,
+ .metadata_release = __qcom_scm_pas_metadata_release,
+};
+
+/**
+ * qcom_scm_is_pas_available() - Check if the peripheral authentication service
+ * is available via SCM or not
+ *
+ * Returns true if PAS is available, otherwise false.
+ */
+static bool qcom_scm_is_pas_available(void)
+{
+ if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
+ QCOM_SCM_PIL_PAS_AUTH_AND_RESET))
+ return false;
+
+ return true;
+}
+
static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
{
struct qcom_scm_desc desc = {
@@ -2782,6 +2749,11 @@ static int qcom_scm_probe(struct platform_device *pdev)
__get_convention();
+ if (qcom_scm_is_pas_available()) {
+ qcom_pas_ops_scm.dev = scm->dev;
+ qcom_pas_ops_register(&qcom_pas_ops_scm);
+ }
+
/*
* If "download mode" is requested, from this point on warmboot
* will cause the boot stages to enter download mode, unless
@@ -2818,6 +2790,7 @@ static void qcom_scm_shutdown(struct platform_device *pdev)
{
/* Clean shutdown, disable download mode to allow normal restart */
qcom_scm_set_download_mode(QCOM_DLOAD_NODUMP);
+ qcom_pas_ops_unregister();
}
static const struct of_device_id qcom_scm_dt_match[] = {
--
2.51.0
^ permalink raw reply related
* [PATCH v3 04/15] firmware: qcom: Add a PAS TEE service
From: Sumit Garg @ 2026-03-27 13:10 UTC (permalink / raw)
To: linux-arm-msm, devicetree, dri-devel, freedreno, linux-media,
netdev, linux-wireless, ath12k, linux-remoteproc
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
harshal.dev, linux-kernel, Sumit Garg
In-Reply-To: <20260327131043.627120-1-sumit.garg@kernel.org>
From: Sumit Garg <sumit.garg@oss.qualcomm.com>
Add support for Peripheral Authentication Service (PAS) driver based
on TEE bus with OP-TEE providing the backend PAS service implementation.
The TEE PAS service ABI is designed to be extensible with additional API
as PTA_QCOM_PAS_CAPABILITIES. This allows to accommodate any future
extensions of the PAS service needed while still maintaining backwards
compatibility.
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
---
drivers/firmware/qcom/Kconfig | 10 +
drivers/firmware/qcom/Makefile | 1 +
drivers/firmware/qcom/qcom_pas_tee.c | 478 +++++++++++++++++++++++++++
3 files changed, 489 insertions(+)
create mode 100644 drivers/firmware/qcom/qcom_pas_tee.c
diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig
index 9a12ae2b639d..300b3a1bd178 100644
--- a/drivers/firmware/qcom/Kconfig
+++ b/drivers/firmware/qcom/Kconfig
@@ -14,6 +14,16 @@ config QCOM_PAS
backends plugged in whether it's an SCM implementation or a proper
TEE bus based PAS service implementation.
+config QCOM_PAS_TEE
+ tristate
+ select QCOM_PAS
+ depends on TEE
+ depends on !CPU_BIG_ENDIAN
+ default m if ARCH_QCOM
+ help
+ Enable the generic Peripheral Authentication Service (PAS) provided
+ by the firmware TEE implementation as the backend.
+
config QCOM_SCM
select QCOM_PAS
select QCOM_TZMEM
diff --git a/drivers/firmware/qcom/Makefile b/drivers/firmware/qcom/Makefile
index dc5ab45f906a..48801d18f37b 100644
--- a/drivers/firmware/qcom/Makefile
+++ b/drivers/firmware/qcom/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_QCOM_TZMEM) += qcom_tzmem.o
obj-$(CONFIG_QCOM_QSEECOM) += qcom_qseecom.o
obj-$(CONFIG_QCOM_QSEECOM_UEFISECAPP) += qcom_qseecom_uefisecapp.o
obj-$(CONFIG_QCOM_PAS) += qcom_pas.o
+obj-$(CONFIG_QCOM_PAS_TEE) += qcom_pas_tee.o
diff --git a/drivers/firmware/qcom/qcom_pas_tee.c b/drivers/firmware/qcom/qcom_pas_tee.c
new file mode 100644
index 000000000000..d63122c34f04
--- /dev/null
+++ b/drivers/firmware/qcom/qcom_pas_tee.c
@@ -0,0 +1,478 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/firmware/qcom/qcom_pas.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/tee_drv.h>
+#include <linux/uuid.h>
+
+#include "qcom_pas.h"
+
+/*
+ * Peripheral Authentication Service (PAS) supported.
+ *
+ * [in] params[0].value.a: Unique 32bit remote processor identifier
+ */
+#define TA_QCOM_PAS_IS_SUPPORTED 1
+
+/*
+ * PAS capabilities.
+ *
+ * [in] params[0].value.a: Unique 32bit remote processor identifier
+ * [out] params[1].value.a: PAS capability flags
+ */
+#define TA_QCOM_PAS_CAPABILITIES 2
+
+/*
+ * PAS image initialization.
+ *
+ * [in] params[0].value.a: Unique 32bit remote processor identifier
+ * [in] params[1].memref: Loadable firmware metadata
+ */
+#define TA_QCOM_PAS_INIT_IMAGE 3
+
+/*
+ * PAS memory setup.
+ *
+ * [in] params[0].value.a: Unique 32bit remote processor identifier
+ * [in] params[0].value.b: Relocatable firmware size
+ * [in] params[1].value.a: 32bit LSB relocatable firmware memory address
+ * [in] params[1].value.b: 32bit MSB relocatable firmware memory address
+ */
+#define TA_QCOM_PAS_MEM_SETUP 4
+
+/*
+ * PAS get resource table.
+ *
+ * [in] params[0].value.a: Unique 32bit remote processor identifier
+ * [inout] params[1].memref: Resource table config
+ */
+#define TA_QCOM_PAS_GET_RESOURCE_TABLE 5
+
+/*
+ * PAS image authentication and co-processor reset.
+ *
+ * [in] params[0].value.a: Unique 32bit remote processor identifier
+ * [in] params[0].value.b: Firmware size
+ * [in] params[1].value.a: 32bit LSB firmware memory address
+ * [in] params[1].value.b: 32bit MSB firmware memory address
+ * [in] params[2].memref: Optional fw memory space shared/lent
+ */
+#define TA_QCOM_PAS_AUTH_AND_RESET 6
+
+/*
+ * PAS co-processor set suspend/resume state.
+ *
+ * [in] params[0].value.a: Unique 32bit remote processor identifier
+ * [in] params[0].value.b: Co-processor state identifier
+ */
+#define TA_QCOM_PAS_SET_REMOTE_STATE 7
+
+/*
+ * PAS co-processor shutdown.
+ *
+ * [in] params[0].value.a: Unique 32bit remote processor identifier
+ */
+#define TA_QCOM_PAS_SHUTDOWN 8
+
+#define TEE_NUM_PARAMS 4
+
+/**
+ * struct qcom_pas_tee_private - PAS service private data
+ * @dev: PAS service device.
+ * @ctx: TEE context handler.
+ * @session_id: PAS TA session identifier.
+ */
+struct qcom_pas_tee_private {
+ struct device *dev;
+ struct tee_context *ctx;
+ u32 session_id;
+};
+
+static bool qcom_pas_tee_supported(struct device *dev, u32 pas_id)
+{
+ struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
+ struct tee_ioctl_invoke_arg inv_arg = {
+ .func = TA_QCOM_PAS_IS_SUPPORTED,
+ .session = data->session_id,
+ .num_params = TEE_NUM_PARAMS
+ };
+ struct tee_param param[4] = {
+ [0] = {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
+ .u.value.a = pas_id
+ }
+ };
+ int ret;
+
+ ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
+ if (ret < 0 || inv_arg.ret != 0) {
+ dev_err(dev, "PAS not supported, pas_id: %d, err: %x\n",
+ pas_id, inv_arg.ret);
+ return false;
+ }
+
+ return true;
+}
+
+static int qcom_pas_tee_init_image(struct device *dev, u32 pas_id,
+ const void *metadata, size_t size,
+ struct qcom_pas_context *ctx)
+{
+ struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
+ struct tee_ioctl_invoke_arg inv_arg = {
+ .func = TA_QCOM_PAS_INIT_IMAGE,
+ .session = data->session_id,
+ .num_params = TEE_NUM_PARAMS
+ };
+ struct tee_param param[4] = {
+ [0] = {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
+ .u.value.a = pas_id
+ },
+ [1] = {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT,
+ }
+ };
+ struct tee_shm *mdata_shm;
+ u8 *mdata_buf = NULL;
+ int ret;
+
+ if (!ctx)
+ return -EINVAL;
+
+ mdata_shm = tee_shm_alloc_kernel_buf(data->ctx, size);
+ if (IS_ERR(mdata_shm)) {
+ dev_err(dev, "mdata_shm allocation failed\n");
+ return PTR_ERR(mdata_shm);
+ }
+
+ mdata_buf = tee_shm_get_va(mdata_shm, 0);
+ if (IS_ERR(mdata_buf)) {
+ dev_err(dev, "mdata_buf get VA failed\n");
+ tee_shm_free(mdata_shm);
+ return PTR_ERR(mdata_buf);
+ }
+ memcpy(mdata_buf, metadata, size);
+
+ param[1].u.memref.shm = mdata_shm;
+ param[1].u.memref.size = size;
+
+ ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
+ if (ret < 0 || inv_arg.ret != 0) {
+ dev_err(dev, "PAS init image failed, pas_id: %d, err: %x\n",
+ pas_id, inv_arg.ret);
+ tee_shm_free(mdata_shm);
+ return -EINVAL;
+ }
+ ctx->ptr = (void *)mdata_shm;
+
+ return 0;
+}
+
+static int qcom_pas_tee_mem_setup(struct device *dev, u32 pas_id,
+ phys_addr_t addr, phys_addr_t size)
+{
+ struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
+ struct tee_ioctl_invoke_arg inv_arg = {
+ .func = TA_QCOM_PAS_MEM_SETUP,
+ .session = data->session_id,
+ .num_params = TEE_NUM_PARAMS
+ };
+ struct tee_param param[4] = {
+ [0] = {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
+ .u.value.a = pas_id,
+ .u.value.b = size,
+ },
+ [1] = {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
+ .u.value.a = lower_32_bits(addr),
+ .u.value.b = upper_32_bits(addr),
+ }
+ };
+ int ret;
+
+ ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
+ if (ret < 0 || inv_arg.ret != 0) {
+ dev_err(dev, "PAS mem setup failed, pas_id: %d, err: %x\n",
+ pas_id, inv_arg.ret);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+DEFINE_FREE(shm_free, struct tee_shm *, tee_shm_free(_T))
+
+static void *qcom_pas_tee_get_rsc_table(struct device *dev,
+ struct qcom_pas_context *ctx,
+ void *input_rt, size_t input_rt_size,
+ size_t *output_rt_size)
+{
+ struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
+ struct tee_ioctl_invoke_arg inv_arg = {
+ .func = TA_QCOM_PAS_GET_RESOURCE_TABLE,
+ .session = data->session_id,
+ .num_params = TEE_NUM_PARAMS
+ };
+ struct tee_param param[4] = {
+ [0] = {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
+ .u.value.a = ctx->pas_id,
+ },
+ [1] = {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT,
+ .u.memref.size = input_rt_size,
+ }
+ };
+ void *rt_buf = NULL;
+ int ret;
+
+ ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
+ if (ret < 0 || inv_arg.ret != 0) {
+ dev_err(dev, "PAS get RT failed, pas_id: %d, err: %x\n",
+ ctx->pas_id, inv_arg.ret);
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (param[1].u.memref.size) {
+ struct tee_shm *rt_shm __free(shm_free) =
+ tee_shm_alloc_kernel_buf(data->ctx,
+ param[1].u.memref.size);
+ void *rt_shm_va;
+
+ if (IS_ERR(rt_shm)) {
+ dev_err(dev, "rt_shm allocation failed\n");
+ return rt_shm;
+ }
+
+ rt_shm_va = tee_shm_get_va(rt_shm, 0);
+ if (IS_ERR_OR_NULL(rt_shm_va)) {
+ dev_err(dev, "rt_shm get VA failed\n");
+ return ERR_PTR(-EINVAL);
+ }
+ memcpy(rt_shm_va, input_rt, input_rt_size);
+
+ param[1].u.memref.shm = rt_shm;
+ ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
+ if (ret < 0 || inv_arg.ret != 0) {
+ dev_err(dev, "PAS get RT failed, pas_id: %d, err: %x\n",
+ ctx->pas_id, inv_arg.ret);
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (param[1].u.memref.size) {
+ *output_rt_size = param[1].u.memref.size;
+ rt_buf = kmemdup(rt_shm_va, *output_rt_size, GFP_KERNEL);
+ if (!rt_buf)
+ return ERR_PTR(-ENOMEM);
+ }
+ }
+
+ return rt_buf;
+}
+
+static int __qcom_pas_tee_auth_and_reset(struct device *dev, u32 pas_id,
+ phys_addr_t mem_phys, size_t mem_size)
+{
+ struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
+ struct tee_ioctl_invoke_arg inv_arg = {
+ .func = TA_QCOM_PAS_AUTH_AND_RESET,
+ .session = data->session_id,
+ .num_params = TEE_NUM_PARAMS
+ };
+ struct tee_param param[4] = {
+ [0] = {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
+ .u.value.a = pas_id,
+ .u.value.b = mem_size,
+ },
+ [1] = {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
+ .u.value.a = lower_32_bits(mem_phys),
+ .u.value.b = upper_32_bits(mem_phys),
+ },
+ /* Reserved for fw memory space to be shared or lent */
+ [2] = {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT,
+ }
+ };
+ int ret;
+
+ ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
+ if (ret < 0 || inv_arg.ret != 0) {
+ dev_err(dev, "PAS auth reset failed, pas_id: %d, err: %x\n",
+ pas_id, inv_arg.ret);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int qcom_pas_tee_auth_and_reset(struct device *dev, u32 pas_id)
+{
+ return __qcom_pas_tee_auth_and_reset(dev, pas_id, 0, 0);
+}
+
+static int qcom_pas_tee_prepare_and_auth_reset(struct device *dev,
+ struct qcom_pas_context *ctx)
+{
+ return __qcom_pas_tee_auth_and_reset(dev, ctx->pas_id, ctx->mem_phys,
+ ctx->mem_size);
+}
+
+static int qcom_pas_tee_set_remote_state(struct device *dev, u32 state,
+ u32 pas_id)
+{
+ struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
+ struct tee_ioctl_invoke_arg inv_arg = {
+ .func = TA_QCOM_PAS_SET_REMOTE_STATE,
+ .session = data->session_id,
+ .num_params = TEE_NUM_PARAMS
+ };
+ struct tee_param param[4] = {
+ [0] = {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
+ .u.value.a = pas_id,
+ .u.value.b = state,
+ }
+ };
+ int ret;
+
+ ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
+ if (ret < 0 || inv_arg.ret != 0) {
+ dev_err(dev, "PAS shutdown failed, pas_id: %d, err: %x\n",
+ pas_id, inv_arg.ret);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int qcom_pas_tee_shutdown(struct device *dev, u32 pas_id)
+{
+ struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
+ struct tee_ioctl_invoke_arg inv_arg = {
+ .func = TA_QCOM_PAS_SHUTDOWN,
+ .session = data->session_id,
+ .num_params = TEE_NUM_PARAMS
+ };
+ struct tee_param param[4] = {
+ [0] = {
+ .attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT,
+ .u.value.a = pas_id
+ }
+ };
+ int ret = 0;
+
+ ret = tee_client_invoke_func(data->ctx, &inv_arg, param);
+ if (ret < 0 || inv_arg.ret != 0) {
+ dev_err(dev, "PAS shutdown failed, pas_id: %d, err: %x\n",
+ pas_id, inv_arg.ret);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void qcom_pas_tee_metadata_release(struct device *dev,
+ struct qcom_pas_context *ctx)
+{
+ struct tee_shm *mdata_shm = ctx->ptr;
+
+ tee_shm_free(mdata_shm);
+}
+
+static struct qcom_pas_ops qcom_pas_ops_tee = {
+ .drv_name = "qcom-pas-tee",
+ .supported = qcom_pas_tee_supported,
+ .init_image = qcom_pas_tee_init_image,
+ .mem_setup = qcom_pas_tee_mem_setup,
+ .get_rsc_table = qcom_pas_tee_get_rsc_table,
+ .auth_and_reset = qcom_pas_tee_auth_and_reset,
+ .prepare_and_auth_reset = qcom_pas_tee_prepare_and_auth_reset,
+ .set_remote_state = qcom_pas_tee_set_remote_state,
+ .shutdown = qcom_pas_tee_shutdown,
+ .metadata_release = qcom_pas_tee_metadata_release,
+};
+
+static int optee_ctx_match(struct tee_ioctl_version_data *ver, const void *data)
+{
+ return ver->impl_id == TEE_IMPL_ID_OPTEE;
+}
+
+static int qcom_pas_tee_probe(struct tee_client_device *pas_dev)
+{
+ struct device *dev = &pas_dev->dev;
+ struct qcom_pas_tee_private *data;
+ struct tee_ioctl_open_session_arg sess_arg = {
+ .clnt_login = TEE_IOCTL_LOGIN_REE_KERNEL
+ };
+ int ret, err = -ENODEV;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->ctx = tee_client_open_context(NULL, optee_ctx_match, NULL, NULL);
+ if (IS_ERR(data->ctx))
+ return -ENODEV;
+
+ export_uuid(sess_arg.uuid, &pas_dev->id.uuid);
+ ret = tee_client_open_session(data->ctx, &sess_arg, NULL);
+ if (ret < 0 || sess_arg.ret != 0) {
+ dev_err(dev, "tee_client_open_session failed, err: %x\n",
+ sess_arg.ret);
+ err = -EINVAL;
+ goto out_ctx;
+ }
+
+ data->session_id = sess_arg.session;
+ dev_set_drvdata(dev, data);
+ qcom_pas_ops_tee.dev = dev;
+ qcom_pas_ops_register(&qcom_pas_ops_tee);
+
+ return 0;
+out_ctx:
+ tee_client_close_context(data->ctx);
+
+ return err;
+}
+
+static void qcom_pas_tee_remove(struct tee_client_device *pas_dev)
+{
+ struct device *dev = &pas_dev->dev;
+ struct qcom_pas_tee_private *data = dev_get_drvdata(dev);
+
+ qcom_pas_ops_unregister();
+ tee_client_close_session(data->ctx, data->session_id);
+ tee_client_close_context(data->ctx);
+}
+
+static const struct tee_client_device_id qcom_pas_tee_id_table[] = {
+ {UUID_INIT(0xcff7d191, 0x7ca0, 0x4784,
+ 0xaf, 0x13, 0x48, 0x22, 0x3b, 0x9a, 0x4f, 0xbe)},
+ {}
+};
+MODULE_DEVICE_TABLE(tee, qcom_pas_tee_id_table);
+
+static struct tee_client_driver optee_pas_tee_driver = {
+ .probe = qcom_pas_tee_probe,
+ .remove = qcom_pas_tee_remove,
+ .id_table = qcom_pas_tee_id_table,
+ .driver = {
+ .name = "qcom-pas-tee",
+ },
+};
+
+module_tee_client_driver(optee_pas_tee_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("TEE bus based Qualcomm PAS driver");
--
2.51.0
^ permalink raw reply related
* [PATCH v3 05/15] remoteproc: qcom_q6v5_pas: Switch over to generic PAS TZ APIs
From: Sumit Garg @ 2026-03-27 13:10 UTC (permalink / raw)
To: linux-arm-msm, devicetree, dri-devel, freedreno, linux-media,
netdev, linux-wireless, ath12k, linux-remoteproc
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
harshal.dev, linux-kernel, Sumit Garg
In-Reply-To: <20260327131043.627120-1-sumit.garg@kernel.org>
From: Sumit Garg <sumit.garg@oss.qualcomm.com>
Switch qcom_q6v5_pas client driver over to generic PAS TZ APIs. Generic PAS
TZ service allows to support multiple TZ implementation backends like QTEE
based SCM PAS service, OP-TEE based PAS service and any further future TZ
backend service.
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
---
drivers/remoteproc/qcom_q6v5_pas.c | 51 +++++++++++++++---------------
1 file changed, 26 insertions(+), 25 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 46204da046fa..8c4313f5bbc2 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -20,6 +20,7 @@
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
+#include <linux/firmware/qcom/qcom_pas.h>
#include <linux/firmware/qcom/qcom_scm.h>
#include <linux/regulator/consumer.h>
#include <linux/remoteproc.h>
@@ -118,8 +119,8 @@ struct qcom_pas {
struct qcom_rproc_ssr ssr_subdev;
struct qcom_sysmon *sysmon;
- struct qcom_scm_pas_context *pas_ctx;
- struct qcom_scm_pas_context *dtb_pas_ctx;
+ struct qcom_pas_context *pas_ctx;
+ struct qcom_pas_context *dtb_pas_ctx;
};
static void qcom_pas_segment_dump(struct rproc *rproc,
@@ -196,7 +197,7 @@ static int qcom_pas_shutdown_poll_decrypt(struct qcom_pas *pas)
do {
msleep(QCOM_PAS_DECRYPT_SHUTDOWN_DELAY_MS);
- ret = qcom_scm_pas_shutdown(pas->pas_id);
+ ret = qcom_pas_shutdown(pas->pas_id);
} while (ret == -EINVAL && --retry_num);
return ret;
@@ -212,9 +213,9 @@ static int qcom_pas_unprepare(struct rproc *rproc)
* auth_and_reset() was successful, but in other cases clean it up
* here.
*/
- qcom_scm_pas_metadata_release(pas->pas_ctx);
+ qcom_pas_metadata_release(pas->pas_ctx);
if (pas->dtb_pas_id)
- qcom_scm_pas_metadata_release(pas->dtb_pas_ctx);
+ qcom_pas_metadata_release(pas->dtb_pas_ctx);
return 0;
}
@@ -228,9 +229,9 @@ static int qcom_pas_load(struct rproc *rproc, const struct firmware *fw)
pas->firmware = fw;
if (pas->lite_pas_id)
- qcom_scm_pas_shutdown(pas->lite_pas_id);
+ qcom_pas_shutdown(pas->lite_pas_id);
if (pas->lite_dtb_pas_id)
- qcom_scm_pas_shutdown(pas->lite_dtb_pas_id);
+ qcom_pas_shutdown(pas->lite_dtb_pas_id);
if (pas->dtb_pas_id) {
ret = request_firmware(&pas->dtb_firmware, pas->dtb_firmware_name, pas->dev);
@@ -250,7 +251,7 @@ static int qcom_pas_load(struct rproc *rproc, const struct firmware *fw)
return 0;
release_dtb_metadata:
- qcom_scm_pas_metadata_release(pas->dtb_pas_ctx);
+ qcom_pas_metadata_release(pas->dtb_pas_ctx);
release_firmware(pas->dtb_firmware);
return ret;
@@ -310,7 +311,7 @@ static int qcom_pas_start(struct rproc *rproc)
if (ret)
goto disable_px_supply;
- ret = qcom_scm_pas_prepare_and_auth_reset(pas->dtb_pas_ctx);
+ ret = qcom_pas_prepare_and_auth_reset(pas->dtb_pas_ctx);
if (ret) {
dev_err(pas->dev,
"failed to authenticate dtb image and release reset\n");
@@ -329,7 +330,7 @@ static int qcom_pas_start(struct rproc *rproc)
if (ret)
goto release_pas_metadata;
- ret = qcom_scm_pas_prepare_and_auth_reset(pas->pas_ctx);
+ ret = qcom_pas_prepare_and_auth_reset(pas->pas_ctx);
if (ret) {
dev_err(pas->dev,
"failed to authenticate image and release reset\n");
@@ -339,13 +340,13 @@ static int qcom_pas_start(struct rproc *rproc)
ret = qcom_q6v5_wait_for_start(&pas->q6v5, msecs_to_jiffies(5000));
if (ret == -ETIMEDOUT) {
dev_err(pas->dev, "start timed out\n");
- qcom_scm_pas_shutdown(pas->pas_id);
+ qcom_pas_shutdown(pas->pas_id);
goto unmap_carveout;
}
- qcom_scm_pas_metadata_release(pas->pas_ctx);
+ qcom_pas_metadata_release(pas->pas_ctx);
if (pas->dtb_pas_id)
- qcom_scm_pas_metadata_release(pas->dtb_pas_ctx);
+ qcom_pas_metadata_release(pas->dtb_pas_ctx);
/* firmware is used to pass reference from qcom_pas_start(), drop it now */
pas->firmware = NULL;
@@ -355,9 +356,9 @@ static int qcom_pas_start(struct rproc *rproc)
unmap_carveout:
qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size);
release_pas_metadata:
- qcom_scm_pas_metadata_release(pas->pas_ctx);
+ qcom_pas_metadata_release(pas->pas_ctx);
if (pas->dtb_pas_id)
- qcom_scm_pas_metadata_release(pas->dtb_pas_ctx);
+ qcom_pas_metadata_release(pas->dtb_pas_ctx);
unmap_dtb_carveout:
if (pas->dtb_pas_id)
@@ -406,7 +407,7 @@ static int qcom_pas_stop(struct rproc *rproc)
if (ret == -ETIMEDOUT)
dev_err(pas->dev, "timed out on wait\n");
- ret = qcom_scm_pas_shutdown(pas->pas_id);
+ ret = qcom_pas_shutdown(pas->pas_id);
if (ret && pas->decrypt_shutdown)
ret = qcom_pas_shutdown_poll_decrypt(pas);
@@ -414,7 +415,7 @@ static int qcom_pas_stop(struct rproc *rproc)
dev_err(pas->dev, "failed to shutdown: %d\n", ret);
if (pas->dtb_pas_id) {
- ret = qcom_scm_pas_shutdown(pas->dtb_pas_id);
+ ret = qcom_pas_shutdown(pas->dtb_pas_id);
if (ret)
dev_err(pas->dev, "failed to shutdown dtb: %d\n", ret);
@@ -484,11 +485,11 @@ static int qcom_pas_parse_firmware(struct rproc *rproc, const struct firmware *f
*
* Here, we call rproc_elf_load_rsc_table() to check firmware binary has resources
* or not and if it is not having then we pass NULL and zero as input resource
- * table pointer and size respectively to the argument of qcom_scm_pas_get_rsc_table()
+ * table pointer and size respectively to the argument of qcom_pas_get_rsc_table()
* and this is even true for Qualcomm remote processor who does follow remoteproc
* framework.
*/
- output_rt = qcom_scm_pas_get_rsc_table(pas->pas_ctx, table, table_sz, &output_rt_size);
+ output_rt = qcom_pas_get_rsc_table(pas->pas_ctx, table, table_sz, &output_rt_size);
ret = IS_ERR(output_rt) ? PTR_ERR(output_rt) : 0;
if (ret) {
dev_err(pas->dev, "Error in getting resource table: %d\n", ret);
@@ -746,7 +747,7 @@ static int qcom_pas_probe(struct platform_device *pdev)
if (!desc)
return -EINVAL;
- if (!qcom_scm_is_available())
+ if (!qcom_pas_is_available())
return -EPROBE_DEFER;
fw_name = desc->firmware_name;
@@ -838,16 +839,16 @@ static int qcom_pas_probe(struct platform_device *pdev)
qcom_add_ssr_subdev(rproc, &pas->ssr_subdev, desc->ssr_name);
- pas->pas_ctx = devm_qcom_scm_pas_context_alloc(pas->dev, pas->pas_id,
- pas->mem_phys, pas->mem_size);
+ pas->pas_ctx = devm_qcom_pas_context_alloc(pas->dev, pas->pas_id,
+ pas->mem_phys, pas->mem_size);
if (IS_ERR(pas->pas_ctx)) {
ret = PTR_ERR(pas->pas_ctx);
goto remove_ssr_sysmon;
}
- pas->dtb_pas_ctx = devm_qcom_scm_pas_context_alloc(pas->dev, pas->dtb_pas_id,
- pas->dtb_mem_phys,
- pas->dtb_mem_size);
+ pas->dtb_pas_ctx = devm_qcom_pas_context_alloc(pas->dev, pas->dtb_pas_id,
+ pas->dtb_mem_phys,
+ pas->dtb_mem_size);
if (IS_ERR(pas->dtb_pas_ctx)) {
ret = PTR_ERR(pas->dtb_pas_ctx);
goto remove_ssr_sysmon;
--
2.51.0
^ permalink raw reply related
* [PATCH v3 06/15] remoteproc: qcom_q6v5_mss: Switch to generic PAS TZ APIs
From: Sumit Garg @ 2026-03-27 13:10 UTC (permalink / raw)
To: linux-arm-msm, devicetree, dri-devel, freedreno, linux-media,
netdev, linux-wireless, ath12k, linux-remoteproc
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
harshal.dev, linux-kernel, Sumit Garg
In-Reply-To: <20260327131043.627120-1-sumit.garg@kernel.org>
From: Sumit Garg <sumit.garg@oss.qualcomm.com>
Switch qcom_q6v5_mss client driver over to generic PAS TZ APIs. Generic PAS
TZ service allows to support multiple TZ implementation backends like QTEE
based SCM PAS service, OP-TEE based PAS service and any further future TZ
backend service.
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
---
drivers/remoteproc/qcom_q6v5_mss.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index 91940977ca89..4d81b4af097f 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -34,6 +34,7 @@
#include "qcom_pil_info.h"
#include "qcom_q6v5.h"
+#include <linux/firmware/qcom/qcom_pas.h>
#include <linux/firmware/qcom/qcom_scm.h>
#define MPSS_CRASH_REASON_SMEM 421
@@ -1442,7 +1443,7 @@ static int q6v5_mpss_load(struct q6v5 *qproc)
}
if (qproc->version == MSS_MSM8953) {
- ret = qcom_scm_pas_mem_setup(MPSS_PAS_ID, qproc->mpss_phys, qproc->mpss_size);
+ ret = qcom_pas_mem_setup(MPSS_PAS_ID, qproc->mpss_phys, qproc->mpss_size);
if (ret) {
dev_err(qproc->dev,
"setting up mpss memory failed: %d\n", ret);
@@ -2039,7 +2040,7 @@ static int q6v5_probe(struct platform_device *pdev)
if (!desc)
return -EINVAL;
- if (desc->need_mem_protection && !qcom_scm_is_available())
+ if (desc->need_mem_protection && !qcom_pas_is_available())
return -EPROBE_DEFER;
mba_image = desc->hexagon_mba_image;
--
2.51.0
^ permalink raw reply related
* [PATCH v3 07/15] soc: qcom: mdtloader: Switch to generic PAS TZ APIs
From: Sumit Garg @ 2026-03-27 13:10 UTC (permalink / raw)
To: linux-arm-msm, devicetree, dri-devel, freedreno, linux-media,
netdev, linux-wireless, ath12k, linux-remoteproc
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
harshal.dev, linux-kernel, Sumit Garg
In-Reply-To: <20260327131043.627120-1-sumit.garg@kernel.org>
From: Sumit Garg <sumit.garg@oss.qualcomm.com>
Switch mdtloader client driver over to generic PAS TZ APIs. Generic PAS
TZ service allows to support multiple TZ implementation backends like QTEE
based SCM PAS service, OP-TEE based PAS service and any further future TZ
backend service.
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
---
drivers/soc/qcom/mdt_loader.c | 12 ++++++------
include/linux/soc/qcom/mdt_loader.h | 6 +++---
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c
index c004d444d698..fdde7eda538a 100644
--- a/drivers/soc/qcom/mdt_loader.c
+++ b/drivers/soc/qcom/mdt_loader.c
@@ -13,7 +13,7 @@
#include <linux/firmware.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/firmware/qcom/qcom_scm.h>
+#include <linux/firmware/qcom/qcom_pas.h>
#include <linux/sizes.h>
#include <linux/slab.h>
#include <linux/soc/qcom/mdt_loader.h>
@@ -229,7 +229,7 @@ EXPORT_SYMBOL_GPL(qcom_mdt_read_metadata);
static int __qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
const char *fw_name, int pas_id, phys_addr_t mem_phys,
- struct qcom_scm_pas_context *ctx)
+ struct qcom_pas_context *ctx)
{
const struct elf32_phdr *phdrs;
const struct elf32_phdr *phdr;
@@ -271,7 +271,7 @@ static int __qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
goto out;
}
- ret = qcom_scm_pas_init_image(pas_id, metadata, metadata_len, ctx);
+ ret = qcom_pas_init_image(pas_id, metadata, metadata_len, ctx);
kfree(metadata);
if (ret) {
/* Invalid firmware metadata */
@@ -280,7 +280,7 @@ static int __qcom_mdt_pas_init(struct device *dev, const struct firmware *fw,
}
if (relocate) {
- ret = qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr);
+ ret = qcom_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr);
if (ret) {
/* Unable to set up relocation */
dev_err(dev, "error %d setting up firmware %s\n", ret, fw_name);
@@ -472,7 +472,7 @@ EXPORT_SYMBOL_GPL(qcom_mdt_load);
* firmware segments (e.g., .bXX files). Authentication of the segments done
* by a separate call.
*
- * The PAS context must be initialized using qcom_scm_pas_context_init()
+ * The PAS context must be initialized using qcom_pas_context_init()
* prior to invoking this function.
*
* @ctx: Pointer to the PAS (Peripheral Authentication Service) context
@@ -483,7 +483,7 @@ EXPORT_SYMBOL_GPL(qcom_mdt_load);
*
* Return: 0 on success or a negative error code on failure.
*/
-int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmware *fw,
+int qcom_mdt_pas_load(struct qcom_pas_context *ctx, const struct firmware *fw,
const char *firmware, void *mem_region, phys_addr_t *reloc_base)
{
int ret;
diff --git a/include/linux/soc/qcom/mdt_loader.h b/include/linux/soc/qcom/mdt_loader.h
index 82372e0db0a1..142409555425 100644
--- a/include/linux/soc/qcom/mdt_loader.h
+++ b/include/linux/soc/qcom/mdt_loader.h
@@ -10,7 +10,7 @@
struct device;
struct firmware;
-struct qcom_scm_pas_context;
+struct qcom_pas_context;
#if IS_ENABLED(CONFIG_QCOM_MDT_LOADER)
@@ -20,7 +20,7 @@ int qcom_mdt_load(struct device *dev, const struct firmware *fw,
phys_addr_t mem_phys, size_t mem_size,
phys_addr_t *reloc_base);
-int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmware *fw,
+int qcom_mdt_pas_load(struct qcom_pas_context *ctx, const struct firmware *fw,
const char *firmware, void *mem_region, phys_addr_t *reloc_base);
int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw,
@@ -45,7 +45,7 @@ static inline int qcom_mdt_load(struct device *dev, const struct firmware *fw,
return -ENODEV;
}
-static inline int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx,
+static inline int qcom_mdt_pas_load(struct qcom_pas_context *ctx,
const struct firmware *fw, const char *firmware,
void *mem_region, phys_addr_t *reloc_base)
{
--
2.51.0
^ permalink raw reply related
* [PATCH v3 08/15] remoteproc: qcom_wcnss: Switch to generic PAS TZ APIs
From: Sumit Garg @ 2026-03-27 13:10 UTC (permalink / raw)
To: linux-arm-msm, devicetree, dri-devel, freedreno, linux-media,
netdev, linux-wireless, ath12k, linux-remoteproc
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
harshal.dev, linux-kernel, Sumit Garg
In-Reply-To: <20260327131043.627120-1-sumit.garg@kernel.org>
From: Sumit Garg <sumit.garg@oss.qualcomm.com>
Switch qcom_wcnss client driver over to generic PAS TZ APIs. Generic PAS
TZ service allows to support multiple TZ implementation backends like QTEE
based SCM PAS service, OP-TEE based PAS service and any further future TZ
backend service.
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
---
drivers/remoteproc/qcom_wcnss.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/remoteproc/qcom_wcnss.c b/drivers/remoteproc/qcom_wcnss.c
index 4add9037dbd5..0dbdd18ab3dd 100644
--- a/drivers/remoteproc/qcom_wcnss.c
+++ b/drivers/remoteproc/qcom_wcnss.c
@@ -19,7 +19,7 @@
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
-#include <linux/firmware/qcom/qcom_scm.h>
+#include <linux/firmware/qcom/qcom_pas.h>
#include <linux/regulator/consumer.h>
#include <linux/remoteproc.h>
#include <linux/soc/qcom/mdt_loader.h>
@@ -257,7 +257,7 @@ static int wcnss_start(struct rproc *rproc)
wcnss_indicate_nv_download(wcnss);
wcnss_configure_iris(wcnss);
- ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
+ ret = qcom_pas_auth_and_reset(WCNSS_PAS_ID);
if (ret) {
dev_err(wcnss->dev,
"failed to authenticate image and release reset\n");
@@ -269,7 +269,7 @@ static int wcnss_start(struct rproc *rproc)
if (wcnss->ready_irq > 0 && ret == 0) {
/* We have a ready_irq, but it didn't fire in time. */
dev_err(wcnss->dev, "start timed out\n");
- qcom_scm_pas_shutdown(WCNSS_PAS_ID);
+ qcom_pas_shutdown(WCNSS_PAS_ID);
ret = -ETIMEDOUT;
goto disable_iris;
}
@@ -311,7 +311,7 @@ static int wcnss_stop(struct rproc *rproc)
0);
}
- ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
+ ret = qcom_pas_shutdown(WCNSS_PAS_ID);
if (ret)
dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);
@@ -557,10 +557,10 @@ static int wcnss_probe(struct platform_device *pdev)
data = of_device_get_match_data(&pdev->dev);
- if (!qcom_scm_is_available())
+ if (!qcom_pas_is_available())
return -EPROBE_DEFER;
- if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
+ if (!qcom_pas_supported(WCNSS_PAS_ID)) {
dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
return -ENXIO;
}
--
2.51.0
^ permalink raw reply related
* [PATCH v3 09/15] remoteproc: qcom: Select QCOM_PAS generic service
From: Sumit Garg @ 2026-03-27 13:10 UTC (permalink / raw)
To: linux-arm-msm, devicetree, dri-devel, freedreno, linux-media,
netdev, linux-wireless, ath12k, linux-remoteproc
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
harshal.dev, linux-kernel, Sumit Garg
In-Reply-To: <20260327131043.627120-1-sumit.garg@kernel.org>
From: Sumit Garg <sumit.garg@oss.qualcomm.com>
Select PAS generic service driver to enable support for multiple PAS
backends like OP-TEE in addition to SCM.
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
---
drivers/remoteproc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index ee54436fea5a..da3c5d9562ea 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -230,6 +230,7 @@ config QCOM_Q6V5_PAS
select QCOM_Q6V5_COMMON
select QCOM_RPROC_COMMON
select QCOM_SCM
+ select QCOM_PAS
help
Say y here to support the TrustZone based Peripheral Image Loader for
the Qualcomm remote processors. This is commonly used to control
--
2.51.0
^ permalink raw reply related
* [PATCH v3 10/15] drm/msm: Switch to generic PAS TZ APIs
From: Sumit Garg @ 2026-03-27 13:10 UTC (permalink / raw)
To: linux-arm-msm, devicetree, dri-devel, freedreno, linux-media,
netdev, linux-wireless, ath12k, linux-remoteproc
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
harshal.dev, linux-kernel, Sumit Garg
In-Reply-To: <20260327131043.627120-1-sumit.garg@kernel.org>
From: Sumit Garg <sumit.garg@oss.qualcomm.com>
Switch drm/msm client drivers over to generic PAS TZ APIs. Generic PAS
TZ service allows to support multiple TZ implementation backends like QTEE
based SCM PAS service, OP-TEE based PAS service and any further future TZ
backend service.
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 ++++++-----
3 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 250246f81ea9..09469d56513b 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -21,6 +21,7 @@ config DRM_MSM
select SHMEM
select TMPFS
select QCOM_SCM
+ select QCOM_PAS
select QCOM_UBWC_CONFIG
select WANT_DEV_COREDUMP
select SND_SOC_HDMI_CODEC if SND_SOC
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index ef9fd6171af7..3283852f9a14 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -5,7 +5,7 @@
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/cpumask.h>
-#include <linux/firmware/qcom/qcom_scm.h>
+#include <linux/firmware/qcom/qcom_pas.h>
#include <linux/pm_opp.h>
#include <linux/nvmem-consumer.h>
#include <linux/slab.h>
@@ -653,7 +653,7 @@ static int a5xx_zap_shader_resume(struct msm_gpu *gpu)
if (adreno_is_a506(adreno_gpu))
return 0;
- ret = qcom_scm_set_remote_state(SCM_GPU_ZAP_SHADER_RESUME, GPU_PAS_ID);
+ ret = qcom_pas_set_remote_state(SCM_GPU_ZAP_SHADER_RESUME, GPU_PAS_ID);
if (ret)
DRM_ERROR("%s: zap-shader resume failed: %d\n",
gpu->name, ret);
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index d5fe6f6f0dec..047df0393128 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -8,6 +8,7 @@
#include <linux/ascii85.h>
#include <linux/interconnect.h>
+#include <linux/firmware/qcom/qcom_pas.h>
#include <linux/firmware/qcom/qcom_scm.h>
#include <linux/kernel.h>
#include <linux/of_reserved_mem.h>
@@ -146,10 +147,10 @@ static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
goto out;
/* Send the image to the secure world */
- ret = qcom_scm_pas_auth_and_reset(pasid);
+ ret = qcom_pas_auth_and_reset(pasid);
/*
- * If the scm call returns -EOPNOTSUPP we assume that this target
+ * If the pas call returns -EOPNOTSUPP we assume that this target
* doesn't need/support the zap shader so quietly fail
*/
if (ret == -EOPNOTSUPP)
@@ -175,9 +176,9 @@ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
if (!zap_available)
return -ENODEV;
- /* We need SCM to be able to load the firmware */
- if (!qcom_scm_is_available()) {
- DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");
+ /* We need PAS to be able to load the firmware */
+ if (!qcom_pas_is_available()) {
+ DRM_DEV_ERROR(&pdev->dev, "Qcom PAS is not available\n");
return -EPROBE_DEFER;
}
--
2.51.0
^ permalink raw reply related
* [PATCH v3 11/15] media: qcom: Switch to generic PAS TZ APIs
From: Sumit Garg @ 2026-03-27 13:10 UTC (permalink / raw)
To: linux-arm-msm, devicetree, dri-devel, freedreno, linux-media,
netdev, linux-wireless, ath12k, linux-remoteproc
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
harshal.dev, linux-kernel, Sumit Garg
In-Reply-To: <20260327131043.627120-1-sumit.garg@kernel.org>
From: Sumit Garg <sumit.garg@oss.qualcomm.com>
Switch qcom media client drivers over to generic PAS TZ APIs. Generic PAS
TZ service allows to support multiple TZ implementation backends like QTEE
based SCM PAS service, OP-TEE based PAS service and any further future TZ
backend service.
Along with that pass proper PAS ID to set_remote_state API. As per testing
the SCM backend just ignores it while OP-TEE makes use of it to for proper
book keeping purpose.
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/Kconfig | 25 ++++++++++---------
.../media/platform/qcom/iris/iris_firmware.c | 9 ++++---
drivers/media/platform/qcom/venus/Kconfig | 1 +
drivers/media/platform/qcom/venus/firmware.c | 11 ++++----
4 files changed, 25 insertions(+), 21 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/Kconfig b/drivers/media/platform/qcom/iris/Kconfig
index 3c803a05305a..f54b759c18aa 100644
--- a/drivers/media/platform/qcom/iris/Kconfig
+++ b/drivers/media/platform/qcom/iris/Kconfig
@@ -1,13 +1,14 @@
config VIDEO_QCOM_IRIS
- tristate "Qualcomm iris V4L2 decoder driver"
- depends on VIDEO_DEV
- depends on ARCH_QCOM || COMPILE_TEST
- select V4L2_MEM2MEM_DEV
- select QCOM_MDT_LOADER if ARCH_QCOM
- select QCOM_SCM
- select VIDEOBUF2_DMA_CONTIG
- help
- This is a V4L2 driver for Qualcomm iris video accelerator
- hardware. It accelerates decoding operations on various
- Qualcomm SoCs.
- To compile this driver as a module choose m here.
+ tristate "Qualcomm iris V4L2 decoder driver"
+ depends on VIDEO_DEV
+ depends on ARCH_QCOM || COMPILE_TEST
+ select V4L2_MEM2MEM_DEV
+ select QCOM_MDT_LOADER if ARCH_QCOM
+ select QCOM_SCM
+ select QCOM_PAS
+ select VIDEOBUF2_DMA_CONTIG
+ help
+ This is a V4L2 driver for Qualcomm iris video accelerator
+ hardware. It accelerates decoding operations on various
+ Qualcomm SoCs.
+ To compile this driver as a module choose m here.
diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c
index 5f408024e967..856fa6a79064 100644
--- a/drivers/media/platform/qcom/iris/iris_firmware.c
+++ b/drivers/media/platform/qcom/iris/iris_firmware.c
@@ -4,6 +4,7 @@
*/
#include <linux/firmware.h>
+#include <linux/firmware/qcom/qcom_pas.h>
#include <linux/firmware/qcom/qcom_scm.h>
#include <linux/of_address.h>
#include <linux/of_reserved_mem.h>
@@ -79,7 +80,7 @@ int iris_fw_load(struct iris_core *core)
return -ENOMEM;
}
- ret = qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id);
+ ret = qcom_pas_auth_and_reset(core->iris_platform_data->pas_id);
if (ret) {
dev_err(core->dev, "auth and reset failed: %d\n", ret);
return ret;
@@ -93,7 +94,7 @@ int iris_fw_load(struct iris_core *core)
cp_config->cp_nonpixel_size);
if (ret) {
dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret);
- qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
+ qcom_pas_shutdown(core->iris_platform_data->pas_id);
return ret;
}
}
@@ -103,10 +104,10 @@ int iris_fw_load(struct iris_core *core)
int iris_fw_unload(struct iris_core *core)
{
- return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
+ return qcom_pas_shutdown(core->iris_platform_data->pas_id);
}
int iris_set_hw_state(struct iris_core *core, bool resume)
{
- return qcom_scm_set_remote_state(resume, 0);
+ return qcom_pas_set_remote_state(resume, core->iris_platform_data->pas_id);
}
diff --git a/drivers/media/platform/qcom/venus/Kconfig b/drivers/media/platform/qcom/venus/Kconfig
index ffb731ecd48c..574172724e8f 100644
--- a/drivers/media/platform/qcom/venus/Kconfig
+++ b/drivers/media/platform/qcom/venus/Kconfig
@@ -6,6 +6,7 @@ config VIDEO_QCOM_VENUS
select OF_DYNAMIC if ARCH_QCOM
select QCOM_MDT_LOADER if ARCH_QCOM
select QCOM_SCM
+ select QCOM_PAS
select VIDEOBUF2_DMA_CONTIG
select V4L2_MEM2MEM_DEV
help
diff --git a/drivers/media/platform/qcom/venus/firmware.c b/drivers/media/platform/qcom/venus/firmware.c
index 1de7436713ed..3c0727ea137d 100644
--- a/drivers/media/platform/qcom/venus/firmware.c
+++ b/drivers/media/platform/qcom/venus/firmware.c
@@ -12,6 +12,7 @@
#include <linux/of_reserved_mem.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
+#include <linux/firmware/qcom/qcom_pas.h>
#include <linux/firmware/qcom/qcom_scm.h>
#include <linux/sizes.h>
#include <linux/soc/qcom/mdt_loader.h>
@@ -58,7 +59,7 @@ int venus_set_hw_state(struct venus_core *core, bool resume)
int ret;
if (core->use_tz) {
- ret = qcom_scm_set_remote_state(resume, 0);
+ ret = qcom_pas_set_remote_state(resume, VENUS_PAS_ID);
if (resume && ret == -EINVAL)
ret = 0;
return ret;
@@ -218,7 +219,7 @@ int venus_boot(struct venus_core *core)
int ret;
if (!IS_ENABLED(CONFIG_QCOM_MDT_LOADER) ||
- (core->use_tz && !qcom_scm_is_available()))
+ (core->use_tz && !qcom_pas_is_available()))
return -EPROBE_DEFER;
ret = of_property_read_string_index(dev->of_node, "firmware-name", 0,
@@ -236,7 +237,7 @@ int venus_boot(struct venus_core *core)
core->fw.mem_phys = mem_phys;
if (core->use_tz)
- ret = qcom_scm_pas_auth_and_reset(VENUS_PAS_ID);
+ ret = qcom_pas_auth_and_reset(VENUS_PAS_ID);
else
ret = venus_boot_no_tz(core, mem_phys, mem_size);
@@ -259,7 +260,7 @@ int venus_boot(struct venus_core *core)
res->cp_nonpixel_start,
res->cp_nonpixel_size);
if (ret) {
- qcom_scm_pas_shutdown(VENUS_PAS_ID);
+ qcom_pas_shutdown(VENUS_PAS_ID);
dev_err(dev, "set virtual address ranges fail (%d)\n",
ret);
return ret;
@@ -274,7 +275,7 @@ int venus_shutdown(struct venus_core *core)
int ret;
if (core->use_tz)
- ret = qcom_scm_pas_shutdown(VENUS_PAS_ID);
+ ret = qcom_pas_shutdown(VENUS_PAS_ID);
else
ret = venus_shutdown_no_tz(core);
--
2.51.0
^ permalink raw reply related
* [PATCH v3 12/15] net: ipa: Switch to generic PAS TZ APIs
From: Sumit Garg @ 2026-03-27 13:10 UTC (permalink / raw)
To: linux-arm-msm, devicetree, dri-devel, freedreno, linux-media,
netdev, linux-wireless, ath12k, linux-remoteproc
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
harshal.dev, linux-kernel, Sumit Garg
In-Reply-To: <20260327131043.627120-1-sumit.garg@kernel.org>
From: Sumit Garg <sumit.garg@oss.qualcomm.com>
Switch ipa client driver over to generic PAS TZ APIs. Generic PAS TZ
service allows to support multiple TZ implementation backends like QTEE
based SCM PAS service, OP-TEE based PAS service and any further future TZ
backend service.
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
---
drivers/net/ipa/Kconfig | 2 +-
drivers/net/ipa/ipa_main.c | 13 ++++++++-----
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ipa/Kconfig b/drivers/net/ipa/Kconfig
index 01d219d3760c..a9aff1b7977d 100644
--- a/drivers/net/ipa/Kconfig
+++ b/drivers/net/ipa/Kconfig
@@ -6,7 +6,7 @@ config QCOM_IPA
depends on QCOM_RPROC_COMMON || (QCOM_RPROC_COMMON=n && COMPILE_TEST)
depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n
select QCOM_MDT_LOADER
- select QCOM_SCM
+ select QCOM_PAS
select QCOM_QMI_HELPERS
help
Choose Y or M here to include support for the Qualcomm
diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c
index edead9c48d1f..8feb8493d5b5 100644
--- a/drivers/net/ipa/ipa_main.c
+++ b/drivers/net/ipa/ipa_main.c
@@ -14,7 +14,7 @@
#include <linux/pm_runtime.h>
#include <linux/types.h>
-#include <linux/firmware/qcom/qcom_scm.h>
+#include <linux/firmware/qcom/qcom_pas.h>
#include <linux/soc/qcom/mdt_loader.h>
#include "ipa.h"
@@ -624,10 +624,13 @@ static int ipa_firmware_load(struct device *dev)
}
ret = qcom_mdt_load(dev, fw, path, IPA_PAS_ID, virt, phys, size, NULL);
- if (ret)
+ if (ret) {
dev_err(dev, "error %d loading \"%s\"\n", ret, path);
- else if ((ret = qcom_scm_pas_auth_and_reset(IPA_PAS_ID)))
- dev_err(dev, "error %d authenticating \"%s\"\n", ret, path);
+ } else {
+ ret = qcom_pas_auth_and_reset(IPA_PAS_ID);
+ if (ret)
+ dev_err(dev, "error %d authenticating \"%s\"\n", ret, path);
+ }
memunmap(virt);
out_release_firmware:
@@ -754,7 +757,7 @@ static enum ipa_firmware_loader ipa_firmware_loader(struct device *dev)
return IPA_LOADER_INVALID;
out_self:
/* We need Trust Zone to load firmware; make sure it's available */
- if (qcom_scm_is_available())
+ if (qcom_pas_is_available())
return IPA_LOADER_SELF;
return IPA_LOADER_DEFER;
--
2.51.0
^ permalink raw reply related
* [PATCH v3 13/15] wifi: ath12k: Switch to generic PAS TZ APIs
From: Sumit Garg @ 2026-03-27 13:10 UTC (permalink / raw)
To: linux-arm-msm, devicetree, dri-devel, freedreno, linux-media,
netdev, linux-wireless, ath12k, linux-remoteproc
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
harshal.dev, linux-kernel, Sumit Garg
In-Reply-To: <20260327131043.627120-1-sumit.garg@kernel.org>
From: Sumit Garg <sumit.garg@oss.qualcomm.com>
Switch ath12k client driver over to generic PAS TZ APIs. Generic PAS TZ
service allows to support multiple TZ implementation backends like QTEE
based SCM PAS service, OP-TEE based PAS service and any further future TZ
backend service.
Acked-by: Jeff Johnson <jjohnson@kernel.org>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
---
drivers/net/wireless/ath/ath12k/Kconfig | 2 +-
drivers/net/wireless/ath/ath12k/ahb.c | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/wireless/ath/ath12k/Kconfig b/drivers/net/wireless/ath/ath12k/Kconfig
index 1ea1af1b8f6c..549d0bd77f07 100644
--- a/drivers/net/wireless/ath/ath12k/Kconfig
+++ b/drivers/net/wireless/ath/ath12k/Kconfig
@@ -19,7 +19,7 @@ config ATH12K_AHB
bool "QTI ath12k AHB support"
depends on ATH12K && REMOTEPROC
select QCOM_MDT_LOADER
- select QCOM_SCM
+ select QCOM_PAS
help
Enable support for Ath12k AHB bus chipsets, example IPQ5332.
diff --git a/drivers/net/wireless/ath/ath12k/ahb.c b/drivers/net/wireless/ath/ath12k/ahb.c
index 9a4d34e49104..935f893d04ef 100644
--- a/drivers/net/wireless/ath/ath12k/ahb.c
+++ b/drivers/net/wireless/ath/ath12k/ahb.c
@@ -5,7 +5,7 @@
*/
#include <linux/dma-mapping.h>
-#include <linux/firmware/qcom/qcom_scm.h>
+#include <linux/firmware/qcom/qcom_pas.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
@@ -415,7 +415,7 @@ static int ath12k_ahb_power_up(struct ath12k_base *ab)
}
/* Authenticate FW image using peripheral ID */
- ret = qcom_scm_pas_auth_and_reset(pasid);
+ ret = qcom_pas_auth_and_reset(pasid);
if (ret) {
ath12k_err(ab, "failed to boot the remote processor %d\n", ret);
goto err_fw2;
@@ -478,9 +478,9 @@ static void ath12k_ahb_power_down(struct ath12k_base *ab, bool is_suspend)
pasid = (u32_encode_bits(ab_ahb->userpd_id, ATH12K_USERPD_ID_MASK)) |
ATH12K_AHB_UPD_SWID;
/* Release the firmware */
- ret = qcom_scm_pas_shutdown(pasid);
+ ret = qcom_pas_shutdown(pasid);
if (ret)
- ath12k_err(ab, "scm pas shutdown failed for userPD%d: %d\n",
+ ath12k_err(ab, "pas shutdown failed for userPD%d: %d\n",
ab_ahb->userpd_id, ret);
}
--
2.51.0
^ permalink raw reply related
* [PATCH v3 14/15] firmware: qcom_scm: Remove SCM PAS wrappers
From: Sumit Garg @ 2026-03-27 13:10 UTC (permalink / raw)
To: linux-arm-msm, devicetree, dri-devel, freedreno, linux-media,
netdev, linux-wireless, ath12k, linux-remoteproc
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
harshal.dev, linux-kernel, Sumit Garg
In-Reply-To: <20260327131043.627120-1-sumit.garg@kernel.org>
From: Sumit Garg <sumit.garg@oss.qualcomm.com>
Now since all the Qcom SCM client drivers have been migrated over to
generic PAS TZ service, let's drop the exported SCM PAS wrappers.
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
---
drivers/firmware/qcom/qcom_scm.c | 143 +++++--------------------
include/linux/firmware/qcom/qcom_scm.h | 29 -----
2 files changed, 29 insertions(+), 143 deletions(-)
diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
index ab802048a719..555642f3ccdd 100644
--- a/drivers/firmware/qcom/qcom_scm.c
+++ b/drivers/firmware/qcom/qcom_scm.c
@@ -554,26 +554,6 @@ static void qcom_scm_set_download_mode(u32 dload_mode)
dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
}
-struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device *dev,
- u32 pas_id,
- phys_addr_t mem_phys,
- size_t mem_size)
-{
- struct qcom_pas_context *ctx;
-
- ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
- if (!ctx)
- return ERR_PTR(-ENOMEM);
-
- ctx->dev = dev;
- ctx->pas_id = pas_id;
- ctx->mem_phys = mem_phys;
- ctx->mem_size = mem_size;
-
- return (struct qcom_scm_pas_context *)ctx;
-}
-EXPORT_SYMBOL_GPL(devm_qcom_scm_pas_context_alloc);
-
static int __qcom_scm_pas_init_image(struct device *dev, u32 pas_id,
dma_addr_t mdata_phys,
struct qcom_scm_res *res)
@@ -631,9 +611,9 @@ static int qcom_scm_pas_prep_and_init_image(struct device *dev,
return ret ? : res.result[0];
}
-static int __qcom_scm_pas_init_image2(struct device *dev, u32 pas_id,
- const void *metadata, size_t size,
- struct qcom_pas_context *ctx)
+static int qcom_scm_pas_init_image(struct device *dev, u32 pas_id,
+ const void *metadata, size_t size,
+ struct qcom_pas_context *ctx)
{
struct qcom_scm_res res;
dma_addr_t mdata_phys;
@@ -673,16 +653,8 @@ static int __qcom_scm_pas_init_image2(struct device *dev, u32 pas_id,
return ret ? : res.result[0];
}
-int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size,
- struct qcom_scm_pas_context *ctx)
-{
- return __qcom_scm_pas_init_image2(__scm->dev, pas_id, metadata, size,
- (struct qcom_pas_context *)ctx);
-}
-EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image);
-
-static void __qcom_scm_pas_metadata_release(struct device *dev,
- struct qcom_pas_context *ctx)
+static void qcom_scm_pas_metadata_release(struct device *dev,
+ struct qcom_pas_context *ctx)
{
if (ctx->use_tzmem)
qcom_tzmem_free(ctx->ptr);
@@ -692,15 +664,8 @@ static void __qcom_scm_pas_metadata_release(struct device *dev,
ctx->ptr = NULL;
}
-void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx)
-{
- __qcom_scm_pas_metadata_release(__scm->dev,
- (struct qcom_pas_context *)ctx);
-}
-EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release);
-
-static int __qcom_scm_pas_mem_setup(struct device *dev, u32 pas_id,
- phys_addr_t addr, phys_addr_t size)
+static int qcom_scm_pas_mem_setup(struct device *dev, u32 pas_id,
+ phys_addr_t addr, phys_addr_t size)
{
int ret;
struct qcom_scm_desc desc = {
@@ -731,12 +696,6 @@ static int __qcom_scm_pas_mem_setup(struct device *dev, u32 pas_id,
return ret ? : res.result[0];
}
-int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size)
-{
- return __qcom_scm_pas_mem_setup(__scm->dev, pas_id, addr, size);
-}
-EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup);
-
static void *__qcom_scm_pas_get_rsc_table(struct device *dev, u32 pas_id,
void *input_rt_tzm,
size_t input_rt_size,
@@ -790,11 +749,10 @@ static void *__qcom_scm_pas_get_rsc_table(struct device *dev, u32 pas_id,
return ret ? ERR_PTR(ret) : output_rt_tzm;
}
-static void *__qcom_scm_pas_get_rsc_table2(struct device *dev,
- struct qcom_pas_context *ctx,
- void *input_rt,
- size_t input_rt_size,
- size_t *output_rt_size)
+static void *qcom_scm_pas_get_rsc_table(struct device *dev,
+ struct qcom_pas_context *ctx,
+ void *input_rt, size_t input_rt_size,
+ size_t *output_rt_size)
{
struct resource_table empty_rsc = {};
size_t size = SZ_16K;
@@ -866,19 +824,7 @@ static void *__qcom_scm_pas_get_rsc_table2(struct device *dev,
return ret ? ERR_PTR(ret) : tbl_ptr;
}
-struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_context *ctx,
- void *input_rt,
- size_t input_rt_size,
- size_t *output_rt_size)
-{
- return __qcom_scm_pas_get_rsc_table2(__scm->dev,
- (struct qcom_pas_context *)ctx,
- input_rt, input_rt_size,
- output_rt_size);
-}
-EXPORT_SYMBOL_GPL(qcom_scm_pas_get_rsc_table);
-
-static int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 pas_id)
+static int qcom_scm_pas_auth_and_reset(struct device *dev, u32 pas_id)
{
int ret;
struct qcom_scm_desc desc = {
@@ -907,14 +853,8 @@ static int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 pas_id)
return ret ? : res.result[0];
}
-int qcom_scm_pas_auth_and_reset(u32 pas_id)
-{
- return __qcom_scm_pas_auth_and_reset(__scm->dev, pas_id);
-}
-EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset);
-
-static int __qcom_scm_pas_prepare_and_auth_reset(struct device *dev,
- struct qcom_pas_context *ctx)
+static int qcom_scm_pas_prepare_and_auth_reset(struct device *dev,
+ struct qcom_pas_context *ctx)
{
u64 handle;
int ret;
@@ -925,7 +865,7 @@ static int __qcom_scm_pas_prepare_and_auth_reset(struct device *dev,
* memory region and then invokes a call to TrustZone to authenticate.
*/
if (!ctx->use_tzmem)
- return __qcom_scm_pas_auth_and_reset(dev, ctx->pas_id);
+ return qcom_scm_pas_auth_and_reset(dev, ctx->pas_id);
/*
* When Linux runs @ EL2 Linux must create the shmbridge itself and then
@@ -935,21 +875,14 @@ static int __qcom_scm_pas_prepare_and_auth_reset(struct device *dev,
if (ret)
return ret;
- ret = __qcom_scm_pas_auth_and_reset(dev, ctx->pas_id);
+ ret = qcom_scm_pas_auth_and_reset(dev, ctx->pas_id);
qcom_tzmem_shm_bridge_delete(handle);
return ret;
}
-int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx)
-{
- return __qcom_scm_pas_prepare_and_auth_reset(__scm->dev,
- (struct qcom_pas_context *)ctx);
-}
-EXPORT_SYMBOL_GPL(qcom_scm_pas_prepare_and_auth_reset);
-
-static int __qcom_scm_pas_set_remote_state(struct device *dev, u32 state,
- u32 pas_id)
+static int qcom_scm_pas_set_remote_state(struct device *dev, u32 state,
+ u32 pas_id)
{
struct qcom_scm_desc desc = {
.svc = QCOM_SCM_SVC_BOOT,
@@ -967,13 +900,7 @@ static int __qcom_scm_pas_set_remote_state(struct device *dev, u32 state,
return ret ? : res.result[0];
}
-int qcom_scm_set_remote_state(u32 state, u32 id)
-{
- return __qcom_scm_pas_set_remote_state(__scm->dev, state, id);
-}
-EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state);
-
-static int __qcom_scm_pas_shutdown(struct device *dev, u32 pas_id)
+static int qcom_scm_pas_shutdown(struct device *dev, u32 pas_id)
{
int ret;
struct qcom_scm_desc desc = {
@@ -1002,13 +929,7 @@ static int __qcom_scm_pas_shutdown(struct device *dev, u32 pas_id)
return ret ? : res.result[0];
}
-int qcom_scm_pas_shutdown(u32 pas_id)
-{
- return __qcom_scm_pas_shutdown(__scm->dev, pas_id);
-}
-EXPORT_SYMBOL_GPL(qcom_scm_pas_shutdown);
-
-static bool __qcom_scm_pas_supported(struct device *dev, u32 pas_id)
+static bool qcom_scm_pas_supported(struct device *dev, u32 pas_id)
{
int ret;
struct qcom_scm_desc desc = {
@@ -1029,23 +950,17 @@ static bool __qcom_scm_pas_supported(struct device *dev, u32 pas_id)
return ret ? false : !!res.result[0];
}
-bool qcom_scm_pas_supported(u32 pas_id)
-{
- return __qcom_scm_pas_supported(__scm->dev, pas_id);
-}
-EXPORT_SYMBOL_GPL(qcom_scm_pas_supported);
-
static struct qcom_pas_ops qcom_pas_ops_scm = {
.drv_name = "qcom_scm",
- .supported = __qcom_scm_pas_supported,
- .init_image = __qcom_scm_pas_init_image2,
- .mem_setup = __qcom_scm_pas_mem_setup,
- .get_rsc_table = __qcom_scm_pas_get_rsc_table2,
- .auth_and_reset = __qcom_scm_pas_auth_and_reset,
- .prepare_and_auth_reset = __qcom_scm_pas_prepare_and_auth_reset,
- .set_remote_state = __qcom_scm_pas_set_remote_state,
- .shutdown = __qcom_scm_pas_shutdown,
- .metadata_release = __qcom_scm_pas_metadata_release,
+ .supported = qcom_scm_pas_supported,
+ .init_image = qcom_scm_pas_init_image,
+ .mem_setup = qcom_scm_pas_mem_setup,
+ .get_rsc_table = qcom_scm_pas_get_rsc_table,
+ .auth_and_reset = qcom_scm_pas_auth_and_reset,
+ .prepare_and_auth_reset = qcom_scm_pas_prepare_and_auth_reset,
+ .set_remote_state = qcom_scm_pas_set_remote_state,
+ .shutdown = qcom_scm_pas_shutdown,
+ .metadata_release = qcom_scm_pas_metadata_release,
};
/**
diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h
index 5747bd191bf1..a0a6bc0229c4 100644
--- a/include/linux/firmware/qcom/qcom_scm.h
+++ b/include/linux/firmware/qcom/qcom_scm.h
@@ -64,35 +64,6 @@ bool qcom_scm_is_available(void);
int qcom_scm_set_cold_boot_addr(void *entry);
int qcom_scm_set_warm_boot_addr(void *entry);
void qcom_scm_cpu_power_down(u32 flags);
-int qcom_scm_set_remote_state(u32 state, u32 id);
-
-struct qcom_scm_pas_context {
- struct device *dev;
- u32 pas_id;
- phys_addr_t mem_phys;
- size_t mem_size;
- void *ptr;
- dma_addr_t phys;
- ssize_t size;
- bool use_tzmem;
-};
-
-struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device *dev,
- u32 pas_id,
- phys_addr_t mem_phys,
- size_t mem_size);
-int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size,
- struct qcom_scm_pas_context *ctx);
-void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx);
-int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size);
-int qcom_scm_pas_auth_and_reset(u32 pas_id);
-int qcom_scm_pas_shutdown(u32 pas_id);
-bool qcom_scm_pas_supported(u32 pas_id);
-struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_context *ctx,
- void *input_rt, size_t input_rt_size,
- size_t *output_rt_size);
-
-int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx);
int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
--
2.51.0
^ permalink raw reply related
* [PATCH v3 15/15] MAINTAINERS: Add maintainer entry for Qualcomm PAS TZ service
From: Sumit Garg @ 2026-03-27 13:10 UTC (permalink / raw)
To: linux-arm-msm, devicetree, dri-devel, freedreno, linux-media,
netdev, linux-wireless, ath12k, linux-remoteproc
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
harshal.dev, linux-kernel, Sumit Garg
In-Reply-To: <20260327131043.627120-1-sumit.garg@kernel.org>
From: Sumit Garg <sumit.garg@oss.qualcomm.com>
Add Sumit Garg as the maintainer for the Qualcomm generic Peripheral
Authentication Service (PAS) as well as the PAS TEE backend driver.
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0481aca2286c..1a50ce3e204e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21806,6 +21806,15 @@ F: Documentation/devicetree/bindings/media/*qcom*
F: drivers/media/platform/qcom
F: include/dt-bindings/media/*qcom*
+QUALCOMM PAS TZ SERVICE
+M: Sumit Garg <sumit.garg@oss.qualcomm.com>
+L: linux-arm-msm@vger.kernel.org
+S: Maintained
+F: drivers/firmware/qcom/qcom_pas.c
+F: drivers/firmware/qcom/qcom_pas.h
+F: drivers/firmware/qcom/qcom_pas_tee.c
+F: include/linux/firmware/qcom/qcom_pas.h
+
QUALCOMM SMB CHARGER DRIVER
M: Casey Connolly <casey.connolly@linaro.org>
L: linux-arm-msm@vger.kernel.org
--
2.51.0
^ permalink raw reply related
* Re: [PATCH v1 1/4] ASoC: dt-bindings: qcom,q6apm-lpass-dais: Document DAI subnode
From: Mohammad Rafi Shaik @ 2026-03-27 13:16 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Srinivas Kandagatla, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
linux-sound, linux-arm-msm, devicetree, linux-kernel,
Srinivas Kandagatla
In-Reply-To: <376ad62e-e6b5-438b-a23a-0988b6489e5c@kernel.org>
On 3/26/2026 3:40 PM, Krzysztof Kozlowski wrote:
> On 26/03/2026 10:57, Mohammad Rafi Shaik wrote:
>>
>>
>> On 3/17/2026 12:41 PM, Krzysztof Kozlowski wrote:
>>> On 17/03/2026 06:27, Mohammad Rafi Shaik wrote:
>>>>
>>>>
>>>> On 3/10/2026 3:25 PM, Krzysztof Kozlowski wrote:
>>>>> On Mon, Mar 09, 2026 at 04:42:57PM +0530, Mohammad Rafi Shaik wrote:
>>>>>> Extend the qcom,q6apm-lpass-dais device tree binding to explicitly
>>>>>> describe Digital Audio Interface (DAI) child nodes.
>>>>>>
>>>>>> Add #address-cells and #size-cells to allow representation of multiple
>>>>>> DAI instances as child nodes, and define a dai@<id> pattern to document
>>>>>> per-DAI properties such as the interface ID and associated clocks.
>>>>>>
>>>>>> Qualcomm platforms like talos integrate third-party audio codecs or use
>>>>>> different external audio paths. These designs often require additional
>>>>>> configuration such as explicit MI2S MCLK settings for audio to work.
>>>>>>
>>>>>> Co-developed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
>>>>>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
>>>>>> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
>>>>>> ---
>>>>>> .../bindings/sound/qcom,q6apm-lpass-dais.yaml | 41 ++++++++++++++++++-
>>>>>> 1 file changed, 40 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml b/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml
>>>>>> index 2fb95544d..1d770cbcb 100644
>>>>>> --- a/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml
>>>>>> +++ b/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml
>>>>>> @@ -21,6 +21,34 @@ properties:
>>>>>> '#sound-dai-cells':
>>>>>> const: 1
>>>>>>
>>>>>> + '#address-cells':
>>>>>> + const: 1
>>>>>> +
>>>>>> + '#size-cells':
>>>>>> + const: 0
>>>>>> +
>>>>>> +# Digital Audio Interfaces
>>>>>> +patternProperties:
>>>>>> + '^dai@[0-9]+$':
>>>>>> + type: object
>>>>>> + description:
>>>>>> + Q6DSP Digital Audio Interfaces.
>>>>>> +
>>>>>> + properties:
>>>>>> + reg:
>>>>>> + description:
>>>>>> + Digital Audio Interface ID
>>>>>> +
>>>>>> + clocks:
>>>>>> + minItems: 1
>>>>>> + maxItems: 3
>>>>>> +
>>>>>> + clock-names:
>>>>>> + minItems: 1
>>>>>> + maxItems: 3
>>>>>
>>>>> No, this is just way too generic. There is no such syntax in the kernel
>>>>> and this should stop you right there. You are not allowed to add your
>>>>> own style.
>>>>>
>>>>> I don't think DAI is here a separate device needing its own resources
>>>>> expressed in DT. This is still part of ADSP so you just described in DT
>>>>> internal routing between two services on ADSP.
>>>>>
>>>>
>>>> Thanks for reviewing.
>>>>
>>>> I’d like to clarify that this is not intended to model the DAI as a
>>>> separate physical device or to describe internal ADSP routing.
>>>
>>> If you do not want to represent the physical device, then I don't think
>>> it should be represented at all.
>>>
>>>>
>>>> Requirement is to allow the kernel to send clock‑voting requests to the
>>>> ADSP. LPASS MCLK routing is not enabled by default on the ADSP, so the
>>>> kernel must explicitly request the ADSP to enable the relevant LPASS
>>>> MCLKs, which is a real hardware control requirement.
>>>>
>>>> These clocks are LPASS‑owned, and driving them via a third‑party codec
>>>> is not appropriate. The intent of adding clock capabilities at the DAI
>>>> level is to allow the kernel to associate LPASS clock votes with a
>>>> specific DAI instance during stream activity.
>>>>
>>>> While the DAI itself is not a physical device, some DT representation is
>>>> required to describe per‑DAI LPASS clock requirements.
>>>
>>> DT's purpose is not to describe software constructs, thus DT is not the
>>> answer to your requirement of mapping clocks to specific DAI needs.
>>> Every person adding software properties made "some DT representation is
>>> required" claim.
>>>
>>>>
>>>> I’m open to considering alternative representations, but removing this
>>>> entirely would leave no generic way for the kernel to handle correct
>>>> LPASS MCLK voting.
>>>
>>> I imagine that, since this is software construct, the software knows
>>> which DAI needs which clock. Clocks are strictly defined, thus driver
>>> should handle all this.
>>>
>>
>> No, the MCLK connection is not fixed to a specific DAI.
>>
>> The LPASS MCLKs
>> LPASS_CLK_ID_MCLK_1 … LPASS_CLK_ID_MCLK_5
>>
>> are hard‑wired connection, each physically routed to an external codec
>> on the board.
>>
>> Because of this, the clock that must be voted depends purely on the
>> hardware wiring, not on which DAI (Primary/Secondary/Tertiary/Quaternary
>> MI2S) is used.
>
> If they are routed to external codecs, then they are already present in
> these nodes and duplicating them here is not necessary.
>
>>
>> In other words, DAI ↔ MCLK is not a fixed mapping.
>>
>> Examples:
>> On Talos‑EVK, the speaker is connected via Primary MI2S, but the
>> corresponding MCLK line wired to the codec is LPASS_CLK_ID_MCLK_2.
>>
>> On Kodiak, the customer connected an SGTL5000 codec via Quaternary MI2S,
>> yet the required MCLK is still LPASS_CLK_ID_MCLK_2.
>>
>> Instead, the kernel must vote for the MCLK that is physically connected
>> to the external codec on that specific board.
>
> No, the external codec driver must vote for that MCLK.
>
I agree that when the MCLK provider is external, it is appropriate for
the codec driver to manage that clock. However, in this case the MCLK
provider is the LPASS/DSP subsystem itself, and the external codec is
only a consumer.
LPASS MCLKs configurations inside the DSP can be lost or reprogrammed
during DSP power collapse or subsystem restart (SSR).
Without visibility into LPASS lifecycle(SSR) events, a third‑party codec
driver cannot reliably perform clock voting or restoration, resulting in
broken or inconsistent audio behavior.
For these reasons, MCLK voting needs to remain owned by the LPASS/HLOS
drivers, which have awareness of DSP power state and board wiring,
Thanks & Regards,
Rafi.
> Best regards,
> Krzysztof
^ permalink raw reply
* Re: [PATCH 1/8] regulator: pbias: Add pbias SIM regulator for OMAP4
From: Thomas Richard @ 2026-03-27 13:18 UTC (permalink / raw)
To: Andreas Kemnade
Cc: Aaro Koskinen, Kevin Hilman, Roger Quadros, Tony Lindgren,
Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Thomas Petazzoni, linux-omap,
linux-kernel, devicetree
In-Reply-To: <20260327133612.6ee909fd@kemnade.info>
Hello Andreas,
Thanks for the review.
On 3/27/26 1:36 PM, Andreas Kemnade wrote:
> On Mon, 23 Mar 2026 16:02:42 +0100
> Thomas Richard <thomas.richard@bootlin.com> wrote:
>
>> Add support for the pbias SIM regulator found on OMAP4 (for USB I/O cell).
>>
>> Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
>> ---
>> drivers/regulator/pbias-regulator.c | 11 +++++++++++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/drivers/regulator/pbias-regulator.c b/drivers/regulator/pbias-regulator.c
>> index cd5a0d7e44555f04d1e44470036c6e3d9feb7be6..10c4940e73635293bebd26bf99a9067eb6e39107 100644
>> --- a/drivers/regulator/pbias-regulator.c
>> +++ b/drivers/regulator/pbias-regulator.c
>> @@ -81,6 +81,16 @@ static const struct pbias_reg_info pbias_sim_omap3 = {
>> .name = "pbias_sim_omap3"
>> };
>>
>> +static const struct pbias_reg_info pbias_sim_omap4 = {
>> + .enable = BIT(28) | BIT(20),
>> + .enable_mask = BIT(31) | BIT(28) | BIT(20),
>> + .vmode = BIT(31),
>
> BIT(27)? or am I mixing something up?
No you're right, I did a mistake.
I'll send a v2 in the next few days to address this, Mark's and Conor's
feedback, as well as few other issues I identified.
Best Regards,
Thomas
^ permalink raw reply
* Re: [PATCH v1 1/4] ASoC: dt-bindings: qcom,q6apm-lpass-dais: Document DAI subnode
From: Krzysztof Kozlowski @ 2026-03-27 13:23 UTC (permalink / raw)
To: Mohammad Rafi Shaik
Cc: Srinivas Kandagatla, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaroslav Kysela, Takashi Iwai,
linux-sound, linux-arm-msm, devicetree, linux-kernel,
Srinivas Kandagatla
In-Reply-To: <2e03441e-4353-4927-8630-aa7730c4033e@oss.qualcomm.com>
On 27/03/2026 14:16, Mohammad Rafi Shaik wrote:
>>
>>>
>>> In other words, DAI ↔ MCLK is not a fixed mapping.
>>>
>>> Examples:
>>> On Talos‑EVK, the speaker is connected via Primary MI2S, but the
>>> corresponding MCLK line wired to the codec is LPASS_CLK_ID_MCLK_2.
>>>
>>> On Kodiak, the customer connected an SGTL5000 codec via Quaternary MI2S,
>>> yet the required MCLK is still LPASS_CLK_ID_MCLK_2.
>>>
>>> Instead, the kernel must vote for the MCLK that is physically connected
>>> to the external codec on that specific board.
>>
>> No, the external codec driver must vote for that MCLK.
>>
>
> I agree that when the MCLK provider is external, it is appropriate for
> the codec driver to manage that clock. However, in this case the MCLK
> provider is the LPASS/DSP subsystem itself, and the external codec is
> only a consumer.
>
> LPASS MCLKs configurations inside the DSP can be lost or reprogrammed
> during DSP power collapse or subsystem restart (SSR).
>
> Without visibility into LPASS lifecycle(SSR) events, a third‑party codec
> driver cannot reliably perform clock voting or restoration, resulting in
> broken or inconsistent audio behavior.
>
> For these reasons, MCLK voting needs to remain owned by the LPASS/HLOS
> drivers, which have awareness of DSP power state and board wiring,
Sounds like you just brought driver model as the arguments here, so not
correct for DT.
But even if we speak about drivers, then I think I also assumption that
only clock consumer driver can manage the clock is not true. The
provider, so LPASS/DSP knows what is happening with entire audio so it
tracks the usage of its clocks and can perform clock
disable/unprepare/prepare/restoration or whatever there is needed.
Anyway, that's not important here. First argument is - you just wrote
stuff for drivers and that we don't want.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v9 2/9] lib: vsprintf: export simple_strntoull() in a safe prototype
From: David Laight @ 2026-03-27 13:28 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Petr Mladek, rodrigo.alencar, linux-kernel, linux-iio, devicetree,
linux-doc, Jonathan Cameron, David Lechner, Andy Shevchenko,
Lars-Peter Clausen, Michael Hennerich, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jonathan Corbet, Andrew Morton,
Steven Rostedt, Rasmus Villemoes, Sergey Senozhatsky, Shuah Khan
In-Reply-To: <acZitENbWQF7cmDA@ashevche-desk.local>
On Fri, 27 Mar 2026 12:57:56 +0200
Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote:
> On Fri, Mar 27, 2026 at 10:44:40AM +0000, David Laight wrote:
,,,
> > > but also wants to have the fraction part be limited in some cases to s32
> > > or so:
> > >
> > > struct float
> > > {
> > > s64 integer;
> > > s32 fraction; // precision may be lost if input is longer
> > > }
> >
> > Are those 'fraction' counts of (say) 10^-6 (like times in seconds+usecs)
> > or true binary values where the value could be treated as a u64 (or u128)
> > for addition and subtraction.
>
> It depends. IIO has scale on top of that, so the fraction part can be 10⁻³,
> 10⁻⁶, 10⁻⁹. I don't remember by heart if the ABI requires all digits to be
> placed, I think we don't require that.
Seems like you want this function (untested):
u64 strtofrac(const char *buf, const char **end, unsigned int len)
{
u64 val = 0;
unsigned int digit;
while (len--) {
digit = *buf - '0';
if (digit <= 9) {
buf++;
val += digit;
}
val *= 10;
}
while (*buf - '0' <= 9u)
buf++;
*end = buf;
return val;
}
David
^ permalink raw reply
* [PATCH v4 1/6] dt-bindings: display: panel: Add Novatek NT35532 LCD DSI
From: Cristian Cozzolino via B4 Relay @ 2026-03-27 14:30 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, Cristian Cozzolino
In-Reply-To: <20260327-rimob-new-features-v4-0-06edff9c4509@protonmail.com>
From: Cristian Cozzolino <cristian_ci@protonmail.com>
Document Novatek NT35532-based DSI display panel.
Since it's not possible to identify panel vendor nor id, add a suitable
compatible (matching the device's user, which makes use of this DDIC)
and set "novatek,nt35532" as fallback.
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
---
.../bindings/display/panel/novatek,nt35532.yaml | 80 ++++++++++++++++++++++
MAINTAINERS | 5 ++
2 files changed, 85 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml
new file mode 100644
index 000000000000..ff6fdad7febf
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/novatek,nt35532.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Novatek NT35532-based DSI display panels
+
+maintainers:
+ - Cristian Cozzolino <cristian_ci@protonmail.com>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - flipkart,rimob-panel-nt35532-cs
+ - const: novatek,nt35532
+
+ reg:
+ maxItems: 1
+
+ backlight: true
+ reset-gpios: true
+
+ avdd-supply:
+ description: positive boost supply regulator
+
+ avee-supply:
+ description: negative boost supply regulator
+
+ vci-supply:
+ description: regulator that supplies the analog voltage
+
+ vddam-supply:
+ description: power supply for MIPI interface
+
+ vddi-supply:
+ description: regulator that supplies the I/O voltage
+
+ port: true
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+ - vddi-supply
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "flipkart,rimob-panel-nt35532-cs", "novatek,nt35532";
+ reg = <0>;
+
+ backlight = <&pmi8950_wled>;
+ reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
+ avdd-supply = <&lab>;
+ avee-supply = <&ibb>;
+ vci-supply = <&pm8953_l17>;
+ vddi-supply = <&pm8953_l6>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 80b9074e96ae..792ce6ee8616 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8174,6 +8174,11 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml
F: drivers/gpu/drm/panel/panel-novatek-nt35510.c
+DRM DRIVER FOR NOVATEK NT35532 PANELS
+M: Cristian Cozzolino <cristian_ci@protonmail.com>
+S: Maintained
+F: Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml
+
DRM DRIVER FOR NOVATEK NT35560 PANELS
M: Linus Walleij <linusw@kernel.org>
S: Maintained
--
2.53.0
^ permalink raw reply related
* [PATCH v4 2/6] drm/panel: Add driver for Novatek NT35532
From: Cristian Cozzolino via B4 Relay @ 2026-03-27 14:30 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, Cristian Cozzolino
In-Reply-To: <20260327-rimob-new-features-v4-0-06edff9c4509@protonmail.com>
From: Cristian Cozzolino <cristian_ci@protonmail.com>
Add support for Novatek NT35532-based 1080p video mode DSI panel.
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
---
MAINTAINERS | 1 +
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-novatek-nt35532.c | 796 ++++++++++++++++++++++++++
4 files changed, 808 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 792ce6ee8616..f58e9d9ee5c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8178,6 +8178,7 @@ DRM DRIVER FOR NOVATEK NT35532 PANELS
M: Cristian Cozzolino <cristian_ci@protonmail.com>
S: Maintained
F: Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml
+F: drivers/gpu/drm/panel/panel-novatek-nt35532.c
DRM DRIVER FOR NOVATEK NT35560 PANELS
M: Linus Walleij <linusw@kernel.org>
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index d6863b28ddc5..386fb6f1ff50 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -549,6 +549,16 @@ config DRM_PANEL_NOVATEK_NT35510
around the Novatek NT35510 display controller, such as some
Hydis panels.
+config DRM_PANEL_NOVATEK_NT35532
+ tristate "Novatek NT35532-based DSI video mode panel"
+ depends on OF
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ select DRM_KMS_HELPER
+ help
+ Say Y or M here if you want to enable support for Novatek
+ NT35532-based 1080p video mode DSI panels.
+
config DRM_PANEL_NOVATEK_NT35560
tristate "Novatek NT35560 DSI command mode panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index a4291dc3905b..7caf60dd3f57 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_DRM_PANEL_NEC_NL8048HL11) += panel-nec-nl8048hl11.o
obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3051D) += panel-newvision-nv3051d.o
obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3052C) += panel-newvision-nv3052c.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35510) += panel-novatek-nt35510.o
+obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35532) += panel-novatek-nt35532.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35560) += panel-novatek-nt35560.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35950) += panel-novatek-nt35950.o
obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36523) += panel-novatek-nt36523.o
diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35532.c b/drivers/gpu/drm/panel/panel-novatek-nt35532.c
new file mode 100644
index 000000000000..184f61bca7ca
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-novatek-nt35532.c
@@ -0,0 +1,796 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree.
+ * Copyright (c) 2026 Cristian Cozzolino <cristian_ci@protonmail.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/property.h>
+#include <linux/regulator/consumer.h>
+
+#include <video/mipi_display.h>
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_probe_helper.h>
+
+struct novatek_nt35532 {
+ struct drm_panel panel;
+ struct mipi_dsi_device *dsi;
+ struct regulator_bulk_data *supplies;
+ struct gpio_desc *reset_gpio;
+ const struct nt35532_panel_desc *desc;
+};
+
+struct nt35532_panel_desc {
+ const struct drm_display_mode *mode;
+ int (*on)(struct novatek_nt35532 *ctx);
+};
+
+static const struct regulator_bulk_data nt35532_supplies[] = {
+ { .supply = "vci" },
+ { .supply = "vddi" },
+ { .supply = "avee" },
+ { .supply = "avdd" },
+};
+
+static inline struct novatek_nt35532 *to_novatek_nt35532(struct drm_panel *panel)
+{
+ return container_of_const(panel, struct novatek_nt35532, panel);
+}
+
+static void nt35532_reset(struct novatek_nt35532 *ctx)
+{
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ usleep_range(10000, 11000);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ usleep_range(5000, 6000);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ usleep_range(10000, 11000);
+}
+
+static int rimob_panel_on(struct novatek_nt35532 *ctx)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6e, 0x80);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x68, 0x13);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x05);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0x31);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0x7e);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x01, 0x55);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x04, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x05, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x06, 0x50);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x07, 0xd0);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0a, 0x0f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0c, 0x06);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0d, 0x6b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0e, 0x6b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0f, 0x70);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x10, 0x63);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x11, 0x3c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x12, 0x5c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x15, 0x60);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x16, 0x15);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x17, 0x15);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5b, 0xca);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5c, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5d, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5f, 0x1b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x60, 0xd5);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x61, 0xf0);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6c, 0xab);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6d, 0x44);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6e, 0x80);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x05);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x00, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x01, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x02, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x03, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x04, 0x38);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x05, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x06, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x07, 0x19);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x08, 0x1b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x09, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0a, 0x1d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0b, 0x17);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0c, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0d, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0e, 0x08);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0f, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x10, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x11, 0x10);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x12, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x13, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x14, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x15, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x16, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x17, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x18, 0x38);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x19, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1a, 0x1a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1b, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1c, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1d, 0x1c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1e, 0x16);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1f, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x20, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x21, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x22, 0x06);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x23, 0x0a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x24, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x25, 0x0e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x26, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x27, 0x3f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x54, 0x08);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x55, 0x07);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x56, 0x1a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x58, 0x19);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x59, 0x36);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5a, 0x1b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5b, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5c, 0x32);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5e, 0x27);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5f, 0x28);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x60, 0x2b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x61, 0x2c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x62, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x63, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x64, 0x32);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x65, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x66, 0x44);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x67, 0x11);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x68, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x69, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6a, 0x06);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6b, 0x22);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6c, 0x08);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6d, 0x08);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x78, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x79, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7e, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7f, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x80, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x81, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8d, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8e, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8f, 0xc0);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x90, 0x73);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x91, 0x10);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x92, 0x09);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x96, 0x11);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x97, 0x14);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x98, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x99, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9a, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9b, 0x61);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9c, 0x15);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9d, 0x30);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9f, 0x0f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa2, 0xb0);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa7, 0x0a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa9, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaa, 0x70);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xab, 0xda);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xac, 0xff);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xae, 0xf4);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaf, 0x40);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x7f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x16);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, 0x53);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb3, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb4, 0x2a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb5, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb6, 0xf0);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbc, 0x85);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbd, 0xf8);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbe, 0x3b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbf, 0x13);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x77);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0xaa);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc9, 0x2a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcb, 0xaa);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcc, 0x92);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcf, 0x88);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd0, 0xaa);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd1, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd2, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xed, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xee, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xef, 0x70);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfa, 0x03);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x75, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x76, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x77, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x78, 0x20);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x79, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7a, 0x49);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7b, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7c, 0x66);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7d, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7e, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7f, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x80, 0x91);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x81, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x82, 0xa3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0xb3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x85, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x86, 0xc1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x87, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x88, 0xf1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x89, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8a, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8b, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8c, 0x54);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8d, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8e, 0x85);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8f, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x90, 0xd1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x91, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x92, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x93, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x94, 0x0e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x95, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x96, 0x43);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x97, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x98, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x99, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9a, 0xa2);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9b, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9c, 0xd7);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9d, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9e, 0xf8);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9f, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa0, 0x2b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa2, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa3, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa4, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa5, 0x4b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa6, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa7, 0x5d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa9, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaa, 0x73);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xab, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xac, 0x8e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xad, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xae, 0xae);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaf, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0xc9);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, 0xcd);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb3, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb4, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb5, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb6, 0x20);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb7, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb8, 0x49);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb9, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xba, 0x66);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbb, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbc, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbd, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbe, 0x91);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbf, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0xa3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0xb3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0xc1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0xf1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc9, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0x54);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcb, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcc, 0x85);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, 0xd1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcf, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd0, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd1, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd2, 0x0e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd4, 0x43);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd5, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0xa2);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xda, 0xd7);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdb, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdc, 0xf8);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdd, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xde, 0x2b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdf, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe0, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe1, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe2, 0x4b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe3, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe4, 0x5d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe5, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe6, 0x73);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe7, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe8, 0x8e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe9, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xea, 0xae);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xeb, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec, 0xc9);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xed, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xee, 0xcd);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xef, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf1, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf2, 0x20);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf3, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf4, 0x49);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf5, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf6, 0x66);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf7, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf8, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf9, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfa, 0x91);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x00, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x01, 0xa3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x02, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x03, 0xb3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x04, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x05, 0xc1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x06, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x07, 0xf1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x08, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x09, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0a, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0b, 0x54);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0c, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0d, 0x85);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0e, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x0f, 0xd1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x10, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x11, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x12, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x13, 0x0e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x14, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x15, 0x43);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x16, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x17, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x18, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x19, 0xa2);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1a, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1b, 0xd7);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1c, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1d, 0xf8);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1e, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x1f, 0x2b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x20, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x21, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x22, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x23, 0x4b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x24, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x25, 0x5d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x26, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x27, 0x73);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x28, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x29, 0x8e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x2a, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x2b, 0xae);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x2d, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x2f, 0xc9);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x30, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x31, 0xcd);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x32, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x33, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x34, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x35, 0x20);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x36, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x37, 0x49);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x38, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x39, 0x66);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x3a, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x3b, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x3d, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x3f, 0x91);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x40, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x41, 0xa3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x42, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x43, 0xb3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x44, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x45, 0xc1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x46, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x47, 0xf1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x48, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x49, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x4a, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x4b, 0x54);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x4c, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x4d, 0x85);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x4e, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x4f, 0xd1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x50, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x51, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x52, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x53, 0x0e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x54, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x55, 0x43);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x56, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x58, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x59, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5a, 0xa2);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5b, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5c, 0xd7);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5d, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5e, 0xf8);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x5f, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x60, 0x2b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x61, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x62, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x63, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x64, 0x4b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x65, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x66, 0x5d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x67, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x68, 0x73);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x69, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6a, 0x8e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6b, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6c, 0xae);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6d, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6e, 0xc9);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x70, 0xcd);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x71, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x72, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x73, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x74, 0x20);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x75, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x76, 0x49);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x77, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x78, 0x66);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x79, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7a, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7b, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7c, 0x91);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7d, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7e, 0xa3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x7f, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x80, 0xb3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x81, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x82, 0xc1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x83, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x84, 0xf1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x85, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x86, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x87, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x88, 0x54);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x89, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8a, 0x85);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8b, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8c, 0xd1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8d, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8e, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x8f, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x90, 0x0e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x91, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x92, 0x43);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x93, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x94, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x95, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x96, 0xa2);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x97, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x98, 0xd7);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x99, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9a, 0xf8);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9b, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9c, 0x2b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9d, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9e, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9f, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa0, 0x4b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa2, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa3, 0x5d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa4, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa5, 0x73);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa6, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa7, 0x8e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xa9, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaa, 0xae);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xab, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xac, 0xc9);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xad, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xae, 0xcd);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xaf, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, 0x20);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb3, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb4, 0x49);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb5, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb6, 0x66);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb7, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb8, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb9, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xba, 0x91);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbb, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbc, 0xa3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbd, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbe, 0xb3);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbf, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc0, 0xc1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc1, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc2, 0xf1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc3, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc4, 0x18);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0x54);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0x85);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc9, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xca, 0xd1);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcb, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcc, 0x0c);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcd, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xce, 0x0e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xcf, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd0, 0x43);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd1, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd2, 0x7d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd4, 0xa2);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd5, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0xd7);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0x02);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd8, 0xf8);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xda, 0x2b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdb, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdc, 0x3a);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdd, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xde, 0x4b);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xdf, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe0, 0x5d);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe1, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe2, 0x73);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe3, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe4, 0x8e);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe5, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe6, 0xae);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe7, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe8, 0xc9);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xe9, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xea, 0xcd);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0xee);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x02, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x40, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x02, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x41, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x02, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x42, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xfb, 0x01);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xba, 0x03);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x35, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x36, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd3, 0x10);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd4, 0x0f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd5, 0x0f);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0x48);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd7, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0x00);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
+ mipi_dsi_msleep(&dsi_ctx, 120);
+ mipi_dsi_generic_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_DISPLAY_ON, 0x00);
+ mipi_dsi_msleep(&dsi_ctx, 50);
+
+ return dsi_ctx.accum_err;
+}
+
+static int nt35532_off(struct novatek_nt35532 *ctx)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
+
+ mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
+ mipi_dsi_msleep(&dsi_ctx, 50);
+ mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
+ mipi_dsi_msleep(&dsi_ctx, 120);
+
+ return dsi_ctx.accum_err;
+}
+
+static int nt35532_prepare(struct drm_panel *panel)
+{
+ struct novatek_nt35532 *ctx = to_novatek_nt35532(panel);
+ struct device *dev = &ctx->dsi->dev;
+ int ret;
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(nt35532_supplies), ctx->supplies);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable regulators: %d\n", ret);
+ return ret;
+ }
+
+ nt35532_reset(ctx);
+
+ ret = ctx->desc->on(ctx);
+ if (ret < 0) {
+ dev_err(dev, "Failed to initialize panel: %d\n", ret);
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ regulator_bulk_disable(ARRAY_SIZE(nt35532_supplies), ctx->supplies);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int nt35532_unprepare(struct drm_panel *panel)
+{
+ struct novatek_nt35532 *ctx = to_novatek_nt35532(panel);
+ struct device *dev = &ctx->dsi->dev;
+ int ret;
+
+ ret = nt35532_off(ctx);
+ if (ret < 0)
+ dev_err(dev, "Failed to un-initialize panel: %d\n", ret);
+
+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+ regulator_bulk_disable(ARRAY_SIZE(nt35532_supplies), ctx->supplies);
+
+ return 0;
+}
+
+static const struct drm_display_mode rimob_panel_mode = {
+ .clock = (1080 + 100 + 6 + 94) * (1920 + 15 + 6 + 10) * 60 / 1000,
+ .hdisplay = 1080,
+ .hsync_start = 1080 + 100,
+ .hsync_end = 1080 + 100 + 6,
+ .htotal = 1080 + 100 + 6 + 94,
+ .vdisplay = 1920,
+ .vsync_start = 1920 + 15,
+ .vsync_end = 1920 + 15 + 6,
+ .vtotal = 1920 + 15 + 6 + 10,
+ .width_mm = 68,
+ .height_mm = 121,
+ .type = DRM_MODE_TYPE_DRIVER,
+};
+
+static int nt35532_get_modes(struct drm_panel *panel,
+ struct drm_connector *connector)
+{
+ struct novatek_nt35532 *ctx = to_novatek_nt35532(panel);
+ const struct drm_display_mode *mode = ctx->desc->mode;
+
+ return drm_connector_helper_get_modes_fixed(connector, mode);
+}
+
+static const struct nt35532_panel_desc rimob_panel_desc = {
+ .mode = &rimob_panel_mode,
+ .on = rimob_panel_on,
+};
+
+static const struct drm_panel_funcs novatek_nt35532_panel_funcs = {
+ .prepare = nt35532_prepare,
+ .unprepare = nt35532_unprepare,
+ .get_modes = nt35532_get_modes,
+};
+
+static int nt35532_probe(struct mipi_dsi_device *dsi)
+{
+ struct device *dev = &dsi->dev;
+ struct novatek_nt35532 *ctx;
+ int ret;
+
+ ctx = devm_drm_panel_alloc(dev, struct novatek_nt35532, panel,
+ &novatek_nt35532_panel_funcs,
+ DRM_MODE_CONNECTOR_DSI);
+ if (IS_ERR(ctx))
+ return PTR_ERR(ctx);
+
+ ctx->desc = device_get_match_data(dev);
+
+ ret = devm_regulator_bulk_get_const(dev,
+ ARRAY_SIZE(nt35532_supplies),
+ nt35532_supplies,
+ &ctx->supplies);
+ if (ret < 0)
+ return ret;
+
+ ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(ctx->reset_gpio))
+ return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
+ "Failed to get reset-gpios\n");
+
+ ctx->dsi = dsi;
+ mipi_dsi_set_drvdata(dsi, ctx);
+
+ dsi->lanes = 4;
+ dsi->format = MIPI_DSI_FMT_RGB888;
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+ MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_LPM;
+
+ ctx->panel.prepare_prev_first = true;
+
+ ret = drm_panel_of_backlight(&ctx->panel);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to get backlight\n");
+
+ drm_panel_add(&ctx->panel);
+
+ ret = mipi_dsi_attach(dsi);
+ if (ret < 0) {
+ drm_panel_remove(&ctx->panel);
+ return dev_err_probe(dev, ret, "Failed to attach to DSI host\n");
+ }
+
+ return 0;
+}
+
+static void nt35532_remove(struct mipi_dsi_device *dsi)
+{
+ struct novatek_nt35532 *ctx = mipi_dsi_get_drvdata(dsi);
+ int ret;
+
+ ret = mipi_dsi_detach(dsi);
+ if (ret < 0)
+ dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
+
+ drm_panel_remove(&ctx->panel);
+}
+
+static const struct of_device_id nt35532_of_match[] = {
+ { .compatible = "flipkart,rimob-panel-nt35532-cs", .data = &rimob_panel_desc },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, nt35532_of_match);
+
+static struct mipi_dsi_driver nt35532_driver = {
+ .probe = nt35532_probe,
+ .remove = nt35532_remove,
+ .driver = {
+ .name = "panel-novatek-nt35532",
+ .of_match_table = nt35532_of_match,
+ },
+};
+module_mipi_dsi_driver(nt35532_driver);
+
+MODULE_DESCRIPTION("DRM driver for Novatek NT35532-based 1080p video mode DSI panel");
+MODULE_LICENSE("GPL");
--
2.53.0
^ permalink raw reply related
* [PATCH v4 0/6] Enable new features for flipkart-rimob
From: Cristian Cozzolino via B4 Relay @ 2026-03-27 14:30 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, Cristian Cozzolino,
Konrad Dybcio, Dmitry Baryshkov
This series enables a set of miscellaneous features for Billion Capture+
(a handset using the MSM8953 SoC released in 2017):
- Panel and GPU
- Touchscreen
- WiFi + Bluetooth
- Hall sensor
Patches 1 and 2 provide a driver for Novatek NT35532 and its corresponding
devicetree bindings, required for enabling panel in DTS. The remaining
patches are all DTS changes, aimed to enable the features listed above.
To: Neil Armstrong <neil.armstrong@linaro.org>
To: Jessica Zhang <jesszhan0024@gmail.com>
To: David Airlie <airlied@gmail.com>
To: Simona Vetter <simona@ffwll.ch>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
To: Maxime Ripard <mripard@kernel.org>
To: Thomas Zimmermann <tzimmermann@suse.de>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>
Cc: dri-devel@lists.freedesktop.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-msm@vger.kernel.org
Cc: ~postmarketos/upstreaming@lists.sr.ht
Cc: phone-devel@vger.kernel.org
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
---
Changes in v4:
- (patch 1/6): added a new compatible (since it's not possible to
identify panel vendor/id), matching user of this device and leaving
novatek,nt35532 as fallback (Dmitry);
- (patch 2/6):
- according to bindings changes, make panel driver handling multiple
panels paired with NT35532 and use specific compatible/data;
- due to changes applied to panel code, remove tag received previously
by Dmitry.
- (patch 3/6):
- use a specific panel compatible, according to bindings changes;
- remove 'output-high' property from panel pinctrl, since panel is not
reset.
- Link to v3: https://lore.kernel.org/r/20260321-rimob-new-features-v3-0-d4b8ee867de7@protonmail.com
Changes in v3:
- (patch 1/6): removed avdd, avee and vci supplies from 'required' properties;
- (patch 2/6):
- removed "select VIDEOMODE_HELPERS" from nt35532 Kconfig entry, since
its functions are not used (but this option is enabled and its code
compiled anyway) by nt35532 panel driver;
- pick up tags (Dmitry).
- (patch 3/6): replaced a506_zap.mdt with a506_zap.mbn firmware name
in gpu_zap_shader (Dmitry);
- (patch 5/6): pick up tags (Konrad);
- (patch 6/6): pick up tags (Konrad);
- Link to v2: https://lore.kernel.org/r/20260318-rimob-new-features-v2-0-c1bf8917449e@protonmail.com
Changes in v2:
- (patch 1/6): define power supplies in the bindings as per datasheet
and update example;
- (patch 2/6): add blank lines where required between mipi dsi write
sequences in nt35532_on() function and make use of names for mipi dcs
commands, instead of hex numbers, to improve readibility (Dmitry);
- (patch 3/6): move pinctrl lines ibto panel node and get rid of
sleep/reset state, since panel just uses one pinctrl state for
default/sleep (Dmitry). Also, update power supplies according to
bindings;
- (patch 4/6): pick up tags (Konrad,Dmitry);
- (patch 6/6): squash hall sensor node into gpio-keys (Dmitry);
- Link to v1: https://lore.kernel.org/r/20260308-rimob-new-features-v1-0-aa2c330572c0@protonmail.com
---
Cristian Cozzolino (6):
dt-bindings: display: panel: Add Novatek NT35532 LCD DSI
drm/panel: Add driver for Novatek NT35532
arm64: dts: qcom: msm8953-flipkart-rimob: Enable display and GPU
arm64: dts: qcom: msm8953-flipkart-rimob: Enable WiFi/Bluetooth
arm64: dts: qcom: msm8953-flipkart-rimob: Enable touchscreen
arm64: dts: qcom: msm8953-flipkart-rimob: Enable Hall sensor
.../bindings/display/panel/novatek,nt35532.yaml | 80 +++
MAINTAINERS | 6 +
.../arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts | 138 +++-
drivers/gpu/drm/panel/Kconfig | 10 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-novatek-nt35532.c | 796 +++++++++++++++++++++
6 files changed, 1030 insertions(+), 1 deletion(-)
---
base-commit: e77a5a5cfe43b4c25bd44a3818e487033287517f
change-id: 20260303-rimob-new-features-037944b3a620
Best regards,
--
Cristian Cozzolino <cristian_ci@protonmail.com>
^ permalink raw reply
* [PATCH v4 3/6] arm64: dts: qcom: msm8953-flipkart-rimob: Enable display and GPU
From: Cristian Cozzolino via B4 Relay @ 2026-03-27 14:30 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, Cristian Cozzolino
In-Reply-To: <20260327-rimob-new-features-v4-0-06edff9c4509@protonmail.com>
From: Cristian Cozzolino <cristian_ci@protonmail.com>
Add the description for the display panel found on this phone.
And with this done we can also enable the GPU and set the zap shader
firmware path.
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
---
.../arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts | 73 ++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
index ef4faf763132..8b72b71f4d4b 100644
--- a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
+++ b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
@@ -78,6 +78,13 @@ vph_pwr: vph-pwr-regulator {
};
};
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/msm8953/flipkart/rimob/a506_zap.mbn";
+};
&hsusb_phy {
vdd-supply = <&pm8953_l3>;
@@ -87,11 +94,70 @@ &hsusb_phy {
status = "okay";
};
+&ibb {
+ qcom,discharge-resistor-kohms = <32>;
+};
+
+&lab {
+ qcom,soft-start-us = <800>;
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&pm8953_s3>;
+ vddio-supply = <&pm8953_l6>;
+
+ status = "okay";
+
+ panel: panel@0 {
+ compatible = "flipkart,rimob-panel-nt35532-cs";
+ reg = <0>;
+
+ backlight = <&pmi8950_wled>;
+ reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
+ avdd-supply = <&lab>;
+ avee-supply = <&ibb>;
+ vci-supply = <&pm8953_l17>;
+ vddi-supply = <&pm8953_l6>;
+
+ pinctrl-0 = <&panel_default>;
+ pinctrl-names = "default";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ data-lanes = <0 1 2 3>;
+ remote-endpoint = <&panel_in>;
+};
+
+&mdss_dsi0_phy {
+ vcca-supply = <&pm8953_l3>;
+
+ status = "okay";
+};
+
&pm8953_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
+&pmi8950_wled {
+ qcom,current-limit-microamp = <10000>;
+ qcom,num-strings = <3>;
+ qcom,ovp-millivolt = <29500>;
+
+ status = "okay";
+};
+
&rpm_requests {
regulators {
compatible = "qcom,rpm-pm8953-regulators";
@@ -244,6 +310,13 @@ gpio_key_default: gpio-key-default-state {
drive-strength = <2>;
bias-pull-up;
};
+
+ panel_default: panel-default-state {
+ pins = "gpio61";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
};
&usb3 {
--
2.53.0
^ permalink raw reply related
* [PATCH v4 4/6] arm64: dts: qcom: msm8953-flipkart-rimob: Enable WiFi/Bluetooth
From: Cristian Cozzolino via B4 Relay @ 2026-03-27 14:30 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, Cristian Cozzolino,
Konrad Dybcio, Dmitry Baryshkov
In-Reply-To: <20260327-rimob-new-features-v4-0-06edff9c4509@protonmail.com>
From: Cristian Cozzolino <cristian_ci@protonmail.com>
Configure and enable the WCNSS which provides WiFi and Bluetooth on this
device using the WCN3660B chip.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
---
arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
index 8b72b71f4d4b..8620143e04a0 100644
--- a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
+++ b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
@@ -326,3 +326,18 @@ &usb3 {
&usb3_dwc3 {
dr_mode = "peripheral";
};
+
+&wcnss {
+ vddpx-supply = <&pm8953_l5>;
+
+ status = "okay";
+};
+
+&wcnss_iris {
+ compatible = "qcom,wcn3660b";
+
+ vddxo-supply = <&pm8953_l7>;
+ vddrfa-supply = <&pm8953_l19>;
+ vddpa-supply = <&pm8953_l9>;
+ vdddig-supply = <&pm8953_l5>;
+};
--
2.53.0
^ permalink raw reply related
* [PATCH v4 5/6] arm64: dts: qcom: msm8953-flipkart-rimob: Enable touchscreen
From: Cristian Cozzolino via B4 Relay @ 2026-03-27 14:30 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, Cristian Cozzolino,
Konrad Dybcio
In-Reply-To: <20260327-rimob-new-features-v4-0-06edff9c4509@protonmail.com>
From: Cristian Cozzolino <cristian_ci@protonmail.com>
This device uses a Goodix GT5688 touch controller, connected to i2c_3.
Add it to the device tree.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
---
.../arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts | 32 ++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
index 8620143e04a0..a1280b0e7e90 100644
--- a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
+++ b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
@@ -94,6 +94,31 @@ &hsusb_phy {
status = "okay";
};
+&i2c_3 {
+ status = "okay";
+
+ touchscreen@5d {
+ compatible = "goodix,gt5688";
+ reg = <0x5d>;
+
+ interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&tsp_int_rst_default>;
+ pinctrl-names = "default";
+
+ irq-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
+
+ VDDIO-supply = <&pm8953_l6>;
+ AVDD28-supply = <&pm8953_l10>;
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <1920>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ };
+};
+
&ibb {
qcom,discharge-resistor-kohms = <32>;
};
@@ -317,6 +342,13 @@ panel_default: panel-default-state {
drive-strength = <8>;
bias-disable;
};
+
+ tsp_int_rst_default: tsp-int-rst-default-state {
+ pins = "gpio64", "gpio65";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
};
&usb3 {
--
2.53.0
^ permalink raw reply related
* [PATCH v4 6/6] arm64: dts: qcom: msm8953-flipkart-rimob: Enable Hall sensor
From: Cristian Cozzolino via B4 Relay @ 2026-03-27 14:30 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: dri-devel, devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel, Cristian Cozzolino,
Konrad Dybcio
In-Reply-To: <20260327-rimob-new-features-v4-0-06edff9c4509@protonmail.com>
From: Cristian Cozzolino <cristian_ci@protonmail.com>
Enable the Hall effect sensor (flip cover) for Billion Capture+.
The GPIO is mapped to SW_LID events as in other qcom devices.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Cristian Cozzolino <cristian_ci@protonmail.com>
---
arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
index a1280b0e7e90..8e3874740cf9 100644
--- a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
+++ b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts
@@ -47,9 +47,18 @@ framebuffer@90001000 {
gpio-keys {
compatible = "gpio-keys";
- pinctrl-0 = <&gpio_key_default>;
+ pinctrl-0 = <&gpio_hall_sensor_default>, <&gpio_key_default>;
pinctrl-names = "default";
+ event-hall-sensor {
+ label = "Hall Effect Sensor";
+ gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ linux,can-disable;
+ wakeup-source;
+ };
+
key-volume-up {
label = "Volume Up";
gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
@@ -329,6 +338,13 @@ &sdhc_2 {
&tlmm {
gpio-reserved-ranges = <0 4>, <135 4>;
+ gpio_hall_sensor_default: gpio-hall-sensor-default-state {
+ pins = "gpio46";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
gpio_key_default: gpio-key-default-state {
pins = "gpio85";
function = "gpio";
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v4 1/2] dt-bindings: embedded-controller: Add synology,microp device
From: Markus Probst @ 2026-03-27 13:34 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozlowski, Krzysztof Kozlowski, Conor Dooley,
Miguel Ojeda, Boqun Feng, Gary Guo, Björn Roy Baron,
Benno Lossin, Andreas Hindborg, Alice Ryhl, Trevor Gross,
Danilo Krummrich, Greg Kroah-Hartman, devicetree, linux-kernel,
rust-for-linux
In-Reply-To: <CAL_JsqJUVh1YnhmYYj4ara5BheaLOL1oayjtWNuPH53q1d4xXA@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 4761 bytes --]
On Thu, 2026-03-26 at 14:36 -0500, Rob Herring wrote:
> On Thu, Mar 26, 2026 at 8:02 AM Markus Probst <markus.probst@posteo.de> wrote:
> >
> > On Wed, 2026-03-25 at 17:07 -0500, Rob Herring wrote:
> > > On Sat, Mar 21, 2026 at 01:02:22PM +0000, Markus Probst wrote:
> > > > On Sat, 2026-03-21 at 13:32 +0100, Krzysztof Kozlowski wrote:
> > > > > On 21/03/2026 13:17, Markus Probst wrote:
> > > > > > On Sat, 2026-03-21 at 11:21 +0100, Krzysztof Kozlowski wrote:
> > > > > > > On Fri, Mar 20, 2026 at 11:09:53PM +0100, Markus Probst wrote:
> > > > > > > > +
> > > > > > > > +examples:
> > > > > > > > + - |
> > > > > > > > + #include <dt-bindings/leds/common.h>
> > > > > > > > +
> > > > > > > > + embedded-controller {
> > > > > > > > + compatible = "synology,microp";
> > > > > > > > +
> > > > > > > > + power-led {
> > > > > > > > + color = <LED_COLOR_ID_BLUE>;
> > > > > > > > + function = LED_FUNCTION_POWER;
> > > > > > > > + };
> > > > > > > > +
> > > > > > > > + status-led {
> > > > > > > > + color = <LED_COLOR_ID_MULTI>;
> > > > > > > > + function = LED_FUNCTION_STATUS;
> > > > > > > > + };
> > > > > > >
> > > > > > > Where are other leds? Binding mentions 4.
> > > > > > >
> > > > > > Status and Power leds exist on every Synology NAS model I am aware of.
> > > > > > But there are models which have additionally a usb or alert led. The
> > > > > > device nodes for those leds should only be present, if they exist
> > > > > > physically on the device.
> > > > >
> > > > > Then help me to understand - are these different models?
> > > > Yes, even with different CPU architectures.
> > > > How much the "microp" device differs is not clear, but the
> > > > communication protocol is the same.
> > > > >
> > > > > EC is not a generic purpose component and is tightly coupled with the
> > > > > actual board it is being present on. Unless exactly same board is used
> > > > > in different models (unlikely) then the compatible defines the LEDs and
> > > > > they are not needed in DT.
> > > > So for instance "synology,ds923p-microp", "synology,ds723p-microp" etc.
> > > > ?
> > > >
> > > > I can do that, but that would be many.
> > >
> > > How many is many?
> > Estimated 300.
>
> Okay, that's a lot and probably safe to say there are not 300
> variations of the EC.
>
> > As a side note: I only have 1 model I can test the driver with.
> > >
> > > > Having it generic seems more flexible.
> > >
> > > Is there firmware for these ECs? If so is it the same or different
> > > firmware for each device? If the former or the functionality is really
> > > trivial, then I'd be more comfortable with 1 or a few compatibles.
> > The firmware is not public and the exact differences between them isn't
> > documented. The communication protocol is the same though.
> >
> > >
> > > Generic means you'll need to add quirk properties when there is some
> > > difference the OS needs to handle which we'll reject. So stuck with one
> > > compatible and no way to distinguish different ECs is anything but
> > > flexible.
> > Describing the physical leds that are present on the NAS device are not
> > quirk properties, at least in my definition.
>
> That's not what I mean. I mean things like this other device needs
> some different timing for power-on/reset or delays between accesses or
> some LED control is inverted or some protocol difference... Could be
> about anything. The key thing is you have specific enough information
> (compatible) to start with that you can handle any issue that comes up
> *without* changing the DT.
>
> As you said, you only have 1 device. Make the binding specific to that
> 1 device. If the next one that comes along can reuse the binding as
> it, then great. Nothing to do. If it can't, then it gets its own new
> compatible. Strictly speaking we would add a new compatible for each
> device, but it's a judgement call that there aren't going to be
> differences to handle. In this case, there likely aren't 300 versions
> of h/w, the functionality is simple enough, and the functionality is
> entirely optional (just a guess). But that's all really your argument
> to make.
I think I will go with different compatible, but instead of 1 I will
compile a small list of devices, which:
- are most similar to my testing device
- have unique functionality (like having additionally a "cpu fan" or
similar). This way I can implement every functionality in the driver,
which makes it easier to add devices in the future.
- I know are owned by people who like to experiment with their device
(including my device)
Thanks
- Markus Probst
>
> Rob
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