* Re: [PATCH v2 02/15] firmware: qcom: Add a generic PAS service
From: Sumit Garg @ 2026-03-30 7:08 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Konrad Dybcio, linux-arm-msm, devicetree, dri-devel, freedreno,
linux-media, netdev, linux-wireless, ath12k, linux-remoteproc,
andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, mukesh.ojha, pavan.kondeti,
jorge.ramirez, tonyh, vignesh.viswanathan, srinivas.kandagatla,
amirreza.zarrabi, jens.wiklander, op-tee, apurupa, skare,
linux-kernel, Sumit Garg
In-Reply-To: <a0a7269d-7a09-4a78-a4b0-b39b67bc253b@kernel.org>
On Fri, Mar 27, 2026 at 02:56:40PM +0100, Krzysztof Kozlowski wrote:
> On 23/03/2026 15:26, Konrad Dybcio wrote:
> >>>
> >>> This pattern has been carried from the PAS API contract among kernel
> >>> clients and the SCM PAS service earlier. The clients don't hold a
> >>> reference to the PAS data like underlying platform or TEE device etc.
> >>> Hence the need to have a global data pointer to hold reference to the
> >>> ops data structure registered by drivers having different lifetime of
> >>> devices. Also, the PAS APIs can be called from very different client
> >>> driver contexts.
> >>>
> >>> Surely, avoiding global data is always better given a better alternative
> >>> is there. Do you have any better alternative proposal here?
> >>
> >> Why it cannot be part of the context?
> >>
> >> Look at your API, e.g.:
> >> qcom_pas_init_image(). It takes struct qcom_pas_context which should
> >> contain the ops.
Have a look at all other PAS client APIs, the context isn't something
that each client takes a reference and pass it on for every PAS
invocation. And changing the PAS API contract for kernel clients is out
of scope of this patch-set.
> >
> > This would make the client have to select the ops. The whole point is to
> > avoid that, since the client has no clue (and is supposed not to have any).
>
> Yeah, I see. The problem is that this patchset just keeps growing the
> singletons so except existing 'struct qcom_scm *__scm' in qcom_scm.c,
> this one brings at least three new: 'ops_ptr', 'qcom_pas_ops_scm' and
> 'qcom_pas_ops_tee'.
Not sure how you equate ops structure __pointer__ to the ops structure
itself. Can you enlighten me how in the rest of the kernel ops data
structures are shared among independent modules registering on different
bus types?
>
> I don't think you need all four in total, but only one which will hold
> whatever pointers are necessary.
Your arguments seems to be in favour of the existing monolithic SCM
driver design but you need to understand that's not how underlying TZ
services are implemented. The PAS service in TZ has nothing to do with
the ICE service for inline crypto as an example.
Please go through the motivation of this patch-set and the corresponding
OP-TEE implementation as TZ which is all open source.
-Sumit
^ permalink raw reply
* Re: [PATCH v9 0/2] media: add Himax HM1246 image sensor
From: Matthias Fend @ 2026-03-30 7:07 UTC (permalink / raw)
To: Matthias Fend, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Hans Verkuil, Sakari Ailus,
Hans de Goede, Ricardo Ribalda, André Apitzsch, Tarang Raval,
Andy Shevchenko, Benjamin Mugnier, Sylvain Petinot, Dongcheng Yan,
Bryan O'Donoghue, Alan Stern, Jingjing Xiong,
Heimir Thor Sverrisson, Mehdi Djait, Vladimir Zapolskiy,
Laurent Pinchart, Hardevsinh Palaniya, Svyatoslav Ryhel,
Philipp Zabel
Cc: linux-media, devicetree, linux-kernel, Hao Yao, Himanshu Bhavani
In-Reply-To: <20260128-hm1246-v9-0-f9c996486a95@emfend.at>
Hi Sakari,
I wanted to ask if, from your perspective, there are any things left
here that you would like to see changed?
Thanks
~Matthias
Am 28.01.2026 um 17:08 schrieb Matthias Fend:
> Hello,
>
> this series adds support for the Himax HM1246 image sensor.
> The Himax HM1246-AWD is a 1/3.7-Inch CMOS image sensor SoC with an active
> array size of 1296 x 976.
> Currently, only the native RAW mode is supported. Other modes and the
> internal image signal processing pipeline are not currently supported.
> The data sheet is available on the manufacturer's website [1].
> Tested on i.MX8MP hardware. A Toshiba TC358746 bridge was used to convert
> the sensor's parallel video output into MIPI signals for the i.MX8MP.
>
> Best regards
> ~Matthias
>
> [1] https://www.himax.com.tw/wp-content/uploads/2024/03/HM1246-AWD_DS_v01.pdf
>
> v4l2-compliance 1.28.1, 64 bits, 64-bit time_t
>
> Compliance test for device /dev/v4l-subdev4:
>
> Driver Info:
> Driver version : 6.12.0
> Capabilities : 0x00000000
> Client Capabilities: 0x0000000000000003
> streams interval-uses-which
> Required ioctls:
> test VIDIOC_SUDBEV_QUERYCAP: OK
> test invalid ioctls: OK
>
> Allow for multiple opens:
> test second /dev/v4l-subdev4 open: OK
> test VIDIOC_SUBDEV_QUERYCAP: OK
> test for unlimited opens: OK
>
> Debug ioctls:
> test VIDIOC_LOG_STATUS: OK (Not Supported)
>
> Input ioctls:
> test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> test VIDIOC_ENUMAUDIO: OK (Not Supported)
> test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDIO: OK (Not Supported)
> Inputs: 0 Audio Inputs: 0 Tuners: 0
>
> Output ioctls:
> test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> Outputs: 0 Audio Outputs: 0 Modulators: 0
>
> Input/Output configuration ioctls:
> test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> test VIDIOC_G/S_EDID: OK (Not Supported)
>
> Control ioctls:
> test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> test VIDIOC_QUERYCTRL: OK
> test VIDIOC_G/S_CTRL: OK
> test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> Standard Controls: 15 Private Controls: 0
>
> Format ioctls:
> test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK (Not Supported)
> test VIDIOC_G/S_PARM: OK (Not Supported)
> test VIDIOC_G_FBUF: OK (Not Supported)
> test VIDIOC_G_FMT: OK (Not Supported)
> test VIDIOC_TRY_FMT: OK (Not Supported)
> test VIDIOC_S_FMT: OK (Not Supported)
> test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> test Cropping: OK (Not Supported)
> test Composing: OK (Not Supported)
> test Scaling: OK (Not Supported)
>
> Codec ioctls:
> test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
> test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
>
> Buffer ioctls:
> test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK (Not Supported)
> test CREATE_BUFS maximum buffers: OK
> test VIDIOC_REMOVE_BUFS: OK
> test VIDIOC_EXPBUF: OK (Not Supported)
> test Requests: OK (Not Supported)
>
> Total for device /dev/v4l-subdev4: 45, Succeeded: 45, Failed: 0, Warnings: 0
>
> Signed-off-by: Matthias Fend <matthias.fend@emfend.at>
> ---
> Changes in v9:
> - Use v4l2_rect in hm1246_mode
> - Return in default case of hm1246_get_selection()
> - Convert gpio based reset handling to use generic reset controller
> - Link to v8: https://lore.kernel.org/r/20260113-hm1246-v8-0-ea93947b192e@emfend.at
>
> Changes in v8:
> - Adjusted copyright year (Sakari)
> - Use local var for unreferenced v4l2 controls (Sakari)
> - Return NULL instead of PTR_ERR if hm1246_find_mode_by_mbus_code() fails (Sakari)
> - Removed unnecessary parentheses (Sakari)
> - Dropped git reference in MAINTAINER entry (Sakari)
> - Added default for bus-width in bindings (Sakari)
> - Link to v7: https://lore.kernel.org/r/20260112-hm1246-v7-0-fee8587f2808@emfend.at
>
> Changes in v7:
> - Expect the PLL to generate the exact link frequency specified in DT (Laurent, Sakari)
> - Dropped {g,s}_register functions
> - Link to v6: https://lore.kernel.org/r/20251202-hm1246-v6-0-3e96ed6b3ffa@emfend.at
>
> Changes in v6:
> - Rework includes to follow include-what-you-use (Andy)
> - Replace 'fsleep(6000)' with 'fsleep(6 * USEC_PER_MSEC)' (Andy)
> - Simplify hm1246_get_selection() return (Andy)
> - Use explicit indexes for test pattern array (Andy)
> - Improve some line-wrappings (Andy)
> - Avoid using __maybe_unused (Andy)
> - Drop an unnecessary type cast (Andy)
> - Use '0' instead of '0x0' (Andy)
> - Reword comments about timings (Andy)
> - Simplify error handling of hm1246_init_controls() (Sakari)
> - Revert 'rework PLL calc to use goto' (Andy, Sakari)
> - Link to v5: https://lore.kernel.org/r/20251104-hm1246-v5-0-97c8f25b5419@emfend.at
>
> Changes in v5:
> - Converted to lower case hexadecimals
> - Use consistent returns in switch of hm1246_get_selection()
> - Adjust some variable types/attributes
> - Removed redundant parentheses
> - Rework PLL calc to use goto
> - Simplified some function returns
> - Use array definition for test patterns
> - Source format adjustments
> - Properly init minimum of pixel_rate control
> - dropped hm1246_update_controls()
> - require and check DT link frequencies
> - Link to v4: https://lore.kernel.org/r/20251017-hm1246-v4-0-e3388ea2f08c@emfend.at
>
> Changes in v4:
> - Split changes to MAINTAINERS into commits
> - Fix comma after statement (use semicolon)
> - Replace abs() with abs_diff() in PLL calculation
> - Inverse needs_cmu_update logic
> - Drop mode from hm1246_set_ctrl()
> - Return if xclk frequency is out of range
> - Fix reset_gpio dev_err_probe()
> - Rebased on media-committers/next
> - Link to v3: https://lore.kernel.org/r/20250912-hm1246-v3-0-3b89f47dfa43@emfend.at
>
> Changes in v3:
> - Bindings: Remove bus-type and add default polarity values
> - Select V4L2_CCI_I2C
> - Convert additional macros to use HZ_PER_*
> - Replace cur_mode with v4l2_find_nearest_size()
> - Remove duplicates in the register init sequence
> - Use container_of_const
> - Check return of hm1246_update_controls()
> - Correct multi-line comments
> - Replace hm1246_cci_write_cmu()
> - Consistently use hm1246->dev
> - Use pm_runtime_put_autosuspend()
> - Remove v4l2 event handling
> - Convert to devm_v4l2_sensor_clk_get()
> - Configure PM before registering subdev
> - Link to v2: https://lore.kernel.org/r/20250526-hm1246-v2-0-6b882827a3a5@emfend.at
> - Depends-on: https://lore.kernel.org/all/20250707143253.167910-1-mehdi.djait@linux.intel.com/
>
> Changes in v2:
> - Use macros for 64-bit division
> - Avoid compiler warnings about potentially uninitialized variables
> - Fix two uses of dev_err_probe
> - Link to v1: https://lore.kernel.org/r/20250403-hm1246-v1-0-30990d71bc42@emfend.at
>
> ---
> Matthias Fend (2):
> media: dt-bindings: i2c: add Himax HM1246 image sensor
> media: i2c: add Himax HM1246 image sensor driver
>
> .../bindings/media/i2c/himax,hm1246.yaml | 120 ++
> MAINTAINERS | 7 +
> drivers/media/i2c/Kconfig | 10 +
> drivers/media/i2c/Makefile | 1 +
> drivers/media/i2c/hm1246.c | 1290 ++++++++++++++++++++
> 5 files changed, 1428 insertions(+)
> ---
> base-commit: 3aa9296a23ec41a8424e9a2346eea59fb6cb7d8c
> change-id: 20250403-hm1246-96b0cdab773c
>
> Best regards,
^ permalink raw reply
* Re: [PATCH v3 2/2] ARM: dts: st: spear: remove undocumented thermal_flags property
From: Krzysztof Kozlowski @ 2026-03-30 7:06 UTC (permalink / raw)
To: Gopi Krishna Menon
Cc: rafael, daniel.lezcano, rui.zhang, lukasz.luba, robh, krzk+dt,
vireshk, conor+dt, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, soc, daniel.baluta, simona.toaca, d-gole,
m-chawdhry
In-Reply-To: <20260329123449.309814-3-krishnagopi487@gmail.com>
On Sun, Mar 29, 2026 at 06:04:44PM +0530, Gopi Krishna Menon wrote:
> spear13xx.dtsi defines a thermal_flags property in spear thermal sensor
> node which is both unused in kernel and undocumented in spear thermal
> sensor's binding.
>
> There were no dtbs_check warnings associated with this property as the
> underlying spear thermal binding was not converted to DTSchema.
>
> Most likely st,thermal-flags is a misspelling of thermal_flags in
> spear13xx.dtsi. Since both st/spear1310.dtsi and st/spear1340.dtsi
> define st,thermal-flags property in spear thermal sensor node, we can
> safely remove this property from spear13xx.dtsi.
>
> Signed-off-by: Gopi Krishna Menon <krishnagopi487@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [RFC uL PATCH 2/2] mux-controller: ti: add driver for event mux router
From: Greg KH @ 2026-03-30 7:03 UTC (permalink / raw)
To: rahul sharma
Cc: peda, robh, krzk+dt, conor+dt, devicetree, vigneshr, linux-kernel
In-Reply-To: <5ba0d92e-7f2f-423a-8d1c-561c350c1db3@ti.com>
On Mon, Mar 30, 2026 at 11:02:11AM +0530, rahul sharma wrote:
> CC: Greg Kroah-Hartman
>
> Hi Greg,
>
> Could you please review this patch(2nd one in the series). It seems Peter is
> not online for almost a month.
But I am not the mux maintainer, so I am probably not the best one to
review it :(
One instant comment though:
> On 13/03/26 11:34, Rahul Sharma wrote:
> > The driver supports event muxing routers like gpio mux router and timesync
> > router. This driver is adaptation of original reg-mux driver, along with
> > changes specific to support TI's mux router.
> >
> > The idle states this driver supports are only 2 which active(represented
> > by 1 in dt-node) and in-active(represented by 0 in dt-node).
> >
> > Signed-off-by: Rahul Sharma <r-sharma3@ti.com>
> > ---
> > drivers/mux/Kconfig | 15 +++
> > drivers/mux/Makefile | 2 +
> > drivers/mux/ti-k3-event-mux.c | 235 ++++++++++++++++++++++++++++++++++
> > 3 files changed, 252 insertions(+)
> > create mode 100644 drivers/mux/ti-k3-event-mux.c
> >
> > diff --git a/drivers/mux/Kconfig b/drivers/mux/Kconfig
> > index c68132e38138..ad3af2724d28 100644
> > --- a/drivers/mux/Kconfig
> > +++ b/drivers/mux/Kconfig
> > @@ -59,4 +59,19 @@ config MUX_MMIO
> > To compile the driver as a module, choose M here: the module will
> > be called mux-mmio.
> > +config MUX_TI_K3_EVENT_ROUTER
> > + tristate "TI Event Mux Router using MMIO registers"
> > + depends on OF && (REGMAP_MMIO || COMPILE_TEST)
> > + help
> > + This is extension of MMIO mux for timesync router and gpiomux
> > + routers on TI K3 SoCs. This driver supports the 3-field format for
> > + mux control: <register-offset mask value>.
> > +
> > + The driver allows configuration of hardware mux routers using
> > + memory-mapped registers. It's based on the mmio-mux driver but
> > + supports the extended 3-field format for more precise control.
> > +
> > + To compile the driver as a module, choose M here: the module will
> > + be called mux-ti-k3-event.
> > +
Don't you need a blank line before your new config option?
thanks,
greg k-h
^ permalink raw reply
* Re: [PATCH v5 3/4] rust: add visibility to of_device_table macro
From: Krzysztof Kozlowski @ 2026-03-30 7:02 UTC (permalink / raw)
To: Markus Probst
Cc: Hans de Goede, Ilpo Järvinen, Bryan O'Donoghue,
Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Miguel Ojeda, Boqun Feng, Gary Guo,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Trevor Gross, Danilo Krummrich, Greg Kroah-Hartman,
Rafael J. Wysocki, Len Brown, Saravana Kannan,
platform-driver-x86, linux-leds, devicetree, linux-kernel,
rust-for-linux, linux-acpi
In-Reply-To: <20260329-synology_microp_initial-v5-3-27cb80bdf591@posteo.de>
On Sun, Mar 29, 2026 at 08:02:17PM +0200, Markus Probst wrote:
> Add visibility argument to macro to allow defining an of device table in
> a different module than the driver, which can improve readability.
No. The of_device_id table must be always placed next to the foo_driver.
You keep introducing completely inconsisting styles in this patchset,
like completely broken usage of compatibles in the driver.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v9 00/21] media: i2c: add Maxim GMSL2/3 serializer and deserializer drivers
From: Ceclan Dumitru @ 2026-03-30 7:54 UTC (permalink / raw)
To: Dayananda, Vivekananda, dumitru.ceclan@analog.com, Tomi Valkeinen,
Mauro Carvalho Chehab, Sakari Ailus, Laurent Pinchart,
Julien Massot, Rob Herring, Niklas Söderlund,
Greg Kroah-Hartman, Cosmin Tanislav
Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-staging@lists.linux.dev,
linux-gpio@vger.kernel.org, Niklas Söderlund,
martin.hecht@avnet.eu, Tomi Valkeinen, Cosmin Tanislav,
Cory Keitz
In-Reply-To: <MW4PR12MB566835A0D88DAA21D6642832E856A@MW4PR12MB5668.namprd12.prod.outlook.com>
On 3/26/26 7:00 PM, Dayananda, Vivekananda wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Hi Dumitru, Sakari,
>
> Thank you for the latest patch series. We have been validating this
> on the following test infrastructure:
>
> - IMX219 image sensor
> - MAX96724 deserializer
> - MAX96717 serializer
>
> With this setup the v9 drivers operate as expected and we are able to
> exercise streaming end-to-end.
>
> One item worth noting: our deserializer sits on a custom daughter card
> where the I2C bus is routed through port 1. The current MAX96724 driver
> only supports I2C on port 0. It would be valuable to extend the driver
> to support additional I2C port configurations so that setups like ours
> can be accommodated.
>
> Vivek
Hi Vivek,
I have found the EZ thread where the I2C port1 issue was raised and
resolved. Would the inclusion of those 2 commits from Cosmin suffice
or were there more changes required for your setup to work?
>> -----Original Message-----
>> From: Dumitru Ceclan via B4 Relay
>> <devnull+dumitru.ceclan.analog.com@kernel.org>
>> Sent: Wednesday, March 11, 2026 12:17 AM
>> To: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>; Mauro
>> Carvalho Chehab <mchehab@kernel.org>; Sakari Ailus
>> <sakari.ailus@linux.intel.com>; Laurent Pinchart
>> <laurent.pinchart@ideasonboard.com>; Julien Massot
>> <julien.massot@collabora.com>; Rob Herring <robh@kernel.org>; Niklas
>> Söderlund <niklas.soderlund@ragnatech.se>; Greg Kroah-Hartman
>> <gregkh@linuxfoundation.org>; Cosmin Tanislav <cosmin.tanislav@analog.com>
>> Cc: mitrutzceclan@gmail.com; linux-media@vger.kernel.org; linux-
>> kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-
>> staging@lists.linux.dev; linux-gpio@vger.kernel.org; Niklas Söderlund
>> <niklas.soderlund+renesas@ragnatech.se>; Martin Hecht
>> <Martin.Hecht@avnet.eu>; Tomi Valkeinen
>> <tomi.valkeinen@ideasonboard.com>; Cosmin Tanislav
>> <demonsingur@gmail.com>; Cory Keitz <ckeitz@amazon.com>
>> Subject: [PATCH v9 00/21] media: i2c: add Maxim GMSL2/3 serializer and
>> deserializer drivers
>>
>> This series adds new drivers for multiple Maxim GMSL2 and GMSL3 devices,
>> replacing the few GMSL2 drivers already in upstream, and introducing a common
>> framework that can be used to implement such GMSL chips, which avoids code
>> duplication while also adding support for previously unsupported features.
>>
>> While the normally acceptable and polite way would be to extend the current
>> mainline drivers, the choice was made here to add a totally new set of drivers.
>> The current drivers support only a small subset of the possible features, and only
>> a few devices, so the end result after extending them would in any case be
>> essentially fully rewritten, new drivers.
>>
>> This series depends on support for internal pads, for which a patch has been
>> added.
>>
>> The previous version is at:
>> https://lore.kernel.org/all/20250718152500.2656391-1-
>> demonsingur@gmail.com/
>>
>> Since the previous series, Cosmin has left Analog Devices.
>> Because included changes from previous version are trivial, his sign-off and tags
>> were retained.
>>
>> The following deserializers are supported:
>> * MAX96712 (already exists in staging)
>> * MAX96714 (already exists)
>> * MAX96714F (already exists)
>> * MAX96714R (GMSL2)
>> * MAX96716 (GMSL2)
>> * MAX96724 (already exists as part of existing MAX96712 driver)
>> * MAX96724F (GMSL2)
>> * MAX96724R (GMSL2)
>> * MAX9296A (GMSL2)
>> * MAX96792A (GMSL3)
>>
>> The following serializers are supported:
>> * MAX96717 (already exists)
>> * MAX9295A (GMSL2)
>> * MAX96793 (GMSL3)
>>
>> The following list enumerates new features that are supported by the common
>> framework and their respective chip-specific drivers:
>> * Full Streams API support. Most deserializers have support for more than one
>> link, and more than one PHY. Streams support allows configuration of routing
>> between these links and PHYs.
>>
>> * .get_frame_desc() support. Both the serializers and deserializers implement this
>> to query and provide frame descriptor data. This is used in features explained in-
>> depth below.
>>
>> * .get_mbus_config() support. The deserializers implement this to allow upstream
>> devices to query the link frequency of its pads.
>>
>> * Address translation with I2C ATR for the serializers.
>>
>> * I2C ATR translation - some deserializers cannot do muxing since I2C
>> communication channel masking is not available per-link, and the only other way
>> to select links is to turn them off, causing link resets.
>> For such cases, I2C ATR is used to change the address of the serializers at probe
>> time.
>>
>> * Automatic GMSL link version negotiation between GMSL3, GMSL2 6Gbps,
>> GMSL2 3Gbps.
>>
>> * Automatic stream id selection for deserializers which need serializers to stream
>> on unique stream ids.
>>
>> * Automatic VC remapping on the deserializers. VCs are picked so that if they
>> were unique on the sink pad, they will end up as unique on the source pad they
>> are routed to too, prioritizing using the same VC ID as the sink pad, to facilitate
>> the possibility of using tunnel mode.
>>
>> * Automatic pixel mode / tunnel mode selection. Tunnel mode is used when VC
>> IDs do not need to be changed and all hardware supports tunnel mode,
>> otherwise, pixel mode is used. The serializers are automatically switched
>> between the two by using a private API.
>>
>> * Automatic double mode selection. In pixel mode, double mode can be used to
>> pack two pixels into a single data unit, optimizing bandwidth usage. The
>> serializers are automatically set up to support the double modes determined by
>> the deserializers using a private API.
>>
>> * Automatic data padding. In pixel mode, if the data being transferred uses two
>> different BPPs, data needs to be padded. The serializers automatically set this up
>> depending on the configured double mode settings and incoming data types.
>>
>> * Logging. Both the deserializers and serializers implement the V4L2
>> .log_status() ops to allow debugging of the internal state and important chip
>> status registers.
>>
>> * PHY modes. Deserializer chips commonly have more than a single PHY.
>> The firmware ports are parsed to determine the modes in which to configure the
>> PHYs (2x4, 4x2, 1x4+2x2, 2x2+1x4, and variations using fewer lanes).
>>
>> * Serializer pinctrl. Serializers implement pinctrl to allow setting configs which
>> would otherwise be inaccessible through GPIO: TX/RX via GMSL link, pull-up &
>> pull-down (with strength), open-drain & push-pull, slew rate, RCLK pin selection.
>>
>> * TPG with selectable formats, resolutions and framerates for both serializers and
>> deserializers.
>>
>> The drivers have been tested on the following hardware combinations, but further
>> testing is welcome to ensure no / minimal breakage:
>> * Raspberry Pi 5 + MAX9296A + 2xMAX96717 + 2xIMX219
>> * Raspberry Pi 5 + MAX96714 + 1xMAX96717 + 1xIMX219
>> * Raspberry Pi 5 + MAX96716A + 2xMAX96717 + 2xIMX219
>> * Raspberry Pi 5 + MAX96712 + 4xMAX96717 + 4xIMX219
>> * Raspberry Pi 5 + MAX96724 + 4xMAX96717 + 4xIMX219
>> * Raspberry Pi 5 + MAX96792A + 1xMAX96793 + 1xMAX96717 + 2xIMX219
>> * Raspberry Pi 5 + MAX96792A + 2xMAX96717 + 2xIMX219
>> * Renesas V4H + MAX96712 + 2xMAX96717 + 2xIMX219
>>
>> Analog Devices is taking responsibility for the maintenance of these drivers and
>> common framework, and plans to add support for new broad-market chips on top
>> of them.
>>
>> Special thanks go to Tomi Valkeinen <
>> tomi.valkeinen+renesas@ideasonboard.com>
>> for testing the drivers, helping debug and coming up with ideas / implementations
>> for various features.
>>
>> The following v4l2-compliance test still fails:
>> fail: v4l2-test-subdevs.cpp(371): fmt.code == 0 || fmt.code == ~0U
>> fail: v4l2-test-subdevs.cpp(418): checkMBusFrameFmt(node, fmt.format)
>> test Active VIDIOC_SUBDEV_G/S_FMT: FAIL
>>
>> As the serializers and deserializers are format agnostic and the values set are not
>> used to configure anything in the chips, this test does not make much sense in this
>> context. If needed, a check for the specific ~0U value can be added.
>>
>> V9:
>> * split max_des_ops into *_info and *_ops
>> * use read_poll_timeout macro in *_wait_for_device()
>> * return read_poll_timeout error -ETIMEDOUT in *_wait_for_device()
>> * remove use_atr duplicate from max9296a_chip_info, present in max_des_info
>> * fix max9296a DPLL register offset
>> * fix C-PHY DPLL frequency in max9296a and max96724
>> reported by: Cory Keitz <ckeitz@amazon.com>
>> * use MAX9296A_COMMON_INFO and MAX9296A_COMMON_OPS to simplify
>> probe ops init
>> * fix borked patches in previous version, actually remove MAX96717 and
>> MAX96714 drivers
>>
>> V8:
>> * max96717: use the renamed PIN_CONFIG_OUTPUT to _LEVEL
>> * max96717: use the renamed set_rv ops from struct gpio_chip
>> * dt-bindings: set minItems lane-polarities to 2
>> * dt-bindings: "add myself as maintainer" commits were removed
>> * max_des & max_ser: use a default format for set_routing
>> * max_des & max_ser: return ENNOTTY in *_frame_interval for non-TPG pads
>>
>> V7:
>> * dt-bindings: max9296a: use full max96717 compatible
>> * max9296a: make max96714_rlms_reg_sequence static
>> * explicitly include linux/bitfield.h
>> * explicitly depend on I2C and PINCTRL
>> * sort media_entity_operations
>> * add has_pad_interdep to media_entity_operations
>>
>> V6:
>> * max9296a: put rlms sequence in max9296a_chip_info
>> * max_des: reflow stream id a comment
>> * max_ser: remove exported symbols not used in other modules
>> * max_ser: init mode to a supported value
>> * add default routing
>> * MAX_SERDES_GMSL_3 -> MAX_SERDES_GMSL_3_12GBPS
>> * guard reg_read/write with CONFIG_VIDEO_ADV_DEBUG
>> * put exported symbols in MAXIM_SERDES namespace
>>
>> V5:
>> * dt-bindings: max96717: restrict RCLKOUT to pins 2 & 4
>> * dt-bindings: max96717: remove confusing rclksel pinconf property
>> * dt-bindings: max96717: remove maxim,gmsl-tx/rx pinconf property
>> * dt-bindings: max96717: remove gmsl prefix from maxim,gmsl-tx-id/rx-id
>> * dt-bindings: max96717: remove minimum: 0
>> * dt-bindings: max96717: better document slew-rate
>> * dt-bindings: max96717: better document maxim,jitter-compensation
>> * dt-bindings: max96717: better document maxim,tx-id/rx-id
>>
>> * max_serdes: add default TPG values
>> * max_serdes: remove MAX_MIPI_FMT macro
>> * max_serdes: EXPORT_SYMBOL -> EXPORT_SYMBOL_GPL
>> * max_serdes: remove EXPORT_SYMBOL_GPL from symbols not used in other
>> modules
>> * max_serdes: rename symbols/macros/types to have max_serdes prefix
>> * max_serdes: slim down TPG functions
>>
>> * max_des: fix may be used uninitialized errors
>> * max_des: fix misplaced TPG validation
>> * max_des: fix setting pipe PHY in tunnel mode for chips that support both
>> set_pipe_phy() and set_pipe_tunnel_phy()
>> * max_des: move doubled_bpp/sink_bpps variables to usage place
>> * max_des: do not dynamically control PHY enable, letting lanes be in
>> LP-11 when not streaming
>> * max_des: refactor get/set_pipe_stream_id() logic
>> * max_des: remove explicit ret = 0
>>
>> * max_ser: make VC remaps not pipe-specific, allocate dynamically
>>
>> * max9296a: add missing 1080p30 TPG entry
>> * max9296a: move BIT() left shift into macro
>> * max9296a: move BIT() ternary into macro
>> * max9296a: reuse max_des_ops for chip-specific ops\
>> * max9296a: document and compress RLMS register writes
>>
>> * max96717: restrict RCLKOUT to pins 2 & 4 because of hardware capabilities
>> * max96717: add support for XTAL/1, XTAL/2, XTAL/4 clocks
>> * max96717: set RX_EN/TX_EN automatically
>> * max96717: reorder custom pinconf flags
>> * max96717: drop OF dependency
>>
>> * drop of_match_ptr
>> * re-do some indentation
>> * implement TPG pattern control
>> * remove pr_info() usage
>> * inline lane polarity val = 0
>> * inline returns
>> * rewrite some Kconfig docs
>> * split up patches for easier review
>>
>> V4:
>> * max_des: fix infinite version loop
>> * max_des: fix pipe link id when there are more pipes than links
>> * max_des: implement setting pipe link
>> * max_des: do not pass routing to phy update
>> * max_des: move GMSL version strings to max_serdes
>> * max_des: split finding existing VC remap from adding a new one
>> * max_des: add tracking for in-use pipes
>> * max_des: skip unused pipes when finding / setting pixel/tunnel mode
>> * max_des: simplify remap code
>> * max_des: split set_pipe_phy() into set_pipe_tunnel_phy()
>>
>> * max_ser: clean up i2c_xlates printing
>> * max_ser: fix changing serializer address
>> * max_ser: move non-continuous mode check into max96717 driver
>>
>> * max96724: use regmap_set_bits for STREAM_SEL_ALL
>> * max96724: match surrounding indent for MAX96724_PHY1_ALT_CLOCK
>> * max96724: fix setting invalid PHY to 1 when PHY 0 is in 4-lane mode
>> * max96724: remove support for setting pipe phy from max96712
>> * max96724: fix setting double mode on pipes 4-7
>> * max96724: drop powerdown gpios
>>
>> * max96717: use gpio_chip's set_rv
>>
>> * max9296a: switch versions to unsigned int
>> * max9296a: remove parantheses from MAX9296A_MIPI_PHY18/20
>> * max9296a: fix printing of PHY packet counts
>> * max9296a: fix phy_hw_ids size
>>
>> * remove usage of cammel case in defines
>> * move field_get/prep to max_serdes.h
>> * rework stream id setup
>> * rework tunnel/pixel mode finding
>> * rework bpps retrieval
>> * pass whole subdev state around
>> * add helper for retrieving a route's hw components / frame desc
>> * update pipe enable based on active routes
>> * add support for tunnel-only chips and VC remaps in tunnel mode
>> * simplify max_get_streams_masks()
>> * add support for TPG
>>
>> V3:
>> * dt-bindings: drop reflow text patches
>>
>> * dt-bindings: max96717: move pinctrl configuration into main file
>> * dt-bindings: max96717: allow a single level of pins configuration
>> * dt-bindings: max96717: use regex for matching pins nodes
>> * dt-bindings: max96717: drop extra allOf in pinctrl configuration
>> * dt-bindings: max96717: fix i2c-atr channel name regex
>> * dt-bindings: max96717: limit pinctrl functions to gpio / rclkout
>> * dt-bindings: max96717: limit pins for gpio / rclkout
>> * dt-bindings: max96717: add description for bias-pull-up/down
>> * dt-bindings: max96717: require pins and function properties
>> * dt-bindings: max96717: turn single compatible strings into an enum
>>
>> * dt-bindings: max9296a: include indices in port descriptions
>> * dt-bindings: max9296a: remove property-less schema from input ports
>> * dt-bindings: max9296a: use ATR for MAX96716A too, removing MUX entirely
>>
>> * dt-bindings: max96712: include indices in port descriptions
>> * dt-bindings: max96712: deprecate enable-gpios in favor of powerdown-gpios
>> * dt-bindings: max96712: switch from MUX to ATR
>>
>> * dt-bindings: max96714: add support for MAX96714R
>>
>> * max_des: fix POC NULL check
>> * max_des: remove index var in POC enable
>> * max_des: fix writing empty remaps
>> * max_des: skip mode setting in tunnel mode
>> * max_des: remove a duplicate source->sd NULL check
>> * max_des: set pipe tunnel mode even for disabled links
>>
>> * max_ser: apply TX ID changes irrespective of serializer ID
>>
>> * max9296a: fix typo in BACKTOP22
>> * max9296a: make register macros more consistent
>> * max9296a: switch MAX96716 from MUX to ATR
>> * max9296a: deduplicate max9296a_phy_id() logic
>> * max9296a: use proper PHY id in remaps
>> * max9296a: fix DPLL reset clear
>> * max9296a: limit MAX96714F to GMSL2 3Gbps
>> * max9296a: add support for MAX96714R
>> * max9296a: do not write GMSL3 link select registers in GMSL2 devices
>> * max9296a: use field_prep when setting RX_RATE
>> * max9296a: simplify setting SEL_STREAM for MAX96714
>> * max9296a: max96716_set_pipe_phy -> max96716a_set_pipe_phy
>> * max9296a: fix off-by-one in lane polarity when using
>> polarity_on_physical_lanes
>>
>> * max96724: fix typo in BACKTOP22
>> * max96724: switch from MUX to ATR
>> * max96724: add support for powerdown GPIO
>> * max96724: remove support for tunneling from MAX96712
>> * max96724: only set tunnel-related bits when in tunnel mode
>> * max96724: add support for MAX96724F/R
>> * max96724: oneshot reset links after link selection
>>
>> * remove GMSL2 version defaults, set all supported versions explicitly
>> * reorder GMSL versions to start from 0
>> * add support for GMSL2 3Gbps
>> * support GMSL version finding for devices using MUX / GATE
>> * add support for deserializers which don't have individual control of each link's
>> GMSL version
>> * add support for deserializers that need unique stream ids across all serializers
>> * select_link_version -> set_link_version
>> * select_resets_link -> use_atr
>>
>> V2:
>> * add missing compatible for MAX96717F
>> * fix embarrassing dt-bindings mistakes
>> * move MAX9296A/MAX96716/MAX96792A to a separate file as they have two
>> links / PHYs, and adding those conditionally seems impossible
>> ---
>> Cosmin Tanislav (20):
>> dt-bindings: media: i2c: max96717: add support for I2C ATR
>> dt-bindings: media: i2c: max96717: add support for pinctrl/pinconf
>> dt-bindings: media: i2c: max96717: add support for MAX9295A
>> dt-bindings: media: i2c: max96717: add support for MAX96793
>> dt-bindings: media: i2c: max96712: use pattern properties for ports
>> dt-bindings: media: i2c: max96712: add support for I2C ATR
>> dt-bindings: media: i2c: max96712: add support for POC supplies
>> dt-bindings: media: i2c: max96712: add support for MAX96724F/R
>> dt-bindings: media: i2c: max96714: add support for MAX96714R
>> dt-bindings: media: i2c: add MAX9296A, MAX96716A, MAX96792A
>> media: i2c: add Maxim GMSL2/3 serializer and deserializer framework
>> media: i2c: add Maxim GMSL2/3 serializer framework
>> media: i2c: add Maxim GMSL2/3 deserializer framework
>> media: i2c: maxim-serdes: add MAX96717 driver
>> media: i2c: maxim-serdes: add MAX96724 driver
>> media: i2c: maxim-serdes: add MAX9296A driver
>> arm64: defconfig: disable deprecated MAX96712 driver
>> staging: media: remove MAX96712 driver
>> media: i2c: remove MAX96717 driver
>> media: i2c: remove MAX96714 driver
>>
>> Sakari Ailus (1):
>> media: mc: Add INTERNAL pad flag
>>
>> .../bindings/media/i2c/maxim,max9296a.yaml | 242 ++
>> .../bindings/media/i2c/maxim,max96712.yaml | 65 +-
>> .../bindings/media/i2c/maxim,max96714.yaml | 5 +-
>> .../bindings/media/i2c/maxim,max96717.yaml | 154 +-
>> .../userspace-api/media/mediactl/media-types.rst | 9 +
>> MAINTAINERS | 10 +-
>> arch/arm64/configs/defconfig | 1 -
>> drivers/media/i2c/Kconfig | 34 +-
>> drivers/media/i2c/Makefile | 3 +-
>> drivers/media/i2c/max96714.c | 1017 -------
>> drivers/media/i2c/max96717.c | 1102 -------
>> drivers/media/i2c/maxim-serdes/Kconfig | 60 +
>> drivers/media/i2c/maxim-serdes/Makefile | 6 +
>> drivers/media/i2c/maxim-serdes/max9296a.c | 1358 +++++++++
>> drivers/media/i2c/maxim-serdes/max96717.c | 1686 +++++++++++
>> drivers/media/i2c/maxim-serdes/max96724.c | 1193 ++++++++
>> drivers/media/i2c/maxim-serdes/max_des.c | 3188
>> ++++++++++++++++++++
>> drivers/media/i2c/maxim-serdes/max_des.h | 156 +
>> drivers/media/i2c/maxim-serdes/max_ser.c | 2138 +++++++++++++
>> drivers/media/i2c/maxim-serdes/max_ser.h | 147 +
>> drivers/media/i2c/maxim-serdes/max_serdes.c | 413 +++
>> drivers/media/i2c/maxim-serdes/max_serdes.h | 183 ++
>> drivers/media/mc/mc-entity.c | 15 +-
>> drivers/staging/media/Kconfig | 2 -
>> drivers/staging/media/Makefile | 1 -
>> drivers/staging/media/max96712/Kconfig | 14 -
>> drivers/staging/media/max96712/Makefile | 2 -
>> drivers/staging/media/max96712/max96712.c | 487 ---
>> include/uapi/linux/media.h | 1 +
>> 29 files changed, 11006 insertions(+), 2686 deletions(-)
>> ---
>> base-commit: a15a902a91b78f1544760fb52ef0151f83815f81
>> change-id: 20251107-gmsl2-3_serdes-3f2b885209c3
>>
>> Best regards,
^ permalink raw reply
* Re: [PATCH v5 2/4] ACPI: of: match PRP0001 in of_match_device
From: Krzysztof Kozlowski @ 2026-03-30 7:00 UTC (permalink / raw)
To: Markus Probst
Cc: Hans de Goede, Ilpo Järvinen, Bryan O'Donoghue,
Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Miguel Ojeda, Boqun Feng, Gary Guo,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Trevor Gross, Danilo Krummrich, Greg Kroah-Hartman,
Rafael J. Wysocki, Len Brown, Saravana Kannan,
platform-driver-x86, linux-leds, devicetree, linux-kernel,
rust-for-linux, linux-acpi
In-Reply-To: <20260329-synology_microp_initial-v5-2-27cb80bdf591@posteo.de>
On Sun, Mar 29, 2026 at 08:02:16PM +0200, Markus Probst wrote:
> Export `acpi_of_match_device` function and use it to match for PRP0001
> in `of_match_device`, if the device does not have a device node.
>
> This fixes the match data being NULL when using ACPI PRP0001, even though
> the device was matched against an of device table.
Fixes tag?
I don't see how this is going to fix !ACPI case - the
acpi_of_match_device() will just return false.
>
> Signed-off-by: Markus Probst <markus.probst@posteo.de>
> ---
> drivers/acpi/bus.c | 7 ++++---
> drivers/of/device.c | 9 +++++++--
> include/linux/acpi.h | 11 +++++++++++
> 3 files changed, 22 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
> index 2ec095e2009e..cd02f04cf685 100644
> --- a/drivers/acpi/bus.c
> +++ b/drivers/acpi/bus.c
> @@ -831,9 +831,9 @@ const struct acpi_device *acpi_companion_match(const struct device *dev)
> * identifiers and a _DSD object with the "compatible" property, use that
> * property to match against the given list of identifiers.
> */
> -static bool acpi_of_match_device(const struct acpi_device *adev,
> - const struct of_device_id *of_match_table,
> - const struct of_device_id **of_id)
> +bool acpi_of_match_device(const struct acpi_device *adev,
> + const struct of_device_id *of_match_table,
> + const struct of_device_id **of_id)
> {
> const union acpi_object *of_compatible, *obj;
> int i, nval;
> @@ -866,6 +866,7 @@ static bool acpi_of_match_device(const struct acpi_device *adev,
>
> return false;
> }
> +EXPORT_SYMBOL_GPL(acpi_of_match_device);
>
> static bool acpi_of_modalias(struct acpi_device *adev,
> char *modalias, size_t len)
> diff --git a/drivers/of/device.c b/drivers/of/device.c
> index f7e75e527667..128682390058 100644
> --- a/drivers/of/device.c
> +++ b/drivers/of/device.c
> @@ -11,6 +11,7 @@
> #include <linux/mod_devicetable.h>
> #include <linux/slab.h>
> #include <linux/platform_device.h>
> +#include <linux/acpi.h>
>
> #include <asm/errno.h>
> #include "of_private.h"
> @@ -26,8 +27,12 @@
> const struct of_device_id *of_match_device(const struct of_device_id *matches,
> const struct device *dev)
> {
> - if (!matches || !dev->of_node || dev->of_node_reused)
> - return NULL;
> + if (!matches || !dev->of_node || dev->of_node_reused) {
> + const struct of_device_id *id = NULL;
> +
> + acpi_of_match_device(ACPI_COMPANION(dev), matches, &id);
I don't think this should be done from of_match_device. Yuo will have
soon recursive calls, because acpi_of_match_device() will call other
match, that will call of_match_device() and so on...
of_match_device() is supposed to match only against OF. Not ACPI. There
should be no ACPI header or code in this unit file.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 3/3] riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2
From: Chukun Pan @ 2026-03-30 7:00 UTC (permalink / raw)
To: gaohan
Cc: alex, aou, conor+dt, devicetree, dlan, krzk+dt, linux-kernel,
linux-riscv, palmer, pjw, rabenda.cn, robh, spacemit, Chukun Pan
In-Reply-To: <84f8e713ef1ee46f9be852f400f52d6c055725f8.1774803532.git.gaohan@iscas.ac.cn>
Hi,
> + usb3_hub_5v: regulator-usb3-hub-5v {
> + compatible = "regulator-fixed";
> + regulator-name = "USB_HUB_EN";
regulator-name = "vcc5v0_usb30";
"USB_HUB_EN" is the pin name.
> +&usb_dwc3 {
> + dr_mode = "host";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + hub_2_0: hub@1 {
> + compatible = "usb5e3,610";
> + reg = <0x1>;
> + vdd-supply = <&usb3_hub_5v>;
This is incorrect...
The hub is powered by VCC_5V0.
VCC5V0_USB30 provides USB VBUS.
Thanks,
Chukun
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: arm: qcom: Add monaco-evk-ac-sku support
From: Krzysztof Kozlowski @ 2026-03-30 6:54 UTC (permalink / raw)
To: Umang Chheda
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Richard Cochran, linux-arm-msm, devicetree,
linux-kernel
In-Reply-To: <f7e63fa7-2579-4dce-974a-8c81a1aee00f@oss.qualcomm.com>
On 30/03/2026 08:50, Umang Chheda wrote:
> Hello Krzysztof,
>
> On 3/29/2026 3:22 PM, Krzysztof Kozlowski wrote:
>> On Sat, Mar 28, 2026 at 05:11:17PM +0530, Umang Chheda wrote:
>>> Introduce new bindings for the monaco-evk-ac-sku,
>>> an IoT board based on the QCS8300-AC variant SoC.
>> Please wrap commit message according to Linux coding style / submission
>> process (neither too early nor over the limit):
>> https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597
>
>
> Ack
>
>>
>>> Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
>>> ---
>>> Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>>> index ca880c105f3b..07053cc2ac1c 100644
>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>>> @@ -918,6 +918,7 @@ properties:
>>> - enum:
>>> - arduino,monza
>>> - qcom,monaco-evk
>>> + - qcom,monaco-evk-ac-sku
>> Why adding name 'sku' to the compatible? What's the meaning here?
>
>
> Monaco SoC has 2 variants - monaco-aa and monaco-ac -- "monaco-evk" board uses monaco-aa variant of SoC and this new
so ac? or ac-sku? Decide.
> introduced board uses the monaco-ac variant SoC. Hence added the compatible as "monaco-evk-ac-sku" to differentiate it from
> monaco-evk board.
Wrap your emails.
"ac" differentiates. Why do you need to say that a variant is a
"-variant"?
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v7 0/5] Add driver for EC found on Qualcomm reference devices
From: Anvesh Jain P @ 2026-03-30 6:52 UTC (permalink / raw)
To: Akhil P Oommen
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
Maya Matuszczyk, Krzysztof Kozlowski, Dmitry Baryshkov,
Konrad Dybcio, Abel Vesa, Gaurav Kohli, Sibi Sankar, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Hans de Goede,
Ilpo Järvinen, Bryan O'Donoghue, Bjorn Andersson,
Konrad Dybcio, Randy Dunlap
In-Reply-To: <45cad9a9-8bb3-4174-aa5b-7a7cb3b7603e@oss.qualcomm.com>
On 3/29/2026 7:52 PM, Akhil P Oommen wrote:
> On 3/27/2026 3:38 PM, Anvesh Jain P wrote:
>> From: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
>>
>> Add Embedded controller driver support for Hamoa/Purwa/Glymur Qualcomm
>> reference boards. It handles fan control, temperature sensors, access
>> to EC state changes and supports reporting suspend entry/exit to the EC.
>
> Just a question, is it possible to force fan to run at full speed
> constantly? That would be helpful to keep the passive cooling minimal
> and get a more consistent results while doing performance profiling.
>
> I see that you are registering a cooling device in this series. So I
> suppose we just need to update the cooling sysfs nodes.
>
> -Akhil
>
Hi Akhil,
Yes, that is possible. The cooling device registered by this driver
exposes the standard thermal sysfs interface. You can force the fan
to full speed by writing the maximum cooling state directly:
# Find the max state
cat /sys/class/thermal/cooling_deviceX/max_state
# Set to max state (force full speed)
echo <max_state> > /sys/class/thermal/cooling_deviceX/cur_state
Where X is the index of the cooling device corresponding to the EC fan.
--
Best Regards,
Anvesh
^ permalink raw reply
* Re: [PATCH v5 1/4] dt-bindings: embedded-controller: Add synology microp devices
From: Krzysztof Kozlowski @ 2026-03-30 6:51 UTC (permalink / raw)
To: Markus Probst
Cc: Hans de Goede, Ilpo Järvinen, Bryan O'Donoghue,
Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Miguel Ojeda, Boqun Feng, Gary Guo,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Trevor Gross, Danilo Krummrich, Greg Kroah-Hartman,
Rafael J. Wysocki, Len Brown, Saravana Kannan,
platform-driver-x86, linux-leds, devicetree, linux-kernel,
rust-for-linux, linux-acpi
In-Reply-To: <20260329-synology_microp_initial-v5-1-27cb80bdf591@posteo.de>
On Sun, Mar 29, 2026 at 08:02:15PM +0200, Markus Probst wrote:
> +properties:
> + compatible:
> + enum:
> + - synology,ds923p-microp
> + - synology,ds918p-microp
> + - synology,ds214play-microp
> + - synology,ds225p-microp
> + - synology,ds425p-microp
> + - synology,ds710p-microp
> + - synology,ds1010p-microp
> + - synology,ds723p-microp
> + - synology,ds1522p-microp
> + - synology,rs422p-microp
> + - synology,ds725p-microp
> + - synology,ds118-microp
> + - synology,ds124-microp
> + - synology,ds223-microp
> + - synology,ds223j-microp
> + - synology,ds1823xsp-microp
> + - synology,rs822p-microp
> + - synology,rs1221p-microp
> + - synology,rs1221rpp-microp
> + - synology,ds925p-microp
> + - synology,ds1525p-microp
> + - synology,ds1825p-microp
Last time you had one compatible and implied they are all compatible.
Now none of them are compatible, which might be accurate, but nothing
explains WHY they are not compatible in the commit msg.
> +
> + fan-failure-gpios:
> + description: GPIOs needed to determine which fans stopped working on a fan failure event.
> + minItems: 2
> + maxItems: 3
Constraints cannot be flexible. You need allOf:if:then: block to narrow
them per variant.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 4/4] platform: Add initial synology microp driver
From: Krzysztof Kozlowski @ 2026-03-30 6:51 UTC (permalink / raw)
To: markus.probst, Hans de Goede, Ilpo Järvinen,
Bryan O'Donoghue, Lee Jones, Pavel Machek, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Miguel Ojeda, Boqun Feng,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Trevor Gross, Danilo Krummrich, Greg Kroah-Hartman,
Rafael J. Wysocki, Len Brown, Saravana Kannan
Cc: platform-driver-x86, linux-leds, devicetree, linux-kernel,
rust-for-linux, linux-acpi
In-Reply-To: <20260329-synology_microp_initial-v5-4-27cb80bdf591@posteo.de>
On 29/03/2026 20:02, Markus Probst via B4 Relay wrote:
> +
> +kernel::of_device_table!(
> + pub(crate) OF_TABLE,
> + MODULE_OF_TABLE,
> + Model,
> + models![
> + apollolake @ [
> + ds918p,
> + ],
> + evansport @ [
> + ds214play,
> + ],
> + geminilakenk @ [
> + ds225p.led_usb_copy(),
> + ds425p,
> + ],
> + pineview @ [
> + ds710p.led_esata(),
> + ds1010p.led_alert(Color::Orange),
> + ],
> + r1000 @ [
> + ds923p,
> + ds723p,
> + ds1522p,
> + rs422p.led_power(Color::Green),
> + ],
> + r1000nk @ [
> + ds725p,
> + ],
> + rtd1296 @ [
> + ds118,
> + ],
> + rtd1619b @ [
> + ds124,
> + ds223.led_usb_copy(),
> + ds223j,
> + ],
> + v1000 @ [
> + ds1823xsp,
> + rs822p.led_power(Color::Green),
> + rs1221p.led_power(Color::Green),
> + rs1221rpp.led_power(Color::Green),
> + ],
> + v1000nk @ [
> + ds925p,
> + ds1525p,
> + ds1825p,
I don't see any compatible strings here. Actually, nowhere in the
driver. If that's how you write Rust drivers then NAK. Compatibles must
be greppable. Not only for humans but also for ABI check.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 2/3] riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2
From: Chukun Pan @ 2026-03-30 6:50 UTC (permalink / raw)
To: gaohan
Cc: alex, aou, conor+dt, devicetree, dlan, krzk+dt, linux-kernel,
linux-riscv, palmer, pjw, rabenda.cn, robh, spacemit, Chukun Pan
In-Reply-To: <492e0bea0fb84f49f4bead3dc3d563b13d98df11.1774803532.git.gaohan@iscas.ac.cn>
Hi,
> The power management hardware design on the OrangePi RV2 is identical to
> the Banana Pi BPI-F3, so the DT Nodes were taken from k1-bananapi-f3.dts.
Why? If you've looked at the schematics, you'll find there are differences.
e.g. The regulator name and the PMIC have several pins left floating:
aldo2, aldo3, aldo4, dldo2, dldo3, dldo7.
> + reg_dc_in: regulator-vcc-in-5v {
> + compatible = "regulator-fixed";
> + regulator-name = "dc_in_5v";
vcc_5v0
> + reg_vcc_4v: regulator-vcc-4v {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc_4v";
vcc4v0
Thanks,
Chukun
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: arm: qcom: Add monaco-evk-ac-sku support
From: Umang Chheda @ 2026-03-30 6:50 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Richard Cochran, linux-arm-msm, devicetree,
linux-kernel
In-Reply-To: <20260329-accelerated-pigeon-of-joy-c6c903@quoll>
Hello Krzysztof,
On 3/29/2026 3:22 PM, Krzysztof Kozlowski wrote:
> On Sat, Mar 28, 2026 at 05:11:17PM +0530, Umang Chheda wrote:
>> Introduce new bindings for the monaco-evk-ac-sku,
>> an IoT board based on the QCS8300-AC variant SoC.
> Please wrap commit message according to Linux coding style / submission
> process (neither too early nor over the limit):
> https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597
Ack
>
>> Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
>> ---
>> Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>> index ca880c105f3b..07053cc2ac1c 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>> @@ -918,6 +918,7 @@ properties:
>> - enum:
>> - arduino,monza
>> - qcom,monaco-evk
>> + - qcom,monaco-evk-ac-sku
> Why adding name 'sku' to the compatible? What's the meaning here?
Monaco SoC has 2 variants - monaco-aa and monaco-ac -- "monaco-evk" board uses monaco-aa variant of SoC and this new
introduced board uses the monaco-ac variant SoC. Hence added the compatible as "monaco-evk-ac-sku" to differentiate it from
monaco-evk board.
>
> Best regards,
> Krzysztof
Thanks,
Umang
^ permalink raw reply
* Re: [PATCH v7 2/5] platform: arm64: Add driver for EC found on Qualcomm reference devices
From: Anvesh Jain P @ 2026-03-30 6:44 UTC (permalink / raw)
To: Ilpo Järvinen
Cc: Sibi Sankar, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Hans de Goede, Bryan O'Donoghue, Bjorn Andersson,
Konrad Dybcio, Randy Dunlap, linux-arm-msm, devicetree,
linux-kernel, platform-driver-x86, Maya Matuszczyk,
Dmitry Baryshkov, Konrad Dybcio
In-Reply-To: <308ae40a-34f1-9b69-bfe7-150ca8ad1d29@linux.intel.com>
On 3/27/2026 5:20 PM, Ilpo Järvinen wrote:
> On Fri, 27 Mar 2026, Anvesh Jain P wrote:
>
>> From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>>
>> Add Embedded controller driver support for Hamoa/Purwa/Glymur qualcomm
>> reference boards. It handles fan control, temperature sensors, access
>> to EC state changes and supports reporting suspend entry/exit to the
>> EC.
>>
>> Co-developed-by: Maya Matuszczyk <maccraft123mc@gmail.com>
>> Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
>> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Co-developed-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
>> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
>> ---
>> MAINTAINERS | 8 +
>> drivers/platform/arm64/Kconfig | 12 +
>> drivers/platform/arm64/Makefile | 1 +
>> drivers/platform/arm64/qcom-hamoa-ec.c | 451 +++++++++++++++++++++++++++++++++
>> 4 files changed, 472 insertions(+)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 30ca84404976..536dfd9adff4 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -21804,6 +21804,14 @@ F: Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml
>> F: drivers/misc/fastrpc.c
>> F: include/uapi/misc/fastrpc.h
>>
>> +QUALCOMM HAMOA EMBEDDED CONTROLLER DRIVER
>> +M: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
>> +M: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>> +L: linux-arm-msm@vger.kernel.org
>> +S: Maintained
>> +F: Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-ec.yaml
>> +F: drivers/platform/arm64/qcom-hamoa-ec.c
>> +
>> QUALCOMM HEXAGON ARCHITECTURE
>> M: Brian Cain <brian.cain@oss.qualcomm.com>
>> L: linux-hexagon@vger.kernel.org
>> diff --git a/drivers/platform/arm64/Kconfig b/drivers/platform/arm64/Kconfig
>> index 10f905d7d6bf..025cdf091f9e 100644
>> --- a/drivers/platform/arm64/Kconfig
>> +++ b/drivers/platform/arm64/Kconfig
>> @@ -90,4 +90,16 @@ config EC_LENOVO_THINKPAD_T14S
>>
>> Say M or Y here to include this support.
>>
>> +config EC_QCOM_HAMOA
>> + tristate "Embedded Controller driver for Qualcomm Hamoa/Glymur reference devices"
>> + depends on ARCH_QCOM || COMPILE_TEST
>> + depends on I2C
>> + help
>> + Say M or Y here to enable the Embedded Controller driver for Qualcomm
>> + Snapdragon-based Hamoa/Glymur reference devices. The driver handles fan
>> + control, temperature sensors, access to EC state changes and supports
>> + reporting suspend entry/exit to the EC.
>> +
>> + This driver currently supports Hamoa/Purwa/Glymur reference devices.
>> +
>> endif # ARM64_PLATFORM_DEVICES
>> diff --git a/drivers/platform/arm64/Makefile b/drivers/platform/arm64/Makefile
>> index 60c131cff6a1..7681be4a46e9 100644
>> --- a/drivers/platform/arm64/Makefile
>> +++ b/drivers/platform/arm64/Makefile
>> @@ -9,3 +9,4 @@ obj-$(CONFIG_EC_ACER_ASPIRE1) += acer-aspire1-ec.o
>> obj-$(CONFIG_EC_HUAWEI_GAOKUN) += huawei-gaokun-ec.o
>> obj-$(CONFIG_EC_LENOVO_YOGA_C630) += lenovo-yoga-c630.o
>> obj-$(CONFIG_EC_LENOVO_THINKPAD_T14S) += lenovo-thinkpad-t14s.o
>> +obj-$(CONFIG_EC_QCOM_HAMOA) += qcom-hamoa-ec.o
>> diff --git a/drivers/platform/arm64/qcom-hamoa-ec.c b/drivers/platform/arm64/qcom-hamoa-ec.c
>> new file mode 100644
>> index 000000000000..0f883130ac9a
>> --- /dev/null
>> +++ b/drivers/platform/arm64/qcom-hamoa-ec.c
>> @@ -0,0 +1,451 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2024 Maya Matuszczyk <maccraft123mc@gmail.com>
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +
>> +#include <linux/bitfield.h>
>> +#include <linux/bits.h>
>> +#include <linux/device.h>
>> +#include <linux/err.h>
>> +#include <linux/i2c.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/pm.h>
>> +#include <linux/slab.h>
>> +#include <linux/thermal.h>
>> +
>> +#define EC_SCI_EVT_READ_CMD 0x05
>> +#define EC_FW_VERSION_CMD 0x0e
>> +#define EC_MODERN_STANDBY_CMD 0x23
>> +#define EC_FAN_DBG_CONTROL_CMD 0x30
>> +#define EC_SCI_EVT_CONTROL_CMD 0x35
>> +#define EC_THERMAL_CAP_CMD 0x42
>> +
>> +#define EC_FW_VERSION_RESP_LEN 4
>> +#define EC_THERMAL_CAP_RESP_LEN 3
>> +#define EC_FAN_DEBUG_CMD_LEN 6
>> +#define EC_FAN_SPEED_DATA_SIZE 4
>> +
>> +#define EC_MODERN_STANDBY_ENTER 0x01
>> +#define EC_MODERN_STANDBY_EXIT 0x00
>> +
>> +#define EC_FAN_DEBUG_MODE_OFF 0
>> +#define EC_FAN_DEBUG_MODE_ON BIT(0)
>
> Add include for BIT().
>
Added <linux/bits.h> in v6 to address this.
>> +#define EC_FAN_ON BIT(1)
>> +#define EC_FAN_DEBUG_TYPE_PWM BIT(2)
>> +#define EC_MAX_FAN_CNT 2
>> +#define EC_FAN_NAME_SIZE 20
>> +#define EC_FAN_MAX_PWM 255
>> +
>> +enum qcom_ec_sci_events {
>> + EC_FAN1_STATUS_CHANGE_EVT = 0x30,
>> + EC_FAN2_STATUS_CHANGE_EVT,
>> + EC_FAN1_SPEED_CHANGE_EVT,
>> + EC_FAN2_SPEED_CHANGE_EVT,
>> + EC_NEW_LUT_SET_EVT,
>> + EC_FAN_PROFILE_SWITCH_EVT,
>> + EC_THERMISTOR_1_THRESHOLD_CROSS_EVT,
>> + EC_THERMISTOR_2_THRESHOLD_CROSS_EVT,
>> + EC_THERMISTOR_3_THRESHOLD_CROSS_EVT,
>> + /* Reserved: 0x39 - 0x3c/0x3f */
>> + EC_RECOVERED_FROM_RESET_EVT = 0x3d,
>> +};
>> +
>> +struct qcom_ec_version {
>> + u8 main_version;
>> + u8 sub_version;
>> + u8 test_version;
>> +};
>> +
>> +struct qcom_ec_thermal_cap {
>> +#define EC_THERMAL_FAN_CNT(x) (FIELD_GET(GENMASK(1, 0), (x)))
>> +#define EC_THERMAL_FAN_TYPE(x) (FIELD_GET(GENMASK(4, 2), (x)))
>> +#define EC_THERMAL_THERMISTOR_MASK(x) (FIELD_GET(GENMASK(7, 0), (x)))
>> + u8 fan_cnt;
>> + u8 fan_type;
>> + u8 thermistor_mask;
>> +};
>> +
>> +struct qcom_ec_cooling_dev {
>> + struct thermal_cooling_device *cdev;
>> + struct device *parent_dev;
>> + u8 fan_id;
>> + u8 state;
>> +};
>> +
>> +struct qcom_ec {
>> + struct qcom_ec_cooling_dev *ec_cdev;
>> + struct qcom_ec_thermal_cap thermal_cap;
>> + struct qcom_ec_version version;
>> + struct i2c_client *client;
>> +};
>> +
>> +static int qcom_ec_read(struct qcom_ec *ec, u8 cmd, u8 resp_len, u8 *resp)
>> +{
>> + int ret;
>> +
>> + ret = i2c_smbus_read_i2c_block_data(ec->client, cmd, resp_len, resp);
>> +
>> + if (ret < 0)
>> + return ret;
>> + else if (ret == 0 || ret == 0xff)
>> + return -EOPNOTSUPP;
>> +
>> + if (resp[0] >= resp_len)
>> + return -EINVAL;
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * EC Device Firmware Version:
>> + *
>> + * Read Response:
>> + * ----------------------------------------------------------------------
>> + * | Offset | Name | Description |
>> + * ----------------------------------------------------------------------
>> + * | 0x00 | Byte count | Number of bytes in response |
>> + * | | | (excluding byte count) |
>> + * ----------------------------------------------------------------------
>> + * | 0x01 | Test-version | Test-version of EC firmware |
>> + * ----------------------------------------------------------------------
>> + * | 0x02 | Sub-version | Sub-version of EC firmware |
>> + * ----------------------------------------------------------------------
>> + * | 0x03 | Main-version | Main-version of EC firmware |
>> + * ----------------------------------------------------------------------
>> + *
>> + */
>> +static int qcom_ec_read_fw_version(struct device *dev)
>> +{
>> + struct i2c_client *client = to_i2c_client(dev);
>> + struct qcom_ec *ec = i2c_get_clientdata(client);
>> + struct qcom_ec_version *version = &ec->version;
>> + u8 resp[EC_FW_VERSION_RESP_LEN];
>> + int ret;
>> +
>> + ret = qcom_ec_read(ec, EC_FW_VERSION_CMD, EC_FW_VERSION_RESP_LEN, resp);
>> + if (ret < 0)
>> + return ret;
>> +
>> + version->main_version = resp[3];
>> + version->sub_version = resp[2];
>> + version->test_version = resp[1];
>> +
>> + dev_dbg(dev, "EC Version %d.%d.%d\n",
>> + version->main_version, version->sub_version, version->test_version);
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * EC Device Thermal Capabilities:
>> + *
>> + * Read Response:
>> + * ------------------------------------------------------------------------------
>> + * | Offset | Name | Description |
>> + * ------------------------------------------------------------------------------
>> + * | 0x00 | Byte count | Number of bytes in response |
>> + * | | | (excluding byte count) |
>> + * ------------------------------------------------------------------------------
>> + * | 0x02 (LSB) | EC Thermal | Bit 0-1: Number of fans |
>> + * | 0x3 | Capabilities | Bit 2-4: Type of fan |
>
> 0x03 ?
>
Typo, Will fix to 0x03 in next respin.
>> + * | | | Bit 5-6: Reserved |
>> + * | | | Bit 7: Data Valid/Invalid |
>> + * | | | (Valid - 1, Invalid - 0) |
>> + * | | | Bit 8-15: Thermistor 0 - 7 presence |
>> + * | | | (1 present, 0 absent) |
>> + * ------------------------------------------------------------------------------
>> + *
>> + */
>> +static int qcom_ec_thermal_capabilities(struct device *dev)
>> +{
>> + struct i2c_client *client = to_i2c_client(dev);
>> + struct qcom_ec *ec = i2c_get_clientdata(client);
>> + struct qcom_ec_thermal_cap *cap = &ec->thermal_cap;
>> + u8 resp[EC_THERMAL_CAP_RESP_LEN];
>> + int ret;
>> +
>> + ret = qcom_ec_read(ec, EC_THERMAL_CAP_CMD, EC_THERMAL_CAP_RESP_LEN, resp);
>> + if (ret < 0)
>> + return ret;
>> +
>> + cap->fan_cnt = min(EC_MAX_FAN_CNT, EC_THERMAL_FAN_CNT(resp[1]));
>> + cap->fan_type = EC_THERMAL_FAN_TYPE(resp[1]);
>> + cap->thermistor_mask = EC_THERMAL_THERMISTOR_MASK(resp[2]);
>> +
>> + dev_dbg(dev, "Fan count: %d Fan Type: %d Thermistor Mask: %x\n",
>
> Please add include for dev_dbg().
>
> It seems you've missed at least some of my comments to v5, please recheck
> those comments. I won't look further for now.
>
> --
> i.
>
Added <linux/device.h> for dev_dbg() in v6, will include
<linux/dev_printk.h> as well in in v8. That said, all your v5 comments
have been addressed, here is a summary of what was fixed:
- Add <linux/bits.h> for BIT()
- Add <linux/err.h> for IS_ERR()
- Switch thermistor mask format specifier from %d to %x
- Add missing braces
- Remove empty line within variable declarations
- Change loop counter i to unsigned int
- Replace snprintf() with scnprintf()
- Use sizeof(name) instead of the EC_FAN_NAME_SIZE macro directly
- Condense devm_thermal_of_cooling_device_register() to 2 lines
Apologies if it appeared otherwise. If anything was missed, please do
point it out and I will address it in the next respin.
>> + cap->fan_cnt, cap->fan_type, cap->thermistor_mask);
>> +
>> + return 0;
>> +}
>> +
>> +static irqreturn_t qcom_ec_irq(int irq, void *data)
>> +{
>> + struct qcom_ec *ec = data;
>> + struct device *dev = &ec->client->dev;
>> + int val;
>> +
>> + val = i2c_smbus_read_byte_data(ec->client, EC_SCI_EVT_READ_CMD);
>> + if (val < 0) {
>> + dev_err_ratelimited(dev, "Failed to read EC SCI Event: %d\n", val);
>> + return IRQ_HANDLED;
>> + }
>> +
>> + switch (val) {
>> + case EC_FAN1_STATUS_CHANGE_EVT:
>> + dev_dbg_ratelimited(dev, "Fan1 status changed\n");
>> + break;
>> + case EC_FAN2_STATUS_CHANGE_EVT:
>> + dev_dbg_ratelimited(dev, "Fan2 status changed\n");
>> + break;
>> + case EC_FAN1_SPEED_CHANGE_EVT:
>> + dev_dbg_ratelimited(dev, "Fan1 speed crossed low/high trip point\n");
>> + break;
>> + case EC_FAN2_SPEED_CHANGE_EVT:
>> + dev_dbg_ratelimited(dev, "Fan2 speed crossed low/high trip point\n");
>> + break;
>> + case EC_NEW_LUT_SET_EVT:
>> + dev_dbg_ratelimited(dev, "New LUT set\n");
>> + break;
>> + case EC_FAN_PROFILE_SWITCH_EVT:
>> + dev_dbg_ratelimited(dev, "FAN Profile switched\n");
>> + break;
>> + case EC_THERMISTOR_1_THRESHOLD_CROSS_EVT:
>> + dev_dbg_ratelimited(dev, "Thermistor 1 threshold crossed\n");
>> + break;
>> + case EC_THERMISTOR_2_THRESHOLD_CROSS_EVT:
>> + dev_dbg_ratelimited(dev, "Thermistor 2 threshold crossed\n");
>> + break;
>> + case EC_THERMISTOR_3_THRESHOLD_CROSS_EVT:
>> + dev_dbg_ratelimited(dev, "Thermistor 3 threshold crossed\n");
>> + break;
>> + case EC_RECOVERED_FROM_RESET_EVT:
>> + dev_dbg_ratelimited(dev, "EC recovered from reset\n");
>> + break;
>> + default:
>> + dev_notice_ratelimited(dev, "Unknown EC event: %d\n", val);
>> + break;
>> + }
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static int qcom_ec_sci_evt_control(struct device *dev, bool enable)
>> +{
>> + struct i2c_client *client = to_i2c_client(dev);
>> +
>> + return i2c_smbus_write_byte_data(client, EC_SCI_EVT_CONTROL_CMD, !!enable);
>> +}
>> +
>> +static int qcom_ec_fan_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state)
>> +{
>> + *state = EC_FAN_MAX_PWM;
>> +
>> + return 0;
>> +}
>> +
>> +static int qcom_ec_fan_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state)
>> +{
>> + struct qcom_ec_cooling_dev *ec_cdev = cdev->devdata;
>> +
>> + *state = ec_cdev->state;
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * Fan Debug control command:
>> + *
>> + * Command Payload:
>> + * --------------------------------------------------------------------------------------
>> + * | Offset | Name | Description |
>> + * --------------------------------------------------------------------------------------
>> + * | 0x00 | Command | Fan control command |
>> + * --------------------------------------------------------------------------------------
>> + * | 0x01 | Fan ID | 0x1 : Fan 1 |
>> + * | | | 0x2 : Fan 2 |
>> + * --------------------------------------------------------------------------------------
>> + * | 0x02 | Byte count = 4| Size of data to set fan speed |
>> + * --------------------------------------------------------------------------------------
>> + * | 0x03 | Mode | Bit 0: Debug Mode On/Off (0 - OFF, 1 - ON ) |
>> + * | | | Bit 1: Fan On/Off (0 - Off, 1 - ON) |
>> + * | | | Bit 2: Debug Type (0 - RPM, 1 - PWM) |
>> + * --------------------------------------------------------------------------------------
>> + * | 0x04 (LSB) | Speed in RPM | RPM value, if mode selected is RPM |
>> + * | 0x05 | | |
>> + * --------------------------------------------------------------------------------------
>> + * | 0x06 | Speed in PWM | PWM value, if mode selected is PWM (0 - 255) |
>> + * ______________________________________________________________________________________
>> + *
>> + */
>> +static int qcom_ec_fan_debug_mode_off(struct qcom_ec_cooling_dev *ec_cdev)
>> +{
>> + struct device *dev = ec_cdev->parent_dev;
>> + struct i2c_client *client = to_i2c_client(dev);
>> + u8 request[6] = { ec_cdev->fan_id, EC_FAN_SPEED_DATA_SIZE,
>> + EC_FAN_DEBUG_MODE_OFF, 0, 0, 0 };
>> + int ret;
>> +
>> + ret = i2c_smbus_write_i2c_block_data(client, EC_FAN_DBG_CONTROL_CMD,
>> + sizeof(request), request);
>> + if (ret) {
>> + dev_err(dev, "Failed to turn off fan%d debug mode: %d\n",
>> + ec_cdev->fan_id, ret);
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static int qcom_ec_fan_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state)
>> +{
>> + struct qcom_ec_cooling_dev *ec_cdev = cdev->devdata;
>> + struct device *dev = ec_cdev->parent_dev;
>> + struct i2c_client *client = to_i2c_client(dev);
>> + u8 request[6] = { ec_cdev->fan_id, EC_FAN_SPEED_DATA_SIZE,
>> + EC_FAN_DEBUG_MODE_ON | EC_FAN_ON | EC_FAN_DEBUG_TYPE_PWM,
>> + 0, 0, state };
>> + int ret;
>> +
>> + ret = i2c_smbus_write_i2c_block_data(client, EC_FAN_DBG_CONTROL_CMD,
>> + sizeof(request), request);
>> + if (ret) {
>> + dev_err(dev, "Failed to set fan pwm: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + ec_cdev->state = state;
>> +
>> + return 0;
>> +}
>> +
>> +static const struct thermal_cooling_device_ops qcom_ec_thermal_ops = {
>> + .get_max_state = qcom_ec_fan_get_max_state,
>> + .get_cur_state = qcom_ec_fan_get_cur_state,
>> + .set_cur_state = qcom_ec_fan_set_cur_state,
>> +};
>> +
>> +static int qcom_ec_resume(struct device *dev)
>> +{
>> + struct i2c_client *client = to_i2c_client(dev);
>> +
>> + return i2c_smbus_write_byte_data(client, EC_MODERN_STANDBY_CMD,
>> + EC_MODERN_STANDBY_ENTER);
>> +}
>> +
>> +static int qcom_ec_suspend(struct device *dev)
>> +{
>> + struct i2c_client *client = to_i2c_client(dev);
>> +
>> + return i2c_smbus_write_byte_data(client, EC_MODERN_STANDBY_CMD,
>> + EC_MODERN_STANDBY_EXIT);
>> +}
>> +
>> +static int qcom_ec_probe(struct i2c_client *client)
>> +{
>> + struct device *dev = &client->dev;
>> + struct qcom_ec *ec;
>> + unsigned int i;
>> + int ret;
>> +
>> + ec = devm_kzalloc(dev, sizeof(*ec), GFP_KERNEL);
>> + if (!ec)
>> + return -ENOMEM;
>> +
>> + ec->client = client;
>> +
>> + ret = devm_request_threaded_irq(dev, client->irq, NULL, qcom_ec_irq,
>> + IRQF_ONESHOT, "qcom_ec", ec);
>> + if (ret < 0)
>> + return ret;
>> +
>> + i2c_set_clientdata(client, ec);
>> +
>> + ret = qcom_ec_read_fw_version(dev);
>> + if (ret < 0)
>> + return dev_err_probe(dev, ret, "Failed to read EC firmware version\n");
>> +
>> + ret = qcom_ec_sci_evt_control(dev, true);
>> + if (ret < 0)
>> + return dev_err_probe(dev, ret, "Failed to enable SCI events\n");
>> +
>> + ret = qcom_ec_thermal_capabilities(dev);
>> + if (ret < 0)
>> + return dev_err_probe(dev, ret, "Failed to read thermal capabilities\n");
>> +
>> + if (ec->thermal_cap.fan_cnt == 0) {
>> + dev_warn(dev, FW_BUG "Failed to get fan count, firmware update required\n");
>> + return 0;
>> + }
>> +
>> + ec->ec_cdev = devm_kcalloc(dev, ec->thermal_cap.fan_cnt, sizeof(*ec->ec_cdev), GFP_KERNEL);
>> + if (!ec->ec_cdev)
>> + return -ENOMEM;
>> +
>> + for (i = 0; i < ec->thermal_cap.fan_cnt; i++) {
>> + struct qcom_ec_cooling_dev *ec_cdev = &ec->ec_cdev[i];
>> + char name[EC_FAN_NAME_SIZE];
>> +
>> + scnprintf(name, sizeof(name), "qcom_ec_fan_%u", i);
>> + ec_cdev->fan_id = i + 1;
>> + ec_cdev->parent_dev = dev;
>> +
>> + ec_cdev->cdev = devm_thermal_of_cooling_device_register(dev, NULL, name, ec_cdev,
>> + &qcom_ec_thermal_ops);
>> + if (IS_ERR(ec_cdev->cdev)) {
>> + return dev_err_probe(dev, PTR_ERR(ec_cdev->cdev),
>> + "Failed to register fan%d cooling device\n", i);
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void qcom_ec_remove(struct i2c_client *client)
>> +{
>> + struct qcom_ec *ec = i2c_get_clientdata(client);
>> + struct device *dev = &client->dev;
>> + int ret;
>> +
>> + ret = qcom_ec_sci_evt_control(dev, false);
>> + if (ret < 0)
>> + dev_err(dev, "Failed to disable SCI events: %d\n", ret);
>> +
>> + for (int i = 0; i < ec->thermal_cap.fan_cnt; i++) {
>> + struct qcom_ec_cooling_dev *ec_cdev = &ec->ec_cdev[i];
>> +
>> + qcom_ec_fan_debug_mode_off(ec_cdev);
>> + }
>> +}
>> +
>> +static const struct of_device_id qcom_ec_of_match[] = {
>> + { .compatible = "qcom,hamoa-crd-ec" },
>> + {}
>> +};
>> +MODULE_DEVICE_TABLE(of, qcom_ec_of_match);
>> +
>> +static const struct i2c_device_id qcom_ec_i2c_id_table[] = {
>> + { "qcom-hamoa-ec", },
>> + {}
>> +};
>> +MODULE_DEVICE_TABLE(i2c, qcom_ec_i2c_id_table);
>> +
>> +static DEFINE_SIMPLE_DEV_PM_OPS(qcom_ec_pm_ops,
>> + qcom_ec_suspend,
>> + qcom_ec_resume);
>> +
>> +static struct i2c_driver qcom_ec_i2c_driver = {
>> + .driver = {
>> + .name = "qcom-hamoa-ec",
>> + .of_match_table = qcom_ec_of_match,
>> + .pm = &qcom_ec_pm_ops
>> + },
>> + .probe = qcom_ec_probe,
>> + .remove = qcom_ec_remove,
>> + .id_table = qcom_ec_i2c_id_table,
>> +};
>> +module_i2c_driver(qcom_ec_i2c_driver);
>> +
>> +MODULE_DESCRIPTION("QCOM Hamoa Embedded Controller");
>> +MODULE_LICENSE("GPL");
>>
>>
--
Best Regards,
Anvesh
^ permalink raw reply
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
From: Krzysztof Kozlowski @ 2026-03-30 6:38 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, linux-gpio, devicetree, linux-kernel
In-Reply-To: <095ba19f-90c9-4410-9b65-607d29413bb1@oss.qualcomm.com>
On 30/03/2026 06:56, Kathiravan Thirumoorthy wrote:
>
> On 3/26/2026 1:55 PM, Krzysztof Kozlowski wrote:
>> On Wed, Mar 25, 2026 at 01:05:15PM +0530, Kathiravan Thirumoorthy wrote:
>>> Add device tree bindings for IPQ5210 TLMM block.
>>>
>>> Signed-off-by: Kathiravan Thirumoorthy<kathiravan.thirumoorthy@oss.qualcomm.com>
>> I don't see any differences here and cover letter does not explain that.
>
> Pin control function names are made generic for some of the functions,
> so I thought I should drop it and mentioned it in the cover letter as below.
>
> Changes in v3:
> - Grouped the QUP SE pins instead of mentioning by function wise
> - Splitted the PWM functions which I messed up in V2
> - Audio primary and secondary mclk function names are expanded to avoid the
> confusion
> - Dropped the R-b tags due to the above changes
>
> Based on your comment, I understand that since there is no schematic
> changes to the binding, there is no need to drop the tag. So I have
> picked up the tags in V4.
So you dropped the tags because something changed in the "function"
property? Why would that matter for review?
I am not looking at this again.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v4 3/4] irqchip/ast2700-intc: Add KUnit tests for route resolution
From: Ryan Chen @ 2026-03-30 6:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Thomas Gleixner, Thomas Gleixner
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-aspeed,
linux-riscv, Ryan Chen
In-Reply-To: <20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com>
Add a KUnit suite for aspeed_intc0_resolve_route().
Cover invalid arguments, invalid domain/range data, connected and
disconnected mappings, and malformed upstream range cases.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
Changes in v4:
- fix warning: the frame size of 1296 bytes is larger than 1280 bytes.
Changes in v2:
- add line break before include "irq-ast2700.h"
- remove pointless newline.
- rename arm_gicv3_fwnode_read_string_array to
gicv3_fwnode_read_string_array
- add .kunitconfig file
---
drivers/irqchip/.kunitconfig | 5 +
drivers/irqchip/Kconfig | 11 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ast2700-intc0-test.c | 473 +++++++++++++++++++++++++++++++
4 files changed, 490 insertions(+)
diff --git a/drivers/irqchip/.kunitconfig b/drivers/irqchip/.kunitconfig
new file mode 100644
index 000000000000..00a12703f635
--- /dev/null
+++ b/drivers/irqchip/.kunitconfig
@@ -0,0 +1,5 @@
+CONFIG_KUNIT=y
+CONFIG_OF=y
+CONFIG_COMPILE_TEST=y
+CONFIG_ASPEED_AST2700_INTC=y
+CONFIG_ASPEED_AST2700_INTC_TEST=y
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 0156fee89b2c..143af3f30a4b 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -122,6 +122,17 @@ config ASPEED_AST2700_INTC
If unsure, say N.
+config ASPEED_AST2700_INTC_TEST
+ bool "Tests for the ASPEED AST2700 Interrupt Controller"
+ depends on ASPEED_AST2700_INTC && KUNIT=y
+ default KUNIT_ALL_TESTS
+ help
+ Enable KUnit tests for AST2700 INTC route resolution.
+ The tests exercise error handling and route selection paths.
+ This option is intended for test builds.
+
+ If unsure, say N.
+
config ATMEL_AIC_IRQ
bool
select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 62790663f982..ac04a4b97797 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -90,6 +90,7 @@ obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o
obj-$(CONFIG_LS_EXTIRQ) += irq-ls-extirq.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_ASPEED_AST2700_INTC) += irq-ast2700.o irq-ast2700-intc0.o irq-ast2700-intc1.o
+obj-$(CONFIG_ASPEED_AST2700_INTC_TEST) += irq-ast2700-intc0-test.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-intc.o
obj-$(CONFIG_STM32MP_EXTI) += irq-stm32mp-exti.o
diff --git a/drivers/irqchip/irq-ast2700-intc0-test.c b/drivers/irqchip/irq-ast2700-intc0-test.c
new file mode 100644
index 000000000000..d49784509ac7
--- /dev/null
+++ b/drivers/irqchip/irq-ast2700-intc0-test.c
@@ -0,0 +1,473 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026 Code Construct
+ */
+#include <kunit/test.h>
+
+#include "irq-ast2700.h"
+
+static void aspeed_intc0_resolve_route_bad_args(struct kunit *test)
+{
+ static const struct aspeed_intc_interrupt_range c1ranges[] = { 0 };
+ static const u32 c1outs[] = { 0 };
+ struct aspeed_intc_interrupt_range resolved;
+ const struct irq_domain c0domain = { 0 };
+ int rc;
+
+ rc = aspeed_intc0_resolve_route(NULL, 0, c1outs, 0, c1ranges, NULL);
+ KUNIT_EXPECT_EQ(test, rc, -EINVAL);
+
+ rc = aspeed_intc0_resolve_route(&c0domain, 0, c1outs,
+ ARRAY_SIZE(c1ranges), c1ranges,
+ &resolved);
+ KUNIT_EXPECT_EQ(test, rc, -ENOENT);
+
+ rc = aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs,
+ 0, c1ranges, &resolved);
+ KUNIT_EXPECT_EQ(test, rc, -ENOENT);
+}
+
+static int gicv3_fwnode_read_string_array(const struct fwnode_handle *fwnode,
+ const char *propname, const char **val, size_t nval)
+{
+ if (!propname)
+ return -EINVAL;
+
+ if (!val)
+ return 1;
+
+ if (WARN_ON(nval != 1))
+ return -EOVERFLOW;
+
+ *val = "arm,gic-v3";
+ return 1;
+}
+
+static const struct fwnode_operations arm_gicv3_fwnode_ops = {
+ .property_read_string_array = gicv3_fwnode_read_string_array,
+};
+
+static void aspeed_intc_resolve_route_invalid_c0domain(struct kunit *test)
+{
+ struct device_node intc0_node = {
+ .fwnode = { .ops = &arm_gicv3_fwnode_ops },
+ };
+ const struct irq_domain c0domain = { .fwnode = &intc0_node.fwnode };
+ static const struct aspeed_intc_interrupt_range c1ranges[] = { 0 };
+ static const u32 c1outs[] = { 0 };
+ struct aspeed_intc_interrupt_range resolved;
+ int rc;
+
+ rc = aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs,
+ ARRAY_SIZE(c1ranges), c1ranges,
+ &resolved);
+ KUNIT_EXPECT_NE(test, rc, 0);
+}
+
+static int
+aspeed_intc0_fwnode_read_string_array(const struct fwnode_handle *fwnode_handle,
+ const char *propname, const char **val,
+ size_t nval)
+{
+ if (!propname)
+ return -EINVAL;
+
+ if (!val)
+ return 1;
+
+ if (WARN_ON(nval != 1))
+ return -EOVERFLOW;
+
+ *val = "aspeed,ast2700-intc0";
+ return nval;
+}
+
+static const struct fwnode_operations intc0_fwnode_ops = {
+ .property_read_string_array = aspeed_intc0_fwnode_read_string_array,
+};
+
+static void
+aspeed_intc0_resolve_route_c1i1o1c0i1o1_connected(struct kunit *test)
+{
+ struct device_node intc0_node = {
+ .fwnode = { .ops = &intc0_fwnode_ops },
+ };
+ struct aspeed_intc_interrupt_range c1ranges[] = {
+ {
+ .start = 0,
+ .count = 1,
+ .upstream = {
+ .fwnode = &intc0_node.fwnode,
+ .param_count = 1,
+ .param = { 128 }
+ }
+ }
+ };
+ static const u32 c1outs[] = { 0 };
+ struct aspeed_intc_interrupt_range resolved;
+ struct aspeed_intc_interrupt_range intc0_ranges[] = {
+ {
+ .start = 128,
+ .count = 1,
+ .upstream = {
+ .fwnode = NULL,
+ .param_count = 0,
+ .param = { 0 },
+ }
+ }
+ };
+ struct aspeed_intc0 intc0 = {
+ .ranges = { .ranges = intc0_ranges, .nranges = ARRAY_SIZE(intc0_ranges), }
+ };
+ const struct irq_domain c0domain = {
+ .host_data = &intc0,
+ .fwnode = &intc0_node.fwnode
+ };
+ int rc;
+
+ rc = aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs,
+ ARRAY_SIZE(c1ranges), c1ranges,
+ &resolved);
+ KUNIT_EXPECT_EQ(test, rc, 0);
+ KUNIT_EXPECT_EQ(test, resolved.start, 0);
+ KUNIT_EXPECT_EQ(test, resolved.count, 1);
+ KUNIT_EXPECT_EQ(test, resolved.upstream.param[0], 128);
+}
+
+static void
+aspeed_intc0_resolve_route_c1i1o1c0i1o1_disconnected(struct kunit *test)
+{
+ struct device_node intc0_node = {
+ .fwnode = { .ops = &intc0_fwnode_ops },
+ };
+ struct aspeed_intc_interrupt_range c1ranges[] = {
+ {
+ .start = 0,
+ .count = 1,
+ .upstream = {
+ .fwnode = &intc0_node.fwnode,
+ .param_count = 1,
+ .param = { 128 }
+ }
+ }
+ };
+ static const u32 c1outs[] = { 0 };
+ struct aspeed_intc_interrupt_range resolved;
+ struct aspeed_intc_interrupt_range intc0_ranges[] = {
+ {
+ .start = 129,
+ .count = 1,
+ .upstream = {
+ .fwnode = NULL,
+ .param_count = 0,
+ .param = { 0 },
+ }
+ }
+ };
+ struct aspeed_intc0 intc0 = {
+ .ranges = {
+ .ranges = intc0_ranges,
+ .nranges = ARRAY_SIZE(intc0_ranges),
+ }
+ };
+ const struct irq_domain c0domain = {
+ .host_data = &intc0,
+ .fwnode = &intc0_node.fwnode
+ };
+ int rc;
+
+ rc = aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs,
+ ARRAY_SIZE(c1ranges), c1ranges,
+ &resolved);
+ KUNIT_EXPECT_NE(test, rc, 0);
+}
+
+static void aspeed_intc0_resolve_route_c1i1o1mc0i1o1(struct kunit *test)
+{
+ struct device_node intc0_node = {
+ .fwnode = { .ops = &intc0_fwnode_ops },
+ };
+ struct aspeed_intc_interrupt_range c1ranges[] = {
+ {
+ .start = 0,
+ .count = 1,
+ .upstream = {
+ .fwnode = &intc0_node.fwnode,
+ .param_count = 1,
+ .param = { 480 }
+ }
+ }
+ };
+ static const u32 c1outs[] = { 0 };
+ struct aspeed_intc_interrupt_range resolved;
+ struct aspeed_intc_interrupt_range intc0_ranges[] = {
+ {
+ .start = 192,
+ .count = 1,
+ .upstream = {
+ .fwnode = NULL,
+ .param_count = 0,
+ .param = { 0 },
+ }
+ }
+ };
+ struct aspeed_intc0 intc0 = {
+ .ranges = {
+ .ranges = intc0_ranges,
+ .nranges = ARRAY_SIZE(intc0_ranges),
+ }
+ };
+ const struct irq_domain c0domain = {
+ .host_data = &intc0,
+ .fwnode = &intc0_node.fwnode
+ };
+ int rc;
+
+ rc = aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs,
+ ARRAY_SIZE(c1ranges), c1ranges,
+ &resolved);
+ KUNIT_EXPECT_EQ(test, rc, 0);
+ KUNIT_EXPECT_EQ(test, resolved.start, 0);
+ KUNIT_EXPECT_EQ(test, resolved.count, 1);
+ KUNIT_EXPECT_EQ(test, resolved.upstream.param[0], 480);
+}
+
+static void aspeed_intc0_resolve_route_c1i2o2mc0i1o1(struct kunit *test)
+{
+ struct device_node intc0_node = {
+ .fwnode = { .ops = &intc0_fwnode_ops },
+ };
+ struct aspeed_intc_interrupt_range c1ranges[] = {
+ {
+ .start = 0,
+ .count = 1,
+ .upstream = {
+ .fwnode = &intc0_node.fwnode,
+ .param_count = 1,
+ .param = { 480 }
+ }
+ },
+ {
+ .start = 1,
+ .count = 1,
+ .upstream = {
+ .fwnode = &intc0_node.fwnode,
+ .param_count = 1,
+ .param = { 510 }
+ }
+ }
+ };
+ static const u32 c1outs[] = { 1 };
+ struct aspeed_intc_interrupt_range resolved;
+ static struct aspeed_intc_interrupt_range intc0_ranges[] = {
+ {
+ .start = 208,
+ .count = 1,
+ .upstream = {
+ .fwnode = NULL,
+ .param_count = 0,
+ .param = { 0 },
+ }
+ }
+ };
+ struct aspeed_intc0 intc0 = {
+ .ranges = {
+ .ranges = intc0_ranges,
+ .nranges = ARRAY_SIZE(intc0_ranges),
+ }
+ };
+ const struct irq_domain c0domain = {
+ .host_data = &intc0,
+ .fwnode = &intc0_node.fwnode
+ };
+ int rc;
+
+ rc = aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs,
+ ARRAY_SIZE(c1ranges), c1ranges,
+ &resolved);
+ KUNIT_EXPECT_EQ(test, rc, 0);
+ KUNIT_EXPECT_EQ(test, resolved.start, 1);
+ KUNIT_EXPECT_EQ(test, resolved.count, 1);
+ KUNIT_EXPECT_EQ(test, resolved.upstream.param[0], 510);
+}
+
+static void aspeed_intc0_resolve_route_c1i1o1mc0i2o1(struct kunit *test)
+{
+ struct device_node intc0_node = {
+ .fwnode = { .ops = &intc0_fwnode_ops },
+ };
+ struct aspeed_intc_interrupt_range c1ranges[] = {
+ {
+ .start = 0,
+ .count = 1,
+ .upstream = {
+ .fwnode = &intc0_node.fwnode,
+ .param_count = 1,
+ .param = { 510 }
+ }
+ },
+ };
+ static const u32 c1outs[] = { 0 };
+ struct aspeed_intc_interrupt_range resolved;
+ static struct aspeed_intc_interrupt_range intc0_ranges[] = {
+ {
+ .start = 192,
+ .count = 1,
+ .upstream = {
+ .fwnode = NULL,
+ .param_count = 0,
+ .param = {0},
+ }
+ },
+ {
+ .start = 208,
+ .count = 1,
+ .upstream = {
+ .fwnode = NULL,
+ .param_count = 0,
+ .param = {0},
+ }
+ }
+ };
+ struct aspeed_intc0 intc0 = {
+ .ranges = {
+ .ranges = intc0_ranges,
+ .nranges = ARRAY_SIZE(intc0_ranges),
+ }
+ };
+ const struct irq_domain c0domain = {
+ .host_data = &intc0,
+ .fwnode = &intc0_node.fwnode
+ };
+ int rc;
+
+ rc = aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs,
+ ARRAY_SIZE(c1ranges), c1ranges,
+ &resolved);
+ KUNIT_EXPECT_EQ(test, rc, 0);
+ KUNIT_EXPECT_EQ(test, resolved.start, 0);
+ KUNIT_EXPECT_EQ(test, resolved.count, 1);
+ KUNIT_EXPECT_EQ(test, resolved.upstream.param[0], 510);
+}
+
+static void aspeed_intc0_resolve_route_c1i1o2mc0i1o1_invalid(struct kunit *test)
+{
+ struct device_node intc0_node = {
+ .fwnode = { .ops = &intc0_fwnode_ops },
+ };
+ struct aspeed_intc_interrupt_range c1ranges[] = {
+ {
+ .start = 0,
+ .count = 1,
+ .upstream = {
+ .fwnode = &intc0_node.fwnode,
+ .param_count = 1,
+ .param = { 480 }
+ }
+ }
+ };
+ static const u32 c1outs[] = {
+ AST2700_INTC_INVALID_ROUTE, 0
+ };
+ struct aspeed_intc_interrupt_range resolved;
+ struct aspeed_intc_interrupt_range intc0_ranges[] = {
+ {
+ .start = 192,
+ .count = 1,
+ .upstream = {
+ .fwnode = NULL,
+ .param_count = 0,
+ .param = { 0 },
+ }
+ }
+ };
+ struct aspeed_intc0 intc0 = {
+ .ranges = {
+ .ranges = intc0_ranges,
+ .nranges = ARRAY_SIZE(intc0_ranges),
+ }
+ };
+ const struct irq_domain c0domain = {
+ .host_data = &intc0,
+ .fwnode = &intc0_node.fwnode
+ };
+ int rc;
+
+ rc = aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs,
+ ARRAY_SIZE(c1ranges), c1ranges,
+ &resolved);
+ KUNIT_EXPECT_EQ(test, rc, 1);
+ KUNIT_EXPECT_EQ(test, resolved.start, 0);
+ KUNIT_EXPECT_EQ(test, resolved.count, 1);
+ KUNIT_EXPECT_EQ(test, resolved.upstream.param[0], 480);
+}
+
+static void
+aspeed_intc0_resolve_route_c1i1o1mc0i1o1_bad_range_upstream(struct kunit *test)
+{
+ struct device_node intc0_node = {
+ .fwnode = { .ops = &intc0_fwnode_ops },
+ };
+ struct aspeed_intc_interrupt_range c1ranges[] = {
+ {
+ .start = 0,
+ .count = 1,
+ .upstream = {
+ .fwnode = &intc0_node.fwnode,
+ .param_count = 0,
+ .param = { 0 }
+ }
+ }
+ };
+ static const u32 c1outs[] = { 0 };
+ struct aspeed_intc_interrupt_range resolved;
+ struct aspeed_intc_interrupt_range intc0_ranges[] = {
+ {
+ .start = 0,
+ .count = 0,
+ .upstream = {
+ .fwnode = NULL,
+ .param_count = 0,
+ .param = { 0 },
+ }
+ }
+ };
+ struct aspeed_intc0 intc0 = {
+ .ranges = {
+ .ranges = intc0_ranges,
+ .nranges = ARRAY_SIZE(intc0_ranges),
+ }
+ };
+ const struct irq_domain c0domain = {
+ .host_data = &intc0,
+ .fwnode = &intc0_node.fwnode
+ };
+ int rc;
+
+ rc = aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs,
+ ARRAY_SIZE(c1ranges), c1ranges,
+ &resolved);
+ KUNIT_EXPECT_NE(test, rc, 0);
+}
+
+static struct kunit_case ast2700_intc0_test_cases[] = {
+ KUNIT_CASE(aspeed_intc0_resolve_route_bad_args),
+ KUNIT_CASE(aspeed_intc_resolve_route_invalid_c0domain),
+ KUNIT_CASE(aspeed_intc0_resolve_route_c1i1o1c0i1o1_connected),
+ KUNIT_CASE(aspeed_intc0_resolve_route_c1i1o1c0i1o1_disconnected),
+ KUNIT_CASE(aspeed_intc0_resolve_route_c1i1o1mc0i1o1),
+ KUNIT_CASE(aspeed_intc0_resolve_route_c1i2o2mc0i1o1),
+ KUNIT_CASE(aspeed_intc0_resolve_route_c1i1o1mc0i2o1),
+ KUNIT_CASE(aspeed_intc0_resolve_route_c1i1o2mc0i1o1_invalid),
+ KUNIT_CASE(aspeed_intc0_resolve_route_c1i1o1mc0i1o1_bad_range_upstream),
+ {},
+};
+
+static struct kunit_suite ast2700_intc0_test_suite = {
+ .name = "ast2700-intc0",
+ .test_cases = ast2700_intc0_test_cases,
+};
+
+kunit_test_suite(ast2700_intc0_test_suite);
+
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related
* [PATCH v4 2/4] irqchip/ast2700-intc: Add AST2700-A2 support
From: Ryan Chen @ 2026-03-30 6:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Thomas Gleixner, Thomas Gleixner
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-aspeed,
linux-riscv, Ryan Chen
In-Reply-To: <20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com>
The AST2700 interrupt fabric is shared by multiple integrated processors
(PSP/SSP/TSP/BootMCU), each with its own interrupt controller and its own
devicetree view of the system. As a result, interrupt routing cannot be
treated as fixed: the valid route for a peripheral interrupt depends on
which processor is consuming it.
The INTC0 driver models this by creating a hierarchical irqdomain under
the upstream interrupt controller selected by the interrupt-parent
property in the devicetree. Information derived from this relationship
is incorporated into the route resolution logic for the controller.
The INTC1 driver implements the banked INTM-fed controller and forwards
interrupts toward INTC0, without embedding assumptions about the final
destination processor.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
Changes in v2:
- remove typedef u32 aspeed_intc_output_t
- modify #include <asm-generic/errno.h> to <linux/err.h>
- add newline after include "irq-ast2700.h"
- make defines tabular
- Struct declarations should align the struct member names in a table
- modify raw_spinlock_irqsave() to raw_spin_lock()
- use u32 ier replace mask/unmask
- remove pointless line break
- refine aspeed_intc0_routes, aspeed_intc1_routes array
- remove range_contains_element(), use in_range32()
- remove dev_dbg()
- remove EXPORT_SYMBOL_GPL(aspeed_intc0_resolve_route);
- make irq_set_chip_and_handler() with one line
- replace magic constants to macro define
- move struct aspeed_intc0 to irq-ast2700.h
- add mcro define for upstream param
---
drivers/irqchip/Kconfig | 12 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ast2700-intc0.c | 584 ++++++++++++++++++++++++++++++++++++
drivers/irqchip/irq-ast2700-intc1.c | 282 +++++++++++++++++
drivers/irqchip/irq-ast2700.c | 106 +++++++
drivers/irqchip/irq-ast2700.h | 47 +++
6 files changed, 1032 insertions(+)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f07b00d7fef9..0156fee89b2c 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -110,6 +110,18 @@ config AL_FIC
help
Support Amazon's Annapurna Labs Fabric Interrupt Controller.
+config ASPEED_AST2700_INTC
+ bool "ASPEED AST2700 Interrupt Controller support"
+ depends on OF
+ depends on ARCH_ASPEED || COMPILE_TEST
+ select IRQ_DOMAIN_HIERARCHY
+ help
+ Enable support for the ASPEED AST2700 interrupt controller.
+ This driver handles interrupt, routing and merged interrupt
+ sources to upstream parent interrupt controllers.
+
+ If unsure, say N.
+
config ATMEL_AIC_IRQ
bool
select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 26aa3b6ec99f..62790663f982 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -89,6 +89,7 @@ obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o
obj-$(CONFIG_LS_EXTIRQ) += irq-ls-extirq.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
+obj-$(CONFIG_ASPEED_AST2700_INTC) += irq-ast2700.o irq-ast2700-intc0.o irq-ast2700-intc1.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-intc.o
obj-$(CONFIG_STM32MP_EXTI) += irq-stm32mp-exti.o
diff --git a/drivers/irqchip/irq-ast2700-intc0.c b/drivers/irqchip/irq-ast2700-intc0.c
new file mode 100644
index 000000000000..66e2fb108281
--- /dev/null
+++ b/drivers/irqchip/irq-ast2700-intc0.c
@@ -0,0 +1,584 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Aspeed AST2700 Interrupt Controller.
+ *
+ * Copyright (C) 2026 ASPEED Technology Inc.
+ */
+
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/fwnode.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/kconfig.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/overflow.h>
+#include <linux/property.h>
+#include <linux/spinlock.h>
+
+#include "irq-ast2700.h"
+
+#define INT_NUM 480
+#define INTM_NUM 50
+#define SWINT_NUM 16
+
+#define INTM_BASE (INT_NUM)
+#define SWINT_BASE (INT_NUM + INTM_NUM)
+#define INT0_NUM (INT_NUM + INTM_NUM + SWINT_NUM)
+
+#define INTC0_IN_NUM 480
+#define INTC0_ROUTE_NUM 5
+#define INTC0_INTM_NUM 50
+#define INTC0_ROUTE_BITS 3
+
+#define GIC_P2P_SPI_END 128
+#define INTC0_SWINT_OUT_BASE 144
+
+#define INTC0_SWINT_IER 0x10
+#define INTC0_SWINT_ISR 0x14
+#define INTC0_INTBANKX_IER 0x1000
+#define INTC0_INTBANK_SIZE 0x100
+#define INTC0_INTBANK_GROUPS 11
+#define INTC0_INTBANKS_PER_GRP 3
+#define INTC0_INTMX_IER 0x1b00
+#define INTC0_INTMX_ISR 0x1b04
+#define INTC0_INTMX_BANK_SIZE 0x10
+#define INTC0_INTM_BANK_NUM 3
+#define INTC0_IRQS_PER_BANK 32
+#define INTM_IRQS_PER_BANK 10
+#define INTC0_SEL_BASE 0x200
+#define INTC0_SEL_BANK_SIZE 0x4
+#define INTC0_SEL_ROUTE_SIZE 0x100
+
+static void aspeed_swint_irq_mask(struct irq_data *data)
+{
+ struct aspeed_intc0 *intc0 = irq_data_get_irq_chip_data(data);
+ int bit = data->hwirq - SWINT_BASE;
+ u32 ier;
+
+ guard(raw_spinlock)(&intc0->intc_lock);
+ ier = readl(intc0->base + INTC0_SWINT_IER) & ~BIT(bit);
+ writel(ier, intc0->base + INTC0_SWINT_IER);
+ irq_chip_mask_parent(data);
+}
+
+static void aspeed_swint_irq_unmask(struct irq_data *data)
+{
+ struct aspeed_intc0 *intc0 = irq_data_get_irq_chip_data(data);
+ int bit = data->hwirq - SWINT_BASE;
+ u32 ier;
+
+ guard(raw_spinlock)(&intc0->intc_lock);
+ ier = readl(intc0->base + INTC0_SWINT_IER) | BIT(bit);
+ writel(ier, intc0->base + INTC0_SWINT_IER);
+ irq_chip_unmask_parent(data);
+}
+
+static void aspeed_swint_irq_eoi(struct irq_data *data)
+{
+ struct aspeed_intc0 *intc0 = irq_data_get_irq_chip_data(data);
+ int bit = data->hwirq - SWINT_BASE;
+
+ writel(BIT(bit), intc0->base + INTC0_SWINT_ISR);
+ irq_chip_eoi_parent(data);
+}
+
+static struct irq_chip aspeed_swint_chip = {
+ .name = "ast2700-swint",
+ .irq_eoi = aspeed_swint_irq_eoi,
+ .irq_mask = aspeed_swint_irq_mask,
+ .irq_unmask = aspeed_swint_irq_unmask,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .flags = IRQCHIP_SET_TYPE_MASKED,
+};
+
+static void aspeed_intc0_irq_mask(struct irq_data *data)
+{
+ struct aspeed_intc0 *intc0 = irq_data_get_irq_chip_data(data);
+ int bank = (data->hwirq - INTM_BASE) / INTM_IRQS_PER_BANK;
+ int bit = (data->hwirq - INTM_BASE) % INTM_IRQS_PER_BANK;
+ u32 ier;
+
+ guard(raw_spinlock)(&intc0->intc_lock);
+ ier = readl(intc0->base + INTC0_INTMX_IER + bank * INTC0_INTMX_BANK_SIZE) & ~BIT(bit);
+ writel(ier, intc0->base + INTC0_INTMX_IER + bank * INTC0_INTMX_BANK_SIZE);
+ irq_chip_mask_parent(data);
+}
+
+static void aspeed_intc0_irq_unmask(struct irq_data *data)
+{
+ struct aspeed_intc0 *intc0 = irq_data_get_irq_chip_data(data);
+ int bank = (data->hwirq - INTM_BASE) / INTM_IRQS_PER_BANK;
+ int bit = (data->hwirq - INTM_BASE) % INTM_IRQS_PER_BANK;
+ u32 ier;
+
+ guard(raw_spinlock)(&intc0->intc_lock);
+ ier = readl(intc0->base + INTC0_INTMX_IER + bank * INTC0_INTMX_BANK_SIZE) | BIT(bit);
+ writel(ier, intc0->base + INTC0_INTMX_IER + bank * INTC0_INTMX_BANK_SIZE);
+ irq_chip_unmask_parent(data);
+}
+
+static void aspeed_intc0_irq_eoi(struct irq_data *data)
+{
+ struct aspeed_intc0 *intc0 = irq_data_get_irq_chip_data(data);
+ int bank = (data->hwirq - INTM_BASE) / INTM_IRQS_PER_BANK;
+ int bit = (data->hwirq - INTM_BASE) % INTM_IRQS_PER_BANK;
+
+ writel(BIT(bit), intc0->base + INTC0_INTMX_ISR + bank * INTC0_INTMX_BANK_SIZE);
+ irq_chip_eoi_parent(data);
+}
+
+static struct irq_chip aspeed_intm_chip = {
+ .name = "ast2700-intmerge",
+ .irq_eoi = aspeed_intc0_irq_eoi,
+ .irq_mask = aspeed_intc0_irq_mask,
+ .irq_unmask = aspeed_intc0_irq_unmask,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .flags = IRQCHIP_SET_TYPE_MASKED,
+};
+
+static struct irq_chip linear_intr_irq_chip = {
+ .name = "ast2700-int",
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .flags = IRQCHIP_SET_TYPE_MASKED,
+};
+
+static const u32 aspeed_intc0_routes[INTC0_IN_NUM / INTC0_IRQS_PER_BANK][INTC0_ROUTE_NUM] = {
+ { 0, 256, 426, AST2700_INTC_INVALID_ROUTE, AST2700_INTC_INVALID_ROUTE },
+ { 32, 288, 458, AST2700_INTC_INVALID_ROUTE, AST2700_INTC_INVALID_ROUTE },
+ { 64, 320, 490, AST2700_INTC_INVALID_ROUTE, AST2700_INTC_INVALID_ROUTE },
+ { 96, 352, 522, AST2700_INTC_INVALID_ROUTE, AST2700_INTC_INVALID_ROUTE },
+ { 128, 384, 554, 160, 176 },
+ { 129, 385, 555, 161, 177 },
+ { 130, 386, 556, 162, 178 },
+ { 131, 387, 557, 163, 179 },
+ { 132, 388, 558, 164, 180 },
+ { 133, 544, 714, 165, 181 },
+ { 134, 545, 715, 166, 182 },
+ { 135, 546, 706, 167, 183 },
+ { 136, 547, 707, 168, 184 },
+ { 137, 548, 708, 169, 185 },
+ { 138, 549, 709, 170, 186 },
+};
+
+static const u32 aspeed_intc0_intm_routes[INTC0_INTM_NUM / INTM_IRQS_PER_BANK] = {
+ 192, 416, 586, 208, 224
+};
+
+static int resolve_input_from_child_ranges(const struct aspeed_intc0 *intc0,
+ const struct aspeed_intc_interrupt_range *range,
+ u32 outpin, u32 *input)
+{
+ u32 offset, base;
+
+ if (!in_range32(outpin, range->start, range->count))
+ return -ENOENT;
+
+ if (range->upstream.param_count == 0)
+ return -EINVAL;
+
+ base = range->upstream.param[ASPEED_INTC_RANGES_BASE];
+ offset = outpin - range->start;
+ if (check_add_overflow(base, offset, input)) {
+ dev_warn(intc0->dev, "%s: Arithmetic overflow for input derivation: %u + %u\n",
+ __func__, base, offset);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int resolve_parent_range_for_output(const struct aspeed_intc0 *intc0,
+ const struct fwnode_handle *parent,
+ u32 output,
+ struct aspeed_intc_interrupt_range *resolved)
+{
+ for (size_t i = 0; i < intc0->ranges.nranges; i++) {
+ struct aspeed_intc_interrupt_range range =
+ intc0->ranges.ranges[i];
+
+ if (!in_range32(output, range.start, range.count))
+ continue;
+
+ if (range.upstream.fwnode != parent)
+ continue;
+
+ if (resolved) {
+ resolved->start = output;
+ resolved->count = 1;
+ resolved->upstream = range.upstream;
+ resolved->upstream.param[ASPEED_INTC_RANGES_COUNT] +=
+ output - range.start;
+ }
+
+ return 0;
+ }
+
+ return -ENOENT;
+}
+
+static int resolve_parent_route_for_input(const struct aspeed_intc0 *intc0,
+ const struct fwnode_handle *parent, u32 input,
+ struct aspeed_intc_interrupt_range *resolved)
+{
+ int rc = -ENOENT;
+ u32 c0o;
+
+ if (input < INT_NUM) {
+ static_assert(INTC0_ROUTE_NUM < INT_MAX, "Broken cast");
+ for (size_t i = 0; rc == -ENOENT && i < INTC0_ROUTE_NUM; i++) {
+ c0o = aspeed_intc0_routes[input / INTC0_IRQS_PER_BANK][i];
+ if (c0o == AST2700_INTC_INVALID_ROUTE)
+ continue;
+
+ if (input < GIC_P2P_SPI_END)
+ c0o += input % INTC0_IRQS_PER_BANK;
+
+ rc = resolve_parent_range_for_output(intc0, parent, c0o, resolved);
+ if (!rc)
+ return (int)i;
+ }
+ } else if (input < (INT_NUM + INTM_NUM)) {
+ c0o = aspeed_intc0_intm_routes[(input - INT_NUM) / INTM_IRQS_PER_BANK];
+ c0o += ((input - INT_NUM) % INTM_IRQS_PER_BANK);
+ return resolve_parent_range_for_output(intc0, parent, c0o, resolved);
+ } else if (input < (INT_NUM + INTM_NUM + SWINT_NUM)) {
+ c0o = input - SWINT_BASE + INTC0_SWINT_OUT_BASE;
+ return resolve_parent_range_for_output(intc0, parent, c0o, resolved);
+ } else {
+ return -ENOENT;
+ }
+
+ return rc;
+}
+
+/**
+ * aspeed_intc0_resolve_route - Determine the necessary interrupt output at intc1
+ * @c0domain: The pointer to intc0's irq_domain
+ * @nc1outs: The number of valid intc1 outputs available for the input
+ * @c1outs: The array of available intc1 output indices for the input
+ * @nc1ranges: The number of interrupt range entries for intc1
+ * @c1ranges: The array of configured intc1 interrupt ranges
+ * @resolved: The fully resolved range entry after applying the resolution
+ * algorithm
+ *
+ * Returns: The intc1 route index associated with the intc1 output identified in
+ * @resolved on success. Otherwise, a negative errno value.
+ *
+ * The AST2700 interrupt architecture allows any peripheral interrupt source
+ * to be routed to one of up to four processors running in the SoC. A processor
+ * binding a driver for a peripheral that requests an interrupt is (without
+ * further design and effort) the destination for the requested interrupt.
+ *
+ * Routing a peripheral interrupt to its destination processor requires
+ * coordination between INTC0 on the CPU die and one or more INTC1 instances.
+ * At least one INTC1 instance exists in the SoC on the IO-die, however up
+ * to two more instances may be integrated via LTPI (LVDS Tunneling Protocol
+ * & Interface).
+ *
+ * Between the multiple destinations, various route constraints, and the
+ * devicetree binding design, some information that's needed at INTC1 instances
+ * to route inbound interrupts correctly to the destination processor is only
+ * available at INTC0.
+ *
+ * aspeed_intc0_resolve_route() is to be invoked by INTC1 driver instances to
+ * perform the route resolution. The implementation in INTC0 allows INTC0 to
+ * encapsulate the information used to perform route selection, and provides it
+ * with an opportunity to apply policy as part of the selection process. Such
+ * policy may, for instance, choose to de-prioritise some interrupts destined
+ * for the PSP (Primary Service Processor) GIC.
+ */
+int aspeed_intc0_resolve_route(const struct irq_domain *c0domain, size_t nc1outs,
+ const u32 *c1outs, size_t nc1ranges,
+ const struct aspeed_intc_interrupt_range *c1ranges,
+ struct aspeed_intc_interrupt_range *resolved)
+{
+ struct fwnode_handle *parent_fwnode;
+ struct aspeed_intc0 *intc0;
+ int ret;
+
+ if (!c0domain || !resolved)
+ return -EINVAL;
+
+ if (nc1outs > INT_MAX)
+ return -EINVAL;
+
+ if (nc1outs == 0 || nc1ranges == 0)
+ return -ENOENT;
+
+ if (!fwnode_device_is_compatible(c0domain->fwnode, "aspeed,ast2700-intc0"))
+ return -ENODEV;
+
+ intc0 = c0domain->host_data;
+ if (!intc0)
+ return -EINVAL;
+
+ parent_fwnode = of_fwnode_handle(intc0->parent);
+
+ for (size_t i = 0; i < nc1outs; i++) {
+ u32 c1o = c1outs[i];
+
+ if (c1o == AST2700_INTC_INVALID_ROUTE)
+ continue;
+
+ for (size_t j = 0; j < nc1ranges; j++) {
+ struct aspeed_intc_interrupt_range c1r = c1ranges[j];
+ u32 input;
+
+ /*
+ * Range match for intc1 output pin
+ *
+ * Assume a failed match is still a match for the purpose of testing,
+ * saves a bunch of mess in the test fixtures
+ */
+ if (!(c0domain == irq_find_matching_fwspec(&c1r.upstream,
+ c0domain->bus_token) ||
+ IS_ENABLED(CONFIG_ASPEED_AST2700_INTC_TEST)))
+ continue;
+
+ ret = resolve_input_from_child_ranges(intc0, &c1r, c1o, &input);
+ if (ret)
+ continue;
+
+ /*
+ * INTC1 should never request routes for peripheral interrupt sources
+ * directly attached to INTC0.
+ */
+ if (input < GIC_P2P_SPI_END)
+ continue;
+
+ ret = resolve_parent_route_for_input(intc0, parent_fwnode, input, NULL);
+ if (ret < 0)
+ continue;
+
+ /* Route resolution succeeded */
+ resolved->start = c1o;
+ resolved->count = 1;
+ resolved->upstream = c1r.upstream;
+ resolved->upstream.param[ASPEED_INTC_RANGES_BASE] = input;
+ /* Cast protected by prior test against nc1outs */
+ return (int)i;
+ }
+ }
+
+ return -ENOENT;
+}
+
+static int aspeed_intc0_irq_domain_map(struct irq_domain *domain,
+ unsigned int irq, irq_hw_number_t hwirq)
+{
+ if (hwirq < GIC_P2P_SPI_END)
+ irq_set_chip_and_handler(irq, &linear_intr_irq_chip, handle_level_irq);
+ else if (hwirq < INTM_BASE)
+ return -EINVAL;
+ else if (hwirq < SWINT_BASE)
+ irq_set_chip_and_handler(irq, &aspeed_intm_chip, handle_level_irq);
+ else if (hwirq < INT0_NUM)
+ irq_set_chip_and_handler(irq, &aspeed_swint_chip, handle_level_irq);
+ else
+ return -EINVAL;
+
+ irq_set_chip_data(irq, domain->host_data);
+ return 0;
+}
+
+static int aspeed_intc0_irq_domain_translate(struct irq_domain *domain,
+ struct irq_fwspec *fwspec,
+ unsigned long *hwirq,
+ unsigned int *type)
+{
+ if (fwspec->param_count != 1)
+ return -EINVAL;
+
+ *hwirq = fwspec->param[0];
+ *type = IRQ_TYPE_NONE;
+ return 0;
+}
+
+static int aspeed_intc0_irq_domain_alloc(struct irq_domain *domain,
+ unsigned int virq,
+ unsigned int nr_irqs, void *data)
+{
+ struct aspeed_intc0 *intc0 = domain->host_data;
+ struct aspeed_intc_interrupt_range resolved;
+ struct irq_fwspec *fwspec = data;
+ struct irq_fwspec parent_fwspec;
+ struct irq_chip *chip;
+ unsigned long hwirq;
+ unsigned int type;
+ int ret;
+
+ ret = aspeed_intc0_irq_domain_translate(domain, fwspec, &hwirq, &type);
+ if (ret)
+ return ret;
+
+ if (hwirq >= GIC_P2P_SPI_END && hwirq < INT_NUM)
+ return -EINVAL;
+
+ if (hwirq < INTM_BASE)
+ chip = &linear_intr_irq_chip;
+ else if (hwirq < SWINT_BASE)
+ chip = &aspeed_intm_chip;
+ else
+ chip = &aspeed_swint_chip;
+
+ ret = resolve_parent_route_for_input(intc0, domain->parent->fwnode,
+ (u32)hwirq, &resolved);
+ if (ret)
+ return ret;
+
+ parent_fwspec = resolved.upstream;
+ ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
+ &parent_fwspec);
+ if (ret)
+ return ret;
+
+ for (int i = 0; i < nr_irqs; ++i, ++hwirq, ++virq) {
+ ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip,
+ domain->host_data);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int aspeed_intc0_irq_domain_activate(struct irq_domain *domain,
+ struct irq_data *data, bool reserve)
+{
+ struct aspeed_intc0 *intc0 = irq_data_get_irq_chip_data(data);
+ unsigned long hwirq = data->hwirq;
+ int route, bank, bit;
+ u32 mask;
+
+ if (hwirq >= INT0_NUM)
+ return -EINVAL;
+
+ if (in_range32(hwirq, INTM_BASE, INTM_NUM + SWINT_NUM))
+ return 0;
+
+ bank = hwirq / INTC0_IRQS_PER_BANK;
+ bit = hwirq % INTC0_IRQS_PER_BANK;
+ mask = BIT(bit);
+
+ route = resolve_parent_route_for_input(intc0, intc0->local->parent->fwnode,
+ hwirq, NULL);
+ if (route < 0)
+ return route;
+
+ guard(raw_spinlock)(&intc0->intc_lock);
+ for (int i = 0; i < INTC0_ROUTE_BITS; i++) {
+ void __iomem *sel = intc0->base + INTC0_SEL_BASE +
+ (bank * INTC0_SEL_BANK_SIZE) +
+ (INTC0_SEL_ROUTE_SIZE * i);
+ u32 reg = readl(sel);
+
+ if (route & BIT(i))
+ reg |= mask;
+ else
+ reg &= ~mask;
+
+ writel(reg, sel);
+ if (readl(sel) != reg)
+ return -EACCES;
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops aspeed_intc0_irq_domain_ops = {
+ .translate = aspeed_intc0_irq_domain_translate,
+ .activate = aspeed_intc0_irq_domain_activate,
+ .alloc = aspeed_intc0_irq_domain_alloc,
+ .free = irq_domain_free_irqs_common,
+ .map = aspeed_intc0_irq_domain_map,
+};
+
+static void aspeed_intc0_disable_swint(struct aspeed_intc0 *intc0)
+{
+ writel(0, intc0->base + INTC0_SWINT_IER);
+}
+
+static void aspeed_intc0_disable_intbank(struct aspeed_intc0 *intc0)
+{
+ for (int i = 0; i < INTC0_INTBANK_GROUPS; i++) {
+ for (int j = 0; j < INTC0_INTBANKS_PER_GRP; j++) {
+ u32 base = INTC0_INTBANKX_IER +
+ (INTC0_INTBANK_SIZE * i) +
+ (INTC0_INTMX_BANK_SIZE * j);
+
+ writel(0, intc0->base + base);
+ }
+ }
+}
+
+static void aspeed_intc0_disable_intm(struct aspeed_intc0 *intc0)
+{
+ for (int i = 0; i < INTC0_INTM_BANK_NUM; i++)
+ writel(0, intc0->base + INTC0_INTMX_IER + (INTC0_INTMX_BANK_SIZE * i));
+}
+
+static int aspeed_intc0_probe(struct platform_device *pdev,
+ struct device_node *parent)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct irq_domain *parent_domain;
+ struct aspeed_intc0 *intc0;
+ int ret;
+
+ if (!parent) {
+ pr_err("missing parent interrupt node\n");
+ return -ENODEV;
+ }
+
+ intc0 = devm_kzalloc(&pdev->dev, sizeof(*intc0), GFP_KERNEL);
+ if (!intc0)
+ return -ENOMEM;
+
+ intc0->dev = &pdev->dev;
+ intc0->parent = parent;
+ intc0->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(intc0->base))
+ return PTR_ERR(intc0->base);
+
+ aspeed_intc0_disable_swint(intc0);
+ aspeed_intc0_disable_intbank(intc0);
+ aspeed_intc0_disable_intm(intc0);
+
+ raw_spin_lock_init(&intc0->intc_lock);
+
+ parent_domain = irq_find_host(parent);
+ if (!parent_domain) {
+ pr_err("unable to obtain parent domain\n");
+ return -ENODEV;
+ }
+
+ if (!of_device_is_compatible(parent, "arm,gic-v3"))
+ return -ENODEV;
+
+ intc0->local = irq_domain_create_hierarchy(parent_domain, 0, INT0_NUM,
+ of_fwnode_handle(node),
+ &aspeed_intc0_irq_domain_ops,
+ intc0);
+ if (!intc0->local)
+ return -ENOMEM;
+
+ ret = aspeed_intc_populate_ranges(&pdev->dev, &intc0->ranges);
+ if (ret < 0) {
+ irq_domain_remove(intc0->local);
+ return ret;
+ }
+
+ return 0;
+}
+
+IRQCHIP_PLATFORM_DRIVER_BEGIN(ast2700_intc0)
+IRQCHIP_MATCH("aspeed,ast2700-intc0", aspeed_intc0_probe)
+IRQCHIP_PLATFORM_DRIVER_END(ast2700_intc0)
diff --git a/drivers/irqchip/irq-ast2700-intc1.c b/drivers/irqchip/irq-ast2700-intc1.c
new file mode 100644
index 000000000000..09b9d5d743e6
--- /dev/null
+++ b/drivers/irqchip/irq-ast2700-intc1.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Aspeed AST2700 Interrupt Controller.
+ *
+ * Copyright (C) 2026 ASPEED Technology Inc.
+ */
+
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/spinlock.h>
+
+#include "irq-ast2700.h"
+
+#define INTC1_IER 0x100
+#define INTC1_ISR 0x104
+#define INTC1_BANK_SIZE 0x10
+#define INTC1_SEL_BASE 0x80
+#define INTC1_SEL_BANK_SIZE 0x4
+#define INTC1_SEL_ROUTE_SIZE 0x20
+#define INTC1_IRQS_PER_BANK 32
+#define INTC1_BANK_NUM 6
+#define INTC1_ROUTE_NUM 7
+#define INTC1_IN_NUM 192
+#define INTC1_BOOTMCU_ROUTE 6
+#define INTC1_ROUTE_SELECTOR_BITS 3
+#define INTC1_ROUTE_IRQS_PER_GROUP 32
+#define INTC1_ROUTE_SHIFT 5
+
+struct aspeed_intc1 {
+ struct device *dev;
+ void __iomem *base;
+ raw_spinlock_t intc_lock;
+ struct irq_domain *local;
+ struct irq_domain *upstream;
+ struct aspeed_intc_interrupt_ranges ranges;
+};
+
+static void aspeed_intc1_disable_int(struct aspeed_intc1 *intc1)
+{
+ for (int i = 0; i < INTC1_BANK_NUM; i++)
+ writel(0, intc1->base + INTC1_IER + (INTC1_BANK_SIZE * i));
+}
+
+static void aspeed_intc1_irq_handler(struct irq_desc *desc)
+{
+ struct aspeed_intc1 *intc1 = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned long bit, status;
+
+ chained_irq_enter(chip, desc);
+
+ for (int bank = 0; bank < INTC1_BANK_NUM; bank++) {
+ status = readl(intc1->base + INTC1_ISR + (INTC1_BANK_SIZE * bank));
+ if (!status)
+ continue;
+
+ for_each_set_bit(bit, &status, INTC1_IRQS_PER_BANK) {
+ generic_handle_domain_irq(intc1->local, (bank * INTC1_IRQS_PER_BANK) + bit);
+ writel(BIT(bit), intc1->base + INTC1_ISR + (INTC1_BANK_SIZE * bank));
+ }
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static void aspeed_intc1_irq_mask(struct irq_data *data)
+{
+ struct aspeed_intc1 *intc1 = irq_data_get_irq_chip_data(data);
+ int bank = data->hwirq / INTC1_IRQS_PER_BANK;
+ int bit = data->hwirq % INTC1_IRQS_PER_BANK;
+ u32 ier;
+
+ guard(raw_spinlock)(&intc1->intc_lock);
+ ier = readl(intc1->base + INTC1_IER + (INTC1_BANK_SIZE * bank)) & ~BIT(bit);
+ writel(ier, intc1->base + INTC1_IER + (INTC1_BANK_SIZE * bank));
+}
+
+static void aspeed_intc1_irq_unmask(struct irq_data *data)
+{
+ struct aspeed_intc1 *intc1 = irq_data_get_irq_chip_data(data);
+ int bank = data->hwirq / INTC1_IRQS_PER_BANK;
+ int bit = data->hwirq % INTC1_IRQS_PER_BANK;
+ u32 ier;
+
+ guard(raw_spinlock)(&intc1->intc_lock);
+ ier = readl(intc1->base + INTC1_IER + (INTC1_BANK_SIZE * bank)) | BIT(bit);
+ writel(ier, intc1->base + INTC1_IER + (INTC1_BANK_SIZE * bank));
+}
+
+static struct irq_chip aspeed_intc_chip = {
+ .name = "ASPEED INTC1",
+ .irq_mask = aspeed_intc1_irq_mask,
+ .irq_unmask = aspeed_intc1_irq_unmask,
+};
+
+static int aspeed_intc1_irq_domain_translate(struct irq_domain *domain,
+ struct irq_fwspec *fwspec,
+ unsigned long *hwirq,
+ unsigned int *type)
+{
+ if (fwspec->param_count != 1)
+ return -EINVAL;
+
+ *hwirq = fwspec->param[0];
+ *type = IRQ_TYPE_LEVEL_HIGH;
+ return 0;
+}
+
+static int aspeed_intc1_map_irq_domain(struct irq_domain *domain,
+ unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ irq_domain_set_info(domain, irq, hwirq, &aspeed_intc_chip,
+ domain->host_data, handle_level_irq, NULL, NULL);
+ return 0;
+}
+
+/*
+ * In-bound interrupts are progressively merged into one out-bound interrupt in
+ * groups of 32. Apply this fact to compress the route table in corresponding
+ * groups of 32.
+ */
+static const u32
+aspeed_intc1_routes[INTC1_IN_NUM / INTC1_ROUTE_IRQS_PER_GROUP][INTC1_ROUTE_NUM] = {
+ { 0, AST2700_INTC_INVALID_ROUTE, 10, 20, 30, 40, 50 },
+ { 1, AST2700_INTC_INVALID_ROUTE, 11, 21, 31, 41, 50 },
+ { 2, AST2700_INTC_INVALID_ROUTE, 12, 22, 32, 42, 50 },
+ { 3, AST2700_INTC_INVALID_ROUTE, 13, 23, 33, 43, 50 },
+ { 4, AST2700_INTC_INVALID_ROUTE, 14, 24, 34, 44, 50 },
+ { 5, AST2700_INTC_INVALID_ROUTE, 15, 25, 35, 45, 50 },
+};
+
+static int aspeed_intc1_irq_domain_activate(struct irq_domain *domain,
+ struct irq_data *data, bool reserve)
+{
+ struct aspeed_intc1 *intc1 = irq_data_get_irq_chip_data(data);
+ struct aspeed_intc_interrupt_range resolved;
+ int rc, bank, bit;
+ u32 mask;
+
+ if (WARN_ON_ONCE((data->hwirq >> INTC1_ROUTE_SHIFT) >= ARRAY_SIZE(aspeed_intc1_routes)))
+ return -EINVAL;
+
+ /*
+ * outpin may be an error if the upstream is the BootMCU APLIC node, or
+ * anything except a valid intc0 driver instance
+ */
+ rc = aspeed_intc0_resolve_route(intc1->upstream, INTC1_ROUTE_NUM,
+ aspeed_intc1_routes[data->hwirq >> INTC1_ROUTE_SHIFT],
+ intc1->ranges.nranges,
+ intc1->ranges.ranges, &resolved);
+ if (rc < 0) {
+ if (!fwnode_device_is_compatible(intc1->upstream->fwnode, "riscv,aplic")) {
+ dev_warn(intc1->dev,
+ "Failed to resolve interrupt route for hwirq %lu in domain %s\n",
+ data->hwirq, domain->name);
+ return rc;
+ }
+ rc = INTC1_BOOTMCU_ROUTE;
+ }
+
+ bank = data->hwirq / INTC1_IRQS_PER_BANK;
+ bit = data->hwirq % INTC1_IRQS_PER_BANK;
+ mask = BIT(bit);
+
+ guard(raw_spinlock)(&intc1->intc_lock);
+ for (int i = 0; i < INTC1_ROUTE_SELECTOR_BITS; i++) {
+ void __iomem *sel = intc1->base + INTC1_SEL_BASE +
+ (bank * INTC1_SEL_BANK_SIZE) +
+ (INTC1_SEL_ROUTE_SIZE * i);
+ u32 reg = readl(sel);
+
+ if (rc & BIT(i))
+ reg |= mask;
+ else
+ reg &= ~mask;
+
+ writel(reg, sel);
+ if (readl(sel) != reg)
+ return -EACCES;
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops aspeed_intc1_irq_domain_ops = {
+ .map = aspeed_intc1_map_irq_domain,
+ .translate = aspeed_intc1_irq_domain_translate,
+ .activate = aspeed_intc1_irq_domain_activate,
+};
+
+static void aspeed_intc1_request_interrupts(struct aspeed_intc1 *intc1)
+{
+ for (unsigned int i = 0; i < intc1->ranges.nranges; i++) {
+ struct aspeed_intc_interrupt_range *r =
+ &intc1->ranges.ranges[i];
+
+ if (intc1->upstream !=
+ irq_find_matching_fwspec(&r->upstream,
+ intc1->upstream->bus_token))
+ continue;
+
+ for (u32 k = 0; k < r->count; k++) {
+ struct of_phandle_args parent_irq;
+ int irq;
+
+ parent_irq.np = to_of_node(r->upstream.fwnode);
+ parent_irq.args_count = 1;
+ parent_irq.args[0] =
+ intc1->ranges.ranges[i].upstream.param[ASPEED_INTC_RANGES_BASE] + k;
+
+ irq = irq_create_of_mapping(&parent_irq);
+ if (!irq)
+ continue;
+
+ irq_set_chained_handler_and_data(irq,
+ aspeed_intc1_irq_handler, intc1);
+ }
+ }
+}
+
+static int aspeed_intc1_probe(struct platform_device *pdev,
+ struct device_node *parent)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct aspeed_intc1 *intc1;
+ struct irq_domain *host;
+ int ret;
+
+ if (!parent) {
+ dev_err(&pdev->dev, "missing parent interrupt node\n");
+ return -ENODEV;
+ }
+
+ if (!of_device_is_compatible(parent, "aspeed,ast2700-intc0"))
+ return -ENODEV;
+
+ host = irq_find_host(parent);
+ if (!host)
+ return -ENODEV;
+
+ intc1 = devm_kzalloc(&pdev->dev, sizeof(*intc1), GFP_KERNEL);
+ if (!intc1)
+ return -ENOMEM;
+
+ intc1->dev = &pdev->dev;
+ intc1->upstream = host;
+ intc1->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(intc1->base))
+ return PTR_ERR(intc1->base);
+
+ aspeed_intc1_disable_int(intc1);
+
+ raw_spin_lock_init(&intc1->intc_lock);
+
+ intc1->local = irq_domain_create_linear(of_fwnode_handle(node),
+ INTC1_BANK_NUM * INTC1_IRQS_PER_BANK,
+ &aspeed_intc1_irq_domain_ops, intc1);
+ if (!intc1->local)
+ return -ENOMEM;
+
+ ret = aspeed_intc_populate_ranges(&pdev->dev, &intc1->ranges);
+ if (ret < 0) {
+ irq_domain_remove(intc1->local);
+ return ret;
+ }
+
+ aspeed_intc1_request_interrupts(intc1);
+
+ return 0;
+}
+
+IRQCHIP_PLATFORM_DRIVER_BEGIN(ast2700_intc1)
+IRQCHIP_MATCH("aspeed,ast2700-intc1", aspeed_intc1_probe)
+IRQCHIP_PLATFORM_DRIVER_END(ast2700_intc1)
diff --git a/drivers/irqchip/irq-ast2700.c b/drivers/irqchip/irq-ast2700.c
new file mode 100644
index 000000000000..280657480d5f
--- /dev/null
+++ b/drivers/irqchip/irq-ast2700.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Aspeed AST2700 Interrupt Controller.
+ *
+ * Copyright (C) 2026 ASPEED Technology Inc.
+ */
+#include "irq-ast2700.h"
+
+#define ASPEED_INTC_RANGE_FIXED_CELLS 3U
+#define ASPEED_INTC_RANGE_OFF_START 0U
+#define ASPEED_INTC_RANGE_OFF_COUNT 1U
+#define ASPEED_INTC_RANGE_OFF_PHANDLE 2U
+
+/**
+ * aspeed_intc_populate_ranges
+ * @dev: Device owning the interrupt controller node.
+ * @ranges: Destination for parsed range descriptors.
+ *
+ * Return: 0 on success, negative errno on error.
+ */
+int aspeed_intc_populate_ranges(struct device *dev,
+ struct aspeed_intc_interrupt_ranges *ranges)
+{
+ struct aspeed_intc_interrupt_range *arr;
+ const __be32 *pvs, *pve;
+ struct device_node *dn;
+ int len;
+
+ if (!dev || !ranges)
+ return -EINVAL;
+
+ dn = dev->of_node;
+
+ pvs = of_get_property(dn, "aspeed,interrupt-ranges", &len);
+ if (!pvs)
+ return -EINVAL;
+
+ if (len % sizeof(__be32))
+ return -EINVAL;
+
+ /* Over-estimate the range entry count for now */
+ ranges->ranges = devm_kmalloc_array(dev,
+ len / (ASPEED_INTC_RANGE_FIXED_CELLS * sizeof(__be32)),
+ sizeof(*ranges->ranges),
+ GFP_KERNEL);
+ if (!ranges->ranges)
+ return -ENOMEM;
+
+ pve = pvs + (len / sizeof(__be32));
+ for (unsigned int i = 0; pve - pvs >= ASPEED_INTC_RANGE_FIXED_CELLS; i++) {
+ struct aspeed_intc_interrupt_range *r;
+ struct device_node *target;
+ u32 target_cells;
+
+ target = of_find_node_by_phandle(be32_to_cpu(pvs[ASPEED_INTC_RANGE_OFF_PHANDLE]));
+ if (!target)
+ return -EINVAL;
+
+ if (of_property_read_u32(target, "#interrupt-cells",
+ &target_cells)) {
+ of_node_put(target);
+ return -EINVAL;
+ }
+
+ if (!target_cells || target_cells > IRQ_DOMAIN_IRQ_SPEC_PARAMS) {
+ of_node_put(target);
+ return -EINVAL;
+ }
+
+ if (pve - pvs < ASPEED_INTC_RANGE_FIXED_CELLS + target_cells) {
+ of_node_put(target);
+ return -EINVAL;
+ }
+
+ r = &ranges->ranges[i];
+ r->start = be32_to_cpu(pvs[ASPEED_INTC_RANGE_OFF_START]);
+ r->count = be32_to_cpu(pvs[ASPEED_INTC_RANGE_OFF_COUNT]);
+
+ {
+ struct of_phandle_args args = {
+ .np = target,
+ .args_count = target_cells,
+ };
+
+ for (u32 j = 0; j < target_cells; j++)
+ args.args[j] = be32_to_cpu(pvs[ASPEED_INTC_RANGE_FIXED_CELLS + j]);
+
+ of_phandle_args_to_fwspec(target, args.args,
+ args.args_count,
+ &r->upstream);
+ }
+
+ of_node_put(target);
+ pvs += ASPEED_INTC_RANGE_FIXED_CELLS + target_cells;
+ ranges->nranges++;
+ }
+
+ /* Re-fit the range array now we know the entry count */
+ arr = devm_krealloc_array(dev, ranges->ranges, ranges->nranges,
+ sizeof(*ranges->ranges), GFP_KERNEL);
+ if (!arr)
+ return -ENOMEM;
+ ranges->ranges = arr;
+
+ return 0;
+}
diff --git a/drivers/irqchip/irq-ast2700.h b/drivers/irqchip/irq-ast2700.h
new file mode 100644
index 000000000000..544f1af4c8ab
--- /dev/null
+++ b/drivers/irqchip/irq-ast2700.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Aspeed AST2700 Interrupt Controller.
+ *
+ * Copyright (C) 2026 ASPEED Technology Inc.
+ */
+#ifndef DRIVERS_IRQCHIP_AST2700
+#define DRIVERS_IRQCHIP_AST2700
+
+#include <linux/device.h>
+#include <linux/irqdomain.h>
+
+#define AST2700_INTC_INVALID_ROUTE (~0U)
+#define ASPEED_INTC_RANGES_BASE 0U
+#define ASPEED_INTC_RANGES_COUNT 1U
+
+struct aspeed_intc_interrupt_range {
+ u32 start;
+ u32 count;
+ struct irq_fwspec upstream;
+};
+
+struct aspeed_intc_interrupt_ranges {
+ struct aspeed_intc_interrupt_range *ranges;
+ unsigned int nranges;
+};
+
+struct aspeed_intc0 {
+ struct device *dev;
+ void __iomem *base;
+ raw_spinlock_t intc_lock;
+ struct irq_domain *local;
+ struct device_node *parent;
+ struct aspeed_intc_interrupt_ranges ranges;
+};
+
+int aspeed_intc_populate_ranges(struct device *dev,
+ struct aspeed_intc_interrupt_ranges *ranges);
+
+int aspeed_intc0_resolve_route(const struct irq_domain *c0domain,
+ size_t nc1outs,
+ const u32 *c1outs,
+ size_t nc1ranges,
+ const struct aspeed_intc_interrupt_range *c1ranges,
+ struct aspeed_intc_interrupt_range *resolved);
+
+#endif
--
2.34.1
^ permalink raw reply related
* [PATCH v4 1/4] dt-bindings: interrupt-controller: Describe AST2700-A2 hardware instead of A0
From: Ryan Chen @ 2026-03-30 6:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Thomas Gleixner, Thomas Gleixner
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-aspeed,
linux-riscv, Ryan Chen
In-Reply-To: <20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com>
Introduce a new binding describing the AST2700 interrupt controller
architecture implemented in the A2 production silicon.
The AST2700 SoC has undergone multiple silicon revisions (A0, A1, A2)
prior to mass production. The interrupt architecture was substantially
reworked after the A0 revision for A1, and the A1 design is retained
unchanged in the A2 production silicon.
The existing AST2700 interrupt controller binding
("aspeed,ast2700-intc-ic")was written against the pre-production A0
design. That binding does not accurately describe the interrupt
hierarchy and routing model present in A1/A2, where interrupts can be
routed to multiple processor-local interrupt controllers (Primary
Service Processor (PSP) GIC, Secondary Service Processor (SSP)/Tertiary
Service Processor (TSP) NVICs, and BootMCU APLIC) depending on the
execution context.
Remove the binding for the pre-production A0 design in favour of the
binding for the A2 production design. There is no significant user
impact from the removal as there are no existing devicetrees in any
of Linux, u-boot or Zephyr that make use of the A0 binding.
Hardware connectivity between interrupt controllers is expressed using
the aspeed,interrupt-ranges property.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
Changes in v3:
- squash patch 5/5.
- modify wrap lines at 80 char.
- modify maintainers name and email.
- modify typo Sevice-> Service
Changes in v2:
- Describe AST2700 A0/A1/A2 design evolution.
- Drop the redundant '-ic' suffix from compatible strings.
- Expand commit message to match the series cover letter context.
- fix ascii diagram
- remove intc0 label
- remove spaces before >
- drop intc1 example
---
.../interrupt-controller/aspeed,ast2700-intc.yaml | 90 ----------
.../aspeed,ast2700-interrupt.yaml | 188 +++++++++++++++++++++
2 files changed, 188 insertions(+), 90 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
deleted file mode 100644
index 258d21fe6e35..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml
+++ /dev/null
@@ -1,90 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Aspeed AST2700 Interrupt Controller
-
-description:
- This interrupt controller hardware is second level interrupt controller that
- is hooked to a parent interrupt controller. It's useful to combine multiple
- interrupt sources into 1 interrupt to parent interrupt controller.
-
-maintainers:
- - Kevin Chen <kevin_chen@aspeedtech.com>
-
-properties:
- compatible:
- enum:
- - aspeed,ast2700-intc-ic
-
- reg:
- maxItems: 1
-
- interrupt-controller: true
-
- '#interrupt-cells':
- const: 1
- description:
- The first cell is the IRQ number, the second cell is the trigger
- type as defined in interrupt.txt in this directory.
-
- interrupts:
- minItems: 1
- maxItems: 10
- description: |
- Depend to which INTC0 or INTC1 used.
- INTC0 and INTC1 are two kinds of interrupt controller with enable and raw
- status registers for use.
- INTC0 is used to assert GIC if interrupt in INTC1 asserted.
- INTC1 is used to assert INTC0 if interrupt of modules asserted.
- +-----+ +-------+ +---------+---module0
- | GIC |---| INTC0 |--+--| INTC1_0 |---module2
- | | | | | | |---...
- +-----+ +-------+ | +---------+---module31
- |
- | +---------+---module0
- +---| INTC1_1 |---module2
- | | |---...
- | +---------+---module31
- ...
- | +---------+---module0
- +---| INTC1_5 |---module2
- | |---...
- +---------+---module31
-
-required:
- - compatible
- - reg
- - interrupt-controller
- - '#interrupt-cells'
- - interrupts
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
-
- bus {
- #address-cells = <2>;
- #size-cells = <2>;
-
- interrupt-controller@12101b00 {
- compatible = "aspeed,ast2700-intc-ic";
- reg = <0 0x12101b00 0 0x10>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml
new file mode 100644
index 000000000000..a62f0fd2435b
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml
@@ -0,0 +1,188 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-interrupt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED AST2700 Interrupt Controllers (INTC0/INTC1)
+
+description: |
+ The ASPEED AST2700 SoC integrates two interrupt controller designs:
+
+ - INTC0: Primary controller that routes interrupt sources to upstream,
+ processor-specific interrupt controllers
+
+ - INTC1: Secondary controller whose interrupt outputs feed into INTC0
+
+ The SoC contains four processors to which interrupts can be routed:
+
+ - PSP: Primary Service Processor (Cortex-A35)
+ - SSP: Secondary Service Processor (Cortex-M4)
+ - TSP: Tertiary Service Processor (Cortex-M4)
+ - BMCU: Boot MCU (a RISC-V microcontroller)
+
+ The following diagram illustrates the overall architecture of the
+ ASPEED AST2700 interrupt controllers:
+
+ +-----------+ +-----------+
+ | INTC0 | | INTC1(0) |
+ +-----------+ +-----------+
+ | Router | +-----------+ | Router |
+ | out int | +Peripheral + | out int |
+ +-----------+ | 0 0 <-+Controllers+ | INTM | +-----------+
+ |PSP GIC <-|---+ . . | +-----------+ | . . <-+Peripheral +
+ +-----------+ | . . | | . . | +Controllers+
+ +-----------+ | . . | | . . | +-----------+
+ |SSP NVIC <-|---+ . . <----------------+ . . |
+ +-----------+ | . . | | . . |
+ +-----------+ | . . <-------- | . . |
+ |TSP NVIC <-|---+ . . | | ----+ . . |
+ +-----------+ | . . | | | | O P |
+ | . . | | | +-----------+
+ | . . <---- | --------------------
+ | . . | | | +-----------+ |
+ | M N | | ---------+ INTC1(1) | |
+ +-----------+ | +-----------+ |
+ | . |
+ | +-----------+ |
+ -------------+ INTC1(N) | |
+ +-----------+ |
+ +--------------+ |
+ + BMCU APLIC <-+---------------------------------------------
+ +--------------+
+
+ INTC0 supports:
+ - 128 local peripheral interrupt inputs
+ - Fan-in from up to three INTC1 instances via banked interrupt lines (INTM)
+ - Local peripheral interrupt outputs
+ - Merged interrupt outputs
+ - Software interrupt outputs (SWINT)
+ - Configurable interrupt routes targeting the PSP, SSP, and TSP
+
+ INTC1 supports:
+ - 192 local peripheral interrupt inputs
+ - Banked interrupt outputs (INTM, 5 x 6 banks x 32 interrupts per bank)
+ - Configurable interrupt routes targeting the PSP, SSP, TSP, and BMCU
+
+ One INTC1 instance is always present, on the SoC's IO die. A further two
+ instances may be attached to the SoC's one INTC0 instance via LTPI (LVDS
+ Tunneling Protocol & Interface).
+
+ Interrupt numbering model
+ -------------------------
+ The binding uses a controller-local numbering model. Peripheral device
+ nodes use the INTCx local interrupt number (hwirq) in their 'interrupts' or
+ 'interrupts-extended' properties.
+
+ For AST2700, INTC0 exposes the following (inclusive) input ranges:
+
+ - 000..479: Independent interrupts
+ - 480..489: INTM0-INTM9
+ - 490..499: INTM10-INTM19
+ - 500..509: INTM20-INTM29
+ - 510..519: INTM30-INTM39
+ - 520..529: INTM40-INTM49
+
+ INTC0's (inclusive) output ranges are as follows:
+
+ - 000..127: 1:1 local peripheral interrupt output to PSP
+ - 144..151: Software interrupts from the SSP output to PSP
+ - 152..159: Software interrupts from the TSP output to PSP
+ - 192..201: INTM0-INTM9 banked outputs to PSP
+ - 208..217: INTM30-INTM39 banked outputs to PSP
+ - 224..233: INTM40-INTM49 banked outputs to PSP
+ - 256..383: 1:1 local peripheral interrupt output to SSP
+ - 384..393: INTM10-INTM19 banked outputs to SSP
+ - 400..407: Software interrupts from the PSP output to SSP
+ - 408..415: Software interrupts from the TSP output to SSP
+ - 426..553: 1:1 local peripheral interrupt output to TSP
+ - 554..563: INTM20-INTM29 banked outputs to TSP
+ - 570..577: Software interrupts from the PSP output to TSP
+ - 578..585: Software interrupts from the SSP output to TSP
+
+ Inputs and outputs for INTC1 instances are context-dependent. However, for the
+ first instance of INTC1, the (inclusive) output ranges are:
+
+ - 00..05: INTM0-INTM5
+ - 10..15: INTM10-INTM15
+ - 20..25: INTM20-INTM25
+ - 30..35: INTM30-INTM35
+ - 40..45: INTM40-INTM45
+ - 50..50: BootMCU
+
+maintainers:
+ - Ryan Chen <ryan_chen@aspeedtech.com>
+ - Andrew Jeffery <andrew@codeconstruct.com.au>
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2700-intc0
+ - aspeed,ast2700-intc1
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+ description: Single cell encoding the INTC local interrupt number (hwirq).
+
+ aspeed,interrupt-ranges:
+ description: |
+ Describes how ranges of controller output pins are routed to a parent
+ interrupt controller.
+
+ Each range entry is encoded as:
+
+ <out count phandle parent-specifier...>
+
+ where:
+ - out: First controller interrupt output index in the range.
+ - count: Number of consecutive controller interrupt outputs and parent
+ interrupt inputs in this range.
+ - phandle: Phandle to the parent interrupt controller node.
+ - parent-specifier: Interrupt specifier, as defined by the parent
+ interrupt controller binding.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 3
+ items:
+ description: Range descriptors with a parent interrupt specifier.
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+ - aspeed,interrupt-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ interrupt-controller@12100000 {
+ compatible = "aspeed,ast2700-intc0";
+ reg = <0x12100000 0x3b00>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ aspeed,interrupt-ranges =
+ <0 128 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <144 8 &gic GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <152 8 &gic GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <192 10 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <208 10 &gic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <224 10 &gic GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+ <256 128 &ssp_nvic 0 0>,
+ <384 10 &ssp_nvic 160 0>,
+ <400 8 &ssp_nvic 144 0>,
+ <408 8 &ssp_nvic 152 0>,
+ <426 128 &tsp_nvic 0 0>,
+ <554 10 &tsp_nvic 160 0>,
+ <570 8 &tsp_nvic 144 0>,
+ <578 8 &tsp_nvic 152 0>;
+ };
--
2.34.1
^ permalink raw reply related
* [PATCH v4 0/4] AST2700-A2 interrupt controller hierarchy and route support
From: Ryan Chen @ 2026-03-30 6:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Thomas Gleixner, Thomas Gleixner
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-aspeed,
linux-riscv, Ryan Chen
The AST2700 SoC has undergone multiple silicon revisions (A0, A1, A2)
prior to mass production.
A0 laid the ground-work with a split controller design (INTC0 and
INTC1) used for early development and bring-up. The interrupt
architecture was substantially reworked in the A1 to introduce an
explicit routing model and clearer hierarchy, though the split
controllers remained. The A1 interrupt architecture is unchanged in A2.
A2 is the production design. A0 and A1 are pre-production silicon and
are no longer intended for deployment outside of ASPEED.
The existing binding and driver were written against A0 prior to the A1
rework. The A0 design directly wired INTC1 instances to INTC0, and
INTC0 to the GIC of the Primary Service Processor (PSP, a Cortex-A35).
The A0 binding and driver therefore do not account for the alternative
destinations of the Secondary and Tertiary Service Processors (SSP,
TSP) and BootMCU, or the necessary route selection logic present in the
production design.
With the above context, this series replaces the existing binding and
driver.
It is not necessary for projects to maintain support for A0 due to its
pre-production nature, and between Linux, U-Boot and Zephyr there are
no upstream devicetree users of the current binding.
The new binding uses localised interrupt numbers and models the
hardware connectivity between interrupt controllers using the
aspeed,interrupt-ranges property. It is introduced in a new file before
the existing binding is removed in order to keep the diff readable.
The INTC0 driver creates a hierarchical irqdomain under the selected
upstream interrupt controller and implements route resolution logic.
INTC1 driver instances defer route selection to INTC0 and expose a
linear interrupt namespace to their parent.
A brief history of related submissions
--------------------------------------
Some modifications to the existing binding were sent to the lists in
the past. Due to process choices the revisions were difficult to track.
They are listed below.
The approaches took several forms but ended in the minor adjustment in
v6 being applied. This enabled use of the A1 design but requires
assumptions about platform route configuration defined in firmware.
These assumptions are removed by this current series.
* [PATCH] dt-bindings: interrupt-controller: aspeed: Refine AST2700 binding description and example
https://lore.kernel.org/all/20250714071753.2653620-1-ryan_chen@aspeedtech.com/
* [PATCH v2] dt-bindings: interrupt-controller: aspeed: Add parent node compatibles and refine documentation
https://lore.kernel.org/all/20250715024258.2304665-1-ryan_chen@aspeedtech.com/
* [PATCH v3 0/2] irqchip: aspeed: Add AST2700 INTC debugfs support and yaml update
https://lore.kernel.org/all/20250722095156.1672873-1-ryan_chen@aspeedtech.com/
* [PATCH v4 0/2] irqchip/ast2700-intc: Add AST2700 INTC debugfs support and yaml update
https://lore.kernel.org/all/20250812100830.145578-1-ryan_chen@aspeedtech.com/
* [PATCH v5 0/3] AST2700 interrupt controller hierarchy support
https://lore.kernel.org/all/20251022065507.1152071-1-ryan_chen@aspeedtech.com/
* [PATCH v6 0/1] Update correct AST2700 interrupt controller binding
https://lore.kernel.org/all/20251030060155.2342604-1-ryan_chen@aspeedtech.com/
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
Changes in v4:
- 3/4 fix warning: the frame size of 1296 bytes is larger than 1280 bytes
- Link to v3: https://lore.kernel.org/r/20260326-irqchip-v3-0-366739f57acf@aspeedtech.com
Changes in v3:
- 1/4 Squash patch 5/5 and 1/5.
- 1/4 modify wrap lines at 80 char.
- 1/4 modify maintainers name and email.
- 1/4 modify typo Sevice-> Service
- Link to v2: https://lore.kernel.org/r/20260306-irqchip-v2-0-f8512c09be63@aspeedtech.com
Changes in v2:
- Change suject to "AST2700-A2 interrupt controller hierarchy and route
support".
- Describe timeline for (pre-)production design evolution and
binding development to support the break in compatibility.
- fix "make dt_binding_check" compatible string consistance with
example.
- Split KUnit coverage out of the main driver patch.
- Link to v1: https://lore.kernel.org/r/20260205-irqchip-v1-0-b0310e06c087@aspeedtech.com
---
Ryan Chen (4):
dt-bindings: interrupt-controller: Describe AST2700-A2 hardware instead of A0
irqchip/ast2700-intc: Add AST2700-A2 support
irqchip/ast2700-intc: Add KUnit tests for route resolution
irqchip/aspeed-intc: Remove AST2700-A0 support
.../interrupt-controller/aspeed,ast2700-intc.yaml | 90 ----
.../aspeed,ast2700-interrupt.yaml | 188 +++++++
drivers/irqchip/.kunitconfig | 5 +
drivers/irqchip/Kconfig | 23 +
drivers/irqchip/Makefile | 3 +-
drivers/irqchip/irq-aspeed-intc.c | 139 -----
drivers/irqchip/irq-ast2700-intc0-test.c | 473 +++++++++++++++++
drivers/irqchip/irq-ast2700-intc0.c | 584 +++++++++++++++++++++
drivers/irqchip/irq-ast2700-intc1.c | 282 ++++++++++
drivers/irqchip/irq-ast2700.c | 106 ++++
drivers/irqchip/irq-ast2700.h | 47 ++
11 files changed, 1710 insertions(+), 230 deletions(-)
---
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
change-id: 20260205-irqchip-7eaef3674de9
Best regards,
--
Ryan Chen <ryan_chen@aspeedtech.com>
^ permalink raw reply
* Re: [PATCH] dt-bindings: power: reset: cortina,gemini-power-controller: convert to DT schema
From: Krzysztof Kozlowski @ 2026-03-30 6:36 UTC (permalink / raw)
To: Linus Walleij, Sebastian Reichel
Cc: Rob Herring (Arm), Khushal Chitturi, devicetree, linux-kernel,
linux-pm, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <CAD++jLn5qQqx5nAOWNifJcNPb00B_CtM=xF16qjB4qXGENmL9Q@mail.gmail.com>
On 29/03/2026 20:57, Linus Walleij wrote:
> On Sun, Mar 29, 2026 at 4:09 AM Sebastian Reichel <sre@kernel.org> wrote:
>
>> The problem is the node name (power-controller@4b000000), which is
>> reserved for power domains. You can keep the compatible.
>
> Ah, sweet, Khushal can you change this?
>
> I think you can use gemini-poweroff@4b000000 because
> this is pretty much a poweroff thingie.
So as I said - poweroff.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v4 4/4] irqchip/aspeed-intc: Remove AST2700-A0 support
From: Ryan Chen @ 2026-03-30 6:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Thomas Gleixner, Thomas Gleixner
Cc: linux-kernel, devicetree, linux-arm-kernel, linux-aspeed,
linux-riscv, Ryan Chen
In-Reply-To: <20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com>
The existing AST2700 interrupt controller driver
("aspeed,ast2700-intc-ic") was written against the A0 pre-production
design.
From A1 onwards (retained in the A2 production silicon), the interrupt
fabric was re-architected: interrupt routing is programmable and
interrupt outputs can be directed to multiple upstream controllers
(PSP GIC, Secondary Service Processor (SSP) NVIC, Tertiary Service
Processor (TSP) NVIC, and Boot MCU interrupt controller). This design
requires route resolution and a controller hierarchy model which the
A0 driver cannot represent.
Remove driver support for A0 in favour of the driver for the A2
production design.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
drivers/irqchip/Makefile | 1 -
drivers/irqchip/irq-aspeed-intc.c | 139 --------------------------------------
2 files changed, 140 deletions(-)
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index ac04a4b97797..3d02441b3ee6 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -92,7 +92,6 @@ obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_ASPEED_AST2700_INTC) += irq-ast2700.o irq-ast2700-intc0.o irq-ast2700-intc1.o
obj-$(CONFIG_ASPEED_AST2700_INTC_TEST) += irq-ast2700-intc0-test.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o
-obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-intc.o
obj-$(CONFIG_STM32MP_EXTI) += irq-stm32mp-exti.o
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
diff --git a/drivers/irqchip/irq-aspeed-intc.c b/drivers/irqchip/irq-aspeed-intc.c
deleted file mode 100644
index 4fb0dd8349da..000000000000
--- a/drivers/irqchip/irq-aspeed-intc.c
+++ /dev/null
@@ -1,139 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Aspeed Interrupt Controller.
- *
- * Copyright (C) 2023 ASPEED Technology Inc.
- */
-
-#include <linux/bitops.h>
-#include <linux/irq.h>
-#include <linux/irqchip.h>
-#include <linux/irqchip/chained_irq.h>
-#include <linux/irqdomain.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/io.h>
-#include <linux/spinlock.h>
-
-#define INTC_INT_ENABLE_REG 0x00
-#define INTC_INT_STATUS_REG 0x04
-#define INTC_IRQS_PER_WORD 32
-
-struct aspeed_intc_ic {
- void __iomem *base;
- raw_spinlock_t gic_lock;
- raw_spinlock_t intc_lock;
- struct irq_domain *irq_domain;
-};
-
-static void aspeed_intc_ic_irq_handler(struct irq_desc *desc)
-{
- struct aspeed_intc_ic *intc_ic = irq_desc_get_handler_data(desc);
- struct irq_chip *chip = irq_desc_get_chip(desc);
-
- chained_irq_enter(chip, desc);
-
- scoped_guard(raw_spinlock, &intc_ic->gic_lock) {
- unsigned long bit, status;
-
- status = readl(intc_ic->base + INTC_INT_STATUS_REG);
- for_each_set_bit(bit, &status, INTC_IRQS_PER_WORD) {
- generic_handle_domain_irq(intc_ic->irq_domain, bit);
- writel(BIT(bit), intc_ic->base + INTC_INT_STATUS_REG);
- }
- }
-
- chained_irq_exit(chip, desc);
-}
-
-static void aspeed_intc_irq_mask(struct irq_data *data)
-{
- struct aspeed_intc_ic *intc_ic = irq_data_get_irq_chip_data(data);
- unsigned int mask = readl(intc_ic->base + INTC_INT_ENABLE_REG) & ~BIT(data->hwirq);
-
- guard(raw_spinlock)(&intc_ic->intc_lock);
- writel(mask, intc_ic->base + INTC_INT_ENABLE_REG);
-}
-
-static void aspeed_intc_irq_unmask(struct irq_data *data)
-{
- struct aspeed_intc_ic *intc_ic = irq_data_get_irq_chip_data(data);
- unsigned int unmask = readl(intc_ic->base + INTC_INT_ENABLE_REG) | BIT(data->hwirq);
-
- guard(raw_spinlock)(&intc_ic->intc_lock);
- writel(unmask, intc_ic->base + INTC_INT_ENABLE_REG);
-}
-
-static struct irq_chip aspeed_intc_chip = {
- .name = "ASPEED INTC",
- .irq_mask = aspeed_intc_irq_mask,
- .irq_unmask = aspeed_intc_irq_unmask,
-};
-
-static int aspeed_intc_ic_map_irq_domain(struct irq_domain *domain, unsigned int irq,
- irq_hw_number_t hwirq)
-{
- irq_set_chip_and_handler(irq, &aspeed_intc_chip, handle_level_irq);
- irq_set_chip_data(irq, domain->host_data);
-
- return 0;
-}
-
-static const struct irq_domain_ops aspeed_intc_ic_irq_domain_ops = {
- .map = aspeed_intc_ic_map_irq_domain,
-};
-
-static int __init aspeed_intc_ic_of_init(struct device_node *node,
- struct device_node *parent)
-{
- struct aspeed_intc_ic *intc_ic;
- int irq, i, ret = 0;
-
- intc_ic = kzalloc_obj(*intc_ic);
- if (!intc_ic)
- return -ENOMEM;
-
- intc_ic->base = of_iomap(node, 0);
- if (!intc_ic->base) {
- pr_err("Failed to iomap intc_ic base\n");
- ret = -ENOMEM;
- goto err_free_ic;
- }
- writel(0xffffffff, intc_ic->base + INTC_INT_STATUS_REG);
- writel(0x0, intc_ic->base + INTC_INT_ENABLE_REG);
-
- intc_ic->irq_domain = irq_domain_create_linear(of_fwnode_handle(node), INTC_IRQS_PER_WORD,
- &aspeed_intc_ic_irq_domain_ops, intc_ic);
- if (!intc_ic->irq_domain) {
- ret = -ENOMEM;
- goto err_iounmap;
- }
-
- raw_spin_lock_init(&intc_ic->gic_lock);
- raw_spin_lock_init(&intc_ic->intc_lock);
-
- /* Check all the irq numbers valid. If not, unmaps all the base and frees the data. */
- for (i = 0; i < of_irq_count(node); i++) {
- irq = irq_of_parse_and_map(node, i);
- if (!irq) {
- pr_err("Failed to get irq number\n");
- ret = -EINVAL;
- goto err_iounmap;
- }
- }
-
- for (i = 0; i < of_irq_count(node); i++) {
- irq = irq_of_parse_and_map(node, i);
- irq_set_chained_handler_and_data(irq, aspeed_intc_ic_irq_handler, intc_ic);
- }
-
- return 0;
-
-err_iounmap:
- iounmap(intc_ic->base);
-err_free_ic:
- kfree(intc_ic);
- return ret;
-}
-
-IRQCHIP_DECLARE(ast2700_intc_ic, "aspeed,ast2700-intc-ic", aspeed_intc_ic_of_init);
--
2.34.1
^ permalink raw reply related
* [PATCH v2] dt-bindings: connector: add pd-disable dependency
From: Xu Yang @ 2026-03-30 6:35 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, gregkh, badhri, amitsd, kyletso
Cc: devicetree, linux-kernel, imx, linux-usb
When Power Delivery is not supported, the source is unable to obtain the
current capability from the Source PDO. As a result, typec-power-opmode
needs to be added to advertise such capability.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Fixes: 7a4440bc0d86 ("dt-bindings: connector: Add pd-disable property")
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v2:
- add acked by tag
- DTS patch has been picked by Frank
---
Documentation/devicetree/bindings/connector/usb-connector.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml b/Documentation/devicetree/bindings/connector/usb-connector.yaml
index a00b239960a3..8ca0292490a2 100644
--- a/Documentation/devicetree/bindings/connector/usb-connector.yaml
+++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml
@@ -335,6 +335,7 @@ properties:
maximum: 100000
dependencies:
+ pd-disable: [typec-power-opmode]
sink-vdos-v1: [ sink-vdos ]
sink-vdos: [ sink-vdos-v1 ]
--
2.34.1
^ permalink raw reply related
* Re: [PATCH] dt-bindings: display: bridge: ldb: Require reg property only for i.MX6SX/8MP LDBs
From: Marco Felsch @ 2026-03-30 6:29 UTC (permalink / raw)
To: Marek Vasut
Cc: Liu Ying, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Marek Vasut, Laurentiu Palcu, dri-devel, devicetree, linux-kernel
In-Reply-To: <0d7c7403-4b77-42f3-82d6-eaf2be8e5b1e@nabladev.com>
Hi Marek,
On 26-03-29, Marek Vasut wrote:
> On 3/29/26 7:42 PM, Marco Felsch wrote:
>
> Hello Marco,
>
> > sorry for not writting back earlier, the last weeks were quite busy.
>
> Tell me about it ...
^^
> > On 26-03-29, Liu Ying wrote:
> > > LDB's parent device could be a syscon which doesn't allow a reg property
> > > to be present in it's child devices, e.g., NXP i.MX93 Media blk-ctrl
> > > has a child device NXP i.MX93 Parallel Display Format Configuration(PDFC)
> > > without a reg property(LDB is also a child device of the Media blk-ctrl).
> > > To make the LDB schema be able to describe LDBs without the reg property
> > > like i.MX93 LDB, require the reg property only for i.MX6SX/8MP LDBs.
> >
> > NACK, we want to describe the HW and from HW PoV the LDB is and was
> > always part of a syscon. This is the case for all SoCs i.MX6SX/8MP/93.
> >
> > > Fixes: 8aa2f0ac08d3 ("dt-bindings: display: bridge: ldb: Add check for reg and reg-names")
> >
> > Therefore I would just revert this patch completely.
> Last time, I pointed out the hardware is part of syscon, but as a subnode
> and therefore with reg properties. What is the problem there ?
To quote the DT spec here:
"""
The reg property describes the address of the device’s resources within
the address space defined by its parent bus.
"""
The parent bus is not the parent iomuxc (i.MX6X) nor the blk-ctrl
(i.MX8MP/93) device. Therefore this is wrong IMHO and should be dropped.
There will be no regression from driver POV since your patchset which
would add the support to parse the reg is not merged yet.
Regards,
Marco
--
#gernperDu
#CallMeByMyFirstName
Pengutronix e.K. | |
Steuerwalder Str. 21 | https://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply
* Re: [PATCH v2 02/15] firmware: qcom: Add a generic PAS service
From: Sumit Garg @ 2026-03-30 6:29 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Mukesh Ojha, linux-arm-msm, devicetree, dri-devel, freedreno,
linux-media, netdev, linux-wireless, ath12k, linux-remoteproc,
andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
sean, akhilpo, lumag, abhinav.kumar, jesszhan0024, marijn.suijten,
airlied, simona, vikash.garodia, dikshita.agarwal, bod, mchehab,
elder, andrew+netdev, davem, edumazet, kuba, pabeni, jjohnson,
mathieu.poirier, trilokkumar.soni, pavan.kondeti, jorge.ramirez,
tonyh, vignesh.viswanathan, srinivas.kandagatla, amirreza.zarrabi,
jens.wiklander, op-tee, apurupa, skare, linux-kernel, Sumit Garg
In-Reply-To: <2da6cbcc-677d-4ba8-9762-ecb47b157f21@kernel.org>
On Fri, Mar 27, 2026 at 02:39:24PM +0100, Krzysztof Kozlowski wrote:
> On 23/03/2026 13:50, Sumit Garg wrote:
> >>> +
> >>> +#include <linux/device/devres.h>
> >>> +#include <linux/firmware/qcom/qcom_pas.h>
> >>> +#include <linux/kernel.h>
> >>> +#include <linux/module.h>
> >>> +
> >>> +#include "qcom_pas.h"
> >>> +
> >>> +struct qcom_pas_ops *ops_ptr;
> >>
> >> Should this be static ?
> >
> > It was static earlier in v1. I dropped it based on earlier v1 discussion
> > with Krzysztof. Let me conclude that discussion on the other thread
> > again.
>
> The discussion was whether this should be singleton in the first place,
> not making it a global singleton.
>
> Of course it cannot be anything else than static - nothing should poke here.
Sure, I have put the static back for v3.
-Sumit
^ permalink raw reply
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