* [PATCH V10 08/13] arm: dts: imx7d: Add Root Port node and PERST property
From: Sherry Sun @ 2026-04-02 9:51 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260402095107.205439-1-sherry.sun@nxp.com>
Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts | 5 +++++
arch/arm/boot/dts/nxp/imx/imx7d.dtsi | 11 +++++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts
index a370e868cafe..0046b276b8b9 100644
--- a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts
@@ -456,10 +456,15 @@ display_out: endpoint {
};
&pcie {
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
+&pcie_port0 {
+ reset-gpios = <&extended_io 1 GPIO_ACTIVE_LOW>;
+};
+
®_1p0d {
vin-supply = <&sw2_reg>;
};
diff --git a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi
index d961c61a93af..3c5c1f2c1460 100644
--- a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi
@@ -155,6 +155,17 @@ pcie: pcie@33800000 {
reset-names = "pciephy", "apps", "turnoff";
fsl,imx7d-pcie-phy = <&pcie_phy>;
status = "disabled";
+
+ pcie_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
};
};
--
2.37.1
^ permalink raw reply related
* [PATCH V10 07/13] arm: dts: imx6sx: Add Root Port node and PERST property
From: Sherry Sun @ 2026-04-02 9:51 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260402095107.205439-1-sherry.sun@nxp.com>
Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi | 5 +++++
arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 11 +++++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi
index 3e238d8118fa..338de4d144b2 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi
@@ -282,11 +282,16 @@ codec: wm8962@1a {
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_pcie_gpio>;
status = "okay";
};
+&pcie_port0 {
+ reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+};
+
&lcdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
index aefae5a3a6be..5484c398aa37 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
@@ -1470,6 +1470,17 @@ pcie: pcie@8ffc000 {
power-domains = <&pd_disp>, <&pd_pci>;
power-domain-names = "pcie", "pcie_phy";
status = "disabled";
+
+ pcie_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
};
};
--
2.37.1
^ permalink raw reply related
* [PATCH v5 0/3] Enable mdss1 Display Port for Qualcomm lemans-ride platform
From: Mani Chandana Ballary Kuntumalla @ 2026-04-02 9:50 UTC (permalink / raw)
To: dmitry.baryshkov, marijn.suijten, swboyd, mripard, abel.vesa,
andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
jessica.zhang, abhinav.kumar, sean, airlied, simona,
alex.vinarskis
Cc: Mani Chandana Ballary Kuntumalla, linux-arm-msm, devicetree,
linux-kernel, linux-arm-kernel, freedreno, dri-devel,
quic_rajeevny, quic_vproddut, quic_riteshk
This series adds the DPTX0 and DPTX1 nodes, as a part of mdss1
on Qualcomm lemans SoC. It also enables Display Port on Qualcomm
lemans-ride and lemans-evk-ifp-mezzanine platforms.
---
This series is dependent on below series:
https://lore.kernel.org/all/20260128114853.2543416-1-quic_riteshk@quicinc.com/
Change in v5:
- Moved OPP tables inside the mdss0 and mdss0_dp0 nodes and reused them for other nodes. [Konrad]
- Added newline before subnode. [Konrad]
- Included lemans-evk-ifp-mezzanine patch: https://lore.kernel.org/lkml/20260219-enable-edp2-3-lemans-evk-mezzanine-v1-1-969316806538@oss.qualcomm.com/ [Konrad]
- Link to v4: https://lore.kernel.org/all/20260226111322.250176-1-quic_mkuntuma@quicinc.com/
Change in v4:
- Moved the OPP tables for DP and MDP one level up to make them common for both nodes. [Dmitry]
- Added an explanation for enabling dispcc1 in the commit message. [Dmitry]
- Removed unnecessary blank lines preceding 'reg'. [Konrad]
- Link to v3: https://lore.kernel.org/all/20260217071420.2240380-1-mkuntuma@qti.qualcomm.com/
Change in v3:
- Patchset v2 [1/3] got merged
https://gitlab.freedesktop.org/lumag/msm/-/commit/1338e8ae4084
- Rebased on top of linux-next and picked the latest patch from the dependent series.
- Removed additional instance of opp table [Dmitry]
- Link to v2: https://lore.kernel.org/all/20251125105622.1755651-1-quic_mkuntuma@quicinc.com/
Change in v2:
- Added fixes tag for the DP driver patch [Dmitry]
- Included below patch in this series after addressing comments [Dmitry and Konrad]
https://lore.kernel.org/all/20250925-lemans_dual-v1-1-9c371803198d@oss.qualcomm.com/
- Removed the misleading comment: "same path used twice" [Konrad]
- Removed unused label in 'display-controller' [Dmitry]
- Removed extra zeroes in dispcc1 node [Konrad]
- Enbaled dispcc1 by default in main dtsi file [Dmitry]
- Added EDP ref clock and updated dependency series.
- Link to v1: https://lore.kernel.org/all/20250926085956.2346179-1-quic_mkuntuma@quicinc.com/
---
Mani Chandana Ballary Kuntumalla (2):
arm64: dts: qcom: lemans: add mdss1 display device nodes
arm64: dts: qcom: lemans-ride: Enable mdss1 display Port
Vishnu Saini (1):
arm64: dts: qcom: lemans-evk-ifp-mezzanine: Enable mdss1 display Port
.../dts/qcom/lemans-evk-ifp-mezzanine.dtso | 74 +++++
.../boot/dts/qcom/lemans-ride-common.dtsi | 80 +++++
arch/arm64/boot/dts/qcom/lemans.dtsi | 289 ++++++++++++++++--
3 files changed, 416 insertions(+), 27 deletions(-)
--
2.34.1
^ permalink raw reply
* [PATCH V10 06/13] arm: dts: imx6qdl: Add Root Port node and PERST property
From: Sherry Sun @ 2026-04-02 9:51 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260402095107.205439-1-sherry.sun@nxp.com>
Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi | 5 +++++
arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 11 +++++++++++
arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts | 5 +++++
3 files changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
index ba29720e3f72..fe9046c03ddd 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
@@ -754,11 +754,16 @@ lvds0_out: endpoint {
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_pcie>;
status = "okay";
};
+&pcie_port0 {
+ reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+};
+
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
index 4dc2c410cf61..9438862b9927 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
@@ -302,6 +302,17 @@ pcie: pcie@1ffc000 {
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
status = "disabled";
+
+ pcie_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
aips1: bus@2000000 { /* AIPS1 */
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
index c5b220aeaefd..6b12cab7175f 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
+++ b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
@@ -45,10 +45,15 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
};
&pcie {
+ /* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
status = "okay";
};
+&pcie_port0 {
+ reset-gpios = <&max7310_c 5 GPIO_ACTIVE_LOW>;
+};
+
&sata {
status = "okay";
};
--
2.37.1
^ permalink raw reply related
* [PATCH v5 2/3] arm64: dts: qcom: lemans-ride: Enable mdss1 display Port
From: Mani Chandana Ballary Kuntumalla @ 2026-04-02 9:50 UTC (permalink / raw)
To: dmitry.baryshkov, marijn.suijten, swboyd, mripard, abel.vesa,
andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
jessica.zhang, abhinav.kumar, sean, airlied, simona,
alex.vinarskis
Cc: Mani Chandana Ballary Kuntumalla, linux-arm-msm, devicetree,
linux-kernel, linux-arm-kernel, freedreno, dri-devel,
quic_rajeevny, quic_vproddut, quic_riteshk
In-Reply-To: <20260402095003.3758176-1-quic_mkuntuma@quicinc.com>
This change enables DP controllers, DPTX0 and DPTX1 alongside
their corresponding PHYs of mdss1 which corresponds to edp2
and edp3.
Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
---
.../boot/dts/qcom/lemans-ride-common.dtsi | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
index 31bd00546d55..9b48e6134ff9 100644
--- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
@@ -154,6 +154,30 @@ dp1_connector_in: endpoint {
};
};
+ dp2-connector {
+ compatible = "dp-connector";
+ label = "eDP2";
+ type = "full-size";
+
+ port {
+ dp2_connector_in: endpoint {
+ remote-endpoint = <&mdss1_dp0_out>;
+ };
+ };
+ };
+
+ dp3-connector {
+ compatible = "dp-connector";
+ label = "eDP3";
+ type = "full-size";
+
+ port {
+ dp3_connector_in: endpoint {
+ remote-endpoint = <&mdss1_dp1_out>;
+ };
+ };
+ };
+
dp-dsi0-connector {
compatible = "dp-connector";
label = "DSI0";
@@ -613,6 +637,50 @@ &mdss0_dsi1_phy {
status = "okay";
};
+&mdss1 {
+ status = "okay";
+};
+
+&mdss1_dp0 {
+ pinctrl-0 = <&dp2_hot_plug_det>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&mdss1_dp0_out {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+ remote-endpoint = <&dp2_connector_in>;
+};
+
+&mdss1_dp0_phy {
+ vdda-phy-supply = <&vreg_l1c>;
+ vdda-pll-supply = <&vreg_l4a>;
+
+ status = "okay";
+};
+
+&mdss1_dp1 {
+ pinctrl-0 = <&dp3_hot_plug_det>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&mdss1_dp1_out {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+ remote-endpoint = <&dp3_connector_in>;
+};
+
+&mdss1_dp1_phy {
+ vdda-phy-supply = <&vreg_l1c>;
+ vdda-pll-supply = <&vreg_l4a>;
+
+ status = "okay";
+};
+
&pmm8654au_0_gpios {
gpio-line-names = "DS_EN",
"POFF_COMPLETE",
@@ -790,6 +858,18 @@ dp1_hot_plug_det: dp1-hot-plug-det-state {
bias-disable;
};
+ dp2_hot_plug_det: dp2-hot-plug-det-state {
+ pins = "gpio104";
+ function = "edp2_hot";
+ bias-disable;
+ };
+
+ dp3_hot_plug_det: dp3-hot-plug-det-state {
+ pins = "gpio103";
+ function = "edp3_hot";
+ bias-disable;
+ };
+
io_expander_intr_active: io-expander-intr-active-state {
pins = "gpio98";
function = "gpio";
--
2.34.1
^ permalink raw reply related
* [PATCH v5 3/3] arm64: dts: qcom: lemans-evk-ifp-mezzanine: Enable mdss1 display Port
From: Mani Chandana Ballary Kuntumalla @ 2026-04-02 9:50 UTC (permalink / raw)
To: dmitry.baryshkov, marijn.suijten, swboyd, mripard, abel.vesa,
andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
jessica.zhang, abhinav.kumar, sean, airlied, simona,
alex.vinarskis
Cc: Vishnu Saini, linux-arm-msm, devicetree, linux-kernel,
linux-arm-kernel, freedreno, dri-devel, quic_rajeevny,
quic_vproddut, quic_riteshk, Mani Chandana Ballary Kuntumalla
In-Reply-To: <20260402095003.3758176-1-quic_mkuntuma@quicinc.com>
From: Vishnu Saini <vishnu.saini@oss.qualcomm.com>
Enable DP controllers, DPTX0 and DPTX1 alongside
their corresponding PHYs of mdss1 which corresponds to eDP2
and eDP3.
Signed-off-by: Vishnu Saini <vishnu.saini@oss.qualcomm.com>
Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
---
.../dts/qcom/lemans-evk-ifp-mezzanine.dtso | 74 +++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
index 268fc6b05d4b..44bd9b1a1765 100644
--- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso
@@ -11,6 +11,30 @@
&{/} {
model = "Qualcomm Technologies, Inc. Lemans-evk IFP Mezzanine";
+ dp2-connector {
+ compatible = "dp-connector";
+ label = "eDP2";
+ type = "full-size";
+
+ port {
+ dp2_connector_in: endpoint {
+ remote-endpoint = <&mdss1_dp0_out>;
+ };
+ };
+ };
+
+ dp3-connector {
+ compatible = "dp-connector";
+ label = "eDP3";
+ type = "full-size";
+
+ port {
+ dp3_connector_in: endpoint {
+ remote-endpoint = <&mdss1_dp1_out>;
+ };
+ };
+ };
+
vreg_0p9: regulator-0v9 {
compatible = "regulator-fixed";
regulator-name = "VREG_0P9";
@@ -141,6 +165,44 @@ mac_addr1: mac-addr@0 {
};
};
+&mdss1 {
+ status = "okay";
+};
+
+&mdss1_dp0 {
+ pinctrl-0 = <&dp2_hot_plug_det>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&mdss1_dp1 {
+ pinctrl-0 = <&dp3_hot_plug_det>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&mdss1_dp0_out {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+ remote-endpoint = <&dp2_connector_in>;
+};
+
+&mdss1_dp1_out {
+ data-lanes = <0 1 2 3>;
+ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+ remote-endpoint = <&dp3_connector_in>;
+};
+
+&mdss1_dp0_phy {
+ status = "okay";
+};
+
+&mdss1_dp1_phy {
+ status = "okay";
+};
+
&pcie0 {
iommu-map = <0x0 &pcie_smmu 0x0 0x1>,
<0x100 &pcie_smmu 0x1 0x1>,
@@ -235,6 +297,18 @@ &serdes1 {
};
&tlmm {
+ dp2_hot_plug_det: dp2-hot-plug-det-state {
+ pins = "gpio104";
+ function = "edp2_hot";
+ bias-disable;
+ };
+
+ dp3_hot_plug_det: dp3-hot-plug-det-state {
+ pins = "gpio103";
+ function = "edp3_hot";
+ bias-disable;
+ };
+
ethernet1_default: ethernet1-default-state {
ethernet1-mdc-pins {
pins = "gpio20";
--
2.34.1
^ permalink raw reply related
* [PATCH v5 1/3] arm64: dts: qcom: lemans: add mdss1 display device nodes
From: Mani Chandana Ballary Kuntumalla @ 2026-04-02 9:50 UTC (permalink / raw)
To: dmitry.baryshkov, marijn.suijten, swboyd, mripard, abel.vesa,
andersson, konradybcio, robh, krzk+dt, conor+dt, robin.clark,
jessica.zhang, abhinav.kumar, sean, airlied, simona,
alex.vinarskis
Cc: Mani Chandana Ballary Kuntumalla, linux-arm-msm, devicetree,
linux-kernel, linux-arm-kernel, freedreno, dri-devel,
quic_rajeevny, quic_vproddut, quic_riteshk, Mahadevan P
In-Reply-To: <20260402095003.3758176-1-quic_mkuntuma@quicinc.com>
Add devicetree changes to enable second Mobile Display Subsystem (mdss1),
Display Processing Unit(DPU), Display Port(DP), Display clock controller
(dispcc1) and eDP PHYs on the Qualcomm Lemans platform.
Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 289 ++++++++++++++++++++++++---
1 file changed, 262 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index bc0ec9a80284..4e608bd6486c 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -5474,7 +5474,7 @@ mdss0_dp1: displayport-controller@af5c000 {
phys = <&mdss0_dp1_phy>;
phy-names = "dp";
- operating-points-v2 = <&dp1_opp_table>;
+ operating-points-v2 = <&dp_opp_table>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#sound-dai-cells = <0>;
@@ -5499,30 +5499,6 @@ port@1 {
mdss0_dp1_out: endpoint { };
};
};
-
- dp1_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-162000000 {
- opp-hz = /bits/ 64 <162000000>;
- required-opps = <&rpmhpd_opp_low_svs>;
- };
-
- opp-270000000 {
- opp-hz = /bits/ 64 <270000000>;
- required-opps = <&rpmhpd_opp_svs>;
- };
-
- opp-540000000 {
- opp-hz = /bits/ 64 <540000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- };
-
- opp-810000000 {
- opp-hz = /bits/ 64 <810000000>;
- required-opps = <&rpmhpd_opp_nom>;
- };
- };
};
};
@@ -7055,6 +7031,265 @@ compute-cb@3 {
};
};
+ mdss1: display-subsystem@22000000 {
+ compatible = "qcom,sa8775p-mdss";
+ reg = <0x0 0x22000000 0x0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+ resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP1_HF_AXI_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+ interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x1800 0x402>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ display-controller@22001000 {
+ compatible = "qcom,sa8775p-dpu";
+ reg = <0x0 0x22001000 0x0 0x8f000>,
+ <0x0 0x220b0000 0x0 0x3000>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP1_HF_AXI_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdss0_mdp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ interrupt-parent = <&mdss1>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu1_intf0_out: endpoint {
+ remote-endpoint = <&mdss1_dp0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dpu1_intf4_out: endpoint {
+ remote-endpoint = <&mdss1_dp1_in>;
+ };
+ };
+ };
+ };
+
+ mdss1_dp0_phy: phy@220c2a00 {
+ compatible = "qcom,sa8775p-edp-phy";
+ reg = <0x0 0x220c2a00 0x0 0x200>,
+ <0x0 0x220c2200 0x0 0xd0>,
+ <0x0 0x220c2600 0x0 0xd0>,
+ <0x0 0x220c2000 0x0 0x1c8>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_EDP_REF_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss1_dp1_phy: phy@220c5a00 {
+ compatible = "qcom,sa8775p-edp-phy";
+ reg = <0x0 0x220c5a00 0x0 0x200>,
+ <0x0 0x220c5200 0x0 0xd0>,
+ <0x0 0x220c5600 0x0 0xd0>,
+ <0x0 0x220c5000 0x0 0x1c8>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_EDP_REF_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss1_dp0: displayport-controller@22154000 {
+ compatible = "qcom,sa8775p-dp";
+ reg = <0x0 0x22154000 0x0 0x104>,
+ <0x0 0x22154200 0x0 0x0c0>,
+ <0x0 0x22155000 0x0 0x770>,
+ <0x0 0x22156000 0x0 0x09c>,
+ <0x0 0x22157000 0x0 0x09c>,
+ <0x0 0x22158000 0x0 0x09c>,
+ <0x0 0x22159000 0x0 0x09c>,
+ <0x0 0x2215a000 0x0 0x23c>,
+ <0x0 0x2215b000 0x0 0x23c>;
+
+ interrupt-parent = <&mdss1>;
+ interrupts = <12>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp0_phy 0>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>;
+ phys = <&mdss1_dp0_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss1_dp0_in: endpoint {
+ remote-endpoint = <&dpu1_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss1_dp0_out: endpoint { };
+ };
+ };
+ };
+
+ mdss1_dp1: displayport-controller@2215c000 {
+ compatible = "qcom,sa8775p-dp";
+ reg = <0x0 0x2215c000 0x0 0x104>,
+ <0x0 0x2215c200 0x0 0x0c0>,
+ <0x0 0x2215d000 0x0 0x770>,
+ <0x0 0x2215e000 0x0 0x09c>,
+ <0x0 0x2215f000 0x0 0x09c>,
+ <0x0 0x22160000 0x0 0x09c>,
+ <0x0 0x22161000 0x0 0x09c>,
+ <0x0 0x22162000 0x0 0x23c>,
+ <0x0 0x22163000 0x0 0x23c>;
+
+ interrupt-parent = <&mdss1>;
+ interrupts = <13>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel";
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp1_phy 0>,
+ <&mdss1_dp1_phy 1>,
+ <&mdss1_dp1_phy 1>;
+ phys = <&mdss1_dp1_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss1_dp1_in: endpoint {
+ remote-endpoint = <&dpu1_intf4_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss1_dp1_out: endpoint { };
+ };
+ };
+
+ };
+ };
+
dispcc1: clock-controller@22100000 {
compatible = "qcom,sa8775p-dispcc1";
reg = <0x0 0x22100000 0x0 0x20000>;
@@ -7062,13 +7297,13 @@ dispcc1: clock-controller@22100000 {
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
- <0>, <0>, <0>, <0>,
+ <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>,
+ <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>,
<0>, <0>, <0>, <0>;
power-domains = <&rpmhpd SA8775P_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
- status = "disabled";
};
ethernet1: ethernet@23000000 {
--
2.34.1
^ permalink raw reply related
* [PATCH V10 05/13] PCI: imx6: Add support for parsing the reset property in new Root Port binding
From: Sherry Sun @ 2026-04-02 9:50 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260402095107.205439-1-sherry.sun@nxp.com>
The current DT binding for pci-imx6 specifies the 'reset-gpios' property
in the host bridge node. However, the PERST# signal logically belongs to
individual Root Ports rather than the host bridge itself. This becomes
important when supporting PCIe KeyE connector and PCI power control
framework for pci-imx6 driver, which requires properties to be specified
in Root Port nodes.
With the common Root Port parsing now handled in dw_pcie_host_init(),
update the reset GPIO handling to use the parsed port list from
bridge->ports. To maintain DT backwards compatibility, fallback to the
legacy method of parsing the host bridge node if the reset property is
not present in the Root Port node (indicated by an empty ports list).
Since now the reset GPIO is obtained with GPIOD_ASIS flag, it may be in
input mode, using gpiod_direction_output() instead of
gpiod_set_value_cansleep() to ensure the reset GPIO is properly
configured as output before setting its value.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 70 +++++++++++++++++++++------
1 file changed, 55 insertions(+), 15 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 948ffb75d122..b44563309d40 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -34,6 +34,7 @@
#include <linux/pm_runtime.h>
#include "../../pci.h"
+#include "../pci-host-common.h"
#include "pcie-designware.h"
#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
@@ -150,7 +151,6 @@ struct imx_lut_data {
struct imx_pcie {
struct dw_pcie *pci;
- struct gpio_desc *reset_gpiod;
struct clk_bulk_data *clks;
int num_clks;
bool supports_clkreq;
@@ -1222,6 +1222,32 @@ static void imx_pcie_disable_device(struct pci_host_bridge *bridge,
imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev));
}
+static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie)
+{
+ struct device *dev = pcie->pci->dev;
+ struct pci_host_bridge *bridge = pcie->pci->pp.bridge;
+ struct pci_host_port *port;
+ struct gpio_desc *reset;
+
+ reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
+ if (IS_ERR(reset))
+ return PTR_ERR(reset);
+
+ if (!reset)
+ return 0;
+
+ port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+ if (!port)
+ return -ENOMEM;
+
+ port->reset = reset;
+ INIT_LIST_HEAD(&port->list);
+ list_add_tail(&port->list, &bridge->ports);
+
+ return devm_add_action_or_reset(dev, pci_host_common_delete_ports,
+ &bridge->ports);
+}
+
static void imx_pcie_vpcie_aux_disable(void *data)
{
struct regulator *vpcie_aux = data;
@@ -1231,13 +1257,22 @@ static void imx_pcie_vpcie_aux_disable(void *data)
static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool assert)
{
- if (assert) {
- gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);
- } else {
- if (imx_pcie->reset_gpiod) {
- msleep(PCIE_T_PVPERL_MS);
- gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0);
- msleep(PCIE_RESET_CONFIG_WAIT_MS);
+ struct dw_pcie *pci = imx_pcie->pci;
+ struct pci_host_bridge *bridge = pci->pp.bridge;
+ struct pci_host_port *port;
+
+ if (!bridge)
+ return;
+
+ list_for_each_entry(port, &bridge->ports, list) {
+ if (assert) {
+ gpiod_direction_output(port->reset, 1);
+ } else {
+ if (port->reset) {
+ msleep(PCIE_T_PVPERL_MS);
+ gpiod_direction_output(port->reset, 0);
+ msleep(PCIE_RESET_CONFIG_WAIT_MS);
+ }
}
}
}
@@ -1247,8 +1282,20 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct device *dev = pci->dev;
struct imx_pcie *imx_pcie = to_imx_pcie(pci);
+ struct pci_host_bridge *bridge = pp->bridge;
int ret;
+ /*
+ * For DT backward compatibility: if no Root Port nodes were parsed
+ * (indicated by empty ports list), parse reset-gpios from the host
+ * bridge node.
+ */
+ if (bridge && list_empty(&bridge->ports)) {
+ ret = imx_pcie_parse_legacy_binding(imx_pcie);
+ if (ret)
+ return ret;
+ }
+
imx_pcie_assert_perst(imx_pcie, true);
/* Keep 3.3Vaux supply enabled for the entire PCIe controller lifecycle */
@@ -1702,13 +1749,6 @@ static int imx_pcie_probe(struct platform_device *pdev)
return PTR_ERR(imx_pcie->phy_base);
}
- /* Fetch GPIOs */
- imx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
- if (IS_ERR(imx_pcie->reset_gpiod))
- return dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod),
- "unable to get reset gpio\n");
- gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset");
-
/* Fetch clocks */
imx_pcie->num_clks = devm_clk_bulk_get_all(dev, &imx_pcie->clks);
if (imx_pcie->num_clks < 0)
--
2.37.1
^ permalink raw reply related
* [PATCH V10 04/13] PCI: imx6: Assert PERST# before enabling regulators
From: Sherry Sun @ 2026-04-02 9:50 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260402095107.205439-1-sherry.sun@nxp.com>
According to the PCIe initialization requirements, PERST# signal should
be asserted before applying power to the PCIe device, and deasserted
after power and reference clock are stable.
Currently, the driver enables the vpcie3v3aux regulator in
imx_pcie_probe() before PERST# is asserted in imx_pcie_host_init(),
which violates the PCIe power sequencing requirements. However, there
is no issue so far because PERST# is requested as GPIOD_OUT_HIGH in
imx_pcie_probe(), which guarantees that PERST# is asserted before
enabling the vpcie3v3aux regulator.
This is prepare for the upcoming changes that will parse the reset
property using the new Root Port binding, which will use GPIOD_ASIS
when requesting the reset GPIO. With GPIOD_ASIS, the GPIO state is not
guaranteed, so explicit sequencing is required.
Fix the power sequencing by:
1. Moving vpcie3v3aux regulator enable from probe to
imx_pcie_host_init(), where it can be properly sequenced with PERST#.
2. Moving imx_pcie_assert_perst() before regulator and clock enable to
ensure correct ordering.
The vpcie3v3aux regulator is kept enabled for the entire PCIe controller
lifecycle and automatically disabled on device removal via devm cleanup.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 49 +++++++++++++++++++++------
1 file changed, 39 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 45d70ae7e04f..948ffb75d122 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -166,6 +166,8 @@ struct imx_pcie {
u32 tx_swing_full;
u32 tx_swing_low;
struct regulator *vpcie;
+ struct regulator *vpcie_aux;
+ bool vpcie_aux_enabled;
struct regulator *vph;
void __iomem *phy_base;
@@ -1220,6 +1222,13 @@ static void imx_pcie_disable_device(struct pci_host_bridge *bridge,
imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev));
}
+static void imx_pcie_vpcie_aux_disable(void *data)
+{
+ struct regulator *vpcie_aux = data;
+
+ regulator_disable(vpcie_aux);
+}
+
static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool assert)
{
if (assert) {
@@ -1240,6 +1249,24 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
struct imx_pcie *imx_pcie = to_imx_pcie(pci);
int ret;
+ imx_pcie_assert_perst(imx_pcie, true);
+
+ /* Keep 3.3Vaux supply enabled for the entire PCIe controller lifecycle */
+ if (imx_pcie->vpcie_aux && !imx_pcie->vpcie_aux_enabled) {
+ ret = regulator_enable(imx_pcie->vpcie_aux);
+ if (ret) {
+ dev_err(dev, "failed to enable vpcie_aux regulator: %d\n",
+ ret);
+ return ret;
+ }
+ imx_pcie->vpcie_aux_enabled = true;
+
+ ret = devm_add_action_or_reset(dev, imx_pcie_vpcie_aux_disable,
+ imx_pcie->vpcie_aux);
+ if (ret)
+ return ret;
+ }
+
if (imx_pcie->vpcie) {
ret = regulator_enable(imx_pcie->vpcie);
if (ret) {
@@ -1249,25 +1276,24 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
}
}
+ ret = imx_pcie_clk_enable(imx_pcie);
+ if (ret) {
+ dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
+ goto err_reg_disable;
+ }
+
if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) {
pp->bridge->enable_device = imx_pcie_enable_device;
pp->bridge->disable_device = imx_pcie_disable_device;
}
imx_pcie_assert_core_reset(imx_pcie);
- imx_pcie_assert_perst(imx_pcie, true);
if (imx_pcie->drvdata->init_phy)
imx_pcie->drvdata->init_phy(imx_pcie);
imx_pcie_configure_type(imx_pcie);
- ret = imx_pcie_clk_enable(imx_pcie);
- if (ret) {
- dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
- goto err_reg_disable;
- }
-
if (imx_pcie->phy) {
ret = phy_init(imx_pcie->phy);
if (ret) {
@@ -1780,9 +1806,12 @@ static int imx_pcie_probe(struct platform_device *pdev)
of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed);
imx_pcie->supports_clkreq = of_property_read_bool(node, "supports-clkreq");
- ret = devm_regulator_get_enable_optional(&pdev->dev, "vpcie3v3aux");
- if (ret < 0 && ret != -ENODEV)
- return dev_err_probe(dev, ret, "failed to enable Vaux supply\n");
+ imx_pcie->vpcie_aux = devm_regulator_get_optional(&pdev->dev, "vpcie3v3aux");
+ if (IS_ERR(imx_pcie->vpcie_aux)) {
+ if (PTR_ERR(imx_pcie->vpcie_aux) != -ENODEV)
+ return PTR_ERR(imx_pcie->vpcie_aux);
+ imx_pcie->vpcie_aux = NULL;
+ }
imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
if (IS_ERR(imx_pcie->vpcie)) {
--
2.37.1
^ permalink raw reply related
* [PATCH V10 03/13] PCI: dwc: Parse Root Port nodes in dw_pcie_host_init()
From: Sherry Sun @ 2026-04-02 9:50 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260402095107.205439-1-sherry.sun@nxp.com>
Add support for parsing Root Port child nodes in dw_pcie_host_init()
using pci_host_common_parse_ports(). This allows DWC-based drivers to
specify Root Port properties (like reset GPIOs) in individual Root Port
nodes rather than in the host bridge node.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index da152c31bb2e..f6fca984fb34 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -20,6 +20,7 @@
#include <linux/platform_device.h>
#include "../../pci.h"
+#include "../pci-host-common.h"
#include "pcie-designware.h"
static struct pci_ops dw_pcie_ops;
@@ -581,6 +582,13 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
pp->bridge = bridge;
+ /* Parse Root Port nodes if present */
+ ret = pci_host_common_parse_ports(dev, bridge);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev, "Failed to parse Root Port nodes: %d\n", ret);
+ return ret;
+ }
+
ret = dw_pcie_host_get_resources(pp);
if (ret)
return ret;
--
2.37.1
^ permalink raw reply related
* [PATCH V10 02/13] PCI: host-generic: Add common helpers for parsing Root Port properties
From: Sherry Sun @ 2026-04-02 9:50 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260402095107.205439-1-sherry.sun@nxp.com>
Introduce generic helper functions to parse Root Port device tree nodes
and extract common properties like reset GPIOs. This allows multiple
PCI host controller drivers to share the same parsing logic.
Define struct pci_host_port to hold common Root Port properties
(currently only reset GPIO descriptor) and add
pci_host_common_parse_ports() to parse Root Port nodes from device tree.
Also add the 'ports' list to struct pci_host_bridge for better maintain
parsed Root Port information.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
drivers/pci/controller/pci-host-common.c | 77 ++++++++++++++++++++++++
drivers/pci/controller/pci-host-common.h | 16 +++++
drivers/pci/probe.c | 1 +
include/linux/pci.h | 1 +
4 files changed, 95 insertions(+)
diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/controller/pci-host-common.c
index d6258c1cffe5..0fb6991dde7b 100644
--- a/drivers/pci/controller/pci-host-common.c
+++ b/drivers/pci/controller/pci-host-common.c
@@ -9,6 +9,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/gpio/consumer.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
@@ -17,6 +18,82 @@
#include "pci-host-common.h"
+/**
+ * pci_host_common_delete_ports - Cleanup function for port list
+ * @data: Pointer to the port list head
+ */
+void pci_host_common_delete_ports(void *data)
+{
+ struct list_head *ports = data;
+ struct pci_host_port *port, *tmp;
+
+ list_for_each_entry_safe(port, tmp, ports, list)
+ list_del(&port->list);
+}
+EXPORT_SYMBOL_GPL(pci_host_common_delete_ports);
+
+/**
+ * pci_host_common_parse_port - Parse a single Root Port node
+ * @dev: Device pointer
+ * @bridge: PCI host bridge
+ * @node: Device tree node of the Root Port
+ *
+ * Returns: 0 on success, negative error code on failure
+ */
+static int pci_host_common_parse_port(struct device *dev,
+ struct pci_host_bridge *bridge,
+ struct device_node *node)
+{
+ struct pci_host_port *port;
+ struct gpio_desc *reset;
+
+ reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
+ "reset", GPIOD_ASIS, "PERST#");
+ if (IS_ERR(reset))
+ return PTR_ERR(reset);
+
+ port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+ if (!port)
+ return -ENOMEM;
+
+ port->reset = reset;
+ INIT_LIST_HEAD(&port->list);
+ list_add_tail(&port->list, &bridge->ports);
+
+ return 0;
+}
+
+/**
+ * pci_host_common_parse_ports - Parse Root Port nodes from device tree
+ * @dev: Device pointer
+ * @bridge: PCI host bridge
+ *
+ * This function iterates through child nodes of the host bridge and parses
+ * Root Port properties (currently only reset GPIO).
+ *
+ * Returns: 0 on success, -ENOENT if no ports found, other negative error codes
+ * on failure
+ */
+int pci_host_common_parse_ports(struct device *dev, struct pci_host_bridge *bridge)
+{
+ int ret = -ENOENT;
+
+ for_each_available_child_of_node_scoped(dev->of_node, of_port) {
+ if (!of_node_is_type(of_port, "pci"))
+ continue;
+ ret = pci_host_common_parse_port(dev, bridge, of_port);
+ if (ret)
+ return ret;
+ }
+
+ if (ret)
+ return ret;
+
+ return devm_add_action_or_reset(dev, pci_host_common_delete_ports,
+ &bridge->ports);
+}
+EXPORT_SYMBOL_GPL(pci_host_common_parse_ports);
+
static void gen_pci_unmap_cfg(void *ptr)
{
pci_ecam_free((struct pci_config_window *)ptr);
diff --git a/drivers/pci/controller/pci-host-common.h b/drivers/pci/controller/pci-host-common.h
index b5075d4bd7eb..37714bedb625 100644
--- a/drivers/pci/controller/pci-host-common.h
+++ b/drivers/pci/controller/pci-host-common.h
@@ -12,6 +12,22 @@
struct pci_ecam_ops;
+/**
+ * struct pci_host_port - Generic Root Port properties
+ * @list: List node for linking multiple ports
+ * @reset: GPIO descriptor for PERST# signal
+ *
+ * This structure contains common properties that can be parsed from
+ * Root Port device tree nodes.
+ */
+struct pci_host_port {
+ struct list_head list;
+ struct gpio_desc *reset;
+};
+
+void pci_host_common_delete_ports(void *data);
+int pci_host_common_parse_ports(struct device *dev, struct pci_host_bridge *bridge);
+
int pci_host_common_probe(struct platform_device *pdev);
int pci_host_common_init(struct platform_device *pdev,
struct pci_host_bridge *bridge,
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 162166c2a9a8..360d4a1e9353 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -677,6 +677,7 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge)
{
INIT_LIST_HEAD(&bridge->windows);
INIT_LIST_HEAD(&bridge->dma_ranges);
+ INIT_LIST_HEAD(&bridge->ports);
/*
* We assume we can manage these PCIe features. Some systems may
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 3e6b92fdabcd..545f6ad4a8a7 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -642,6 +642,7 @@ struct pci_host_bridge {
int domain_nr;
struct list_head windows; /* resource_entry */
struct list_head dma_ranges; /* dma ranges resource list */
+ struct list_head ports; /* Root Port list (pci_host_port) */
#ifdef CONFIG_PCI_IDE
u16 nr_ide_streams; /* Max streams possibly active in @ide_stream_ida */
struct ida ide_stream_ida;
--
2.37.1
^ permalink raw reply related
* [PATCH V10 01/13] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node
From: Sherry Sun @ 2026-04-02 9:50 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260402095107.205439-1-sherry.sun@nxp.com>
Update fsl,imx6q-pcie.yaml to include the standard reset-gpios property
for the Root Port node.
The reset-gpios property is already defined in pci-bus-common.yaml for
PERST#, so use it instead of the local reset-gpio property. Keep the
existing reset-gpio property in the bridge node for backward
compatibility, but mark it as deprecated.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../bindings/pci/fsl,imx6q-pcie.yaml | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 12a01f7a5744..d1a2526f43dc 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -59,16 +59,34 @@ properties:
- const: dma
reset-gpio:
+ deprecated: true
description: Should specify the GPIO for controlling the PCI bus device
reset signal. It's not polarity aware and defaults to active-low reset
sequence (L=reset state, H=operation state) (optional required).
+ This property is deprecated, instead of referencing this property from the
+ host bridge node, use the reset-gpios property from the root port node.
reset-gpio-active-high:
+ deprecated: true
description: If present then the reset sequence using the GPIO
specified in the "reset-gpio" property is reversed (H=reset state,
L=operation state) (optional required).
+ This property is deprecated along with the reset-gpio property above, use
+ the reset-gpios property from the root port node.
type: boolean
+ pcie@0:
+ description:
+ Describe the i.MX6 PCIe Root Port.
+ type: object
+ $ref: /schemas/pci/pci-pci-bridge.yaml#
+
+ properties:
+ reg:
+ maxItems: 1
+
+ unevaluatedProperties: false
+
required:
- compatible
- reg
@@ -229,6 +247,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
+ #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pcie: pcie@1ffc000 {
@@ -255,5 +274,18 @@ examples:
<&clks IMX6QDL_CLK_LVDS1_GATE>,
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
+
+ pcie_port0: pcie@0 {
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+ };
};
...
--
2.37.1
^ permalink raw reply related
* [PATCH V10 00/13] pci-imx6: Add support for parsing the reset property in new Root Port binding
From: Sherry Sun @ 2026-04-02 9:50 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
Note: This patch set depends on my two patches [1] and [2], which do some
cleanup work on the pci-imx6 driver.
This patch set adds support for parsing the reset property in new Root Port
binding in pci-imx6 driver, similar to the implementation in the qcom pcie
driver[3].
Also introduce generic helper functions to parse Root Port device tree
nodes and extract common properties like reset GPIOs. This allows multiple
PCI host controller drivers to share the same parsing logic.
Define struct pci_host_port to hold common Root Port properties
(currently only reset GPIO descriptor) and add
pci_host_common_parse_ports() to parse Root Port nodes from device tree.
Also add the 'ports' list to struct pci_host_bridge for better maintain
parsed Root Port information.
The plan is to add the wake-gpio property to the root port in subsequent
patches. Also, the vpcie-supply property will be moved to the root port
node later based on the refactoring patch set for the PCI pwrctrl
framework[4].
The initial idea is to adopt the Manivannan’s recent PCIe M.2 KeyE
connector support patch set[5] and PCI power control framework patches[4],
and extend them to the pcie-imx6 driver. Since the new M.2/pwrctrl model is
implemented based on Root Ports and requires the pwrctrl driver to bind to
a Root Port device, we need to introduce a Root Port child node on i.MX
boards that provide an M.2 connector.
To follow a more standardized DT structure, it also makes sense to move
the reset-gpios and wake-gpios properties into the Root Port node. These
signals logically belong to the Root Port rather than the host bridge,
and placing them there aligns with the new M.2/pwrctrl model.
Regarding backward compatibility, as Frank suggested, I will not remove
the old reset-gpio property from existing DTS files to avoid function
break.
For new i.MX platforms — such as the upcoming i.MX952-evk will add
vpcie-supply, reset-gpios, and wake-gpios directly under the Root Port
node.
Therefore, driver updates are needed to support both the legacy
properties and the new standardized Root Port based layout.
[1] https://lore.kernel.org/all/20260306021247.991976-1-sherry.sun@nxp.com/
[2] https://lore.kernel.org/all/20260306030456.1032815-1-sherry.sun@nxp.com/
[3] https://lore.kernel.org/linux-pci/20250702-perst-v5-0-920b3d1f6ee1@qti.qualcomm.com/
[4] https://lore.kernel.org/linux-pci/20260115-pci-pwrctrl-rework-v5-0-9d26da3ce903@oss.qualcomm.com/
[5] https://lore.kernel.org/linux-pci/20260112-pci-m2-e-v4-0-eff84d2c6d26@oss.qualcomm.com/
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
Changes in V10:
1. Use gpiod_direction_output() instead of gpiod_set_value_cansleep() to
ensure the reset GPIO is properly configured as output before setting
its value in patch#5 as now the reset GPIO is obtained with
GPIOD_ASIS flag.
Changes in V9:
1. Improve the error handling in pci_host_common_parse_ports() as Mani suggested.
2. Move the list_empty check and the comment to imx_pcie_host_init() to make it
clear that imx_pcie_parse_legacy_binding() is a fallback as Mani suggested.
3. Export pci_host_common_delete_ports() so that it can be called by
imx_pcie_parse_legacy_binding().
Changes in V8:
1. Add back the cleanup function pci_host_common_delete_ports() to properly
handles the ports list instead of simply using pci_free_resource_list().
2. Improve the patch#4 commit message.
3. Remove the irrelevant code change in patch#4.
Changes in V7:
1. Change to use GPIOD_ASIS when requesting perst gpio as Mani suggested.
using bridge->dev.
2. Add a seperate patch to move vpcie3v3aux regulator enable from probe to
imx_pcie_host_init() and move imx_pcie_assert_perst() before regulator and
clock enable for pci-imx6.
3. Add device pointer parameter for pci_host_common_parse_port() instead of
Changes in V6:
1. Drop the pre-allocate pci_host_bridge struct changes in dw_pcie_host_init()
and imx_pcie_probe().
2. Parse Root Port nodes in dw_pcie_host_init() as Frank and Mani suggested.
3. Move the imx_pcie_parse_legacy_binding() from imx_pcie_probe() to
imx_pcie_host_init(), so that dw_pcie_host_init() parse Root Port first, if
no Root Port nodes were parsed(indicated by empty ports list), then parse
legacy binding.
4. Add device pointer parameter for pci_host_common_parse_ports().
5. Add NULL pointer check for reset gpio in imx_pcie_parse_legacy_binding().
Changes in V5:
1. Add the Root Port list(pci_host_port) to struct pci_host_bridge for better
maintain parsed Root Port information.
2. Delete the pci_host_common_delete_ports() as now the Root Port list in
pci_host_bridge can be cleared by pci_release_host_bridge_dev().
3. Change the common API pci_host_common_parse_ports() pass down struct
pci_host_bridge *.
4. Modify dw_pcie_host_init() to allow drivers to pre-allocate pci_host_bridge
struct when needed.
5. Allocate bridge early in imx_pcie_probe() to parse Root Ports.
Changes in V4:
1. Add common helpers for parsing Root Port properties in pci-host-common.c in
patch#2.
2. Call common pci_host_common_parse_ports() and pci_host_common_delete_ports()
in pci-imx6 driver.
3. Use PCIE_T_PVPERL_MS and PCIE_RESET_CONFIG_WAIT_MS instead of magic number
100 in patch#3 as Manivannan suggested.
4. Use "PERST#" instead of "PCIe reset" for the reset gpio lable in patch#3.
Changes in V3:
1. Improve the patch#2 commit message as Frank suggested.
2. Add Reviewed-by tag for patch#1.
Changes in V2:
1. Improve the patch#1 commit message as Frank suggested.
2. Also mark the reset-gpio-active-high property as deprecated in
imx6q-pcie DT binding as Rob suggested.
3. The imx_pcie_delete_ports() has been moved up so that the
imx_pcie_parse_ports() can call this helper function in error handling.
4. Keep the old reset-gpio property in the host bridge node for the
existing dts files and add comments to avoid confusion.
---
Sherry Sun (13):
dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node
PCI: host-generic: Add common helpers for parsing Root Port properties
PCI: dwc: Parse Root Port nodes in dw_pcie_host_init()
PCI: imx6: Assert PERST# before enabling regulators
PCI: imx6: Add support for parsing the reset property in new Root Port
binding
arm: dts: imx6qdl: Add Root Port node and PERST property
arm: dts: imx6sx: Add Root Port node and PERST property
arm: dts: imx7d: Add Root Port node and PERST property
arm64: dts: imx8mm: Add Root Port node and PERST property
arm64: dts: imx8mp: Add Root Port node and PERST property
arm64: dts: imx8mq: Add Root Port node and PERST property
arm64: dts: imx8dxl/qm/qxp: Add Root Port node and PERST property
arm64: dts: imx95: Add Root Port node and PERST property
.../bindings/pci/fsl,imx6q-pcie.yaml | 32 +++++
.../arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi | 5 +
arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 11 ++
.../arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts | 5 +
arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi | 5 +
arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 11 ++
arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts | 5 +
arch/arm/boot/dts/nxp/imx/imx7d.dtsi | 11 ++
.../boot/dts/freescale/imx8-ss-hsio.dtsi | 11 ++
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 5 +
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 5 +
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 11 ++
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 5 +
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 11 ++
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 10 ++
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 22 ++++
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 10 ++
.../boot/dts/freescale/imx8qm-ss-hsio.dtsi | 22 ++++
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 5 +
.../boot/dts/freescale/imx95-15x15-evk.dts | 5 +
.../boot/dts/freescale/imx95-19x19-evk.dts | 10 ++
arch/arm64/boot/dts/freescale/imx95.dtsi | 22 ++++
drivers/pci/controller/dwc/pci-imx6.c | 119 ++++++++++++++----
.../pci/controller/dwc/pcie-designware-host.c | 8 ++
drivers/pci/controller/pci-host-common.c | 77 ++++++++++++
drivers/pci/controller/pci-host-common.h | 16 +++
drivers/pci/probe.c | 1 +
include/linux/pci.h | 1 +
28 files changed, 436 insertions(+), 25 deletions(-)
--
2.37.1
^ permalink raw reply
* Re: [PATCH RFC 1/2] arm64: dts: qcom: eliza: Add display (MDSS) with Display CC
From: Krzysztof Kozlowski @ 2026-04-02 9:49 UTC (permalink / raw)
To: Konrad Dybcio, Krzysztof Kozlowski, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
In-Reply-To: <6488e6e7-726c-4f0b-a6b0-2914b04e118a@oss.qualcomm.com>
On 02/04/2026 11:42, Konrad Dybcio wrote:
> On 3/31/26 4:02 PM, Krzysztof Kozlowski wrote:
>> Add device nodes for almost entire display: MDSS, DPU, DSI, DSI PHYs,
>> DisplayPort and Display Clock Controller.
>>
>> Missing pieces are HDMI PHY and HDMI controller.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>>
>> ---
>
> [...]
>
>> + mdss_mdp: display-controller@ae01000 {
>> + compatible = "qcom,eliza-dpu";
>> + reg = <0x0 0x0ae01000 0x0 0x93000>,
>> + <0x0 0x0aeb0000 0x0 0x2008>;
>
> sz=0x3000
>
> [...]
Thanks, I will double check with spec.
>
>> + mdss_dsi0: dsi@ae94000 {
>> + compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
>
> linebreak?
>
>> + reg = <0x0 0x0ae94000 0x0 0x400>;
>> + reg-names = "dsi_ctrl";
>> +
>> + interrupts-extended = <&mdss 4>;
>> +
>> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
>> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
>> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
>> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
>> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&gcc GCC_DISP_HF_AXI_CLK>,
>> + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
>> + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
>> + <&dispcc DISP_CC_ESYNC0_CLK>,
>> + <&dispcc DISP_CC_OSC_CLK>,
>> + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
>
> Why the source clocks?
Short answer: because SM8750 binding requires it and that's the
same/derivative as indicated by compatibles.
Typical mailing list answer when people do not have any arguments: But
Kaanapali has the same!
Long answer: because that's how we represent the parent clocks in ABI
for the kernel. IOW, assigned-clocks do not work :(.
Rationale is in the 34bdf809a567ccefa1984ccda010c4b5de6c68c8 commit.
>
> [...]
>
>> + mdss_dsi0_phy: phy@ae95000 {
>> + compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";
>> + reg = <0x0 0x0ae95000 0x0 0x200>,
>> + <0x0 0x0ae95200 0x0 0x280>,
>
> sz=0x300
>
> [...]
>
>> + mdss_dp0: displayport-controller@af54000 {
>> + compatible = "qcom,eliza-dp", "qcom,sm8650-dp";
>> + reg = <0x0 0xaf54000 0x0 0x104>,
>
> please pad the addr to 8 hex digits
>
> sz=0x200
>
>> + <0x0 0xaf54200 0x0 0xc0>,
>
> sz=0x200
>
>> + <0x0 0xaf55000 0x0 0x770>,
>
> sz=0xc00
>> + <0x0 0xaf56000 0x0 0x9c>,
>
> sz=0x400
>> + <0x0 0xaf57000 0x0 0x9c>;
>
> sz=0x400
>
> Also missing regs for quad-MST (Pixel2/3 @ 0x0af5_[89]000, each 0x400-long
> and MST2/3_link @ 0x0af5_[ab]000, 0x600-long). I don't know if the DPU can
> do quad-MST but there's registers..
OK, let me look at datasheet again.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: timestamp: Add Tegra264 support
From: Jon Hunter @ 2026-04-02 9:49 UTC (permalink / raw)
To: Krzysztof Kozlowski, Suneel Garapati
Cc: dipenp, thierry.reding, krzk+dt, conor+dt, amhetre, sheetal,
kkartik, robh, pshete, timestamp, devicetree, linux-tegra,
linux-kernel
In-Reply-To: <1902fb50-ed1e-49a3-b210-cd9167824c1b@kernel.org>
On 02/04/2026 09:47, Krzysztof Kozlowski wrote:
> On 02/04/2026 10:47, Krzysztof Kozlowski wrote:
>> On Wed, Apr 01, 2026 at 09:38:29PM +0000, Suneel Garapati wrote:
>>> reg:
>>> maxItems: 1
>>> @@ -112,6 +114,7 @@ allOf:
>>> contains:
>>> enum:
>>> - nvidia,tegra234-gte-aon
>>> + - nvidia,tegra264-gte-aon
>>
>> And why exactly the slices are variable here? Explain that in commit
>> msg.
>
> s/Explain/Shortly describe/
So this is not related to slices, but indicating the
'nvidia,gpio-controller' property is required for the AON controller.
However, maybe your comment still applies and you want the commit
message to be explicit that for the AON instance the
'nvidia,gpio-controller' is needed?
Jon
--
nvpublic
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: kodiak: increase fastrpc compute-cb session slots
From: Jianping Li @ 2026-04-02 9:48 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Dmitry Baryshkov, Bjorn Andersson, konradybcio, robh, krzk+dt,
conor+dt, linux-arm-msm, devicetree, linux-kernel, Ekansh Gupta
In-Reply-To: <7b271810-c1ab-4d07-8364-e4c30588722d@oss.qualcomm.com>
On 4/1/2026 7:40 PM, Konrad Dybcio wrote:
> On 4/1/26 1:33 PM, Dmitry Baryshkov wrote:
>> On Wed, Apr 01, 2026 at 03:33:45PM +0800, Jianping Li wrote:
>>> Some workloads on Kodiak can exhaust FastRPC sessions when multiple
>>> compute clients open contexts concurrently, leading to -EBUSY failures.
>>>
>>> Describe the compute context bank with qcom,nsessions = <5> so the
>>> driver can provision enough session slots for the compute-cb instance.
>> This is a software property, so it probably should not have been added
>> to the DT in the first place. Can we replace it with the driver code,
>> allocating more sessions to the last CB?
> Nov 2025 => https://lore.kernel.org/linux-arm-msm/53644b36-2eff-4b1c-9886-591afee8b589@oss.qualcomm.com/
>
> Konrad
Received the comments you gave eariler, currentl checking them.
Thanks,
Jianping.
^ permalink raw reply
* Re: [PATCH v3 1/4] arm64: dts: qcom: sdm845-xiaomi-beryllium: Introduce framebuffer
From: Konrad Dybcio @ 2026-04-02 9:45 UTC (permalink / raw)
To: david, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sam Day, Dzmitry Sankouski,
Dmitry Baryshkov
Cc: linux-arm-msm, devicetree, linux-kernel, phone-devel, Petr Hodina
In-Reply-To: <20260401-beryllium-fb-v3-1-ec7d443402ab@ixit.cz>
On 4/1/26 10:40 PM, David Heidelberg via B4 Relay wrote:
> From: Petr Hodina <petr.hodina@protonmail.com>
>
> Add framebuffer for early console and u-boot support.
>
> Signed-off-by: Petr Hodina <petr.hodina@protonmail.com>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH RFC 1/2] arm64: dts: qcom: eliza: Add display (MDSS) with Display CC
From: Konrad Dybcio @ 2026-04-02 9:42 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
In-Reply-To: <20260331-dts-qcom-eliza-display-v1-1-856f0b66b282@oss.qualcomm.com>
On 3/31/26 4:02 PM, Krzysztof Kozlowski wrote:
> Add device nodes for almost entire display: MDSS, DPU, DSI, DSI PHYs,
> DisplayPort and Display Clock Controller.
>
> Missing pieces are HDMI PHY and HDMI controller.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>
> ---
[...]
> + mdss_mdp: display-controller@ae01000 {
> + compatible = "qcom,eliza-dpu";
> + reg = <0x0 0x0ae01000 0x0 0x93000>,
> + <0x0 0x0aeb0000 0x0 0x2008>;
sz=0x3000
[...]
> + mdss_dsi0: dsi@ae94000 {
> + compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
linebreak?
> + reg = <0x0 0x0ae94000 0x0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupts-extended = <&mdss 4>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
> + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
> + <&dispcc DISP_CC_ESYNC0_CLK>,
> + <&dispcc DISP_CC_OSC_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
Why the source clocks?
[...]
> + mdss_dsi0_phy: phy@ae95000 {
> + compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";
> + reg = <0x0 0x0ae95000 0x0 0x200>,
> + <0x0 0x0ae95200 0x0 0x280>,
sz=0x300
[...]
> + mdss_dp0: displayport-controller@af54000 {
> + compatible = "qcom,eliza-dp", "qcom,sm8650-dp";
> + reg = <0x0 0xaf54000 0x0 0x104>,
please pad the addr to 8 hex digits
sz=0x200
> + <0x0 0xaf54200 0x0 0xc0>,
sz=0x200
> + <0x0 0xaf55000 0x0 0x770>,
sz=0xc00
> + <0x0 0xaf56000 0x0 0x9c>,
sz=0x400
> + <0x0 0xaf57000 0x0 0x9c>;
sz=0x400
Also missing regs for quad-MST (Pixel2/3 @ 0x0af5_[89]000, each 0x400-long
and MST2/3_link @ 0x0af5_[ab]000, 0x600-long). I don't know if the DPU can
do quad-MST but there's registers..
Konrad
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: kodiak: increase fastrpc compute-cb session slots
From: Jianping Li @ 2026-04-02 9:41 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, konradybcio, robh, krzk+dt, conor+dt,
linux-arm-msm, devicetree, linux-kernel, Ekansh Gupta
In-Reply-To: <ejt3dzkuo76sb6jipkuae2u47kushc3vporxn3xclts445pgck@5qfcnufjljiw>
On 4/1/2026 7:33 PM, Dmitry Baryshkov wrote:
> On Wed, Apr 01, 2026 at 03:33:45PM +0800, Jianping Li wrote:
>> Some workloads on Kodiak can exhaust FastRPC sessions when multiple
>> compute clients open contexts concurrently, leading to -EBUSY failures.
>>
>> Describe the compute context bank with qcom,nsessions = <5> so the
>> driver can provision enough session slots for the compute-cb instance.
> This is a software property, so it probably should not have been added
> to the DT in the first place. Can we replace it with the driver code,
> allocating more sessions to the last CB?
Thank you for your suggestion. I will check the methods you mentioned.
Thanks,
Jianping.
>
>> Signed-off-by: Jianping Li <jianping.li@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/kodiak.dtsi | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
>> index 6079e67ea829..5bd20909f9db 100644
>> --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
>> @@ -4465,6 +4465,7 @@ compute-cb@5 {
>> compatible = "qcom,fastrpc-compute-cb";
>> reg = <5>;
>> iommus = <&apps_smmu 0x1805 0x0>;
>> + qcom,nsessions = <5>;
>> dma-coherent;
>> };
>> };
>> --
>> 2.43.0
>>
^ permalink raw reply
* [PATCH v3 11/11] drm/mxsfb/lcdif: use DRM_BRIDGE_ATTACH_NO_CONNECTOR and the bridge-connector
From: Luca Ceresoli @ 2026-04-02 9:26 UTC (permalink / raw)
To: Marek Vasut, Stefan Agner, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Liu Ying, Rob Herring,
Saravana Kannan
Cc: Damon Ding, Kory Maincent (TI.com), Hervé Codina, Hui Pu,
Ian Ray, Thomas Petazzoni, dri-devel, imx, linux-arm-kernel,
linux-kernel, devicetree, Adam Ford, Alexander Stein,
Christopher Obbard, Daniel Scally, Emanuele Ghidoli,
Fabio Estevam, Francesco Dolcini, Frieder Schrempf, Gilles Talis,
Goran Rađenović, Heiko Schocher, Josua Mayer,
Kieran Bingham, Marco Felsch, Martyn Welch, Oleksij Rempel,
Peng Fan, Richard Hu, Shengjiu Wang, Stefan Eichenberger,
Vitor Soares, Luca Ceresoli
In-Reply-To: <20260402-drm-lcdif-dbanc-v3-0-27cd247a0847@bootlin.com>
Convert this driver to DRM_BRIDGE_ATTACH_NO_CONNECTOR and to the
drm_bridge_connector framework which is the current DRM bridge best
practice.
Tested-by: Martyn Welch <martyn.welch@collabora.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # TQMa8MPxL/MBa8MPxL
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
---
Changes in v2:
- Added missing select DRM_DISPLAY_HELPER in Kconfig
- Rebased on previous patch changes
---
drivers/gpu/drm/mxsfb/Kconfig | 2 ++
drivers/gpu/drm/mxsfb/lcdif_drv.c | 16 +++++++++++++++-
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mxsfb/Kconfig b/drivers/gpu/drm/mxsfb/Kconfig
index 264e74f45554..31db7a824a93 100644
--- a/drivers/gpu/drm/mxsfb/Kconfig
+++ b/drivers/gpu/drm/mxsfb/Kconfig
@@ -33,6 +33,8 @@ config DRM_IMX_LCDIF
select DRM_GEM_DMA_HELPER
select DRM_PANEL
select DRM_PANEL_BRIDGE
+ select DRM_DISPLAY_HELPER
+ select DRM_BRIDGE_CONNECTOR
help
Choose this option if you have an LCDIFv3 LCD controller.
Those devices are found in various i.MX SoC (i.MX8MP,
diff --git a/drivers/gpu/drm/mxsfb/lcdif_drv.c b/drivers/gpu/drm/mxsfb/lcdif_drv.c
index c8ba8f9b1da8..7f07ae24e0dc 100644
--- a/drivers/gpu/drm/mxsfb/lcdif_drv.c
+++ b/drivers/gpu/drm/mxsfb/lcdif_drv.c
@@ -18,6 +18,7 @@
#include <drm/clients/drm_client_setup.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
+#include <drm/drm_bridge_connector.h>
#include <drm/drm_drv.h>
#include <drm/drm_encoder.h>
#include <drm/drm_fbdev_dma.h>
@@ -57,6 +58,7 @@ static int lcdif_attach_bridge(struct lcdif_drm_private *lcdif)
struct of_endpoint of_ep;
struct drm_bridge *bridge;
struct drm_encoder *encoder;
+ struct drm_connector *connector;
int ret;
if (!of_device_is_available(remote))
@@ -86,11 +88,23 @@ static int lcdif_attach_bridge(struct lcdif_drm_private *lcdif)
"Failed to initialize encoder for endpoint%u\n",
of_ep.id);
- ret = drm_bridge_attach(encoder, bridge, NULL, 0);
+ ret = drm_bridge_attach(encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
if (ret)
return dev_err_probe(dev, ret,
"Failed to attach bridge for endpoint%u\n",
of_ep.id);
+
+ connector = drm_bridge_connector_init(lcdif->drm, encoder);
+ if (IS_ERR(connector))
+ return dev_err_probe(dev, PTR_ERR(connector),
+ "Failed to init bridge_connector for endpoint%u\n",
+ of_ep.id);
+
+ ret = drm_connector_attach_encoder(connector, encoder);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to attach connector for endpoint%u\n",
+ of_ep.id);
}
return 0;
--
2.53.0
^ permalink raw reply related
* [PATCH v3 10/11] drm/bridge: imx8mp-hdmi-tx: switch to DRM_BRIDGE_ATTACH_NO_CONNECTOR
From: Luca Ceresoli @ 2026-04-02 9:26 UTC (permalink / raw)
To: Marek Vasut, Stefan Agner, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Liu Ying, Rob Herring,
Saravana Kannan
Cc: Damon Ding, Kory Maincent (TI.com), Hervé Codina, Hui Pu,
Ian Ray, Thomas Petazzoni, dri-devel, imx, linux-arm-kernel,
linux-kernel, devicetree, Adam Ford, Alexander Stein,
Christopher Obbard, Daniel Scally, Emanuele Ghidoli,
Fabio Estevam, Francesco Dolcini, Frieder Schrempf, Gilles Talis,
Goran Rađenović, Heiko Schocher, Josua Mayer,
Kieran Bingham, Marco Felsch, Martyn Welch, Oleksij Rempel,
Peng Fan, Richard Hu, Shengjiu Wang, Stefan Eichenberger,
Vitor Soares, Luca Ceresoli
In-Reply-To: <20260402-drm-lcdif-dbanc-v3-0-27cd247a0847@bootlin.com>
The imx8mp-hdmi-tx one of many drivers based on dw-hdmi. dw-hdmi in turn
can operate in two different modes, depending on the platform data as set
by the driver:
A. hdmi->plat_data->output_port = 0:
the HDMI output (port@1) in device tree is not used [0]
B. hdmi->plat_data->output_port = 1:
the HDMI output (port@1) is parsed to find the next bridge
The imx8mp-hdmi-tx driver falls in case A. Switching to case B, which is
the current best practice, requires that the HDMI connector is always
described in the live device tree, and a previous commit ensured this is
always the case by adding an overlay in case the device tree does not
comply.
So now we can simply switch to the new mode and support
DRM_BRIDGE_ATTACH_NO_CONNECTOR.
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
---
Changes in v2:
- new patch, split out of the previous patch
---
drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
index 32fd3554e267..8e8cfd66f23b 100644
--- a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
+++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c
@@ -138,6 +138,7 @@ static int imx8mp_dw_hdmi_probe(struct platform_device *pdev)
plat_data->phy_name = "SAMSUNG HDMI TX PHY";
plat_data->priv_data = hdmi;
plat_data->phy_force_vendor = true;
+ plat_data->output_port = 1;
platform_set_drvdata(pdev, hdmi);
--
2.53.0
^ permalink raw reply related
* [PATCH v3 09/11] drm/bridge: imx8mp-hdmi-tx-connector-fixup: show a warning when adding the overlay
From: Luca Ceresoli @ 2026-04-02 9:26 UTC (permalink / raw)
To: Marek Vasut, Stefan Agner, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Liu Ying, Rob Herring,
Saravana Kannan
Cc: Damon Ding, Kory Maincent (TI.com), Hervé Codina, Hui Pu,
Ian Ray, Thomas Petazzoni, dri-devel, imx, linux-arm-kernel,
linux-kernel, devicetree, Adam Ford, Alexander Stein,
Christopher Obbard, Daniel Scally, Emanuele Ghidoli,
Fabio Estevam, Francesco Dolcini, Frieder Schrempf, Gilles Talis,
Goran Rađenović, Heiko Schocher, Josua Mayer,
Kieran Bingham, Marco Felsch, Martyn Welch, Oleksij Rempel,
Peng Fan, Richard Hu, Shengjiu Wang, Stefan Eichenberger,
Vitor Soares, Luca Ceresoli
In-Reply-To: <20260402-drm-lcdif-dbanc-v3-0-27cd247a0847@bootlin.com>
Describing the HDMI connector in device tree is recommended. While the
overlay insertion is a workaround to avoid breaking existing devices, every
dts should be improved by adding a connector description.
Add a warning to make users aware as far as possible.
As a warning line cannot hold all the relevant info, add a detailed comment
in the code so it easy to find when the warning is seen.
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
---
Patch added in v3. Kept as a separate comment w.r.t. the patch adding the
overlay to let it be added in a later moment in case we want to convert
existing dts files before adding the warning.
---
.../gpu/drm/bridge/imx/imx8mp-hdmi-tx-connector-fixup.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx-connector-fixup.c b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx-connector-fixup.c
index dc1736bfc3ac..f6190d86abd0 100644
--- a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx-connector-fixup.c
+++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx-connector-fixup.c
@@ -44,6 +44,23 @@ static int __init imx8mp_hdmi_tx_connector_fixup_init(void)
if (endpoint)
return 0;
+ /*
+ * Boards with an HDMI connector should describe it in a device
+ * tree node with compatible = "hdmi-connector".
+ *
+ * If you see this warning, it means such a node was not found and
+ * a fallback one is added using a device tree overlay. Please add
+ * one in your device tree, also describing the exact connector
+ * type (the added overlay assumes Type A as a fallback, but it
+ * might be wrong).
+ *
+ * This node is necessary for modern DRM, where bridge drivers do
+ * not create a connector (see the DRM_BRIDGE_ATTACH_NO_CONNECTOR
+ * flag). See https://docs.kernel.org/gpu/drm-kms-helpers.html for
+ * more info.
+ */
+ pr_warn("Please add a hdmi-connector DT node for imx8mp-hdmi-tx.");
+
dtbo_start = __dtbo_imx8mp_hdmi_tx_connector_fixup_begin;
dtbo_size = __dtbo_imx8mp_hdmi_tx_connector_fixup_end -
__dtbo_imx8mp_hdmi_tx_connector_fixup_begin;
--
2.53.0
^ permalink raw reply related
* [PATCH v3 08/11] drm/bridge: imx8mp-hdmi-tx-connector-fixup: add an hdmi-connector when missing using a DT overlay at boot time
From: Luca Ceresoli @ 2026-04-02 9:26 UTC (permalink / raw)
To: Marek Vasut, Stefan Agner, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Liu Ying, Rob Herring,
Saravana Kannan
Cc: Damon Ding, Kory Maincent (TI.com), Hervé Codina, Hui Pu,
Ian Ray, Thomas Petazzoni, dri-devel, imx, linux-arm-kernel,
linux-kernel, devicetree, Adam Ford, Alexander Stein,
Christopher Obbard, Daniel Scally, Emanuele Ghidoli,
Fabio Estevam, Francesco Dolcini, Frieder Schrempf, Gilles Talis,
Goran Rađenović, Heiko Schocher, Josua Mayer,
Kieran Bingham, Marco Felsch, Martyn Welch, Oleksij Rempel,
Peng Fan, Richard Hu, Shengjiu Wang, Stefan Eichenberger,
Vitor Soares, Luca Ceresoli
In-Reply-To: <20260402-drm-lcdif-dbanc-v3-0-27cd247a0847@bootlin.com>
The imx8mp-hdmi-tx is one of many drivers based on dw-hdmi. dw-hdmi in turn
can operate in two different modes, depending on the platform data as set
by the driver:
A. hdmi->plat_data->output_port = 0:
the HDMI output (port@1) in device tree is not used [0]
B. hdmi->plat_data->output_port = 1:
the HDMI output (port@1) is parsed to find the next bridge
The imx8mp-hdmi-tx driver falls in case A. This implies next_bridge will
always be NULL, and so dw_hdmi_bridge_attach() [1] will always fail if
called with the DRM_BRIDGE_ATTACH_NO_CONNECTOR flag.
In fact case A assumes that DRM_BRIDGE_ATTACH_NO_CONNECTOR is not set and
in that case it adds an HDMI Type A connector programmatically at bridge
attach time.
Support for DRM_BRIDGE_ATTACH_NO_CONNECTOR is implemented by dw-hdmi.c in
case B. However switching to base B requires that port@1 is connected to a
"next bridge" DT node, typically the HDMI connector, because dw-hdmi won't
add the connector when using DRM_BRIDGE_ATTACH_NO_CONNECTOR.
Many dts files for imx8mp-based boards in the kernel have such a connector
described and linked to port@1, so the pipeline will be fully attached up
to a display-connector and a drm_connector added by the
bridge-connector. Sadly some of those dts files don't have the connector
described. Adding it would solve the problem easily, but this would break
existing devices which do not update the dtb when upgrading to a newer
kernel.
In preparation for switching to case B while preserving backward
compatibility for such devices, introduce a module adding the
hdmi-connector node to the live device tree at init time. This will allow
the dw-hdmi code to find the next bridge (the one wrapping the
hdmi-connector) and let the pipeline work as before.
The module is inserted only if there is no endpoint in port@1. So boards
whose device tree describe the connector will not have the device tre
modified, and will start isntantiating the correct HDMI connector type as
described in the device tree.
For boards lacking a connector description in DT the overlay will be added,
abd the HDMI connector will be Type A, which is a reasonable fallback and
is what the driver is currently doing.
[0] https://elixir.bootlin.com/linux/v7.0-rc1/source/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c#L3310
[1] https://elixir.bootlin.com/linux/v7.0-rc1/source/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c#L2907
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
---
Changes in v3:
- removed unused variable
- simplified overlay using full path to port@1
- handle of_overlay_fdt_apply() errors
- use of_graph_get_endpoint_by_regs() for more robust endpoint lookup
- improve subject line
Changes in v2:
- don't apply the overlay if the SoC is not i.MX8MP
- build unconditionally, but depend on DRM_IMX_LCDIF
- remove useless error check
- add missing cleanup.h and init.h includes, remove unneeded includes
- avoid dtc warnings on overlay
- fix typo in Kconfig help text
- not added the Tested-bys because the code has changed
- split the 'plat_data->output_port = 1' line to a separate patch
- improve commit message
This patch is inspired by commit 0ff223d99147 ("drm/tilcdc: Convert legacy
panel binding via DT overlay at boot time")
---
drivers/gpu/drm/bridge/imx/Kconfig | 18 +++++++
drivers/gpu/drm/bridge/imx/Makefile | 2 +
.../bridge/imx/imx8mp-hdmi-tx-connector-fixup.c | 58 ++++++++++++++++++++++
.../bridge/imx/imx8mp-hdmi-tx-connector-fixup.dtso | 33 ++++++++++++
4 files changed, 111 insertions(+)
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
index b9028a5e5a06..49f074559b00 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -18,6 +18,8 @@ config DRM_IMX8MP_DW_HDMI_BRIDGE
depends on OF
depends on COMMON_CLK
select DRM_DW_HDMI
+ select OF_OVERLAY
+ select DRM_DISPLAY_CONNECTOR
imply DRM_IMX8MP_HDMI_PAI
imply DRM_IMX8MP_HDMI_PVI
imply PHY_FSL_SAMSUNG_HDMI_PHY
@@ -25,6 +27,22 @@ config DRM_IMX8MP_DW_HDMI_BRIDGE
Choose this to enable support for the internal HDMI encoder found
on the i.MX8MP SoC.
+config DRM_IMX8MP_DW_HDMI_BRIDGE_CONNECTOR_FIXUP
+ bool
+ default y
+ depends on DRM_IMX_LCDIF
+ depends on DRM_IMX8MP_DW_HDMI_BRIDGE
+ depends on OF
+ help
+ Modifies at early boot the live device tree of boards using the
+ i.MX8MP fsl,imx8mp-hdmi-tx adding a hdmi-connector node linked to
+ the hdmi-tx. This is needed to support bridge-connector usage in
+ the i.MX8MP LCDIF driver.
+
+ You need this if you use the i.MX8MP HDMI output and your board
+ device tree file does not have an hdmi-connector node connected
+ to it.
+
config DRM_IMX8MP_HDMI_PAI
tristate "Freescale i.MX8MP HDMI PAI bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
index 8d01fda25451..84499fe2e444 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1,6 +1,8 @@
obj-$(CONFIG_DRM_IMX_LDB_HELPER) += imx-ldb-helper.o
obj-$(CONFIG_DRM_IMX_LEGACY_BRIDGE) += imx-legacy-bridge.o
obj-$(CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE) += imx8mp-hdmi-tx.o
+obj-$(CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE_CONNECTOR_FIXUP) += imx8mp-hdmi-tx-connector-fixup.o \
+ imx8mp-hdmi-tx-connector-fixup.dtbo.o
obj-$(CONFIG_DRM_IMX8MP_HDMI_PAI) += imx8mp-hdmi-pai.o
obj-$(CONFIG_DRM_IMX8MP_HDMI_PVI) += imx8mp-hdmi-pvi.o
obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx-connector-fixup.c b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx-connector-fixup.c
new file mode 100644
index 000000000000..dc1736bfc3ac
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx-connector-fixup.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Add an hdmi-connector node to boards using the imx8mp hdmi_tx which
+ * don't have one. This is needed for the i.MX LCDIF to work with
+ * DRM_BRIDGE_ATTACH_NO_CONNECTOR.
+ *
+ * Copyright (C) 2026 GE HealthCare
+ * Author: Luca Ceresoli <luca.ceresoli@bootlin.com>
+ */
+
+#include <linux/cleanup.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_graph.h>
+
+/* Embedded dtbo symbols created by cmd_wrap_S_dtb in scripts/Makefile.dtbs */
+extern char __dtbo_imx8mp_hdmi_tx_connector_fixup_begin[];
+extern char __dtbo_imx8mp_hdmi_tx_connector_fixup_end[];
+
+static int __init imx8mp_hdmi_tx_connector_fixup_init(void)
+{
+ struct device_node *soc __free(device_node) = NULL;
+ struct device_node *hdmi_tx __free(device_node) = NULL;
+ struct device_node *endpoint __free(device_node) = NULL;
+ void *dtbo_start;
+ u32 dtbo_size;
+ int ovcs_id;
+ int err;
+
+ soc = of_find_node_by_path("/soc@0");
+ if (!soc)
+ return 0;
+
+ /* This applies to i.MX8MP only, do nothing on other systems */
+ if (!of_device_is_compatible(soc, "fsl,imx8mp-soc"))
+ return 0;
+
+ hdmi_tx = of_find_node_by_path("/soc@0/bus@32c00000/hdmi@32fd8000");
+ if (!of_device_is_available(hdmi_tx))
+ return 0;
+
+ /* If endpoint exists, assume an hdmi-connector exists already */
+ endpoint = of_graph_get_endpoint_by_regs(hdmi_tx, 1, -1);
+ if (endpoint)
+ return 0;
+
+ dtbo_start = __dtbo_imx8mp_hdmi_tx_connector_fixup_begin;
+ dtbo_size = __dtbo_imx8mp_hdmi_tx_connector_fixup_end -
+ __dtbo_imx8mp_hdmi_tx_connector_fixup_begin;
+
+ err = of_overlay_fdt_apply(dtbo_start, dtbo_size, &ovcs_id, NULL);
+ if (err)
+ err = of_overlay_remove(&ovcs_id);
+
+ return err;
+}
+
+subsys_initcall(imx8mp_hdmi_tx_connector_fixup_init);
diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx-connector-fixup.dtso b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx-connector-fixup.dtso
new file mode 100644
index 000000000000..070be24fed3e
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx-connector-fixup.dtso
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DTS overlay adding an hdmi-connector node to boards using the imx8mp hdmi_tx
+ *
+ * Copyright (C) 2026 GE HealthCare
+ * Author: Luca Ceresoli <luca.ceresoli@bootlin.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ fixup-hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "HDMI";
+ type = "a";
+
+ port {
+ fixup_hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+ };
+};
+
+&{/soc@0/bus@32c00000/hdmi@32fd8000/ports/port@1} {
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&fixup_hdmi_connector_in>;
+ };
+};
--
2.53.0
^ permalink raw reply related
* [PATCH v13 7/7] qcom-tgu: Add reset node to initialize
From: Songwei Chai @ 2026-04-02 9:28 UTC (permalink / raw)
To: andersson, alexander.shishkin, mike.leach, konrad.dybcio,
suzuki.poulose, james.clark, krzk+dt, conor+dt
Cc: Songwei Chai, linux-kernel, linux-arm-kernel, linux-arm-msm,
coresight, devicetree, gregkh
In-Reply-To: <20260402092838.341295-1-songwei.chai@oss.qualcomm.com>
Add reset node to initialize the value of
priority/condition_decode/condition_select/timer/counter nodes.
Signed-off-by: Songwei Chai <songwei.chai@oss.qualcomm.com>
---
.../ABI/testing/sysfs-bus-amba-devices-tgu | 7 ++
drivers/hwtracing/qcom/tgu.c | 74 +++++++++++++++++++
2 files changed, 81 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
index 7a3573e03e27..a6b6019c8ef1 100644
--- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
+++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
@@ -42,3 +42,10 @@ KernelVersion: 7.1
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Songwei Chai <songwei.chai@oss.qualcomm.com>
Description:
(RW) Set/Get the counter value with specific step for TGU.
+
+What: /sys/bus/amba/devices/<tgu-name>/reset_tgu
+Date: April 2026
+KernelVersion: 7.1
+Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Songwei Chai <songwei.chai@oss.qualcomm.com>
+Description:
+ (Write) Write 1 to reset the dataset for TGU.
diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c
index 4a529520b428..752fcd2963e1 100644
--- a/drivers/hwtracing/qcom/tgu.c
+++ b/drivers/hwtracing/qcom/tgu.c
@@ -420,8 +420,82 @@ static ssize_t enable_tgu_store(struct device *dev,
}
static DEVICE_ATTR_RW(enable_tgu);
+/* reset_tgu_store - Reset Trace and Gating Unit (TGU) configuration. */
+static ssize_t reset_tgu_store(struct device *dev,
+ struct device_attribute *attr, const char *buf,
+ size_t size)
+{
+ struct tgu_drvdata *drvdata = dev_get_drvdata(dev);
+ struct value_table *vt = drvdata->value_table;
+ u32 *cond_decode = drvdata->value_table->condition_decode;
+ unsigned long value;
+ int i, j, ret;
+
+ if (kstrtoul(buf, 0, &value) || value != 1)
+ return -EINVAL;
+
+ spin_lock(&drvdata->lock);
+ if (!drvdata->enabled) {
+ spin_unlock(&drvdata->lock);
+ ret = pm_runtime_resume_and_get(drvdata->dev);
+ if (ret)
+ return ret;
+ spin_lock(&drvdata->lock);
+ }
+
+ tgu_do_disable(drvdata);
+
+ if (vt->priority) {
+ size_t size = MAX_PRIORITY * drvdata->num_step *
+ drvdata->num_reg * sizeof(unsigned int);
+ memset(vt->priority, 0, size);
+ }
+
+ if (vt->condition_decode) {
+ size_t size = drvdata->num_condition_decode *
+ drvdata->num_step * sizeof(unsigned int);
+ memset(vt->condition_decode, 0, size);
+ }
+
+ /* Initialize all condition registers to NOT(value=0x1000000) */
+ for (i = 0; i < drvdata->num_step; i++) {
+ for (j = 0; j < drvdata->num_condition_decode; j++) {
+ cond_decode[calculate_array_location(drvdata, i,
+ TGU_CONDITION_DECODE, j)] = 0x1000000;
+ }
+ }
+
+ if (vt->condition_select) {
+ size_t size = drvdata->num_condition_select *
+ drvdata->num_step * sizeof(unsigned int);
+ memset(vt->condition_select, 0, size);
+ }
+
+ if (vt->timer) {
+ size_t size = (drvdata->num_step) * (drvdata->num_timer) *
+ sizeof(unsigned int);
+ memset(vt->timer, 0, size);
+ }
+
+ if (vt->counter) {
+ size_t size = (drvdata->num_step) * (drvdata->num_counter) *
+ sizeof(unsigned int);
+ memset(vt->counter, 0, size);
+ }
+
+ spin_unlock(&drvdata->lock);
+
+ dev_dbg(dev, "Qualcomm-TGU reset complete\n");
+
+ pm_runtime_put(drvdata->dev);
+
+ return size;
+}
+static DEVICE_ATTR_WO(reset_tgu);
+
static struct attribute *tgu_common_attrs[] = {
&dev_attr_enable_tgu.attr,
+ &dev_attr_reset_tgu.attr,
NULL,
};
--
2.34.1
^ permalink raw reply related
* [PATCH v13 6/7] qcom-tgu: Add timer/counter functionality for TGU
From: Songwei Chai @ 2026-04-02 9:28 UTC (permalink / raw)
To: andersson, alexander.shishkin, mike.leach, konrad.dybcio,
suzuki.poulose, james.clark, krzk+dt, conor+dt
Cc: Songwei Chai, linux-kernel, linux-arm-kernel, linux-arm-msm,
coresight, devicetree, gregkh, Jie Gan
In-Reply-To: <20260402092838.341295-1-songwei.chai@oss.qualcomm.com>
Add counter and timer node for each step which could be
programed if they are to be utilized in trigger event/sequence.
Reviewed-by: Jie Gan <jie.gan@oss.qualcomm.com>
Signed-off-by: Songwei Chai <songwei.chai@oss.qualcomm.com>
---
.../ABI/testing/sysfs-bus-amba-devices-tgu | 14 +++
drivers/hwtracing/qcom/tgu.c | 116 +++++++++++++++++-
drivers/hwtracing/qcom/tgu.h | 56 +++++++++
3 files changed, 184 insertions(+), 2 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
index 786cb852bbe5..7a3573e03e27 100644
--- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
+++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
@@ -28,3 +28,17 @@ KernelVersion: 7.1
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Songwei Chai <songwei.chai@oss.qualcomm.com>
Description:
(RW) Set/Get the next action with specific step for TGU.
+
+What: /sys/bus/amba/devices/<tgu-name>/step[0:7]_timer/reg[0:1]
+Date: April 2026
+KernelVersion: 7.1
+Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Songwei Chai <songwei.chai@oss.qualcomm.com>
+Description:
+ (RW) Set/Get the timer value with specific step for TGU.
+
+What: /sys/bus/amba/devices/<tgu-name>/step[0:7]_counter/reg[0:1]
+Date: April 2026
+KernelVersion: 7.1
+Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Songwei Chai <songwei.chai@oss.qualcomm.com>
+Description:
+ (RW) Set/Get the counter value with specific step for TGU.
diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c
index 4112e6a691d6..4a529520b428 100644
--- a/drivers/hwtracing/qcom/tgu.c
+++ b/drivers/hwtracing/qcom/tgu.c
@@ -32,6 +32,10 @@ static int calculate_array_location(struct tgu_drvdata *drvdata,
case TGU_CONDITION_SELECT:
return step_index * (drvdata->num_condition_select) +
reg_index;
+ case TGU_COUNTER:
+ return step_index * (drvdata->num_counter) + reg_index;
+ case TGU_TIMER:
+ return step_index * (drvdata->num_timer) + reg_index;
default:
break;
}
@@ -77,6 +81,12 @@ static ssize_t tgu_dataset_show(struct device *dev,
case TGU_CONDITION_SELECT:
return sysfs_emit(buf, "0x%x\n",
drvdata->value_table->condition_select[index]);
+ case TGU_TIMER:
+ return sysfs_emit(buf, "0x%x\n",
+ drvdata->value_table->timer[index]);
+ case TGU_COUNTER:
+ return sysfs_emit(buf, "0x%x\n",
+ drvdata->value_table->counter[index]);
default:
break;
}
@@ -122,6 +132,14 @@ static ssize_t tgu_dataset_store(struct device *dev,
tgu_drvdata->value_table->condition_select[index] = val;
ret = size;
break;
+ case TGU_TIMER:
+ tgu_drvdata->value_table->timer[index] = val;
+ ret = size;
+ break;
+ case TGU_COUNTER:
+ tgu_drvdata->value_table->counter[index] = val;
+ ret = size;
+ break;
default:
ret = -EINVAL;
break;
@@ -163,6 +181,18 @@ static umode_t tgu_node_visible(struct kobject *kobject,
if (tgu_attr->reg_num < drvdata->num_condition_select)
return attr->mode;
break;
+ case TGU_COUNTER:
+ if (!drvdata->num_counter)
+ break;
+ if (tgu_attr->reg_num < drvdata->num_counter)
+ return attr->mode;
+ break;
+ case TGU_TIMER:
+ if (!drvdata->num_timer)
+ break;
+ if (tgu_attr->reg_num < drvdata->num_timer)
+ return attr->mode;
+ break;
default:
break;
}
@@ -213,6 +243,30 @@ static ssize_t tgu_write_all_hw_regs(struct tgu_drvdata *drvdata)
drvdata->base + CONDITION_SELECT_STEP(i, j));
}
}
+
+ for (i = 0; i < drvdata->num_step; i++) {
+ for (j = 0; j < drvdata->num_timer; j++) {
+ index = check_array_location(drvdata, i, TGU_TIMER, j);
+
+ if (index == -EINVAL)
+ goto exit;
+
+ writel(drvdata->value_table->timer[index],
+ drvdata->base + TIMER_COMPARE_STEP(i, j));
+ }
+ }
+
+ for (i = 0; i < drvdata->num_step; i++) {
+ for (j = 0; j < drvdata->num_counter; j++) {
+ index = check_array_location(drvdata, i, TGU_COUNTER, j);
+
+ if (index == -EINVAL)
+ goto exit;
+
+ writel(drvdata->value_table->counter[index],
+ drvdata->base + COUNTER_COMPARE_STEP(i, j));
+ }
+ }
/* Enable TGU to program the triggers */
writel(1, drvdata->base + TGU_CONTROL);
exit:
@@ -256,6 +310,27 @@ static void tgu_set_conditions(struct tgu_drvdata *drvdata)
drvdata->num_condition_select = TGU_DEVID_CONDITIONS(devid) + 1;
}
+static void tgu_set_timer_counter(struct tgu_drvdata *drvdata)
+{
+ int num_timers = 0, num_counters = 0;
+ u32 devid2;
+
+ devid2 = readl(drvdata->base + CORESIGHT_DEVID2);
+
+ if (TGU_DEVID2_TIMER0(devid2))
+ num_timers++;
+ if (TGU_DEVID2_TIMER1(devid2))
+ num_timers++;
+
+ if (TGU_DEVID2_COUNTER0(devid2))
+ num_counters++;
+ if (TGU_DEVID2_COUNTER1(devid2))
+ num_counters++;
+
+ drvdata->num_timer = num_timers;
+ drvdata->num_counter = num_counters;
+}
+
static int tgu_enable(struct device *dev)
{
struct tgu_drvdata *drvdata = dev_get_drvdata(dev);
@@ -405,6 +480,22 @@ static const struct attribute_group *tgu_attr_groups[] = {
CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(5),
CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(6),
CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(7),
+ TIMER_ATTRIBUTE_GROUP_INIT(0),
+ TIMER_ATTRIBUTE_GROUP_INIT(1),
+ TIMER_ATTRIBUTE_GROUP_INIT(2),
+ TIMER_ATTRIBUTE_GROUP_INIT(3),
+ TIMER_ATTRIBUTE_GROUP_INIT(4),
+ TIMER_ATTRIBUTE_GROUP_INIT(5),
+ TIMER_ATTRIBUTE_GROUP_INIT(6),
+ TIMER_ATTRIBUTE_GROUP_INIT(7),
+ COUNTER_ATTRIBUTE_GROUP_INIT(0),
+ COUNTER_ATTRIBUTE_GROUP_INIT(1),
+ COUNTER_ATTRIBUTE_GROUP_INIT(2),
+ COUNTER_ATTRIBUTE_GROUP_INIT(3),
+ COUNTER_ATTRIBUTE_GROUP_INIT(4),
+ COUNTER_ATTRIBUTE_GROUP_INIT(5),
+ COUNTER_ATTRIBUTE_GROUP_INIT(6),
+ COUNTER_ATTRIBUTE_GROUP_INIT(7),
NULL,
};
@@ -412,8 +503,8 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id)
{
struct device *dev = &adev->dev;
struct tgu_drvdata *drvdata;
- unsigned int *priority, *condition, *select;
- size_t priority_size, condition_size, select_size;
+ unsigned int *priority, *condition, *select, *timer, *counter;
+ size_t priority_size, condition_size, select_size, timer_size, counter_size;
int ret;
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
@@ -432,6 +523,7 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id)
tgu_set_reg_number(drvdata);
tgu_set_steps(drvdata);
tgu_set_conditions(drvdata);
+ tgu_set_timer_counter(drvdata);
ret = sysfs_create_groups(&dev->kobj, tgu_attr_groups);
if (ret) {
@@ -474,6 +566,26 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id)
drvdata->value_table->condition_select = select;
+ timer_size = drvdata->num_step * drvdata->num_timer;
+
+ timer = devm_kcalloc(dev, timer_size,
+ sizeof(*(drvdata->value_table->timer)),
+ GFP_KERNEL);
+ if (!timer)
+ return -ENOMEM;
+
+ drvdata->value_table->timer = timer;
+
+ counter_size = drvdata->num_step * drvdata->num_counter;
+
+ counter = devm_kcalloc(dev, counter_size,
+ sizeof(*(drvdata->value_table->counter)),
+ GFP_KERNEL);
+ if (!counter)
+ return -ENOMEM;
+
+ drvdata->value_table->counter = counter;
+
drvdata->enabled = false;
pm_runtime_put(&adev->dev);
diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h
index ac46a2875209..5dfef0afbad6 100644
--- a/drivers/hwtracing/qcom/tgu.h
+++ b/drivers/hwtracing/qcom/tgu.h
@@ -11,6 +11,7 @@
#define TGU_LAR 0xfb0
#define TGU_UNLOCK_OFFSET 0xc5acce55
#define TGU_DEVID 0xfc8
+#define CORESIGHT_DEVID2 0xfc0
#define TGU_DEVID_SENSE_INPUT(devid_val) \
((int)FIELD_GET(GENMASK(17, 10), devid_val))
@@ -18,6 +19,16 @@
((int)FIELD_GET(GENMASK(6, 3), devid_val))
#define TGU_DEVID_CONDITIONS(devid_val) \
((int)FIELD_GET(GENMASK(2, 0), devid_val))
+#define TGU_DEVID2_TIMER0(devid_val) \
+ ((int)FIELD_GET(GENMASK(23, 18), devid_val))
+#define TGU_DEVID2_TIMER1(devid_val) \
+ ((int)FIELD_GET(GENMASK(17, 13), devid_val))
+#define TGU_DEVID2_COUNTER0(devid_val) \
+ ((int)FIELD_GET(GENMASK(11, 6), devid_val))
+#define TGU_DEVID2_COUNTER1(devid_val) \
+ ((int)FIELD_GET(GENMASK(5, 0), devid_val))
+
+
#define TGU_BITS_PER_SIGNAL 4
#define LENGTH_REGISTER 32
@@ -53,6 +64,8 @@
#define PRIORITY_START_OFFSET 0x0074
#define CONDITION_DECODE_OFFSET 0x0050
#define CONDITION_SELECT_OFFSET 0x0060
+#define TIMER_START_OFFSET 0x0040
+#define COUNTER_START_OFFSET 0x0048
#define PRIORITY_OFFSET 0x60
#define REG_OFFSET 0x4
@@ -67,6 +80,12 @@
#define CONDITION_SELECT_STEP(step, select) \
(CONDITION_SELECT_OFFSET + REG_OFFSET * select + STEP_OFFSET * step)
+#define TIMER_COMPARE_STEP(step, timer) \
+ (TIMER_START_OFFSET + REG_OFFSET * timer + STEP_OFFSET * step)
+
+#define COUNTER_COMPARE_STEP(step, counter) \
+ (COUNTER_START_OFFSET + REG_OFFSET * counter + STEP_OFFSET * step)
+
#define tgu_dataset_rw(name, step_index, type, reg_num) \
(&((struct tgu_attribute[]){ { \
__ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \
@@ -82,6 +101,10 @@
tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_DECODE, reg_num)
#define STEP_SELECT(step_index, reg_num) \
tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_SELECT, reg_num)
+#define STEP_TIMER(step_index, reg_num) \
+ tgu_dataset_rw(reg##reg_num, step_index, TGU_TIMER, reg_num)
+#define STEP_COUNTER(step_index, reg_num) \
+ tgu_dataset_rw(reg##reg_num, step_index, TGU_COUNTER, reg_num)
#define STEP_PRIORITY_LIST(step_index, priority) \
{STEP_PRIORITY(step_index, 0, priority), \
@@ -122,6 +145,18 @@
NULL \
}
+#define STEP_TIMER_LIST(n) \
+ {STEP_TIMER(n, 0), \
+ STEP_TIMER(n, 1), \
+ NULL \
+ }
+
+#define STEP_COUNTER_LIST(n) \
+ {STEP_COUNTER(n, 0), \
+ STEP_COUNTER(n, 1), \
+ NULL \
+ }
+
#define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\
(&(const struct attribute_group){\
.attrs = (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\
@@ -143,6 +178,19 @@
.name = "step" #step "_condition_select" \
})
+#define TIMER_ATTRIBUTE_GROUP_INIT(step)\
+ (&(const struct attribute_group){\
+ .attrs = (struct attribute*[])STEP_TIMER_LIST(step),\
+ .is_visible = tgu_node_visible,\
+ .name = "step" #step "_timer" \
+ })
+
+#define COUNTER_ATTRIBUTE_GROUP_INIT(step)\
+ (&(const struct attribute_group){\
+ .attrs = (struct attribute*[])STEP_COUNTER_LIST(step),\
+ .is_visible = tgu_node_visible,\
+ .name = "step" #step "_counter" \
+ })
enum operation_index {
TGU_PRIORITY0,
@@ -151,6 +199,8 @@ enum operation_index {
TGU_PRIORITY3,
TGU_CONDITION_DECODE,
TGU_CONDITION_SELECT,
+ TGU_TIMER,
+ TGU_COUNTER
};
/* Maximum priority that TGU supports */
@@ -167,6 +217,8 @@ struct value_table {
unsigned int *priority;
unsigned int *condition_decode;
unsigned int *condition_select;
+ unsigned int *timer;
+ unsigned int *counter;
};
static inline void TGU_LOCK(void __iomem *addr)
@@ -198,6 +250,8 @@ static inline void TGU_UNLOCK(void __iomem *addr)
* @num_step: Maximum step size
* @num_condition_decode: Maximum number of condition_decode
* @num_condition_select: Maximum number of condition_select
+ * @num_timer: Maximum number of timers
+ * @num_counter: Maximum number of counters
*
* This structure defines the data associated with a TGU device,
* including its base address, device pointers, clock, spinlock for
@@ -214,6 +268,8 @@ struct tgu_drvdata {
int num_step;
int num_condition_decode;
int num_condition_select;
+ int num_timer;
+ int num_counter;
};
#endif
--
2.34.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox