* [PATCH V2 3/8] arm: dts: imx6sx-sdb: Move power supply property to Root Port node
From: Sherry Sun @ 2026-04-02 10:10 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260402101007.208419-1-sherry.sun@nxp.com>
Move the vpcie-supply property from the PCIe controller node to the Root
Port child node to support the new PCI pwrctrl framework.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi
index 338de4d144b2..7633ba2139d3 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi
@@ -284,12 +284,12 @@ &pcie {
pinctrl-0 = <&pinctrl_pcie>;
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
- vpcie-supply = <®_pcie_gpio>;
status = "okay";
};
&pcie_port0 {
reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_pcie_gpio>;
};
&lcdif1 {
--
2.37.1
^ permalink raw reply related
* [PATCH V2 4/8] arm64: dts: imx8mm-evk: Move power supply property to Root Port node
From: Sherry Sun @ 2026-04-02 10:10 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260402101007.208419-1-sherry.sun@nxp.com>
Move the vpcie-supply property from the PCIe controller node to the Root
Port child node to support the new PCI pwrctrl framework.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index e03aba825c18..ba7fa0815d13 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -542,7 +542,6 @@ &pcie0 {
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
- vpcie-supply = <®_pcie0>;
supports-clkreq;
status = "okay";
};
@@ -562,6 +561,7 @@ &pcie0_ep {
&pcie0_port0 {
reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_pcie0>;
};
&sai2 {
--
2.37.1
^ permalink raw reply related
* [PATCH V2 5/8] arm64: dts: imx8mp-evk: Move power supply properties to Root Port node
From: Sherry Sun @ 2026-04-02 10:10 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260402101007.208419-1-sherry.sun@nxp.com>
Move the vpcie-supply and vpcie3v3aux-supply properties from the PCIe
controller node to the Root Port child node to support the new PCI
pwrctrl framework.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index a7f3acdc36d1..cb2b820cf3bc 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -772,8 +772,6 @@ &pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
- vpcie-supply = <®_pcie0>;
- vpcie3v3aux-supply = <®_pcie0>;
supports-clkreq;
status = "disabled";
};
@@ -786,6 +784,8 @@ &pcie0_ep {
&pcie0_port0 {
reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_pcie0>;
+ vpcie3v3aux-supply = <®_pcie0>;
};
&pwm1 {
--
2.37.1
^ permalink raw reply related
* [PATCH V2 6/8] arm64: dts: imx8mq-evk: Move power supply properties to Root Port node
From: Sherry Sun @ 2026-04-02 10:10 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260402101007.208419-1-sherry.sun@nxp.com>
Move the vpcie-supply and vpcie3v3aux-supply properties from the PCIe
controller node to the Root Port child node to support the new PCI
pwrctrl framework.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index e7d87ea81b69..75d9b25d1f0e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -403,8 +403,6 @@ &pcie1 {
<&pcie0_refclk>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_AUX>;
- vpcie-supply = <®_pcie1>;
- vpcie3v3aux-supply = <®_pcie1>;
vph-supply = <&vgen5_reg>;
supports-clkreq;
status = "okay";
@@ -422,6 +420,8 @@ &pcie1_ep {
&pcie1_port0 {
reset-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_pcie1>;
+ vpcie3v3aux-supply = <®_pcie1>;
};
&pgc_gpu {
--
2.37.1
^ permalink raw reply related
* [PATCH V2 7/8] arm64: dts: imx8dxl/qm/qxp: Move power supply properties to Root Port node
From: Sherry Sun @ 2026-04-02 10:10 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260402101007.208419-1-sherry.sun@nxp.com>
Move the vpcie-supply and vpcie3v3aux-supply properties from the PCIe
controller nodes to the Root Port child nodes to support the new PCI
pwrctrl framework.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 4 ++--
arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 4 ++--
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index 39108a915f96..66b2d496b73f 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -677,8 +677,6 @@ &pcie0 {
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
- vpcie-supply = <®_pcieb>;
- vpcie3v3aux-supply = <®_pcieb>;
status = "okay";
};
@@ -694,6 +692,8 @@ &pcie0_ep {
&pcieb_port0 {
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_pcieb>;
+ vpcie3v3aux-supply = <®_pcieb>;
};
&sai0 {
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index f706c86137c0..5e725ad8aef9 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -812,14 +812,14 @@ &pciea {
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
- vpcie-supply = <®_pciea>;
- vpcie3v3aux-supply = <®_pciea>;
supports-clkreq;
status = "okay";
};
&pciea_port0 {
reset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_pciea>;
+ vpcie3v3aux-supply = <®_pciea>;
};
&pcieb {
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 489e174df4c4..4a4e9bcca9d0 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -732,8 +732,6 @@ &pcie0 {
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
- vpcie-supply = <®_pcieb>;
- vpcie3v3aux-supply = <®_pcieb>;
supports-clkreq;
status = "okay";
};
@@ -749,6 +747,8 @@ &pcie0_ep {
&pcieb_port0 {
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_pcieb>;
+ vpcie3v3aux-supply = <®_pcieb>;
};
&scu_key {
--
2.37.1
^ permalink raw reply related
* [PATCH V2 8/8] arm64: dts: imx95: Move power supply properties to Root Port node
From: Sherry Sun @ 2026-04-02 10:10 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam,
lpieralisi, kwilczynski, mani, bhelgaas, hongxing.zhu, l.stach
Cc: imx, linux-pci, linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20260402101007.208419-1-sherry.sun@nxp.com>
Move the vpcie-supply and vpcie3v3aux-supply properties from the PCIe
controller nodes to the Root Port child nodes to support the new PCI
pwrctrl framework.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 4 ++--
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
index 7d820a0f80b2..0d1cdfd54cce 100644
--- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
@@ -555,8 +555,6 @@ &pcie0 {
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;
- vpcie-supply = <®_m2_pwr>;
- vpcie3v3aux-supply = <®_m2_pwr>;
supports-clkreq;
status = "disabled";
};
@@ -570,6 +568,8 @@ &pcie0_ep {
&pcie0_port0 {
reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_m2_pwr>;
+ vpcie3v3aux-supply = <®_m2_pwr>;
};
&sai1 {
diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
index 6f193cf04119..77c3a87d9065 100644
--- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
@@ -542,8 +542,6 @@ &pcie0 {
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
- vpcie-supply = <®_pcie0>;
- vpcie3v3aux-supply = <®_pcie0>;
supports-clkreq;
status = "okay";
};
@@ -557,6 +555,8 @@ &pcie0_ep {
&pcie0_port0 {
reset-gpios = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_pcie0>;
+ vpcie3v3aux-supply = <®_pcie0>;
};
&pcie1 {
@@ -564,8 +564,6 @@ &pcie1 {
pinctrl-names = "default";
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
- vpcie-supply = <®_slot_pwr>;
- vpcie3v3aux-supply = <®_slot_pwr>;
status = "okay";
};
@@ -578,6 +576,8 @@ &pcie1_ep {
&pcie1_port0 {
reset-gpios = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
+ vpcie-supply = <®_slot_pwr>;
+ vpcie3v3aux-supply = <®_slot_pwr>;
};
&sai1 {
--
2.37.1
^ permalink raw reply related
* Re: [PATCH v6 00/13] Enable I2C on SA8255p Qualcomm platforms
From: Andi Shyti @ 2026-04-02 10:16 UTC (permalink / raw)
To: Praveen Talari
Cc: Mattijs Korpershoek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mukesh Kumar Savaliya, Viken Dadhaniya,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, bjorn.andersson, dmitry.baryshkov,
konrad.dybcio, prasad.sodagudi, aniket.randive,
chandana.chiluveru, jyothi.seerapu, chiluka.harish
In-Reply-To: <3d3f51e7-02c1-4628-a381-5a1ba67b5bc1@oss.qualcomm.com>
> > Note that I used a downstream device tree which has both
> > i2c11 (i2c@a90000) and i2c18(i2c@890000) enabled.
> >
> > The sources for that dts can be found here:
> > https://gitlab.com/mkorpershoek-rh/downstream-dtbs/-/tree/8775-upstream-i2c/qcom?ref_type=heads
> >
> > If this is considered useful testing, feel free to add:
> >
> > Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
>
> Thank you for validation and Tested-by tag.
>
> @Andi Shyti, Looking forward to the series being picked up. Feedback is
> welcome if anything further is needed.
Yes, I can take everything in the i2c branches, but I need
Bjorn's ack here for the Qualcomm part.
Thanks,
Andi
^ permalink raw reply
* Re: [PATCH v6 00/13] Enable I2C on SA8255p Qualcomm platforms
From: Krzysztof Kozlowski @ 2026-04-02 10:16 UTC (permalink / raw)
To: Praveen Talari, Mattijs Korpershoek, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mukesh Kumar Savaliya,
Viken Dadhaniya, Bjorn Andersson, Konrad Dybcio, linux-arm-msm,
linux-i2c, devicetree, linux-kernel, bjorn.andersson,
dmitry.baryshkov, konrad.dybcio
Cc: prasad.sodagudi, aniket.randive, chandana.chiluveru,
jyothi.seerapu, chiluka.harish
In-Reply-To: <3d3f51e7-02c1-4628-a381-5a1ba67b5bc1@oss.qualcomm.com>
On 27/03/2026 11:57, Praveen Talari wrote:
>> https://gitlab.com/mkorpershoek-rh/downstream-dtbs/-/tree/8775-upstream-i2c/qcom?ref_type=heads
>>
>> If this is considered useful testing, feel free to add:
>>
>> Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
>
> Thank you for validation and Tested-by tag.
>
> @Andi Shyti, Looking forward to the series being picked up. Feedback is
> welcome if anything further is needed.
Heh, no, don't ping needlessly Andi, but solve the his problems first -
is this acked for I2C? No. And Konrad's review, since he always reviews
patches picked up by Bjorn, is not explicit enough to tell that this can
go via I2C.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v13 2/7] qcom-tgu: Add TGU driver
From: Jie Gan @ 2026-04-02 10:18 UTC (permalink / raw)
To: Songwei Chai, andersson, alexander.shishkin, mike.leach,
konrad.dybcio, suzuki.poulose, james.clark, krzk+dt, conor+dt
Cc: linux-kernel, linux-arm-kernel, linux-arm-msm, coresight,
devicetree, gregkh
In-Reply-To: <20260402092838.341295-3-songwei.chai@oss.qualcomm.com>
On 4/2/2026 5:28 PM, Songwei Chai wrote:
> Add driver to support device TGU (Trigger Generation Unit).
> TGU is a Data Engine which can be utilized to sense a plurality of
> signals and create a trigger into the CTI or generate interrupts to
> processors. Add probe/enable/disable functions for tgu.
>
> Signed-off-by: Songwei Chai <songwei.chai@oss.qualcomm.com>
> ---
> .../ABI/testing/sysfs-bus-amba-devices-tgu | 9 +
> drivers/Makefile | 1 +
> drivers/hwtracing/Kconfig | 2 +
> drivers/hwtracing/qcom/Kconfig | 18 ++
> drivers/hwtracing/qcom/Makefile | 3 +
> drivers/hwtracing/qcom/tgu.c | 193 ++++++++++++++++++
> drivers/hwtracing/qcom/tgu.h | 51 +++++
> 7 files changed, 277 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
> create mode 100644 drivers/hwtracing/qcom/Kconfig
> create mode 100644 drivers/hwtracing/qcom/Makefile
> create mode 100644 drivers/hwtracing/qcom/tgu.c
> create mode 100644 drivers/hwtracing/qcom/tgu.h
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
> new file mode 100644
> index 000000000000..f877a00fcaa5
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
> @@ -0,0 +1,9 @@
> +What: /sys/bus/amba/devices/<tgu-name>/enable_tgu
> +Date: April 2026
> +KernelVersion: 7.1
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Songwei Chai <songwei.chai@oss.qualcomm.com>
> +Description:
> + (RW) Set/Get the enable/disable status of TGU
> + Accepts only one of the 2 values - 0 or 1.
> + 0 : disable TGU.
> + 1 : enable TGU.
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 53fbd2e0acdd..82b712a12a26 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -177,6 +177,7 @@ obj-$(CONFIG_RAS) += ras/
> obj-$(CONFIG_USB4) += thunderbolt/
> obj-$(CONFIG_CORESIGHT) += hwtracing/coresight/
> obj-y += hwtracing/intel_th/
> +obj-y += hwtracing/qcom/
> obj-$(CONFIG_STM) += hwtracing/stm/
> obj-$(CONFIG_HISI_PTT) += hwtracing/ptt/
> obj-y += android/
> diff --git a/drivers/hwtracing/Kconfig b/drivers/hwtracing/Kconfig
> index 911ee977103c..8a640218eed8 100644
> --- a/drivers/hwtracing/Kconfig
> +++ b/drivers/hwtracing/Kconfig
> @@ -7,4 +7,6 @@ source "drivers/hwtracing/intel_th/Kconfig"
>
> source "drivers/hwtracing/ptt/Kconfig"
>
> +source "drivers/hwtracing/qcom/Kconfig"
> +
> endmenu
> diff --git a/drivers/hwtracing/qcom/Kconfig b/drivers/hwtracing/qcom/Kconfig
> new file mode 100644
> index 000000000000..d6f6d4b0f28e
> --- /dev/null
> +++ b/drivers/hwtracing/qcom/Kconfig
> @@ -0,0 +1,18 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +#
> +# QCOM specific hwtracing drivers
> +#
> +menu "Qualcomm specific hwtracing drivers"
> +
> +config QCOM_TGU
> + tristate "QCOM Trigger Generation Unit driver"
depends on ARCH_QCOM || COMPILE_TEST
depends on ARM_AMBA
> + help
> + This driver provides support for Trigger Generation Unit that is
> + used to detect patterns or sequences on a given set of signals.
> + TGU is used to monitor a particular bus within a given region to
> + detect illegal transaction sequences or slave responses. It is also
> + used to monitor a data stream to detect protocol violations and to
> + provide a trigger point for centering data around a specific event
> + within the trace data buffer.
> +
> +endmenu
> diff --git a/drivers/hwtracing/qcom/Makefile b/drivers/hwtracing/qcom/Makefile
> new file mode 100644
> index 000000000000..5a0a868c1ea0
> --- /dev/null
> +++ b/drivers/hwtracing/qcom/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-$(CONFIG_QCOM_TGU) += tgu.o
> diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c
> new file mode 100644
> index 000000000000..49c8f710b931
> --- /dev/null
> +++ b/drivers/hwtracing/qcom/tgu.c
> @@ -0,0 +1,193 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <linux/amba/bus.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/pm_runtime.h>
> +
> +#include "tgu.h"
> +
> +static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata)
> +{
> + TGU_UNLOCK(drvdata->base);
> + /* Enable TGU to program the triggers */
> + writel(1, drvdata->base + TGU_CONTROL);
> + TGU_LOCK(drvdata->base);
> +}
> +
> +static int tgu_enable(struct device *dev)
> +{
> + struct tgu_drvdata *drvdata = dev_get_drvdata(dev);
> +
> + guard(spinlock)(&drvdata->lock);
> + drvdata->enabled = true;
> +
> + tgu_write_all_hw_regs(drvdata);
> +
> + return 0;
> +}
> +
> +static void tgu_do_disable(struct tgu_drvdata *drvdata)
> +{
> + TGU_UNLOCK(drvdata->base);
> + writel(0, drvdata->base + TGU_CONTROL);
> + TGU_LOCK(drvdata->base);
> +
> + drvdata->enabled = false;
> +}
> +
> +static void tgu_disable(struct device *dev)
> +{
> + struct tgu_drvdata *drvdata = dev_get_drvdata(dev);
> +
> + guard(spinlock)(&drvdata->lock);
> + if (!drvdata->enabled)
> + return;
> +
> + tgu_do_disable(drvdata);
> +}
> +
> +static ssize_t enable_tgu_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct tgu_drvdata *drvdata = dev_get_drvdata(dev);
> + bool enabled;
> +
> + guard(spinlock)(&drvdata->lock);
> + enabled = drvdata->enabled;
> +
> + return sysfs_emit(buf, "%d\n", !!enabled);
> +}
> +
> +/* enable_tgu_store - Configure Trace and Gating Unit (TGU) triggers. */
> +static ssize_t enable_tgu_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t size)
> +{
> + struct tgu_drvdata *drvdata = dev_get_drvdata(dev);
> + unsigned long val;
> + int ret;
> +
> + ret = kstrtoul(buf, 0, &val);
> + if (ret || val > 1)
> + return -EINVAL;
> +
> + if (val) {
> + scoped_guard(spinlock, &drvdata->lock) {
> + if (drvdata->enabled)
> + return -EBUSY;
> + }
> +
> + ret = pm_runtime_resume_and_get(dev);
> + if (ret)
> + return ret;
> +
> + ret = tgu_enable(dev);
> + if (ret) {
> + pm_runtime_put(dev);
> + return ret;
> + }
> + } else {
> + scoped_guard(spinlock, &drvdata->lock) {
> + if (!drvdata->enabled)
> + return -EINVAL;
> + }
> +
> + tgu_disable(dev);
> + pm_runtime_put(dev);
> + }
> +
> + return size;
> +}
> +static DEVICE_ATTR_RW(enable_tgu);
> +
> +static struct attribute *tgu_common_attrs[] = {
> + &dev_attr_enable_tgu.attr,
> + NULL,
> +};
> +
> +static const struct attribute_group tgu_common_grp = {
> + .attrs = tgu_common_attrs,
> + NULL,
> +};
> +
> +static const struct attribute_group *tgu_attr_groups[] = {
> + &tgu_common_grp,
> + NULL,
> +};
> +
> +static int tgu_probe(struct amba_device *adev, const struct amba_id *id)
> +{
> + struct device *dev = &adev->dev;
> + struct tgu_drvdata *drvdata;
> + int ret;
> +
> + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> + if (!drvdata)
> + return -ENOMEM;
> +
> + drvdata->dev = &adev->dev;
> + dev_set_drvdata(dev, drvdata);
> +
> + drvdata->base = devm_ioremap_resource(dev, &adev->res);
> + if (IS_ERR(drvdata->base))
> + return PTR_ERR(drvdata->base);
pm_runtime_enable is called in amba_probe, and amba_probe calls
pm_runtime_put_noidle only when tgu_probe succeeds. We need call the
pm_runtime_put in error path to reset the runtime refcount.
> +
> + spin_lock_init(&drvdata->lock);
> +
> + ret = sysfs_create_groups(&dev->kobj, tgu_attr_groups);
> + if (ret) {
> + dev_err(dev, "failed to create sysfs groups: %d\n", ret);
> + return ret;
> + }
> +
> + drvdata->enabled = false;
> +
> + pm_runtime_put(&adev->dev);
> +
> + return 0;
> +}
> +
> +static void tgu_remove(struct amba_device *adev)
> +{
> + struct device *dev = &adev->dev;
> +
> + sysfs_remove_groups(&dev->kobj, tgu_attr_groups);
> +
> + tgu_disable(dev);
> +}
> +
> +static const struct amba_id tgu_ids[] = {
> + {
> + .id = 0x000f0e00,
> + .mask = 0x000fffff,
> + },
> + { 0, 0, NULL },
> +};
> +
> +MODULE_DEVICE_TABLE(amba, tgu_ids);
> +
> +static struct amba_driver tgu_driver = {
> + .drv = {
> + .name = "qcom-tgu",
> + .suppress_bind_attrs = true,
> + },
> + .probe = tgu_probe,
> + .remove = tgu_remove,
> + .id_table = tgu_ids,
> +};
> +
> +module_amba_driver(tgu_driver);
> +
> +MODULE_AUTHOR("Songwei Chai <songwei.chai@oss.qualcomm.com>");
> +MODULE_AUTHOR("Jinlong Mao <jinlong.mao@oss.qualcomm.com>");
> +MODULE_DESCRIPTION("Qualcomm Trigger Generation Unit driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h
> new file mode 100644
> index 000000000000..dd7533b9d735
> --- /dev/null
> +++ b/drivers/hwtracing/qcom/tgu.h
> @@ -0,0 +1,51 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#ifndef _QCOM_TGU_H
> +#define _QCOM_TGU_H
> +
> +/* Register addresses */
> +#define TGU_CONTROL 0x0000
> +#define TGU_LAR 0xfb0
nit: wrong indent here (you can check in vim)
Thanks,
Jie
> +#define TGU_UNLOCK_OFFSET 0xc5acce55
> +
> +static inline void TGU_LOCK(void __iomem *addr)
> +{
> + do {
> + /* Wait for things to settle */
> + mb();
> + writel_relaxed(0x0, addr + TGU_LAR);
> + } while (0);
> +}
> +
> +static inline void TGU_UNLOCK(void __iomem *addr)
> +{
> + do {
> + writel_relaxed(TGU_UNLOCK_OFFSET, addr + TGU_LAR);
> + /* Make sure everyone has seen this */
> + mb();
> + } while (0);
> +}
> +
> +/**
> + * struct tgu_drvdata - Data structure for a TGU (Trigger Generator Unit)
> + * @base: Memory-mapped base address of the TGU device
> + * @dev: Pointer to the associated device structure
> + * @lock: Spinlock for handling concurrent access to private data
> + * @enabled: Flag indicating whether the TGU device is enabled
> + *
> + * This structure defines the data associated with a TGU device,
> + * including its base address, device pointers, clock, spinlock for
> + * synchronization, trigger data pointers, maximum limits for various
> + * trigger-related parameters, and enable status.
> + */
> +struct tgu_drvdata {
> + void __iomem *base;
> + struct device *dev;
> + spinlock_t lock;
> + bool enabled;
> +};
> +
> +#endif
^ permalink raw reply
* Re: [PATCH v6 00/13] Enable I2C on SA8255p Qualcomm platforms
From: Krzysztof Kozlowski @ 2026-04-02 10:18 UTC (permalink / raw)
To: Andi Shyti, Praveen Talari
Cc: Mattijs Korpershoek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mukesh Kumar Savaliya, Viken Dadhaniya,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, bjorn.andersson, dmitry.baryshkov,
konrad.dybcio, prasad.sodagudi, aniket.randive,
chandana.chiluveru, jyothi.seerapu, chiluka.harish
In-Reply-To: <ac5BiFn28inwixCi@zenone.zhora.eu>
On 02/04/2026 12:16, Andi Shyti wrote:
>>> Note that I used a downstream device tree which has both
>>> i2c11 (i2c@a90000) and i2c18(i2c@890000) enabled.
>>>
>>> The sources for that dts can be found here:
>>> https://gitlab.com/mkorpershoek-rh/downstream-dtbs/-/tree/8775-upstream-i2c/qcom?ref_type=heads
>>>
>>> If this is considered useful testing, feel free to add:
>>>
>>> Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
>>
>> Thank you for validation and Tested-by tag.
>>
>> @Andi Shyti, Looking forward to the series being picked up. Feedback is
>> welcome if anything further is needed.
>
> Yes, I can take everything in the i2c branches, but I need
> Bjorn's ack here for the Qualcomm part.
>
Nothing in the cover letter explains that there is any dependency here
or any merging decision to be solved.
Praveen,
If cover letter is poor and does not explain maintainer needs, then why
you are pinging? Your patchset gets ignored for example for that reason.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: timestamp: Add Tegra264 support
From: Jon Hunter @ 2026-04-02 10:21 UTC (permalink / raw)
To: Krzysztof Kozlowski, Suneel Garapati
Cc: dipenp, thierry.reding, krzk+dt, conor+dt, amhetre, sheetal,
kkartik, robh, pshete, timestamp, devicetree, linux-tegra,
linux-kernel
In-Reply-To: <c4f41a94-50d0-4f7d-b5cb-2fc966129440@kernel.org>
On 02/04/2026 10:53, Krzysztof Kozlowski wrote:
> On 02/04/2026 11:49, Jon Hunter wrote:
>>
>> On 02/04/2026 09:47, Krzysztof Kozlowski wrote:
>>> On 02/04/2026 10:47, Krzysztof Kozlowski wrote:
>>>> On Wed, Apr 01, 2026 at 09:38:29PM +0000, Suneel Garapati wrote:
>>>>> reg:
>>>>> maxItems: 1
>>>>> @@ -112,6 +114,7 @@ allOf:
>>>>> contains:
>>>>> enum:
>>>>> - nvidia,tegra234-gte-aon
>>>>> + - nvidia,tegra264-gte-aon
>>>>
>>>> And why exactly the slices are variable here? Explain that in commit
>>>> msg.
>>>
>>> s/Explain/Shortly describe/
>>
>> So this is not related to slices, but indicating the
>> 'nvidia,gpio-controller' property is required for the AON controller.
>> However, maybe your comment still applies and you want the commit
>> message to be explicit that for the AON instance the
>> 'nvidia,gpio-controller' is needed?
>
> You have two devices there - AON and LIC - and variable properties. I
> want answer why things are variable. HW is rarely variable. It is
> opposite of variable - afixed.
So note that 'nvidia,slices' is a deprecated property ...
1815e37b6e67 ("dt-bindings: timestamp: Deprecate nvidia,slices property")
I am guessing we did not bother to specify the slices for Tegra264
because this is no longer being used/supported. And yes, we should have
made this clear in the commit message :-)
Do you want the commit message updated?
Jon
--
nvpublic
^ permalink raw reply
* Re: [PATCH v13 3/7] qcom-tgu: Add signal priority support
From: Jie Gan @ 2026-04-02 10:23 UTC (permalink / raw)
To: Songwei Chai, andersson, alexander.shishkin, mike.leach,
konrad.dybcio, suzuki.poulose, james.clark, krzk+dt, conor+dt
Cc: linux-kernel, linux-arm-kernel, linux-arm-msm, coresight,
devicetree, gregkh
In-Reply-To: <20260402092838.341295-4-songwei.chai@oss.qualcomm.com>
On 4/2/2026 5:28 PM, Songwei Chai wrote:
> Like circuit of a Logic analyzer, in TGU, the requirement could be
> configured in each step and the trigger will be created once the
> requirements are met. Add priority functionality here to sort the
> signals into different priorities. The signal which is wanted could
> be configured in each step's priority node, the larger number means
> the higher priority and the signal with higher priority will be sensed
> more preferentially.
>
> Reviewed-by: Jie Gan <jie.gan@oss.qualcomm.com>
> Signed-off-by: Songwei Chai <songwei.chai@oss.qualcomm.com>
> ---
> .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 +
> drivers/hwtracing/qcom/tgu.c | 161 ++++++++++++++++++
> drivers/hwtracing/qcom/tgu.h | 114 +++++++++++++
> 3 files changed, 282 insertions(+)
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
> index f877a00fcaa5..223873789ca6 100644
> --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
> +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
> @@ -7,3 +7,10 @@ Description:
> Accepts only one of the 2 values - 0 or 1.
> 0 : disable TGU.
> 1 : enable TGU.
> +
> +What: /sys/bus/amba/devices/<tgu-name>/step[0:7]_priority[0:3]/reg[0:17]
> +Date: April 2026
> +KernelVersion: 7.1
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Songwei Chai <songwei.chai@oss.qualcomm.com>
> +Description:
> + (RW) Set/Get the sensed signal with specific step and priority for TGU.
> diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c
> index 49c8f710b931..7d69986c3e3d 100644
> --- a/drivers/hwtracing/qcom/tgu.c
> +++ b/drivers/hwtracing/qcom/tgu.c
> @@ -14,14 +14,123 @@
>
> #include "tgu.h"
>
> +static int calculate_array_location(struct tgu_drvdata *drvdata,
> + int step_index, int operation_index,
> + int reg_index)
> +{
> + return operation_index * (drvdata->num_step) * (drvdata->num_reg) +
> + step_index * (drvdata->num_reg) + reg_index;
> +}
> +
> +static ssize_t tgu_dataset_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct tgu_drvdata *drvdata = dev_get_drvdata(dev);
> + struct tgu_attribute *tgu_attr =
> + container_of(attr, struct tgu_attribute, attr);
> + int index;
> +
> + index = calculate_array_location(drvdata, tgu_attr->step_index,
> + tgu_attr->operation_index,
> + tgu_attr->reg_num);
> +
> + return sysfs_emit(buf, "0x%x\n",
> + drvdata->value_table->priority[index]);
> +}
> +
> +static ssize_t tgu_dataset_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t size)
> +{
> + struct tgu_drvdata *tgu_drvdata = dev_get_drvdata(dev);
> + struct tgu_attribute *tgu_attr =
> + container_of(attr, struct tgu_attribute, attr);
> + unsigned long val;
> + int index;
> + int ret;
> +
> + ret = kstrtoul(buf, 0, &val);
> + if (ret)
> + return ret;
> +
> + guard(spinlock)(&tgu_drvdata->lock);
> + index = calculate_array_location(tgu_drvdata, tgu_attr->step_index,
> + tgu_attr->operation_index,
> + tgu_attr->reg_num);
> +
> + tgu_drvdata->value_table->priority[index] = val;
> +
> + return size;
> +}
> +
> +static umode_t tgu_node_visible(struct kobject *kobject,
> + struct attribute *attr,
> + int n)
> +{
> + struct device *dev = kobj_to_dev(kobject);
> + struct tgu_drvdata *drvdata = dev_get_drvdata(dev);
> + struct device_attribute *dev_attr =
> + container_of(attr, struct device_attribute, attr);
> + struct tgu_attribute *tgu_attr =
> + container_of(dev_attr, struct tgu_attribute, attr);
> +
> + if (tgu_attr->step_index >= drvdata->num_step)
> + return SYSFS_GROUP_INVISIBLE;
> +
> + if (tgu_attr->reg_num >= drvdata->num_reg)
> + return 0;
> +
> + return attr->mode;
> +}
> +
> static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata)
> {
> + int i, j, k, index;
> +
> TGU_UNLOCK(drvdata->base);
> + for (i = 0; i < drvdata->num_step; i++) {
> + for (j = 0; j < MAX_PRIORITY; j++) {
> + for (k = 0; k < drvdata->num_reg; k++) {
> + index = calculate_array_location(
> + drvdata, i, j, k);
> +
> + writel(drvdata->value_table->priority[index],
> + drvdata->base +
> + PRIORITY_REG_STEP(i, j, k));
> + }
> + }
> + }
> /* Enable TGU to program the triggers */
> writel(1, drvdata->base + TGU_CONTROL);
> TGU_LOCK(drvdata->base);
> }
>
> +static void tgu_set_reg_number(struct tgu_drvdata *drvdata)
> +{
> + int num_sense_input;
> + int num_reg;
> + u32 devid;
> +
> + devid = readl(drvdata->base + TGU_DEVID);
> +
> + num_sense_input = TGU_DEVID_SENSE_INPUT(devid);
> + num_reg = (num_sense_input * TGU_BITS_PER_SIGNAL) / LENGTH_REGISTER;
> +
> + if ((num_sense_input * TGU_BITS_PER_SIGNAL) % LENGTH_REGISTER)
> + num_reg++;
> +
> + drvdata->num_reg = num_reg;
> +}
> +
> +static void tgu_set_steps(struct tgu_drvdata *drvdata)
> +{
> + u32 devid;
> +
> + devid = readl(drvdata->base + TGU_DEVID);
> +
> + drvdata->num_step = TGU_DEVID_STEPS(devid);
> +}
> +
> static int tgu_enable(struct device *dev)
> {
> struct tgu_drvdata *drvdata = dev_get_drvdata(dev);
> @@ -121,6 +230,38 @@ static const struct attribute_group tgu_common_grp = {
>
> static const struct attribute_group *tgu_attr_groups[] = {
> &tgu_common_grp,
> + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 0),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 1),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 2),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 3),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 0),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 1),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 2),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 3),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 0),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 1),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 2),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 3),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 0),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 1),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 2),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 3),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 0),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 1),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 2),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 3),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 0),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 1),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 2),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 3),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 0),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 1),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 2),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 3),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 0),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 1),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 2),
> + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 3),
> NULL,
> };
>
> @@ -128,6 +269,8 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id)
> {
> struct device *dev = &adev->dev;
> struct tgu_drvdata *drvdata;
> + unsigned int *priority;
> + size_t priority_size;
> int ret;
>
> drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> @@ -143,12 +286,30 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id)
>
> spin_lock_init(&drvdata->lock);
>
> + tgu_set_reg_number(drvdata);
> + tgu_set_steps(drvdata);
> +
> ret = sysfs_create_groups(&dev->kobj, tgu_attr_groups);
> if (ret) {
> dev_err(dev, "failed to create sysfs groups: %d\n", ret);
> return ret;
> }
>
> + drvdata->value_table =
> + devm_kzalloc(dev, sizeof(*drvdata->value_table), GFP_KERNEL);
> + if (!drvdata->value_table)
> + return -ENOMEM;
> +
> + priority_size = MAX_PRIORITY * drvdata->num_reg * drvdata->num_step;
> +
> + priority = devm_kcalloc(dev, priority_size,
> + sizeof(*drvdata->value_table->priority),
> + GFP_KERNEL);
> + if (!priority)
> + return -ENOMEM;
> +
> + drvdata->value_table->priority = priority;
> +
> drvdata->enabled = false;
>
> pm_runtime_put(&adev->dev);
> diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h
> index dd7533b9d735..df570c89ffd7 100644
> --- a/drivers/hwtracing/qcom/tgu.h
> +++ b/drivers/hwtracing/qcom/tgu.h
> @@ -10,6 +10,114 @@
> #define TGU_CONTROL 0x0000
> #define TGU_LAR 0xfb0
> #define TGU_UNLOCK_OFFSET 0xc5acce55
> +#define TGU_DEVID 0xfc8
> +
> +#define TGU_DEVID_SENSE_INPUT(devid_val) \
> + ((int)FIELD_GET(GENMASK(17, 10), devid_val))
> +#define TGU_DEVID_STEPS(devid_val) \
> + ((int)FIELD_GET(GENMASK(6, 3), devid_val))
> +#define TGU_BITS_PER_SIGNAL 4
> +#define LENGTH_REGISTER 32
> +
> +/*
> + * TGU configuration space Step configuration
> + * offset table space layout
> + * x-------------------------x$ x-------------x$
> + * | |$ | |$
> + * | | | reserve |$
> + * | | | |$
> + * |coresight management | |-------------|base+n*0x1D8+0x1F4$
> + * | registe | |---> |prioroty[3] |$
s/registe/registers
s/prioroty/priority
Thanks,
Jie
> + * | | | |-------------|base+n*0x1D8+0x194$
> + * | | | |prioroty[2] |$
> + * |-------------------------| | |-------------|base+n*0x1D8+0x134$
> + * | | | |prioroty[1] |$
> + * | step[7] | | |-------------|base+n*0x1D8+0xD4$
> + * |-------------------------|->base+0x40+7*0x1D8 | |prioroty[0] |$
> + * | | | |-------------|base+n*0x1D8+0x74$
> + * | ... | | | condition |$
> + * | | | | select |$
> + * |-------------------------|->base+0x40+1*0x1D8 | |-------------|base+n*0x1D8+0x60$
> + * | | | | condition |$
> + * | step[0] |--------------------> | decode |$
> + * |-------------------------|-> base+0x40 |-------------|base+n*0x1D8+0x50$
> + * | | | |$
> + * | Control and status space| |Timer/Counter|$
> + * | space | | |$
> + * x-------------------------x->base x-------------x base+n*0x1D8+0x40$
> + *
> + */
> +#define STEP_OFFSET 0x1D8
> +#define PRIORITY_START_OFFSET 0x0074
> +#define PRIORITY_OFFSET 0x60
> +#define REG_OFFSET 0x4
> +
> +/* Calculate compare step addresses */
> +#define PRIORITY_REG_STEP(step, priority, reg)\
> + (PRIORITY_START_OFFSET + PRIORITY_OFFSET * priority +\
> + REG_OFFSET * reg + STEP_OFFSET * step)
> +
> +#define tgu_dataset_rw(name, step_index, type, reg_num) \
> + (&((struct tgu_attribute[]){ { \
> + __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \
> + step_index, \
> + type, \
> + reg_num, \
> + } })[0].attr.attr)
> +
> +#define STEP_PRIORITY(step_index, reg_num, priority) \
> + tgu_dataset_rw(reg##reg_num, step_index, TGU_PRIORITY##priority, \
> + reg_num)
> +
> +#define STEP_PRIORITY_LIST(step_index, priority) \
> + {STEP_PRIORITY(step_index, 0, priority), \
> + STEP_PRIORITY(step_index, 1, priority), \
> + STEP_PRIORITY(step_index, 2, priority), \
> + STEP_PRIORITY(step_index, 3, priority), \
> + STEP_PRIORITY(step_index, 4, priority), \
> + STEP_PRIORITY(step_index, 5, priority), \
> + STEP_PRIORITY(step_index, 6, priority), \
> + STEP_PRIORITY(step_index, 7, priority), \
> + STEP_PRIORITY(step_index, 8, priority), \
> + STEP_PRIORITY(step_index, 9, priority), \
> + STEP_PRIORITY(step_index, 10, priority), \
> + STEP_PRIORITY(step_index, 11, priority), \
> + STEP_PRIORITY(step_index, 12, priority), \
> + STEP_PRIORITY(step_index, 13, priority), \
> + STEP_PRIORITY(step_index, 14, priority), \
> + STEP_PRIORITY(step_index, 15, priority), \
> + STEP_PRIORITY(step_index, 16, priority), \
> + STEP_PRIORITY(step_index, 17, priority), \
> + NULL \
> + }
> +
> +#define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\
> + (&(const struct attribute_group){\
> + .attrs = (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\
> + .is_visible = tgu_node_visible,\
> + .name = "step" #step "_priority" #priority \
> + })
> +
> +enum operation_index {
> + TGU_PRIORITY0,
> + TGU_PRIORITY1,
> + TGU_PRIORITY2,
> + TGU_PRIORITY3,
> +};
> +
> +/* Maximum priority that TGU supports */
> +#define MAX_PRIORITY 4
> +
> +struct tgu_attribute {
> + struct device_attribute attr;
> + u32 step_index;
> + enum operation_index operation_index;
> + u32 reg_num;
> +};
> +
> +struct value_table {
> + unsigned int *priority;
> +};
>
> static inline void TGU_LOCK(void __iomem *addr)
> {
> @@ -35,6 +143,9 @@ static inline void TGU_UNLOCK(void __iomem *addr)
> * @dev: Pointer to the associated device structure
> * @lock: Spinlock for handling concurrent access to private data
> * @enabled: Flag indicating whether the TGU device is enabled
> + * @value_table: Store given value based on relevant parameters
> + * @num_reg: Maximum number of registers
> + * @num_step: Maximum step size
> *
> * This structure defines the data associated with a TGU device,
> * including its base address, device pointers, clock, spinlock for
> @@ -46,6 +157,9 @@ struct tgu_drvdata {
> struct device *dev;
> spinlock_t lock;
> bool enabled;
> + struct value_table *value_table;
> + int num_reg;
> + int num_step;
> };
>
> #endif
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: timestamp: Add Tegra264 support
From: Krzysztof Kozlowski @ 2026-04-02 10:24 UTC (permalink / raw)
To: Jon Hunter, Suneel Garapati
Cc: dipenp, thierry.reding, krzk+dt, conor+dt, amhetre, sheetal,
kkartik, robh, pshete, timestamp, devicetree, linux-tegra,
linux-kernel
In-Reply-To: <5ea58a03-a349-49be-9549-0836d4bc3254@nvidia.com>
On 02/04/2026 12:21, Jon Hunter wrote:
>
> On 02/04/2026 10:53, Krzysztof Kozlowski wrote:
>> On 02/04/2026 11:49, Jon Hunter wrote:
>>>
>>> On 02/04/2026 09:47, Krzysztof Kozlowski wrote:
>>>> On 02/04/2026 10:47, Krzysztof Kozlowski wrote:
>>>>> On Wed, Apr 01, 2026 at 09:38:29PM +0000, Suneel Garapati wrote:
>>>>>> reg:
>>>>>> maxItems: 1
>>>>>> @@ -112,6 +114,7 @@ allOf:
>>>>>> contains:
>>>>>> enum:
>>>>>> - nvidia,tegra234-gte-aon
>>>>>> + - nvidia,tegra264-gte-aon
>>>>>
>>>>> And why exactly the slices are variable here? Explain that in commit
>>>>> msg.
>>>>
>>>> s/Explain/Shortly describe/
>>>
>>> So this is not related to slices, but indicating the
>>> 'nvidia,gpio-controller' property is required for the AON controller.
>>> However, maybe your comment still applies and you want the commit
>>> message to be explicit that for the AON instance the
>>> 'nvidia,gpio-controller' is needed?
>>
>> You have two devices there - AON and LIC - and variable properties. I
>> want answer why things are variable. HW is rarely variable. It is
>> opposite of variable - afixed.
>
> So note that 'nvidia,slices' is a deprecated property ...
>
> 1815e37b6e67 ("dt-bindings: timestamp: Deprecate nvidia,slices property")
>
> I am guessing we did not bother to specify the slices for Tegra264
> because this is no longer being used/supported. And yes, we should have
> made this clear in the commit message :-)
>
Deprecated properties should not be allowed by the schema for new devices.
> Do you want the commit message updated?
It's enough to disallow the property.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v13 6/7] qcom-tgu: Add timer/counter functionality for TGU
From: Jie Gan @ 2026-04-02 10:26 UTC (permalink / raw)
To: Songwei Chai, andersson, alexander.shishkin, mike.leach,
konrad.dybcio, suzuki.poulose, james.clark, krzk+dt, conor+dt
Cc: linux-kernel, linux-arm-kernel, linux-arm-msm, coresight,
devicetree, gregkh
In-Reply-To: <20260402092838.341295-7-songwei.chai@oss.qualcomm.com>
On 4/2/2026 5:28 PM, Songwei Chai wrote:
> Add counter and timer node for each step which could be
> programed if they are to be utilized in trigger event/sequence.
>
> Reviewed-by: Jie Gan <jie.gan@oss.qualcomm.com>
> Signed-off-by: Songwei Chai <songwei.chai@oss.qualcomm.com>
> ---
> .../ABI/testing/sysfs-bus-amba-devices-tgu | 14 +++
> drivers/hwtracing/qcom/tgu.c | 116 +++++++++++++++++-
> drivers/hwtracing/qcom/tgu.h | 56 +++++++++
> 3 files changed, 184 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
> index 786cb852bbe5..7a3573e03e27 100644
> --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
> +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
> @@ -28,3 +28,17 @@ KernelVersion: 7.1
> Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Songwei Chai <songwei.chai@oss.qualcomm.com>
> Description:
> (RW) Set/Get the next action with specific step for TGU.
> +
> +What: /sys/bus/amba/devices/<tgu-name>/step[0:7]_timer/reg[0:1]
> +Date: April 2026
> +KernelVersion: 7.1
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Songwei Chai <songwei.chai@oss.qualcomm.com>
> +Description:
> + (RW) Set/Get the timer value with specific step for TGU.
> +
> +What: /sys/bus/amba/devices/<tgu-name>/step[0:7]_counter/reg[0:1]
> +Date: April 2026
> +KernelVersion: 7.1
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Songwei Chai <songwei.chai@oss.qualcomm.com>
> +Description:
> + (RW) Set/Get the counter value with specific step for TGU.
> diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c
> index 4112e6a691d6..4a529520b428 100644
> --- a/drivers/hwtracing/qcom/tgu.c
> +++ b/drivers/hwtracing/qcom/tgu.c
> @@ -32,6 +32,10 @@ static int calculate_array_location(struct tgu_drvdata *drvdata,
> case TGU_CONDITION_SELECT:
> return step_index * (drvdata->num_condition_select) +
> reg_index;
> + case TGU_COUNTER:
> + return step_index * (drvdata->num_counter) + reg_index;
> + case TGU_TIMER:
> + return step_index * (drvdata->num_timer) + reg_index;
> default:
> break;
> }
> @@ -77,6 +81,12 @@ static ssize_t tgu_dataset_show(struct device *dev,
> case TGU_CONDITION_SELECT:
> return sysfs_emit(buf, "0x%x\n",
> drvdata->value_table->condition_select[index]);
> + case TGU_TIMER:
> + return sysfs_emit(buf, "0x%x\n",
> + drvdata->value_table->timer[index]);
> + case TGU_COUNTER:
> + return sysfs_emit(buf, "0x%x\n",
> + drvdata->value_table->counter[index]);
> default:
> break;
> }
> @@ -122,6 +132,14 @@ static ssize_t tgu_dataset_store(struct device *dev,
> tgu_drvdata->value_table->condition_select[index] = val;
> ret = size;
> break;
> + case TGU_TIMER:
> + tgu_drvdata->value_table->timer[index] = val;
> + ret = size;
> + break;
> + case TGU_COUNTER:
> + tgu_drvdata->value_table->counter[index] = val;
> + ret = size;
> + break;
> default:
> ret = -EINVAL;
> break;
> @@ -163,6 +181,18 @@ static umode_t tgu_node_visible(struct kobject *kobject,
> if (tgu_attr->reg_num < drvdata->num_condition_select)
> return attr->mode;
> break;
> + case TGU_COUNTER:
> + if (!drvdata->num_counter)
> + break;
> + if (tgu_attr->reg_num < drvdata->num_counter)
> + return attr->mode;
> + break;
> + case TGU_TIMER:
> + if (!drvdata->num_timer)
> + break;
> + if (tgu_attr->reg_num < drvdata->num_timer)
> + return attr->mode;
> + break;
> default:
> break;
> }
> @@ -213,6 +243,30 @@ static ssize_t tgu_write_all_hw_regs(struct tgu_drvdata *drvdata)
> drvdata->base + CONDITION_SELECT_STEP(i, j));
> }
> }
> +
> + for (i = 0; i < drvdata->num_step; i++) {
> + for (j = 0; j < drvdata->num_timer; j++) {
> + index = check_array_location(drvdata, i, TGU_TIMER, j);
> +
> + if (index == -EINVAL)
> + goto exit;
> +
> + writel(drvdata->value_table->timer[index],
> + drvdata->base + TIMER_COMPARE_STEP(i, j));
> + }
> + }
> +
> + for (i = 0; i < drvdata->num_step; i++) {
> + for (j = 0; j < drvdata->num_counter; j++) {
> + index = check_array_location(drvdata, i, TGU_COUNTER, j);
> +
> + if (index == -EINVAL)
> + goto exit;
> +
> + writel(drvdata->value_table->counter[index],
> + drvdata->base + COUNTER_COMPARE_STEP(i, j));
> + }
> + }
> /* Enable TGU to program the triggers */
> writel(1, drvdata->base + TGU_CONTROL);
> exit:
> @@ -256,6 +310,27 @@ static void tgu_set_conditions(struct tgu_drvdata *drvdata)
> drvdata->num_condition_select = TGU_DEVID_CONDITIONS(devid) + 1;
> }
>
> +static void tgu_set_timer_counter(struct tgu_drvdata *drvdata)
> +{
> + int num_timers = 0, num_counters = 0;
> + u32 devid2;
> +
> + devid2 = readl(drvdata->base + CORESIGHT_DEVID2);
> +
> + if (TGU_DEVID2_TIMER0(devid2))
> + num_timers++;
> + if (TGU_DEVID2_TIMER1(devid2))
> + num_timers++;
> +
> + if (TGU_DEVID2_COUNTER0(devid2))
> + num_counters++;
> + if (TGU_DEVID2_COUNTER1(devid2))
> + num_counters++;
> +
> + drvdata->num_timer = num_timers;
> + drvdata->num_counter = num_counters;
> +}
> +
> static int tgu_enable(struct device *dev)
> {
> struct tgu_drvdata *drvdata = dev_get_drvdata(dev);
> @@ -405,6 +480,22 @@ static const struct attribute_group *tgu_attr_groups[] = {
> CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(5),
> CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(6),
> CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(7),
> + TIMER_ATTRIBUTE_GROUP_INIT(0),
> + TIMER_ATTRIBUTE_GROUP_INIT(1),
> + TIMER_ATTRIBUTE_GROUP_INIT(2),
> + TIMER_ATTRIBUTE_GROUP_INIT(3),
> + TIMER_ATTRIBUTE_GROUP_INIT(4),
> + TIMER_ATTRIBUTE_GROUP_INIT(5),
> + TIMER_ATTRIBUTE_GROUP_INIT(6),
> + TIMER_ATTRIBUTE_GROUP_INIT(7),
> + COUNTER_ATTRIBUTE_GROUP_INIT(0),
> + COUNTER_ATTRIBUTE_GROUP_INIT(1),
> + COUNTER_ATTRIBUTE_GROUP_INIT(2),
> + COUNTER_ATTRIBUTE_GROUP_INIT(3),
> + COUNTER_ATTRIBUTE_GROUP_INIT(4),
> + COUNTER_ATTRIBUTE_GROUP_INIT(5),
> + COUNTER_ATTRIBUTE_GROUP_INIT(6),
> + COUNTER_ATTRIBUTE_GROUP_INIT(7),
> NULL,
> };
>
> @@ -412,8 +503,8 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id)
> {
> struct device *dev = &adev->dev;
> struct tgu_drvdata *drvdata;
> - unsigned int *priority, *condition, *select;
> - size_t priority_size, condition_size, select_size;
> + unsigned int *priority, *condition, *select, *timer, *counter;
> + size_t priority_size, condition_size, select_size, timer_size, counter_size;
> int ret;
>
> drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> @@ -432,6 +523,7 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id)
> tgu_set_reg_number(drvdata);
> tgu_set_steps(drvdata);
> tgu_set_conditions(drvdata);
> + tgu_set_timer_counter(drvdata);
>
> ret = sysfs_create_groups(&dev->kobj, tgu_attr_groups);
> if (ret) {
> @@ -474,6 +566,26 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id)
>
> drvdata->value_table->condition_select = select;
>
> + timer_size = drvdata->num_step * drvdata->num_timer;
> +
> + timer = devm_kcalloc(dev, timer_size,
> + sizeof(*(drvdata->value_table->timer)),
> + GFP_KERNEL);
> + if (!timer)
> + return -ENOMEM;
> +
> + drvdata->value_table->timer = timer;
> +
> + counter_size = drvdata->num_step * drvdata->num_counter;
> +
> + counter = devm_kcalloc(dev, counter_size,
> + sizeof(*(drvdata->value_table->counter)),
> + GFP_KERNEL);
> + if (!counter)
> + return -ENOMEM;
> +
> + drvdata->value_table->counter = counter;
> +
> drvdata->enabled = false;
>
> pm_runtime_put(&adev->dev);
> diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h
> index ac46a2875209..5dfef0afbad6 100644
> --- a/drivers/hwtracing/qcom/tgu.h
> +++ b/drivers/hwtracing/qcom/tgu.h
> @@ -11,6 +11,7 @@
> #define TGU_LAR 0xfb0
> #define TGU_UNLOCK_OFFSET 0xc5acce55
> #define TGU_DEVID 0xfc8
> +#define CORESIGHT_DEVID2 0xfc0
>
> #define TGU_DEVID_SENSE_INPUT(devid_val) \
> ((int)FIELD_GET(GENMASK(17, 10), devid_val))
> @@ -18,6 +19,16 @@
> ((int)FIELD_GET(GENMASK(6, 3), devid_val))
> #define TGU_DEVID_CONDITIONS(devid_val) \
> ((int)FIELD_GET(GENMASK(2, 0), devid_val))
> +#define TGU_DEVID2_TIMER0(devid_val) \
> + ((int)FIELD_GET(GENMASK(23, 18), devid_val))
> +#define TGU_DEVID2_TIMER1(devid_val) \
> + ((int)FIELD_GET(GENMASK(17, 13), devid_val))
> +#define TGU_DEVID2_COUNTER0(devid_val) \
> + ((int)FIELD_GET(GENMASK(11, 6), devid_val))
> +#define TGU_DEVID2_COUNTER1(devid_val) \
> + ((int)FIELD_GET(GENMASK(5, 0), devid_val))
> +
> +
> #define TGU_BITS_PER_SIGNAL 4
> #define LENGTH_REGISTER 32
>
> @@ -53,6 +64,8 @@
> #define PRIORITY_START_OFFSET 0x0074
> #define CONDITION_DECODE_OFFSET 0x0050
> #define CONDITION_SELECT_OFFSET 0x0060
> +#define TIMER_START_OFFSET 0x0040
> +#define COUNTER_START_OFFSET 0x0048
> #define PRIORITY_OFFSET 0x60
> #define REG_OFFSET 0x4
>
> @@ -67,6 +80,12 @@
> #define CONDITION_SELECT_STEP(step, select) \
> (CONDITION_SELECT_OFFSET + REG_OFFSET * select + STEP_OFFSET * step)
>
> +#define TIMER_COMPARE_STEP(step, timer) \
> + (TIMER_START_OFFSET + REG_OFFSET * timer + STEP_OFFSET * step)
> +
> +#define COUNTER_COMPARE_STEP(step, counter) \
> + (COUNTER_START_OFFSET + REG_OFFSET * counter + STEP_OFFSET * step)
> +
> #define tgu_dataset_rw(name, step_index, type, reg_num) \
> (&((struct tgu_attribute[]){ { \
> __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \
> @@ -82,6 +101,10 @@
> tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_DECODE, reg_num)
> #define STEP_SELECT(step_index, reg_num) \
> tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_SELECT, reg_num)
> +#define STEP_TIMER(step_index, reg_num) \
> + tgu_dataset_rw(reg##reg_num, step_index, TGU_TIMER, reg_num)
> +#define STEP_COUNTER(step_index, reg_num) \
> + tgu_dataset_rw(reg##reg_num, step_index, TGU_COUNTER, reg_num)
>
> #define STEP_PRIORITY_LIST(step_index, priority) \
> {STEP_PRIORITY(step_index, 0, priority), \
> @@ -122,6 +145,18 @@
> NULL \
> }
>
> +#define STEP_TIMER_LIST(n) \
> + {STEP_TIMER(n, 0), \
> + STEP_TIMER(n, 1), \
> + NULL \
> + }
> +
> +#define STEP_COUNTER_LIST(n) \
> + {STEP_COUNTER(n, 0), \
> + STEP_COUNTER(n, 1), \
> + NULL \
> + }
> +
> #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\
> (&(const struct attribute_group){\
> .attrs = (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\
> @@ -143,6 +178,19 @@
> .name = "step" #step "_condition_select" \
> })
>
> +#define TIMER_ATTRIBUTE_GROUP_INIT(step)\
> + (&(const struct attribute_group){\
> + .attrs = (struct attribute*[])STEP_TIMER_LIST(step),\
> + .is_visible = tgu_node_visible,\
> + .name = "step" #step "_timer" \
> + })
> +
> +#define COUNTER_ATTRIBUTE_GROUP_INIT(step)\
> + (&(const struct attribute_group){\
> + .attrs = (struct attribute*[])STEP_COUNTER_LIST(step),\
> + .is_visible = tgu_node_visible,\
> + .name = "step" #step "_counter" \
> + })
>
> enum operation_index {
> TGU_PRIORITY0,
> @@ -151,6 +199,8 @@ enum operation_index {
> TGU_PRIORITY3,
> TGU_CONDITION_DECODE,
> TGU_CONDITION_SELECT,
> + TGU_TIMER,
> + TGU_COUNTER
[Nit] TGU_COUNTER,
Thanks,
Jie
> };
>
> /* Maximum priority that TGU supports */
> @@ -167,6 +217,8 @@ struct value_table {
> unsigned int *priority;
> unsigned int *condition_decode;
> unsigned int *condition_select;
> + unsigned int *timer;
> + unsigned int *counter;
> };
>
> static inline void TGU_LOCK(void __iomem *addr)
> @@ -198,6 +250,8 @@ static inline void TGU_UNLOCK(void __iomem *addr)
> * @num_step: Maximum step size
> * @num_condition_decode: Maximum number of condition_decode
> * @num_condition_select: Maximum number of condition_select
> + * @num_timer: Maximum number of timers
> + * @num_counter: Maximum number of counters
> *
> * This structure defines the data associated with a TGU device,
> * including its base address, device pointers, clock, spinlock for
> @@ -214,6 +268,8 @@ struct tgu_drvdata {
> int num_step;
> int num_condition_decode;
> int num_condition_select;
> + int num_timer;
> + int num_counter;
> };
>
> #endif
^ permalink raw reply
* Re: [PATCH v13 5/7] qcom-tgu: Add support to configure next action
From: Jie Gan @ 2026-04-02 10:28 UTC (permalink / raw)
To: Songwei Chai, andersson, alexander.shishkin, mike.leach,
konrad.dybcio, suzuki.poulose, james.clark, krzk+dt, conor+dt
Cc: linux-kernel, linux-arm-kernel, linux-arm-msm, coresight,
devicetree, gregkh
In-Reply-To: <20260402092838.341295-6-songwei.chai@oss.qualcomm.com>
On 4/2/2026 5:28 PM, Songwei Chai wrote:
> Add "select" node for each step to determine if another step is taken,
> trigger(s) are generated, counters/timers incremented/decremented, etc.
>
> Reviewed-by: Jie Gan <jie.gan@oss.qualcomm.com>
> Signed-off-by: Songwei Chai <songwei.chai@oss.qualcomm.com>
> ---
> .../ABI/testing/sysfs-bus-amba-devices-tgu | 7 +++
> drivers/hwtracing/qcom/tgu.c | 53 ++++++++++++++++++-
> drivers/hwtracing/qcom/tgu.h | 27 ++++++++++
> 3 files changed, 85 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
> index 4ef0d696d3d0..786cb852bbe5 100644
> --- a/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
> +++ b/Documentation/ABI/testing/sysfs-bus-amba-devices-tgu
> @@ -21,3 +21,10 @@ KernelVersion: 7.1
> Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Songwei Chai <songwei.chai@oss.qualcomm.com>
> Description:
> (RW) Set/Get the decode mode with specific step for TGU.
> +
> +What: /sys/bus/amba/devices/<tgu-name>/step[0:7]_condition_select/reg[0:3]
> +Date: April 2026
> +KernelVersion: 7.1
> +Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Songwei Chai <songwei.chai@oss.qualcomm.com>
> +Description:
> + (RW) Set/Get the next action with specific step for TGU.
> diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c
> index 5b37eb10f863..4112e6a691d6 100644
> --- a/drivers/hwtracing/qcom/tgu.c
> +++ b/drivers/hwtracing/qcom/tgu.c
> @@ -29,6 +29,9 @@ static int calculate_array_location(struct tgu_drvdata *drvdata,
> case TGU_CONDITION_DECODE:
> return step_index * (drvdata->num_condition_decode) +
> reg_index;
> + case TGU_CONDITION_SELECT:
> + return step_index * (drvdata->num_condition_select) +
> + reg_index;
> default:
> break;
> }
> @@ -71,6 +74,9 @@ static ssize_t tgu_dataset_show(struct device *dev,
> case TGU_CONDITION_DECODE:
> return sysfs_emit(buf, "0x%x\n",
> drvdata->value_table->condition_decode[index]);
> + case TGU_CONDITION_SELECT:
> + return sysfs_emit(buf, "0x%x\n",
> + drvdata->value_table->condition_select[index]);
> default:
> break;
> }
> @@ -112,6 +118,10 @@ static ssize_t tgu_dataset_store(struct device *dev,
> tgu_drvdata->value_table->condition_decode[index] = val;
> ret = size;
> break;
> + case TGU_CONDITION_SELECT:
> + tgu_drvdata->value_table->condition_select[index] = val;
> + ret = size;
> + break;
> default:
> ret = -EINVAL;
> break;
> @@ -146,6 +156,13 @@ static umode_t tgu_node_visible(struct kobject *kobject,
> if (tgu_attr->reg_num < drvdata->num_condition_decode)
> return attr->mode;
> break;
> + case TGU_CONDITION_SELECT:
> + /* 'default' register is at the end of 'select' region */
> + if (tgu_attr->reg_num == drvdata->num_condition_select - 1)
> + attr->name = "default";
> + if (tgu_attr->reg_num < drvdata->num_condition_select)
> + return attr->mode;
> + break;
> default:
> break;
> }
> @@ -184,6 +201,18 @@ static ssize_t tgu_write_all_hw_regs(struct tgu_drvdata *drvdata)
> drvdata->base + CONDITION_DECODE_STEP(i, j));
> }
> }
> +
> + for (i = 0; i < drvdata->num_step; i++) {
> + for (j = 0; j < drvdata->num_condition_select; j++) {
> + index = check_array_location(drvdata, i,
> + TGU_CONDITION_SELECT, j);
> + if (index == -EINVAL)
> + goto exit;
> +
> + writel(drvdata->value_table->condition_select[index],
> + drvdata->base + CONDITION_SELECT_STEP(i, j));
> + }
> + }
> /* Enable TGU to program the triggers */
> writel(1, drvdata->base + TGU_CONTROL);
> exit:
> @@ -223,6 +252,8 @@ static void tgu_set_conditions(struct tgu_drvdata *drvdata)
>
> devid = readl(drvdata->base + TGU_DEVID);
> drvdata->num_condition_decode = TGU_DEVID_CONDITIONS(devid);
> + /* select region has an additional 'default' register */
> + drvdata->num_condition_select = TGU_DEVID_CONDITIONS(devid) + 1;
> }
>
> static int tgu_enable(struct device *dev)
> @@ -366,6 +397,14 @@ static const struct attribute_group *tgu_attr_groups[] = {
> CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(5),
> CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(6),
> CONDITION_DECODE_ATTRIBUTE_GROUP_INIT(7),
> + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(0),
> + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(1),
> + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(2),
> + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(3),
> + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(4),
> + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(5),
> + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(6),
> + CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(7),
> NULL,
> };
>
> @@ -373,8 +412,8 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id)
> {
> struct device *dev = &adev->dev;
> struct tgu_drvdata *drvdata;
> - unsigned int *priority, *condition;
> - size_t priority_size, condition_size;
> + unsigned int *priority, *condition, *select;
> + size_t priority_size, condition_size, select_size;
> int ret;
>
> drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> @@ -425,6 +464,16 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id)
>
> drvdata->value_table->condition_decode = condition;
>
> + select_size = drvdata->num_condition_select * drvdata->num_step;
> +
> + select = devm_kcalloc(dev, select_size,
> + sizeof(*(drvdata->value_table->condition_select)),
> + GFP_KERNEL);
> + if (!select)
> + return -ENOMEM;
> +
> + drvdata->value_table->condition_select = select;
> +
> drvdata->enabled = false;
>
> pm_runtime_put(&adev->dev);
> diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h
> index 987ea07bd618..ac46a2875209 100644
> --- a/drivers/hwtracing/qcom/tgu.h
> +++ b/drivers/hwtracing/qcom/tgu.h
> @@ -52,6 +52,7 @@
> #define STEP_OFFSET 0x1D8
> #define PRIORITY_START_OFFSET 0x0074
> #define CONDITION_DECODE_OFFSET 0x0050
> +#define CONDITION_SELECT_OFFSET 0x0060
> #define PRIORITY_OFFSET 0x60
> #define REG_OFFSET 0x4
>
> @@ -63,6 +64,9 @@
> #define CONDITION_DECODE_STEP(step, decode) \
> (CONDITION_DECODE_OFFSET + REG_OFFSET * decode + STEP_OFFSET * step)
>
> +#define CONDITION_SELECT_STEP(step, select) \
> + (CONDITION_SELECT_OFFSET + REG_OFFSET * select + STEP_OFFSET * step)
> +
> #define tgu_dataset_rw(name, step_index, type, reg_num) \
> (&((struct tgu_attribute[]){ { \
> __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \
> @@ -76,6 +80,8 @@
> reg_num)
> #define STEP_DECODE(step_index, reg_num) \
> tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_DECODE, reg_num)
> +#define STEP_SELECT(step_index, reg_num) \
> + tgu_dataset_rw(reg##reg_num, step_index, TGU_CONDITION_SELECT, reg_num)
>
> #define STEP_PRIORITY_LIST(step_index, priority) \
> {STEP_PRIORITY(step_index, 0, priority), \
> @@ -107,6 +113,15 @@
> NULL \
> }
>
> +#define STEP_SELECT_LIST(n) \
> + {STEP_SELECT(n, 0), \
> + STEP_SELECT(n, 1), \
> + STEP_SELECT(n, 2), \
> + STEP_SELECT(n, 3), \
> + STEP_SELECT(n, 4), \
> + NULL \
> + }
> +
> #define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\
> (&(const struct attribute_group){\
> .attrs = (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\
> @@ -121,12 +136,21 @@
> .name = "step" #step "_condition_decode" \
> })
>
> +#define CONDITION_SELECT_ATTRIBUTE_GROUP_INIT(step)\
> + (&(const struct attribute_group){\
> + .attrs = (struct attribute*[])STEP_SELECT_LIST(step),\
> + .is_visible = tgu_node_visible,\
> + .name = "step" #step "_condition_select" \
> + })
> +
> +
remove extra blank line.
Thanks,
Jie
> enum operation_index {
> TGU_PRIORITY0,
> TGU_PRIORITY1,
> TGU_PRIORITY2,
> TGU_PRIORITY3,
> TGU_CONDITION_DECODE,
> + TGU_CONDITION_SELECT,
> };
>
> /* Maximum priority that TGU supports */
> @@ -142,6 +166,7 @@ struct tgu_attribute {
> struct value_table {
> unsigned int *priority;
> unsigned int *condition_decode;
> + unsigned int *condition_select;
> };
>
> static inline void TGU_LOCK(void __iomem *addr)
> @@ -172,6 +197,7 @@ static inline void TGU_UNLOCK(void __iomem *addr)
> * @num_reg: Maximum number of registers
> * @num_step: Maximum step size
> * @num_condition_decode: Maximum number of condition_decode
> + * @num_condition_select: Maximum number of condition_select
> *
> * This structure defines the data associated with a TGU device,
> * including its base address, device pointers, clock, spinlock for
> @@ -187,6 +213,7 @@ struct tgu_drvdata {
> int num_reg;
> int num_step;
> int num_condition_decode;
> + int num_condition_select;
> };
>
> #endif
^ permalink raw reply
* Re: [PATCH 2/2] riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers
From: Han Gao @ 2026-04-02 10:30 UTC (permalink / raw)
To: Chen Wang
Cc: Han Gao, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Zixian Zeng,
linux-pci, devicetree, sophgo, linux-kernel, linux-riscv, stable
In-Reply-To: <MA5PR01MB12500707BE1C6E11EC3F4B94FFE51A@MA5PR01MB12500.INDPRD01.PROD.OUTLOOK.COM>
On Thu, Apr 2, 2026 at 4:44 PM Chen Wang <unicorn_wang@outlook.com> wrote:
>
>
> On 4/1/2026 1:12 AM, Han Gao wrote:
> > SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all
> > four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent
> > so the kernel uses coherent DMA mappings instead of non-coherent bounce
> > buffering.
> >
> > Cc: stable@vger.kernel.org
> > Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> > ---
> > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > index 9fddf3f0b3b9..3af770549742 100644
> > --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > @@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 {
> > vendor-id = <0x1f1c>;
> > device-id = <0x2042>;
> > cdns,no-bar-match-nbits = <48>;
> > + dma-coherent;
> > msi-parent = <&msi>;
> > status = "disabled";
> > };
> > @@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 {
> > vendor-id = <0x1f1c>;
> > device-id = <0x2042>;
> > cdns,no-bar-match-nbits = <48>;
> > + dma-coherent;
> > msi-parent = <&msi>;
> > status = "disabled";
> > };
> > @@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 {
> > vendor-id = <0x1f1c>;
> > device-id = <0x2042>;
> > cdns,no-bar-match-nbits = <48>;
> > + dma-coherent;
> > msi-parent = <&msi>;
> > status = "disabled";
> > };
> > @@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 {
> > vendor-id = <0x1f1c>;
> > device-id = <0x2042>;
> > cdns,no-bar-match-nbits = <48>;
> > + dma-coherent;
> > msi-parent = <&msi>;
> > status = "disabled";
> > };
> For binding changes, LGTM. But I have a question regarding this change
> in dtsi.
>
> From your patch description, I understand that enabling the
> `dma-coherent` attribute requires upgrading the firmware `fip.bin`. If a
> user only updates the kernel (which is relatively easy) but forgets or
> doesn't know how to upgrade the firmware, enabling `coherent` might
> cause the kernel to skip all explicit cache maintenance operations.
> Could this pose a subtle risk?
>
> Wouldn't it be safer to leave the upstream unchanged in dtsi and allow
> users to add the `dma-coherent` attribute themselves after they upgrade
> the firmware?
In the firmware, fip.bin and devicetree are distributed together.
So matching issues are unlikely.
>
> I would greatly appreciate your guidance.
>
> Thanks,
>
> Chen
>
>
Thanks,
Han
^ permalink raw reply
* Re: [PATCH v4 0/2] hwmon: pmbus: Sony APS-379
From: Guenter Roeck @ 2026-04-02 10:38 UTC (permalink / raw)
To: Chris Packham, robh, krzk+dt, conor+dt
Cc: devicetree, linux-hwmon, linux-kernel
In-Reply-To: <20260402024101.4136697-1-chris.packham@alliedtelesis.co.nz>
On 4/1/26 19:40, Chris Packham wrote:
> This series add support for the PMBus hwmon on the Sony
> APS-379 power supply module. There's some deviations from
> the PMBus specification that need to be dealt with.
>
> Chris Packham (2):
> dt-bindings: trivial-devices: Add sony,aps-379
> hwmon: pmbus: Add support for Sony APS-379
>
> .../devicetree/bindings/trivial-devices.yaml | 2 +
> Documentation/hwmon/aps-379.rst | 58 ++++++
> Documentation/hwmon/index.rst | 1 +
> drivers/hwmon/pmbus/Kconfig | 6 +
> drivers/hwmon/pmbus/Makefile | 1 +
> drivers/hwmon/pmbus/aps-379.c | 178 ++++++++++++++++++
> 6 files changed, 246 insertions(+)
> create mode 100644 Documentation/hwmon/aps-379.rst
> create mode 100644 drivers/hwmon/pmbus/aps-379.c
>
Sashiko still doesn't like it.
https://sashiko.dev/#/patchset/20260402024101.4136697-1-chris.packham%40alliedtelesis.co.nz
- Yes, "extracted while probing" is no longer accurate.
Maybe add a comment explaining that the exponent is constant.
Maybe even use a define ? That would make struct aps_379_data
unnecessary.
- Rejecting virtual registers: Why indeed ? Is there a reason ?
Thanks,
Guenter
^ permalink raw reply
* [PATCH v1] arm64: dts: qcom: Enable CAN RX via GPIO expander
From: Anup Kulkarni @ 2026-04-02 10:52 UTC (permalink / raw)
To: andersson, konradybcio, robh, krzk+dt, conor+dt, linux-arm-msm,
devicetree, linux-kernel
Cc: mukesh.savaliya, viken.dadhaniya, Anup Kulkarni
Few CAN controllers, part of RTSS sub-system on LeMans, route
their RX signal through a I2C GPIO expander at address 0x3b.
RTSS subsystem is an MCU like sub-system on LeMans with independent
booting capability through OSPI interface and supports peripherals like
RGMII, CAN-FD, UART, I2C, SPI etc.
Describe this hardware wiring by configuring the expander GPIO 4 pin as
hog with output-high, asserting the selected line during boot.
Signed-off-by: Anup Kulkarni <anup.kulkarni@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans-evk.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts
index a1ef4eba2a20..b8371bdf9933 100644
--- a/arch/arm64/boot/dts/qcom/lemans-evk.dts
+++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts
@@ -615,6 +615,13 @@ expander3: gpio@3b {
interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&expander3_int>;
pinctrl-names = "default";
+
+ rtss-can-sel-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rtss-can-sel";
+ };
};
eeprom@50 {
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v5 3/3] arm64,ppc64le/kdump: pass dm-crypt keys to kdump kernel
From: Sourabh Jain @ 2026-04-02 10:54 UTC (permalink / raw)
To: Coiby Xu, kexec, linux-arm-kernel, linuxppc-dev, devicetree
Cc: Arnaud Lefebvre, Baoquan he, Dave Young, Kairui Song, Pingfan Liu,
Andrew Morton, Krzysztof Kozlowski, Rob Herring, Thomas Staudt,
Will Deacon, Christophe Leroy (CS GROUP), Catalin Marinas,
Madhavan Srinivasan, Michael Ellerman, Nicholas Piggin,
Saravana Kannan, open list
In-Reply-To: <20260225060347.718905-4-coxu@redhat.com>
On 25/02/26 11:33, Coiby Xu wrote:
> CONFIG_CRASH_DM_CRYPT has been introduced to support LUKS-encrypted
> device dump target by addressing two challenges [1],
> - Kdump kernel may not be able to decrypt the LUKS partition. For some
> machines, a system administrator may not have a chance to enter the
> password to decrypt the device in kdump initramfs after the 1st kernel
> crashes
>
> - LUKS2 by default use the memory-hard Argon2 key derivation function
> which is quite memory-consuming compared to the limited memory reserved
> for kdump.
>
> To also enable this feature for ARM64 and PowerPC, the missing piece is
> to let the kdump kernel know where to find the dm-crypt keys which are
> randomly stored in memory reserved for kdump. Introduce a new device
> tree property dmcryptkeys [2] as similar to elfcorehdr to pass the
> memory address of the stored info of dm-crypt keys to the kdump kernel.
> Since this property is only needed by the kdump kernel, it won't be
> exposed to user space.
>
> [1] https://lore.kernel.org/all/20250502011246.99238-1-coxu@redhat.com/
> [2] https://github.com/devicetree-org/dt-schema/pull/181
>
> Cc: Arnaud Lefebvre <arnaud.lefebvre@clever-cloud.com>
> Cc: Baoquan he <bhe@redhat.com>
> Cc: Dave Young <dyoung@redhat.com>
> Cc: Kairui Song <ryncsn@gmail.com>
> Cc: Pingfan Liu <kernelfans@gmail.com>
> Cc: Andrew Morton <akpm@linux-foundation.org>
> Cc: Krzysztof Kozlowski <krzk@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Thomas Staudt <tstaudt@de.ibm.com>
> Cc: Sourabh Jain <sourabhjain@linux.ibm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
> Signed-off-by: Coiby Xu <coxu@redhat.com>
> ---
> arch/arm64/kernel/machine_kexec_file.c | 4 ++++
> arch/powerpc/kexec/elf_64.c | 4 ++++
> drivers/of/fdt.c | 21 +++++++++++++++++++++
> drivers/of/kexec.c | 19 +++++++++++++++++++
> 4 files changed, 48 insertions(+)
>
> diff --git a/arch/arm64/kernel/machine_kexec_file.c b/arch/arm64/kernel/machine_kexec_file.c
> index fba260ad87a9..e31fabed378a 100644
> --- a/arch/arm64/kernel/machine_kexec_file.c
> +++ b/arch/arm64/kernel/machine_kexec_file.c
> @@ -134,6 +134,10 @@ int load_other_segments(struct kimage *image,
>
> kexec_dprintk("Loaded elf core header at 0x%lx bufsz=0x%lx memsz=0x%lx\n",
> image->elf_load_addr, kbuf.bufsz, kbuf.memsz);
> +
> + ret = crash_load_dm_crypt_keys(image);
> + if (ret)
> + goto out_err;
> }
> #endif
>
> diff --git a/arch/powerpc/kexec/elf_64.c b/arch/powerpc/kexec/elf_64.c
> index 5d6d616404cf..ea50a072debf 100644
> --- a/arch/powerpc/kexec/elf_64.c
> +++ b/arch/powerpc/kexec/elf_64.c
> @@ -79,6 +79,10 @@ static void *elf64_load(struct kimage *image, char *kernel_buf,
> goto out;
> }
>
> + ret = crash_load_dm_crypt_keys(image);
> + if (ret)
> + goto out;
> +
> /* Setup cmdline for kdump kernel case */
> modified_cmdline = setup_kdump_cmdline(image, cmdline,
> cmdline_len);
> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> index 331646d667b9..2967e4aff807 100644
> --- a/drivers/of/fdt.c
> +++ b/drivers/of/fdt.c
> @@ -866,6 +866,26 @@ static void __init early_init_dt_check_for_elfcorehdr(unsigned long node)
> elfcorehdr_addr, elfcorehdr_size);
> }
>
> +static void __init early_init_dt_check_for_dmcryptkeys(unsigned long node)
> +{
> + const char *prop_name = "linux,dmcryptkeys";
> + const __be32 *prop;
> +
> + if (!IS_ENABLED(CONFIG_CRASH_DM_CRYPT))
> + return;
> +
> + pr_debug("Looking for dmcryptkeys property... ");
> +
> + prop = of_get_flat_dt_prop(node, prop_name, NULL);
> + if (!prop)
> + return;
> +
> + dm_crypt_keys_addr = dt_mem_next_cell(dt_root_addr_cells, &prop);
> +
> + /* Property only accessible to crash dump kernel */
> + fdt_delprop(initial_boot_params, node, prop_name);
> +}
> +
> static unsigned long chosen_node_offset = -FDT_ERR_NOTFOUND;
>
> /*
> @@ -1097,6 +1117,7 @@ int __init early_init_dt_scan_chosen(char *cmdline)
>
> early_init_dt_check_for_initrd(node);
> early_init_dt_check_for_elfcorehdr(node);
> + early_init_dt_check_for_dmcryptkeys(node);
>
> rng_seed = of_get_flat_dt_prop(node, "rng-seed", &l);
> if (rng_seed && l > 0) {
> diff --git a/drivers/of/kexec.c b/drivers/of/kexec.c
> index c4cf3552c018..fbd253f0d3c5 100644
> --- a/drivers/of/kexec.c
> +++ b/drivers/of/kexec.c
> @@ -423,6 +423,25 @@ void *of_kexec_alloc_and_setup_fdt(const struct kimage *image,
> if (ret)
> goto out;
>
> + if (image->dm_crypt_keys_addr != 0) {
> + ret = fdt_appendprop_addrrange(fdt, 0, chosen_node,
> + "linux,dmcryptkeys",
> + image->dm_crypt_keys_addr,
> + image->dm_crypt_keys_sz);
> +
> + if (ret)
> + goto out;
> +
> + /*
> + * Avoid dmcryptkeys from being stomped on in kdump kernel by
> + * setting up memory reserve map.
> + */
> + ret = fdt_add_mem_rsv(fdt, image->dm_crypt_keys_addr,
> + image->dm_crypt_keys_sz);
> + if (ret)
> + goto out;
> + }
> +
> #ifdef CONFIG_CRASH_DUMP
> /* add linux,usable-memory-range */
> ret = fdt_appendprop_addrrange(fdt, 0, chosen_node,
The above changes look good to me.
Feel free to add:
Reviewed-by: Sourabh Jain <sourabhjain@linux.ibm.com>
But while reading crash_load_dm_crypt_keys() I noticed a possibility of a
double free at the address pointed by `keys_header`:
In crash_load_dm_crypt_keys()/crash_dump_dm_crypt.c
snip...
kbuf.buffer = keys_header;
snip....
r = kexec_add_buffer(&kbuf);
if (r) {
pr_err("Failed to call kexec_add_buffer, ret=%d\n", r);
kvfree((void *)kbuf.buffer); <---
First Free
return r;
}
Since `keys_header` is not reset, the next call to build_keys_header()
will cause a double free at `keys_header`.
static int build_keys_header(void)
{
snip...
if (keys_header != NULL)
kvfree(keys_header);
snip...
}
What do you think?
- Sourabh Jain
^ permalink raw reply
* [PATCH 4/5] arm64: dts: freescale: imx93-phyboard-nash: Add gpio-line-names
From: Florijan Plohl @ 2026-04-02 10:56 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, upstream
In-Reply-To: <20260402105613.1303871-1-florijan.plohl@norik.com>
Add gpio-line-names for GPIOs with a defined board-level
function on the PHYTEC phyBOARD-Nash-i.MX93.
Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
---
.../dts/freescale/imx93-phyboard-nash.dts | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
index eac389ed30f3..b82192f25498 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
@@ -141,6 +141,37 @@ &flexcan1 {
status = "okay";
};
+&gpio1 {
+ gpio-line-names = "", "USER_LED", "I2C2_SCL", "I2C2_SDA";
+};
+
+&gpio2 {
+ gpio-line-names = "SPI6_CS0", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "TPM_nIRQ", "", "",
+ "", "", "", "", "",
+ "", "", "", "I2C3_SDA", "I2C3_SCL";
+};
+
+&gpio3 {
+ gpio-line-names = "SD2_nCD", "", "", "", "",
+ "", "", "SD2_nRESET", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "nENET1_INT";
+};
+
+&gpio4 {
+ gpio-line-names = "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "nCAN_EN", "", "", "",
+ "", "", "", "RESET_PHY", "",
+ "", "RTC_nINT", "PMIC_IRQ_B";
+};
+
/* I2C2 */
&lpi2c2 {
clock-frequency = <400000>;
--
2.43.0
^ permalink raw reply related
* [PATCH 1/5] arm64: dts: freescale: imx91-phycore-som: Add gpio-line-names
From: Florijan Plohl @ 2026-04-02 10:56 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, upstream
Add gpio-line-names for GPIOs with a defined board-level
function on the PHYTEC phyCORE-i.MX91 SoM.
Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
---
.../boot/dts/freescale/imx91-phycore-som.dtsi | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi
index 29a428a052b0..b9a453f6b290 100644
--- a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi
@@ -88,6 +88,28 @@ ethphy1: ethernet-phy@1 {
};
};
+&gpio1 {
+ gpio-line-names = "", "USER_LED";
+};
+
+&gpio2 {
+ gpio-line-names = "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "I2C3_SDA", "I2C3_SCL";
+};
+
+&gpio4 {
+ gpio-line-names = "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "RESET_PHY", "",
+ "", "", "PMIC_IRQ_B";
+};
+
/* I2C3 */
&lpi2c3 {
clock-frequency = <400000>;
--
2.43.0
^ permalink raw reply related
* [PATCH 5/5] arm64: dts: freescale: imx93-phyboard-segin: Add gpio-line-names
From: Florijan Plohl @ 2026-04-02 10:56 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, upstream
In-Reply-To: <20260402105613.1303871-1-florijan.plohl@norik.com>
Add gpio-line-names for GPIOs with a defined board-level
function on the PHYTEC phyBOARD-Segin-i.MX93.
Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
---
.../dts/freescale/imx93-phyboard-segin.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
index a982606de1ee..4e4356397ba0 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
@@ -145,6 +145,24 @@ &flexcan1 {
status = "okay";
};
+&gpio1 {
+ gpio-line-names = "", "USER_LED", "I2C1_SCL", "I2C1_SDA";
+};
+
+&gpio3 {
+ gpio-line-names = "SD1_nCD", "", "", "", "",
+ "", "", "SD1_nRESET";
+};
+
+&gpio4 {
+ gpio-line-names = "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "CAN_EN", "", "", "",
+ "", "", "", "RESET_PHY", "",
+ "", "RTC_nINT", "PMIC_IRQ_B";
+};
+
/* I2C2 */
&lpi2c2 {
clock-frequency = <400000>;
--
2.43.0
^ permalink raw reply related
* [PATCH 3/5] arm64: dts: freescale: imx93-phycore-som: Add gpio-line-names
From: Florijan Plohl @ 2026-04-02 10:56 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, upstream
In-Reply-To: <20260402105613.1303871-1-florijan.plohl@norik.com>
Add gpio-line-names for GPIOs with a defined board-level
function on the PHYTEC phyCORE-i.MX93 SoM.
Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
---
.../boot/dts/freescale/imx93-phycore-som.dtsi | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
index ebc57841f27f..94eb04ace96e 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
@@ -90,6 +90,28 @@ ethphy1: ethernet-phy@1 {
};
};
+&gpio1 {
+ gpio-line-names = "", "USER_LED";
+};
+
+&gpio2 {
+ gpio-line-names = "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "I2C3_SDA", "I2C3_SCL";
+};
+
+&gpio4 {
+ gpio-line-names = "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "RESET_PHY", "",
+ "", "", "PMIC_IRQ_B";
+};
+
/* I2C3 */
&lpi2c3 {
clock-frequency = <400000>;
--
2.43.0
^ permalink raw reply related
* [PATCH 2/5] arm64: dts: freescale: imx91-phyboard-segin: Add gpio-line-names
From: Florijan Plohl @ 2026-04-02 10:56 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, upstream
In-Reply-To: <20260402105613.1303871-1-florijan.plohl@norik.com>
Add gpio-line-names for GPIOs with a defined board-level
function on the PHYTEC phyBOARD-Segin-i.MX91.
Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
---
.../dts/freescale/imx91-phyboard-segin.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts
index 7b18a58024f5..8b19fc17eacd 100644
--- a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts
@@ -137,6 +137,24 @@ ethphy2: ethernet-phy@2 {
};
};
+&gpio1 {
+ gpio-line-names = "", "USER_LED", "I2C1_SCL", "I2C1_SDA";
+};
+
+&gpio3 {
+ gpio-line-names = "SD1_nCD", "", "", "", "",
+ "", "", "SD1_nRESET";
+};
+
+&gpio4 {
+ gpio-line-names = "", "", "", "", "",
+ "", "", "", "", "",
+ "", "", "", "", "",
+ "", "CAN_EN", "", "", "",
+ "", "", "", "RESET_PHY", "",
+ "", "RTC_nINT", "PMIC_IRQ_B";
+};
+
/* CAN */
&flexcan1 {
pinctrl-names = "default";
--
2.43.0
^ permalink raw reply related
* [PATCH v1 02/22] reset: starfive: Convert the word "jh71x0" to "starfive"
From: Changhuang Liang @ 2026-04-02 10:55 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran
Cc: linux-clk, linux-kernel, devicetree, linux-riscv, linux-hardening,
netdev, Sia Jee Heng, Hal Feng, Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260402105523.447523-1-changhuang.liang@starfivetech.com>
From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Function names that consist of the 'jh71x0' naming convention are
renamed to use the 'starfive' wording.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clk/starfive/clk-starfive-jh7110-sys.c | 4 +-
.../reset/starfive/reset-starfive-common.c | 64 +++++++++----------
.../reset/starfive/reset-starfive-common.h | 8 +--
.../reset/starfive/reset-starfive-jh7100.c | 2 +-
.../reset/starfive/reset-starfive-jh7110.c | 4 +-
include/soc/starfive/reset-starfive-common.h | 6 +-
6 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index edf4c45e6ff0..17fd061ee196 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -334,7 +334,7 @@ static void jh7110_reset_unregister_adev(void *_adev)
static void jh7110_reset_adev_release(struct device *dev)
{
struct auxiliary_device *adev = to_auxiliary_dev(dev);
- struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev);
+ struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev);
kfree(rdev);
}
@@ -343,7 +343,7 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
const char *adev_name,
u32 adev_id)
{
- struct jh71x0_reset_adev *rdev;
+ struct starfive_reset_adev *rdev;
struct auxiliary_device *adev;
int ret;
diff --git a/drivers/reset/starfive/reset-starfive-common.c b/drivers/reset/starfive/reset-starfive-common.c
index d615c4a68cc0..772bdf6763d1 100644
--- a/drivers/reset/starfive/reset-starfive-common.c
+++ b/drivers/reset/starfive/reset-starfive-common.c
@@ -14,7 +14,7 @@
#include "reset-starfive-common.h"
-struct jh71x0_reset {
+struct starfive_reset {
struct reset_controller_dev rcdev;
/* protect registers against concurrent read-modify-write */
spinlock_t lock;
@@ -23,16 +23,16 @@ struct jh71x0_reset {
const u32 *asserted;
};
-static inline struct jh71x0_reset *
-jh71x0_reset_from(struct reset_controller_dev *rcdev)
+static inline struct starfive_reset *
+starfive_reset_from(struct reset_controller_dev *rcdev)
{
- return container_of(rcdev, struct jh71x0_reset, rcdev);
+ return container_of(rcdev, struct starfive_reset, rcdev);
}
-static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
- unsigned long id, bool assert)
+static int starfive_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
{
- struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
+ struct starfive_reset *data = starfive_reset_from(rcdev);
unsigned long offset = id / 32;
u32 mask = BIT(id % 32);
void __iomem *reg_assert = data->assert + offset * sizeof(u32);
@@ -61,34 +61,34 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
return ret;
}
-static int jh71x0_reset_assert(struct reset_controller_dev *rcdev,
- unsigned long id)
+static int starfive_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
{
- return jh71x0_reset_update(rcdev, id, true);
+ return starfive_reset_update(rcdev, id, true);
}
-static int jh71x0_reset_deassert(struct reset_controller_dev *rcdev,
- unsigned long id)
+static int starfive_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
{
- return jh71x0_reset_update(rcdev, id, false);
+ return starfive_reset_update(rcdev, id, false);
}
-static int jh71x0_reset_reset(struct reset_controller_dev *rcdev,
- unsigned long id)
+static int starfive_reset_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
{
int ret;
- ret = jh71x0_reset_assert(rcdev, id);
+ ret = starfive_reset_assert(rcdev, id);
if (ret)
return ret;
- return jh71x0_reset_deassert(rcdev, id);
+ return starfive_reset_deassert(rcdev, id);
}
-static int jh71x0_reset_status(struct reset_controller_dev *rcdev,
- unsigned long id)
+static int starfive_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
{
- struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
+ struct starfive_reset *data = starfive_reset_from(rcdev);
unsigned long offset = id / 32;
u32 mask = BIT(id % 32);
void __iomem *reg_status = data->status + offset * sizeof(u32);
@@ -100,25 +100,25 @@ static int jh71x0_reset_status(struct reset_controller_dev *rcdev,
return !((value ^ data->asserted[offset]) & mask);
}
-static const struct reset_control_ops jh71x0_reset_ops = {
- .assert = jh71x0_reset_assert,
- .deassert = jh71x0_reset_deassert,
- .reset = jh71x0_reset_reset,
- .status = jh71x0_reset_status,
+static const struct reset_control_ops starfive_reset_ops = {
+ .assert = starfive_reset_assert,
+ .deassert = starfive_reset_deassert,
+ .reset = starfive_reset_reset,
+ .status = starfive_reset_status,
};
-int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
- void __iomem *assert, void __iomem *status,
- const u32 *asserted, unsigned int nr_resets,
- struct module *owner)
+int reset_starfive_register(struct device *dev, struct device_node *of_node,
+ void __iomem *assert, void __iomem *status,
+ const u32 *asserted, unsigned int nr_resets,
+ struct module *owner)
{
- struct jh71x0_reset *data;
+ struct starfive_reset *data;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
- data->rcdev.ops = &jh71x0_reset_ops;
+ data->rcdev.ops = &starfive_reset_ops;
data->rcdev.owner = owner;
data->rcdev.nr_resets = nr_resets;
data->rcdev.dev = dev;
@@ -131,4 +131,4 @@ int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_no
return devm_reset_controller_register(dev, &data->rcdev);
}
-EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register);
+EXPORT_SYMBOL_GPL(reset_starfive_register);
diff --git a/drivers/reset/starfive/reset-starfive-common.h b/drivers/reset/starfive/reset-starfive-common.h
index 266acc4b2caf..83461b22ee55 100644
--- a/drivers/reset/starfive/reset-starfive-common.h
+++ b/drivers/reset/starfive/reset-starfive-common.h
@@ -6,9 +6,9 @@
#ifndef __RESET_STARFIVE_COMMON_H
#define __RESET_STARFIVE_COMMON_H
-int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
- void __iomem *assert, void __iomem *status,
- const u32 *asserted, unsigned int nr_resets,
- struct module *owner);
+int reset_starfive_register(struct device *dev, struct device_node *of_node,
+ void __iomem *assert, void __iomem *status,
+ const u32 *asserted, unsigned int nr_resets,
+ struct module *owner);
#endif /* __RESET_STARFIVE_COMMON_H */
diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
index 546dea2e5811..122ac6c3893b 100644
--- a/drivers/reset/starfive/reset-starfive-jh7100.c
+++ b/drivers/reset/starfive/reset-starfive-jh7100.c
@@ -51,7 +51,7 @@ static int __init jh7100_reset_probe(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
- return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node,
+ return reset_starfive_register(&pdev->dev, pdev->dev.of_node,
base + JH7100_RESET_ASSERT0,
base + JH7100_RESET_STATUS0,
jh7100_reset_asserted,
diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c
index 87dba01491ae..c4dd21761e53 100644
--- a/drivers/reset/starfive/reset-starfive-jh7110.c
+++ b/drivers/reset/starfive/reset-starfive-jh7110.c
@@ -53,13 +53,13 @@ static int jh7110_reset_probe(struct auxiliary_device *adev,
const struct auxiliary_device_id *id)
{
struct jh7110_reset_info *info = (struct jh7110_reset_info *)(id->driver_data);
- struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev);
+ struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev);
void __iomem *base = rdev->base;
if (!info || !base)
return -ENODEV;
- return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node,
+ return reset_starfive_register(&adev->dev, adev->dev.parent->of_node,
base + info->assert_offset,
base + info->status_offset,
NULL,
diff --git a/include/soc/starfive/reset-starfive-common.h b/include/soc/starfive/reset-starfive-common.h
index 56d8f413cf18..16df46a074bc 100644
--- a/include/soc/starfive/reset-starfive-common.h
+++ b/include/soc/starfive/reset-starfive-common.h
@@ -6,12 +6,12 @@
#include <linux/compiler_types.h>
#include <linux/container_of.h>
-struct jh71x0_reset_adev {
+struct starfive_reset_adev {
void __iomem *base;
struct auxiliary_device adev;
};
-#define to_jh71x0_reset_adev(_adev) \
- container_of((_adev), struct jh71x0_reset_adev, adev)
+#define to_starfive_reset_adev(_adev) \
+ container_of((_adev), struct starfive_reset_adev, adev)
#endif
--
2.25.1
^ permalink raw reply related
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