* Re: [PATCH v20 06/10] power: reset: Add psci-reboot-mode driver
From: Shivendra Pratap @ 2026-04-02 18:38 UTC (permalink / raw)
To: Arnd Bergmann, Lorenzo Pieralisi
Cc: Bjorn Andersson, Sebastian Reichel, Rob Herring,
Souvik Chakravarty, Krzysztof Kozlowski, Andy Yan,
Matthias Brugger, Mark Rutland, Conor Dooley, Konrad Dybcio,
John Stultz, Moritz Fischer, Bartosz Golaszewski, Sudeep Holla,
Florian Fainelli, Krzysztof Kozlowski, Dmitry Baryshkov,
Mukesh Ojha, André Draszik, Kathiravan Thirumoorthy,
linux-pm, linux-kernel, linux-arm-kernel, linux-arm-msm,
devicetree, Srinivas Kandagatla
In-Reply-To: <f6ed07b1-8bfc-49ea-951e-b590bf8b299a@app.fastmail.com>
On 01-04-2026 20:26, Arnd Bergmann wrote:
> On Wed, Apr 1, 2026, at 16:37, Lorenzo Pieralisi wrote:
>> On Tue, Mar 31, 2026 at 11:30:09PM +0530, Shivendra Pratap wrote:
>>>
>>>>> +#include <linux/err.h>
>>>>> +#include <linux/of.h>
>>>>> +#include <linux/psci.h>
>>>>> +#include <linux/reboot.h>
>>>>> +#include <linux/reboot-mode.h>
>>>>> +#include <linux/types.h>
>>>>> +
>>>>> +/*
>>>>> + * Predefined reboot-modes are defined as per the values
>>>>> + * of enum reboot_mode defined in the kernel: reboot.c.
>>>>> + */
>>>>> +static struct mode_info psci_resets[] = {
>>>>> + { .mode = "warm", .magic = REBOOT_WARM},
>>>>> + { .mode = "soft", .magic = REBOOT_SOFT},
>>>>> + { .mode = "cold", .magic = REBOOT_COLD},
>>
>> These strings match the command userspace issue right ? I think that we
>> should make them match the corresponding PSCI reset types, the list above
>> maps command to reboot_mode values and those can belong to any reboot
>> mode driver to be honest they don't make much sense in a PSCI reboot
>> mode driver only.
>>
>> It is a question for everyone here: would it make sense to make these
>> predefined resets a set of strings, eg:
>>
>> psci-system-reset
>> psci-system-reset2-arch-warm-reset
>>
>> and then vendor resets:
>>
>> psci-system-reset2-vendor-reset
>>
>> at least we know what a string maps to ?
>>
>> We can export a function from the PSCI driver to detect whether PSCI
>> SYSTEM_RESET2 is supported, an equivalent of psci_has_osi_support() for
>> instance that we can call from this driver to detect its presence.
>
> Sorry I've been out of the loop for this series for a while, but
> can someone refresh me on why we got back to mixing in
> the 'enum reboot_mode' from legacy i386 and arm32 into the new
> interface?
>
> I don't mind having whichever strings are defined for PSCI present
> in the user interface, but this seems like a mistake to me.
> If at all possible, lets define your own magic constants that
> are not tied to "enum reboot_mode" or the legacy reboot= command
> line argument.
sure. will remove usage of "enum reboot_mode".
thanks,
Shivendra
^ permalink raw reply
* Re: [PATCH v10 6/6] usb: typec: tcpm/tcpci_maxim: deprecate WAR for setting charger mode
From: Amit Sunil Dhamne @ 2026-04-02 18:47 UTC (permalink / raw)
To: Heikki Krogerus
Cc: André Draszik, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Jagan Sridharan, Mark Brown,
Matti Vaittinen, Andrew Morton, Sebastian Reichel, Peter Griffin,
Tudor Ambarus, Alim Akhtar, linux-kernel, devicetree, linux-usb,
linux-pm, linux-arm-kernel, linux-samsung-soc, RD Babiera,
Kyle Tso
In-Reply-To: <ac5-OzwQkczTWtMg@kuha>
Hi Heikki,
On 4/2/26 7:33 AM, Heikki Krogerus wrote:
> Hi Amit,
>
>> +static int get_vbus_regulator_handle(struct max_tcpci_chip *chip)
>> +{
>> + if (IS_ERR_OR_NULL(chip->vbus_reg)) {
>> + chip->vbus_reg = devm_regulator_get_exclusive(chip->dev,
>> + "vbus");
> Sorry to go back to this, but why can't you just get the regulator in
> max_tcpci_probe()?
Thanks for calling this out. This was an intentional design decision to
break a circular dependency.
The charger driver is guaranteed to probe after the TCPC driver due to a
power supply dependency (the TCPC is a supplier of power for the Battery
Charger). However, the charger driver is also the regulator provider for
VBUS out (when Type-C goes into source mode).
Because of this, the regulator handle will not be available during the
TCPC driver's probe. If we tried to fetch it in max_tcpci_probe() and
returned -EPROBE_DEFER, it would create a probe deadlock, as the charger
would then never probe. Therefore, I made the decision to get the
regulator handle lazily and on-demand.
Thanks,
Amit
>
> thanks,
>
>> + if (IS_ERR_OR_NULL(chip->vbus_reg)) {
>> + dev_err(chip->dev,
>> + "Failed to get vbus regulator handle\n");
>> + return -ENODEV;
>> + }
>> + }
>> +
>> + return 0;
>> +}
^ permalink raw reply
* Re: [PATCH v9 00/13] ASoC: qcom: q6dsp: few fixes and enhancements
From: Mark Brown @ 2026-04-02 15:35 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Srinivas Kandagatla
Cc: mohammad.rafi.shaik, linux-sound, lgirdwood, perex, tiwai, johan,
dmitry.baryshkov, konrad.dybcio, linux-arm-msm, devicetree,
linux-kernel, srini, val, mailingradian
In-Reply-To: <20260402081118.348071-1-srinivas.kandagatla@oss.qualcomm.com>
On Thu, 02 Apr 2026 08:11:05 +0000, Srinivas Kandagatla wrote:
> ASoC: qcom: q6dsp: few fixes and enhancements
>
> This patchset contains few fixes for the bugs hit during testing with
> Monza EVK platform
> - around array out of bounds access on dai ids which keep extending but
> the drivers seems to have hardcoded some numbers, fix this and clean
> the mess up
> - fix few issues discovered while trying to shut down dsp.
> - flooding rpmsg with write requests due to not resetting queue pointer,
> fix this resetting the pointer in trigger stop.
> - possible multiple graph opens which can result in open failures.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-7.1
Thanks!
[01/13] ASoC: qcom: q6apm: move component registration to unmanaged version
https://git.kernel.org/broonie/sound/c/6ec1235fc941
[02/13] ASoC: qcom: q6apm: remove child devices when apm is removed
https://git.kernel.org/broonie/sound/c/4a0e1bcc98f7
[03/13] ASoC: qcom: qdsp6: topology: check widget type before accessing data
https://git.kernel.org/broonie/sound/c/d5bfdd28e0cd
[04/13] ASoC: qcom: q6apm-lpass-dai: Fix multiple graph opens
https://git.kernel.org/broonie/sound/c/69acc488aaf3
[05/13] ASoC: qcom: q6apm-dai: reset queue ptr on trigger stop
https://git.kernel.org/broonie/sound/c/cab45ab95ce7
[06/13] ASoC: dt-bindings: qcom: add LPASS LPI MI2S dai ids
https://git.kernel.org/broonie/sound/c/e46957f27c60
[07/13] ASoC: qcom: common: validate cpu dai id during parsing
https://git.kernel.org/broonie/sound/c/d49ee8faefec
[08/13] ASoC: qcom: qdsp6: lpass-ports: add support for LPASS LPI MI2S dais
https://git.kernel.org/broonie/sound/c/bcd0df1ebc9d
[09/13] ASoC: qcom: q6dsp: Add Senary MI2S audio interface support
https://git.kernel.org/broonie/sound/c/ae0de4e50f8f
[10/13] ASoC: qcom: qdapm-lpass-dai: correct the error message
https://git.kernel.org/broonie/sound/c/8f542c7c4aa9
[11/13] ASoC: qcom: q6apm-lpass-dai: move graph start to trigger
https://git.kernel.org/broonie/sound/c/b54a38af7138
[12/13] ASoC: qcom: qdsp6: remove search for module iid in hot path
https://git.kernel.org/broonie/sound/c/d8b4163038dc
[13/13] ASoC: qcom: q6apm: Add support for early buffer mapping on DSP
https://git.kernel.org/broonie/sound/c/8ea6e25c8536
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* Re: [PATCH v4 0/6] media: iris: enable SM8350 and SC8280XP support
From: Vikash Garodia @ 2026-04-02 19:18 UTC (permalink / raw)
To: Steev Klimaszewski, dmitry.baryshkov
Cc: abhinav.kumar, andersson, bod, bryan.odonoghue, conor+dt, david,
devicetree, dikshita.agarwal, johan+linaro, konrad.dybcio,
konradybcio, krzk+dt, linux-arm-msm, linux-kernel, linux-media,
mchehab, robh, stanimir.varbanov
In-Reply-To: <20260402183209.27159-1-threeway@gmail.com>
Hi Steev, Dmitry,
On 4/3/2026 12:02 AM, Steev Klimaszewski wrote:
> Hi Dmitry,
>
>> Thanks for the additional testing!
>
>> This might be:
>> - A bug in the firmware
>> - A bug in the Gen1 support in the Iris driver.
>> - A bug in totem (heh).
>
>> Would you mind sharing details, which video were you trying to play (at
>> least, the codec that it used, please).
>
>> Also, does it kill the playback afterwards? Can you start another
>> playing stream afterwards?
>
> The video that does not work seems to be
>
> Metadata:
> major_brand : M4V
> minor_version : 1
> compatible_brands: isomavc1mp42
> creation_time : 2025-08-04T19:42:21.000000Z
> Duration: 00:00:35.24, start: 0.000000, bitrate: 6291 kb/s
> Stream #0:0[0x1](und): Video: h264 (High) (avc1 / 0x31637661), yuv420p(progressive), 1280x720 [SAR 1:1 DAR 16:9], 6126 kb/s, 23.98 fps, 23.98 tbr, 24k tbn (default)
> Metadata:
> creation_time : 2025-08-04T19:42:21.000000Z
> handler_name : ETI ISO Video Media Handler
> vendor_id : [0][0][0][0]
> encoder : Elemental H.264
> Stream #0:1[0x2](und): Audio: aac (LC) (mp4a / 0x6134706D), 48000 Hz, stereo, fltp, 159 kb/s (default)
>
>
> However, a video that *does* work is
>
> Stream #0:0: Video: av1 (libdav1d) (Main), yuv420p(tv, bt709), 1920x1080, 23.98 fps, 23.98 tbr, 1k tbn
> Metadata:
> HANDLER_NAME : ISO Media file produced by Google Inc.
> VENDOR_ID : [0][0][0][0]
> DURATION : 00:05:16.732000000
> Stream #0:1(eng): Audio: opus, 48000 Hz, stereo, fltp, start 0.007000
> Metadata:
> DURATION : 00:05:16.744000000
> Stream #0:2: Video: mjpeg (Baseline), yuvj420p(pc, bt470bg/unknown/unknown), 1280x720, 90k tbr, 90k tbn (attached pic)
> Metadata:
> filename : cover.jpg
> mimetype : image/jpeg
>
> I do not have a ton of videos to test, so I just used 2 that are on my system.
>
> This is not just with totem, showtime shows the same issue. If I let the video
> play, it plays just fine, however, if I attempt to skip forward, back, or even
> play *after* the video has played, then I see the smmu fault
>
> arm-smmu 15000000.iommu: Unhandled context fault: fsr=0x402, iova=0xd51e3e00, fsynr=0x600002, cbfrsynra=0x2a00, cb=6
please log the info about which "iova=0xd51e3e00" buffer is faulting in
this case
Regards,
Vikash
> arm-smmu 15000000.iommu: FSR = 00000402 [Format=2 TF], SID=0x2a00
> arm-smmu 15000000.iommu: FSYNR0 = 00600002 [S1CBNDX=96 PLVL=2]
> qcom-iris aa00000.video-codec: sys error (type: 1, session id:ff, data1:1, data2:deadbead)
>
> If I exit and re-launch totem, it will play the video through, but again, if I
> attempt to skip forward, back or play once it has finished the video, then again
> the smmu fault occurs.
>
> totem and showtime both use gstreamer, and show the issue. showtime replaces
> totem as the media player on modern gnome systems. mpv and vlc do *not* show
> the issue, but they also do not appear to use iris/venus at all.
>
> Totem is version 43.2-11
> Showtime is version 50~rc2
>
> Host system is Kali, which is essentially Debian Testing.
>
> -- steev
^ permalink raw reply
* Re: [PATCH v4 0/6] media: iris: enable SM8350 and SC8280XP support
From: Vikash Garodia @ 2026-04-02 19:21 UTC (permalink / raw)
To: Dmitry Baryshkov, Dikshita Agarwal, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Konrad Dybcio, Abhinav Kumar, Bjorn Andersson,
David Heidelberg, Stanimir Varbanov
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio, Johan Hovold, Bryan O'Donoghue
In-Reply-To: <20260312-iris-sc8280xp-v4-0-a047ef1e3c7d@oss.qualcomm.com>
On 3/12/2026 8:44 PM, Dmitry Baryshkov wrote:
> In order to enable wider testing of the Iris driver on the HFI Gen1
> platforms enable support for Qualcomm SM8350 and SC8280XP platforms.
>
> Note, this has been tested only with the Iris driver. Venus driver fails
> to boot the Iris core on SM8350 pointing out the UC_REGION error.
>
> Note, the firmware for SM8250 isn't compatible with SM8350 (nor with
> SC8280XP). Please use corresponding firmware, extracted from the Windows
> / Android data.
>
> On SM8350 with the Iris driver:
>
> $ v4l2-compliance
> v4l2-compliance 1.30.1, 64 bits, 64-bit time_t
>
> Compliance test for iris_driver device /dev/video0:
>
> Driver Info:
> Driver name : iris_driver
> Card type : Iris Decoder
> Bus info : platform:aa00000.video-codec
> Driver version : 7.0.0
> Capabilities : 0x84204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Device Capabilities
> Device Caps : 0x04204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Detected Stateful Decoder
>
> Required ioctls:
> test VIDIOC_QUERYCAP: OK
> test invalid ioctls: OK
>
> Allow for multiple opens:
> test second /dev/video0 open: OK
> test VIDIOC_QUERYCAP: OK
> test VIDIOC_G/S_PRIORITY: OK
> test for unlimited opens: OK
>
> Debug ioctls:
> test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> test VIDIOC_LOG_STATUS: OK (Not Supported)
>
> Input ioctls:
> test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> test VIDIOC_ENUMAUDIO: OK (Not Supported)
> test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDIO: OK (Not Supported)
> Inputs: 0 Audio Inputs: 0 Tuners: 0
>
> Output ioctls:
> test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> Outputs: 0 Audio Outputs: 0 Modulators: 0
>
> Input/Output configuration ioctls:
> test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> test VIDIOC_G/S_EDID: OK (Not Supported)
>
> Control ioctls:
> test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> test VIDIOC_QUERYCTRL: OK
> test VIDIOC_G/S_CTRL: OK
> test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> Standard Controls: 2 Private Controls: 0
>
> Format ioctls:
> test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> test VIDIOC_G/S_PARM: OK (Not Supported)
> test VIDIOC_G_FBUF: OK (Not Supported)
> test VIDIOC_G_FMT: OK
> test VIDIOC_TRY_FMT: OK
> test VIDIOC_S_FMT: OK
> test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> test Cropping: OK
> test Composing: OK
> test Scaling: OK (Not Supported)
>
> Codec ioctls:
> test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
> test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> test VIDIOC_(TRY_)DECODER_CMD: OK
>
> Buffer ioctls:
> test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> test CREATE_BUFS maximum buffers: OK
> test VIDIOC_REMOVE_BUFS: OK
> test VIDIOC_EXPBUF: OK
> test Requests: OK (Not Supported)
> test blocking wait: OK
>
> Total for iris_driver device /dev/video0: 48, Succeeded: 48, Failed: 0, Warnings: 0
>
> |TOTALS|FFmpeg-H.265-v4l2m2m|GStreamer-H.265-V4L2-Gst1.0|FFmpeg-H.264-v4l2m2m|GStreamer-H.264-V4L2-Gst1.0|FFmpeg-VP9-v4l2m2m|GStreamer-VP9-V4L2-Gst1.0|
> |-|-|-|-|-|-|-|
> |TOTAL|169/316|128/316|154/447|126/447|159/311|229/311|
> |TOTAL TIME|242.251s|267.903s|293.458s|261.934s|203.009s|366.936s|
> |-|-|-|-|-|-|-|
> |Profile|FFmpeg-H.265-v4l2m2m|GStreamer-H.265-V4L2-Gst1.0|FFmpeg-H.264-v4l2m2m|GStreamer-H.264-V4L2-Gst1.0|FFmpeg-VP9-v4l2m2m|GStreamer-VP9-V4L2-Gst1.0|
could you list the failing cases and compare the result with sm8250 ?
Regards,
Vikash
> |BASELINE|0/0|0/0|3/7|4/7|0/0|0/0|
> |CAVLC_4_4_4|0/0|0/0|0/3|0/3|0/0|0/0|
> |CAVLC_4_4_4_INTRA|0/0|0/0|0/4|0/4|0/0|0/0|
> |CONSTRAINED_BASELINE|0/0|0/0|32/33|33/33|0/0|0/0|
> |EXTENDED|0/0|0/0|1/6|1/6|0/0|0/0|
> |HIGH|0/0|0/0|22/45|22/45|0/0|0/0|
> |HIGH_10|0/0|0/0|0/2|0/2|0/0|0/0|
> |HIGH_10_INTRA|0/0|0/0|0/7|0/7|0/0|0/0|
> |HIGH_4_2_2|0/0|0/0|0/21|0/21|0/0|0/0|
> |HIGH_4_2_2_INTRA|0/0|0/0|0/7|0/7|0/0|0/0|
> |HIGH_4_4_4_INTRA|0/0|0/0|0/6|0/6|0/0|0/0|
> |HIGH_4_4_4_PREDICTIVE|0/0|0/0|0/11|0/11|0/0|0/0|
> |MAIN|127/135|126/135|41/90|41/90|0/0|0/0|
> |MAIN_10|0/11|0/11|0/0|0/0|0/0|0/0|
> |MAIN_STILL_PICTURE|1/1|1/1|0/0|0/0|0/0|0/0|
> |-|-|-|-|-|-|-|
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> Changes in v4:
> - Changed compat strings to use -iris instead of -venus (Konrad,
> Dikshita)
> - Dropped separate schema file, switched to SM8250 schema
> - Dropped driver bits, it's covered by compatible string now
> - Link to v3: https://lore.kernel.org/r/20260125-iris-sc8280xp-v3-0-d21861a9ea33@oss.qualcomm.com
>
> Changes in v3:
> - Add missing header, sorry.
> - Link to v2: https://lore.kernel.org/r/20260125-iris-sc8280xp-v2-0-552cdc3ea691@oss.qualcomm.com
>
> Changes in v2:
> - Added missing chunk, including sm8350-videocc.h, lost in rebases.
> - Link to v1: https://lore.kernel.org/r/20260125-iris-sc8280xp-v1-0-2c5e69fae76b@oss.qualcomm.com
>
> ---
> Dmitry Baryshkov (4):
> media: dt-bindings: Document SC8280XP/SM8350 Iris
> arm64: dts: qcom: sc8280xp: sort reserved memory regions
> arm64: dts: qcom: sm8350: add Iris device
> arm64: dts: qcom: sm8350-hdk: enable Iris core
>
> Konrad Dybcio (2):
> arm64: dts: qcom: sc8280xp: Add Iris core
> arm64: dts: qcom: sc8280xp-x13s: Enable Iris
>
> .../bindings/media/qcom,sm8250-venus.yaml | 10 +-
> .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 ++
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 103 ++++++++++++++++++++-
> arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 6 ++
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 81 ++++++++++++++++
> 5 files changed, 202 insertions(+), 4 deletions(-)
> ---
> base-commit: a0ae2a256046c0c5d3778d1a194ff2e171f16e5f
> change-id: 20260120-iris-sc8280xp-85d13bc60536
> prerequisite-change-id: 20260131-iris-venus-fix-sm8250-f938e29e7497:v5
> prerequisite-patch-id: 6d85e3db422bc7f16246249288a17b92f6edbc09
> prerequisite-patch-id: 579d712ec3f942ba0c362e242c71361c151092b5
> prerequisite-patch-id: fa4629a3909fbae3917d8c067cce4f673ee857c0
> prerequisite-patch-id: cbbd40736f7a797ff76b0fe2b1ddfb559e14e666
> prerequisite-patch-id: 5b50917dcfef01db13af320cbd1cba15fd5fa16f
> prerequisite-patch-id: 8948139735836adb9fbc51d93b969911dc5b38e8
> prerequisite-patch-id: 7ec91bd0149f347c479c906e73cabaa28601ab3d
> prerequisite-patch-id: c711522b63f640b7504767b3af7adc05a0b36cac
> prerequisite-patch-id: 42b9cd5e0fd6fd99eae267c78b239333adff7637
> prerequisite-patch-id: 11c487545e2462ff0a515d689863c3f7f25f9449
> prerequisite-change-id: 20251119-venus-iris-flip-switch-d59a3fbc6a4b:v4
> prerequisite-patch-id: 615a763749fdc0c4ee184478bc64120972d8c7a1
> prerequisite-patch-id: 6d85e3db422bc7f16246249288a17b92f6edbc09
> prerequisite-patch-id: 579d712ec3f942ba0c362e242c71361c151092b5
> prerequisite-patch-id: fa4629a3909fbae3917d8c067cce4f673ee857c0
> prerequisite-patch-id: cbbd40736f7a797ff76b0fe2b1ddfb559e14e666
> prerequisite-patch-id: 5b50917dcfef01db13af320cbd1cba15fd5fa16f
>
> Best regards,
^ permalink raw reply
* Re: [PATCH v10 0/6] mfd: Add support for NXP MC33978/MC34978 MSDI
From: Oleksij Rempel @ 2026-04-02 20:09 UTC (permalink / raw)
To: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lee Jones, Peter Rosin, Linus Walleij
Cc: kernel, linux-kernel, devicetree, linux-hwmon, linux-gpio,
David Jander
In-Reply-To: <20260402174349.3220518-1-o.rempel@pengutronix.de>
https://sashiko.dev/#/patchset/20260402174349.3220518-1-o.rempel%40pengutronix.de
TL;DR: Sashiko's analysis of the phantom transient fault interrupt is
correct, but the behavior is an acceptable compromise given the hardware
limitations. I would be glad if this driver could be accepted without
additional modifications, as it has already passed human review and
addressed 99% of bot comments.
---
The MC33978/MC34978 hardware's interrupt architecture is problematic:
1. INT_B is clear-on-read for *any* SPI transaction.
2. For persistent faults, INT_B immediately re-asserts if the fault remains.
3. Fault flags are latched and only cleared when the hwmon child reads
the FAULT register.
If the core driver passed the raw hardware state, the system would hang
in an interrupt storm (INT_B low -> SPI read clears it -> hardware
re-asserts -> repeat).
To prevent this storm, the core implements a software edge-detection
cache. When the hwmon child finally clears the fault latch, the core's
cache gets out of sync. Re-syncing it requires the synthetic wake bit
mentioned in the report, which causes the spurious interrupt edge.
The result is just one extra hwmon wakeup/SPI read when a fault clears.
Working around this would require more complexity. Trading one spurious
interrupt to prevent a hardware interrupt storm is an acceptable cost
for this silicon.
On Thu, Apr 02, 2026 at 07:43:43PM +0200, Oleksij Rempel wrote:
> changes v7:
> - drop gpiolib irq fix and make pinctrl more robust against NULL point
> dereference.
>
> This series adds support for the NXP MC33978/MC34978 Multiple Switch Detection
> Interface (MSDI) via the MFD framework.
>
> Architecture overview:
> * mfd: Core driver handling 2-frame pipelined SPI, regulator sequencing, and
> linear irq_domain. Harvests status bits from SPI MISO MSB.
> * pinctrl: Exposes 22 physical switch inputs as standard GPIOs. Proxies IRQs to
> the MFD domain.
> * hwmon: Exposes thermal limits, VBATP/VDDQ voltage boundaries, and dynamic
> fault alarms.
> * mux: Controls the 24-to-1 AMUX routing analog signals (switch voltages,
> temperature, VBATP) to an external ADC.
>
> Initial pinctrl implementation by David Jander, reworked into this MFD
> architecture.
>
> Best regards,
> Oleksij
>
> David Jander (1):
> pinctrl: add NXP MC33978/MC34978 pinctrl driver
>
> Oleksij Rempel (5):
> dt-bindings: pinctrl: add NXP MC33978/MC34978 MSDI
> mfd: add NXP MC33978/MC34978 core driver
> pinctrl: core: Make pin group callbacks optional for pin-only drivers
> hwmon: add NXP MC33978/MC34978 driver
> mux: add NXP MC33978/MC34978 AMUX driver
>
> .../bindings/pinctrl/nxp,mc33978.yaml | 158 +++
> drivers/hwmon/Kconfig | 10 +
> drivers/hwmon/Makefile | 1 +
> drivers/hwmon/mc33978-hwmon.c | 549 +++++++++
> drivers/mfd/Kconfig | 15 +
> drivers/mfd/Makefile | 2 +
> drivers/mfd/mc33978.c | 1088 +++++++++++++++++
> drivers/mux/Kconfig | 14 +
> drivers/mux/Makefile | 2 +
> drivers/mux/mc33978-mux.c | 141 +++
> drivers/pinctrl/Kconfig | 16 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/core.c | 41 +-
> drivers/pinctrl/pinconf.c | 9 +-
> drivers/pinctrl/pinctrl-mc33978.c | 1008 +++++++++++++++
> include/linux/mfd/mc33978.h | 95 ++
> 16 files changed, 3143 insertions(+), 7 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/nxp,mc33978.yaml
> create mode 100644 drivers/hwmon/mc33978-hwmon.c
> create mode 100644 drivers/mfd/mc33978.c
> create mode 100644 drivers/mux/mc33978-mux.c
> create mode 100644 drivers/pinctrl/pinctrl-mc33978.c
> create mode 100644 include/linux/mfd/mc33978.h
>
> --
> 2.47.3
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* Re: [RFC PATCH 1/1] dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU
From: Drew Fustini @ 2026-04-02 20:35 UTC (permalink / raw)
To: Joel Stanley, Joerg Roedel
Cc: Nicholas Piggin, devicetree, Tomasz Jeznach, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, linux-riscv, linux-kernel,
Michael Ellerman
In-Reply-To: <CACPK8Xc=imZXXPp-CYY39=Ww4oVDdXPS5My_R1qODzGhOD2qnw@mail.gmail.com>
On Wed, Apr 01, 2026 at 11:57:57AM +1030, Joel Stanley wrote:
> On Tue, 10 Mar 2026 at 11:09, Nicholas Piggin <npiggin@gmail.com> wrote:
> >
> > Extend the binding to cover details specific to the Tenstorrent RISC-V
> > IOMMU. In particular, a second register range is added which contains
> > M-privileged registers, e.g., PMAs and PMPs.
> >
> > The RISC-V spec S-privileged registers remain in the first register
> > range and are compatible with "riscv,iommu" so the Linux driver does not
> > notice any difference, but the binding will be used by OpenSBI and
> > potentially other M-mode software.
> >
> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>
> Reviewed-by: Joel Stanley <joel@jms.id.au>
>
> Drew, will you take this through the the tt soc tree?
I think it would go through Joerg's iommu tree, but I could if Joerg can
an Ack.
Thanks,
Drew
^ permalink raw reply
* Re: [PATCH 2/2] pinctrl: qcom: Add Hawi pinctrl driver
From: Bjorn Andersson @ 2026-04-02 21:18 UTC (permalink / raw)
To: Mukesh Ojha
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, linux-gpio, devicetree, linux-kernel,
Konrad Dybcio
In-Reply-To: <20260401-hawi-pinctrl-v1-2-4718da24e531@oss.qualcomm.com>
On Wed, Apr 01, 2026 at 05:22:08PM +0530, Mukesh Ojha wrote:
> Add pinctrl driver for TLMM block found in the Hawi SoC.
>
For everyone's information, I had a couple of comments about the
function names that was missed in this version.
Not repeating them here, but I've asked Mukesh to send a v2.
Regards,
Bjorn
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> ---
> drivers/pinctrl/qcom/Kconfig.msm | 10 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-hawi.c | 1716 +++++++++++++++++++++++++++++++++++
> 3 files changed, 1727 insertions(+)
>
> diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm
> index 6df6159fa5f8..63c88cbf2381 100644
> --- a/drivers/pinctrl/qcom/Kconfig.msm
> +++ b/drivers/pinctrl/qcom/Kconfig.msm
> @@ -35,6 +35,16 @@ config PINCTRL_GLYMUR
> Say Y here to compile statically, or M here to compile it as a module.
> If unsure, say N.
>
> +config PINCTRL_HAWI
> + tristate "Qualcomm Technologies Inc Hawi pin controller driver"
> + depends on ARM64 || COMPILE_TEST
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> + Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
> + block found on the Qualcomm Technologies Inc Hawi platform.
> + Say Y here to compile statically, or M here to compile it as a module.
> + If unsure, say N.
> +
> config PINCTRL_IPQ4019
> tristate "Qualcomm IPQ4019 pin controller driver"
> depends on ARM || COMPILE_TEST
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index a8fd12f90d6e..dc6457e69a02 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
> obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
> obj-$(CONFIG_PINCTRL_ELIZA) += pinctrl-eliza.o
> obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o
> +obj-$(CONFIG_PINCTRL_HAWI) += pinctrl-hawi.o
> obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
> obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
> obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-hawi.c b/drivers/pinctrl/qcom/pinctrl-hawi.c
> new file mode 100644
> index 000000000000..3c0648a6931a
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-hawi.c
> @@ -0,0 +1,1716 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +
> +#include "pinctrl-msm.h"
> +
> +#define REG_SIZE 0x1000
> +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
> + { \
> + .grp = PINCTRL_PINGROUP("gpio" #id, \
> + gpio##id##_pins, \
> + ARRAY_SIZE(gpio##id##_pins)), \
> + .funcs = (int[]){ \
> + msm_mux_gpio, /* gpio mode */ \
> + msm_mux_##f1, \
> + msm_mux_##f2, \
> + msm_mux_##f3, \
> + msm_mux_##f4, \
> + msm_mux_##f5, \
> + msm_mux_##f6, \
> + msm_mux_##f7, \
> + msm_mux_##f8, \
> + msm_mux_##f9, \
> + msm_mux_##f10, \
> + msm_mux_##f11 /* egpio mode */ \
> + }, \
> + .nfuncs = 12, \
> + .ctl_reg = REG_SIZE * id, \
> + .io_reg = 0x4 + REG_SIZE * id, \
> + .intr_cfg_reg = 0x8 + REG_SIZE * id, \
> + .intr_status_reg = 0xc + REG_SIZE * id, \
> + .mux_bit = 2, \
> + .pull_bit = 0, \
> + .drv_bit = 6, \
> + .egpio_enable = 12, \
> + .egpio_present = 11, \
> + .oe_bit = 9, \
> + .in_bit = 0, \
> + .out_bit = 1, \
> + .intr_enable_bit = 0, \
> + .intr_status_bit = 0, \
> + .intr_wakeup_present_bit = 6, \
> + .intr_wakeup_enable_bit = 7, \
> + .intr_target_bit = 8, \
> + .intr_target_kpss_val = 3, \
> + .intr_raw_status_bit = 4, \
> + .intr_polarity_bit = 1, \
> + .intr_detection_bit = 2, \
> + .intr_detection_width = 2, \
> + }
> +
> +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
> + { \
> + .grp = PINCTRL_PINGROUP(#pg_name, \
> + pg_name##_pins, \
> + ARRAY_SIZE(pg_name##_pins)), \
> + .ctl_reg = ctl, \
> + .io_reg = 0, \
> + .intr_cfg_reg = 0, \
> + .intr_status_reg = 0, \
> + .intr_target_reg = 0, \
> + .mux_bit = -1, \
> + .pull_bit = pull, \
> + .drv_bit = drv, \
> + .oe_bit = -1, \
> + .in_bit = -1, \
> + .out_bit = -1, \
> + .intr_enable_bit = -1, \
> + .intr_status_bit = -1, \
> + .intr_target_bit = -1, \
> + .intr_raw_status_bit = -1, \
> + .intr_polarity_bit = -1, \
> + .intr_detection_bit = -1, \
> + .intr_detection_width = -1, \
> + }
> +
> +#define UFS_RESET(pg_name, ctl, io) \
> + { \
> + .grp = PINCTRL_PINGROUP(#pg_name, \
> + pg_name##_pins, \
> + ARRAY_SIZE(pg_name##_pins)), \
> + .ctl_reg = ctl, \
> + .io_reg = io, \
> + .intr_cfg_reg = 0, \
> + .intr_status_reg = 0, \
> + .intr_target_reg = 0, \
> + .mux_bit = -1, \
> + .pull_bit = 3, \
> + .drv_bit = 0, \
> + .oe_bit = -1, \
> + .in_bit = -1, \
> + .out_bit = 0, \
> + .intr_enable_bit = -1, \
> + .intr_status_bit = -1, \
> + .intr_target_bit = -1, \
> + .intr_raw_status_bit = -1, \
> + .intr_polarity_bit = -1, \
> + .intr_detection_bit = -1, \
> + .intr_detection_width = -1, \
> + }
> +
> +static const struct pinctrl_pin_desc hawi_pins[] = {
> + PINCTRL_PIN(0, "GPIO_0"),
> + PINCTRL_PIN(1, "GPIO_1"),
> + PINCTRL_PIN(2, "GPIO_2"),
> + PINCTRL_PIN(3, "GPIO_3"),
> + PINCTRL_PIN(4, "GPIO_4"),
> + PINCTRL_PIN(5, "GPIO_5"),
> + PINCTRL_PIN(6, "GPIO_6"),
> + PINCTRL_PIN(7, "GPIO_7"),
> + PINCTRL_PIN(8, "GPIO_8"),
> + PINCTRL_PIN(9, "GPIO_9"),
> + PINCTRL_PIN(10, "GPIO_10"),
> + PINCTRL_PIN(11, "GPIO_11"),
> + PINCTRL_PIN(12, "GPIO_12"),
> + PINCTRL_PIN(13, "GPIO_13"),
> + PINCTRL_PIN(14, "GPIO_14"),
> + PINCTRL_PIN(15, "GPIO_15"),
> + PINCTRL_PIN(16, "GPIO_16"),
> + PINCTRL_PIN(17, "GPIO_17"),
> + PINCTRL_PIN(18, "GPIO_18"),
> + PINCTRL_PIN(19, "GPIO_19"),
> + PINCTRL_PIN(20, "GPIO_20"),
> + PINCTRL_PIN(21, "GPIO_21"),
> + PINCTRL_PIN(22, "GPIO_22"),
> + PINCTRL_PIN(23, "GPIO_23"),
> + PINCTRL_PIN(24, "GPIO_24"),
> + PINCTRL_PIN(25, "GPIO_25"),
> + PINCTRL_PIN(26, "GPIO_26"),
> + PINCTRL_PIN(27, "GPIO_27"),
> + PINCTRL_PIN(28, "GPIO_28"),
> + PINCTRL_PIN(29, "GPIO_29"),
> + PINCTRL_PIN(30, "GPIO_30"),
> + PINCTRL_PIN(31, "GPIO_31"),
> + PINCTRL_PIN(32, "GPIO_32"),
> + PINCTRL_PIN(33, "GPIO_33"),
> + PINCTRL_PIN(34, "GPIO_34"),
> + PINCTRL_PIN(35, "GPIO_35"),
> + PINCTRL_PIN(36, "GPIO_36"),
> + PINCTRL_PIN(37, "GPIO_37"),
> + PINCTRL_PIN(38, "GPIO_38"),
> + PINCTRL_PIN(39, "GPIO_39"),
> + PINCTRL_PIN(40, "GPIO_40"),
> + PINCTRL_PIN(41, "GPIO_41"),
> + PINCTRL_PIN(42, "GPIO_42"),
> + PINCTRL_PIN(43, "GPIO_43"),
> + PINCTRL_PIN(44, "GPIO_44"),
> + PINCTRL_PIN(45, "GPIO_45"),
> + PINCTRL_PIN(46, "GPIO_46"),
> + PINCTRL_PIN(47, "GPIO_47"),
> + PINCTRL_PIN(48, "GPIO_48"),
> + PINCTRL_PIN(49, "GPIO_49"),
> + PINCTRL_PIN(50, "GPIO_50"),
> + PINCTRL_PIN(51, "GPIO_51"),
> + PINCTRL_PIN(52, "GPIO_52"),
> + PINCTRL_PIN(53, "GPIO_53"),
> + PINCTRL_PIN(54, "GPIO_54"),
> + PINCTRL_PIN(55, "GPIO_55"),
> + PINCTRL_PIN(56, "GPIO_56"),
> + PINCTRL_PIN(57, "GPIO_57"),
> + PINCTRL_PIN(58, "GPIO_58"),
> + PINCTRL_PIN(59, "GPIO_59"),
> + PINCTRL_PIN(60, "GPIO_60"),
> + PINCTRL_PIN(61, "GPIO_61"),
> + PINCTRL_PIN(62, "GPIO_62"),
> + PINCTRL_PIN(63, "GPIO_63"),
> + PINCTRL_PIN(64, "GPIO_64"),
> + PINCTRL_PIN(65, "GPIO_65"),
> + PINCTRL_PIN(66, "GPIO_66"),
> + PINCTRL_PIN(67, "GPIO_67"),
> + PINCTRL_PIN(68, "GPIO_68"),
> + PINCTRL_PIN(69, "GPIO_69"),
> + PINCTRL_PIN(70, "GPIO_70"),
> + PINCTRL_PIN(71, "GPIO_71"),
> + PINCTRL_PIN(72, "GPIO_72"),
> + PINCTRL_PIN(73, "GPIO_73"),
> + PINCTRL_PIN(74, "GPIO_74"),
> + PINCTRL_PIN(75, "GPIO_75"),
> + PINCTRL_PIN(76, "GPIO_76"),
> + PINCTRL_PIN(77, "GPIO_77"),
> + PINCTRL_PIN(78, "GPIO_78"),
> + PINCTRL_PIN(79, "GPIO_79"),
> + PINCTRL_PIN(80, "GPIO_80"),
> + PINCTRL_PIN(81, "GPIO_81"),
> + PINCTRL_PIN(82, "GPIO_82"),
> + PINCTRL_PIN(83, "GPIO_83"),
> + PINCTRL_PIN(84, "GPIO_84"),
> + PINCTRL_PIN(85, "GPIO_85"),
> + PINCTRL_PIN(86, "GPIO_86"),
> + PINCTRL_PIN(87, "GPIO_87"),
> + PINCTRL_PIN(88, "GPIO_88"),
> + PINCTRL_PIN(89, "GPIO_89"),
> + PINCTRL_PIN(90, "GPIO_90"),
> + PINCTRL_PIN(91, "GPIO_91"),
> + PINCTRL_PIN(92, "GPIO_92"),
> + PINCTRL_PIN(93, "GPIO_93"),
> + PINCTRL_PIN(94, "GPIO_94"),
> + PINCTRL_PIN(95, "GPIO_95"),
> + PINCTRL_PIN(96, "GPIO_96"),
> + PINCTRL_PIN(97, "GPIO_97"),
> + PINCTRL_PIN(98, "GPIO_98"),
> + PINCTRL_PIN(99, "GPIO_99"),
> + PINCTRL_PIN(100, "GPIO_100"),
> + PINCTRL_PIN(101, "GPIO_101"),
> + PINCTRL_PIN(102, "GPIO_102"),
> + PINCTRL_PIN(103, "GPIO_103"),
> + PINCTRL_PIN(104, "GPIO_104"),
> + PINCTRL_PIN(105, "GPIO_105"),
> + PINCTRL_PIN(106, "GPIO_106"),
> + PINCTRL_PIN(107, "GPIO_107"),
> + PINCTRL_PIN(108, "GPIO_108"),
> + PINCTRL_PIN(109, "GPIO_109"),
> + PINCTRL_PIN(110, "GPIO_110"),
> + PINCTRL_PIN(111, "GPIO_111"),
> + PINCTRL_PIN(112, "GPIO_112"),
> + PINCTRL_PIN(113, "GPIO_113"),
> + PINCTRL_PIN(114, "GPIO_114"),
> + PINCTRL_PIN(115, "GPIO_115"),
> + PINCTRL_PIN(116, "GPIO_116"),
> + PINCTRL_PIN(117, "GPIO_117"),
> + PINCTRL_PIN(118, "GPIO_118"),
> + PINCTRL_PIN(119, "GPIO_119"),
> + PINCTRL_PIN(120, "GPIO_120"),
> + PINCTRL_PIN(121, "GPIO_121"),
> + PINCTRL_PIN(122, "GPIO_122"),
> + PINCTRL_PIN(123, "GPIO_123"),
> + PINCTRL_PIN(124, "GPIO_124"),
> + PINCTRL_PIN(125, "GPIO_125"),
> + PINCTRL_PIN(126, "GPIO_126"),
> + PINCTRL_PIN(127, "GPIO_127"),
> + PINCTRL_PIN(128, "GPIO_128"),
> + PINCTRL_PIN(129, "GPIO_129"),
> + PINCTRL_PIN(130, "GPIO_130"),
> + PINCTRL_PIN(131, "GPIO_131"),
> + PINCTRL_PIN(132, "GPIO_132"),
> + PINCTRL_PIN(133, "GPIO_133"),
> + PINCTRL_PIN(134, "GPIO_134"),
> + PINCTRL_PIN(135, "GPIO_135"),
> + PINCTRL_PIN(136, "GPIO_136"),
> + PINCTRL_PIN(137, "GPIO_137"),
> + PINCTRL_PIN(138, "GPIO_138"),
> + PINCTRL_PIN(139, "GPIO_139"),
> + PINCTRL_PIN(140, "GPIO_140"),
> + PINCTRL_PIN(141, "GPIO_141"),
> + PINCTRL_PIN(142, "GPIO_142"),
> + PINCTRL_PIN(143, "GPIO_143"),
> + PINCTRL_PIN(144, "GPIO_144"),
> + PINCTRL_PIN(145, "GPIO_145"),
> + PINCTRL_PIN(146, "GPIO_146"),
> + PINCTRL_PIN(147, "GPIO_147"),
> + PINCTRL_PIN(148, "GPIO_148"),
> + PINCTRL_PIN(149, "GPIO_149"),
> + PINCTRL_PIN(150, "GPIO_150"),
> + PINCTRL_PIN(151, "GPIO_151"),
> + PINCTRL_PIN(152, "GPIO_152"),
> + PINCTRL_PIN(153, "GPIO_153"),
> + PINCTRL_PIN(154, "GPIO_154"),
> + PINCTRL_PIN(155, "GPIO_155"),
> + PINCTRL_PIN(156, "GPIO_156"),
> + PINCTRL_PIN(157, "GPIO_157"),
> + PINCTRL_PIN(158, "GPIO_158"),
> + PINCTRL_PIN(159, "GPIO_159"),
> + PINCTRL_PIN(160, "GPIO_160"),
> + PINCTRL_PIN(161, "GPIO_161"),
> + PINCTRL_PIN(162, "GPIO_162"),
> + PINCTRL_PIN(163, "GPIO_163"),
> + PINCTRL_PIN(164, "GPIO_164"),
> + PINCTRL_PIN(165, "GPIO_165"),
> + PINCTRL_PIN(166, "GPIO_166"),
> + PINCTRL_PIN(167, "GPIO_167"),
> + PINCTRL_PIN(168, "GPIO_168"),
> + PINCTRL_PIN(169, "GPIO_169"),
> + PINCTRL_PIN(170, "GPIO_170"),
> + PINCTRL_PIN(171, "GPIO_171"),
> + PINCTRL_PIN(172, "GPIO_172"),
> + PINCTRL_PIN(173, "GPIO_173"),
> + PINCTRL_PIN(174, "GPIO_174"),
> + PINCTRL_PIN(175, "GPIO_175"),
> + PINCTRL_PIN(176, "GPIO_176"),
> + PINCTRL_PIN(177, "GPIO_177"),
> + PINCTRL_PIN(178, "GPIO_178"),
> + PINCTRL_PIN(179, "GPIO_179"),
> + PINCTRL_PIN(180, "GPIO_180"),
> + PINCTRL_PIN(181, "GPIO_181"),
> + PINCTRL_PIN(182, "GPIO_182"),
> + PINCTRL_PIN(183, "GPIO_183"),
> + PINCTRL_PIN(184, "GPIO_184"),
> + PINCTRL_PIN(185, "GPIO_185"),
> + PINCTRL_PIN(186, "GPIO_186"),
> + PINCTRL_PIN(187, "GPIO_187"),
> + PINCTRL_PIN(188, "GPIO_188"),
> + PINCTRL_PIN(189, "GPIO_189"),
> + PINCTRL_PIN(190, "GPIO_190"),
> + PINCTRL_PIN(191, "GPIO_191"),
> + PINCTRL_PIN(192, "GPIO_192"),
> + PINCTRL_PIN(193, "GPIO_193"),
> + PINCTRL_PIN(194, "GPIO_194"),
> + PINCTRL_PIN(195, "GPIO_195"),
> + PINCTRL_PIN(196, "GPIO_196"),
> + PINCTRL_PIN(197, "GPIO_197"),
> + PINCTRL_PIN(198, "GPIO_198"),
> + PINCTRL_PIN(199, "GPIO_199"),
> + PINCTRL_PIN(200, "GPIO_200"),
> + PINCTRL_PIN(201, "GPIO_201"),
> + PINCTRL_PIN(202, "GPIO_202"),
> + PINCTRL_PIN(203, "GPIO_203"),
> + PINCTRL_PIN(204, "GPIO_204"),
> + PINCTRL_PIN(205, "GPIO_205"),
> + PINCTRL_PIN(206, "GPIO_206"),
> + PINCTRL_PIN(207, "GPIO_207"),
> + PINCTRL_PIN(208, "GPIO_208"),
> + PINCTRL_PIN(209, "GPIO_209"),
> + PINCTRL_PIN(210, "GPIO_210"),
> + PINCTRL_PIN(211, "GPIO_211"),
> + PINCTRL_PIN(212, "GPIO_212"),
> + PINCTRL_PIN(213, "GPIO_213"),
> + PINCTRL_PIN(214, "GPIO_214"),
> + PINCTRL_PIN(215, "GPIO_215"),
> + PINCTRL_PIN(216, "GPIO_216"),
> + PINCTRL_PIN(217, "GPIO_217"),
> + PINCTRL_PIN(218, "GPIO_218"),
> + PINCTRL_PIN(219, "GPIO_219"),
> + PINCTRL_PIN(220, "GPIO_220"),
> + PINCTRL_PIN(221, "GPIO_221"),
> + PINCTRL_PIN(222, "GPIO_222"),
> + PINCTRL_PIN(223, "GPIO_223"),
> + PINCTRL_PIN(224, "GPIO_224"),
> + PINCTRL_PIN(225, "GPIO_225"),
> + PINCTRL_PIN(226, "UFS_RESET"),
> + PINCTRL_PIN(227, "SDC2_CLK"),
> + PINCTRL_PIN(228, "SDC2_CMD"),
> + PINCTRL_PIN(229, "SDC2_DATA"),
> +};
> +
> +#define DECLARE_MSM_GPIO_PINS(pin) \
> + static const unsigned int gpio##pin##_pins[] = { pin }
> +DECLARE_MSM_GPIO_PINS(0);
> +DECLARE_MSM_GPIO_PINS(1);
> +DECLARE_MSM_GPIO_PINS(2);
> +DECLARE_MSM_GPIO_PINS(3);
> +DECLARE_MSM_GPIO_PINS(4);
> +DECLARE_MSM_GPIO_PINS(5);
> +DECLARE_MSM_GPIO_PINS(6);
> +DECLARE_MSM_GPIO_PINS(7);
> +DECLARE_MSM_GPIO_PINS(8);
> +DECLARE_MSM_GPIO_PINS(9);
> +DECLARE_MSM_GPIO_PINS(10);
> +DECLARE_MSM_GPIO_PINS(11);
> +DECLARE_MSM_GPIO_PINS(12);
> +DECLARE_MSM_GPIO_PINS(13);
> +DECLARE_MSM_GPIO_PINS(14);
> +DECLARE_MSM_GPIO_PINS(15);
> +DECLARE_MSM_GPIO_PINS(16);
> +DECLARE_MSM_GPIO_PINS(17);
> +DECLARE_MSM_GPIO_PINS(18);
> +DECLARE_MSM_GPIO_PINS(19);
> +DECLARE_MSM_GPIO_PINS(20);
> +DECLARE_MSM_GPIO_PINS(21);
> +DECLARE_MSM_GPIO_PINS(22);
> +DECLARE_MSM_GPIO_PINS(23);
> +DECLARE_MSM_GPIO_PINS(24);
> +DECLARE_MSM_GPIO_PINS(25);
> +DECLARE_MSM_GPIO_PINS(26);
> +DECLARE_MSM_GPIO_PINS(27);
> +DECLARE_MSM_GPIO_PINS(28);
> +DECLARE_MSM_GPIO_PINS(29);
> +DECLARE_MSM_GPIO_PINS(30);
> +DECLARE_MSM_GPIO_PINS(31);
> +DECLARE_MSM_GPIO_PINS(32);
> +DECLARE_MSM_GPIO_PINS(33);
> +DECLARE_MSM_GPIO_PINS(34);
> +DECLARE_MSM_GPIO_PINS(35);
> +DECLARE_MSM_GPIO_PINS(36);
> +DECLARE_MSM_GPIO_PINS(37);
> +DECLARE_MSM_GPIO_PINS(38);
> +DECLARE_MSM_GPIO_PINS(39);
> +DECLARE_MSM_GPIO_PINS(40);
> +DECLARE_MSM_GPIO_PINS(41);
> +DECLARE_MSM_GPIO_PINS(42);
> +DECLARE_MSM_GPIO_PINS(43);
> +DECLARE_MSM_GPIO_PINS(44);
> +DECLARE_MSM_GPIO_PINS(45);
> +DECLARE_MSM_GPIO_PINS(46);
> +DECLARE_MSM_GPIO_PINS(47);
> +DECLARE_MSM_GPIO_PINS(48);
> +DECLARE_MSM_GPIO_PINS(49);
> +DECLARE_MSM_GPIO_PINS(50);
> +DECLARE_MSM_GPIO_PINS(51);
> +DECLARE_MSM_GPIO_PINS(52);
> +DECLARE_MSM_GPIO_PINS(53);
> +DECLARE_MSM_GPIO_PINS(54);
> +DECLARE_MSM_GPIO_PINS(55);
> +DECLARE_MSM_GPIO_PINS(56);
> +DECLARE_MSM_GPIO_PINS(57);
> +DECLARE_MSM_GPIO_PINS(58);
> +DECLARE_MSM_GPIO_PINS(59);
> +DECLARE_MSM_GPIO_PINS(60);
> +DECLARE_MSM_GPIO_PINS(61);
> +DECLARE_MSM_GPIO_PINS(62);
> +DECLARE_MSM_GPIO_PINS(63);
> +DECLARE_MSM_GPIO_PINS(64);
> +DECLARE_MSM_GPIO_PINS(65);
> +DECLARE_MSM_GPIO_PINS(66);
> +DECLARE_MSM_GPIO_PINS(67);
> +DECLARE_MSM_GPIO_PINS(68);
> +DECLARE_MSM_GPIO_PINS(69);
> +DECLARE_MSM_GPIO_PINS(70);
> +DECLARE_MSM_GPIO_PINS(71);
> +DECLARE_MSM_GPIO_PINS(72);
> +DECLARE_MSM_GPIO_PINS(73);
> +DECLARE_MSM_GPIO_PINS(74);
> +DECLARE_MSM_GPIO_PINS(75);
> +DECLARE_MSM_GPIO_PINS(76);
> +DECLARE_MSM_GPIO_PINS(77);
> +DECLARE_MSM_GPIO_PINS(78);
> +DECLARE_MSM_GPIO_PINS(79);
> +DECLARE_MSM_GPIO_PINS(80);
> +DECLARE_MSM_GPIO_PINS(81);
> +DECLARE_MSM_GPIO_PINS(82);
> +DECLARE_MSM_GPIO_PINS(83);
> +DECLARE_MSM_GPIO_PINS(84);
> +DECLARE_MSM_GPIO_PINS(85);
> +DECLARE_MSM_GPIO_PINS(86);
> +DECLARE_MSM_GPIO_PINS(87);
> +DECLARE_MSM_GPIO_PINS(88);
> +DECLARE_MSM_GPIO_PINS(89);
> +DECLARE_MSM_GPIO_PINS(90);
> +DECLARE_MSM_GPIO_PINS(91);
> +DECLARE_MSM_GPIO_PINS(92);
> +DECLARE_MSM_GPIO_PINS(93);
> +DECLARE_MSM_GPIO_PINS(94);
> +DECLARE_MSM_GPIO_PINS(95);
> +DECLARE_MSM_GPIO_PINS(96);
> +DECLARE_MSM_GPIO_PINS(97);
> +DECLARE_MSM_GPIO_PINS(98);
> +DECLARE_MSM_GPIO_PINS(99);
> +DECLARE_MSM_GPIO_PINS(100);
> +DECLARE_MSM_GPIO_PINS(101);
> +DECLARE_MSM_GPIO_PINS(102);
> +DECLARE_MSM_GPIO_PINS(103);
> +DECLARE_MSM_GPIO_PINS(104);
> +DECLARE_MSM_GPIO_PINS(105);
> +DECLARE_MSM_GPIO_PINS(106);
> +DECLARE_MSM_GPIO_PINS(107);
> +DECLARE_MSM_GPIO_PINS(108);
> +DECLARE_MSM_GPIO_PINS(109);
> +DECLARE_MSM_GPIO_PINS(110);
> +DECLARE_MSM_GPIO_PINS(111);
> +DECLARE_MSM_GPIO_PINS(112);
> +DECLARE_MSM_GPIO_PINS(113);
> +DECLARE_MSM_GPIO_PINS(114);
> +DECLARE_MSM_GPIO_PINS(115);
> +DECLARE_MSM_GPIO_PINS(116);
> +DECLARE_MSM_GPIO_PINS(117);
> +DECLARE_MSM_GPIO_PINS(118);
> +DECLARE_MSM_GPIO_PINS(119);
> +DECLARE_MSM_GPIO_PINS(120);
> +DECLARE_MSM_GPIO_PINS(121);
> +DECLARE_MSM_GPIO_PINS(122);
> +DECLARE_MSM_GPIO_PINS(123);
> +DECLARE_MSM_GPIO_PINS(124);
> +DECLARE_MSM_GPIO_PINS(125);
> +DECLARE_MSM_GPIO_PINS(126);
> +DECLARE_MSM_GPIO_PINS(127);
> +DECLARE_MSM_GPIO_PINS(128);
> +DECLARE_MSM_GPIO_PINS(129);
> +DECLARE_MSM_GPIO_PINS(130);
> +DECLARE_MSM_GPIO_PINS(131);
> +DECLARE_MSM_GPIO_PINS(132);
> +DECLARE_MSM_GPIO_PINS(133);
> +DECLARE_MSM_GPIO_PINS(134);
> +DECLARE_MSM_GPIO_PINS(135);
> +DECLARE_MSM_GPIO_PINS(136);
> +DECLARE_MSM_GPIO_PINS(137);
> +DECLARE_MSM_GPIO_PINS(138);
> +DECLARE_MSM_GPIO_PINS(139);
> +DECLARE_MSM_GPIO_PINS(140);
> +DECLARE_MSM_GPIO_PINS(141);
> +DECLARE_MSM_GPIO_PINS(142);
> +DECLARE_MSM_GPIO_PINS(143);
> +DECLARE_MSM_GPIO_PINS(144);
> +DECLARE_MSM_GPIO_PINS(145);
> +DECLARE_MSM_GPIO_PINS(146);
> +DECLARE_MSM_GPIO_PINS(147);
> +DECLARE_MSM_GPIO_PINS(148);
> +DECLARE_MSM_GPIO_PINS(149);
> +DECLARE_MSM_GPIO_PINS(150);
> +DECLARE_MSM_GPIO_PINS(151);
> +DECLARE_MSM_GPIO_PINS(152);
> +DECLARE_MSM_GPIO_PINS(153);
> +DECLARE_MSM_GPIO_PINS(154);
> +DECLARE_MSM_GPIO_PINS(155);
> +DECLARE_MSM_GPIO_PINS(156);
> +DECLARE_MSM_GPIO_PINS(157);
> +DECLARE_MSM_GPIO_PINS(158);
> +DECLARE_MSM_GPIO_PINS(159);
> +DECLARE_MSM_GPIO_PINS(160);
> +DECLARE_MSM_GPIO_PINS(161);
> +DECLARE_MSM_GPIO_PINS(162);
> +DECLARE_MSM_GPIO_PINS(163);
> +DECLARE_MSM_GPIO_PINS(164);
> +DECLARE_MSM_GPIO_PINS(165);
> +DECLARE_MSM_GPIO_PINS(166);
> +DECLARE_MSM_GPIO_PINS(167);
> +DECLARE_MSM_GPIO_PINS(168);
> +DECLARE_MSM_GPIO_PINS(169);
> +DECLARE_MSM_GPIO_PINS(170);
> +DECLARE_MSM_GPIO_PINS(171);
> +DECLARE_MSM_GPIO_PINS(172);
> +DECLARE_MSM_GPIO_PINS(173);
> +DECLARE_MSM_GPIO_PINS(174);
> +DECLARE_MSM_GPIO_PINS(175);
> +DECLARE_MSM_GPIO_PINS(176);
> +DECLARE_MSM_GPIO_PINS(177);
> +DECLARE_MSM_GPIO_PINS(178);
> +DECLARE_MSM_GPIO_PINS(179);
> +DECLARE_MSM_GPIO_PINS(180);
> +DECLARE_MSM_GPIO_PINS(181);
> +DECLARE_MSM_GPIO_PINS(182);
> +DECLARE_MSM_GPIO_PINS(183);
> +DECLARE_MSM_GPIO_PINS(184);
> +DECLARE_MSM_GPIO_PINS(185);
> +DECLARE_MSM_GPIO_PINS(186);
> +DECLARE_MSM_GPIO_PINS(187);
> +DECLARE_MSM_GPIO_PINS(188);
> +DECLARE_MSM_GPIO_PINS(189);
> +DECLARE_MSM_GPIO_PINS(190);
> +DECLARE_MSM_GPIO_PINS(191);
> +DECLARE_MSM_GPIO_PINS(192);
> +DECLARE_MSM_GPIO_PINS(193);
> +DECLARE_MSM_GPIO_PINS(194);
> +DECLARE_MSM_GPIO_PINS(195);
> +DECLARE_MSM_GPIO_PINS(196);
> +DECLARE_MSM_GPIO_PINS(197);
> +DECLARE_MSM_GPIO_PINS(198);
> +DECLARE_MSM_GPIO_PINS(199);
> +DECLARE_MSM_GPIO_PINS(200);
> +DECLARE_MSM_GPIO_PINS(201);
> +DECLARE_MSM_GPIO_PINS(202);
> +DECLARE_MSM_GPIO_PINS(203);
> +DECLARE_MSM_GPIO_PINS(204);
> +DECLARE_MSM_GPIO_PINS(205);
> +DECLARE_MSM_GPIO_PINS(206);
> +DECLARE_MSM_GPIO_PINS(207);
> +DECLARE_MSM_GPIO_PINS(208);
> +DECLARE_MSM_GPIO_PINS(209);
> +DECLARE_MSM_GPIO_PINS(210);
> +DECLARE_MSM_GPIO_PINS(211);
> +DECLARE_MSM_GPIO_PINS(212);
> +DECLARE_MSM_GPIO_PINS(213);
> +DECLARE_MSM_GPIO_PINS(214);
> +DECLARE_MSM_GPIO_PINS(215);
> +DECLARE_MSM_GPIO_PINS(216);
> +DECLARE_MSM_GPIO_PINS(217);
> +DECLARE_MSM_GPIO_PINS(218);
> +DECLARE_MSM_GPIO_PINS(219);
> +DECLARE_MSM_GPIO_PINS(220);
> +DECLARE_MSM_GPIO_PINS(221);
> +DECLARE_MSM_GPIO_PINS(222);
> +DECLARE_MSM_GPIO_PINS(223);
> +DECLARE_MSM_GPIO_PINS(224);
> +DECLARE_MSM_GPIO_PINS(225);
> +
> +static const unsigned int ufs_reset_pins[] = { 226 };
> +static const unsigned int sdc2_clk_pins[] = { 227 };
> +static const unsigned int sdc2_cmd_pins[] = { 228 };
> +static const unsigned int sdc2_data_pins[] = { 229 };
> +
> +enum hawi_functions {
> + msm_mux_gpio,
> + msm_mux_aoss_cti,
> + msm_mux_atest_char,
> + msm_mux_atest_usb,
> + msm_mux_audio_ext_mclk,
> + msm_mux_audio_ref_clk,
> + msm_mux_cam_mclk,
> + msm_mux_cci_async_in,
> + msm_mux_cci_i2c_scl,
> + msm_mux_cci_i2c_sda,
> + msm_mux_cci_timer,
> + msm_mux_coex_espmi_sclk,
> + msm_mux_coex_espmi_sdata,
> + msm_mux_coex_uart1_rx,
> + msm_mux_coex_uart1_tx,
> + msm_mux_dbg_out_clk,
> + msm_mux_ddr_bist,
> + msm_mux_ddr_pxi,
> + msm_mux_dp_hot,
> + msm_mux_egpio,
> + msm_mux_gcc_gp,
> + msm_mux_gnss_adc,
> + msm_mux_host_rst,
> + msm_mux_i2chub0_se0,
> + msm_mux_i2chub0_se1,
> + msm_mux_i2chub0_se2,
> + msm_mux_i2chub0_se3,
> + msm_mux_i2chub0_se4,
> + msm_mux_i2s0_data,
> + msm_mux_i2s0_sck,
> + msm_mux_i2s0_ws,
> + msm_mux_i2s1_data,
> + msm_mux_i2s1_sck,
> + msm_mux_i2s1_ws,
> + msm_mux_ibi_i3c,
> + msm_mux_jitter_bist,
> + msm_mux_mdp_esync0,
> + msm_mux_mdp_esync1,
> + msm_mux_mdp_esync2,
> + msm_mux_mdp_vsync,
> + msm_mux_mdp_vsync_e,
> + msm_mux_mdp_vsync_p,
> + msm_mux_mdp_vsync0_out,
> + msm_mux_mdp_vsync1_out,
> + msm_mux_mdp_vsync2_out,
> + msm_mux_mdp_vsync3_out,
> + msm_mux_mdp_vsync5_out,
> + msm_mux_modem_pps_in,
> + msm_mux_modem_pps_out,
> + msm_mux_nav_gpio0,
> + msm_mux_nav_gpio1,
> + msm_mux_nav_gpio2,
> + msm_mux_nav_gpio3,
> + msm_mux_nav_gpio4,
> + msm_mux_nav_gpio5,
> + msm_mux_nav_rffe,
> + msm_mux_pcie0_clk_req_n,
> + msm_mux_pcie0_rst_n,
> + msm_mux_pcie1_clk_req_n,
> + msm_mux_phase_flag,
> + msm_mux_pll_bist_sync,
> + msm_mux_pll_clk_aux,
> + msm_mux_qdss_cti,
> + msm_mux_qlink_enable,
> + msm_mux_qlink_request,
> + msm_mux_qlink_wmss,
> + msm_mux_qspi,
> + msm_mux_qspi_clk,
> + msm_mux_qspi_cs,
> + msm_mux_qup1_se0,
> + msm_mux_qup1_se1,
> + msm_mux_qup1_se2,
> + msm_mux_qup1_se3,
> + msm_mux_qup1_se4,
> + msm_mux_qup1_se5,
> + msm_mux_qup1_se6,
> + msm_mux_qup1_se7,
> + msm_mux_qup2_se0,
> + msm_mux_qup2_se1,
> + msm_mux_qup2_se2,
> + msm_mux_qup2_se3,
> + msm_mux_qup2_se4_l0,
> + msm_mux_qup2_se4_l1,
> + msm_mux_qup2_se4_l2,
> + msm_mux_qup2_se4_l3,
> + msm_mux_qup3_se0_l0,
> + msm_mux_qup3_se0_l1,
> + msm_mux_qup3_se0_l2,
> + msm_mux_qup3_se0_l3,
> + msm_mux_qup3_se1,
> + msm_mux_qup3_se2,
> + msm_mux_qup3_se3,
> + msm_mux_qup3_se4,
> + msm_mux_qup3_se5,
> + msm_mux_qup4_se0,
> + msm_mux_qup4_se1,
> + msm_mux_qup4_se2,
> + msm_mux_qup4_se3_l0,
> + msm_mux_qup4_se3_l1,
> + msm_mux_qup4_se3_l2,
> + msm_mux_qup4_se3_l3,
> + msm_mux_qup4_se4_l0,
> + msm_mux_qup4_se4_l1,
> + msm_mux_qup4_se4_l2,
> + msm_mux_qup4_se4_l3,
> + msm_mux_rng_rosc,
> + msm_mux_sd_write_protect,
> + msm_mux_sdc4_clk,
> + msm_mux_sdc4_cmd,
> + msm_mux_sdc4_data,
> + msm_mux_sys_throttle,
> + msm_mux_tb_trig_sdc,
> + msm_mux_tmess_rng,
> + msm_mux_tsense_clm,
> + msm_mux_tsense_pwm,
> + msm_mux_uim0_clk,
> + msm_mux_uim0_data,
> + msm_mux_uim0_present,
> + msm_mux_uim0_reset,
> + msm_mux_uim1_clk,
> + msm_mux_uim1_data,
> + msm_mux_uim1_present,
> + msm_mux_uim1_reset,
> + msm_mux_usb0_hs,
> + msm_mux_usb_phy,
> + msm_mux_vfr,
> + msm_mux_vsense_trigger_mirnat,
> + msm_mux_wcn_sw_ctrl,
> + msm_mux__,
> +};
> +
> +static const char *const gpio_groups[] = {
> + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
> + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
> + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
> + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
> + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
> + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
> + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
> + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
> + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
> + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59",
> + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
> + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71",
> + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
> + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
> + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89",
> + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
> + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101",
> + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
> + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113",
> + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119",
> + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
> + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131",
> + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137",
> + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
> + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149",
> + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155",
> + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161",
> + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167",
> + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173",
> + "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179",
> + "gpio180", "gpio181", "gpio182", "gpio183", "gpio184", "gpio185",
> + "gpio186", "gpio187", "gpio188", "gpio189", "gpio190", "gpio191",
> + "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197",
> + "gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203",
> + "gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209",
> + "gpio210", "gpio211", "gpio212", "gpio213", "gpio214", "gpio215",
> + "gpio216", "gpio217", "gpio218", "gpio219", "gpio220", "gpio221",
> + "gpio222", "gpio223", "gpio224", "gpio225",
> +};
> +
> +static const char *const aoss_cti_groups[] = {
> + "gpio74", "gpio75", "gpio76", "gpio77",
> +};
> +
> +static const char *const atest_char_groups[] = {
> + "gpio126", "gpio127", "gpio128", "gpio129", "gpio133",
> +};
> +
> +static const char *const atest_usb_groups[] = {
> + "gpio70", "gpio71", "gpio72", "gpio73", "gpio129",
> +};
> +
> +static const char *const audio_ext_mclk_groups[] = {
> + "gpio120", "gpio121",
> +};
> +
> +static const char *const audio_ref_clk_groups[] = {
> + "gpio120",
> +};
> +
> +static const char *const cam_mclk_groups[] = {
> + "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94",
> + "gpio95", "gpio96",
> +};
> +
> +static const char *const cci_async_in_groups[] = {
> + "gpio15", "gpio109", "gpio110",
> +};
> +
> +static const char *const cci_i2c_scl_groups[] = {
> + "gpio110", "gpio112", "gpio114", "gpio116", "gpio149", "gpio160",
> +};
> +
> +static const char *const cci_i2c_sda_groups[] = {
> + "gpio107", "gpio108", "gpio109", "gpio111", "gpio113", "gpio115",
> +};
> +
> +static const char *const cci_timer_groups[] = {
> + "gpio105", "gpio106", "gpio107", "gpio159", "gpio160",
> +};
> +
> +static const char *const coex_espmi_sclk_groups[] = {
> + "gpio144",
> +};
> +
> +static const char *const coex_espmi_sdata_groups[] = {
> + "gpio145",
> +};
> +
> +static const char *const coex_uart1_rx_groups[] = {
> + "gpio144",
> +};
> +
> +static const char *const coex_uart1_tx_groups[] = {
> + "gpio145",
> +};
> +
> +static const char *const dbg_out_clk_groups[] = {
> + "gpio82",
> +};
> +
> +static const char *const ddr_bist_groups[] = {
> + "gpio40", "gpio41", "gpio44", "gpio45",
> +};
> +
> +static const char *const ddr_pxi_groups[] = {
> + "gpio43", "gpio44", "gpio45", "gpio46",
> + "gpio52", "gpio53", "gpio54", "gpio55",
> +};
> +
> +static const char *const dp_hot_groups[] = {
> + "gpio47",
> +};
> +
> +static const char *const egpio_groups[] = {
> + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
> + "gpio6", "gpio7", "gpio28", "gpio29", "gpio30", "gpio31",
> + "gpio48", "gpio49", "gpio50", "gpio51", "gpio163", "gpio164",
> + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
> + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
> + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182",
> + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188",
> + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194",
> + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200",
> + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206",
> + "gpio207", "gpio208", "gpio209", "gpio212", "gpio213", "gpio214",
> + "gpio215", "gpio216", "gpio217", "gpio218",
> +};
> +
> +static const char *const gcc_gp_groups[] = {
> + "gpio86", "gpio87", "gpio130", "gpio131", "gpio132", "gpio158",
> +};
> +
> +static const char *const gnss_adc_groups[] = {
> + "gpio40", "gpio41", "gpio42", "gpio77",
> +};
> +
> +static const char *const host_rst_groups[] = {
> + "gpio106",
> +};
> +
> +static const char *const i2chub0_se0_groups[] = {
> + "gpio66", "gpio67",
> +};
> +
> +static const char *const i2chub0_se1_groups[] = {
> + "gpio78", "gpio79",
> +};
> +
> +static const char *const i2chub0_se2_groups[] = {
> + "gpio68", "gpio69",
> +};
> +
> +static const char *const i2chub0_se3_groups[] = {
> + "gpio70", "gpio71",
> +};
> +
> +static const char *const i2chub0_se4_groups[] = {
> + "gpio72", "gpio73",
> +};
> +
> +static const char *const i2s0_data_groups[] = {
> + "gpio123", "gpio124",
> +};
> +
> +static const char *const i2s0_sck_groups[] = {
> + "gpio122",
> +};
> +
> +static const char *const i2s0_ws_groups[] = {
> + "gpio125",
> +};
> +
> +static const char *const i2s1_data_groups[] = {
> + "gpio118", "gpio120",
> +};
> +
> +static const char *const i2s1_sck_groups[] = {
> + "gpio117",
> +};
> +
> +static const char *const i2s1_ws_groups[] = {
> + "gpio119",
> +};
> +
> +static const char *const ibi_i3c_groups[] = {
> + "gpio0", "gpio1", "gpio4", "gpio5", "gpio8", "gpio9",
> + "gpio12", "gpio13", "gpio28", "gpio29", "gpio32", "gpio33",
> + "gpio36", "gpio37", "gpio48", "gpio49", "gpio60", "gpio61",
> +};
> +
> +static const char *const jitter_bist_groups[] = {
> + "gpio73",
> +};
> +
> +static const char *const mdp_esync0_groups[] = {
> + "gpio88", "gpio100",
> +};
> +
> +static const char *const mdp_esync1_groups[] = {
> + "gpio86", "gpio100",
> +};
> +
> +static const char *const mdp_esync2_groups[] = {
> + "gpio87", "gpio97",
> +};
> +
> +static const char *const mdp_vsync_groups[] = {
> + "gpio86", "gpio87", "gpio88", "gpio97",
> +};
> +
> +static const char *const mdp_vsync_e_groups[] = {
> + "gpio98",
> +};
> +
> +static const char *const mdp_vsync_p_groups[] = {
> + "gpio98",
> +};
> +
> +static const char *const mdp_vsync0_out_groups[] = {
> + "gpio86",
> +};
> +
> +static const char *const mdp_vsync1_out_groups[] = {
> + "gpio86",
> +};
> +
> +static const char *const mdp_vsync2_out_groups[] = {
> + "gpio87",
> +};
> +
> +static const char *const mdp_vsync3_out_groups[] = {
> + "gpio87",
> +};
> +
> +static const char *const mdp_vsync5_out_groups[] = {
> + "gpio87",
> +};
> +
> +static const char *const modem_pps_in_groups[] = {
> + "gpio151",
> +};
> +
> +static const char *const modem_pps_out_groups[] = {
> + "gpio151",
> +};
> +
> +static const char *const nav_gpio0_groups[] = {
> + "gpio150",
> +};
> +
> +static const char *const nav_gpio1_groups[] = {
> + "gpio151",
> +};
> +
> +static const char *const nav_gpio2_groups[] = {
> + "gpio148",
> +};
> +
> +static const char *const nav_gpio3_groups[] = {
> + "gpio150",
> +};
> +
> +static const char *const nav_gpio4_groups[] = {
> + "gpio146",
> +};
> +
> +static const char *const nav_gpio5_groups[] = {
> + "gpio147",
> +};
> +
> +static const char *const nav_rffe_groups[] = {
> + "gpio134", "gpio135", "gpio138", "gpio139",
> +};
> +
> +static const char *const pcie0_clk_req_n_groups[] = {
> + "gpio103",
> +};
> +
> +static const char *const pcie0_rst_n_groups[] = {
> + "gpio102",
> +};
> +
> +static const char *const pcie1_clk_req_n_groups[] = {
> + "gpio221",
> +};
> +
> +static const char *const phase_flag_groups[] = {
> + "gpio117", "gpio118", "gpio119", "gpio123", "gpio124", "gpio125",
> + "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", "gpio175",
> + "gpio176", "gpio179", "gpio180", "gpio181", "gpio184", "gpio185",
> + "gpio192", "gpio196", "gpio197", "gpio198", "gpio199", "gpio204",
> + "gpio206", "gpio207", "gpio208", "gpio210", "gpio211", "gpio214",
> + "gpio215", "gpio216",
> +};
> +
> +static const char *const pll_bist_sync_groups[] = {
> + "gpio104",
> +};
> +
> +static const char *const pll_clk_aux_groups[] = {
> + "gpio94",
> +};
> +
> +static const char *const qdss_cti_groups[] = {
> + "gpio27", "gpio31", "gpio72", "gpio73", "gpio82", "gpio83",
> + "gpio152", "gpio158",
> +};
> +
> +static const char *const qlink_enable_groups[] = {
> + "gpio153",
> +};
> +
> +static const char *const qlink_request_groups[] = {
> + "gpio152",
> +};
> +
> +static const char *const qlink_wmss_groups[] = {
> + "gpio154",
> +};
> +
> +static const char *const qspi_groups[] = {
> + "gpio80", "gpio81", "gpio82", "gpio147",
> +};
> +
> +static const char *const qspi_clk_groups[] = {
> + "gpio83",
> +};
> +
> +static const char *const qspi_cs_groups[] = {
> + "gpio146", "gpio148",
> +};
> +
> +static const char *const qup1_se0_groups[] = {
> + "gpio80", "gpio81", "gpio82", "gpio83",
> +};
> +
> +static const char *const qup1_se1_groups[] = {
> + "gpio74", "gpio75", "gpio76", "gpio77",
> +};
> +
> +static const char *const qup1_se2_groups[] = {
> + "gpio40", "gpio41", "gpio42", "gpio43", "gpio130", "gpio131", "gpio132",
> +};
> +
> +static const char *const qup1_se3_groups[] = {
> + "gpio44", "gpio45", "gpio46", "gpio47",
> +};
> +
> +static const char *const qup1_se4_groups[] = {
> + "gpio36", "gpio37", "gpio38", "gpio39",
> +};
> +
> +static const char *const qup1_se5_groups[] = {
> + "gpio52", "gpio53", "gpio54", "gpio55",
> +};
> +
> +static const char *const qup1_se6_groups[] = {
> + "gpio56", "gpio57", "gpio58", "gpio59",
> +};
> +
> +static const char *const qup1_se7_groups[] = {
> + "gpio60", "gpio61", "gpio62", "gpio63",
> +};
> +
> +static const char *const qup2_se0_groups[] = {
> + "gpio0", "gpio1", "gpio2", "gpio3",
> +};
> +
> +static const char *const qup2_se1_groups[] = {
> + "gpio4", "gpio5", "gpio6", "gpio7",
> +};
> +
> +static const char *const qup2_se2_groups[] = {
> + "gpio117", "gpio118", "gpio119", "gpio120",
> +};
> +
> +static const char *const qup2_se3_groups[] = {
> + "gpio97", "gpio122", "gpio123", "gpio124", "gpio125",
> +};
> +
> +static const char *const qup2_se4_l0_groups[] = {
> + "gpio208",
> +};
> +
> +static const char *const qup2_se4_l1_groups[] = {
> + "gpio209",
> +};
> +
> +static const char *const qup2_se4_l2_groups[] = {
> + "gpio208",
> +};
> +
> +static const char *const qup2_se4_l3_groups[] = {
> + "gpio209",
> +};
> +
> +static const char *const qup3_se0_l0_groups[] = {
> + "gpio64",
> +};
> +
> +static const char *const qup3_se0_l1_groups[] = {
> + "gpio65",
> +};
> +
> +static const char *const qup3_se0_l2_groups[] = {
> + "gpio64",
> +};
> +
> +static const char *const qup3_se0_l3_groups[] = {
> + "gpio65",
> +};
> +
> +static const char *const qup3_se1_groups[] = {
> + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio15",
> +};
> +
> +static const char *const qup3_se2_groups[] = {
> + "gpio12", "gpio13", "gpio14", "gpio15",
> +};
> +
> +static const char *const qup3_se3_groups[] = {
> + "gpio16", "gpio17", "gpio18", "gpio19",
> +};
> +
> +static const char *const qup3_se4_groups[] = {
> + "gpio20", "gpio21", "gpio22", "gpio23",
> +};
> +
> +static const char *const qup3_se5_groups[] = {
> + "gpio24", "gpio25", "gpio26", "gpio27",
> +};
> +
> +static const char *const qup4_se0_groups[] = {
> + "gpio48", "gpio49", "gpio50", "gpio51",
> +};
> +
> +static const char *const qup4_se1_groups[] = {
> + "gpio28", "gpio29", "gpio30", "gpio31",
> +};
> +
> +static const char *const qup4_se2_groups[] = {
> + "gpio32", "gpio33", "gpio34", "gpio35",
> +};
> +
> +static const char *const qup4_se3_l0_groups[] = {
> + "gpio121",
> +};
> +
> +static const char *const qup4_se3_l1_groups[] = {
> + "gpio84",
> +};
> +
> +static const char *const qup4_se3_l2_groups[] = {
> + "gpio121",
> +};
> +
> +static const char *const qup4_se3_l3_groups[] = {
> + "gpio84", "gpio98",
> +};
> +
> +static const char *const qup4_se4_l0_groups[] = {
> + "gpio161",
> +};
> +
> +static const char *const qup4_se4_l1_groups[] = {
> + "gpio162",
> +};
> +
> +static const char *const qup4_se4_l2_groups[] = {
> + "gpio161",
> +};
> +
> +static const char *const qup4_se4_l3_groups[] = {
> + "gpio88", "gpio162",
> +};
> +
> +static const char *const rng_rosc_groups[] = {
> + "gpio64", "gpio65", "gpio66", "gpio84",
> +};
> +
> +static const char *const sd_write_protect_groups[] = {
> + "gpio85",
> +};
> +
> +static const char *const sdc4_clk_groups[] = {
> + "gpio83",
> +};
> +
> +static const char *const sdc4_cmd_groups[] = {
> + "gpio148",
> +};
> +
> +static const char *const sdc4_data_groups[] = {
> + "gpio80", "gpio81", "gpio82", "gpio147",
> +};
> +
> +static const char *const sys_throttle_groups[] = {
> + "gpio99",
> +};
> +
> +static const char *const tb_trig_sdc_groups[] = {
> + "gpio88", "gpio146",
> +};
> +
> +static const char *const tmess_rng_groups[] = {
> + "gpio64", "gpio65", "gpio66", "gpio84",
> +};
> +
> +static const char *const tsense_clm_groups[] = {
> + "gpio10", "gpio87", "gpio97", "gpio99", "gpio105", "gpio106",
> + "gpio159",
> +};
> +
> +static const char *const tsense_pwm_groups[] = {
> + "gpio10", "gpio87", "gpio97", "gpio99", "gpio223", "gpio224",
> + "gpio225",
> +};
> +
> +static const char *const uim0_clk_groups[] = {
> + "gpio127",
> +};
> +
> +static const char *const uim0_data_groups[] = {
> + "gpio126",
> +};
> +
> +static const char *const uim0_present_groups[] = {
> + "gpio129",
> +};
> +
> +static const char *const uim0_reset_groups[] = {
> + "gpio128",
> +};
> +
> +static const char *const uim1_clk_groups[] = {
> + "gpio37", "gpio55", "gpio71", "gpio131",
> +};
> +
> +static const char *const uim1_data_groups[] = {
> + "gpio36", "gpio54", "gpio70", "gpio130",
> +};
> +
> +static const char *const uim1_present_groups[] = {
> + "gpio133",
> +};
> +
> +static const char *const uim1_reset_groups[] = {
> + "gpio39", "gpio56", "gpio72", "gpio132",
> +};
> +
> +static const char *const usb0_hs_groups[] = {
> + "gpio79",
> +};
> +
> +static const char *const usb_phy_groups[] = {
> + "gpio59", "gpio60",
> +};
> +
> +static const char *const vfr_groups[] = {
> + "gpio146", "gpio151",
> +};
> +
> +static const char *const vsense_trigger_mirnat_groups[] = {
> + "gpio59",
> +};
> +
> +static const char *const wcn_sw_ctrl_groups[] = {
> + "gpio18", "gpio19", "gpio155", "gpio156",
> +};
> +
> +static const struct pinfunction hawi_functions[] = {
> + MSM_GPIO_PIN_FUNCTION(gpio),
> + MSM_PIN_FUNCTION(aoss_cti),
> + MSM_PIN_FUNCTION(atest_char),
> + MSM_PIN_FUNCTION(atest_usb),
> + MSM_PIN_FUNCTION(audio_ext_mclk),
> + MSM_PIN_FUNCTION(audio_ref_clk),
> + MSM_PIN_FUNCTION(cam_mclk),
> + MSM_PIN_FUNCTION(cci_async_in),
> + MSM_PIN_FUNCTION(cci_i2c_scl),
> + MSM_PIN_FUNCTION(cci_i2c_sda),
> + MSM_PIN_FUNCTION(cci_timer),
> + MSM_PIN_FUNCTION(coex_espmi_sclk),
> + MSM_PIN_FUNCTION(coex_espmi_sdata),
> + MSM_PIN_FUNCTION(coex_uart1_rx),
> + MSM_PIN_FUNCTION(coex_uart1_tx),
> + MSM_PIN_FUNCTION(dbg_out_clk),
> + MSM_PIN_FUNCTION(ddr_bist),
> + MSM_PIN_FUNCTION(ddr_pxi),
> + MSM_PIN_FUNCTION(dp_hot),
> + MSM_PIN_FUNCTION(egpio),
> + MSM_PIN_FUNCTION(gcc_gp),
> + MSM_PIN_FUNCTION(gnss_adc),
> + MSM_PIN_FUNCTION(host_rst),
> + MSM_PIN_FUNCTION(i2chub0_se0),
> + MSM_PIN_FUNCTION(i2chub0_se1),
> + MSM_PIN_FUNCTION(i2chub0_se2),
> + MSM_PIN_FUNCTION(i2chub0_se3),
> + MSM_PIN_FUNCTION(i2chub0_se4),
> + MSM_PIN_FUNCTION(i2s0_data),
> + MSM_PIN_FUNCTION(i2s0_sck),
> + MSM_PIN_FUNCTION(i2s0_ws),
> + MSM_PIN_FUNCTION(i2s1_data),
> + MSM_PIN_FUNCTION(i2s1_sck),
> + MSM_PIN_FUNCTION(i2s1_ws),
> + MSM_PIN_FUNCTION(ibi_i3c),
> + MSM_PIN_FUNCTION(jitter_bist),
> + MSM_PIN_FUNCTION(mdp_esync0),
> + MSM_PIN_FUNCTION(mdp_esync1),
> + MSM_PIN_FUNCTION(mdp_esync2),
> + MSM_PIN_FUNCTION(mdp_vsync),
> + MSM_PIN_FUNCTION(mdp_vsync_e),
> + MSM_PIN_FUNCTION(mdp_vsync_p),
> + MSM_PIN_FUNCTION(mdp_vsync0_out),
> + MSM_PIN_FUNCTION(mdp_vsync1_out),
> + MSM_PIN_FUNCTION(mdp_vsync2_out),
> + MSM_PIN_FUNCTION(mdp_vsync3_out),
> + MSM_PIN_FUNCTION(mdp_vsync5_out),
> + MSM_PIN_FUNCTION(modem_pps_in),
> + MSM_PIN_FUNCTION(modem_pps_out),
> + MSM_PIN_FUNCTION(nav_gpio0),
> + MSM_PIN_FUNCTION(nav_gpio1),
> + MSM_PIN_FUNCTION(nav_gpio2),
> + MSM_PIN_FUNCTION(nav_gpio3),
> + MSM_PIN_FUNCTION(nav_gpio4),
> + MSM_PIN_FUNCTION(nav_gpio5),
> + MSM_PIN_FUNCTION(nav_rffe),
> + MSM_PIN_FUNCTION(pcie0_clk_req_n),
> + MSM_PIN_FUNCTION(pcie0_rst_n),
> + MSM_PIN_FUNCTION(pcie1_clk_req_n),
> + MSM_PIN_FUNCTION(phase_flag),
> + MSM_PIN_FUNCTION(pll_bist_sync),
> + MSM_PIN_FUNCTION(pll_clk_aux),
> + MSM_PIN_FUNCTION(qdss_cti),
> + MSM_PIN_FUNCTION(qlink_enable),
> + MSM_PIN_FUNCTION(qlink_request),
> + MSM_PIN_FUNCTION(qlink_wmss),
> + MSM_PIN_FUNCTION(qspi),
> + MSM_PIN_FUNCTION(qspi_clk),
> + MSM_PIN_FUNCTION(qspi_cs),
> + MSM_PIN_FUNCTION(qup1_se0),
> + MSM_PIN_FUNCTION(qup1_se1),
> + MSM_PIN_FUNCTION(qup1_se2),
> + MSM_PIN_FUNCTION(qup1_se3),
> + MSM_PIN_FUNCTION(qup1_se4),
> + MSM_PIN_FUNCTION(qup1_se5),
> + MSM_PIN_FUNCTION(qup1_se6),
> + MSM_PIN_FUNCTION(qup1_se7),
> + MSM_PIN_FUNCTION(qup2_se0),
> + MSM_PIN_FUNCTION(qup2_se1),
> + MSM_PIN_FUNCTION(qup2_se2),
> + MSM_PIN_FUNCTION(qup2_se3),
> + MSM_PIN_FUNCTION(qup2_se4_l0),
> + MSM_PIN_FUNCTION(qup2_se4_l1),
> + MSM_PIN_FUNCTION(qup2_se4_l2),
> + MSM_PIN_FUNCTION(qup2_se4_l3),
> + MSM_PIN_FUNCTION(qup3_se0_l0),
> + MSM_PIN_FUNCTION(qup3_se0_l1),
> + MSM_PIN_FUNCTION(qup3_se0_l2),
> + MSM_PIN_FUNCTION(qup3_se0_l3),
> + MSM_PIN_FUNCTION(qup3_se1),
> + MSM_PIN_FUNCTION(qup3_se2),
> + MSM_PIN_FUNCTION(qup3_se3),
> + MSM_PIN_FUNCTION(qup3_se4),
> + MSM_PIN_FUNCTION(qup3_se5),
> + MSM_PIN_FUNCTION(qup4_se0),
> + MSM_PIN_FUNCTION(qup4_se1),
> + MSM_PIN_FUNCTION(qup4_se2),
> + MSM_PIN_FUNCTION(qup4_se3_l0),
> + MSM_PIN_FUNCTION(qup4_se3_l1),
> + MSM_PIN_FUNCTION(qup4_se3_l2),
> + MSM_PIN_FUNCTION(qup4_se3_l3),
> + MSM_PIN_FUNCTION(qup4_se4_l0),
> + MSM_PIN_FUNCTION(qup4_se4_l1),
> + MSM_PIN_FUNCTION(qup4_se4_l2),
> + MSM_PIN_FUNCTION(qup4_se4_l3),
> + MSM_PIN_FUNCTION(rng_rosc),
> + MSM_PIN_FUNCTION(sd_write_protect),
> + MSM_PIN_FUNCTION(sdc4_clk),
> + MSM_PIN_FUNCTION(sdc4_cmd),
> + MSM_PIN_FUNCTION(sdc4_data),
> + MSM_PIN_FUNCTION(sys_throttle),
> + MSM_PIN_FUNCTION(tb_trig_sdc),
> + MSM_PIN_FUNCTION(tmess_rng),
> + MSM_PIN_FUNCTION(tsense_clm),
> + MSM_PIN_FUNCTION(tsense_pwm),
> + MSM_PIN_FUNCTION(uim0_clk),
> + MSM_PIN_FUNCTION(uim0_data),
> + MSM_PIN_FUNCTION(uim0_present),
> + MSM_PIN_FUNCTION(uim0_reset),
> + MSM_PIN_FUNCTION(uim1_clk),
> + MSM_PIN_FUNCTION(uim1_data),
> + MSM_PIN_FUNCTION(uim1_present),
> + MSM_PIN_FUNCTION(uim1_reset),
> + MSM_PIN_FUNCTION(usb0_hs),
> + MSM_PIN_FUNCTION(usb_phy),
> + MSM_PIN_FUNCTION(vfr),
> + MSM_PIN_FUNCTION(vsense_trigger_mirnat),
> + MSM_PIN_FUNCTION(wcn_sw_ctrl),
> +};
> +
> +/*
> + * Every pin is maintained as a single group, and missing or non-existing pin
> + * would be maintained as dummy group to synchronize pin group index with
> + * pin descriptor registered with pinctrl core.
> + * Clients would not be able to request these dummy pin groups.
> + */
> +static const struct msm_pingroup hawi_groups[] = {
> + [0] = PINGROUP(0, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [1] = PINGROUP(1, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, egpio),
> + [3] = PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, egpio),
> + [4] = PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [5] = PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [6] = PINGROUP(6, qup2_se1, _, _, _, _, _, _, _, _, _, egpio),
> + [7] = PINGROUP(7, qup2_se1, _, _, _, _, _, _, _, _, _, egpio),
> + [8] = PINGROUP(8, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),
> + [9] = PINGROUP(9, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),
> + [10] = PINGROUP(10, qup3_se1, _, tsense_clm, tsense_pwm, _, _, _, _, _, _, _),
> + [11] = PINGROUP(11, qup3_se1, _, _, _, _, _, _, _, _, _, _),
> + [12] = PINGROUP(12, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _),
> + [13] = PINGROUP(13, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _),
> + [14] = PINGROUP(14, qup3_se2, _, _, _, _, _, _, _, _, _, _),
> + [15] = PINGROUP(15, qup3_se2, cci_async_in, qup3_se1, _, _, _, _, _, _, _, _),
> + [16] = PINGROUP(16, qup3_se3, _, _, _, _, _, _, _, _, _, _),
> + [17] = PINGROUP(17, qup3_se3, _, _, _, _, _, _, _, _, _, _),
> + [18] = PINGROUP(18, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _),
> + [19] = PINGROUP(19, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _),
> + [20] = PINGROUP(20, qup3_se4, _, _, _, _, _, _, _, _, _, _),
> + [21] = PINGROUP(21, qup3_se4, _, _, _, _, _, _, _, _, _, _),
> + [22] = PINGROUP(22, qup3_se4, _, _, _, _, _, _, _, _, _, _),
> + [23] = PINGROUP(23, qup3_se4, _, _, _, _, _, _, _, _, _, _),
> + [24] = PINGROUP(24, qup3_se5, _, _, _, _, _, _, _, _, _, _),
> + [25] = PINGROUP(25, qup3_se5, _, _, _, _, _, _, _, _, _, _),
> + [26] = PINGROUP(26, qup3_se5, _, _, _, _, _, _, _, _, _, _),
> + [27] = PINGROUP(27, qup3_se5, qdss_cti, _, _, _, _, _, _, _, _, _),
> + [28] = PINGROUP(28, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [29] = PINGROUP(29, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [30] = PINGROUP(30, qup4_se1, _, _, _, _, _, _, _, _, _, egpio),
> + [31] = PINGROUP(31, qup4_se1, qdss_cti, _, _, _, _, _, _, _, _, egpio),
> + [32] = PINGROUP(32, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _),
> + [33] = PINGROUP(33, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _),
> + [34] = PINGROUP(34, qup4_se2, _, _, _, _, _, _, _, _, _, _),
> + [35] = PINGROUP(35, qup4_se2, _, _, _, _, _, _, _, _, _, _),
> + [36] = PINGROUP(36, qup1_se4, uim1_data, ibi_i3c, _, _, _, _, _, _, _, _),
> + [37] = PINGROUP(37, qup1_se4, uim1_clk, ibi_i3c, _, _, _, _, _, _, _, _),
> + [38] = PINGROUP(38, qup1_se4, _, _, _, _, _, _, _, _, _, _),
> + [39] = PINGROUP(39, qup1_se4, uim1_reset, _, _, _, _, _, _, _, _, _),
> + [40] = PINGROUP(40, qup1_se2, ddr_bist, _, gnss_adc, _, _, _, _, _, _, _),
> + [41] = PINGROUP(41, qup1_se2, ddr_bist, _, gnss_adc, _, _, _, _, _, _, _),
> + [42] = PINGROUP(42, qup1_se2, gnss_adc, _, _, _, _, _, _, _, _, _),
> + [43] = PINGROUP(43, qup1_se2, _, ddr_pxi, _, _, _, _, _, _, _, _),
> + [44] = PINGROUP(44, qup1_se3, ddr_bist, ddr_pxi, _, _, _, _, _, _, _, _),
> + [45] = PINGROUP(45, qup1_se3, ddr_bist, ddr_pxi, _, _, _, _, _, _, _, _),
> + [46] = PINGROUP(46, qup1_se3, ddr_pxi, _, _, _, _, _, _, _, _, _),
> + [47] = PINGROUP(47, qup1_se3, dp_hot, _, _, _, _, _, _, _, _, _),
> + [48] = PINGROUP(48, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [49] = PINGROUP(49, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [50] = PINGROUP(50, qup4_se0, _, _, _, _, _, _, _, _, _, egpio),
> + [51] = PINGROUP(51, qup4_se0, _, _, _, _, _, _, _, _, _, egpio),
> + [52] = PINGROUP(52, qup1_se5, ddr_pxi, _, _, _, _, _, _, _, _, _),
> + [53] = PINGROUP(53, qup1_se5, _, ddr_pxi, _, _, _, _, _, _, _, _),
> + [54] = PINGROUP(54, qup1_se5, uim1_data, ddr_pxi, _, _, _, _, _, _, _, _),
> + [55] = PINGROUP(55, qup1_se5, uim1_clk, ddr_pxi, _, _, _, _, _, _, _, _),
> + [56] = PINGROUP(56, qup1_se6, uim1_reset, _, _, _, _, _, _, _, _, _),
> + [57] = PINGROUP(57, qup1_se6, _, _, _, _, _, _, _, _, _, _),
> + [58] = PINGROUP(58, qup1_se6, _, _, _, _, _, _, _, _, _, _),
> + [59] = PINGROUP(59, qup1_se6, usb_phy, vsense_trigger_mirnat, _, _, _, _, _, _, _, _),
> + [60] = PINGROUP(60, qup1_se7, usb_phy, ibi_i3c, _, _, _, _, _, _, _, _),
> + [61] = PINGROUP(61, qup1_se7, ibi_i3c, _, _, _, _, _, _, _, _, _),
> + [62] = PINGROUP(62, qup1_se7, _, _, _, _, _, _, _, _, _, _),
> + [63] = PINGROUP(63, qup1_se7, _, _, _, _, _, _, _, _, _, _),
> + [64] = PINGROUP(64, qup3_se0_l0, qup3_se0_l2, rng_rosc, tmess_rng, _, _, _, _, _, _, _),
> + [65] = PINGROUP(65, qup3_se0_l1, qup3_se0_l3, rng_rosc, tmess_rng, _, _, _, _, _, _, _),
> + [66] = PINGROUP(66, i2chub0_se0, rng_rosc, tmess_rng, _, _, _, _, _, _, _, _),
> + [67] = PINGROUP(67, i2chub0_se0, _, _, _, _, _, _, _, _, _, _),
> + [68] = PINGROUP(68, i2chub0_se2, _, _, _, _, _, _, _, _, _, _),
> + [69] = PINGROUP(69, i2chub0_se2, _, _, _, _, _, _, _, _, _, _),
> + [70] = PINGROUP(70, i2chub0_se3, uim1_data, _, atest_usb, _, _, _, _, _, _, _),
> + [71] = PINGROUP(71, i2chub0_se3, uim1_clk, _, atest_usb, _, _, _, _, _, _, _),
> + [72] = PINGROUP(72, i2chub0_se4, uim1_reset, qdss_cti, _, atest_usb, _, _, _, _, _, _),
> + [73] = PINGROUP(73, i2chub0_se4, qdss_cti, jitter_bist, atest_usb, _, _, _, _, _, _, _),
> + [74] = PINGROUP(74, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),
> + [75] = PINGROUP(75, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),
> + [76] = PINGROUP(76, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),
> + [77] = PINGROUP(77, qup1_se1, aoss_cti, gnss_adc, _, _, _, _, _, _, _, _),
> + [78] = PINGROUP(78, i2chub0_se1, _, _, _, _, _, _, _, _, _, _),
> + [79] = PINGROUP(79, i2chub0_se1, usb0_hs, _, _, _, _, _, _, _, _, _),
> + [80] = PINGROUP(80, qup1_se0, sdc4_data, qspi, _, _, _, _, _, _, _, _),
> + [81] = PINGROUP(81, qup1_se0, sdc4_data, qspi, _, _, _, _, _, _, _, _),
> + [82] = PINGROUP(82, qup1_se0, sdc4_data, qdss_cti, qspi, dbg_out_clk, _, _, _, _, _, _),
> + [83] = PINGROUP(83, qup1_se0, sdc4_clk, qdss_cti, qspi_clk, _, _, _, _, _, _, _),
> + [84] = PINGROUP(84, qup4_se3_l1, qup4_se3_l3, rng_rosc, tmess_rng, _, _, _, _, _, _, _),
> + [85] = PINGROUP(85, sd_write_protect, _, _, _, _, _, _, _, _, _, _),
> + [86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_esync1, gcc_gp,
> + _, _, _, _, _, _),
> + [87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,
> + mdp_esync2, gcc_gp, _, tsense_clm, tsense_pwm, _, _),
> + [88] = PINGROUP(88, mdp_esync0, mdp_vsync, qup4_se4_l3, tb_trig_sdc, _, _, _, _, _, _, _),
> + [89] = PINGROUP(89, cam_mclk, _, _, _, _, _, _, _, _, _, _),
> + [90] = PINGROUP(90, cam_mclk, _, _, _, _, _, _, _, _, _, _),
> + [91] = PINGROUP(91, cam_mclk, _, _, _, _, _, _, _, _, _, _),
> + [92] = PINGROUP(92, cam_mclk, _, _, _, _, _, _, _, _, _, _),
> + [93] = PINGROUP(93, cam_mclk, _, _, _, _, _, _, _, _, _, _),
> + [94] = PINGROUP(94, cam_mclk, pll_clk_aux, _, _, _, _, _, _, _, _, _),
> + [95] = PINGROUP(95, cam_mclk, _, _, _, _, _, _, _, _, _, _),
> + [96] = PINGROUP(96, cam_mclk, _, _, _, _, _, _, _, _, _, _),
> + [97] = PINGROUP(97, mdp_esync2, qup2_se3, mdp_vsync, tsense_clm, tsense_pwm, _, _,
> + _, _, _, _),
> + [98] = PINGROUP(98, mdp_vsync_e, qup4_se3_l3, mdp_vsync_p, _, _, _, _, _, _, _, _),
> + [99] = PINGROUP(99, sys_throttle, tsense_clm, tsense_pwm, _, _, _, _, _, _, _, _),
> + [100] = PINGROUP(100, mdp_esync1, mdp_esync0, _, _, _, _, _, _, _, _, _),
> + [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _),
> + [102] = PINGROUP(102, pcie0_rst_n, _, _, _, _, _, _, _, _, _, _),
> + [103] = PINGROUP(103, pcie0_clk_req_n, _, _, _, _, _, _, _, _, _, _),
> + [104] = PINGROUP(104, pll_bist_sync, _, _, _, _, _, _, _, _, _, _),
> + [105] = PINGROUP(105, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _),
> + [106] = PINGROUP(106, host_rst, cci_timer, tsense_clm, _, _, _, _, _, _, _, _),
> + [107] = PINGROUP(107, cci_i2c_sda, cci_timer, _, _, _, _, _, _, _, _, _),
> + [108] = PINGROUP(108, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _),
> + [109] = PINGROUP(109, cci_i2c_sda, cci_async_in, _, _, _, _, _, _, _, _, _),
> + [110] = PINGROUP(110, cci_i2c_scl, cci_async_in, _, _, _, _, _, _, _, _, _),
> + [111] = PINGROUP(111, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _),
> + [112] = PINGROUP(112, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _),
> + [113] = PINGROUP(113, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _),
> + [114] = PINGROUP(114, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _),
> + [115] = PINGROUP(115, cci_i2c_sda, _, _, _, _, _, _, _, _, _, _),
> + [116] = PINGROUP(116, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _),
> + [117] = PINGROUP(117, i2s1_sck, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),
> + [118] = PINGROUP(118, i2s1_data, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),
> + [119] = PINGROUP(119, i2s1_ws, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),
> + [120] = PINGROUP(120, i2s1_data, qup2_se2, audio_ext_mclk, audio_ref_clk, _, _,
> + _, _, _, _, _),
> + [121] = PINGROUP(121, audio_ext_mclk, qup4_se3_l0, qup4_se3_l2, _, _, _, _, _, _, _, _),
> + [122] = PINGROUP(122, i2s0_sck, qup2_se3, _, _, _, _, _, _, _, _, _),
> + [123] = PINGROUP(123, i2s0_data, qup2_se3, _, phase_flag, _, _, _, _, _, _, _),
> + [124] = PINGROUP(124, i2s0_data, qup2_se3, _, phase_flag, _, _, _, _, _, _, _),
> + [125] = PINGROUP(125, i2s0_ws, qup2_se3, phase_flag, _, _, _, _, _, _, _, _),
> + [126] = PINGROUP(126, uim0_data, atest_char, _, _, _, _, _, _, _, _, _),
> + [127] = PINGROUP(127, uim0_clk, atest_char, _, _, _, _, _, _, _, _, _),
> + [128] = PINGROUP(128, uim0_reset, atest_char, _, _, _, _, _, _, _, _, _),
> + [129] = PINGROUP(129, uim0_present, atest_usb, atest_char, _, _, _, _, _, _, _, _),
> + [130] = PINGROUP(130, uim1_data, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),
> + [131] = PINGROUP(131, uim1_clk, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),
> + [132] = PINGROUP(132, uim1_reset, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),
> + [133] = PINGROUP(133, uim1_present, atest_char, _, _, _, _, _, _, _, _, _),
> + [134] = PINGROUP(134, _, _, nav_rffe, _, _, _, _, _, _, _, _),
> + [135] = PINGROUP(135, _, _, nav_rffe, _, _, _, _, _, _, _, _),
> + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _),
> + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _),
> + [138] = PINGROUP(138, _, _, nav_rffe, _, _, _, _, _, _, _, _),
> + [139] = PINGROUP(139, _, _, nav_rffe, _, _, _, _, _, _, _, _),
> + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _, _, _),
> + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, _),
> + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, _),
> + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, _),
> + [144] = PINGROUP(144, coex_uart1_rx, coex_espmi_sclk, _, _, _, _, _, _, _, _, _),
> + [145] = PINGROUP(145, coex_uart1_tx, coex_espmi_sdata, _, _, _, _, _, _, _, _, _),
> + [146] = PINGROUP(146, _, vfr, nav_gpio4, tb_trig_sdc, qspi_cs, _, _, _, _, _, _),
> + [147] = PINGROUP(147, _, nav_gpio5, sdc4_data, qspi, _, _, _, _, _, _, _),
> + [148] = PINGROUP(148, nav_gpio2, _, sdc4_cmd, qspi_cs, _, _, _, _, _, _, _),
> + [149] = PINGROUP(149, cci_i2c_scl, _, _, _, _, _, _, _, _, _, _),
> + [150] = PINGROUP(150, nav_gpio0, nav_gpio3, _, _, _, _, _, _, _, _, _),
> + [151] = PINGROUP(151, nav_gpio1, vfr, modem_pps_in, modem_pps_out, _, _, _, _, _, _, _),
> + [152] = PINGROUP(152, qlink_request, qdss_cti, _, _, _, _, _, _, _, _, _),
> + [153] = PINGROUP(153, qlink_enable, _, _, _, _, _, _, _, _, _, _),
> + [154] = PINGROUP(154, qlink_wmss, _, _, _, _, _, _, _, _, _, _),
> + [155] = PINGROUP(155, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _),
> + [156] = PINGROUP(156, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _),
> + [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _),
> + [158] = PINGROUP(158, qdss_cti, gcc_gp, _, _, _, _, _, _, _, _, _),
> + [159] = PINGROUP(159, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _),
> + [160] = PINGROUP(160, cci_timer, cci_i2c_scl, _, _, _, _, _, _, _, _, _),
> + [161] = PINGROUP(161, qup4_se4_l0, qup4_se4_l2, _, _, _, _, _, _, _, _, _),
> + [162] = PINGROUP(162, qup4_se4_l1, qup4_se4_l3, _, _, _, _, _, _, _, _, _),
> + [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, egpio),
> + [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, egpio),
> + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, egpio),
> + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, egpio),
> + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _, _, egpio),
> + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _, _, egpio),
> + [169] = PINGROUP(169, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [170] = PINGROUP(170, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [171] = PINGROUP(171, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [172] = PINGROUP(172, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [173] = PINGROUP(173, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _, _, egpio),
> + [175] = PINGROUP(175, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [176] = PINGROUP(176, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _, _, egpio),
> + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _, _, egpio),
> + [179] = PINGROUP(179, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [180] = PINGROUP(180, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [181] = PINGROUP(181, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _, _, egpio),
> + [183] = PINGROUP(183, _, _, _, _, _, _, _, _, _, _, egpio),
> + [184] = PINGROUP(184, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [185] = PINGROUP(185, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _, _, egpio),
> + [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _, _, egpio),
> + [188] = PINGROUP(188, _, _, _, _, _, _, _, _, _, _, egpio),
> + [189] = PINGROUP(189, _, _, _, _, _, _, _, _, _, _, egpio),
> + [190] = PINGROUP(190, _, _, _, _, _, _, _, _, _, _, egpio),
> + [191] = PINGROUP(191, _, _, _, _, _, _, _, _, _, _, egpio),
> + [192] = PINGROUP(192, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [193] = PINGROUP(193, _, _, _, _, _, _, _, _, _, _, egpio),
> + [194] = PINGROUP(194, _, _, _, _, _, _, _, _, _, _, egpio),
> + [195] = PINGROUP(195, _, _, _, _, _, _, _, _, _, _, egpio),
> + [196] = PINGROUP(196, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [197] = PINGROUP(197, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [198] = PINGROUP(198, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [199] = PINGROUP(199, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [200] = PINGROUP(200, _, _, _, _, _, _, _, _, _, _, egpio),
> + [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _, _, egpio),
> + [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _, _, egpio),
> + [203] = PINGROUP(203, _, _, _, _, _, _, _, _, _, _, egpio),
> + [204] = PINGROUP(204, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [205] = PINGROUP(205, _, _, _, _, _, _, _, _, _, _, egpio),
> + [206] = PINGROUP(206, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [207] = PINGROUP(207, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [208] = PINGROUP(208, qup2_se4_l0, qup2_se4_l2, phase_flag, _, _, _, _, _, _, _, egpio),
> + [209] = PINGROUP(209, qup2_se4_l1, qup2_se4_l3, _, _, _, _, _, _, _, _, egpio),
> + [210] = PINGROUP(210, phase_flag, _, _, _, _, _, _, _, _, _, _),
> + [211] = PINGROUP(211, phase_flag, _, _, _, _, _, _, _, _, _, _),
> + [212] = PINGROUP(212, _, _, _, _, _, _, _, _, _, _, egpio),
> + [213] = PINGROUP(213, _, _, _, _, _, _, _, _, _, _, egpio),
> + [214] = PINGROUP(214, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [215] = PINGROUP(215, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [216] = PINGROUP(216, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [217] = PINGROUP(217, _, _, _, _, _, _, _, _, _, _, egpio),
> + [218] = PINGROUP(218, _, _, _, _, _, _, _, _, _, _, egpio),
> + [219] = PINGROUP(219, _, _, _, _, _, _, _, _, _, _, _),
> + [220] = PINGROUP(220, _, _, _, _, _, _, _, _, _, _, _),
> + [221] = PINGROUP(221, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _),
> + [222] = PINGROUP(222, _, _, _, _, _, _, _, _, _, _, _),
> + [223] = PINGROUP(223, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
> + [224] = PINGROUP(224, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
> + [225] = PINGROUP(225, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
> + [226] = UFS_RESET(ufs_reset, 0xf1004, 0xf2000),
> + [227] = SDC_QDSD_PINGROUP(sdc2_clk, 0xe6000, 14, 6),
> + [228] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xe6000, 11, 3),
> + [229] = SDC_QDSD_PINGROUP(sdc2_data, 0xe6000, 9, 0),
> +};
> +
> +static const struct msm_gpio_wakeirq_map hawi_pdc_map[] = {
> + { 0, 105 }, { 3, 113 }, { 4, 106 }, { 7, 107 }, { 8, 108 }, { 11, 109 },
> + { 12, 115 }, { 15, 131 }, { 16, 116 }, { 17, 141 }, { 18, 143 }, { 19, 112 },
> + { 23, 117 }, { 24, 118 }, { 27, 119 }, { 28, 125 }, { 31, 126 }, { 32, 127 },
> + { 35, 101 }, { 36, 128 }, { 39, 129 }, { 43, 130 }, { 47, 154 }, { 48, 135 },
> + { 51, 114 }, { 55, 104 }, { 57, 136 }, { 58, 137 }, { 59, 138 }, { 60, 139 },
> + { 61, 145 }, { 63, 124 }, { 64, 110 }, { 65, 123 }, { 67, 132 }, { 68, 146 },
> + { 69, 147 }, { 75, 151 }, { 77, 148 }, { 78, 149 }, { 79, 155 }, { 80, 156 },
> + { 81, 157 }, { 82, 158 }, { 84, 134 }, { 85, 159 }, { 86, 160 }, { 87, 161 },
> + { 88, 162 }, { 95, 163 }, { 96, 164 }, { 97, 133 }, { 98, 150 }, { 99, 111 },
> + { 101, 165 }, { 102, 166 }, { 103, 167 }, { 104, 168 }, { 120, 169 }, { 123, 170 },
> + { 125, 171 }, { 129, 153 }, { 133, 100 }, { 144, 172 }, { 146, 173 }, { 151, 174 },
> + { 152, 175 }, { 155, 122 }, { 158, 120 }, { 162, 142 }, { 164, 176 }, { 165, 177 },
> + { 167, 178 }, { 168, 179 }, { 174, 180 }, { 177, 181 }, { 179, 182 }, { 183, 183 },
> + { 184, 184 }, { 185, 185 }, { 186, 152 }, { 188, 144 }, { 202, 102 }, { 203, 103 },
> + { 205, 140 }, { 209, 186 }, { 213, 121 }, { 216, 187 }, { 221, 188 }, { 222, 189 },
> + { 223, 190 }, { 224, 191 }, { 225, 192 },
> +};
> +
> +static const struct msm_pinctrl_soc_data hawi_tlmm = {
> + .pins = hawi_pins,
> + .npins = ARRAY_SIZE(hawi_pins),
> + .functions = hawi_functions,
> + .nfunctions = ARRAY_SIZE(hawi_functions),
> + .groups = hawi_groups,
> + .ngroups = ARRAY_SIZE(hawi_groups),
> + .ngpios = 227,
> + .wakeirq_map = hawi_pdc_map,
> + .nwakeirq_map = ARRAY_SIZE(hawi_pdc_map),
> + .egpio_func = 11,
> +};
> +
> +static int hawi_tlmm_probe(struct platform_device *pdev)
> +{
> + return msm_pinctrl_probe(pdev, &hawi_tlmm);
> +}
> +
> +static const struct of_device_id hawi_tlmm_of_match[] = {
> + { .compatible = "qcom,hawi-tlmm", },
> + {},
> +};
> +
> +static struct platform_driver hawi_tlmm_driver = {
> + .driver = {
> + .name = "hawi-tlmm",
> + .of_match_table = hawi_tlmm_of_match,
> + },
> + .probe = hawi_tlmm_probe,
> +};
> +
> +static int __init hawi_tlmm_init(void)
> +{
> + return platform_driver_register(&hawi_tlmm_driver);
> +}
> +arch_initcall(hawi_tlmm_init);
> +
> +static void __exit hawi_tlmm_exit(void)
> +{
> + platform_driver_unregister(&hawi_tlmm_driver);
> +}
> +module_exit(hawi_tlmm_exit);
> +
> +MODULE_DESCRIPTION("QTI Hawi TLMM driver");
> +MODULE_LICENSE("GPL");
> +MODULE_DEVICE_TABLE(of, hawi_tlmm_of_match);
>
> --
> 2.53.0
>
^ permalink raw reply
* Re: [PATCH v4 3/6] arm64: dts: qcom: Add AYN QCS8550 Common
From: Aaron Kling @ 2026-04-02 22:04 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel, Teguh Sobirin
In-Reply-To: <fbpk7dm72aiy673r2776pudw2ydpdirr6bu2rwvceour6lgwdx@melipr4mhv5i>
On Mon, Mar 30, 2026 at 6:32 AM Dmitry Baryshkov
<dmitry.baryshkov@oss.qualcomm.com> wrote:
>
> On Mon, Mar 30, 2026 at 01:00:55PM +0200, Konrad Dybcio wrote:
> > On 3/27/26 10:26 PM, Aaron Kling wrote:
> > > On Tue, Mar 24, 2026 at 7:36 AM Konrad Dybcio
> > > <konrad.dybcio@oss.qualcomm.com> wrote:
> > >>
> > >> On 3/23/26 5:27 PM, Aaron Kling via B4 Relay wrote:
> > >>> From: Teguh Sobirin <teguh@sobir.in>
> > >>>
> > >>> This contains everything common between the AYN QCS8550 devices. It will
> > >>> be included by device specific dts'.
> > >>>
> > >>> Signed-off-by: Teguh Sobirin <teguh@sobir.in>
> > >>> Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
> > >>> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> > >>> ---
> > >>
> > >> [...]
> > >>
> > >>> + sound {
> > >>> + compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
> > >>> + pinctrl-0 = <&lpi_i2s3_active>;
> > >>> + pinctrl-names = "default";
> > >>> +
> > >>> + model = "AYN-Odin2";
> > >>
> > >> Is this enough of a distinction? Do you need to make any changes to the
> > >> one with a HDMI bridge to get HDMI audio?
> > >
> > > After this quesstion, I tried to verify hdmi and am unable to even get
> > > the connector to come up. The lt8912b driver complains that the
> > > connector doesn't support edid read.
>
> Looking at the driver, please drop lt8912_bridge_edid_read(),
> lt8912_bridge_detect() and lt->bridge.ops assignment. Those bits are
> lame and useless.
>
> > Which per the current connector
> > > node is correct, none of the devices list a ddc node. I am trying to
> > > investigate this further, but vendor source release unfortunately
> > > appears to be missing pieces related to this. And no other current
> > > qcom device uses this bridge to take a guess at which controller the
> > > ddc is on.
> >
> > Go through the I2C buses that are enabled on the vendor kernel and try
> > inspecting them with toos like i2cdetect
>
> I'd second this suggestion. The chip doesn't support EDID reading, so it
> is (hopefully) handled via some existing bus. Does downstream handle
> EDID / HDMI at all?
I have been unable to get the stock OS to display anything on hdmi at
all. The downstream kernel reports the head as DSI, and is hardcoded
to a 1920x1080 mode in the kernel dt. We have been unable to find any
kernel handling of this bridge at all for downstream, in the source
release or the prebuilt kernel shipped with the stock OS. Best I can
tell, they just hardcode the one mode and nothing else will work.
There are reports of hdmi audio working, though; which I'm not sure
how if the bridge has no kernel driver at all.
All i2c nodes used by downstream are already enabled. And when an hdmi
cable is plugged in, I never see the ddc address, 0x50 if I understand
correctly, show up on any of them. I tried enabling other i2c nodes to
check if anything shows up on them, but that causes kernel panics
during boot and without uart, I can't see why.
This all seems rather broken, perhaps by odm design. Given this state,
should I just drop all references to hdmi and leave a comment in the
dts where the bridge should be to explain why?
> >
> > >
> > > On a related note, I'm not sure hdmi is covered in the audio topology.
> >
> > Since this is a DSI bridge, I'd imagine it needs a separate connection
> > to the SoC's sound hardware. We've had similar occurences in the past,
> > e.g. this on the SM8250 RB5 board (qrb5165-rb5.dts):
>
> Yes. Unfortunately, the driver doesn't seem to implement audio support.
> I'd suggest pinging Lontium for the information regarding InfoFrame and
> audio bits programming.
>
> >
> > https://github.com/alsa-project/alsa-ucm-conf/blob/master/ucm2/Qualcomm/sm8250/HDMI.conf
> >
> > Maybe +Dmitry could help you out
> >
> > Konrad
> >
> > > What I'm using is here [0]. This is in a fork of the topology repo
> > > with aosp build rules added. Speakers work, headphones out and in
> > > work. DP works only with the pending q6dsp fixups series, which I
> > > should probably narrow down and ask for a 6.18 backport for. The ucm
> > > config [1] I'm basing tests on doesn't handle the built-in mic and I
> > > haven't been able to figure that out yet, so that's also unknown.
> > >
> > > Aaron
> > >
> > > [0] https://github.com/LineageOS/android_hardware_qcom_audioreach-topology/blob/ad67f3777b1d4dec5289bc7117f2ec34521be7e6/AYN-Odin2.m4
> > > [1] https://github.com/AYNTechnologies/alsa-ucm-conf/commit/d33738b93e9560e8d9e08a024cc84c8055bb7eb9
>
> --
> With best wishes
> Dmitry
Aaron
^ permalink raw reply
* Re: [PATCH 5/6] drm/msm/adreno: add Adreno 810 GPU support
From: Alexander Koskovich @ 2026-04-02 22:14 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Akhil P Oommen,
Bjorn Andersson, Luca Weiss, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel
In-Reply-To: <6da36e75-effb-4e3e-a2f9-c0f3ebdbcc21@oss.qualcomm.com>
On Wednesday, April 1st, 2026 at 6:15 AM, Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote:
>
> I may be on an older tag or something, but:
>
> $ diff /tmp/downstream.txt /tmp/upstream.txt
> 24a25
> > { GEN7_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
> 27,28c28,29
> < { GEN8_TPL1_DBG_ECO_CNTL1, 0x04000724, BIT(PIPE_NONE) },
> < { GEN8_UCHE_MODE_CNTL, 0x00020000, BIT(PIPE_NONE) },
> ---
> > { GEN8_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) },
> > { GEN8_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
> 31,32c32
> < /* Disable write slow pointer in data phase queue */
> < { GEN8_UCHE_HW_DBG_CNTL, BIT(8), BIT(PIPE_NONE) },
> ---
> > { GEN8_UCHE_CACHE_WAYS, 0x00080000, BIT(PIPE_NONE) },
>
>
> > +};
> > +
> > +static const u32 a810_protect_regs[] = {
>
> $ diff /tmp/downstream.txt /tmp/upstream.txt
>
> < A6XX_PROTECT_NORDWR(0x0ae00, 0x0),
> < A6XX_PROTECT_NORDWR(0x0ae02, 0x4),
> ---
> > A6XX_PROTECT_NORDWR(0x0ae00, 0x6),
>
> -> the difference is that
>
> SP_DBG_ECO_CNTL and SP_ADDR_MODE_CNTL are not protected
>
> that might have been a part of the ^ difference
Going back for v2 and making sure this is 1:1 to GRAPHICS.LA.14.0.r5-03100-lanai.0, I
think I was going back and forth between my own downstream from the OEM,
GRAPHICS.LA.14.0.r5 and GRAPHICS.LA.15.0.r1.
GRAPHICS.LA.15.0.r1 has gen8_3_0 support, but I'm not sure if there are any
devices that actually ship with it on that branch. Seemed to be fairly out
of sync from LA.14.
>
> Also it may be that the better name for this table is a830_protect_regs[]
Can you elaborate on this? The only names I know this GPU by are "a810" and
"gen8_3_0".
>
>
> The other tables, I'm lost. Akhil, please take a look.
>
>
> Konrad
Thanks,
Alex
>
>
^ permalink raw reply
* Re: [PATCH v2 2/3] power: supply: Add PD SPR AVS support to USB type enum
From: Sebastian Reichel @ 2026-04-02 22:39 UTC (permalink / raw)
To: Badhri Jagan Sridharan
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heikki Krogerus,
Greg Kroah-Hartman, Amit Sunil Dhamne, devicetree, linux-kernel,
linux-pm, linux-usb
In-Reply-To: <20260316150301.3892223-3-badhri@google.com>
[-- Attachment #1: Type: text/plain, Size: 2989 bytes --]
Hi,
On Mon, Mar 16, 2026 at 03:03:00PM +0000, Badhri Jagan Sridharan wrote:
> Add two new members to the power_supply_usb_type to represent the
> USB Power Delivery (PD) Standard Power Range (SPR) Adjustable Voltage
> Supply (AVS) charging types:
>
> POWER_SUPPLY_USB_TYPE_PD_SPR_AVS: For devices supporting only the
> PD SPR AVS type.
>
> POWER_SUPPLY_USB_TYPE_PD_PPS_SPR_AVS: For devices that support both
> PD Programmable Power Supply (PPS) and PD SPR AVS.
>
> Signed-off-by: Badhri Jagan Sridharan <badhri@google.com>
> ---
I'm not too fond of these types, but I guess we already fell into
the rabbit hole when PD_PPS was added. So:
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
I guess the patches will be handled via the USB tree.
Greetings,
-- Sebastian
> Documentation/ABI/testing/sysfs-class-power | 3 ++-
> drivers/power/supply/power_supply_sysfs.c | 2 ++
> include/linux/power_supply.h | 3 +++
> 3 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-class-power b/Documentation/ABI/testing/sysfs-class-power
> index 4b21d5d23251..32697b926cc8 100644
> --- a/Documentation/ABI/testing/sysfs-class-power
> +++ b/Documentation/ABI/testing/sysfs-class-power
> @@ -675,7 +675,8 @@ Description:
>
> Valid values:
> "Unknown", "SDP", "DCP", "CDP", "ACA", "C", "PD",
> - "PD_DRP", "PD_PPS", "BrickID"
> + "PD_DRP", "PD_PPS", "BrickID", "PD_SPR_AVS",
> + "PD_PPS_SPR_AVS"
>
> **Device Specific Properties**
>
> diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supply/power_supply_sysfs.c
> index dd3a48d72d2b..f30a7b9ccd5e 100644
> --- a/drivers/power/supply/power_supply_sysfs.c
> +++ b/drivers/power/supply/power_supply_sysfs.c
> @@ -70,6 +70,8 @@ static const char * const POWER_SUPPLY_USB_TYPE_TEXT[] = {
> [POWER_SUPPLY_USB_TYPE_PD] = "PD",
> [POWER_SUPPLY_USB_TYPE_PD_DRP] = "PD_DRP",
> [POWER_SUPPLY_USB_TYPE_PD_PPS] = "PD_PPS",
> + [POWER_SUPPLY_USB_TYPE_PD_SPR_AVS] = "PD_SPR_AVS",
> + [POWER_SUPPLY_USB_TYPE_PD_PPS_SPR_AVS] = "PD_PPS_SPR_AVS",
> [POWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID] = "BrickID",
> };
>
> diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
> index 360ffdf272da..7a5e4c3242a0 100644
> --- a/include/linux/power_supply.h
> +++ b/include/linux/power_supply.h
> @@ -210,6 +210,9 @@ enum power_supply_usb_type {
> POWER_SUPPLY_USB_TYPE_PD, /* Power Delivery Port */
> POWER_SUPPLY_USB_TYPE_PD_DRP, /* PD Dual Role Port */
> POWER_SUPPLY_USB_TYPE_PD_PPS, /* PD Programmable Power Supply */
> + /* PD Standard Power Range Adjustable Voltage Supply */
> + POWER_SUPPLY_USB_TYPE_PD_SPR_AVS,
> + POWER_SUPPLY_USB_TYPE_PD_PPS_SPR_AVS, /* Supports both PD PPS + SPR AVS */
> POWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID, /* Apple Charging Method */
> };
>
> --
> 2.53.0.851.ga537e3e6e9-goog
>
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^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: cache: qcom,llcc: Document Hawi and future SoCs
From: Francisco Munoz Ruiz @ 2026-04-02 22:44 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Konrad Dybcio, Krzysztof Kozlowski, Conor Dooley,
Jonathan Cameron, Rob Herring, Kees Cook, Gustavo A. R. Silva,
linux-arm-msm, devicetree, linux-kernel, linux-hardening,
Konrad Dybcio
In-Reply-To: <20260402-dynamic-axolotl-of-tempest-eeeb7c@quoll>
On Thu, Apr 02, 2026 at 11:19:42AM +0200, Krzysztof Kozlowski wrote:
> On Wed, Apr 01, 2026 at 08:01:34PM -0700, Francisco Munoz Ruiz wrote:
> > Add documentation for the Last Level Cache Controller (LLCC) bindings to
> > support Hawi and upcoming Qualcomm SoCs where the System Cache Table (SCT)
> > is programmed by firmware outside of Linux.
> >
> > Introduce a property that specifies the base address of the shared memory
> > region from which the driver should read SCT descriptors provided by
> > firmware.
>
> Subject - I do not see any future SoCs in the binding. Which future SoCs
> are you documenting here?
>
You're right.
The "future SoCs" wording is not justified by what is currently
documented. I'll drop that wording.
> >
> > Signed-off-by: Francisco Munoz Ruiz <francisco.ruiz@oss.qualcomm.com>
> > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > ---
> > .../devicetree/bindings/cache/qcom,llcc.yaml | 29 ++++++++++++++++++----
> > 1 file changed, 24 insertions(+), 5 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> > index 995d57815781..ca1313de10ca 100644
> > --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> > +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> > @@ -11,16 +11,17 @@ maintainers:
> >
> > description: |
> > LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
> > - that can be shared by multiple clients. Clients here are different cores in the
> > - SoC, the idea is to minimize the local caches at the clients and migrate to
> > - common pool of memory. Cache memory is divided into partitions called slices
> > - which are assigned to clients. Clients can query the slice details, activate
> > - and deactivate them.
> > + that can be shared by multiple clients. Clients here are different cores in
> > + the SoC. The idea is to minimize the local caches at the clients and migrate
> > + to a common pool of memory. Cache memory is divided into partitions called
> > + slices which are assigned to clients. Clients can query the slice details,
> > + activate and deactivate them.
>
> I don't get why you are changing this. I read it and still cannot find
> the difference.
>
> Introducing irrelevant changes only obfuscates the work you are doing
> here.
>
> Best regards,
> Krzysztof
>
Agreed — The description change is unnecessary.
I'll fix both in a V2 of the series once more feedback is collected.
Thank you,
Francisco.
^ permalink raw reply
* Re: (subset) [PATCH v3 0/2] dt-bindings: power: reset: cortina: Convert to DT schema and rename node
From: Sebastian Reichel @ 2026-04-02 22:54 UTC (permalink / raw)
To: sre, robh, krzk+dt, conor+dt, ulli.kroll, linusw,
Khushal Chitturi
Cc: daniel.baluta, simona.toaca, d-gole, m-chawdhry, linux-pm,
devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260330110135.10316-1-khushalchitturi@gmail.com>
On Mon, 30 Mar 2026 16:31:33 +0530, Khushal Chitturi wrote:
> Convert the Cortina Systems Gemini Poweroff Controller bindings to
> DT schema and update corresponding dtsi file with new node name
>
Applied, thanks!
[1/2] dt-bindings: power: reset: cortina,gemini-power-controller: convert to DT schema
commit: 64a97c98f93e344be00d4ff10fef4119973938bd
Best regards,
--
Sebastian Reichel <sebastian.reichel@collabora.com>
^ permalink raw reply
* [PATCH RFC v2 0/6] Add support for Adreno 810 GPU
From: Alexander Koskovich @ 2026-04-02 23:08 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Akhil P Oommen,
Bjorn Andersson
Cc: Luca Weiss, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Alexander Koskovich, Konrad Dybcio
Adreno 810 is present in the Milos SoC and is the first GPU to be released in
the A8x family.
Note that the OPP table is limited to 1050MHz to start with as the only Milos
device I have is limited to that speed in GPU_CC_FREQ_LIMIT_VAL.
This series is marked as RFC because it depends on a couple other in review
series, batch 2 for A8x [1] and the GXCLKCTL block for Milos [2].
There is also currently an issue on Milos with gx_clkctl_gx_gdsc being stuck on
during runtime PM [3]. The proper fix is to only toggle the GX GDSC during GMU
recovery, as the firmware manages it in all other cases. This is the same issue
seen on SM8750 and is being worked on by Qualcomm. Right now I am just working
around this locally by not collapsing the GX GDSC during runtime suspend.
[1]: https://lore.kernel.org/linux-arm-msm/20260327-a8xx-gpu-batch2-v2-0-2b53c38d2101@oss.qualcomm.com
[2]: https://lore.kernel.org/linux-arm-msm/20260306-milos-gxclkctl-v1-0-00b09ee159a7@fairphone.com
[3]: https://lore.kernel.org/linux-arm-msm/5409e13e-280c-47b6-a29f-351cb609bc6f@oss.qualcomm.com
Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
Changes in v2:
- Mark as RFC due to dependency on in-review changes
- Explain in DTS commit why qcom,kaanapali-gxclkctl.h and not qcom,milos-gxclkctl.h
- cx_mmio -> cx_misc_mmio
- Sync a810_nonctxt_regs with GRAPHICS.LA.14.0.r5-03100-lanai.0
- Link to v1: https://lore.kernel.org/r/20260331-adreno-810-v1-0-725801dbb12b@pm.me
---
Alexander Koskovich (6):
dt-bindings: display/msm/gmu: Document Adreno 810 GMU
drm/msm/adreno: rename llc_mmio to cx_misc_mmio
drm/msm/adreno: set cx_misc_mmio regardless of if platform has LLCC
drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound feature
drm/msm/adreno: add Adreno 810 GPU support
arm64: dts: qcom: milos: Add Adreno 810 GPU and GMU nodes
.../devicetree/bindings/display/msm/gmu.yaml | 32 +++
arch/arm64/boot/dts/qcom/milos.dtsi | 148 +++++++++++
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 271 +++++++++++++++++++++
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 44 ++--
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 14 +-
drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 11 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +
8 files changed, 493 insertions(+), 40 deletions(-)
---
base-commit: 128d2eccd20bd74fd104b412d949d869aa48f108
change-id: 20260330-adreno-810-5a47525522cd
Best regards,
--
Alexander Koskovich <akoskovich@pm.me>
^ permalink raw reply
* [PATCH RFC v2 1/6] dt-bindings: display/msm/gmu: Document Adreno 810 GMU
From: Alexander Koskovich @ 2026-04-02 23:09 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Akhil P Oommen,
Bjorn Andersson
Cc: Luca Weiss, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Alexander Koskovich
In-Reply-To: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me>
Document Adreno 810 GMU in the dt-binding specification.
Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
.../devicetree/bindings/display/msm/gmu.yaml | 32 ++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index e32056ae0f5d..2853f6aef966 100644
--- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
@@ -299,6 +299,38 @@ allOf:
required:
- qcom,qmp
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,adreno-gmu-810.0
+ then:
+ properties:
+ reg:
+ items:
+ - description: Core GMU registers
+ reg-names:
+ items:
+ - const: gmu
+ clocks:
+ items:
+ - description: GPU AHB clock
+ - description: GMU clock
+ - description: GPU CX clock
+ - description: GPU AXI clock
+ - description: GPU MEMNOC clock
+ - description: GMU HUB clock
+ - description: GPUSS DEMET clock
+ clock-names:
+ items:
+ - const: ahb
+ - const: gmu
+ - const: cxo
+ - const: axi
+ - const: memnoc
+ - const: hub
+ - const: demet
+
- if:
properties:
compatible:
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v2 2/6] drm/msm/adreno: rename llc_mmio to cx_misc_mmio
From: Alexander Koskovich @ 2026-04-02 23:09 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Akhil P Oommen,
Bjorn Andersson
Cc: Luca Weiss, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Alexander Koskovich
In-Reply-To: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me>
This region is used for more than just LLCC, it also provides access to
software fuse values (raytracing, etc).
Rename relevant symbols from _llc to _cx_misc for use in a follow up
change that decouples this from LLCC.
Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++----
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++--------
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 14 +++++++-------
drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 2 +-
4 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 916c5d99c4d1..23e5b3a22ea5 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -947,7 +947,7 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
/* Turn on TCM (Tightly Coupled Memory) retention */
if (adreno_is_a7xx(adreno_gpu))
- a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1);
+ a6xx_cx_misc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1);
else if (!adreno_is_a8xx(adreno_gpu))
gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
@@ -1215,7 +1215,7 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx_gpu)
if (!qcom_scm_is_available()) {
dev_warn_once(gpu->dev->dev,
"SCM is not available, poking fuse register\n");
- a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
+ a6xx_cx_misc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
@@ -1236,7 +1236,7 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx_gpu)
* firmware, find out whether that's the case. The scm call
* above sets the fuse register.
*/
- fuse_val = a6xx_llc_read(a6xx_gpu,
+ fuse_val = a6xx_cx_misc_read(a6xx_gpu,
REG_A7XX_CX_MISC_SW_FUSE_VALUE);
adreno_gpu->has_ray_tracing =
!!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING);
@@ -1299,7 +1299,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
/* Check to see if we are doing a cold or warm boot */
if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) {
- status = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ?
+ status = a6xx_cx_misc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ?
GMU_WARM_BOOT : GMU_COLD_BOOT;
} else if (gmu->legacy) {
status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index e1eae6cb1e40..9847f83b92af 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2039,7 +2039,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
struct msm_gpu *gpu = &adreno_gpu->base;
u32 cntl1_regval = 0;
- if (IS_ERR(a6xx_gpu->llc_mmio))
+ if (IS_ERR(a6xx_gpu->cx_misc_mmio))
return;
if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
@@ -2078,14 +2078,14 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
* pagetables
*/
if (!a6xx_gpu->have_mmu500) {
- a6xx_llc_write(a6xx_gpu,
+ a6xx_cx_misc_write(a6xx_gpu,
REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval);
/*
* Program cacheability overrides to not allocate cache
* lines on a write miss
*/
- a6xx_llc_rmw(a6xx_gpu,
+ a6xx_cx_misc_rmw(a6xx_gpu,
REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03);
return;
}
@@ -2098,7 +2098,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
struct msm_gpu *gpu = &adreno_gpu->base;
- if (IS_ERR(a6xx_gpu->llc_mmio))
+ if (IS_ERR(a6xx_gpu->cx_misc_mmio))
return;
if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
@@ -2151,15 +2151,15 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
of_node_put(phandle);
if (is_a7xx || !a6xx_gpu->have_mmu500)
- a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem");
+ a6xx_gpu->cx_misc_mmio = msm_ioremap(pdev, "cx_mem");
else
- a6xx_gpu->llc_mmio = NULL;
+ a6xx_gpu->cx_misc_mmio = NULL;
a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
- a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
+ a6xx_gpu->cx_misc_mmio = ERR_PTR(-EINVAL);
}
#define GBIF_CLIENT_HALT_MASK BIT(0)
@@ -2560,7 +2560,7 @@ static int a6xx_read_speedbin(struct device *dev, struct a6xx_gpu *a6xx_gpu,
return ret;
if (info->quirks & ADRENO_QUIRK_SOFTFUSE) {
- *speedbin = a6xx_llc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS);
+ *speedbin = a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS);
*speedbin = A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINALFREQLIMIT(*speedbin);
return 0;
}
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index eb431e5e00b1..648608c1c98e 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -102,7 +102,7 @@ struct a6xx_gpu {
bool has_whereami;
- void __iomem *llc_mmio;
+ void __iomem *cx_misc_mmio;
void *llc_slice;
void *htw_llc_slice;
bool have_mmu500;
@@ -240,19 +240,19 @@ static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
return true;
}
-static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
+static inline void a6xx_cx_misc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
{
- return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
+ return msm_rmw(a6xx_gpu->cx_misc_mmio + (reg << 2), mask, or);
}
-static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
+static inline u32 a6xx_cx_misc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
{
- return readl(a6xx_gpu->llc_mmio + (reg << 2));
+ return readl(a6xx_gpu->cx_misc_mmio + (reg << 2));
}
-static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
+static inline void a6xx_cx_misc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
{
- writel(value, a6xx_gpu->llc_mmio + (reg << 2));
+ writel(value, a6xx_gpu->cx_misc_mmio + (reg << 2));
}
#define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \
diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
index 9e6f2ed69247..8b4b022d9a6b 100644
--- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
@@ -103,7 +103,7 @@ void a8xx_gpu_get_slice_info(struct msm_gpu *gpu)
return;
}
- slice_mask &= a6xx_llc_read(a6xx_gpu,
+ slice_mask &= a6xx_cx_misc_read(a6xx_gpu,
REG_A8XX_CX_MISC_SLICE_ENABLE_FINAL);
a6xx_gpu->slice_mask = slice_mask;
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v2 3/6] drm/msm/adreno: set cx_misc_mmio regardless of if platform has LLCC
From: Alexander Koskovich @ 2026-04-02 23:09 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Akhil P Oommen,
Bjorn Andersson
Cc: Luca Weiss, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Alexander Koskovich, Konrad Dybcio
In-Reply-To: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me>
Platforms without a LLCC (e.g. milos) still need to be able to read and
write to the cx_mem region. Previously if LLCC slices were unavailable
the cx_misc_mmio mapping was overwritten with ERR_PTR, causing a crash
when the GMU later accessed cx_mem.
Move the cx_misc_mmio mapping out of a6xx_llc_slices_init() into
a6xx_gpu_init() so that cx_mem mapping is independent of LLCC.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 ++++++++++++++++-------------------
1 file changed, 17 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 9847f83b92af..d691ad1f88b3 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2039,7 +2039,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
struct msm_gpu *gpu = &adreno_gpu->base;
u32 cntl1_regval = 0;
- if (IS_ERR(a6xx_gpu->cx_misc_mmio))
+ if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
return;
if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
@@ -2098,7 +2098,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
struct msm_gpu *gpu = &adreno_gpu->base;
- if (IS_ERR(a6xx_gpu->cx_misc_mmio))
+ if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
return;
if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
@@ -2135,31 +2135,12 @@ static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu)
static void a6xx_llc_slices_init(struct platform_device *pdev,
struct a6xx_gpu *a6xx_gpu, bool is_a7xx)
{
- struct device_node *phandle;
-
/* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */
if (adreno_has_gmu_wrapper(&a6xx_gpu->base))
return;
- /*
- * There is a different programming path for A6xx targets with an
- * mmu500 attached, so detect if that is the case
- */
- phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0);
- a6xx_gpu->have_mmu500 = (phandle &&
- of_device_is_compatible(phandle, "arm,mmu-500"));
- of_node_put(phandle);
-
- if (is_a7xx || !a6xx_gpu->have_mmu500)
- a6xx_gpu->cx_misc_mmio = msm_ioremap(pdev, "cx_mem");
- else
- a6xx_gpu->cx_misc_mmio = NULL;
-
a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
-
- if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
- a6xx_gpu->cx_misc_mmio = ERR_PTR(-EINVAL);
}
#define GBIF_CLIENT_HALT_MASK BIT(0)
@@ -2621,6 +2602,7 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
struct platform_device *pdev = priv->gpu_pdev;
struct adreno_platform_config *config = pdev->dev.platform_data;
const struct adreno_info *info = config->info;
+ struct device_node *phandle;
struct device_node *node;
struct a6xx_gpu *a6xx_gpu;
struct adreno_gpu *adreno_gpu;
@@ -2656,6 +2638,20 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx);
+ /*
+ * There is a different programming path for A6xx targets with an
+ * mmu500 attached, so detect if that is the case
+ */
+ phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0);
+ a6xx_gpu->have_mmu500 = (phandle &&
+ of_device_is_compatible(phandle, "arm,mmu-500"));
+ of_node_put(phandle);
+
+ if (is_a7xx || !a6xx_gpu->have_mmu500)
+ a6xx_gpu->cx_misc_mmio = msm_ioremap(pdev, "cx_mem");
+ else
+ a6xx_gpu->cx_misc_mmio = NULL;
+
ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info);
if (ret) {
a6xx_llc_slices_destroy(a6xx_gpu);
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v2 4/6] drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound feature
From: Alexander Koskovich @ 2026-04-02 23:09 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Akhil P Oommen,
Bjorn Andersson
Cc: Luca Weiss, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Alexander Koskovich, Konrad Dybcio
In-Reply-To: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me>
A8XX GPUs have two sets of protect registers: 64 global slots and 16
pipe specific slots. The last-span-unbound feature is only available
on pipe protect registers, and should always target pipe slot 15.
This matches the downstream driver which hardcodes pipe slot 15 for
all A8XX GPUs (GRAPHICS.LA.15.0.r1) and resolves protect errors on
A810.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
index 8b4b022d9a6b..102d5e751536 100644
--- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
@@ -252,11 +252,12 @@ static void a8xx_set_cp_protect(struct msm_gpu *gpu)
}
/*
- * Last span feature is only supported on PIPE specific register.
- * So update those here
+ * Last span setting is only being applied to the last pipe specific
+ * register. Hence duplicate the last span from protect reg into the
+ * BR and BV protect reg pipe 15.
*/
- a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg);
- a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg);
+ a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg);
+ a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg);
a8xx_aperture_clear(gpu);
}
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v2 5/6] drm/msm/adreno: add Adreno 810 GPU support
From: Alexander Koskovich @ 2026-04-02 23:09 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Akhil P Oommen,
Bjorn Andersson
Cc: Luca Weiss, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Alexander Koskovich
In-Reply-To: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me>
Add catalog entry and register configuration for the Adreno 810
found in Qualcomm SM7635 (Milos) based devices.
Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 271 ++++++++++++++++++++++++++++++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +
2 files changed, 276 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 550ff3a9b82e..8a57e6f9cee0 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1799,6 +1799,240 @@ static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = {
};
DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist);
+static const struct adreno_reglist_pipe a810_nonctxt_regs[] = {
+ { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
+ { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00f80800, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BR) },
+ { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000023, BIT(PIPE_BV) }, /* Avoid partial waves at VFD */
+ { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
+ { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
+ { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
+ { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
+ { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
+ { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
+ { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
+ { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
+ { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
+ { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
+ /*
+ * BIT(22): Disable PS out of order retire
+ * BIT(23): Enable half wave mode and MM instruction src&dst is half precision
+ */
+ { REG_A7XX_SP_CHICKEN_BITS_2, BIT(22) | BIT(23), BIT(PIPE_NONE) },
+ { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
+ { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
+ { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
+ { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
+ { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) },
+ { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000724, BIT(PIPE_NONE) },
+ { REG_A6XX_UCHE_MODE_CNTL, 0x00020000, BIT(PIPE_NONE) },
+ { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
+ { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
+ { REG_A8XX_UCHE_CACHE_WAYS, 0x00080000, BIT(PIPE_NONE) },
+ { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
+ { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00100020, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VSC_BIN_SIZE, 0x00010001, BIT(PIPE_NONE) },
+ { REG_A8XX_RB_GC_GMEM_PROTECT, 0x00900000, BIT(PIPE_BR) },
+ { },
+};
+
+static const u32 a810_protect_regs[] = {
+ A6XX_PROTECT_RDONLY(0x00000, 0x03a3),
+ A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
+ A6XX_PROTECT_NORDWR(0x00440, 0x001f),
+ A6XX_PROTECT_RDONLY(0x00580, 0x005f),
+ A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
+ A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
+ A6XX_PROTECT_RDONLY(0x00759, 0x0026),
+ A6XX_PROTECT_RDONLY(0x00789, 0x0000),
+ A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
+ A6XX_PROTECT_NORDWR(0x00800, 0x0029),
+ A6XX_PROTECT_NORDWR(0x00837, 0x00af),
+ A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
+ A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
+ A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
+ A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
+ A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
+ A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
+ A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
+ A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
+ A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
+ A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
+ A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
+ A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
+ A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
+ A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
+ A6XX_PROTECT_NORDWR(0x0ae00, 0x0006),
+ A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
+ A6XX_PROTECT_NORDWR(0x0ae10, 0x036f),
+ A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
+ A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x18400, 0x003f),
+ A6XX_PROTECT_RDONLY(0x18440, 0x013f),
+ A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
+ A6XX_PROTECT_RDONLY(0x1f878, 0x0787),
+ A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
+ A6XX_PROTECT_NORDWR(0x20000, 0x1fff),
+ A6XX_PROTECT_NORDWR(0x27800, 0x007f),
+ A6XX_PROTECT_RDONLY(0x27880, 0x0381),
+ A6XX_PROTECT_NORDWR(0x27882, 0x0001),
+ /* CP_PROTECT_REG[46, 62] are left untouched! */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ A6XX_PROTECT_NORDWR(0x27c02, 0x0000),
+};
+DECLARE_ADRENO_PROTECT(a810_protect, 64);
+
+static const uint32_t a810_pwrup_reglist_regs[] = {
+ REG_A6XX_UCHE_MODE_CNTL,
+ REG_A8XX_UCHE_VARB_IDLE_TIMEOUT,
+ REG_A8XX_UCHE_GBIF_GX_CONFIG,
+ REG_A8XX_UCHE_CACHE_WAYS,
+ REG_A8XX_UCHE_CCHE_MODE_CNTL,
+ REG_A8XX_UCHE_CCHE_CACHE_WAYS,
+ REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN,
+ REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1,
+ REG_A8XX_UCHE_WRITE_THRU_BASE,
+ REG_A8XX_UCHE_WRITE_THRU_BASE + 1,
+ REG_A8XX_UCHE_TRAP_BASE,
+ REG_A8XX_UCHE_TRAP_BASE + 1,
+ REG_A8XX_UCHE_CLIENT_PF,
+ REG_A8XX_VSC_BIN_SIZE,
+ REG_A8XX_RB_CMP_NC_MODE_CNTL,
+ REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP,
+ REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN,
+ REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1,
+ REG_A7XX_SP_READ_SEL,
+};
+DECLARE_ADRENO_REGLIST_LIST(a810_pwrup_reglist);
+
+static const u32 a810_ifpc_reglist_regs[] = {
+ REG_A8XX_RBBM_NC_MODE_CNTL,
+ REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL,
+ REG_A8XX_RBBM_SLICE_NC_MODE_CNTL,
+ REG_A6XX_SP_NC_MODE_CNTL,
+ REG_A7XX_SP_CHICKEN_BITS_2,
+ REG_A7XX_SP_CHICKEN_BITS_3,
+ REG_A6XX_SP_PERFCTR_SHADER_MASK,
+ REG_A6XX_TPL1_NC_MODE_CNTL,
+ REG_A6XX_TPL1_DBG_ECO_CNTL,
+ REG_A6XX_TPL1_DBG_ECO_CNTL1,
+ REG_A8XX_RBBM_PERFCTR_CNTL,
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18),
+ REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19),
+ REG_A8XX_CP_PROTECT_GLOBAL(0),
+ REG_A8XX_CP_PROTECT_GLOBAL(1),
+ REG_A8XX_CP_PROTECT_GLOBAL(2),
+ REG_A8XX_CP_PROTECT_GLOBAL(3),
+ REG_A8XX_CP_PROTECT_GLOBAL(4),
+ REG_A8XX_CP_PROTECT_GLOBAL(5),
+ REG_A8XX_CP_PROTECT_GLOBAL(6),
+ REG_A8XX_CP_PROTECT_GLOBAL(7),
+ REG_A8XX_CP_PROTECT_GLOBAL(8),
+ REG_A8XX_CP_PROTECT_GLOBAL(9),
+ REG_A8XX_CP_PROTECT_GLOBAL(10),
+ REG_A8XX_CP_PROTECT_GLOBAL(11),
+ REG_A8XX_CP_PROTECT_GLOBAL(12),
+ REG_A8XX_CP_PROTECT_GLOBAL(13),
+ REG_A8XX_CP_PROTECT_GLOBAL(14),
+ REG_A8XX_CP_PROTECT_GLOBAL(15),
+ REG_A8XX_CP_PROTECT_GLOBAL(16),
+ REG_A8XX_CP_PROTECT_GLOBAL(17),
+ REG_A8XX_CP_PROTECT_GLOBAL(18),
+ REG_A8XX_CP_PROTECT_GLOBAL(19),
+ REG_A8XX_CP_PROTECT_GLOBAL(20),
+ REG_A8XX_CP_PROTECT_GLOBAL(21),
+ REG_A8XX_CP_PROTECT_GLOBAL(22),
+ REG_A8XX_CP_PROTECT_GLOBAL(23),
+ REG_A8XX_CP_PROTECT_GLOBAL(24),
+ REG_A8XX_CP_PROTECT_GLOBAL(25),
+ REG_A8XX_CP_PROTECT_GLOBAL(26),
+ REG_A8XX_CP_PROTECT_GLOBAL(27),
+ REG_A8XX_CP_PROTECT_GLOBAL(28),
+ REG_A8XX_CP_PROTECT_GLOBAL(29),
+ REG_A8XX_CP_PROTECT_GLOBAL(30),
+ REG_A8XX_CP_PROTECT_GLOBAL(31),
+ REG_A8XX_CP_PROTECT_GLOBAL(32),
+ REG_A8XX_CP_PROTECT_GLOBAL(33),
+ REG_A8XX_CP_PROTECT_GLOBAL(34),
+ REG_A8XX_CP_PROTECT_GLOBAL(35),
+ REG_A8XX_CP_PROTECT_GLOBAL(36),
+ REG_A8XX_CP_PROTECT_GLOBAL(37),
+ REG_A8XX_CP_PROTECT_GLOBAL(38),
+ REG_A8XX_CP_PROTECT_GLOBAL(39),
+ REG_A8XX_CP_PROTECT_GLOBAL(40),
+ REG_A8XX_CP_PROTECT_GLOBAL(41),
+ REG_A8XX_CP_PROTECT_GLOBAL(42),
+ REG_A8XX_CP_PROTECT_GLOBAL(43),
+ REG_A8XX_CP_PROTECT_GLOBAL(44),
+ REG_A8XX_CP_PROTECT_GLOBAL(45),
+ REG_A8XX_CP_PROTECT_GLOBAL(63),
+};
+DECLARE_ADRENO_REGLIST_LIST(a810_ifpc_reglist);
+
+static const struct adreno_reglist_pipe a810_dyn_pwrup_reglist_regs[] = {
+ { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
+ { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
+ { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) },
+ { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
+ { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
+ { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) },
+ { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) },
+ { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) },
+ { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) },
+ { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
+ { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
+ { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
+ { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
+ { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
+};
+DECLARE_ADRENO_REGLIST_PIPE_LIST(a810_dyn_pwrup_reglist);
+
static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
@@ -2193,6 +2427,43 @@ static const struct adreno_info a8xx_gpus[] = {
{ 252, 2 },
{ 221, 3 },
),
+ }, {
+ .chip_ids = ADRENO_CHIP_IDS(0x44010000),
+ .family = ADRENO_8XX_GEN1,
+ .fw = {
+ [ADRENO_FW_SQE] = "gen80300_sqe.fw",
+ [ADRENO_FW_GMU] = "gen80300_gmu.bin",
+ },
+ .gmem = SZ_512K + SZ_64K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+ ADRENO_QUIRK_HAS_HW_APRIV |
+ ADRENO_QUIRK_PREEMPTION |
+ ADRENO_QUIRK_IFPC,
+ .funcs = &a8xx_gpu_funcs,
+ .zapfw = "gen80300_zap.mbn",
+ .a6xx = &(const struct a6xx_info) {
+ .protect = &a810_protect,
+ .nonctxt_reglist = a810_nonctxt_regs,
+ .pwrup_reglist = &a810_pwrup_reglist,
+ .dyn_pwrup_reglist = &a810_dyn_pwrup_reglist,
+ .ifpc_reglist = &a810_ifpc_reglist,
+ .gbif_cx = a840_gbif,
+ .max_slices = 1,
+ .gmu_chipid = 0x8030000,
+ .bcms = (const struct a6xx_bcm[]) {
+ { .name = "SH0", .buswidth = 16 },
+ { .name = "MC0", .buswidth = 4 },
+ {
+ .name = "ACV",
+ .fixed = true,
+ .perfmode = BIT(2),
+ .perfmode_bw = 10687500,
+ },
+ { /* sentinel */ },
+ },
+ },
+ .preempt_record_size = 4558 * SZ_1K,
}
};
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index c0ee544ce257..d474d88b9152 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -596,6 +596,11 @@ static inline int adreno_is_a8xx(struct adreno_gpu *gpu)
return gpu->info->family >= ADRENO_8XX_GEN1;
}
+static inline int adreno_is_a810(struct adreno_gpu *gpu)
+{
+ return gpu->info->chip_ids[0] == 0x44010000;
+}
+
static inline int adreno_is_x285(struct adreno_gpu *gpu)
{
return gpu->info->chip_ids[0] == 0x44070001;
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v2 6/6] arm64: dts: qcom: milos: Add Adreno 810 GPU and GMU nodes
From: Alexander Koskovich @ 2026-04-02 23:09 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Akhil P Oommen,
Bjorn Andersson
Cc: Luca Weiss, linux-arm-msm, dri-devel, freedreno, devicetree,
linux-kernel, Alexander Koskovich, Konrad Dybcio
In-Reply-To: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me>
Add GPU and GMU devicetree nodes for the Adreno 810 GPU found on
Qualcomm SM7635 (Milos) based devices.
The qcom,kaanapali-gxclkctl.h header can be reused here because
Milos uses the same driver and the GX_CLKCTL_GX_GDSC definition
is identical.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
arch/arm64/boot/dts/qcom/milos.dtsi | 148 ++++++++++++++++++++++++++++++++++++
1 file changed, 148 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index 621f05820826..095c58515117 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
*/
+#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h>
#include <dt-bindings/clock/qcom,milos-camcc.h>
#include <dt-bindings/clock/qcom,milos-dispcc.h>
#include <dt-bindings/clock/qcom,milos-gcc.h>
@@ -1224,6 +1225,153 @@ lpass_ag_noc: interconnect@3c40000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ gpu: gpu@3d00000 {
+ compatible = "qcom,adreno-44010000", "qcom,adreno";
+ reg = <0x0 0x03d00000 0x0 0x40000>,
+ <0x0 0x03d9e000 0x0 0x2000>,
+ <0x0 0x03d61000 0x0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ iommus = <&adreno_smmu 0 0x0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+ #cooling-cells = <2>;
+
+ interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "gfx-mem";
+
+ status = "disabled";
+
+ gpu_zap_shader: zap-shader {
+ memory-region = <&gpu_microcode_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2-adreno",
+ "operating-points-v2";
+
+ opp-264000000 {
+ opp-hz = /bits/ 64 <264000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ opp-peak-kBps = <2136718>;
+ qcom,opp-acd-level = <0xc8295ffd>;
+ };
+
+ opp-362000000 {
+ opp-hz = /bits/ 64 <362000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <2136718>;
+ qcom,opp-acd-level = <0xc02c5ffd>;
+ };
+
+ opp-510000000 {
+ opp-hz = /bits/ 64 <510000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <3972656>;
+ qcom,opp-acd-level = <0x882b5ffd>;
+ };
+
+ opp-644000000 {
+ opp-hz = /bits/ 64 <644000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <5285156>;
+ qcom,opp-acd-level = <0x882a5ffd>;
+ };
+
+ opp-688000000 {
+ opp-hz = /bits/ 64 <688000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-peak-kBps = <6074218>;
+ qcom,opp-acd-level = <0x882a5ffd>;
+ };
+
+ opp-763000000 {
+ opp-hz = /bits/ 64 <763000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <6671875>;
+ qcom,opp-acd-level = <0xa8295ffd>;
+ };
+
+ opp-895000000 {
+ opp-hz = /bits/ 64 <895000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-peak-kBps = <8171875>;
+ qcom,opp-acd-level = <0x88295ffd>;
+ };
+
+ opp-960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <8171875>;
+ qcom,opp-acd-level = <0xa8285ffd>;
+ };
+
+ opp-1050000000 {
+ opp-hz = /bits/ 64 <1050000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <18597656>;
+ qcom,opp-acd-level = <0x88285ffd>;
+ };
+ };
+ };
+
+ gmu: gmu@3d37000 {
+ compatible = "qcom,adreno-gmu-810.0", "qcom,adreno-gmu";
+ reg = <0x0 0x03d37000 0x0 0x68000>;
+ reg-names = "gmu";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_DEMET_CLK>;
+ clock-names = "ahb",
+ "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "hub",
+ "demet";
+
+ power-domains = <&gpucc GPU_CC_CX_GDSC>,
+ <&gxclkctl GX_CLKCTL_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+
+ iommus = <&adreno_smmu 5 0x0>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-350000000 {
+ opp-hz = /bits/ 64 <350000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+ };
+ };
+
gxclkctl: clock-controller@3d64000 {
compatible = "qcom,milos-gxclkctl";
reg = <0x0 0x03d64000 0x0 0x6000>;
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v5 3/3] riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2
From: Yixun Lan @ 2026-04-03 0:05 UTC (permalink / raw)
To: Han Gao
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chukun Pan,
devicetree, linux-riscv, spacemit, linux-kernel, Han Gao
In-Reply-To: <cfe646a5549a2b3fc8a4335c3ab4918599615369.1775148159.git.gaohan@iscas.ac.cn>
Hi Han,
On 00:54 Fri 03 Apr , Han Gao wrote:
> Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the
> OrangePi RV2 board.
>
> The board utilizes a Genesys Logic GL3523 USB3.0 hub.
>
> Define a 3.3v fixed voltage regulator for PCIe and enable PCIe and
> PHY-related Device Tree nodes for the OrangePi RV2.
>
> Co-developed-by: Chukun Pan <amadeus@jmu.edu.cn>
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> ---
> .../boot/dts/spacemit/k1-orangepi-rv2.dts | 80 +++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
> index a6de3753b876..c19952e70c31 100644
> --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
> +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
> @@ -23,6 +23,15 @@ chosen {
> stdout-path = "serial0";
> };
>
> + pcie_vcc_3v3: regulator-pcie-vcc3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "pcie_vcc3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> vcc_5v0: regulator-vcc-5v0 {
> compatible = "regulator-fixed";
> regulator-name = "vcc_5v0";
> @@ -42,6 +51,16 @@ vcc4v0: regulator-vcc4v0 {
> vin-supply = <&vcc_5v0>;
> };
>
> + vcc5v0_usb30: regulator-vcc5v0-usb30 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v0_usb30";
> + enable-active-high;
> + gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&vcc_5v0>;
> + };
> +
> leds {
> compatible = "gpio-leds";
>
> @@ -54,6 +73,10 @@ led1 {
> };
> };
>
> +&combo_phy {
> + status = "okay";
> +};
> +
> ð0 {
> phy-handle = <&rgmii0>;
> phy-mode = "rgmii-id";
> @@ -200,8 +223,65 @@ dldo6 {
> };
> };
>
> +&pcie1_phy {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_3_cfg>;
> + status = "okay";
> +};
> +
> +&pcie1_port {
> + phys = <&pcie1_phy>;
> + vpcie3v3-supply = <&pcie_vcc_3v3>;
> +};
> +
> +&pcie1 {
> + vpcie3v3-supply = <&pcie_vcc_3v3>;
> + status = "okay";
> +};
> +
> +&pcie2_phy {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie2_4_cfg>;
> + status = "okay";
> +};
> +
> +&pcie2_port {
> + phys = <&pcie2_phy>;
> + vpcie3v3-supply = <&pcie_vcc_3v3>;
> +};
> +
> +&pcie2 {
> + vpcie3v3-supply = <&pcie_vcc_3v3>;
> + status = "okay";
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0_2_cfg>;
> status = "okay";
> };
> +
> +&usbphy2 {
> + status = "okay";
> +};
> +
> +&usb_dwc3 {
> + dr_mode = "host";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
Can you put vbus-supply here? see Chukun's patch
http://lore.kernel.org/r/20260402100007.110201-4-amadeus@jmu.edu.cn
> +
> + hub_2_0: hub@1 {
> + compatible = "usb5e3,610";
> + reg = <0x1>;
> + peer-hub = <&hub_3_0>;
..
> + vdd-supply = <&vcc5v0_usb30>;
I think the vdd is vcc_5v0, while vcc5v0_usb30 is the vbus, if we check
page 16 of RV2 schematics, GL3523-QFN75 (USB HUB)'s pin V5, VDDP directly
connect to VCC_5V0
> + };
> +
> + hub_3_0: hub@2 {
> + compatible = "usb5e3,620";
> + reg = <0x2>;
> + peer-hub = <&hub_2_0>;
> + vdd-supply = <&vcc5v0_usb30>;
> + };
> +};
> --
> 2.47.3
>
>
--
Yixun Lan (dlan)
^ permalink raw reply
* Re: [PATCH v2 3/3] riscv: dts: spacemit: enable USB3 on OrangePi RV2
From: Yixun Lan @ 2026-04-03 0:16 UTC (permalink / raw)
To: Chukun Pan
Cc: alex, aou, conor+dt, devicetree, krzk+dt, linux-kernel,
linux-riscv, palmer, pjw, robh, spacemit
In-Reply-To: <20260402130608.133154-1-amadeus@jmu.edu.cn>
Hi Chukun,
On 21:06 Thu 02 Apr , Chukun Pan wrote:
> Hi,
>
> > Can you work with Han for adding USB support[1]? this will simply
> > distribute our effort, and make the review process even harder
>
> Sorry, I didn't consider this.
> Could you drop this patch ([PATCH v2 3/3]...)?
> The first two patches should not cause conflicts.
>
> > > + vbus-supply = <&vcc5v0_usb30>;
> > IMO, the vbus doesn't directly tie to dwc3 host, but to HUB's port
> > so I think this is still wrong, although it may work on the board..
>
> We can switch to the onboard_usb_dev driver after it's merged.
Sure, I think that's a more elegant solution
> Keeping vbus always-on may cause unnecessary waste.
> I won't insist if you think this is wrong.
Currently either way isn't ideal.. but binding vbus to the host is kind
of acceptable to me, if no ojection, I can take this, then we can adjust
later once the USB HUB vbus support[1] landing in tree
https://lore.kernel.org/all/20260223-v6-16-topic-usb-onboard-dev-v5-0-28d3018a8026@pengutronix.de/ [1]
btw, Could you take a look at Han's patch? if you have final say?
https://lore.kernel.org/spacemit/20260403000539-GKB1016296@kernel.org/ [2]
I'd like to push this series to v7.1, it's almost running out of time..
>
> Thanks,
> Chukun
--
Yixun Lan (dlan)
^ permalink raw reply
* Re: [PATCH 2/3] dt-bindings: power: qcom,rpmhpd: Add new power domains and new levels
From: Fenglin Wu @ 2026-04-03 0:27 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Ulf Hansson, Konrad Dybcio, Subbaraman Narayanamurthy,
linux-arm-msm, devicetree, linux-kernel, linux-pm, kernel
In-Reply-To: <20260402-great-affable-panther-1a5ed7@quoll>
On 4/2/2026 4:34 PM, Krzysztof Kozlowski wrote:
> On Wed, Apr 01, 2026 at 02:15:30AM -0700, Fenglin Wu wrote:
>> Add definitions for the new power domains which present in Hawi SoC:
>> - RPMHPD_DCX (Display Core X): supplies VDD_DISP for the display
>> subsystem
>> - RPMHPD_GBX (Graphics Box): supplies VDD_GFX_BX for the GPU/graphics
>> subsystem
>>
>> Also, add constants for new power domain levels that supported in Hawi
>> SoC, including: LOW_SVS_D3_0, LOW_SVS_D1_0, LOW_SVS_D0_0, SVS_L2_0,
>> TURBO_L1_0/1/2, TURBO_L1_0/1/2.
>>
>> Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com>
> This belongs to the binding change. Unless you are not doing it for
> Hawi...
Sure, I will squash patch 1 and patch 2 and resend.
Thanks.
>
> Best regards,
> Krzysztof
>
^ permalink raw reply
* [PATCH v2 0/2] power: qcom,rpmpd: add RPMh power doamins support for Hawi SoC
From: Fenglin Wu @ 2026-04-03 0:35 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Ulf Hansson, Konrad Dybcio
Cc: Subbaraman Narayanamurthy, linux-arm-msm, devicetree,
linux-kernel, linux-pm, kernel, Fenglin Wu, Taniya Das
Add constant definitions for the new power domains and new voltage
levels present in Hawi SoC. Also add RPMH power domain support for
Hawi SoC.
Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com>
---
Changes in v2:
- Squash patch 1 and 2 into a single binding change
- Add trailers for the new patch 2
- Link to v1: https://patch.msgid.link/20260401-haw-rpmhpd-v1-0-c830c79ed8f9@oss.qualcomm.com
---
Fenglin Wu (2):
dt-bindings: power: qcom,rpmhpd: Add RPMh power domain for Hawi SoC
pmdomain: qcom: rpmhpd: Add power domains for Hawi SoC
.../devicetree/bindings/power/qcom,rpmpd.yaml | 1 +
drivers/pmdomain/qcom/rpmhpd.c | 38 ++++++++++++++++++++++
include/dt-bindings/power/qcom,rpmhpd.h | 12 +++++++
3 files changed, 51 insertions(+)
---
base-commit: 33b1a2ee3a3df63e7a08e51e6de2b2d28ddf257f
change-id: 20260401-haw-rpmhpd-b40a68a3ce79
Best regards,
--
Fenglin Wu <fenglin.wu@oss.qualcomm.com>
^ permalink raw reply
* [PATCH v2 1/2] dt-bindings: power: qcom,rpmhpd: Add RPMh power domain for Hawi SoC
From: Fenglin Wu @ 2026-04-03 0:35 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Ulf Hansson, Konrad Dybcio
Cc: Subbaraman Narayanamurthy, linux-arm-msm, devicetree,
linux-kernel, linux-pm, kernel, Fenglin Wu
In-Reply-To: <20260402-haw-rpmhpd-v2-0-2bce0767f2ca@oss.qualcomm.com>
Document the RPMh power domain for Hawi SoC, and add definitions for
the new power domains which present in Hawi SoC:
- RPMHPD_DCX (Display Core X): supplies VDD_DISP for the display
subsystem
- RPMHPD_GBX (Graphics Box): supplies VDD_GFX_BX for the GPU/graphics
subsystem
Also, add constants for new power domain levels that supported in Hawi
SoC, including: LOW_SVS_D3_0, LOW_SVS_D1_0, LOW_SVS_D0_0, SVS_L2_0,
TURBO_L1_0/1/2, TURBO_L1_0/1/2.
Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com>
---
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 +
include/dt-bindings/power/qcom,rpmhpd.h | 12 ++++++++++++
2 files changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
index 27af5b8aa134..35a0e01c2015 100644
--- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
+++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
@@ -18,6 +18,7 @@ properties:
oneOf:
- enum:
- qcom,glymur-rpmhpd
+ - qcom,hawi-rpmhpd
- qcom,kaanapali-rpmhpd
- qcom,mdm9607-rpmpd
- qcom,milos-rpmhpd
diff --git a/include/dt-bindings/power/qcom,rpmhpd.h b/include/dt-bindings/power/qcom,rpmhpd.h
index 06851363ae0e..67e2634fdc99 100644
--- a/include/dt-bindings/power/qcom,rpmhpd.h
+++ b/include/dt-bindings/power/qcom,rpmhpd.h
@@ -28,15 +28,20 @@
#define RPMHPD_XO 18
#define RPMHPD_NSP2 19
#define RPMHPD_GMXC 20
+#define RPMHPD_DCX 21
+#define RPMHPD_GBX 22
/* RPMh Power Domain performance levels */
#define RPMH_REGULATOR_LEVEL_RETENTION 16
#define RPMH_REGULATOR_LEVEL_MIN_SVS 48
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D3_0 49
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D3 50
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1 51
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1 54
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1_0 55
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0_0 59
#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60
#define RPMH_REGULATOR_LEVEL_LOW_SVS 64
#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72
@@ -47,6 +52,7 @@
#define RPMH_REGULATOR_LEVEL_SVS_L0 144
#define RPMH_REGULATOR_LEVEL_SVS_L1 192
#define RPMH_REGULATOR_LEVEL_SVS_L2 224
+#define RPMH_REGULATOR_LEVEL_SVS_L2_0 225
#define RPMH_REGULATOR_LEVEL_NOM 256
#define RPMH_REGULATOR_LEVEL_NOM_L0 288
#define RPMH_REGULATOR_LEVEL_NOM_L1 320
@@ -54,8 +60,14 @@
#define RPMH_REGULATOR_LEVEL_TURBO 384
#define RPMH_REGULATOR_LEVEL_TURBO_L0 400
#define RPMH_REGULATOR_LEVEL_TURBO_L1 416
+#define RPMH_REGULATOR_LEVEL_TURBO_L1_0 417
+#define RPMH_REGULATOR_LEVEL_TURBO_L1_1 418
+#define RPMH_REGULATOR_LEVEL_TURBO_L1_2 419
#define RPMH_REGULATOR_LEVEL_TURBO_L2 432
#define RPMH_REGULATOR_LEVEL_TURBO_L3 448
+#define RPMH_REGULATOR_LEVEL_TURBO_L3_0 449
+#define RPMH_REGULATOR_LEVEL_TURBO_L3_1 450
+#define RPMH_REGULATOR_LEVEL_TURBO_L3_2 451
#define RPMH_REGULATOR_LEVEL_TURBO_L4 452
#define RPMH_REGULATOR_LEVEL_TURBO_L5 456
#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464
--
2.43.0
^ permalink raw reply related
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