* [PATCH v2 2/2] arm64: dts: qcom: Add Motorola Edge 30 (dubai) DTS
From: Val Packett @ 2026-04-03 5:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kees Cook, Tony Luck, Guilherme G. Piccoli
Cc: Val Packett, ~postmarketos/upstreaming, phone-devel,
linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260403054417.167917-1-val@packett.cool>
The Motorola Edge 30 is a smartphone released in 2022.
This commit has the following features working:
- Display (simplefb)
- Touchscreen
- Power and volume buttons
- Storage (UFS 3.1)
- Battery (ADSP battmgr)
- USB (Type-C, 2.0, dual-role)
- Wi-Fi and Bluetooth (WCN6750 hw1.0)
Signed-off-by: Val Packett <val@packett.cool>
---
v2: Apply suggestions from Konrad
v1: https://lore.kernel.org/all/20260329103055.96649-2-val@packett.cool/
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/sm7325-motorola-dubai.dts | 1456 +++++++++++++++++
2 files changed, 1457 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index c46d94bb6dd5..c4d5dba342e3 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -334,6 +334,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-curtana.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-joyeuse.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-nothing-spacewar.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts
new file mode 100644
index 000000000000..3c836e196b19
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts
@@ -0,0 +1,1456 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2026, Val Packett <val@packett.cool>
+ */
+
+/dts-v1/;
+
+/* PM7250B is configured to use SID8/9 */
+#define PM7250B_SID 8
+#define PM7250B_SID1 9
+
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "sm7325.dtsi"
+#include "pm7325.dtsi"
+#include "pm7250b.dtsi"
+#include "pm8350c.dtsi" /* PM7350C */
+#include "pmk8350.dtsi" /* PMK7325 */
+
+/ {
+ model = "Motorola Edge 30";
+ compatible = "motorola,dubai", "qcom,sm7325";
+ chassis-type = "handset";
+
+ aliases {
+ bluetooth0 = &bluetooth;
+ serial0 = &uart5;
+ serial1 = &uart7;
+ wifi0 = &wifi;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "serial0:115200n8";
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ memory-region = <&framebuffer_mem>;
+ width = <1080>;
+ height = <2400>;
+ stride = <(1080 * 4)>;
+ format = "a8r8g8b8";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&kypd_vol_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm7325-pmic-glink",
+ "qcom,qcm6490-pmic-glink",
+ "qcom,pmic-glink";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&fsa4480_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ramoops@ae000000 {
+ compatible = "ramoops";
+ reg = <0x0 0xae000000 0x0 0xc0000>;
+ console-size = <0x40000>;
+ mem-type = <2>;
+ pmsg-size = <0x40000>;
+ record-size = <0x3f800>;
+ };
+
+ removed@c0000000 {
+ reg = <0x0 0xc0000000 0x0 0x5100000>;
+ no-map;
+ };
+
+ framebuffer_mem: framebuffer@e1000000 {
+ reg = <0x0 0xe1000000 0x0 (1080 * 2400 * 4)>;
+ no-map;
+ };
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ size = <0x0 0x8000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ thermal-zones {
+ cam-flash-thermal {
+ thermal-sensors = <&pmk8350_adc_tm 2>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ chg-skin-thermal {
+ thermal-sensors = <&pm7250b_adc_tm 0>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ chg-thermal {
+ thermal-sensors = <&pmk8350_adc_tm 4>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ conn-thermal {
+ thermal-sensors = <&pm7250b_adc_tm 1>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa-1-thermal {
+ thermal-sensors = <&pmk8350_adc_tm 5>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa-2-thermal {
+ thermal-sensors = <&pmk8350_adc_tm 6>;
+
+ /* Reports negative temperature. */
+ status = "disabled";
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ quiet-thermal {
+ thermal-sensors = <&pmk8350_adc_tm 1>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ sdm-skin-thermal {
+ thermal-sensors = <&pmk8350_adc_tm 3>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-thermal {
+ thermal-sensors = <&pmk8350_adc_tm 0>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+ };
+
+ // S2B is really ebi.lvl but it's there for supply map completeness sake.
+ vreg_s2b_0p7: smpb2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s2b_0p7";
+
+ regulator-min-microvolt = <65535>;
+ regulator-max-microvolt = <65535>;
+ regulator-always-on;
+ vin-supply = <&vph_pwr>;
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ wcn6750-pmu {
+ compatible = "qcom,wcn6750-pmu";
+ pinctrl-0 = <&bt_en>;
+ pinctrl-names = "default";
+ vddaon-supply = <&mos_0p95_aon_s10c>;
+ vddasd-supply = <&vreg_l11c_2p8>;
+ vddpmu-supply = <&mos_0p95_dig_s10c>;
+ vddio-supply = <&vdd18_io>;
+ vddrfa0p8-supply = <&vdd09_pmu_rfa_i>;
+ vddrfa1p2-supply = <&vdd13_pmu_rfa_i>;
+ vddrfa1p7-supply = <&vdd19_pmu_rfa_i>;
+ vddrfa2p2-supply = <&vdd22_wlpa_s1c>;
+
+ bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p7: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p7";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm7325-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+
+ vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p952>;
+ vdd-l2-l7-supply = <&vreg_bob>;
+ vdd-l3-supply = <&vreg_s2b_0p7>;
+ vdd-l5-supply = <&vreg_s2b_0p7>;
+ vdd-l6-l9-l10-supply = <&vreg_s8b_1p256>;
+ vdd-l8-supply = <&vreg_s7b_0p952>;
+ vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p856>;
+ vdd-l13-supply = <&vreg_s7b_0p952>;
+ vdd-l14-l16-supply = <&vreg_s8b_1p256>;
+
+ /*
+ * S2, L4-L5 are ARCs:
+ * S2 - ebi.lvl,
+ * L4 - lmx.lvl,
+ * l5 - lcx.lvl.
+ *
+ * L10 are unused.
+ */
+
+ vdd19_pmu_rfa_i:
+ vreg_s1b_1p856: smps1 {
+ regulator-name = "vreg_s1b_1p856";
+ regulator-min-microvolt = <1840000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ mos_0p95_aon_s10c:
+ mos_0p95_dig_s10c:
+ vdd09_pmu_rfa_i:
+ vreg_s7b_0p952: smps7 {
+ regulator-name = "vreg_s7b_0p952";
+ regulator-min-microvolt = <535000>;
+ regulator-max-microvolt = <1120000>;
+ };
+
+ vdd13_pmu_rfa_i:
+ vreg_s8b_1p256: smps8 {
+ regulator-name = "vreg_s8b_1p256";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
+ };
+
+ vreg_l1b_0p912: ldo1 {
+ regulator-name = "vreg_l1b_0p912";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <925000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_a_usbhs_3p1:
+ vreg_l2b_3p072: ldo2 {
+ regulator-name = "vreg_l2b_3p072";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3b_0p6: ldo3 {
+ regulator-name = "vreg_l3b_0p6";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <910000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_a_dsi_0_1p2:
+ vdd_a_ufs_0_1p2:
+ vreg_l6b_1p2: ldo6 {
+ regulator-name = "vreg_l6b_1p2";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_2p96: ldo7 {
+ regulator-name = "vreg_l7b_2p96";
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_0p904: ldo8 {
+ regulator-name = "vreg_l8b_0p904";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_1p2: ldo9 {
+ regulator-name = "vreg_l9b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p776: ldo11 {
+ regulator-name = "vreg_l11b_1p776";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_0p8: ldo12 {
+ regulator-name = "vreg_l12b_0p8";
+ regulator-min-microvolt = <751000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_0p8: ldo13 {
+ regulator-name = "vreg_l13b_0p8";
+ regulator-min-microvolt = <530000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_1p2: ldo14 {
+ regulator-name = "vreg_l14b_1p2";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_0p88: ldo15 {
+ regulator-name = "vreg_l15b_0p88";
+ regulator-min-microvolt = <765000>;
+ regulator-max-microvolt = <1020000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_1p2: ldo16 {
+ regulator-name = "vreg_l16b_1p2";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_1p8: ldo17 {
+ regulator-name = "vreg_l17b_1p8";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b_1p8: ldo18 {
+ regulator-name = "vreg_l18b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd18_io:
+ vreg_l19b_1p8: ldo19 {
+ regulator-name = "vreg_l19b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8350c-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l12-supply = <&vreg_s1b_1p856>;
+ vdd-l2-l8-supply = <&vreg_s1b_1p856>;
+ vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
+ vdd-l6-l9-l11-supply = <&vreg_bob>;
+ vdd-l10-supply = <&vreg_s7b_0p952>;
+
+ vdd-bob-supply = <&vph_pwr>;
+
+ /*
+ * S2, S5, S7, S10 are ARCs:
+ * S2 - cx.lvl,
+ * S5 - mss.lvl,
+ * S7 - gfx.lvl,
+ * S10 - mx.lvl.
+ */
+
+ vdd22_wlpa_s1c:
+ vreg_s1c_2p2: smps1 {
+ regulator-name = "vreg_s1c_2p2";
+ regulator-min-microvolt = <2190000>;
+ regulator-max-microvolt = <2210000>;
+ };
+
+ vreg_s9c_0p676: smps9 {
+ regulator-name = "vreg_s9c_0p676";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1170000>;
+ };
+
+ vdd_a_usbhs_1p8:
+ vdd_qfprom:
+ vreg_l1c_1p8: ldo1 {
+ regulator-name = "vreg_l1c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ iovdd_ts:
+ vreg_l2c_1p8: ldo2 {
+ regulator-name = "vreg_l2c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_ts:
+ vreg_l3c_3p0: ldo3 {
+ regulator-name = "vreg_l3c_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c_1p8_3p0: ldo4 {
+ regulator-name = "vreg_l4c_1p8_3p0";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5c_1p8_3p0: ldo5 {
+ regulator-name = "vreg_l5c_1p8_3p0";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p96: ldo6 {
+ regulator-name = "vreg_l6c_2p96";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-name = "vreg_l7c_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-name = "vreg_l8c_1p8";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_3p3: ldo9 {
+ regulator-name = "vreg_l9c_2p96";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_a_dsi_0_0p9:
+ vdd_a_ufs_0_core:
+ vdd_a_usbhs_core:
+ vreg_l10c_0p88: ldo10 {
+ regulator-name = "vreg_l10c_0p88";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_2p8: ldo11 {
+ regulator-name = "vreg_l11c_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ disp_iovcc_1p8:
+ vreg_l12c_1p8: ldo12 {
+ regulator-name = "vreg_l12c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ disp_vci_3p0:
+ vreg_l13c_3p0: ldo13 {
+ regulator-name = "vreg_l13c_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ audio_sw_vcc:
+ vreg_bob: bob {
+ regulator-name = "vreg_bob";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+};
+
+&gcc {
+ protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
+ <GCC_MSS_CFG_AHB_CLK>,
+ <GCC_MSS_OFFLINE_AXI_CLK>,
+ <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
+ <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+ <GCC_MSS_SNOC_AXI_CLK>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_SEC_CTRL_CLK_SRC>,
+ <GCC_WPSS_AHB_BDG_MST_CLK>,
+ <GCC_WPSS_AHB_CLK>,
+ <GCC_WPSS_RSCP_CLK>;
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/sm7325/motorola/dubai/a660_zap.mbn";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+
+ typec-mux@42 {
+ compatible = "fcs,fsa4480";
+ reg = <0x42>;
+
+ interrupts-extended = <&tlmm 6 IRQ_TYPE_LEVEL_LOW>;
+
+ vcc-supply = <&audio_sw_vcc>;
+
+ mode-switch;
+ orientation-switch;
+
+ port {
+ fsa4480_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+};
+
+&ipa {
+ firmware-name = "qcom/sm7325/motorola/dubai/yupik_ipa_fws.mbn";
+ memory-region = <&ipa_fw_mem>;
+
+ qcom,gsi-loader = "self";
+
+ status = "okay";
+};
+
+&pm7250b_adc {
+ channel@4e {
+ reg = <ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "chg_skin_therm";
+ };
+
+ channel@4f {
+ reg = <ADC5_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "conn_therm";
+ };
+};
+
+&pm7250b_adc_tm {
+ status = "okay";
+
+ chg-skin-therm@0 {
+ reg = <0>;
+ io-channels = <&pm7250b_adc ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ conn-therm@1 {
+ reg = <1>;
+ io-channels = <&pm7250b_adc ADC5_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
+&pm7250b_gpios {
+ gpio-line-names = "FG_ALERT_N", /* GPIO_1 */
+ "SLAVECP_INT",
+ "NC",
+ "NC",
+ "NC",
+ "DOUBLER_STAT",
+ "NC",
+ "NC",
+ "NC",
+ "NC", /* GPIO_10 */
+ "NC",
+ "NC";
+};
+
+&pm7325_gpios {
+ gpio-line-names = "PA_THERM1", /* GPIO_1 */
+ "NC",
+ "NC",
+ "PA_THERM2",
+ "CBL_PWR_N",
+ "KYPD_VOL_UP_N",
+ "NC",
+ "NC",
+ "NC",
+ "NC"; /* GPIO_10 */
+
+ kypd_vol_up_n: kypd-volp-n-state {
+ pins = "gpio6";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-pull-up;
+ input-enable;
+ power-source = <1>;
+ };
+};
+
+&pm8350c_gpios {
+ gpio-line-names = "NC", /* GPIO_1 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC"; /* GPIO_9 */
+};
+
+&pm8350c_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <1>, <4>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <400000>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <2>, <3>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <400000>;
+ };
+};
+
+&pmk8350_adc_tm {
+ status = "okay";
+
+ xo-therm@0 {
+ reg = <0>;
+ io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ quiet-therm@1 {
+ reg = <1>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ cam-flash-therm@2 {
+ reg = <2>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ sdm-skin-therm@3 {
+ reg = <3>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ chg-therm@4 {
+ reg = <4>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ pa-therm-1@5 {
+ reg = <5>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ pa-therm-2@6 {
+ reg = <6>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO4_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
+&pmk8350_gpios {
+ gpio-line-names = "NC", /* GPIO_0 */
+ "NC",
+ "TP_PMK_GPIO_3",
+ "PMK_OPTION"; /* GPIO_4 */
+};
+
+&pmk8350_rtc {
+ status = "okay";
+};
+
+&pmk8350_vadc {
+ status = "okay";
+
+ channel@44 {
+ reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pmk8350_xo_therm";
+ };
+
+ channel@144 {
+ reg = <PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_quiet_therm";
+ };
+
+ channel@145 {
+ reg = <PM7325_ADC7_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_cam_flash_therm";
+ };
+
+ channel@146 {
+ reg = <PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_sdm_skin_therm";
+ };
+
+ channel@147 {
+ reg = <PM7325_ADC7_AMUX_THM4_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_chg_therm";
+ };
+
+ channel@14a {
+ reg = <PM7325_ADC7_GPIO1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_pa_therm1";
+ };
+
+ channel@14d {
+ reg = <PM7325_ADC7_GPIO4_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_pa_therm2";
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qfprom {
+ vcc-supply = <&vdd_qfprom>;
+};
+
+&qup_spi13_cs {
+ drive-strength = <6>;
+ bias-pull-down;
+};
+
+&qup_spi13_data_clk {
+ drive-strength = <6>;
+ bias-pull-down;
+};
+
+&qup_uart5_rx {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart5_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart7_cts {
+ /*
+ * Configure a bias-bus-hold on CTS to lower power
+ * usage when Bluetooth is turned off. Bus hold will
+ * maintain a low power state regardless of whether
+ * the Bluetooth module drives the pin in either
+ * direction or leaves the pin fully unpowered.
+ */
+ bias-bus-hold;
+};
+
+&qup_uart7_rts {
+ /* We'll drive RTS, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart7_rx {
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module is
+ * in tri-state (module powered off or not driving the
+ * signal yet).
+ */
+ bias-pull-up;
+};
+
+&qup_uart7_tx {
+ /* We'll drive TX, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm7325/motorola/dubai/adsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm7325/motorola/dubai/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/sm7325/motorola/dubai/modem.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_wpss {
+ firmware-name = "qcom/sm7325/motorola/dubai/wpss.mbn";
+
+ status = "okay";
+};
+
+&rmtfs_mem {
+ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>,
+ <QCOM_SCM_VMID_NAV>;
+};
+
+&spi13 {
+ status = "okay";
+
+ touchscreen@0 {
+ compatible = "goodix,gt9916";
+ reg = <0>;
+
+ interrupts-extended = <&tlmm 81 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&tlmm 105 GPIO_ACTIVE_LOW>;
+
+ avdd-supply = <&vdd_ts>;
+ vddio-supply = <&iovdd_ts>;
+
+ spi-max-frequency = <1000000>;
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <2400>;
+
+ pinctrl-0 = <&ts_int_n>, <&ts_reset_n>;
+ pinctrl-names = "default";
+ };
+};
+
+&tlmm {
+ gpio-line-names = "NC", /* GPIO_0 */
+ "NC",
+ "NC",
+ "NC",
+ "SMARTPA_I2C_SDA",
+ "SMARTPA_I2C_SCK",
+ "AUD_4480_DET",
+ "AUD_4480_INT",
+ "FASTCHARGE_I2C_SDA",
+ "FASTCHARGE_I2C_SCL",
+ "SM_GPSLNA_EN_GPIO10", /* GPIO_10 */
+ "NC",
+ "PERI_I2C_SDA",
+ "PERI_I2C_SCL",
+ "NC",
+ "NC",
+ "APPS_I2C_SDA",
+ "APPS_I2C_SCL",
+ "NC",
+ "DISP_LDO_EN",
+ "CAM_FW_RST_N", /* GPIO_20 */
+ "CAM_RM_RST_N",
+ "DBG_UART_TXD",
+ "DBG_UART_RXD",
+ "TOPSB_INT_N",
+ "MCAM_LDO_EN",
+ "HOST2WLAN_SOL",
+ "WLAN2HOST_SOL",
+ "UART_BT_RTS_AP_CTS",
+ "UART_BT_CTS_AP_RTS",
+ "UART_BT_RX_AP_TX", /* GPIO_30 */
+ "UART_BT_TX_AP_RX",
+ "FRONT_60M_INT",
+ "FRONT_60M_RST",
+ "FP_INT",
+ "FP_RST",
+ "NFC_I2C_SDA",
+ "NFC_I2C_SCL",
+ "NFC_EN",
+ "NFC_CLK_REQ",
+ "NFC_SE_SPI_NREST", /* GPIO_40 */
+ "NFC_IRQ",
+ "RF_LDO_GPIO42_EN",
+ "GOOGLE_KEY_INT", /* no such key exists */
+ "DISP_RST_N",
+ "SB_INT_N",
+ "HAP_RST_N",
+ "HAP_INT",
+ "ESE_SPI_MISO",
+ "ESE_SPI_MOSI",
+ "ESE_SPI_CLK", /* GPIO_50 */
+ "ESE_SPI_CS",
+ "TP_SPI_MISO",
+ "TP_SPI_MOSI",
+ "TP_SPI_CLK",
+ "TP_SPI_CS_N",
+ "FP_SPI_MISO",
+ "FP_SPI_MOSI",
+ "FP_SPI_CLK",
+ "FP_SPI_CS_N",
+ "HW_ID_1", /* GPIO_60 */
+ "HW_ID_2",
+ "CAM_PMU_EN",
+ "WIDE_DVDD_LDO_EN",
+ "CAM_MCLK0",
+ "CAM_MCLK1",
+ "CAM_MCLK2",
+ "CAM_MCLK3",
+ "NC",
+ "CCI_I2C_SDA0",
+ "CCI_I2C_SCL0", /* GPIO_70 */
+ "CCI_I2C_SDA1",
+ "CCI_I2C_SCL1",
+ "CCI_I2C_SDA2",
+ "CCI_I2C_SCL2",
+ "CCI_I2C_SDA3",
+ "CCI_I2C_SCL3",
+ "CAM_RT_RST_N",
+ "CAM_RU_RST_N",
+ "FCAM_LDO_EN",
+ "DISP_TE", /* GPIO_80 */
+ "TP_INT_N",
+ "FORCED_USB_BOOT",
+ "SM_CDC_RST_N",
+ "WLAN_EN",
+ "BT_EN",
+ "WCN_SW_CTRL",
+ "PCIE0_RESET_N",
+ "PCIE0_CLK_REQ_N",
+ "PCIE0_WAKE_N",
+ "MOS_AS_EN", /* GPIO_90 */
+ "NC",
+ "",
+ "NC",
+ "BT_FM_SLIMBUS_CLK",
+ "BT_FM_SLIMBUS_DATA",
+ "NC",
+ "RFCONN_DET_1",
+ "RF_CON_DET_2",
+ "RF_CON_DET_3",
+ "NC", /* GPIO_100 */
+ "NC",
+ "NC",
+ "ACCEL_INT",
+ "NC",
+ "TP_RST_N",
+ "NC",
+ "NC",
+ "NC",
+ "UIM2_DATA",
+ "UIM2_CLK", /* GPIO_110 */
+ "UIM2_RESET",
+ "UIM2_PRESENT",
+ "UIM1_DATA",
+ "UIM1_CLK",
+ "UIM1_RESET",
+ "UIM1_PRESENT",
+ "SM_RFFE0_CLK",
+ "SM_RFFE0_DATA",
+ "SM_RFFE1_CLK",
+ "SM_RFFE1_DATA", /* GPIO_120 */
+ "PA_MUTING",
+ "SM_GRFC5",
+ "LAA_RX",
+ "SM_GRFC7",
+ "SM_RFFE4_CLK",
+ "SM_RFFE4_DATA",
+ "WLAN_COEX_UART_RX",
+ "WLAN_COEX_UART_TX",
+ "NC",
+ "NC", /* GPIO_130 */
+ "SM_GRFC12",
+ "NC",
+ "QLINK0_REQUEST",
+ "QLINK0_ENABLE",
+ "QLINK0_WMSS_RESET_N",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "USB_CC_DIR", /* GPIO_140 */
+ "SAR_INT_N",
+ "PROX_INT_N",
+ "",
+ "SM_SWR_TX_CLK",
+ "SM_SWR_TX_DATA0",
+ "SM_SWR_TX_DATA1",
+ "SM_SWR_RX_CLK",
+ "SM_SWR_RX_DATA0",
+ "SM_SWR_RX_DATA1",
+ "NC", /* GPIO_150 */
+ "NC",
+ "NC",
+ "NC",
+ "SB_MI2S_SCK",
+ "SB_MI2S_WS",
+ "SB_MI2S_RXDAT_AP_TX",
+ "SB_MI2S_TXDAT_AP_RX",
+ "NC",
+ "SNS_I3C0_SDA",
+ "SNS_I3C0_SCL", /* GPIO_160 */
+ "SSC_I2C4_SDA",
+ "SSC_I2C4_SCL",
+ "MAG_I2C_SDA",
+ "MAG_I2C_SCL",
+ "NC",
+ "NC",
+ "",
+ "",
+ "",
+ "", /* GPIO_170 */
+ "SSC_BT_UART4_TX",
+ "SSC_BT_UART4_RX",
+ "NC",
+ "NC";
+ gpio-reserved-ranges = <48 4>, /* SPI (eSE - embedded Secure Element) */
+ <56 4>; /* SPI (fingerprint reader) */
+
+ qup_uart7_sleep_cts: qup-uart7-sleep-cts-state {
+ pins = "gpio28";
+ function = "gpio";
+ /*
+ * Configure a bias-bus-hold on CTS to lower power
+ * usage when Bluetooth is turned off. Bus hold will
+ * maintain a low power state regardless of whether
+ * the Bluetooth module drives the pin in either
+ * direction or leaves the pin fully unpowered.
+ */
+ bias-bus-hold;
+ };
+
+ qup_uart7_sleep_rts: qup-uart7-sleep-rts-state {
+ pins = "gpio29";
+ function = "gpio";
+ /*
+ * Configure pull-down on RTS. As RTS is active low
+ * signal, pull it low to indicate the BT SoC that it
+ * can wakeup the system anytime from suspend state by
+ * pulling RX low (by sending wakeup bytes).
+ */
+ bias-pull-down;
+ };
+
+ qup_uart7_sleep_tx: qup-uart7-sleep-tx-state {
+ pins = "gpio30";
+ function = "gpio";
+ /*
+ * Configure pull-up on TX when it isn't actively driven
+ * to prevent BT SoC from receiving garbage during sleep.
+ */
+ bias-pull-up;
+ };
+
+ qup_uart7_sleep_rx: qup-uart7-sleep-rx-state {
+ pins = "gpio31";
+ function = "gpio";
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module
+ * is floating which may cause spurious wakeups.
+ */
+ bias-pull-up;
+ };
+
+ oled_reset_n: oled-reset-n-state {
+ pins = "gpio44";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ aw86224_reset_default: aw86224-reset-default-state {
+ pins = "gpio46";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ aw86224_int_default: aw86224-int-default-state {
+ pins = "gpio47";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ mdp_vsync_p: mdp-vsync-p-state {
+ pins = "gpio80";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ ts_int_n: ts-int-n-state {
+ pins = "gpio81";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ bt_en: bt-en-state {
+ pins = "gpio85";
+ function = "gpio";
+ output-low;
+ bias-disable;
+ };
+
+ ts_reset_n: ts-int-n-state {
+ pins = "gpio105";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&uart7 {
+ /delete-property/ interrupts;
+ interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-1 = <&qup_uart7_sleep_cts>,
+ <&qup_uart7_sleep_rts>,
+ <&qup_uart7_sleep_tx>,
+ <&qup_uart7_sleep_rx>;
+ pinctrl-names = "default",
+ "sleep";
+
+ status = "okay";
+
+ bluetooth: bluetooth {
+ compatible = "qcom,wcn6750-bt";
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+
+ max-speed = <3200000>;
+
+ qcom,local-bd-address-broken;
+ };
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l7b_2p96>;
+ vcc-max-microamp = <800000>;
+
+ vccq-supply = <&vreg_l9b_1p2>;
+ vccq-max-microamp = <900000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vdd_a_ufs_0_core>;
+ vdda-pll-supply = <&vdd_a_ufs_0_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ /* USB 2.0 only */
+ qcom,select-utmi-as-pipe-clk;
+ maximum-speed = "high-speed";
+
+ /* Remove USB3 phy */
+ phys = <&usb_1_hsphy>;
+ phy-names = "usb2-phy";
+
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&vdd_a_usbhs_core>;
+ vdda18-supply = <&vdd_a_usbhs_1p8>;
+ vdda33-supply = <&vdd_a_usbhs_3p1>;
+
+ status = "okay";
+};
+
+&venus {
+ firmware-name = "qcom/sm7325/motorola/dubai/vpu20_1v.mbn";
+
+ status = "okay";
+};
+
+&wifi {
+ qcom,calibration-variant = "Motorola_dubai";
+
+ status = "okay";
+};
--
2.53.0
^ permalink raw reply related
* [PATCH v1 00/13] Add StarFive JHB100 syscon modules
From: Changhuang Liang @ 2026-04-03 5:49 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Ley Foon Tan, Changhuang Liang
StarFive JHB100 has many syscon modules, as listed below:
- pcieep0_ecsr_syscon (PCIe endpoint 0 externel syscon)
- pcieep1_ecsr_syscon
- host0_syscon (Host0 syscon)
- host1_syscon
- husb0_syscon (Host USB 0 syscon)
- husb1_syscon
- husbd0_syscon (Host USB device 0 syscon)
- husbd1_syscon
- husbcmn_syscon (Host USB common)
- gpu0_syscon (GPU0 syscon)
- gpu1_syscon
- b2h0_syscon (BMC to Host0 syscon)
- b2h1_syscon (BMC to Host1 syscon)
- h02b_syscon (Host0 to BMC syscon)
- h12b_syscon (Host1 to BMC syscon)
- vout_syscon (Video output syscon)
- pcierp_ecsr_syscon (PCIe root port externel syscon)
- pcierp_syscon (PCIe root port syscon)
- usb_syscon
- npu_syscon
- per0_syscon (Peripheral 0 syscon)
- per1_syscon
- per2_syscon
- per3_syscon
- sys0_syscon (System 0 syscon)
- sys1_syscon
- sys2_syscon
- strap_syscon
Some syscon modules contain PLL, reset, and socinfo nodes
This series will add these syscon modules, as well as the
nodes under them.
-PATCH 1: syscon binging
-PATCH 2-7: syscon PLL driver
-PATCH 8-10: syscon reset driver
-PATCH 11-12: syscon socinfo driver
-PATCH 13: syscon device tree
This series depends on the series:
https://lore.kernel.org/all/20260402105523.447523-1-changhuang.liang@starfivetech.com/
Changhuang Liang (13):
dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
dt-bindings: clock: Add system-0 domain PLL clock
clk: starfive: Add system-0 domain PLL clock driver
dt-bindings: clock: Add peripheral-0 domain PLL clock
clk: starfive: Add peripheral-0 domain PLL clock driver
dt-bindings: clock: Add peripheral-1 domain PLL clock
clk: starfive: Add Peripheral-1 domain PLL clock driver
dt-bindings: reset: Add StarFive JHB100 reset generator
reset: starfive: Introduce assert_polarity
reset: starfive: Add syscon reset driver support
dt-bindings: hwinfo: Add starfive,jhb100-socinfo
soc: starfive: Add socinfo driver for JHB100 SoC
riscv: dts: starfive: jhb100: Add syscon nodes
.../bindings/clock/starfive,jhb100-pll.yaml | 46 ++
.../hwinfo/starfive,jhb100-socinfo.yaml | 36 ++
.../reset/starfive,jhb100-reset-pcierp.yaml | 38 ++
.../soc/starfive/starfive,jhb100-syscon.yaml | 140 +++++
MAINTAINERS | 11 +
arch/riscv/boot/dts/starfive/jhb100.dtsi | 220 +++++--
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-pll.c | 554 ++++++++++++++++++
drivers/reset/starfive/Kconfig | 9 +
drivers/reset/starfive/Makefile | 1 +
.../reset/starfive/reset-starfive-common.c | 51 +-
.../reset/starfive/reset-starfive-common.h | 5 +
.../starfive/reset-starfive-jhb100-syscon.c | 48 ++
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/starfive/Kconfig | 6 +
drivers/soc/starfive/Makefile | 2 +
drivers/soc/starfive/socinfo/Kconfig | 11 +
drivers/soc/starfive/socinfo/Makefile | 2 +
drivers/soc/starfive/socinfo/jhb100-socinfo.c | 90 +++
.../dt-bindings/clock/starfive,jhb100-crg.h | 12 +
.../dt-bindings/reset/starfive,jhb100-crg.h | 3 +
23 files changed, 1259 insertions(+), 37 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
create mode 100644 Documentation/devicetree/bindings/hwinfo/starfive,jhb100-socinfo.yaml
create mode 100644 Documentation/devicetree/bindings/reset/starfive,jhb100-reset-pcierp.yaml
create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-pll.c
create mode 100644 drivers/reset/starfive/reset-starfive-jhb100-syscon.c
create mode 100644 drivers/soc/starfive/Kconfig
create mode 100644 drivers/soc/starfive/Makefile
create mode 100644 drivers/soc/starfive/socinfo/Kconfig
create mode 100644 drivers/soc/starfive/socinfo/Makefile
create mode 100644 drivers/soc/starfive/socinfo/jhb100-socinfo.c
--
2.25.1
^ permalink raw reply
* [PATCH v1 01/13] dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
From: Changhuang Liang @ 2026-04-03 5:49 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>
Add documentation to describe StarFive JHB100 SoC System Controller
Registers.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../soc/starfive/starfive,jhb100-syscon.yaml | 140 ++++++++++++++++++
MAINTAINERS | 5 +
2 files changed, 145 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
new file mode 100644
index 000000000000..c0e1f6f68fa2
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/starfive,jhb100-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 SoC system controller
+
+maintainers:
+ - Kevin Xie <kevin.xie@starfivetech.com>
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+description:
+ The StarFive JHB100 SoC system controller provides register information such
+ as offset, mask and shift to configure related modules such as PLL and PCIe.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - starfive,jhb100-pcierp-syscon
+ - starfive,jhb100-per0-syscon
+ - starfive,jhb100-per1-syscon
+ - starfive,jhb100-sys0-syscon
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - enum:
+ - starfive,jhb100-b2h-syscon
+ - starfive,jhb100-gpu-syscon
+ - starfive,jhb100-h2b-syscon
+ - starfive,jhb100-host-syscon
+ - starfive,jhb100-husb-syscon
+ - starfive,jhb100-husbcmn-syscon
+ - starfive,jhb100-husbd-syscon
+ - starfive,jhb100-npu-syscon
+ - starfive,jhb100-pcieep-ecsr-syscon
+ - starfive,jhb100-pcierp-ecsr-syscon
+ - starfive,jhb100-per2-syscon
+ - starfive,jhb100-per3-syscon
+ - starfive,jhb100-strap-syscon
+ - starfive,jhb100-sys1-syscon
+ - starfive,jhb100-sys2-syscon
+ - starfive,jhb100-usb-syscon
+ - starfive,jhb100-vout-syscon
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clock-controller:
+ $ref: /schemas/clock/starfive,jhb100-pll.yaml#
+ type: object
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - starfive,jhb100-per0-syscon
+ - starfive,jhb100-per1-syscon
+ - starfive,jhb100-sys0-syscon
+ then:
+ required:
+ - clock-controller
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jhb100-sys0-syscon
+ then:
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ patternProperties:
+ "^chipid@[0-9a-f]+$":
+ $ref: /schemas/hwinfo/starfive,jhb100-socinfo.yaml#
+ type: object
+
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jhb100-pcierp-syscon
+ then:
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ patternProperties:
+ "^reset-controller@[0-9a-f]+$":
+ $ref: /schemas/reset/starfive,jhb100-reset-pcierp.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ syscon@10240000 {
+ compatible = "starfive,jhb100-b2h-syscon", "syscon";
+ reg = <0x0 0x10240000 0x0 0x1000>;
+ };
+
+ syscon@11719000 {
+ compatible = "starfive,jhb100-pcierp-syscon", "syscon",
+ "simple-mfd";
+ reg = <0x0 0x11719000 0x0 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x11719000 0x0 0x1000>;
+
+ reset-controller@14c {
+ compatible = "starfive,jhb100-reset-pcierp";
+ reg = <0x0 0x14c 0x0 0x4>;
+ #reset-cells = <1>;
+ };
+ };
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 4ddf8ba2e60d..eb5f6a383146 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25325,6 +25325,11 @@ S: Maintained
F: drivers/reset/starfive/reset-starfive-jhb1*
F: include/dt-bindings/reset/starfive,jhb1*.h
+STARFIVE JHB100 SYSCON
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+S: Maintained
+F: Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
+
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
--
2.25.1
^ permalink raw reply related
* [PATCH v1 02/13] dt-bindings: clock: Add system-0 domain PLL clock
From: Changhuang Liang @ 2026-04-03 5:49 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>
Add system-0 domain PLL clock for StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../bindings/clock/starfive,jhb100-pll.yaml | 44 +++++++++++++++++++
.../dt-bindings/clock/starfive,jhb100-crg.h | 6 +++
2 files changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
new file mode 100644
index 000000000000..f7ab90c05281
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jhb100-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 PLL Clock Generator
+
+description:
+ These PLLs are high speed, low jitter frequency synthesizers in the JHB100.
+ Each PLL works in integer mode or fraction mode, with configuration
+ registers in the syscon. So the PLLs node should be a child of SYSCON node.
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ enum:
+ - starfive,jhb100-sys0-pll
+
+ clocks:
+ maxItems: 1
+ description: Main Oscillator (25 MHz)
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller {
+ compatible = "starfive,jhb100-sys0-pll";
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index 6b7d53a0391a..719a6eb9b1a4 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -8,6 +8,12 @@
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__
#define __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__
+/* SYS0PLL clocks */
+#define JHB100_SYS0PLL_PLL2_OUT 0
+#define JHB100_SYS0PLL_PLL3_OUT 1
+#define JHB100_SYS0PLL_PLL4_OUT 2
+#define JHB100_SYS0PLL_PLL5_OUT 3
+
/* SYS0CRG clocks */
#define JHB100_SYS0CLK_BMCPCIERP_600 17
#define JHB100_SYS0CLK_BMCPCIERP_100 18
--
2.25.1
^ permalink raw reply related
* [PATCH v1 04/13] dt-bindings: clock: Add peripheral-0 domain PLL clock
From: Changhuang Liang @ 2026-04-03 5:49 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>
Add peripheral-0 domain PLL clock for StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../devicetree/bindings/clock/starfive,jhb100-pll.yaml | 1 +
include/dt-bindings/clock/starfive,jhb100-crg.h | 3 +++
2 files changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
index f7ab90c05281..920fde5e1b0a 100644
--- a/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
+++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
@@ -18,6 +18,7 @@ properties:
compatible:
enum:
- starfive,jhb100-sys0-pll
+ - starfive,jhb100-per0-pll
clocks:
maxItems: 1
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index 719a6eb9b1a4..55e91ede977e 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -14,6 +14,9 @@
#define JHB100_SYS0PLL_PLL4_OUT 2
#define JHB100_SYS0PLL_PLL5_OUT 3
+/* PER0PLL clocks */
+#define JHB100_PER0PLL_PLL6_OUT 0
+
/* SYS0CRG clocks */
#define JHB100_SYS0CLK_BMCPCIERP_600 17
#define JHB100_SYS0CLK_BMCPCIERP_100 18
--
2.25.1
^ permalink raw reply related
* [PATCH v1 05/13] clk: starfive: Add peripheral-0 domain PLL clock driver
From: Changhuang Liang @ 2026-04-03 5:49 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>
Add peripheral-0 domain PLL clock driver support for StarFive JHB100
SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clk/starfive/clk-starfive-jhb100-pll.c | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-pll.c b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
index 1751a734ee83..5fddb07d0d13 100644
--- a/drivers/clk/starfive/clk-starfive-jhb100-pll.c
+++ b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
@@ -27,6 +27,9 @@
#define JHB100_PLL4_OFFSET 0x18
#define JHB100_PLL5_OFFSET 0x24
+/* Peripheral-0 domain PLL */
+#define JHB100_PLL6_OFFSET 0x00
+
#define JHB100_PLL_CFG0_OFFSET 0x0
#define JHB100_PLL_CFG1_OFFSET 0x4
#define JHB100_PLL_CFG2_OFFSET 0x8
@@ -479,10 +482,35 @@ static const struct jhb100_pll_match_data jhb100_sys0_pll = {
.num_pll = ARRAY_SIZE(jhb100_sys0_pll_info),
};
+static const struct jhb100_pll_preset jhb100_pll6_presets[] = {
+ {
+ .freq = 2400000000,
+ .fbdiv = 192,
+ .frac = 0,
+ .refdiv = 1,
+ .postdiv = 0,
+ .foutpostdiv_en = 1,
+ .foutvcop_en = 0,
+ },
+};
+
+static const struct jhb100_pll_info jhb100_per0_pll_info[] = {
+ JHB100_PLL(JHB100_PER0PLL_PLL6_OUT, "pll6_out", jhb100_pll6_presets,
+ ARRAY_SIZE(jhb100_pll6_presets), JHB100_PLL6_OFFSET, false),
+};
+
+static const struct jhb100_pll_match_data jhb100_per0_pll = {
+ .pll_info = jhb100_per0_pll_info,
+ .num_pll = ARRAY_SIZE(jhb100_per0_pll_info),
+};
+
static const struct of_device_id jhb100_pll_match[] = {
{
.compatible = "starfive,jhb100-sys0-pll",
.data = (void *)&jhb100_sys0_pll,
+ }, {
+ .compatible = "starfive,jhb100-per0-pll",
+ .data = (void *)&jhb100_per0_pll,
}, {
/* sentinel */
}
--
2.25.1
^ permalink raw reply related
* [PATCH v1 03/13] clk: starfive: Add system-0 domain PLL clock driver
From: Changhuang Liang @ 2026-04-03 5:49 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>
Add system-0 domain PLL clock driver for StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jhb100-pll.c | 498 ++++++++++++++++++
3 files changed, 507 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-pll.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index c612f1ede7d7..cc712da68bd0 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -105,6 +105,14 @@ config CLK_STARFIVE_JHB100_PER3
Say yes here to support the peripheral-3 clock controller
on the StarFive JHB100 SoC.
+config CLK_STARFIVE_JHB100_PLL
+ bool "StarFive JHB100 PLL clock support"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the PLL clock controller on the
+ StarFive JHB100 SoC.
+
config CLK_STARFIVE_JHB100_SYS0
bool "StarFive JHB100 system-0 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index f00690f0cdad..547a8c170728 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CLK_STARFIVE_JHB100_PER0) += clk-starfive-jhb100-per0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER1) += clk-starfive-jhb100-per1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER2) += clk-starfive-jhb100-per2.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_PER3) += clk-starfive-jhb100-per3.o
+obj-$(CONFIG_CLK_STARFIVE_JHB100_PLL) += clk-starfive-jhb100-pll.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o
obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-pll.c b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
new file mode 100644
index 000000000000..1751a734ee83
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
@@ -0,0 +1,498 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JHB100 PLL Clock Generator Driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/starfive,jhb100-crg.h>
+
+/* this driver expects a 25MHz input frequency from the oscillator */
+#define JHB100_PLL_OSC_RATE 25000000UL
+
+/* System-0 domain PLL */
+#define JHB100_PLL2_OFFSET 0x00
+#define JHB100_PLL3_OFFSET 0x0c
+#define JHB100_PLL4_OFFSET 0x18
+#define JHB100_PLL5_OFFSET 0x24
+
+#define JHB100_PLL_CFG0_OFFSET 0x0
+#define JHB100_PLL_CFG1_OFFSET 0x4
+#define JHB100_PLL_CFG2_OFFSET 0x8
+
+#define JHB100_PLLX_CFG0(offset) ((offset) + JHB100_PLL_CFG0_OFFSET)
+/* fbdiv value should be 16 to 4095 */
+#define JHB100_PLL_FBDIV GENMASK(13, 2)
+#define JHB100_PLL_FBDIV_SHIFT 2
+#define JHB100_PLL_FOUTPOSTDIV_EN BIT(14)
+#define JHB100_PLL_FOUTPOSTDIV_EN_SHIFT 14
+#define JHB100_PLL_FOUTVCOP_EN BIT(16)
+#define JHB100_PLL_FOUTVCOP_EN_SHIFT 16
+
+#define JHB100_PLLX_CFG1(offset) ((offset) + JHB100_PLL_CFG1_OFFSET)
+/* frac value should be decimals multiplied by 2^24 */
+#define JHB100_PLL_FRAC GENMASK(23, 0)
+#define JHB100_PLL_FRAC_SHIFT 0
+#define JHB100_PLL_LOCK BIT(24)
+#define JHB100_PLL_LOCK_SHIFT 24
+
+#define JHB100_PLLX_CFG2(offset) ((offset) + JHB100_PLL_CFG2_OFFSET)
+#define JHB100_PLL_PD BIT(13)
+#define JHB100_PLL_PD_SHIFT 13
+#define JHB100_PLL_POSTDIV GENMASK(15, 14)
+#define JHB100_PLL_POSTDIV_SHIFT 14
+#define JHB100_PLL_REFDIV GENMASK(23, 18)
+#define JHB100_PLL_REFDIV_SHIFT 18
+
+#define JHB100_PLL_TIMEOUT_US 1000
+#define JHB100_PLL_INTERVAL_US 100
+
+struct jhb100_pll_preset {
+ unsigned long freq;
+ u32 frac; /* frac value should be decimals multiplied by 2^24 */
+ unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */
+ unsigned refdiv : 6;
+ unsigned postdiv : 2;
+ unsigned foutpostdiv_en : 1;
+ unsigned foutvcop_en : 1;
+};
+
+struct jhb100_pll_info {
+ char *name;
+ const struct jhb100_pll_preset *presets;
+ unsigned int npresets;
+ unsigned long flag;
+ u8 offset;
+ bool continuous;
+};
+
+#define _JHB100_PLL(_idx, _name, _presets, _npresets, _offset, _flag, _cont) \
+ [_idx] = { \
+ .name = _name, \
+ .offset = _offset, \
+ .presets = _presets, \
+ .npresets = _npresets, \
+ .flag = _flag, \
+ .continuous = _cont, \
+ }
+
+#define JHB100_PLL(idx, name, presets, npresets, offset, cont) \
+ _JHB100_PLL(idx, name, presets, npresets, offset, 0, cont)
+
+struct jhb100_pll_match_data {
+ const struct jhb100_pll_info *pll_info;
+ int num_pll;
+};
+
+struct jhb100_pll_data {
+ struct clk_hw hw;
+ unsigned int idx;
+};
+
+struct jhb100_pll_priv {
+ struct device *dev;
+ struct regmap *regmap;
+ const struct jhb100_pll_match_data *match_data;
+ struct jhb100_pll_data pll[];
+};
+
+struct jhb100_pll_regvals {
+ u32 fbdiv;
+ u32 frac;
+ u32 postdiv;
+ u32 refdiv;
+ bool foutpostdiv_en;
+ bool foutvcop_en;
+};
+
+static struct jhb100_pll_data *jhb100_pll_data_from(struct clk_hw *hw)
+{
+ return container_of(hw, struct jhb100_pll_data, hw);
+}
+
+static struct jhb100_pll_priv *jhb100_pll_priv_from(struct jhb100_pll_data *pll)
+{
+ return container_of(pll, struct jhb100_pll_priv, pll[pll->idx]);
+}
+
+static int jhb100_pll_enable(struct clk_hw *hw)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ const struct jhb100_pll_info *info = &priv->match_data->pll_info[pll->idx];
+
+ regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset),
+ JHB100_PLL_PD, 0);
+
+ return 0;
+}
+
+static void jhb100_pll_disable(struct clk_hw *hw)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ const struct jhb100_pll_info *info = &priv->match_data->pll_info[pll->idx];
+
+ regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset),
+ JHB100_PLL_PD, BIT(JHB100_PLL_PD_SHIFT));
+}
+
+static int jhb100_pll_is_enabled(struct clk_hw *hw)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ const struct jhb100_pll_info *info = &priv->match_data->pll_info[pll->idx];
+ u32 val;
+
+ regmap_read(priv->regmap, JHB100_PLLX_CFG2(info->offset), &val);
+
+ return !(val & JHB100_PLL_PD);
+}
+
+static void jhb100_pll_regvals_get(struct regmap *regmap,
+ const struct jhb100_pll_info *info,
+ struct jhb100_pll_regvals *ret)
+{
+ u32 val;
+
+ regmap_read(regmap, JHB100_PLLX_CFG0(info->offset), &val);
+ ret->fbdiv = (val & JHB100_PLL_FBDIV) >> JHB100_PLL_FBDIV_SHIFT;
+ ret->foutpostdiv_en = !!((val & JHB100_PLL_FOUTPOSTDIV_EN) >>
+ JHB100_PLL_FOUTPOSTDIV_EN_SHIFT);
+ ret->foutvcop_en = !!((val & JHB100_PLL_FOUTVCOP_EN) >>
+ JHB100_PLL_FOUTVCOP_EN_SHIFT);
+
+ regmap_read(regmap, JHB100_PLLX_CFG1(info->offset), &val);
+ ret->frac = (val & JHB100_PLL_FRAC) >> JHB100_PLL_FRAC_SHIFT;
+
+ regmap_read(regmap, JHB100_PLLX_CFG2(info->offset), &val);
+ ret->postdiv = (val & JHB100_PLL_POSTDIV) >> JHB100_PLL_POSTDIV_SHIFT;
+ ret->refdiv = (val & JHB100_PLL_REFDIV) >> JHB100_PLL_REFDIV_SHIFT;
+}
+
+static unsigned long jhb100_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ struct jhb100_pll_regvals val;
+ unsigned long rate;
+ u32 power = 0;
+
+ jhb100_pll_regvals_get(priv->regmap, &priv->match_data->pll_info[pll->idx], &val);
+
+ /*
+ *
+ * if (foutvcop_en)
+ * rate = parent * (fbdiv + frac / 2^24) / refdiv
+ *
+ * if (foutpostdiv_en)
+ * rate = parent * (fbdiv + frac / 2^24) / refdiv / 2^(postdiv + 1)
+ *
+ * parent * (fbdiv + frac / 2^24) = parent * fbdiv + parent * frac / 2^24
+ */
+
+ if (!!val.foutvcop_en == !!val.foutpostdiv_en)
+ return 0;
+
+ rate = (parent_rate * val.frac) >> 24;
+
+ if (val.foutpostdiv_en)
+ power = val.postdiv + 1;
+
+ rate += parent_rate * val.fbdiv;
+ rate /= val.refdiv << power;
+
+ return rate;
+}
+
+static int jhb100_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ const struct jhb100_pll_info *info = &priv->match_data->pll_info[pll->idx];
+ const struct jhb100_pll_preset *selected = &info->presets[0];
+ unsigned int idx;
+
+ /* if the parent rate doesn't match our expectations the presets won't work */
+ if (req->best_parent_rate != JHB100_PLL_OSC_RATE) {
+ req->rate = jhb100_pll_recalc_rate(hw, req->best_parent_rate);
+ return 0;
+ }
+
+ /* continuous means support any rate */
+ if (info->continuous)
+ return 0;
+
+ /* find highest rate lower or equal to the requested rate */
+ for (idx = 1; idx < info->npresets; idx++) {
+ const struct jhb100_pll_preset *val = &info->presets[idx];
+
+ if (req->rate < val->freq)
+ break;
+
+ selected = val;
+ }
+
+ req->rate = selected->freq;
+
+ return 0;
+}
+
+static int jhb100_pll_set_preset(struct clk_hw *hw, struct jhb100_pll_preset *val)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ const struct jhb100_pll_info *info = &priv->match_data->pll_info[pll->idx];
+ unsigned int value;
+
+ regmap_update_bits(priv->regmap, JHB100_PLLX_CFG0(info->offset), JHB100_PLL_FBDIV,
+ (u32)val->fbdiv << JHB100_PLL_FBDIV_SHIFT);
+ regmap_update_bits(priv->regmap, JHB100_PLLX_CFG0(info->offset), JHB100_PLL_FOUTPOSTDIV_EN,
+ (u32)val->foutpostdiv_en << JHB100_PLL_FOUTPOSTDIV_EN_SHIFT);
+ regmap_update_bits(priv->regmap, JHB100_PLLX_CFG0(info->offset), JHB100_PLL_FOUTVCOP_EN,
+ (u32)val->foutvcop_en << JHB100_PLL_FOUTVCOP_EN_SHIFT);
+ regmap_update_bits(priv->regmap, JHB100_PLLX_CFG1(info->offset), JHB100_PLL_FRAC,
+ val->frac << JHB100_PLL_FRAC_SHIFT);
+ regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset), JHB100_PLL_REFDIV,
+ (u32)val->refdiv << JHB100_PLL_REFDIV_SHIFT);
+ regmap_update_bits(priv->regmap, JHB100_PLLX_CFG2(info->offset), JHB100_PLL_POSTDIV,
+ (u32)val->postdiv << JHB100_PLL_POSTDIV_SHIFT);
+
+ /* waiting for PLL to lock */
+ return regmap_read_poll_timeout_atomic(priv->regmap, JHB100_PLLX_CFG1(info->offset),
+ value, value & JHB100_PLL_LOCK,
+ JHB100_PLL_INTERVAL_US,
+ JHB100_PLL_TIMEOUT_US);
+}
+
+static int jhb100_pll_rate_to_preset(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct jhb100_pll_preset val = {
+ .refdiv = 1,
+ .postdiv = 3,
+ .foutpostdiv_en = 1,
+ .foutvcop_en = 0,
+ };
+ unsigned int power = 0;
+ unsigned long fbdiv_24, t;
+
+ if (val.foutpostdiv_en)
+ power = val.postdiv + 1;
+
+ t = val.refdiv << power;
+ t *= rate;
+
+ val.fbdiv = t / parent_rate;
+
+ fbdiv_24 = (t << 24) / parent_rate;
+ val.frac = fbdiv_24 - (val.fbdiv << 24);
+
+ return jhb100_pll_set_preset(hw, &val);
+}
+
+static int jhb100_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ const struct jhb100_pll_info *info = &priv->match_data->pll_info[pll->idx];
+ const struct jhb100_pll_preset *val;
+ unsigned int idx;
+
+ /* if the parent rate doesn't match our expectations the presets won't work */
+ if (parent_rate != JHB100_PLL_OSC_RATE)
+ return -EINVAL;
+
+ if (info->continuous)
+ return jhb100_pll_rate_to_preset(hw, rate, parent_rate);
+
+ for (idx = 0, val = &info->presets[0]; idx < info->npresets; idx++, val++) {
+ if (val->freq == rate)
+ return jhb100_pll_set_preset(hw, (struct jhb100_pll_preset *)val);
+ }
+ return -EINVAL;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int jhb100_pll_registers_read(struct seq_file *s, void *unused)
+{
+ struct jhb100_pll_data *pll = s->private;
+ struct jhb100_pll_priv *priv = jhb100_pll_priv_from(pll);
+ struct jhb100_pll_regvals val;
+
+ jhb100_pll_regvals_get(priv->regmap, &priv->match_data->pll_info[pll->idx], &val);
+
+ seq_printf(s, "fbdiv=%u\n"
+ "frac=%u\n"
+ "refdiv=%u\n"
+ "postdiv=%u\n"
+ "foutpostdiv_en=%u\n"
+ "foutvcop_en=%u\n",
+ val.fbdiv, val.frac, val.refdiv, val.postdiv,
+ val.foutpostdiv_en, val.foutvcop_en);
+
+ return 0;
+}
+
+static int jhb100_pll_registers_open(struct inode *inode, struct file *f)
+{
+ return single_open(f, jhb100_pll_registers_read, inode->i_private);
+}
+
+static const struct file_operations jhb100_pll_registers_ops = {
+ .owner = THIS_MODULE,
+ .open = jhb100_pll_registers_open,
+ .release = single_release,
+ .read = seq_read,
+ .llseek = seq_lseek
+};
+
+static void jhb100_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
+{
+ struct jhb100_pll_data *pll = jhb100_pll_data_from(hw);
+
+ debugfs_create_file("registers", 0400, dentry, pll,
+ &jhb100_pll_registers_ops);
+}
+#else
+#define jhb100_pll_debug_init NULL
+#endif
+
+static const struct clk_ops jhb100_pll_ops = {
+ .enable = jhb100_pll_enable,
+ .disable = jhb100_pll_disable,
+ .is_enabled = jhb100_pll_is_enabled,
+ .recalc_rate = jhb100_pll_recalc_rate,
+ .determine_rate = jhb100_pll_determine_rate,
+ .set_rate = jhb100_pll_set_rate,
+ .debug_init = jhb100_pll_debug_init,
+};
+
+static struct clk_hw *jhb100_pll_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct jhb100_pll_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < priv->match_data->num_pll)
+ return &priv->pll[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int __init jhb100_pll_probe(struct platform_device *pdev)
+{
+ const struct jhb100_pll_match_data *match_data;
+ struct jhb100_pll_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ match_data = of_device_get_match_data(&pdev->dev);
+ if (!match_data)
+ return -EINVAL;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, pll, match_data->num_pll),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->match_data = match_data;
+ priv->dev = &pdev->dev;
+ priv->regmap = syscon_node_to_regmap(priv->dev->of_node->parent);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ for (idx = 0; idx < match_data->num_pll; idx++) {
+ struct clk_parent_data parents = {
+ .index = 0,
+ };
+ struct clk_init_data init = {
+ .name = match_data->pll_info[idx].name,
+ .ops = &jhb100_pll_ops,
+ .parent_data = &parents,
+ .num_parents = 1,
+ .flags = match_data->pll_info[idx].flag,
+ };
+ struct jhb100_pll_data *pll = &priv->pll[idx];
+
+ pll->hw.init = &init;
+ pll->idx = idx;
+
+ ret = devm_clk_hw_register(&pdev->dev, &pll->hw);
+ if (ret)
+ return ret;
+ }
+
+ return devm_of_clk_add_hw_provider(&pdev->dev, jhb100_pll_get, priv);
+}
+
+static const struct jhb100_pll_preset jhb100_pll2_presets[] = {
+ {
+ .freq = 903168000,
+ .fbdiv = 72,
+ .frac = 4252017,
+ .refdiv = 1,
+ .postdiv = 0,
+ .foutpostdiv_en = 1,
+ .foutvcop_en = 0,
+ },
+};
+
+static const struct jhb100_pll_preset jhb100_pll3_presets[] = {
+ {
+ .freq = 800000000,
+ .fbdiv = 64,
+ .frac = 0,
+ .refdiv = 1,
+ .postdiv = 0,
+ .foutpostdiv_en = 1,
+ .foutvcop_en = 0,
+ },
+};
+
+static const struct jhb100_pll_info jhb100_sys0_pll_info[] = {
+ JHB100_PLL(JHB100_SYS0PLL_PLL2_OUT, "pll2_out", jhb100_pll2_presets,
+ ARRAY_SIZE(jhb100_pll2_presets), JHB100_PLL2_OFFSET, false),
+ _JHB100_PLL(JHB100_SYS0PLL_PLL3_OUT, "pll3_out", jhb100_pll3_presets,
+ ARRAY_SIZE(jhb100_pll3_presets), JHB100_PLL3_OFFSET,
+ CLK_IS_CRITICAL, false),
+ _JHB100_PLL(JHB100_SYS0PLL_PLL4_OUT, "pll4_out", NULL, 0,
+ JHB100_PLL4_OFFSET, CLK_IGNORE_UNUSED, true),
+ _JHB100_PLL(JHB100_SYS0PLL_PLL5_OUT, "pll5_out", NULL, 0,
+ JHB100_PLL5_OFFSET, CLK_IGNORE_UNUSED, true),
+};
+
+static const struct jhb100_pll_match_data jhb100_sys0_pll = {
+ .pll_info = jhb100_sys0_pll_info,
+ .num_pll = ARRAY_SIZE(jhb100_sys0_pll_info),
+};
+
+static const struct of_device_id jhb100_pll_match[] = {
+ {
+ .compatible = "starfive,jhb100-sys0-pll",
+ .data = (void *)&jhb100_sys0_pll,
+ }, {
+ /* sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_pll_match);
+
+static struct platform_driver jhb100_pll_driver = {
+ .driver = {
+ .name = "clk-starfive-jhb100-pll",
+ .of_match_table = jhb100_pll_match,
+ },
+};
+builtin_platform_driver_probe(jhb100_pll_driver, jhb100_pll_probe);
--
2.25.1
^ permalink raw reply related
* [PATCH v1 06/13] dt-bindings: clock: Add peripheral-1 domain PLL clock
From: Changhuang Liang @ 2026-04-03 5:49 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>
Add peripheral-1 domain PLL clock for StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../devicetree/bindings/clock/starfive,jhb100-pll.yaml | 1 +
include/dt-bindings/clock/starfive,jhb100-crg.h | 3 +++
2 files changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
index 920fde5e1b0a..1f619adb30a1 100644
--- a/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
+++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-pll.yaml
@@ -19,6 +19,7 @@ properties:
enum:
- starfive,jhb100-sys0-pll
- starfive,jhb100-per0-pll
+ - starfive,jhb100-per1-pll
clocks:
maxItems: 1
diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h
index 55e91ede977e..49fb1694bc79 100644
--- a/include/dt-bindings/clock/starfive,jhb100-crg.h
+++ b/include/dt-bindings/clock/starfive,jhb100-crg.h
@@ -17,6 +17,9 @@
/* PER0PLL clocks */
#define JHB100_PER0PLL_PLL6_OUT 0
+/* PER1PLL clocks */
+#define JHB100_PER1PLL_PLL7_OUT 0
+
/* SYS0CRG clocks */
#define JHB100_SYS0CLK_BMCPCIERP_600 17
#define JHB100_SYS0CLK_BMCPCIERP_100 18
--
2.25.1
^ permalink raw reply related
* [PATCH v1 07/13] clk: starfive: Add Peripheral-1 domain PLL clock driver
From: Changhuang Liang @ 2026-04-03 5:49 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>
Add Peripheral-1 domain PLL clock driver support for StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../clk/starfive/clk-starfive-jhb100-pll.c | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/clk/starfive/clk-starfive-jhb100-pll.c b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
index 5fddb07d0d13..522d920a3353 100644
--- a/drivers/clk/starfive/clk-starfive-jhb100-pll.c
+++ b/drivers/clk/starfive/clk-starfive-jhb100-pll.c
@@ -30,6 +30,9 @@
/* Peripheral-0 domain PLL */
#define JHB100_PLL6_OFFSET 0x00
+/* Peripheral-1 domain PLL */
+#define JHB100_PLL7_OFFSET 0x40
+
#define JHB100_PLL_CFG0_OFFSET 0x0
#define JHB100_PLL_CFG1_OFFSET 0x4
#define JHB100_PLL_CFG2_OFFSET 0x8
@@ -504,6 +507,28 @@ static const struct jhb100_pll_match_data jhb100_per0_pll = {
.num_pll = ARRAY_SIZE(jhb100_per0_pll_info),
};
+static const struct jhb100_pll_preset jhb100_pll7_presets[] = {
+ {
+ .freq = 1950000000,
+ .fbdiv = 156,
+ .frac = 0,
+ .refdiv = 1,
+ .postdiv = 0,
+ .foutpostdiv_en = 1,
+ .foutvcop_en = 0,
+ },
+};
+
+static const struct jhb100_pll_info jhb100_per1_pll_info[] = {
+ JHB100_PLL(JHB100_PER1PLL_PLL7_OUT, "pll7_out", jhb100_pll7_presets,
+ ARRAY_SIZE(jhb100_pll7_presets), JHB100_PLL7_OFFSET, false),
+};
+
+static const struct jhb100_pll_match_data jhb100_per1_pll = {
+ .pll_info = jhb100_per1_pll_info,
+ .num_pll = ARRAY_SIZE(jhb100_per1_pll_info),
+};
+
static const struct of_device_id jhb100_pll_match[] = {
{
.compatible = "starfive,jhb100-sys0-pll",
@@ -511,6 +536,9 @@ static const struct of_device_id jhb100_pll_match[] = {
}, {
.compatible = "starfive,jhb100-per0-pll",
.data = (void *)&jhb100_per0_pll,
+ }, {
+ .compatible = "starfive,jhb100-per1-pll",
+ .data = (void *)&jhb100_per1_pll,
}, {
/* sentinel */
}
--
2.25.1
^ permalink raw reply related
* [PATCH v1 08/13] dt-bindings: reset: Add StarFive JHB100 reset generator
From: Changhuang Liang @ 2026-04-03 5:49 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>
Add bindings for thr reset generator which locates in pcierp syscon.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../reset/starfive,jhb100-reset-pcierp.yaml | 38 +++++++++++++++++++
.../dt-bindings/reset/starfive,jhb100-crg.h | 3 ++
2 files changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/starfive,jhb100-reset-pcierp.yaml
diff --git a/Documentation/devicetree/bindings/reset/starfive,jhb100-reset-pcierp.yaml b/Documentation/devicetree/bindings/reset/starfive,jhb100-reset-pcierp.yaml
new file mode 100644
index 000000000000..fc6b0d1e64f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/starfive,jhb100-reset-pcierp.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/starfive,jhb100-reset-pcierp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 SoC PCIe root port Reset Controller
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+ compatible:
+ enum:
+ - starfive,jhb100-reset-pcierp
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@14c {
+ compatible = "starfive,jhb100-reset-pcierp";
+ reg = <0x14c 0x4>;
+ #reset-cells = <1>;
+ };
+
+...
diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h
index 4b15e348e92f..49326b7f486f 100644
--- a/include/dt-bindings/reset/starfive,jhb100-crg.h
+++ b/include/dt-bindings/reset/starfive,jhb100-crg.h
@@ -190,4 +190,7 @@
#define JHB100_PER3RST_MAIN_RSTN_PERIPH3_SENSORS 5
#define JHB100_PER3RST_IOMUX_PRESETN 6
+/* PCIERP SYSCON resets */
+#define JHB100_PCIERP_SYSCONRST_PE2RST_OUT 0
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */
--
2.25.1
^ permalink raw reply related
* [PATCH v1 09/13] reset: starfive: Introduce assert_polarity
From: Changhuang Liang @ 2026-04-03 5:49 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>
The JHB100 SoC supports inverted operations for reset
assertion/deassertion, introducing the an assert_polarity field to
distinguish between different operation logics.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../reset/starfive/reset-starfive-common.c | 51 +++++++++++++++++--
.../reset/starfive/reset-starfive-common.h | 5 ++
2 files changed, 53 insertions(+), 3 deletions(-)
diff --git a/drivers/reset/starfive/reset-starfive-common.c b/drivers/reset/starfive/reset-starfive-common.c
index 772bdf6763d1..61d69cef4bc9 100644
--- a/drivers/reset/starfive/reset-starfive-common.c
+++ b/drivers/reset/starfive/reset-starfive-common.c
@@ -20,6 +20,12 @@ struct starfive_reset {
spinlock_t lock;
void __iomem *assert;
void __iomem *status;
+
+ /* If assert_polarity is false, setting the bit to 1 asserts
+ * the signal while clearing it to 0 deasserts it, and vice
+ * versa.
+ */
+ bool assert_polarity;
const u32 *asserted;
};
@@ -42,7 +48,7 @@ static int starfive_reset_update(struct reset_controller_dev *rcdev,
unsigned long flags;
int ret;
- if (!assert)
+ if (data->assert_polarity == assert)
done ^= mask;
spin_lock_irqsave(&data->lock, flags);
@@ -64,13 +70,25 @@ static int starfive_reset_update(struct reset_controller_dev *rcdev,
static int starfive_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
- return starfive_reset_update(rcdev, id, true);
+ struct starfive_reset *data = starfive_reset_from(rcdev);
+ bool assert = false;
+
+ if (!data->assert_polarity)
+ assert = true;
+
+ return starfive_reset_update(rcdev, id, assert);
}
static int starfive_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
- return starfive_reset_update(rcdev, id, false);
+ struct starfive_reset *data = starfive_reset_from(rcdev);
+ bool deassert = false;
+
+ if (data->assert_polarity)
+ deassert = true;
+
+ return starfive_reset_update(rcdev, id, deassert);
}
static int starfive_reset_reset(struct reset_controller_dev *rcdev,
@@ -132,3 +150,30 @@ int reset_starfive_register(struct device *dev, struct device_node *of_node,
return devm_reset_controller_register(dev, &data->rcdev);
}
EXPORT_SYMBOL_GPL(reset_starfive_register);
+
+int reset_starfive_register_polarity(struct device *dev, struct device_node *of_node,
+ void __iomem *assert, void __iomem *status,
+ const u32 *asserted, unsigned int nr_resets,
+ struct module *owner)
+{
+ struct starfive_reset *data;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->rcdev.ops = &starfive_reset_ops;
+ data->rcdev.owner = owner;
+ data->rcdev.nr_resets = nr_resets;
+ data->rcdev.dev = dev;
+ data->rcdev.of_node = of_node;
+
+ spin_lock_init(&data->lock);
+ data->assert = assert;
+ data->status = status;
+ data->assert_polarity = true;
+ data->asserted = asserted;
+
+ return devm_reset_controller_register(dev, &data->rcdev);
+}
+EXPORT_SYMBOL_GPL(reset_starfive_register_polarity);
diff --git a/drivers/reset/starfive/reset-starfive-common.h b/drivers/reset/starfive/reset-starfive-common.h
index 83461b22ee55..bad56613deb9 100644
--- a/drivers/reset/starfive/reset-starfive-common.h
+++ b/drivers/reset/starfive/reset-starfive-common.h
@@ -11,4 +11,9 @@ int reset_starfive_register(struct device *dev, struct device_node *of_node,
const u32 *asserted, unsigned int nr_resets,
struct module *owner);
+int reset_starfive_register_polarity(struct device *dev, struct device_node *of_node,
+ void __iomem *assert, void __iomem *status,
+ const u32 *asserted, unsigned int nr_resets,
+ struct module *owner);
+
#endif /* __RESET_STARFIVE_COMMON_H */
--
2.25.1
^ permalink raw reply related
* [PATCH v1 10/13] reset: starfive: Add syscon reset driver support
From: Changhuang Liang @ 2026-04-03 5:49 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>
Add syscon reset driver for JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/reset/starfive/Kconfig | 9 ++++
drivers/reset/starfive/Makefile | 1 +
.../starfive/reset-starfive-jhb100-syscon.c | 48 +++++++++++++++++++
3 files changed, 58 insertions(+)
create mode 100644 drivers/reset/starfive/reset-starfive-jhb100-syscon.c
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
index 6f9a0f24f9b9..cd5ae9cad9d9 100644
--- a/drivers/reset/starfive/Kconfig
+++ b/drivers/reset/starfive/Kconfig
@@ -28,3 +28,12 @@ config RESET_STARFIVE_JHB100
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JHB100 SoC.
+
+config RESET_STARFIVE_JHB100_SYSCON
+ bool "StarFive JHB100 SYSCON Reset Driver"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select RESET_STARFIVE_COMMON
+ default ARCH_STARFIVE
+ help
+ This enables the SYSCON reset controller driver for the StarFive
+ JHB100 SoC.
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
index 217002302a9f..d5033d723167 100644
--- a/drivers/reset/starfive/Makefile
+++ b/drivers/reset/starfive/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_RESET_STARFIVE_COMMON) += reset-starfive-common.o
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
obj-$(CONFIG_RESET_STARFIVE_JHB100) += reset-starfive-jhb100.o
+obj-$(CONFIG_RESET_STARFIVE_JHB100_SYSCON) += reset-starfive-jhb100-syscon.o
diff --git a/drivers/reset/starfive/reset-starfive-jhb100-syscon.c b/drivers/reset/starfive/reset-starfive-jhb100-syscon.c
new file mode 100644
index 000000000000..8de6419615c2
--- /dev/null
+++ b/drivers/reset/starfive/reset-starfive-jhb100-syscon.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * SYSCON Reset driver for the StarFive JHB110 SoC
+ *
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ */
+
+#include <dt-bindings/reset/starfive,jhb100-crg.h>
+#include <linux/platform_device.h>
+#include <soc/starfive/reset-starfive-common.h>
+
+#include "reset-starfive-common.h"
+
+#define JHB100_PCIERP_SYSCON_RESET_ASSERT0 0x00
+
+static int jhb100_syscon_reset_probe(struct platform_device *pdev)
+{
+ void __iomem *base = devm_platform_ioremap_resource(pdev, 0);
+
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ return reset_starfive_register_polarity(&pdev->dev, pdev->dev.of_node,
+ base + JHB100_PCIERP_SYSCON_RESET_ASSERT0,
+ base + JHB100_PCIERP_SYSCON_RESET_ASSERT0,
+ NULL,
+ JHB100_PCIERP_SYSCONRST_PE2RST_OUT + 1,
+ NULL);
+}
+
+static const struct of_device_id jhb100_syscon_reset_dt_ids[] = {
+ { .compatible = "starfive,jhb100-reset-pcierp" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jhb100_syscon_reset_dt_ids);
+
+static struct platform_driver jhb100_syscon_reset_driver = {
+ .probe = jhb100_syscon_reset_probe,
+ .driver = {
+ .name = "jhb100-syscon-reset",
+ .of_match_table = jhb100_syscon_reset_dt_ids,
+ },
+};
+module_platform_driver(jhb100_syscon_reset_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 SYSCON reset driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related
* [PATCH v1 11/13] dt-bindings: hwinfo: Add starfive,jhb100-socinfo
From: Changhuang Liang @ 2026-04-03 5:49 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>
Add starfive,jhb100-socinfo for StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../hwinfo/starfive,jhb100-socinfo.yaml | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwinfo/starfive,jhb100-socinfo.yaml
diff --git a/Documentation/devicetree/bindings/hwinfo/starfive,jhb100-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/starfive,jhb100-socinfo.yaml
new file mode 100644
index 000000000000..cc6b7d5a4c91
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwinfo/starfive,jhb100-socinfo.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwinfo/starfive,jhb100-socinfo.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 SoC platform chipid module
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+description:
+ StarFive JHB100 SoC platform chipid module is represented by JHB100_PRODUCT_ID
+ register which contains information about revision. This register is located
+ under the syscon.
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-socinfo
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ chipid@38 {
+ compatible = "starfive,jhb100-socinfo";
+ reg = <0x38 0x4>;
+ };
--
2.25.1
^ permalink raw reply related
* [PATCH v1 12/13] soc: starfive: Add socinfo driver for JHB100 SoC
From: Changhuang Liang @ 2026-04-03 5:49 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>
Add socinfo driver for JHB100 SoC. Currently available for distinguishing
between the two reversions, A0 and A1.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 6 ++
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/starfive/Kconfig | 6 ++
drivers/soc/starfive/Makefile | 2 +
drivers/soc/starfive/socinfo/Kconfig | 11 +++
drivers/soc/starfive/socinfo/Makefile | 2 +
drivers/soc/starfive/socinfo/jhb100-socinfo.c | 90 +++++++++++++++++++
8 files changed, 119 insertions(+)
create mode 100644 drivers/soc/starfive/Kconfig
create mode 100644 drivers/soc/starfive/Makefile
create mode 100644 drivers/soc/starfive/socinfo/Kconfig
create mode 100644 drivers/soc/starfive/socinfo/Makefile
create mode 100644 drivers/soc/starfive/socinfo/jhb100-socinfo.c
diff --git a/MAINTAINERS b/MAINTAINERS
index eb5f6a383146..32bd94a0b94c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25325,6 +25325,12 @@ S: Maintained
F: drivers/reset/starfive/reset-starfive-jhb1*
F: include/dt-bindings/reset/starfive,jhb1*.h
+STARFIVE JHB100 SOCINFO DRIVER
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+S: Maintained
+F: Documentation/devicetree/bindings/hwinfo/starfive,jhb100-socinfo.yaml
+F: drivers/soc/starfive/socinfo/jhb100-socinfo.c
+
STARFIVE JHB100 SYSCON
M: Changhuang Liang <changhuang.liang@starfivetech.com>
S: Maintained
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index a2d65adffb80..b3b01fc38139 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -24,6 +24,7 @@ source "drivers/soc/renesas/Kconfig"
source "drivers/soc/rockchip/Kconfig"
source "drivers/soc/samsung/Kconfig"
source "drivers/soc/sophgo/Kconfig"
+source "drivers/soc/starfive/Kconfig"
source "drivers/soc/sunxi/Kconfig"
source "drivers/soc/tegra/Kconfig"
source "drivers/soc/ti/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index c9e689080ceb..009f85ff891a 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -30,6 +30,7 @@ obj-y += renesas/
obj-y += rockchip/
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
obj-y += sophgo/
+obj-y += starfive/
obj-y += sunxi/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += ti/
diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig
new file mode 100644
index 000000000000..04b020083d3e
--- /dev/null
+++ b/drivers/soc/starfive/Kconfig
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+menu "StarFive SoC (System On Chip) specific Drivers"
+
+source "drivers/soc/starfive/socinfo/Kconfig"
+
+endmenu
diff --git a/drivers/soc/starfive/Makefile b/drivers/soc/starfive/Makefile
new file mode 100644
index 000000000000..ca1e609b8104
--- /dev/null
+++ b/drivers/soc/starfive/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-y += socinfo/
diff --git a/drivers/soc/starfive/socinfo/Kconfig b/drivers/soc/starfive/socinfo/Kconfig
new file mode 100644
index 000000000000..0a20382da5d3
--- /dev/null
+++ b/drivers/soc/starfive/socinfo/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config STARFIVE_JHB100_SOCINFO
+ tristate "StarFive JHB100 SoC Information"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select SOC_BUS
+ default ARCH_STARFIVE
+ help
+ Include support for the SoC bus socinfo for the StarFive JHB100 SoC
+ platforms to provide information about the SoC family and variant
+ to user space.
diff --git a/drivers/soc/starfive/socinfo/Makefile b/drivers/soc/starfive/socinfo/Makefile
new file mode 100644
index 000000000000..26c2bdf1de3b
--- /dev/null
+++ b/drivers/soc/starfive/socinfo/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_STARFIVE_JHB100_SOCINFO) += jhb100-socinfo.o
diff --git a/drivers/soc/starfive/socinfo/jhb100-socinfo.c b/drivers/soc/starfive/socinfo/jhb100-socinfo.c
new file mode 100644
index 000000000000..c2ad1c269314
--- /dev/null
+++ b/drivers/soc/starfive/socinfo/jhb100-socinfo.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/sys_soc.h>
+
+#define JHB100_REV_ID_CHAR GENMASK(3, 2)
+#define JHB100_REV_ID_NUM GENMASK(1, 0)
+
+static void jhb100_soc_socdev_release(void *data)
+{
+ struct soc_device *soc_dev = data;
+
+ soc_device_unregister(soc_dev);
+}
+
+static int jhb100_soc_probe(struct platform_device *pdev)
+{
+ struct soc_device_attribute *soc_dev_attr;
+ struct soc_device *soc_dev;
+ void __iomem *base;
+ char rev_char;
+ u32 rev_id;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ soc_dev_attr = devm_kzalloc(&pdev->dev, sizeof(*soc_dev_attr), GFP_KERNEL);
+ if (!soc_dev_attr)
+ return -ENOMEM;
+
+ rev_id = readl(base);
+ rev_char = (char)FIELD_GET(JHB100_REV_ID_CHAR, rev_id) + 'A';
+ rev_id = (u32)FIELD_GET(JHB100_REV_ID_NUM, rev_id);
+
+ soc_dev_attr->revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%c%u",
+ rev_char, rev_id);
+ soc_dev_attr->family = "JH";
+ soc_dev_attr->soc_id = "JHB100";
+
+ soc_dev = soc_device_register(soc_dev_attr);
+ if (IS_ERR(soc_dev))
+ return -ENODEV;
+
+ dev_info(&pdev->dev, "StarFive %s SoC rev(%s)\n", soc_dev_attr->soc_id,
+ soc_dev_attr->revision);
+
+ return devm_add_action_or_reset(&pdev->dev, jhb100_soc_socdev_release,
+ soc_dev);
+}
+
+static const struct of_device_id jhb100_soc_of_match[] = {
+ { .compatible = "starfive,jhb100-socinfo", },
+ { }
+};
+
+static struct platform_driver jhb100_soc_driver = {
+ .probe = jhb100_soc_probe,
+ .driver = {
+ .name = "jhb100-socinfo",
+ .of_match_table = jhb100_soc_of_match,
+ },
+};
+
+static int __init jhb100_soc_init(void)
+{
+ return platform_driver_register(&jhb100_soc_driver);
+}
+
+static void __exit jhb100_soc_exit(void)
+{
+ platform_driver_unregister(&jhb100_soc_driver);
+}
+
+subsys_initcall(jhb100_soc_init);
+module_exit(jhb100_soc_exit);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 SoC Information Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related
* [PATCH v1 13/13] riscv: dts: starfive: jhb100: Add syscon nodes
From: Changhuang Liang @ 2026-04-03 5:49 UTC (permalink / raw)
To: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing
Cc: Chen Wang, Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer,
Keguang Zhang, linux-clk, linux-kernel, devicetree, linux-riscv,
Ley Foon Tan, Changhuang Liang
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>
Add syscon nodes for JHB100 RISC-V BMC SoC. They contain
pcieep0_ecsr_syscon | host0_syscon | husb0_syscon | husbd0_syscon |
pcieep1_ecsr_syscon | host1_syscon | husb1_syscon | husbd1_syscon |
gpu0_syscon | gpu1_syscon | husbcmn_syscon | b2h0_syscon | b2h1_syscon |
h02b_syscon | h12b_syscon | vout_syscon | pcierp_ecsr_syscon |
pcierp_syscon | usb_syscon | npu_syscon | per0_syscon | per1_syscon |
per2_syscon | per3_syscon | sys0_syscon | sys1_syscon | sys2_syscon |
strap_syscon.
Simultaneously add the pll, reset, and chipid nodes under syscon.
Also update the references of pll nodes.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jhb100.dtsi | 220 +++++++++++++++++++----
1 file changed, 186 insertions(+), 34 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
index 700d00f800bc..3456aef30500 100644
--- a/arch/riscv/boot/dts/starfive/jhb100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
@@ -288,36 +288,6 @@ pll1: pll1 {
clock-frequency = <1000000000>;
};
- pll2: pll2 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <903168000>;
- };
-
- pll4: pll4 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100700000>;
- };
-
- pll5: pll5 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100700000>;
- };
-
- pll6: pll6 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <2400000000>;
- };
-
- pll7: pll7 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1950000000>;
- };
-
per2_gmac2_rgmii_rx: per2-gmac2-rgmii-rx {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -398,6 +368,116 @@ bus_nioc: bus_nioc {
<0x4 0x00000000 0x4 0x00000000 0x2 0x0>;
ranges;
+ pcieep0_ecsr_syscon: syscon@10511000 {
+ compatible = "starfive,jhb100-pcieep-ecsr-syscon", "syscon";
+ reg = <0x0 0x10511000 0x0 0x1000>;
+ };
+
+ host0_syscon: syscon@10519000 {
+ compatible = "starfive,jhb100-host-syscon", "syscon";
+ reg = <0x0 0x10519000 0x0 0x1000>;
+ };
+
+ husb0_syscon: syscon@10695000 {
+ compatible = "starfive,jhb100-husb-syscon", "syscon";
+ reg = <0x0 0x10695000 0x0 0x800>;
+ };
+
+ husbd0_syscon: syscon@10695800 {
+ compatible = "starfive,jhb100-husbd-syscon", "syscon";
+ reg = <0x0 0x10695800 0x0 0x800>;
+ };
+
+ gpu0_syscon: syscon@10745000 {
+ compatible = "starfive,jhb100-gpu-syscon", "syscon";
+ reg = <0x0 0x10745000 0x0 0x1000>;
+ };
+
+ pcieep1_ecsr_syscon: syscon@10d11000 {
+ compatible = "starfive,jhb100-pcieep-ecsr-syscon", "syscon";
+ reg = <0x0 0x10d11000 0x0 0x1000>;
+ };
+
+ host1_syscon: syscon@10d19000 {
+ compatible = "starfive,jhb100-host-syscon", "syscon";
+ reg = <0x0 0x10d19000 0x0 0x1000>;
+ };
+
+ husb1_syscon: syscon@10e95000 {
+ compatible = "starfive,jhb100-husb-syscon", "syscon";
+ reg = <0x0 0x10e95000 0x0 0x800>;
+ };
+
+ husbd1_syscon: syscon@10e95800 {
+ compatible = "starfive,jhb100-husbd-syscon", "syscon";
+ reg = <0x0 0x10e95800 0x0 0x800>;
+ };
+
+ gpu1_syscon: syscon@10f45000 {
+ compatible = "starfive,jhb100-gpu-syscon", "syscon";
+ reg = <0x0 0x10f45000 0x0 0x1000>;
+ };
+
+ husbcmn_syscon: syscon@11045000 {
+ compatible = "starfive,jhb100-husbcmn-syscon", "syscon";
+ reg = <0x0 0x11045000 0x0 0x1000>;
+ };
+
+ b2h0_syscon: syscon@11135000 {
+ compatible = "starfive,jhb100-b2h-syscon", "syscon";
+ reg = <0x0 0x11135000 0x0 0x200>;
+ };
+
+ b2h1_syscon: syscon@11135200 {
+ compatible = "starfive,jhb100-b2h-syscon", "syscon";
+ reg = <0x0 0x11135200 0x0 0x200>;
+ };
+
+ h02b_syscon: syscon@11135400 {
+ compatible = "starfive,jhb100-h2b-syscon", "syscon";
+ reg = <0x0 0x11135400 0x0 0x100>;
+ };
+
+ h12b_syscon: syscon@11135500 {
+ compatible = "starfive,jhb100-h2b-syscon", "syscon";
+ reg = <0x0 0x11135500 0x0 0x100>;
+ };
+
+ vout_syscon: syscon@11135800 {
+ compatible = "starfive,jhb100-vout-syscon", "syscon";
+ reg = <0x0 0x11135800 0x0 0x400>;
+ };
+
+ pcierp_ecsr_syscon: syscon@11711000 {
+ compatible = "starfive,jhb100-pcierp-ecsr-syscon", "syscon";
+ reg = <0x0 0x11711000 0x0 0x1000>;
+ };
+
+ pcierp_syscon: syscon@11719000 {
+ compatible = "starfive,jhb100-pcierp-syscon", "syscon",
+ "simple-mfd";
+ reg = <0x0 0x11719000 0x0 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x11719000 0x0 0x1000>;
+
+ pcierp_syscon_rst: reset-controller@14c {
+ compatible = "starfive,jhb100-reset-pcierp";
+ reg = <0x0 0x14c 0x0 0x4>;
+ #reset-cells = <1>;
+ };
+ };
+
+ usb_syscon: syscon@11820000 {
+ compatible = "starfive,jhb100-usb-syscon", "syscon";
+ reg = <0x0 0x11820000 0x0 0x10000>;
+ };
+
+ npu_syscon: syscon@118e5000 {
+ compatible = "starfive,jhb100-npu-syscon", "syscon";
+ reg = <0x0 0x118e5000 0x0 0x100>;
+ };
+
uart6: serial@11982000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x11982000 0x0 0x400>;
@@ -413,7 +493,8 @@ uart6: serial@11982000 {
per0crg: clock-controller@11a08000 {
compatible = "starfive,jhb100-per0crg";
reg = <0x0 0x11a08000 0x0 0x1000>;
- clocks = <&osc>, <&pll6>,
+ clocks = <&osc>,
+ <&per0pll JHB100_PER0PLL_PLL6_OUT>,
<&sys0crg JHB100_SYS0CLK_BMCPER0_400>,
<&sys0crg JHB100_SYS0CLK_BMCPER0_800>,
<&sys0crg JHB100_SYS0CLK_BMCPER0_600>,
@@ -425,10 +506,22 @@ per0crg: clock-controller@11a08000 {
#reset-cells = <1>;
};
+ per0_syscon: syscon@11a09000 {
+ compatible = "starfive,jhb100-per0-syscon", "syscon",
+ "simple-mfd";
+ reg = <0x0 0x11a09000 0x0 0x1000>;
+
+ per0pll: clock-controller {
+ compatible = "starfive,jhb100-per0-pll";
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+ };
+
per1crg: clock-controller@11b40000 {
compatible = "starfive,jhb100-per1crg";
reg = <0x0 0x11b40000 0x0 0x1000>;
- clocks = <&pll7>,
+ clocks = <&per1pll JHB100_PER1PLL_PLL7_OUT>,
<&sys0crg JHB100_SYS0CLK_BMCPER1_600>,
<&sys0crg JHB100_SYS0CLK_BMCPER1_800>,
<&sys2crg JHB100_SYS2CLK_BMCPER1_200>,
@@ -440,6 +533,18 @@ per1crg: clock-controller@11b40000 {
#reset-cells = <1>;
};
+ per1_syscon: syscon@11b41000 {
+ compatible = "starfive,jhb100-per1-syscon", "syscon",
+ "simple-mfd";
+ reg = <0x0 0x11b41000 0x0 0x1000>;
+
+ per1pll: clock-controller {
+ compatible = "starfive,jhb100-per1-pll";
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+ };
+
per2crg: clock-controller@11bc0000 {
compatible = "starfive,jhb100-per2crg";
reg = <0x0 0x11bc0000 0x0 0x1000>;
@@ -461,6 +566,11 @@ per2crg: clock-controller@11bc0000 {
#reset-cells = <1>;
};
+ per2_syscon: syscon@11bc1000 {
+ compatible = "starfive,jhb100-per2-syscon", "syscon";
+ reg = <0x0 0x11bc1000 0x0 0x1000>;
+ };
+
per3crg: clock-controller@11c40000 {
compatible = "starfive,jhb100-per3crg";
reg = <0x0 0x11c40000 0x0 0x1000>;
@@ -480,11 +590,16 @@ per3crg: clock-controller@11c40000 {
#reset-cells = <1>;
};
+ per3_syscon: syscon@11c41000 {
+ compatible = "starfive,jhb100-per3-syscon", "syscon";
+ reg = <0x0 0x11c41000 0x0 0x1000>;
+ };
+
sys0crg: clock-controller@13000000 {
compatible = "starfive,jhb100-sys0crg";
reg = <0x0 0x13000000 0x0 0x4000>;
clocks = <&osc>, <&pll0>, <&pll1>,
- <&pll2>;
+ <&sys0pll JHB100_SYS0PLL_PLL2_OUT>;
clock-names = "osc", "pll0", "pll1", "pll2";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -494,7 +609,9 @@ sys1crg: clock-controller@13004000 {
compatible = "starfive,jhb100-sys1crg";
reg = <0x0 0x13004000 0x0 0x4000>;
clocks = <&osc>, <&pll0>, <&pll1>,
- <&pll2>, <&pll4>, <&pll5>,
+ <&sys0pll JHB100_SYS0PLL_PLL2_OUT>,
+ <&sys0pll JHB100_SYS0PLL_PLL4_OUT>,
+ <&sys0pll JHB100_SYS0PLL_PLL5_OUT>,
<&sys0crg JHB100_SYS0CLK_NPU_600>;
clock-names = "osc", "pll0", "pll1", "pll2",
"pll4", "pll5", "sys1_npu_600";
@@ -513,6 +630,41 @@ sys2crg: clock-controller@13008000 {
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ sys0_syscon: syscon@13010000 {
+ compatible = "starfive,jhb100-sys0-syscon", "syscon",
+ "simple-mfd";
+ reg = <0x0 0x13010000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x13010000 0x0 0x2000>;
+
+ sys0pll: clock-controller {
+ compatible = "starfive,jhb100-sys0-pll";
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
+ chipid@38 {
+ compatible = "starfive,jhb100-socinfo";
+ reg = <0x0 0x38 0x0 0x4>;
+ };
+ };
+
+ sys1_syscon: syscon@13014000 {
+ compatible = "starfive,jhb100-sys1-syscon", "syscon";
+ reg = <0x0 0x13014000 0x0 0x4000>;
+ };
+
+ sys2_syscon: syscon@13018000 {
+ compatible = "starfive,jhb100-sys2-syscon", "syscon";
+ reg = <0x0 0x13018000 0x0 0x4000>;
+ };
+
+ strap_syscon: syscon@1301a000 {
+ compatible = "starfive,jhb100-strap-syscon", "syscon";
+ reg = <0x0 0x1301a000 0x0 0x2000>;
+ };
};
};
};
--
2.25.1
^ permalink raw reply related
* [PATCH v2] drivers/of: fdt: validate flat DT string properties before string use
From: Pengpeng Hou @ 2026-04-03 5:59 UTC (permalink / raw)
To: Rob Herring, Saravana Kannan; +Cc: devicetree, linux-kernel, pengpeng
Firmware-supplied flat DT properties are raw byte sequences. Several
early FDT helpers fetch properties such as status, model, compatible,
and device_type and then use them as C strings with strcmp(), strlen(),
or pr_info() without first proving that the property is NUL-terminated
within its declared length.
Use fdt_stringlist_get() for these string properties instead. That
preserves the existing behavior for valid DTBs while rejecting malformed
unterminated properties before they are passed to C string helpers.
Signed-off-by: Pengpeng Hou <pengpeng@iscas.ac.cn>
---
Changes since v1:
- also validate raw compatible string-list walks in `of_fdt_is_compatible()`
drivers/of/fdt.c | 38 ++++++++++++++------------------------
1 file changed, 14 insertions(+), 24 deletions(-)
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index 331646d667b9..00cd3da3d880 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -68,7 +68,7 @@ void __init of_fdt_limit_memory(int limit)
bool of_fdt_device_is_available(const void *blob, unsigned long node)
{
- const char *status = fdt_getprop(blob, node, "status", NULL);
+ const char *status = fdt_stringlist_get(blob, node, "status", 0, NULL);
if (!status)
return true;
@@ -677,22 +677,15 @@ void __init of_flat_dt_read_addr_size(const __be32 *prop, int entry_index,
* specific compatible values.
*/
static int of_fdt_is_compatible(const void *blob,
- unsigned long node, const char *compat)
+ unsigned long node, const char *compat)
{
const char *cp;
- int cplen;
- unsigned long l, score = 0;
+ int idx = 0, score = 0;
- cp = fdt_getprop(blob, node, "compatible", &cplen);
- if (cp == NULL)
- return 0;
- while (cplen > 0) {
+ while ((cp = fdt_stringlist_get(blob, node, "compatible", idx++, NULL))) {
score++;
if (of_compat_cmp(cp, compat, strlen(compat)) == 0)
return score;
- l = strlen(cp) + 1;
- cp += l;
- cplen -= l;
}
return 0;
@@ -741,9 +734,10 @@ const char * __init of_flat_dt_get_machine_name(void)
const char *name;
unsigned long dt_root = of_get_flat_dt_root();
- name = of_get_flat_dt_prop(dt_root, "model", NULL);
+ name = fdt_stringlist_get(initial_boot_params, dt_root, "model", 0, NULL);
if (!name)
- name = of_get_flat_dt_prop(dt_root, "compatible", NULL);
+ name = fdt_stringlist_get(initial_boot_params, dt_root,
+ "compatible", 0, NULL);
return name;
}
@@ -775,19 +769,14 @@ const void * __init of_flat_dt_match_machine(const void *default_match,
}
if (!best_data) {
const char *prop;
- int size;
+ int idx = 0, size;
pr_err("\n unrecognized device tree list:\n[ ");
- prop = of_get_flat_dt_prop(dt_root, "compatible", &size);
- if (prop) {
- while (size > 0) {
- printk("'%s' ", prop);
- size -= strlen(prop) + 1;
- prop += strlen(prop) + 1;
- }
- }
- printk("]\n\n");
+ while ((prop = fdt_stringlist_get(initial_boot_params, dt_root,
+ "compatible", idx++, &size)))
+ pr_err("'%s' ", prop);
+ pr_err("]\n\n");
return NULL;
}
@@ -1032,7 +1021,8 @@ int __init early_init_dt_scan_memory(void)
const void *fdt = initial_boot_params;
fdt_for_each_subnode(node, fdt, 0) {
- const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
+ const char *type = fdt_stringlist_get(fdt, node,
+ "device_type", 0, NULL);
const __be32 *reg;
int i, l;
bool hotpluggable;
--
2.50.1 (Apple Git-155)
^ permalink raw reply related
* Re: [PATCH v5 3/3] arm64,ppc64le/kdump: pass dm-crypt keys to kdump kernel
From: Andrew Morton @ 2026-04-03 6:31 UTC (permalink / raw)
To: Sourabh Jain
Cc: Coiby Xu, kexec, linux-arm-kernel, linuxppc-dev, devicetree,
Arnaud Lefebvre, Baoquan he, Dave Young, Kairui Song, Pingfan Liu,
Krzysztof Kozlowski, Rob Herring, Thomas Staudt, Will Deacon,
Christophe Leroy (CS GROUP), Catalin Marinas, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Saravana Kannan, open list
In-Reply-To: <51761fcf-955f-45e2-97a5-2b49d8e79d04@linux.ibm.com>
On Thu, 2 Apr 2026 16:24:14 +0530 Sourabh Jain <sourabhjain@linux.ibm.com> wrote:
> But while reading crash_load_dm_crypt_keys() I noticed a possibility of a
> double free at the address pointed by `keys_header`:
>
> In crash_load_dm_crypt_keys()/crash_dump_dm_crypt.c
> snip...
>
> kbuf.buffer = keys_header;
>
> snip....
>
> r = kexec_add_buffer(&kbuf);
> if (r) {
> pr_err("Failed to call kexec_add_buffer, ret=%d\n", r);
> kvfree((void *)kbuf.buffer); <---
> First Free
> return r;
> }
>
> Since `keys_header` is not reset, the next call to build_keys_header()
> will cause a double free at `keys_header`.
>
> static int build_keys_header(void)
> {
>
> snip...
>
> if (keys_header != NULL)
> kvfree(keys_header);
>
> snip...
> }
>
> What do you think?
It looks that way to me.
^ permalink raw reply
* [PATCH v1] arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller
From: Viken Dadhaniya @ 2026-04-03 6:40 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Viken Dadhaniya
Enable the MCP2518FD CAN controller on the QCS6490 RB3 Gen2 platform.
The controller is connected via SPI3 and uses a 40 MHz oscillator.
Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index e393ccf1884a..ceb68a890bf4 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -44,6 +44,14 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ clocks {
+ mcp2518fd_osc: can-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ #clock-cells = <0>;
+ };
+ };
+
dp-connector {
compatible = "dp-connector";
label = "DP";
@@ -1208,6 +1216,20 @@ platform {
};
};
+&spi3 {
+ status = "okay";
+
+ can@0 {
+ compatible = "microchip,mcp2518fd";
+ reg = <0>;
+ interrupts-extended = <&tlmm 7 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mcp2518fd_osc>;
+ spi-max-frequency = <14000000>;
+ vdd-supply = <&vreg_l11c_2p8>;
+ microchip,xstbyen;
+ };
+};
+
&swr2 {
status = "okay";
---
base-commit: cc13002a9f984d37906e9476f3e532a8cdd126f5
change-id: 20260403-can-spi-kodiak-dtsi-64ceebf28431
Best regards,
--
Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
^ permalink raw reply related
* [PATCH v6 0/3] Mediatek MT8189 JPEG support
From: Jianhua Lin @ 2026-04-03 6:49 UTC (permalink / raw)
To: nicolas, mchehab, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno
Cc: devicetree, linux-kernel, linux-media, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, Jianhua Lin
This series is based on tag: next-20260327, linux-next/master
Changes compared with v5:
- Patches 1/3 (dt-bindings: decoder):
- Drop top-level minItems/maxItems for clock-names per Krzysztof's
review.
- Refine allOf block to strictly enforce clock constraints.
Changes compared with v4:
- Refines the device tree bindings for JPEG decoder and encoder.
- Patches 1/3 (dt-bindings: decoder):
Moved the standalone compatible string mediatek,mt8189-jpgdec
into the first oneOf entry along with mt2701 and mt8173, as
suggested by Rob Herring. This correctly groups all independent
ICs and removes the redundant items wrapper.
- Patches 2/3 (dt-bindings: encoder):
Applied the same logic suggested by Rob Herring to the encoder
binding. Restructured the compatible property to clearly
distinguish between the standalone IC (mediatek,mt8189-jpgenc)
and the ICs that must fallback to mediatek,mtk-jpgenc.
Changes compared with v3:
- The v4 is resending the cover-letter, because the v3 cover-letter was
not sent successfully.
Changes compared with v2:
- Dropped the dts patch (arm64: dts: mt8188: update JPEG encoder/decoder
compatible) as it belongs to a different tree/series.
- Patches 1/3 (dt-bindings: decoder):
- Changed the MT8189 compatible to be a standalone `const` instead of
an `enum`.
- Added an `allOf` block with conditional checks to enforce the single
clock ("jpgdec") requirement for MT8189, while preserving the
two-clock requirement for older SoCs.
- Updated commit message to reflect the schema structure changes and
hardware differences.
- Patches 2/3 (dt-bindings: encoder):
- Changed the MT8189 compatible to be a standalone `const` instead of
an `enum` inside the `items` list, as it does not fallback to
"mediatek,mtk-jpgenc" due to 34-bit IOVA requirements.
- Updated commit message to explain the standalone compatible design.
- Patches 3/3 (media: mediatek: jpeg):
- Refined commit message for better clarity regarding 34-bit IOVA and
single clock configuration.
Changes compared with v1:
- Patches 1/4:
- Updating commit message
- Patches 2/4, 3/4:
- Updating commit message
- Adjusted property descriptions acorrding to hardware requirements
- Improved formatting for better readability and consistency
- Patches 4/4:
- Updating commit message
Jianhua Lin (3):
dt-bindings: media: mediatek-jpeg-decoder: add MT8189 compatible
string
dt-bindings: media: mediatek-jpeg-encoder: add MT8189 compatible
string
media: mediatek: jpeg: add compatible for MT8189 SoC
.../bindings/media/mediatek-jpeg-decoder.yaml | 46 +++++++++++++++----
.../bindings/media/mediatek-jpeg-encoder.yaml | 19 +++++---
.../platform/mediatek/jpeg/mtk_jpeg_core.c | 44 ++++++++++++++++++
3 files changed, 95 insertions(+), 14 deletions(-)
--
2.45.2
^ permalink raw reply
* [PATCH v6 1/3] dt-bindings: media: mediatek-jpeg-decoder: add MT8189 compatible string
From: Jianhua Lin @ 2026-04-03 6:49 UTC (permalink / raw)
To: nicolas, mchehab, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno
Cc: devicetree, linux-kernel, linux-media, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, Jianhua Lin, Krzysztof Kozlowski
In-Reply-To: <20260403064912.17259-1-jianhua.lin@mediatek.com>
Add the compatible string for the JPEG decoder block found in the
MediaTek MT8189 SoC.
Compared to previous generation ICs, the MT8189 JPEG decoder requires
34-bit IOVA address space support and only needs a single clock
("jpgdec") instead of two. Therefore, it is added as a standalone
compatible string without falling back to older SoCs.
Update the binding schema to include the new compatible string and add
an `allOf` block with conditional checks. This enforces the single clock
requirement for MT8189 while preserving the two-clock requirement
("jpgdec-smi", "jpgdec") for older SoCs.
Suggested-by: Krzysztof Kozlowski <krzk@kernel.org>
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jianhua Lin <jianhua.lin@mediatek.com>
---
.../bindings/media/mediatek-jpeg-decoder.yaml | 46 +++++++++++++++----
1 file changed, 38 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
index a4aacd3eb189..6596b686980c 100644
--- a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
@@ -15,10 +15,10 @@ description: |-
properties:
compatible:
oneOf:
- - items:
- - enum:
- - mediatek,mt8173-jpgdec
- - mediatek,mt2701-jpgdec
+ - enum:
+ - mediatek,mt2701-jpgdec
+ - mediatek,mt8173-jpgdec
+ - mediatek,mt8189-jpgdec
- items:
- enum:
- mediatek,mt7623-jpgdec
@@ -32,13 +32,20 @@ properties:
maxItems: 1
clocks:
+ minItems: 1
maxItems: 2
- minItems: 2
clock-names:
- items:
- - const: jpgdec-smi
- - const: jpgdec
+ oneOf:
+ - items:
+ - const: jpgdec
+ - items:
+ - const: jpgdec-smi
+ - const: jpgdec
+
+ mediatek,larb:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: a phandle to the smi_larb node.
power-domains:
maxItems: 1
@@ -60,6 +67,29 @@ required:
- power-domains
- iommus
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8189-jpgdec
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ minItems: 1
+ maxItems: 1
+ else:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ minItems: 2
+ maxItems: 2
+
additionalProperties: false
examples:
--
2.45.2
^ permalink raw reply related
* [PATCH v6 2/3] dt-bindings: media: mediatek-jpeg-encoder: add MT8189 compatible string
From: Jianhua Lin @ 2026-04-03 6:49 UTC (permalink / raw)
To: nicolas, mchehab, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno
Cc: devicetree, linux-kernel, linux-media, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, Jianhua Lin, Krzysztof Kozlowski
In-Reply-To: <20260403064912.17259-1-jianhua.lin@mediatek.com>
Add the compatible string for the JPEG encoder block found in the
MediaTek MT8189 SoC.
Unlike some previous SoCs, the MT8189 JPEG encoder requires 34-bit IOVA
address space support. Therefore, it is added as a standalone compatible
string without falling back to the generic "mediatek,mtk-jpgenc" to
ensure the driver applies the correct hardware-specific configurations.
Suggested-by: Krzysztof Kozlowski <krzk@kernel.org>
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jianhua Lin <jianhua.lin@mediatek.com>
---
.../bindings/media/mediatek-jpeg-encoder.yaml | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
index 5b15f8977f67..19948ed25f98 100644
--- a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
@@ -14,13 +14,16 @@ description: |-
properties:
compatible:
- items:
+ oneOf:
- enum:
- - mediatek,mt2701-jpgenc
- - mediatek,mt8183-jpgenc
- - mediatek,mt8186-jpgenc
- - mediatek,mt8188-jpgenc
- - const: mediatek,mtk-jpgenc
+ - mediatek,mt8189-jpgenc
+ - items:
+ - enum:
+ - mediatek,mt2701-jpgenc
+ - mediatek,mt8183-jpgenc
+ - mediatek,mt8186-jpgenc
+ - mediatek,mt8188-jpgenc
+ - const: mediatek,mtk-jpgenc
reg:
maxItems: 1
@@ -34,6 +37,10 @@ properties:
items:
- const: jpgenc
+ mediatek,larb:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: a phandle to the smi_larb node.
+
power-domains:
maxItems: 1
--
2.45.2
^ permalink raw reply related
* [PATCH v6 3/3] media: mediatek: jpeg: add compatible for MT8189 SoC
From: Jianhua Lin @ 2026-04-03 6:49 UTC (permalink / raw)
To: nicolas, mchehab, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno
Cc: devicetree, linux-kernel, linux-media, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, Jianhua Lin
In-Reply-To: <20260403064912.17259-1-jianhua.lin@mediatek.com>
Compared to the previous generation ICs, the MT8189 uses a 34-bit IOVA
address space (16GB) and requires a single clock configuration.
Therefore, add new compatible strings ("mediatek,mt8189-jpgenc" and
"mediatek,mt8189-jpgdec") along with their specific driver data to
support the JPEG encoder and decoder of the MT8189 SoC.
Signed-off-by: Jianhua Lin <jianhua.lin@mediatek.com>
---
.../platform/mediatek/jpeg/mtk_jpeg_core.c | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 8c684756d5fc..786cc2942c3a 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1867,6 +1867,10 @@ static struct clk_bulk_data mt8173_jpeg_dec_clocks[] = {
{ .id = "jpgdec" },
};
+static struct clk_bulk_data mtk_jpeg_dec_clocks[] = {
+ { .id = "jpgdec" },
+};
+
static const struct mtk_jpeg_variant mt8173_jpeg_drvdata = {
.clks = mt8173_jpeg_dec_clocks,
.num_clks = ARRAY_SIZE(mt8173_jpeg_dec_clocks),
@@ -1898,6 +1902,38 @@ static const struct mtk_jpeg_variant mtk_jpeg_drvdata = {
.multi_core = false,
};
+static const struct mtk_jpeg_variant mtk8189_jpegenc_drvdata = {
+ .clks = mtk_jpeg_clocks,
+ .num_clks = ARRAY_SIZE(mtk_jpeg_clocks),
+ .formats = mtk_jpeg_enc_formats,
+ .num_formats = MTK_JPEG_ENC_NUM_FORMATS,
+ .qops = &mtk_jpeg_enc_qops,
+ .irq_handler = mtk_jpeg_enc_irq,
+ .hw_reset = mtk_jpeg_enc_reset,
+ .m2m_ops = &mtk_jpeg_enc_m2m_ops,
+ .dev_name = "mtk-jpeg-enc",
+ .ioctl_ops = &mtk_jpeg_enc_ioctl_ops,
+ .out_q_default_fourcc = V4L2_PIX_FMT_YUYV,
+ .cap_q_default_fourcc = V4L2_PIX_FMT_JPEG,
+ .support_34bit = true,
+};
+
+static const struct mtk_jpeg_variant mtk8189_jpegdec_drvdata = {
+ .clks = mtk_jpeg_dec_clocks,
+ .num_clks = ARRAY_SIZE(mtk_jpeg_dec_clocks),
+ .formats = mtk_jpeg_dec_formats,
+ .num_formats = MTK_JPEG_DEC_NUM_FORMATS,
+ .qops = &mtk_jpeg_dec_qops,
+ .irq_handler = mtk_jpeg_dec_irq,
+ .hw_reset = mtk_jpeg_dec_reset,
+ .m2m_ops = &mtk_jpeg_dec_m2m_ops,
+ .dev_name = "mtk-jpeg-dec",
+ .ioctl_ops = &mtk_jpeg_dec_ioctl_ops,
+ .out_q_default_fourcc = V4L2_PIX_FMT_JPEG,
+ .cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M,
+ .support_34bit = true,
+};
+
static struct mtk_jpeg_variant mtk8195_jpegenc_drvdata = {
.formats = mtk_jpeg_enc_formats,
.num_formats = MTK_JPEG_ENC_NUM_FORMATS,
@@ -1937,6 +1973,14 @@ static const struct of_device_id mtk_jpeg_match[] = {
.compatible = "mediatek,mtk-jpgenc",
.data = &mtk_jpeg_drvdata,
},
+ {
+ .compatible = "mediatek,mt8189-jpgenc",
+ .data = &mtk8189_jpegenc_drvdata,
+ },
+ {
+ .compatible = "mediatek,mt8189-jpgdec",
+ .data = &mtk8189_jpegdec_drvdata,
+ },
{
.compatible = "mediatek,mt8195-jpgenc",
.data = &mtk8195_jpegenc_drvdata,
--
2.45.2
^ permalink raw reply related
* Re: [PATCH v2 2/3] riscv: dts: spacemit: enable USB3 on OrangePi R2S
From: Chukun Pan @ 2026-04-03 7:00 UTC (permalink / raw)
To: michael.opdenacker
Cc: alex, amadeus, aou, conor+dt, devicetree, dlan, krzk+dt,
linux-kernel, linux-riscv, palmer, pjw, robh, spacemit
In-Reply-To: <46e715a4-0fd7-4692-9a25-a44d469b17b0@rootcommit.com>
Hi,
> Thanks a lot for the patch!
> Would you mind sharing your configuration with me (in PM?).
>
> I can list the USB 3 hub, but I can't see the USB mass storage device
> plugged in the USB3 port.
Are you running the latest linux-next? Otherwise, a patch is needed:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=764c2e6e60bf17910d84e7179fee14129e053b96
Thanks,
Chukun
^ permalink raw reply
* Re: [RFC PATCH 05/15] libfdt: Introduce fdt_first_node()
From: Herve Codina @ 2026-04-03 7:07 UTC (permalink / raw)
To: Luca Ceresoli
Cc: David Gibson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Ayush Singh, Geert Uytterhoeven, devicetree-compiler, devicetree,
linux-kernel, devicetree-spec, Hui Pu, Ian Ray, Thomas Petazzoni
In-Reply-To: <DHHWXNCDAWG9.2LYVXAWG8RBTY@bootlin.com>
Hi Luca, David,
On Wed, 01 Apr 2026 17:11:15 +0200
"Luca Ceresoli" <luca.ceresoli@bootlin.com> wrote:
> Hi Hervé, David,
>
> I'm trying to review the patches that have no feedback so far.
>
> Being new to the dtc codebase I'm mostly pointing out things that are not
> clear from a newcomer point of view. I hope this helps anyway.
>
> On Tue Feb 10, 2026 at 6:33 PM CET, Herve Codina wrote:
> > In several places, libfdt assumes that a FDT_BEGIN_NODE tag is present
> > at the offset 0 of the structure block.
> >
> > This assumption is not correct. Indeed, a FDT_NOP can be present at the
> > offset 0 and this is a legit case.
>
> I wonder whether this can be proven by showing an example, or the specs, or
> whatever use case that makes sense.
I can point the device-tree specification and add the following:
--- 8< ---
Indeed, the FDT_NOP definition according to the device-tree specification [0]
is the following:
The FDT_NOP token will be ignored by any program parsing the device
tree. This token has no extra data; so it is followed immediately by
the next token, which can be any valid token. A property or node
definition in the tree can be overwritten with FDT_NOP tokens to
remove it from the tree without needing to move other sections of
the tree’s representation in the devicetree blob.
Nothing refers to any location for this tag and it has to be simply ignored.
Having this tag at offset 0 doesn't make an exception, the tag has to be
ignored.
[0] https://github.com/devicetree-org/devicetree-specification/blob/main/source/chapter5-flattened-format.rst?plain=1#L317
--- 8< ---
>
> > Introduce fdt_first_node() in order to get the offset of the first node
> > (first FDT_BEGIN_NODE tag) available in a fdt blob.
> >
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> > ---
> > libfdt/fdt.c | 25 +++++++++++++++++++++++++
> > libfdt/libfdt_internal.h | 1 +
> > 2 files changed, 26 insertions(+)
> >
> > diff --git a/libfdt/fdt.c b/libfdt/fdt.c
> > index 56d4dcb..676c7d7 100644
> > --- a/libfdt/fdt.c
> > +++ b/libfdt/fdt.c
> > @@ -252,6 +252,31 @@ int fdt_check_prop_offset_(const void *fdt, int offset)
> > return offset;
> > }
> >
>
> Even though this seems to be quite uncommon in this repository, I think
> documenting new functions would be helpful, especially preconditions,
> postconditions and parameter values when not obvious.
>
> What about:
>
> Find the initial node with content (FDT_BEGIN_NODE) in a fdt, skipping
> FDT_NOP [and <other tags> is applicable].
>
> *return: pointer to the first node into the fdt or e negative error value
As you already said, documentation is quite uncommon here.
I would prefer to keep the code consistent and avoid adding documentation for
some functions and not others.
On the other side, adding some documentation could be beneficial.
David, what do you prefer?
Should I document new functions I introduce?
Best regards,
Hervé
^ permalink raw reply
* Re: [PATCH v6 1/3] dt-bindings: media: mediatek-jpeg-decoder: add MT8189 compatible string
From: Krzysztof Kozlowski @ 2026-04-03 7:13 UTC (permalink / raw)
To: Jianhua Lin, nicolas, mchehab, robh, krzk+dt, conor+dt,
matthias.bgg, angelogioacchino.delregno
Cc: devicetree, linux-kernel, linux-media, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu
In-Reply-To: <20260403064912.17259-2-jianhua.lin@mediatek.com>
On 03/04/2026 08:49, Jianhua Lin wrote:
> Add the compatible string for the JPEG decoder block found in the
> MediaTek MT8189 SoC.
>
> Compared to previous generation ICs, the MT8189 JPEG decoder requires
> 34-bit IOVA address space support and only needs a single clock
> ("jpgdec") instead of two. Therefore, it is added as a standalone
> compatible string without falling back to older SoCs.
>
> Update the binding schema to include the new compatible string and add
> an `allOf` block with conditional checks. This enforces the single clock
> requirement for MT8189 while preserving the two-clock requirement
> ("jpgdec-smi", "jpgdec") for older SoCs.
>
> Suggested-by: Krzysztof Kozlowski <krzk@kernel.org>
What?
> Suggested-by: Rob Herring <robh@kernel.org>
Where?
And I would say also - Why?
> Signed-off-by: Jianhua Lin <jianhua.lin@mediatek.com>
> ---
> .../bindings/media/mediatek-jpeg-decoder.yaml | 46 +++++++++++++++----
> 1 file changed, 38 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
> index a4aacd3eb189..6596b686980c 100644
> --- a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
> +++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
> @@ -15,10 +15,10 @@ description: |-
> properties:
> compatible:
> oneOf:
> - - items:
> - - enum:
> - - mediatek,mt8173-jpgdec
> - - mediatek,mt2701-jpgdec
> + - enum:
> + - mediatek,mt2701-jpgdec
> + - mediatek,mt8173-jpgdec
> + - mediatek,mt8189-jpgdec
> - items:
> - enum:
> - mediatek,mt7623-jpgdec
> @@ -32,13 +32,20 @@ properties:
> maxItems: 1
>
> clocks:
> + minItems: 1
> maxItems: 2
> - minItems: 2
>
> clock-names:
> - items:
> - - const: jpgdec-smi
> - - const: jpgdec
> + oneOf:
> + - items:
> + - const: jpgdec
> + - items:
> + - const: jpgdec-smi
> + - const: jpgdec
> +
> + mediatek,larb:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: a phandle to the smi_larb node.
>
> power-domains:
> maxItems: 1
> @@ -60,6 +67,29 @@ required:
> - power-domains
> - iommus
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: mediatek,mt8189-jpgdec
> + then:
> + properties:
> + clocks:
> + minItems: 1
You are making some random changes to this.
Please go to previous version and read again feedback.
Best regards,
Krzysztof
^ permalink raw reply
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