* [PATCH v2 3/4] arm64: dts: qcom: hamoa-pmics: define VADC for pmk8550
From: Aleksandrs Vinarskis @ 2026-04-04 12:55 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Hans de Goede, Ilpo Järvinen,
Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
laurentiu.tudor1, Abel Vesa, Tobias Heider, Val Packett
In-Reply-To: <20260404-dell-xps-9345-ec-v2-0-c977c3caa81f@vinarskis.com>
Follow pattern of pmk8350 to add missing pmk8550 VADC to hamoa.
Register address of 0x9000 matches example schema for spmi-adc5-gen3.
Signed-off-by: Aleksandrs Vinarskis <alex@vinarskis.com>
---
arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
index 6a31a0adf8be472badea502a916cdbc9477e9f2b..cc69d299bc356d90aa1483f347f5eee43b853e45 100644
--- a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi
@@ -218,6 +218,32 @@ pon_resin: resin {
};
};
+ pmk8550_vadc: adc@9000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x9000>, <0x9100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+ #thermal-sensor-cells = <1>;
+
+ channel@3 {
+ reg = <0x3>;
+ label = "pmk8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@44 {
+ reg = <0x44>;
+ label = "pmk8550_xo_therm";
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,adc-tm;
+ };
+ };
+
pmk8550_rtc: rtc@6100 {
compatible = "qcom,pmk8350-rtc";
reg = <0x6100>, <0x6200>;
--
2.53.0
^ permalink raw reply related
* [PATCH v2 2/4] platform: arm64: dell-xps-ec: new driver
From: Aleksandrs Vinarskis @ 2026-04-04 12:55 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Hans de Goede, Ilpo Järvinen,
Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
laurentiu.tudor1, Abel Vesa, Tobias Heider, Val Packett
In-Reply-To: <20260404-dell-xps-9345-ec-v2-0-c977c3caa81f@vinarskis.com>
Introduce EC driver for Dell XPS 13 9345 (codename 'tributo') which may
partially of fully compatible with Snapdragon-based Dell Latitude,
Inspiron ('thena'). Primary function of this driver is unblock EC's
thermal management, specifically to provide it with necessary
information to control device fans, peripherals power.
The driver was developed primarily by analyzing ACPI DSDT's _DSM and
i2c dumps of communication between SoC and EC. Changes to Windows
driver's behavior include increasing temperature feed loop from ~50ms
to 100ms here.
While Xps's EC is rather complex and controls practically all device
peripherals including touch row's brightness and special keys such as
mic mute, these do not go over this particular i2c interface.
Not yet implemented features:
- On lid-close IRQ event is registered. Windows performs what to
appears to be thermistor constants readout, though its not obvious
what it used for.
- According to ACPI's _DSM there is a method to readout fans' RPM.
- Initial thermistor constants were sniffed from Windows, these can be
likely fine tuned for better cooling performance.
- There is additional temperature reading that Windows sents to EC but
more rare than others, likely SoC T_j / TZ98 or TZ4. This is the only
thermal zone who's reading can exceed 115C without triggering thermal
shutdown.
- Given similarities between 'tributo' and 'thena' platforms, including
EC i2c address, driver can be potentially extended to support both.
Signed-off-by: Aleksandrs Vinarskis <alex@vinarskis.com>
---
MAINTAINERS | 1 +
drivers/platform/arm64/Kconfig | 12 ++
drivers/platform/arm64/Makefile | 1 +
drivers/platform/arm64/dell-xps-ec.c | 267 +++++++++++++++++++++++++++++++++++
4 files changed, 281 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a5d175559f4468dfe363b319a1b08d3425f4d712..c150f57b60706224e5b24b0dfb3d8a9b81f36398 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7240,6 +7240,7 @@ DELL XPS EMBEDDED CONTROLLER DRIVER
M: Aleksandrs Vinarskis <alex@vinarskis.com>
S: Maintained
F: Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml
+F: drivers/platform/arm64/dell-xps-ec.c
DELTA AHE-50DC FAN CONTROL MODULE DRIVER
M: Zev Weiss <zev@bewilderbeest.net>
diff --git a/drivers/platform/arm64/Kconfig b/drivers/platform/arm64/Kconfig
index 10f905d7d6bfa5fad30a0689d3a20481268c781e..0bc8f016032bb05cb3a7cc50bdf1092da04153bc 100644
--- a/drivers/platform/arm64/Kconfig
+++ b/drivers/platform/arm64/Kconfig
@@ -33,6 +33,18 @@ config EC_ACER_ASPIRE1
laptop where this information is not properly exposed via the
standard ACPI devices.
+config EC_DELL_XPS
+ tristate "Dell XPS 9345 Embedded Controller driver"
+ depends on ARCH_QCOM || COMPILE_TEST
+ depends on I2C
+ depends on IIO
+ help
+ Driver for the Embedded Controller in the Qualcomm Snapdragon-based
+ Dell XPS 13 9345, which handles thermal management and fan speed
+ control.
+
+ Say M or Y here to include this support.
+
config EC_HUAWEI_GAOKUN
tristate "Huawei Matebook E Go Embedded Controller driver"
depends on ARCH_QCOM || COMPILE_TEST
diff --git a/drivers/platform/arm64/Makefile b/drivers/platform/arm64/Makefile
index 60c131cff6a15bb51a49c9edab95badf513ee0f6..6768dc6c2310837374e67381cfc729bed1fdaaef 100644
--- a/drivers/platform/arm64/Makefile
+++ b/drivers/platform/arm64/Makefile
@@ -6,6 +6,7 @@
#
obj-$(CONFIG_EC_ACER_ASPIRE1) += acer-aspire1-ec.o
+obj-$(CONFIG_EC_DELL_XPS) += dell-xps-ec.o
obj-$(CONFIG_EC_HUAWEI_GAOKUN) += huawei-gaokun-ec.o
obj-$(CONFIG_EC_LENOVO_YOGA_C630) += lenovo-yoga-c630.o
obj-$(CONFIG_EC_LENOVO_THINKPAD_T14S) += lenovo-thinkpad-t14s.o
diff --git a/drivers/platform/arm64/dell-xps-ec.c b/drivers/platform/arm64/dell-xps-ec.c
new file mode 100644
index 0000000000000000000000000000000000000000..bf1495fbe473ccdb82b95a66b56e8525f782cc8e
--- /dev/null
+++ b/drivers/platform/arm64/dell-xps-ec.c
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2026, Aleksandrs Vinarskis <alex@vinarskis.com>
+ */
+
+#include <linux/array_size.h>
+#include <linux/dev_printk.h>
+#include <linux/device.h>
+#include <linux/devm-helpers.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/iio/consumer.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/module.h>
+#include <linux/pm.h>
+#include <linux/unaligned.h>
+#include <linux/workqueue.h>
+
+#define DELL_XPS_EC_SUSPEND_CMD 0xb9
+#define DELL_XPS_EC_SUSPEND_MSG_LEN 64
+
+#define DELL_XPS_EC_TEMP_CMD0 0xfb
+#define DELL_XPS_EC_TEMP_CMD1 0x20
+#define DELL_XPS_EC_TEMP_CMD3 0x02
+#define DELL_XPS_EC_TEMP_MSG_LEN 6
+#define DELL_XPS_EC_TEMP_POLL_JIFFIES msecs_to_jiffies(100)
+
+/*
+ * Format:
+ * - header/unknown (2 bytes)
+ * - per-thermistor entries (3 bytes): thermistor_id, param1, param2
+ */
+static const u8 dell_xps_ec_thermistor_profile[] = {
+ 0xff, 0x54,
+ 0x01, 0x00, 0x2b, /* sys_therm0 */
+ 0x02, 0x44, 0x2a, /* sys_therm1 */
+ 0x03, 0x44, 0x2b, /* sys_therm2 */
+ 0x04, 0x44, 0x28, /* sys_therm3 */
+ 0x05, 0x55, 0x2a, /* sys_therm4 */
+ 0x06, 0x44, 0x26, /* sys_therm5 */
+ 0x07, 0x44, 0x2b, /* sys_therm6 */
+};
+
+/*
+ * Mapping from IIO channel name to EC command byte
+ */
+static const struct {
+ const char *name;
+ u8 cmd;
+} dell_xps_ec_therms[] = {
+ /* TODO: 0x01 is sent only occasionally, likely TZ98 or TZ4 */
+ { "sys_therm0", 0x02 },
+ { "sys_therm1", 0x03 },
+ { "sys_therm2", 0x04 },
+ { "sys_therm3", 0x05 },
+ { "sys_therm4", 0x06 },
+ { "sys_therm5", 0x07 },
+ { "sys_therm6", 0x08 },
+};
+
+struct dell_xps_ec {
+ struct device *dev;
+ struct i2c_client *client;
+ struct iio_channel *therm_channels[ARRAY_SIZE(dell_xps_ec_therms)];
+ struct delayed_work temp_work;
+};
+
+static int dell_xps_ec_suspend_cmd(struct dell_xps_ec *ec, bool suspend)
+{
+ u8 buf[DELL_XPS_EC_SUSPEND_MSG_LEN] = {};
+ int ret;
+
+ buf[0] = DELL_XPS_EC_SUSPEND_CMD;
+ buf[1] = suspend ? 0x01 : 0x00;
+ /* bytes 2..63 remain zero */
+
+ ret = i2c_master_send(ec->client, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int dell_xps_ec_send_temp(struct dell_xps_ec *ec, u8 cmd_byte,
+ int milli_celsius)
+{
+ u8 buf[DELL_XPS_EC_TEMP_MSG_LEN];
+ u16 deci_celsius;
+ int ret;
+
+ /* Convert milli-Celsius to deci-Celsius (Celsius * 10) */
+ deci_celsius = milli_celsius / 100;
+
+ buf[0] = DELL_XPS_EC_TEMP_CMD0;
+ buf[1] = DELL_XPS_EC_TEMP_CMD1;
+ buf[2] = cmd_byte;
+ buf[3] = DELL_XPS_EC_TEMP_CMD3;
+ put_unaligned_le16(deci_celsius, &buf[4]);
+
+ ret = i2c_master_send(ec->client, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static void dell_xps_ec_temp_work_fn(struct work_struct *work)
+{
+ struct dell_xps_ec *ec = container_of(work, struct dell_xps_ec,
+ temp_work.work);
+ int val, ret, i;
+
+ for (i = 0; i < ARRAY_SIZE(dell_xps_ec_therms); i++) {
+ if (!ec->therm_channels[i])
+ continue;
+
+ ret = iio_read_channel_processed(ec->therm_channels[i], &val);
+ if (ret < 0) {
+ dev_err_ratelimited(ec->dev,
+ "Failed to read thermistor %s: %d\n",
+ dell_xps_ec_therms[i].name, ret);
+ continue;
+ }
+
+ ret = dell_xps_ec_send_temp(ec, dell_xps_ec_therms[i].cmd, val);
+ if (ret < 0) {
+ dev_err_ratelimited(ec->dev,
+ "Failed to send temp for %s: %d\n",
+ dell_xps_ec_therms[i].name, ret);
+ }
+ }
+
+ schedule_delayed_work(&ec->temp_work, DELL_XPS_EC_TEMP_POLL_JIFFIES);
+}
+
+static irqreturn_t dell_xps_ec_irq_handler(int irq, void *data)
+{
+ struct dell_xps_ec *ec = data;
+
+ /*
+ * TODO: IRQ is fired on lid-close. Follow Windows example to read out
+ * the thermistor thresholds and potentially fan speeds.
+ */
+ dev_info_ratelimited(ec->dev, "IRQ triggered! (irq=%d)\n", irq);
+
+ return IRQ_HANDLED;
+}
+
+static int dell_xps_ec_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ struct dell_xps_ec *ec;
+ int ret, i;
+
+ ec = devm_kzalloc(dev, sizeof(*ec), GFP_KERNEL);
+ if (!ec)
+ return -ENOMEM;
+
+ ec->dev = dev;
+ ec->client = client;
+ i2c_set_clientdata(client, ec);
+
+ /* Set default thermistor profile */
+ ret = i2c_master_send(client, dell_xps_ec_thermistor_profile,
+ sizeof(dell_xps_ec_thermistor_profile));
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to set thermistor profile\n");
+
+ /* Get IIO channels for thermistors */
+ for (i = 0; i < ARRAY_SIZE(dell_xps_ec_therms); i++) {
+ ec->therm_channels[i] =
+ devm_iio_channel_get(dev, dell_xps_ec_therms[i].name);
+ if (IS_ERR(ec->therm_channels[i])) {
+ ret = PTR_ERR(ec->therm_channels[i]);
+ ec->therm_channels[i] = NULL;
+ if (ret == -EPROBE_DEFER)
+ return ret;
+ dev_warn(dev, "Thermistor %s not available: %d\n",
+ dell_xps_ec_therms[i].name, ret);
+ }
+ }
+
+ /* Start periodic temperature reporting */
+ ret = devm_delayed_work_autocancel(dev, &ec->temp_work,
+ dell_xps_ec_temp_work_fn);
+ if (ret)
+ return ret;
+ schedule_delayed_work(&ec->temp_work, DELL_XPS_EC_TEMP_POLL_JIFFIES);
+ dev_dbg(dev, "Started periodic temperature reporting to EC every %d ms\n",
+ jiffies_to_msecs(DELL_XPS_EC_TEMP_POLL_JIFFIES));
+
+ /* Request IRQ for EC events */
+ ret = devm_request_threaded_irq(dev, client->irq, NULL,
+ dell_xps_ec_irq_handler,
+ IRQF_ONESHOT, dev_name(dev), ec);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to request IRQ\n");
+
+ return 0;
+}
+
+/*
+ * Notify EC of suspend
+ *
+ * This will:
+ * - Cut power to display/trackpad/keyboard/touchrow, wake-up source still works
+ */
+static int dell_xps_ec_suspend(struct device *dev)
+{
+ struct dell_xps_ec *ec = dev_get_drvdata(dev);
+
+ cancel_delayed_work_sync(&ec->temp_work);
+
+ return dell_xps_ec_suspend_cmd(ec, true);
+}
+
+/*
+ * Notify EC of resume
+ *
+ * This will undo the suspend actions
+ * Without the resume signal, device would wake up but be forced back into
+ * suspend by EC within seconds
+ */
+static int dell_xps_ec_resume(struct device *dev)
+{
+ struct dell_xps_ec *ec = dev_get_drvdata(dev);
+ int ret;
+
+ ret = dell_xps_ec_suspend_cmd(ec, false);
+ if (ret)
+ return ret;
+
+ schedule_delayed_work(&ec->temp_work, DELL_XPS_EC_TEMP_POLL_JIFFIES);
+ return 0;
+}
+
+static const struct of_device_id dell_xps_ec_of_match[] = {
+ { .compatible = "dell,xps13-9345-ec" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, dell_xps_ec_of_match);
+
+static const struct i2c_device_id dell_xps_ec_i2c_id[] = {
+ { "dell-xps-ec" },
+ {}
+};
+MODULE_DEVICE_TABLE(i2c, dell_xps_ec_i2c_id);
+
+static const struct dev_pm_ops dell_xps_ec_pm_ops = {
+ SYSTEM_SLEEP_PM_OPS(dell_xps_ec_suspend, dell_xps_ec_resume)
+};
+
+static struct i2c_driver dell_xps_ec_driver = {
+ .driver = {
+ .name = "dell-xps-ec",
+ .of_match_table = dell_xps_ec_of_match,
+ .pm = &dell_xps_ec_pm_ops,
+ },
+ .probe = dell_xps_ec_probe,
+ .id_table = dell_xps_ec_i2c_id,
+};
+module_i2c_driver(dell_xps_ec_driver);
+
+MODULE_AUTHOR("Aleksandrs Vinarskis <alex@vinarskis.com>");
+MODULE_DESCRIPTION("Dell XPS 13 9345 Embedded Controller");
+MODULE_LICENSE("GPL");
--
2.53.0
^ permalink raw reply related
* [PATCH v2 1/4] dt-bindings: platform: introduce EC for Dell XPS 13 9345
From: Aleksandrs Vinarskis @ 2026-04-04 12:55 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Hans de Goede, Ilpo Järvinen,
Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
laurentiu.tudor1, Abel Vesa, Tobias Heider, Val Packett,
Krzysztof Kozlowski
In-Reply-To: <20260404-dell-xps-9345-ec-v2-0-c977c3caa81f@vinarskis.com>
Add bindings for Embedded Controller (EC) in Dell XPS 13 9345 (platform
codename 'tributo'). It may be partially or fully compatible with EC
found in Snapdragon-based Dell Latitude, Inspiron ('thena').
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Aleksandrs Vinarskis <alex@vinarskis.com>
---
.../embedded-controller/dell,xps13-9345-ec.yaml | 91 ++++++++++++++++++++++
MAINTAINERS | 5 ++
2 files changed, 96 insertions(+)
diff --git a/Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..e14dbf2f1a6af8cc7511890fbef08c6c717c0aa6
--- /dev/null
+++ b/Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/embedded-controller/dell,xps13-9345-ec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Dell XPS 13 9345 Embedded Controller
+
+maintainers:
+ - Aleksandrs Vinarskis <alex@vinarskis.com>
+
+description:
+ The Dell XPS 13 9345 has an Embedded Controller (EC) which handles thermal
+ and power management. It is communicating with SoC over multiple i2c busses.
+ Among other things, it handles fan speed control, thermal shutdown, peripheral
+ power supply including trackpad, touch-row, display. For these functions, it
+ requires frequently updated thermal readings from onboard thermistors.
+
+properties:
+ compatible:
+ const: dell,xps13-9345-ec
+
+ reg:
+ const: 0x3b
+
+ interrupts:
+ maxItems: 1
+
+ io-channels:
+ description:
+ ADC channels connected to the 7 onboard thermistors on PMK8550.
+ EC requires frequent thermal readings of these channels to perform
+ automated fan speed control.
+ items:
+ - description: ADC channel for sys_therm0
+ - description: ADC channel for sys_therm1
+ - description: ADC channel for sys_therm2
+ - description: ADC channel for sys_therm3
+ - description: ADC channel for sys_therm4
+ - description: ADC channel for sys_therm5
+ - description: ADC channel for sys_therm6
+
+ io-channel-names:
+ items:
+ - const: sys_therm0
+ - const: sys_therm1
+ - const: sys_therm2
+ - const: sys_therm3
+ - const: sys_therm4
+ - const: sys_therm5
+ - const: sys_therm6
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - io-channels
+ - io-channel-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ embedded-controller@3b {
+ compatible = "dell,xps13-9345-ec";
+ reg = <0x3b>;
+ interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_LOW>;
+
+ io-channels = <&pmk8550_vadc PM8350_ADC7_GPIO3_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_GPIO4_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>,
+ <&pmk8550_vadc PM8350_ADC7_AMUX_THM5_100K_PU(1)>;
+ io-channel-names = "sys_therm0",
+ "sys_therm1",
+ "sys_therm2",
+ "sys_therm3",
+ "sys_therm4",
+ "sys_therm5",
+ "sys_therm6";
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 96e0781f2201b41b976dfa69efd44d62c4ff0058..a5d175559f4468dfe363b319a1b08d3425f4d712 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7236,6 +7236,11 @@ S: Maintained
F: Documentation/ABI/testing/sysfs-class-firmware-attributes
F: drivers/platform/x86/dell/dell-wmi-sysman/
+DELL XPS EMBEDDED CONTROLLER DRIVER
+M: Aleksandrs Vinarskis <alex@vinarskis.com>
+S: Maintained
+F: Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml
+
DELTA AHE-50DC FAN CONTROL MODULE DRIVER
M: Zev Weiss <zev@bewilderbeest.net>
L: linux-hwmon@vger.kernel.org
--
2.53.0
^ permalink raw reply related
* [PATCH v2 0/4] Introduce EC driver for Snapdragon X1E based Dell XPS 13 9345
From: Aleksandrs Vinarskis @ 2026-04-04 12:55 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Hans de Goede, Ilpo Järvinen,
Bryan O'Donoghue
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
laurentiu.tudor1, Abel Vesa, Tobias Heider, Val Packett,
Krzysztof Kozlowski
This series adds Embedded Controller (EC) driver for Dell XPS 13 9345.
While EC appears to control most of device's peripherals, particular
driver addresses power and thermal managment issues. Key operational
principle involves initial thermistor constants configuration followed
by a periodic reporting of these onboard thermistor values from across
the motherboard to the EC. The latter then handles fan ramp-up/
ramp-down internally. Suspend/Resume must be likewise propagated to EC
for power management.
The driver was developed primarily by analyzing ACPI DSDT's _DSM and
i2c dumps of communication between SoC and EC during various stages of
operation (bootup, suspend, resume).
With EC driver in place, the following issues are addressed:
1. Fans were not properly cooling the laptop, would kick in late and
spin lazily, resulting in heavy throttling. With EC driver fans
start sooner and hit high RPM under heavy load.
2. Fans were not stopping once SoC temperature dropped, they would keep
slowly spinning irrespective of suspend and/or closed lid until the
next powercycle. With EC driver shortly after SoC temperature drops,
thermistors temperature drops, and fans ramp-down.
3. Keyboard and touch row backlight were not turning off during
suspend - only lid close would power off the touch row. With EC
driver behavior matches that of Windows, suspending device with lid
open powers off the peripherals.
As thermistor readout depends on pmic's ADCs, this series introduces
EC driver and its schema, adds missing ADC to hamoa-pmics, and finally
adds thermistor and EC nodes to x1e80100-dell-xps13-9345.dts.
Additional findings:
- Max fan speed depends on Dell's power mode settings, configurable in
BIOS or using Windows app (relies on ACPI-WMI). It appears best
cooling performance is achieved under 'Ultra Performance' profile.
- When the said power mode is changed using Windows app, EC IRQ is
triggered. Windows performs what appears to be thermistor contants
readout, though its not obvious what it is used for.
- Given similarities between Dell XPS 13 series (codename 'tributo')
and Snapdragon-based Latitude, Inspiron ('thena'), including matching
EC address and response to suspend/resume command the EC driver can
be likely used for both, though in-depth testing on 'thena' is
required.
This series depends on QCOM SPMI PMIC5 Gen3 ADC [1], which was added to
`linux-next` for v7.1, but must be picked if this series to be backported.
[1] https://lore.kernel.org/all/20260209105438.596339-1-jishnu.prakash@oss.qualcomm.com/
Signed-off-by: Aleksandrs Vinarskis <alex@vinarskis.com>
---
Changes in v2:
- Update cover letter to indicate dependency on QCOM ADC series, only
relevant for backporting
- Update description of dell_xps_ec_suspend: entering suspend does not
necessarily ramp down the fans, if thermistors still report high temps
- Add die_temp/xo_therm to pmk8550 as per Konrad Dybcio
- Add missing header imports as per Ilpo Järvinen
- Add explanation for EC reset pin being reserved
- Fix device-tree: minor issues as per Konrad Dybcio
- Fix device-tree: alingment issues as per Konrad Dybcio
- Fix driver: alingment issues as per Bjorn Andersson
- Fix driver: handle temp value as 16bit register as per Ilpo Järvinen
- Fix bindigs: description and example as per Krzysztof Kozlowski
- Link to v1: https://lore.kernel.org/r/20260401-dell-xps-9345-ec-v1-0-afa5cacd49be@vinarskis.com
---
Aleksandrs Vinarskis (4):
dt-bindings: platform: introduce EC for Dell XPS 13 9345
platform: arm64: dell-xps-ec: new driver
arm64: dts: qcom: hamoa-pmics: define VADC for pmk8550
arm64: dts: qcom: x1e80100-dell-xps13-9345: introduce EC
.../embedded-controller/dell,xps13-9345-ec.yaml | 91 +++++++
MAINTAINERS | 6 +
arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi | 26 ++
.../boot/dts/qcom/x1e80100-dell-xps13-9345.dts | 94 +++++++-
drivers/platform/arm64/Kconfig | 12 +
drivers/platform/arm64/Makefile | 1 +
drivers/platform/arm64/dell-xps-ec.c | 267 +++++++++++++++++++++
7 files changed, 495 insertions(+), 2 deletions(-)
---
base-commit: ec07eff1fd1ed6c4dca399aee4e8da15856589f0
change-id: 20260331-dell-xps-9345-ec-e5f49d1bef61
Best regards,
--
Aleksandrs Vinarskis <alex@vinarskis.com>
^ permalink raw reply
* Re: [PATCH v1 17/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator
From: Krzysztof Kozlowski @ 2026-04-04 11:34 UTC (permalink / raw)
To: Changhuang Liang
Cc: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Kees Cook,
Gustavo A . R . Silva, Richard Cochran, linux-clk, linux-kernel,
devicetree, linux-riscv, linux-hardening, netdev, Sia Jee Heng,
Hal Feng, Ley Foon Tan
In-Reply-To: <20260402105523.447523-18-changhuang.liang@starfivetech.com>
On Thu, Apr 02, 2026 at 03:55:18AM -0700, Changhuang Liang wrote:
> + clocks:
> + items:
> + - description: Peripheral-2 600MHz
> + - description: Peripheral-2 400MHz
> + - description: Peripheral-2 125MHz
> + - description: Peripheral-2 GMAC2 RGMII RX
> + - description: Peripheral-2 GMAC2 RMII Reference
> + - description: Peripheral-2 GMAC3 SGMII TX
> + - description: Peripheral-2 GMAC3 SGMII RX
> + - description: Main Oscillator (25 MHz)
> +
> + clock-names:
> + items:
> + - const: per2_600
Does not have any meaningful name in datasheet / clock hierarchy?
> + - const: per2_400
> + - const: per2_125
> + - const: per2_gmac2_rgmii_rx
> + - const: per2_gmac2_rmii_ref
> + - const: per2_gmac3_sgmii_tx
> + - const: per2_gmac3_sgmii_rx
per2 is redundant. Name these according to clock input names.
Same for your patch for per3.
> + - const: osc
> +
> +
Just one blank line
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: arm: qcom: Add monaco-evk-ac support
From: Umang Chheda @ 2026-04-04 11:12 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Richard Cochran, linux-arm-msm, devicetree,
linux-kernel, netdev, umang.chheda
In-Reply-To: <4d32e86f-353c-4951-89ca-46aa49d60f76@oss.qualcomm.com>
On 4/4/2026 4:15 PM, Umang Chheda wrote:
>
>
> On 4/4/2026 1:58 AM, Dmitry Baryshkov wrote:
>> On Fri, Apr 03, 2026 at 04:14:28PM +0530, Umang Chheda wrote:
>>> Hello Dmitry,
>>>
>>> On 4/1/2026 5:06 PM, Dmitry Baryshkov wrote:
>>>> On Wed, Apr 01, 2026 at 12:14:42AM +0530, Umang Chheda wrote:
>>>>> Introduce bindings for the monaco-evk-ac IoT board, which is
>>>>> based on the monaco-ac (QCS8300-AC) SoC variant.
>>>>
>>>> If it is a different SoC SKU, should it be reflected in the SoC compat
>>>> strings?
>>>
>>> Monaco‑AC does not introduce any S/W differences compared to Monaco SoC
>>> -- All IP blocks and bindings remain identical from S/W PoV, Hence
>>> haven't included the SoC SKU in the SoC compat strings.
>>>
>>> Hope this is okay ? Your view on this ?
>>
>> You are descibing -AC as the main difference between the kits, but then
>> you say that -AC doesn't bring new software interfaces. What is the
>> difference then between monako-evk and the -ac variant?
>>
>
> The major difference between monaco-evk and monaco-ac-evk boards is that
> of power grid. monaco-evk requires 4 PMICs (2x PM8650AU + Maxim MAX20018
> + TI TPS6594) to support higher power requirements of monaco-AA variant
> of SoC which supports upto 40 TOPS of NPU - whereas this board
> "monaco-ac-evk" supports 20 TOPS of NPU and has lesser power
> requirements hence 2 PMICs suffice the power requirements (2x PM8650AU).
>
>
>> Also, from the naming point of view, it is monako-ac-evk, not the other
>> way.
>
> Ack, will change this to "monaco-ac-evk" in the next version.
>
> Also, should I change DT name "monaco-ac-evk.dts" instead of current
> "monaco-evk-ac-sku" ?
Corrected Typo - I meant change DT name to "monaco-ac-evk.dts" and drop
"sku" from the DT name as well ?
>
>>
>>>
>>>>
>>>>>
>>>>> Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
>>>>> ---
>>>>> Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
>>>>> 1 file changed, 1 insertion(+)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>>> index ca880c105f3b..c76365a89687 100644
>>>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>>>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>>> @@ -918,6 +918,7 @@ properties:
>>>>> - enum:
>>>>> - arduino,monza
>>>>> - qcom,monaco-evk
>>>>> + - qcom,monaco-evk-ac
>>>>> - qcom,qcs8300-ride
>>>>> - const: qcom,qcs8300
>>>>>
>>>>>
>>>>> --
>>>>> 2.34.1
>>>>>
>>>>
>>>
>>> Thanks,
>>> Umang
>>
>
> Thanks,
> Umang
Thanks,
Umang
>
>
^ permalink raw reply
* Re: [PATCH] ASoC: dt-bindings: rockchip: Convert rk3399-gru-sound to YAML
From: Krzysztof Kozlowski @ 2026-04-04 11:11 UTC (permalink / raw)
To: Anushka Badhe
Cc: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, linux-sound, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <20260402055635.8798-1-anushkabadhe@gmail.com>
On Thu, Apr 02, 2026 at 11:26:35AM +0530, Anushka Badhe wrote:
> Convert the rockchip,rk3399-gru-sound.txt DT binding to YAML Schema.
DT Schema, not YAML Schema.
Same in subject.
https://elixir.bootlin.com/linux/v6.17-rc3/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
...
> +---
> +$id: http://devicetree.org/schemas/sound/rockchip,rk3399-gru-sound.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ROCKCHIP with MAX98357A/RT5514/DA7219 codecs on GRU boards
Rockchip
> +
> +maintainers:
> + - Heiko Stuebner <heiko@sntech.de>
> +
> +properties:
> + compatible:
> + const: rockchip,rk3399-gru-sound
> +
> + rockchip,cpu:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
Need to list items. See msm/gpu.yaml,
allwinner,sun4i-a10-display-engine.yaml and others.
And read the driver code to understand what is supposed to be here.
> + description:
> + The phandle of the Rockchip I2S controller that's connected to the codecs
> +
> + rockchip,codec:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
Same here.
> + description: The phandle of the audio codecs
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 3/7] dt-bindings: net: wireless: ath11k: Document WCN6755 WiFi
From: Krzysztof Kozlowski @ 2026-04-04 11:03 UTC (permalink / raw)
To: Luca Weiss
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Koskovich, Liam Girdwood, Mark Brown,
Bartosz Golaszewski, Marcel Holtmann, Luiz Augusto von Dentz,
Balakrishna Godavarthi, Rocky Liao, Johannes Berg, Jeff Johnson,
~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, devicetree, linux-bluetooth, linux-wireless, ath11k
In-Reply-To: <20260403-milos-fp6-bt-wifi-v2-3-393322b27c5f@fairphone.com>
On Fri, Apr 03, 2026 at 03:52:49PM +0200, Luca Weiss wrote:
> Document the WCN6755 WiFi using a fallback to WCN6750 since the two
> chips seem to be completely pin and software compatible. In fact the
> original downstream kernel just pretends the WCN6755 is a WCN6750.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> .../devicetree/bindings/net/wireless/qcom,ath11k.yaml | 16 +++++++++++-----
> 1 file changed, 11 insertions(+), 5 deletions(-)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 2/7] dt-bindings: bluetooth: qcom,wcn6750-bt: Document WCN6755 Bluetooth
From: Krzysztof Kozlowski @ 2026-04-04 10:58 UTC (permalink / raw)
To: Luca Weiss
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Koskovich, Liam Girdwood, Mark Brown,
Bartosz Golaszewski, Marcel Holtmann, Luiz Augusto von Dentz,
Balakrishna Godavarthi, Rocky Liao, Johannes Berg, Jeff Johnson,
~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, devicetree, linux-bluetooth, linux-wireless, ath11k
In-Reply-To: <20260403-milos-fp6-bt-wifi-v2-2-393322b27c5f@fairphone.com>
On Fri, Apr 03, 2026 at 03:52:48PM +0200, Luca Weiss wrote:
> Document the WCN6755 Bluetooth using a fallback to WCN6750 since the two
> chips seem to be completely pin and software compatible. In fact the
> original downstream kernel just pretends the WCN6755 is a WCN6750.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> .../devicetree/bindings/net/bluetooth/qcom,wcn6750-bt.yaml | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 1/7] regulator: dt-bindings: qcom,qca6390-pmu: Document WCN6755 PMU
From: Krzysztof Kozlowski @ 2026-04-04 10:57 UTC (permalink / raw)
To: Luca Weiss
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Koskovich, Liam Girdwood, Mark Brown,
Bartosz Golaszewski, Marcel Holtmann, Luiz Augusto von Dentz,
Balakrishna Godavarthi, Rocky Liao, Johannes Berg, Jeff Johnson,
~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, devicetree, linux-bluetooth, linux-wireless, ath11k
In-Reply-To: <20260403-milos-fp6-bt-wifi-v2-1-393322b27c5f@fairphone.com>
On Fri, Apr 03, 2026 at 03:52:47PM +0200, Luca Weiss wrote:
> Document the WCN6755 PMU using a fallback to WCN6750 since the two chips
> seem to be completely pin and software compatible. In fact the original
> downstream kernel just pretends the WCN6755 is a WCN6750.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> .../devicetree/bindings/regulator/qcom,qca6390-pmu.yaml | 16 +++++++++++-----
> 1 file changed, 11 insertions(+), 5 deletions(-)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 1/3] dt-bindings: clock: qcom: document the Milos GX clock controller
From: Krzysztof Kozlowski @ 2026-04-04 10:54 UTC (permalink / raw)
To: Luca Weiss
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Alexander Koskovich, ~postmarketos/upstreaming, phone-devel,
linux-arm-msm, linux-clk, devicetree, linux-kernel
In-Reply-To: <20260403-milos-gxclkctl-v2-1-95eb94a7d0a4@fairphone.com>
On Fri, Apr 03, 2026 at 02:03:46PM +0200, Luca Weiss wrote:
> + power-domains:
> + description:
> + Power domains required for the clock controller to operate
> + items:
> + - description: GFX power domain
> + - description: GPUCC(CX) power domain
> +
> + '#power-domain-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - power-domains
> + - '#power-domain-cells'
> +
> +unevaluatedProperties: false
additionalProperties instead. I will fix the other file.
With this:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH] dt-bindings: clock: qcom,kaanapali-gxclkctl: Correctly use additionalProperties
From: Krzysztof Kozlowski @ 2026-04-04 10:54 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Taniya Das, linux-arm-msm,
linux-clk, devicetree, linux-kernel
Cc: Krzysztof Kozlowski
The binding does not reference any other schema, thus should use
"additionalProperties: false" to disallow any undocumented properties.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
.../devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml
index 466c884aa2ba..e868963f659b 100644
--- a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml
@@ -44,7 +44,7 @@ required:
- power-domains
- '#power-domain-cells'
-unevaluatedProperties: false
+additionalProperties: false
examples:
- |
--
2.51.0
^ permalink raw reply related
* Re: [PATCH v2] dt-bindings: arm-smmu: qcom: Add compatible for Hawi SoC
From: Krzysztof Kozlowski @ 2026-04-04 10:50 UTC (permalink / raw)
To: Mukesh Ojha
Cc: Will Deacon, Joerg Roedel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Robin Murphy, linux-arm-kernel, iommu, devicetree,
linux-kernel
In-Reply-To: <20260403080956.2714415-1-mukesh.ojha@oss.qualcomm.com>
On Fri, Apr 03, 2026 at 01:39:56PM +0530, Mukesh Ojha wrote:
> Qualcomm Hawi SoC include apps smmu that implements arm,mmu-500, which
> is used to translate device-visible virtual addresses to physical
> addresses. Add compatible for these items.
>
> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 5/5] arm64: dts: qcom: sdm845-mezzanine: Fix camss ports unit_address_vs_reg warning
From: David Heidelberg @ 2026-04-04 10:49 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Konrad Dybcio, linux-arm-msm, devicetree, linux-kernel,
Conor Dooley, Dmitry Baryshkov, Abel Vesa, Krzysztof Kozlowski,
Pankaj Patil, Taniya Das, Wesley Cheng, Qiang Yu, Maulik Shah,
Varadarajan Narayanan, Raviteja Laggyshetty, Kamal Wadhwa,
Konrad Dybcio, Jishnu Prakash, Bryan O'Donoghue,
Dmitry Baryshkov, Jyothi Kumar Seerapu, Rob Herring,
Bjorn Andersson
In-Reply-To: <20260404-dts-qcom-w-1-fixes-v1-5-b8a9e6806e0a@oss.qualcomm.com>
On 04/04/2026 11:51, Krzysztof Kozlowski wrote:
> Add necessary properties for ports node in SDM845 DB845c Navigation
> mezzanine overlay to fix W=1 DTC warning:
>
> sdm845-db845c-navigation-mezzanine.dtso:19.10-24.5: Warning (unit_address_vs_reg): /fragment@0/__overlay__/ports/port@0: node has a unit name, but no reg or ranges property
>
> Fixes: 30df676a31b7 ("arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Convert mezzanine riser to dtso")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso
> index dbe1911d8e47..678a17c805f7 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso
> +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso
> @@ -16,7 +16,12 @@ &camss {
> status = "okay";
>
> ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> port@0 {
> + reg = <0>;
> +
> csiphy0_ep: endpoint {
> data-lanes = <0 1 2 3>;
> remote-endpoint = <&ov8856_ep>;
>
Reviewed-by: David Heidelberg <david@ixit.cz>
--
David Heidelberg
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: arm: qcom: Add monaco-evk-ac support
From: Umang Chheda @ 2026-04-04 10:45 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Richard Cochran, linux-arm-msm, devicetree,
linux-kernel, netdev
In-Reply-To: <zyarcaimg67uivssnm4uxqiwc2jadolf5kx6moycwlbzhg4gmv@xa75wcpotzpr>
On 4/4/2026 1:58 AM, Dmitry Baryshkov wrote:
> On Fri, Apr 03, 2026 at 04:14:28PM +0530, Umang Chheda wrote:
>> Hello Dmitry,
>>
>> On 4/1/2026 5:06 PM, Dmitry Baryshkov wrote:
>>> On Wed, Apr 01, 2026 at 12:14:42AM +0530, Umang Chheda wrote:
>>>> Introduce bindings for the monaco-evk-ac IoT board, which is
>>>> based on the monaco-ac (QCS8300-AC) SoC variant.
>>>
>>> If it is a different SoC SKU, should it be reflected in the SoC compat
>>> strings?
>>
>> Monaco‑AC does not introduce any S/W differences compared to Monaco SoC
>> -- All IP blocks and bindings remain identical from S/W PoV, Hence
>> haven't included the SoC SKU in the SoC compat strings.
>>
>> Hope this is okay ? Your view on this ?
>
> You are descibing -AC as the main difference between the kits, but then
> you say that -AC doesn't bring new software interfaces. What is the
> difference then between monako-evk and the -ac variant?
>
The major difference between monaco-evk and monaco-ac-evk boards is that
of power grid. monaco-evk requires 4 PMICs (2x PM8650AU + Maxim MAX20018
+ TI TPS6594) to support higher power requirements of monaco-AA variant
of SoC which supports upto 40 TOPS of NPU - whereas this board
"monaco-ac-evk" supports 20 TOPS of NPU and has lesser power
requirements hence 2 PMICs suffice the power requirements (2x PM8650AU).
> Also, from the naming point of view, it is monako-ac-evk, not the other
> way.
Ack, will change this to "monaco-ac-evk" in the next version.
Also, should I change DT name "monaco-ac-sku.dts" instead of current
"monaco-evk-ac-sku" ?
>
>>
>>>
>>>>
>>>> Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
>>>> ---
>>>> Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
>>>> 1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> index ca880c105f3b..c76365a89687 100644
>>>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>>>> @@ -918,6 +918,7 @@ properties:
>>>> - enum:
>>>> - arduino,monza
>>>> - qcom,monaco-evk
>>>> + - qcom,monaco-evk-ac
>>>> - qcom,qcs8300-ride
>>>> - const: qcom,qcs8300
>>>>
>>>>
>>>> --
>>>> 2.34.1
>>>>
>>>
>>
>> Thanks,
>> Umang
>
Thanks,
Umang
^ permalink raw reply
* Re: (subset) [PATCH v8 0/5] Add i.MX943 PCIe supports
From: Manivannan Sadhasivam @ 2026-04-04 10:42 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, s.hauer, kernel, festevam, Richard Zhu
Cc: linux-pci, linux-arm-kernel, devicetree, imx, linux-kernel
In-Reply-To: <20260324023036.784466-1-hongxing.zhu@nxp.com>
On Tue, 24 Mar 2026 10:30:31 +0800, Richard Zhu wrote:
> This patch-set adds i.MX943 PCIe supports on EVK board. Please pay
> attention to that it relies on the patch-set[1], and the PCIe1 port on
> the EVK board relies on the [2].
>
> Both of them are included in the v7.0 kernel.
> [1] https://lore.kernel.org/imx/176649331066.523506.9443864112044699350.b4-ty@kernel.org/
> [2] https://lore.kernel.org/imx/inzg46tc2fwsajxq4vzdyuiq7krzy6xtcg2mjaieninz7zsmgm@mtdjr4tuegpq/
>
> [...]
Applied, thanks!
[1/5] dt-bindings: PCI: imx6q-pcie: Change maxItems of clocks and clock-names to 6
commit: 401359ef44af43b6b775dc01bb7b31396db67aab
[2/5] dt-bindings: PCI: imx6q-pcie: Add i.MX94 and i.MX943 PCIe compatible strings
commit: 4d7937d8cc32b027a14cb8152d9df64d17e9392c
Best regards,
--
Manivannan Sadhasivam <mani@kernel.org>
^ permalink raw reply
* Re: [PATCH v3 1/5] dt-bindings: nfc: nxp,nci: Document PN557 compatible
From: Krzysztof Kozlowski @ 2026-04-04 10:35 UTC (permalink / raw)
To: David Heidelberg
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Martinz, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Casey Connolly,
Alexander Martinz, Petr Hodina, biemster, netdev, linux-arm-msm,
oe-linux-nfc, devicetree, linux-kernel, phone-devel
In-Reply-To: <20260403-oneplus-nfc-v3-1-fbdce57d63c1@ixit.cz>
On Fri, Apr 03, 2026 at 03:58:46PM +0200, David Heidelberg wrote:
> The PN557 uses the same hardware as the PN553 but ships with
> firmware compliant with NCI 2.0.
>
> Document PN557 as a compatible device.
>
> Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 5/5] arm64: dts: qcom: sdm845-mezzanine: Fix camss ports unit_address_vs_reg warning
From: Krzysztof Kozlowski @ 2026-04-04 9:51 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Abel Vesa, Wesley Cheng,
Maulik Shah, Qiang Yu, Taniya Das, Pankaj Patil,
Jyothi Kumar Seerapu, Dmitry Baryshkov, Varadarajan Narayanan,
Bryan O'Donoghue
Cc: Konrad Dybcio, linux-arm-msm, devicetree, linux-kernel,
Raviteja Laggyshetty, Kamal Wadhwa, Jishnu Prakash,
Krzysztof Kozlowski
In-Reply-To: <20260404-dts-qcom-w-1-fixes-v1-0-b8a9e6806e0a@oss.qualcomm.com>
Add necessary properties for ports node in SDM845 DB845c Navigation
mezzanine overlay to fix W=1 DTC warning:
sdm845-db845c-navigation-mezzanine.dtso:19.10-24.5: Warning (unit_address_vs_reg): /fragment@0/__overlay__/ports/port@0: node has a unit name, but no reg or ranges property
Fixes: 30df676a31b7 ("arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Convert mezzanine riser to dtso")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso
index dbe1911d8e47..678a17c805f7 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso
@@ -16,7 +16,12 @@ &camss {
status = "okay";
ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
port@0 {
+ reg = <0>;
+
csiphy0_ep: endpoint {
data-lanes = <0 1 2 3>;
remote-endpoint = <&ov8856_ep>;
--
2.51.0
^ permalink raw reply related
* [PATCH 4/5] arm64: dts: qcom: sc8180x: Fix phy simple_bus_reg warning
From: Krzysztof Kozlowski @ 2026-04-04 9:51 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Abel Vesa, Wesley Cheng,
Maulik Shah, Qiang Yu, Taniya Das, Pankaj Patil,
Jyothi Kumar Seerapu, Dmitry Baryshkov, Varadarajan Narayanan,
Bryan O'Donoghue
Cc: Konrad Dybcio, linux-arm-msm, devicetree, linux-kernel,
Raviteja Laggyshetty, Kamal Wadhwa, Jishnu Prakash,
Krzysztof Kozlowski
In-Reply-To: <20260404-dts-qcom-w-1-fixes-v1-0-b8a9e6806e0a@oss.qualcomm.com>
Correct the unit address of phy node in Qualcomm SC8180x SoC DTSI to fix
W=1 DTC warning:
sc8180x.dtsi:2650.31-2695.5: Warning (simple_bus_reg): /soc@0/phy@88ee000: simple-bus unit address format error, expected "88ed000"
Fixes: 35e3a9c1afce ("arm64: dts: qcom: sc8180x: switch USB+DP QMP PHYs to new bindings")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index f45deb188c6c..e87e82fa73e9 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -2647,7 +2647,7 @@ usb_mp_qmpphy1: phy@88ec000 {
status = "disabled";
};
- usb_sec_qmpphy: phy@88ee000 {
+ usb_sec_qmpphy: phy@88ed000 {
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
reg = <0 0x088ed000 0 0x3000>;
--
2.51.0
^ permalink raw reply related
* [PATCH 3/5] arm64: dts: qcom: glymur: Fix USB simple_bus_reg warnings
From: Krzysztof Kozlowski @ 2026-04-04 9:51 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Abel Vesa, Wesley Cheng,
Maulik Shah, Qiang Yu, Taniya Das, Pankaj Patil,
Jyothi Kumar Seerapu, Dmitry Baryshkov, Varadarajan Narayanan,
Bryan O'Donoghue
Cc: Konrad Dybcio, linux-arm-msm, devicetree, linux-kernel,
Raviteja Laggyshetty, Kamal Wadhwa, Jishnu Prakash,
Krzysztof Kozlowski
In-Reply-To: <20260404-dts-qcom-w-1-fixes-v1-0-b8a9e6806e0a@oss.qualcomm.com>
Correct the unit address of USB nodes in Qualcomm IPQ5424 SoC DTSI to
fix W=1 DTC warnings:
ipq5424.dtsi:642.22-693.5: Warning (simple_bus_reg): /soc@0/usb2@1e00000: simple-bus unit address format error, expected "1ef8800"
ipq5424.dtsi:733.22-786.5: Warning (simple_bus_reg): /soc@0/usb3@8a00000: simple-bus unit address format error, expected "8af8800"
Fixes: 113d52bdc820 ("arm64: dts: qcom: ipq5424: Add USB controller and phy nodes")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index f20cda429094..876bf6a8b8ff 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -639,7 +639,7 @@ qusb_phy_1: phy@71000 {
status = "disabled";
};
- usb2: usb2@1e00000 {
+ usb2: usb2@1ef8800 {
compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
reg = <0 0x01ef8800 0 0x400>;
#address-cells = <2>;
@@ -730,7 +730,7 @@ ssphy_0: phy@7d000 {
status = "disabled";
};
- usb3: usb3@8a00000 {
+ usb3: usb3@8af8800 {
compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
reg = <0 0x08af8800 0 0x400>;
--
2.51.0
^ permalink raw reply related
* [PATCH 2/5] arm64: dts: qcom: glymur: Fix cache and SRAM simple_bus_reg warnings
From: Krzysztof Kozlowski @ 2026-04-04 9:51 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Abel Vesa, Wesley Cheng,
Maulik Shah, Qiang Yu, Taniya Das, Pankaj Patil,
Jyothi Kumar Seerapu, Dmitry Baryshkov, Varadarajan Narayanan,
Bryan O'Donoghue
Cc: Konrad Dybcio, linux-arm-msm, devicetree, linux-kernel,
Raviteja Laggyshetty, Kamal Wadhwa, Jishnu Prakash,
Krzysztof Kozlowski
In-Reply-To: <20260404-dts-qcom-w-1-fixes-v1-0-b8a9e6806e0a@oss.qualcomm.com>
Correct the unit address of cache controller and SRAM nodes in Qualcomm
Glymur SoC DTSI to fix W=1 DTC warnings:
glymur.dtsi:5876.36-5908.5: Warning (simple_bus_reg): /soc@0/system-cache-controller@20400000: simple-bus unit address format error, expected "21800000"
glymur.dtsi:5917.23-5934.5: Warning (simple_bus_reg): /soc@0/sram@81e08000: simple-bus unit address format error, expected "81e08600"
Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 3389103408b6..0c5cb8532b20 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -5873,7 +5873,7 @@ oobm_ss_noc: interconnect@1f300000 {
#interconnect-cells = <2>;
};
- system-cache-controller@20400000 {
+ system-cache-controller@21800000 {
compatible = "qcom,glymur-llcc";
reg = <0x0 0x21800000 0x0 0x100000>,
<0x0 0x21a00000 0x0 0x100000>,
@@ -5914,7 +5914,7 @@ nsp_noc: interconnect@320c0000 {
#interconnect-cells = <2>;
};
- imem: sram@81e08000 {
+ imem: sram@81e08600 {
compatible = "mmio-sram";
reg = <0x0 0x81e08600 0x0 0x300>;
--
2.51.0
^ permalink raw reply related
* [PATCH 1/5] arm64: dts: qcom: glymur: Fix USB simple_bus_reg warning
From: Krzysztof Kozlowski @ 2026-04-04 9:51 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Abel Vesa, Wesley Cheng,
Maulik Shah, Qiang Yu, Taniya Das, Pankaj Patil,
Jyothi Kumar Seerapu, Dmitry Baryshkov, Varadarajan Narayanan,
Bryan O'Donoghue
Cc: Konrad Dybcio, linux-arm-msm, devicetree, linux-kernel,
Raviteja Laggyshetty, Kamal Wadhwa, Jishnu Prakash,
Krzysztof Kozlowski
In-Reply-To: <20260404-dts-qcom-w-1-fixes-v1-0-b8a9e6806e0a@oss.qualcomm.com>
Correct the unit address of USB node in Qualcomm Glymur SoC DTSI to fix
W=1 DTC warning:
glymur.dtsi:4027.23-4093.5: Warning (simple_bus_reg): /soc@0/usb@a2f8800: simple-bus unit address format error, expected "a200000"
Fixes: 4eee57dd4df9 ("arm64: dts: qcom: glymur: Add USB related nodes")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index f23cf81ddb77..3389103408b6 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -4024,7 +4024,7 @@ usb_2_dwc3_ss: endpoint {
};
};
- usb_hs: usb@a2f8800 {
+ usb_hs: usb@a200000 {
compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3";
reg = <0x0 0x0a200000 0x0 0xfc100>;
--
2.51.0
^ permalink raw reply related
* [PATCH 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
From: Joe Sandom via B4 Relay @ 2026-04-04 9:50 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom
In-Reply-To: <20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com>
From: Joe Sandom <jsandom@axon.com>
The RB5gen2 is an embedded development platform for the
QCS8550, based on the Snapdragon 8 Gen 2 SoC (SM8550).
This change implements the main board, the vision mezzanine
will be supported in a follow up patch.
The main board has the following features:
- Qualcomm Dragonwing QCS8550 SoC
- Adreno GPU 740
- Spectra ISP
- Adreno VPU 8550
- Adreno DPU 1295
- 1 x 1GbE Ethernet (USB Ethernet)
- WIFI 7 + Bluetooth 5.4
- 1 x USB 2.0 Micro B (Debug)
- 1 x USB 3.0 Type C (ADB, DP out)
- 2 x USB 3.0 Type A
- 1 x HDMI 1.4 Type A
- 1 x DP 1.4 Type C
- 2 x WSA8845 Speaker amplifiers
- 2 x Speaker connectors
- 1 x On Board PDM MIC
- Accelerometer + Gyro Sensor
- 96Boards compatible low-speed and high-speed connectors [1]
- 7 x LED indicators (4 user, 2 radio, 1 power)
- Buttons for power, volume up/down, force USB boot
- 3 x Dip switches
On-Board PMICs:
- PMK8550 2.1
- PM8550 2.0
- PM8550VS 2.0 x4
- PM8550VE 2.0
- PM8550B 2.0
- PMR735D 2.0
- PM8010 1.1 x2
Product Page: [2]
[1] https://www.96boards.org/specifications/
[2] https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 1610 ++++++++++++++++++++++++++
2 files changed, 1611 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 4ba8e73064194926096b98b9556a3207e8f24d72..f8c65771f76629d7fafee15ac8d7bb62cd24a20f 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -184,6 +184,7 @@ qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-rb5gen2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
new file mode 100644
index 0000000000000000000000000000000000000000..280fbd3a09997e3e2613498e25ac188680484cc4
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
@@ -0,0 +1,1610 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2026 Axon Enterprise, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "qcs8550.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+#include "pmr735d_a.dtsi"
+#include "pmr735d_b.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCS8550 RB5Gen2";
+ compatible = "qcom,qcs8550-rb5gen2", "qcom,qcs8550", "qcom,sm8550";
+ chassis-type = "embedded";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ clk40m: can-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
+ /* Lontium LT9611UXC fails FW upgrade and has timeouts with geni-i2c */
+ /* Workaround is to use bit-banged I2C */
+ i2c_hub_3_gpio: i2c {
+ compatible = "i2c-gpio";
+
+ sda-gpios = <&tlmm 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&tlmm 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "green:status-3";
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pm8550_gpios 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-1 {
+ label = "blue:bt-power";
+ function = LED_FUNCTION_BLUETOOTH;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pm8550b_gpios 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ default-state = "off";
+ };
+
+ led-2 {
+ label = "yellow:wlan";
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_YELLOW>;
+ gpios = <&pm8550b_gpios 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+ };
+
+ lt9611_1v2: lt9611-regulator-1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_1V2";
+
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ vin-supply = <&vreg_l14b_3p2>;
+ };
+
+ lt9611_3v3: lt9611-regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_3V3";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ vin-supply = <&vreg_l14b_3p2>;
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&redriver_usb_con_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu_in: endpoint {
+ remote-endpoint = <&redriver_usb_con_sbu>;
+ };
+ };
+ };
+ };
+ };
+
+ pcie_upd_1p05: regulator-pcie-upd-1p05 {
+ compatible = "regulator-fixed";
+ regulator-name = "PCIE_UPD_1P05";
+ gpio = <&tlmm 179 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vdd_ntn_0p9>;
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ enable-active-high;
+ regulator-enable-ramp-delay = <5000>;
+ pinctrl-0 = <&upd_1p05_en>;
+ pinctrl-names = "default";
+ };
+
+ pcie_upd_3p3: regulator-pcie-upd-3p3 {
+ compatible = "regulator-fixed";
+ regulator-name = "PCIE_UPD_3P3";
+ gpio = <&tlmm 13 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&pcie_upd_1p05>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-enable-ramp-delay = <10000>;
+ pinctrl-0 = <&upd_3p3_en>;
+ pinctrl-names = "default";
+ };
+
+ upd_reset: regulator-upd-reset {
+ compatible = "regulator-fixed";
+ regulator-name = "UPD_RESET";
+ gpio = <&tlmm 182 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&pcie_upd_3p3>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-enable-ramp-delay = <10000>;
+ regulator-boot-on;
+ regulator-always-on;
+ pinctrl-0 = <&upd_ponrst>;
+ pinctrl-names = "default";
+ };
+
+ usbhub_reset: regulator-usbhub-reset {
+ compatible = "regulator-fixed";
+ regulator-name = "USBHUB_RESET";
+ gpio = <&tlmm 41 GPIO_ACTIVE_LOW>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ startup-delay-us = <1500>;
+ off-on-delay-us = <1500>;
+ pinctrl-0 = <&usbhub_rst>;
+ pinctrl-names = "default";
+ };
+
+ vdd_ntn_0p9: regulator-vdd-ntn-0p9 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN_0P9";
+ vin-supply = <&vdd_ntn_1p8>;
+ regulator-min-microvolt = <899400>;
+ regulator-max-microvolt = <899400>;
+ regulator-enable-ramp-delay = <4300>;
+ };
+
+ vdd_ntn_1p8: regulator-vdd-ntn-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN_1P8";
+ gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ pinctrl-0 = <&ntn0_en>;
+ pinctrl-names = "default";
+ regulator-enable-ramp-delay = <10000>;
+ };
+
+ vdd_ntn1_0p9: regulator-vdd-ntn1-0p9 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN1_0P9";
+ vin-supply = <&vdd_ntn1_1p8>;
+ regulator-min-microvolt = <899400>;
+ regulator-max-microvolt = <899400>;
+ regulator-enable-ramp-delay = <4300>;
+ };
+
+ vdd_ntn1_1p8: regulator-vdd-ntn1-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN1_1P8";
+ gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ pinctrl-0 = <&ntn1_en>;
+ pinctrl-names = "default";
+ regulator-enable-ramp-delay = <10000>;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sound {
+ compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
+ model = "QCS8550-RB5Gen2";
+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA DMIC0", "vdd-micb",
+ "VA DMIC1", "vdd-micb";
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&left_spkr>, <&right_spkr>,
+ <&swr0 0>, <&lpass_wsamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ va-dai-link {
+ link-name = "VA Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+ };
+
+ codec {
+ sound-dai = <&lpass_vamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
+ wcn7850-pmu {
+ compatible = "qcom,wcn7850-pmu";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_en>, <&bt_default>, <&pmk8550_sleep_clk>;
+
+ wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
+ bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <&vreg_s5g_0p85>;
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddaon-supply = <&vreg_s2g_0p852>;
+ vdddig-supply = <&vreg_s4e_0p95>;
+ vddrfa1p2-supply = <&vreg_s4g_1p25>;
+ vddrfa1p8-supply = <&vreg_s6g_1p86>;
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p8: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p8";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s4g_1p25>;
+ vdd-l12-supply = <&vreg_s6g_1p86>;
+ vdd-l15-supply = <&vreg_s6g_1p86>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1760000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_l3c_0p9: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <835000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <958000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2d_0p752: ldo2 {
+ regulator-name = "vreg_l2d_0p752";
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <808000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4d_0p628: smps4 {
+ regulator-name = "vreg_s4d_0p628";
+ regulator-min-microvolt = <572000>;
+ regulator-max-microvolt = <988000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5d_0p728: smps5 {
+ regulator-name = "vreg_s5d_0p728";
+ regulator-min-microvolt = <572000>;
+ regulator-max-microvolt = <988000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <831000>;
+ regulator-max-microvolt = <904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s1e_0p72: smps1 {
+ regulator-name = "vreg_s1e_0p72";
+ regulator-min-microvolt = <532000>;
+ regulator-max-microvolt = <852000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3e_0p75: smps3 {
+ regulator-name = "vreg_s3e_0p75";
+ regulator-min-microvolt = <716000>;
+ regulator-max-microvolt = <884000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4e_0p95: smps4 {
+ regulator-name = "vreg_s4e_0p95";
+ regulator-min-microvolt = <870100>;
+ regulator-max-microvolt = <1152000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p08: smps5 {
+ regulator-name = "vreg_s5e_1p08";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6e_0p728: smps6 {
+ regulator-name = "vreg_s6e_0p728";
+ regulator-min-microvolt = <528000>;
+ regulator-max-microvolt = <904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <866000>;
+ regulator-max-microvolt = <958000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <866000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p88: ldo3 {
+ regulator-name = "vreg_l3f_0p88";
+ regulator-min-microvolt = <830000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s1f_0p728: smps1 {
+ regulator-name = "vreg_s1f_0p728";
+ regulator-min-microvolt = <516000>;
+ regulator-max-microvolt = <904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3f_0p852: smps3 {
+ regulator-name = "vreg_s3f_0p852";
+ regulator-min-microvolt = <688000>;
+ regulator-max-microvolt = <952000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <500000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5f_0p752: smps5 {
+ regulator-name = "vreg_s5f_0p752";
+ regulator-min-microvolt = <716000>;
+ regulator-max-microvolt = <884000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s7f_0p628: smps7 {
+ regulator-name = "vreg_s7f_0p628";
+ regulator-min-microvolt = <516000>;
+ regulator-max-microvolt = <812000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "g";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s1g_1p256: smps1 {
+ regulator-name = "vreg_s1g_1p256";
+ regulator-min-microvolt = <1172000>;
+ regulator-max-microvolt = <1388000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p852: smps2 {
+ regulator-name = "vreg_s2g_0p852";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1053200>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p752: smps3 {
+ regulator-name = "vreg_s3g_0p752";
+ regulator-min-microvolt = <532000>;
+ regulator-max-microvolt = <1148000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p25: smps4 {
+ regulator-name = "vreg_s4g_1p25";
+ regulator-min-microvolt = <1172000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5g_0p85: smps5 {
+ regulator-name = "vreg_s5g_0p85";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1002600>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p86: smps6 {
+ regulator-name = "vreg_s6g_1p86";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2192000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ vdd-l1-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6g_1p86>;
+ vdd-l6-supply = <&vreg_s6g_1p86>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ qcom,pmic-id = "m";
+
+ vreg_l1m_1p056: ldo1 {
+ regulator-name = "vreg_l1m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_1p8: ldo6 {
+ regulator-name = "vreg_l6m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p9: ldo7 {
+ regulator-name = "vreg_l7m_2p9";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ vdd-l1-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6g_1p86>;
+ vdd-l6-supply = <&vreg_bob1>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ qcom,pmic-id = "n";
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p1: ldo2 {
+ regulator-name = "vreg_l2n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_2p8: ldo3 {
+ regulator-name = "vreg_l3n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_2p8: ldo4 {
+ regulator-name = "vreg_l4n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_1p8: ldo5 {
+ regulator-name = "vreg_l5n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_3p3: ldo6 {
+ regulator-name = "vreg_l6n_3p3";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_2p96: ldo7 {
+ regulator-name = "vreg_l7n_2p96";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpi_dma2 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/qcs8550/a740_zap.mbn";
+};
+
+&i2c_hub_2 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+
+ typec-mux@1c {
+ compatible = "onnn,nb7vpq904m";
+ reg = <0x1c>;
+
+ vcc-supply = <&vreg_l15b_1p8>;
+
+ retimer-switch;
+ orientation-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ redriver_usb_con_ss: endpoint {
+ remote-endpoint = <&pmic_glink_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ redriver_phy_con_ss: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ redriver_usb_con_sbu: endpoint {
+ remote-endpoint = <&pmic_glink_sbu_in>;
+ };
+ };
+ };
+ };
+};
+
+&i2c_hub_3_gpio {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+
+ interrupts-extended = <&tlmm 40 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <<9611_1v2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&i2c_hub_4 {
+ status = "okay";
+};
+
+&i2c_master_hub_0 {
+ status = "okay";
+};
+
+&ipa {
+ qcom,gsi-loader = "self";
+ memory-region = <&ipa_fw_mem>;
+ firmware-name = "qcom/qcs8550/ipa_fws.mbn";
+
+ status = "okay";
+};
+
+&iris {
+ status = "okay";
+};
+
+&lpass_vamacro {
+ pinctrl-0 = <&dmic01_default>;
+ pinctrl-names = "default";
+
+ qcom,dmic-sample-rate = <4800000>;
+
+ vdd-micb-supply = <&vreg_l15b_1p8>;
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+&pcie0 {
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
+ <0x100 &apps_smmu 0x1401 0x1>,
+ <0x208 &apps_smmu 0x1402 0x1>,
+ <0x210 &apps_smmu 0x1403 0x1>,
+ <0x218 &apps_smmu 0x1404 0x1>,
+ <0x300 &apps_smmu 0x1407 0x1>,
+ <0x400 &apps_smmu 0x1408 0x1>,
+ <0x500 &apps_smmu 0x140c 0x1>,
+ <0x501 &apps_smmu 0x140e 0x1>;
+
+ /delete-property/ msi-map;
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pcie0_port0 {
+ pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x2 0xff>;
+
+ vddc-supply = <&vdd_ntn_0p9>;
+ vdd18-supply = <&vdd_ntn_1p8>;
+ vdd09-supply = <&vdd_ntn_0p9>;
+ vddio1-supply = <&vdd_ntn_1p8>;
+ vddio2-supply = <&vdd_ntn_1p8>;
+ vddio18-supply = <&vdd_ntn_1p8>;
+
+ i2c-parent = <&i2c_hub_4 0x77>;
+
+ resx-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&tc9563_0_rst>;
+ pinctrl-names = "default";
+
+ pcie@1,0 {
+ reg = <0x20800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x3 0xff>;
+ };
+
+ pcie@2,0 {
+ reg = <0x21000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x4 0xff>;
+ };
+
+ pcie@3,0 {
+ reg = <0x21800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ bus-range = <0x5 0xff>;
+
+ pci@0,0 {
+ reg = <0x50000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+
+ pci@0,1 {
+ reg = <0x50100 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+ };
+ };
+};
+
+&pcie1 {
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+
+ iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
+ <0x100 &apps_smmu 0x1481 0x1>,
+ <0x208 &apps_smmu 0x1482 0x1>,
+ <0x210 &apps_smmu 0x1483 0x1>,
+ <0x218 &apps_smmu 0x1484 0x1>,
+ <0x300 &apps_smmu 0x1487 0x1>,
+ <0x400 &apps_smmu 0x1488 0x1>,
+ <0x500 &apps_smmu 0x148c 0x1>,
+ <0x501 &apps_smmu 0x148e 0x1>;
+
+ /delete-property/ msi-map;
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l3c_0p9>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ vdda-qref-supply = <&vreg_l1e_0p88>;
+
+ status = "okay";
+};
+
+&pcie1_port0 {
+ pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x2 0xff>;
+
+ vddc-supply = <&vdd_ntn1_0p9>;
+ vdd18-supply = <&vdd_ntn1_1p8>;
+ vdd09-supply = <&vdd_ntn1_0p9>;
+ vddio1-supply = <&vdd_ntn1_1p8>;
+ vddio2-supply = <&vdd_ntn1_1p8>;
+ vddio18-supply = <&vdd_ntn1_1p8>;
+
+ i2c-parent = <&i2c_hub_3_gpio 0x77>;
+
+ resx-gpios = <&tlmm 65 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&tc9563_1_rst>;
+ pinctrl-names = "default";
+
+ pcie@1,0 {
+ reg = <0x20800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x3 0xff>;
+ };
+
+ pcie@2,0 {
+ reg = <0x21000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x4 0xff>;
+
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x40000 0x0 0x0 0x0 0x0>;
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+ };
+
+ pcie@3,0 {
+ reg = <0x21800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ bus-range = <0x5 0xff>;
+ };
+ };
+};
+
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+
+ sdc2_card_det_n: sdc2-card-det-state {
+ pins = "gpio12";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pm8550_pwm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <0>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <2>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pmk8550_gpios {
+ pmk8550_sleep_clk: sleep-clk-state {
+ pins = "gpio3";
+ function = "func1";
+ input-disable;
+ output-enable;
+ bias-disable;
+ power-source = <0>;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/qcs8550/adsp.mdt",
+ "qcom/qcs8550/adsp_dtb.mdt";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/qcs8550/cdsp.mdt",
+ "qcom/qcs8550/cdsp_dtb.mdt";
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/qcs8550/modem.mdt",
+ "qcom/qcs8550/modem_dtb.mdt";
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+
+ max-sd-hs-hz = <37000000>;
+
+ no-sdio;
+ no-mmc;
+
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32764>;
+};
+
+&spi11 {
+ status = "okay";
+
+ can@0 {
+ compatible = "microchip,mcp2518fd";
+ reg = <0>;
+ interrupts-extended = <&tlmm 55 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk40m>;
+ spi-max-frequency = <10000000>;
+ vdd-supply = <&vreg_l14b_3p2>;
+ xceiver-supply = <&vreg_l14b_3p2>;
+ };
+};
+
+&swr0 {
+ status = "okay";
+
+ left_spkr: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrLeft";
+ qcom,port-mapping = <1 2 3 7 10 13>;
+ };
+
+ right_spkr: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrRight";
+ qcom,port-mapping = <4 5 6 7 11 13>;
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 8>;
+
+ bt_default: bt-default-state {
+ bt-en-pins {
+ pins = "gpio81";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sw-ctrl-pins {
+ pins = "gpio82";
+ function = "gpio";
+ bias-pull-down;
+ };
+ };
+
+ lt9611_irq_pin: lt9611-irq-state {
+ pins = "gpio40";
+ function = "gpio";
+ bias-disable;
+ };
+
+ lt9611_rst_pin: lt9611-rst-state {
+ pins = "gpio7";
+ function = "gpio";
+ output-high;
+ };
+
+ ntn0_en: ntn0-en-state {
+ pins = "gpio67";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ntn1_en: ntn1-en-state {
+ pins = "gpio42";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ upd_1p05_en: upd-1p05-en-state {
+ pins = "gpio179";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ upd_3p3_en: upd-3p3-en-state {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ upd_ponrst: upd-ponrst-state {
+ pins = "gpio182";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ usbhub_rst: usbhub-rst-state {
+ pins = "gpio41";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ tc9563_0_rst: tc9563-0-rst-state {
+ pins = "gpio64";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tc9563_1_rst: tc9563-1-rst-state {
+ pins = "gpio65";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wlan_en: wlan-en-state {
+ pins = "gpio80";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&uart14 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ };
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1e_0p88>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ phys = <&pm8550b_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3f_0p88>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&redriver_phy_con_ss>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
--
2.34.1
^ permalink raw reply related
* [PATCH 0/5] arm64: dts: qcom: Few dtc W=1 warning fixes
From: Krzysztof Kozlowski @ 2026-04-04 9:50 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Abel Vesa, Wesley Cheng,
Maulik Shah, Qiang Yu, Taniya Das, Pankaj Patil,
Jyothi Kumar Seerapu, Dmitry Baryshkov, Varadarajan Narayanan,
Bryan O'Donoghue
Cc: Konrad Dybcio, linux-arm-msm, devicetree, linux-kernel,
Raviteja Laggyshetty, Kamal Wadhwa, Jishnu Prakash,
Krzysztof Kozlowski
Not marking stable as these do not have actual impact on user, but still
warnings are not desired.
Best regards,
Krzysztof
---
Krzysztof Kozlowski (5):
arm64: dts: qcom: glymur: Fix USB simple_bus_reg warning
arm64: dts: qcom: glymur: Fix cache and SRAM simple_bus_reg warnings
arm64: dts: qcom: glymur: Fix USB simple_bus_reg warnings
arm64: dts: qcom: sc8180x: Fix phy simple_bus_reg warning
arm64: dts: qcom: sdm845-mezzanine: Fix camss ports unit_address_vs_reg warning
arch/arm64/boot/dts/qcom/glymur.dtsi | 6 +++---
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso | 5 +++++
4 files changed, 11 insertions(+), 6 deletions(-)
---
base-commit: 36ece9697e89016181e5ae87510e40fb31d86f2b
change-id: 20260404-dts-qcom-w-1-fixes-1a25bbd0519a
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
^ permalink raw reply
* [PATCH 4/5] dt-bindings: arm: qcom: document QCS8550 RB5Gen2 board
From: Joe Sandom via B4 Relay @ 2026-04-04 9:50 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom
In-Reply-To: <20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com>
From: Joe Sandom <jsandom@axon.com>
Document the Qualcomm RB5gen2 from Thundercomm based on the
QCS8550 chipset from Qualcomm.
[1] https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit/
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 1335a7bee397c46e8dc62806091531e32b7327d4..f9f8001e3e6b66e3a926255bdb15363f4c7c2b66 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -1093,6 +1093,12 @@ properties:
- const: qcom,qcs8550
- const: qcom,sm8550
+ - items:
+ - enum:
+ - qcom,qcs8550-rb5gen2
+ - const: qcom,qcs8550
+ - const: qcom,sm8550
+
- items:
- enum:
- ayaneo,pocket-s2
--
2.34.1
^ permalink raw reply related
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