* [PATCH RFC 2/4] arm64: dts: qcom: glymur: Add GPU smmu node
From: Akhil P Oommen @ 2026-04-04 21:03 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann
Cc: linux-arm-msm, devicetree, linux-kernel, dri-devel, freedreno,
Akhil P Oommen, Rajendra Nayak, Rajendra Nayak
In-Reply-To: <20260405-glymur-gpu-dt-v1-0-2135eb11c562@oss.qualcomm.com>
From: Rajendra Nayak <quic_rjendra@quicinc.com>
Add the nodes to describe the GPU SMMU node.
Signed-off-by: Rajendra Nayak <rajendra.nayak@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 40 ++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index e65e40857b3e..a3fe2b12aee0 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -3724,6 +3724,46 @@ gpucc: clock-controller@3d90000 {
#power-domain-cells = <1>;
};
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,glymur-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x03da0000 0x0 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>;
+ clock-names = "hlos";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+ interconnects = <&hsc_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ dma-coherent;
+ };
+
ipcc: mailbox@3e04000 {
compatible = "qcom,glymur-ipcc", "qcom,ipcc";
reg = <0x0 0x03e04000 0x0 0x1000>;
--
2.51.0
^ permalink raw reply related
* [PATCH RFC 3/4] arm64: dts: qcom: Add GPU support for Glymur
From: Akhil P Oommen @ 2026-04-04 21:03 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann
Cc: linux-arm-msm, devicetree, linux-kernel, dri-devel, freedreno,
Akhil P Oommen
In-Reply-To: <20260405-glymur-gpu-dt-v1-0-2135eb11c562@oss.qualcomm.com>
The Adreno X2 series GPU present in Glymur SoC belongs to the A8x
family. It is a new HW IP with architectural improvements as well
as different set of hw configs like GMEM, num SPs, Caches sizes etc.
Add the GPU and GMU nodes to describe this hardware.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 194 +++++++++++++++++++++++++++++++++++
1 file changed, 194 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index a3fe2b12aee0..0174917fe942 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -3712,6 +3712,200 @@ gxclkctl: clock-controller@3d64000 {
#power-domain-cells = <1>;
};
+ gpu: gpu@3d00000 {
+ compatible = "qcom,adreno-44070001", "qcom,adreno";
+ reg = <0x0 0x03d00000 0x0 0x40000>,
+ <0x0 0x03d9e000 0x0 0x2000>,
+ <0x0 0x03d61000 0x0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0 0x0>,
+ <&adreno_smmu 1 0x0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+ #cooling-cells = <2>;
+
+ interconnects = <&hsc_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "gfx-mem";
+
+ status = "disabled";
+
+ gpu_zap_shader: zap-shader {
+ status = "disabled";
+ memory-region = <&gpu_microcode_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2-adreno",
+ "operating-points-v2";
+
+ opp-310000000 {
+ opp-hz = /bits/ 64 <310000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ opp-peak-kBps = <2136719>;
+ opp-supported-hw = <0xf>;
+ /* ACD is disabled */
+ };
+
+ opp-410000000 {
+ opp-hz = /bits/ 64 <410000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <6074219>;
+ opp-supported-hw = <0xf>;
+ /* ACD is disabled */
+ };
+
+ opp-572000000 {
+ opp-hz = /bits/ 64 <572000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <12449219>;
+ opp-supported-hw = <0xf>;
+ qcom,opp-acd-level = <0xe02d5ffd>;
+ };
+
+ opp-760000000 {
+ opp-hz = /bits/ 64 <760000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <12449219>;
+ opp-supported-hw = <0xf>;
+ qcom,opp-acd-level = <0xc0285ffd>;
+ };
+
+ opp-820000000 {
+ opp-hz = /bits/ 64 <820000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-peak-kBps = <16500000>;
+ opp-supported-hw = <0xf>;
+ qcom,opp-acd-level = <0xa82e5ffd>;
+ };
+
+ opp-915000000 {
+ opp-hz = /bits/ 64 <915000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <16500000>;
+ opp-supported-hw = <0xf>;
+ qcom,opp-acd-level = <0x882d5ffd>;
+ };
+
+ opp-1070000000 {
+ opp-hz = /bits/ 64 <1070000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-peak-kBps = <16500000>;
+ opp-supported-hw = <0xf>;
+ qcom,opp-acd-level = <0x882b5ffd>;
+ };
+
+ opp-1185000000 {
+ opp-hz = /bits/ 64 <1185000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <16500000>;
+ opp-supported-hw = <0xf>;
+ qcom,opp-acd-level = <0x882a5ffd>;
+ };
+
+ opp-1350000000 {
+ opp-hz = /bits/ 64 <1350000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <18597657>;
+ opp-supported-hw = <0xf>;
+ qcom,opp-acd-level = <0x882a5ffd>;
+ };
+
+ opp-1550000000 {
+ opp-hz = /bits/ 64 <1550000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+ opp-peak-kBps = <18597657>;
+ opp-supported-hw = <0x7>;
+ qcom,opp-acd-level = <0xa8295ffd>;
+ };
+
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+ opp-peak-kBps = <18597657>;
+ opp-supported-hw = <0x7>;
+ qcom,opp-acd-level = <0x88295ffd>;
+ };
+
+ opp-1850000000 {
+ opp-hz = /bits/ 64 <1850000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
+ opp-peak-kBps = <18597657>;
+ opp-supported-hw = <0x3>;
+ qcom,opp-acd-level = <0x88285ffd>;
+ };
+ };
+ };
+
+ gmu: gmu@3d6a000 {
+ compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu";
+
+ reg = <0x0 0x03d37000 0x0 0x68000>;
+ reg-names = "gmu";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi",
+ "gmu";
+
+ clocks = <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_GPU_GEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_RSCC_HUB_AON_CLK>;
+ clock-names = "ahb",
+ "gmu",
+ "cxo",
+ "memnoc",
+ "hub",
+ "rscc";
+
+ power-domains = <&gpucc GPU_CC_CX_GDSC>,
+ <&gxclkctl GX_CLKCTL_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+
+ iommus = <&adreno_smmu 5 0x0>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ status = "disabled";
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-575000000 {
+ opp-hz = /bits/ 64 <575000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-725000000 {
+ opp-hz = /bits/ 64 <725000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-750000000 {
+ opp-hz = /bits/ 64 <750000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+ };
+ };
+
gpucc: clock-controller@3d90000 {
compatible = "qcom,glymur-gpucc";
reg = <0x0 0x03d90000 0x0 0x9800>;
--
2.51.0
^ permalink raw reply related
* [PATCH RFC 4/4] arm64: dts: qcom: Enable GPU & GMU on Glymur CRD
From: Akhil P Oommen @ 2026-04-04 21:03 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann
Cc: linux-arm-msm, devicetree, linux-kernel, dri-devel, freedreno,
Akhil P Oommen
In-Reply-To: <20260405-glymur-gpu-dt-v1-0-2135eb11c562@oss.qualcomm.com>
Enable the necessary DT nodes to add support for GPU on the Glymur CRD.
The Glymur CRD boots Linux at EL2, which means it doesn't require the
secure GPU firmware (zap fw).
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index 51ea23a49b9e..a579df902323 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -110,6 +110,14 @@ vreg_misc_3p3: regulator-misc-3p3 {
};
};
+&gpu {
+ status = "okay";
+};
+
+&gmu {
+ status = "okay";
+};
+
&i2c0 {
clock-frequency = <400000>;
--
2.51.0
^ permalink raw reply related
* Re: [PATCH v3 4/5] arm64: dts: qcom: sdm845-shift-axolotl: Enable NFC
From: Dmitry Baryshkov @ 2026-04-04 21:04 UTC (permalink / raw)
To: david
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Martinz, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Casey Connolly,
Alexander Martinz, Petr Hodina, biemster, netdev, linux-arm-msm,
oe-linux-nfc, devicetree, linux-kernel, phone-devel,
Krzysztof Kozlowski
In-Reply-To: <20260403-oneplus-nfc-v3-4-fbdce57d63c1@ixit.cz>
On Fri, Apr 03, 2026 at 03:58:49PM +0200, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
>
> Enable NFC controller NXP PN553.
>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 52 +++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v3 2/5] arm64: dts: qcom: sdm845-oneplus: Enable NFC
From: Dmitry Baryshkov @ 2026-04-04 21:05 UTC (permalink / raw)
To: david
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Martinz, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Casey Connolly,
Alexander Martinz, Petr Hodina, biemster, netdev, linux-arm-msm,
oe-linux-nfc, devicetree, linux-kernel, phone-devel,
Krzysztof Kozlowski
In-Reply-To: <20260403-oneplus-nfc-v3-2-fbdce57d63c1@ixit.cz>
On Fri, Apr 03, 2026 at 03:58:47PM +0200, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
>
> Enable NFC controller NXP PN553, which is part of the package NXP NQ330
> (NFC + eSE).
>
> Based on work of biemster <l.j.beemster@gmail.com>.
>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> .../arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 57 ++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v3 5/5] arm64: dts: qcom: sdm845-google-common: Enable NFC
From: Dmitry Baryshkov @ 2026-04-04 21:05 UTC (permalink / raw)
To: david
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alexander Martinz, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Casey Connolly,
Alexander Martinz, Petr Hodina, biemster, netdev, linux-arm-msm,
oe-linux-nfc, devicetree, linux-kernel, phone-devel,
Krzysztof Kozlowski
In-Reply-To: <20260403-oneplus-nfc-v3-5-fbdce57d63c1@ixit.cz>
On Fri, Apr 03, 2026 at 03:58:50PM +0200, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
>
> Enable NFC controller NXP PN557.
>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 31 ++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions and port labels
From: Dmitry Baryshkov @ 2026-04-04 21:07 UTC (permalink / raw)
To: jsandom
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260404-rb5gen2-dts-v1-1-895f8fc494fc@axon.com>
On Sat, Apr 04, 2026 at 10:50:54AM +0100, Joe Sandom via B4 Relay wrote:
> From: Joe Sandom <jsandom@axon.com>
>
> Add the MHI register regions to the pcie0 and pcie1 controller nodes
> so that the MHI bus layer can access controller registers directly.
>
> Also add labels to the root port nodes (pcie0_port0, pcie1_port0) to
> allow board DTS files to reference them for adding endpoint devices
> to each pcie root port.
Two separate changes, please.
>
> Signed-off-by: Joe Sandom <jsandom@axon.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 912525e9bca6f5e1cbb8887ee0bf9e39650dc4ff..d4caf4d00832d7f1e8f65bf2bc873cddadc42168 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1964,8 +1964,9 @@ pcie0: pcie@1c00000 {
> <0 0x60000000 0 0xf1d>,
> <0 0x60000f20 0 0xa8>,
> <0 0x60001000 0 0x1000>,
> - <0 0x60100000 0 0x100000>;
> - reg-names = "parf", "dbi", "elbi", "atu", "config";
> + <0 0x60100000 0 0x100000>,
> + <0 0x01C03000 0 0x1000>;
Lowercase the hex, align vertically.
> + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
> #address-cells = <3>;
> #size-cells = <2>;
> ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
> @@ -2092,7 +2093,7 @@ opp-16000000-3 {
> };
> };
>
> - pcieport0: pcie@0 {
> + pcie0_port0: pcie@0 {
> device_type = "pci";
> reg = <0x0 0x0 0x0 0x0 0x0>;
> bus-range = <0x01 0xff>;
> @@ -2138,8 +2139,9 @@ pcie1: pcie@1c08000 {
> <0x0 0x40000000 0x0 0xf1d>,
> <0x0 0x40000f20 0x0 0xa8>,
> <0x0 0x40001000 0x0 0x1000>,
> - <0x0 0x40100000 0x0 0x100000>;
> - reg-names = "parf", "dbi", "elbi", "atu", "config";
> + <0x0 0x40100000 0x0 0x100000>,
> + <0x0 0x01C0B000 0x0 0x1000>;
> + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
> #address-cells = <3>;
> #size-cells = <2>;
> ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> @@ -2288,7 +2290,7 @@ opp-32000000-4 {
> };
> };
>
> - pcie@0 {
> + pcie1_port0: pcie@0 {
> device_type = "pci";
> reg = <0x0 0x0 0x0 0x0 0x0>;
> bus-range = <0x01 0xff>;
>
> --
> 2.34.1
>
>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 2/5] arm64: dts: qcom: sm8550-hdk: update PCIe port label reference
From: Dmitry Baryshkov @ 2026-04-04 21:07 UTC (permalink / raw)
To: jsandom
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260404-rb5gen2-dts-v1-2-895f8fc494fc@axon.com>
On Sat, Apr 04, 2026 at 10:50:55AM +0100, Joe Sandom via B4 Relay wrote:
> From: Joe Sandom <jsandom@axon.com>
>
> Update the pcieport0 reference to pcie0_port0 to match the label
> rename in sm8550.dtsi.
This one (and the next one) should be squashed with the port label
rename.
>
> Signed-off-by: Joe Sandom <jsandom@axon.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> index ee13e6136a8259d28540e718851e094f74ead278..e821b731bdc496c872703723df02ae9b9b0233b5 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> @@ -1012,7 +1012,7 @@ &pcie0 {
> status = "okay";
> };
>
> -&pcieport0 {
> +&pcie0_port0 {
> wifi@0 {
> compatible = "pci17cb,1107";
> reg = <0x10000 0x0 0x0 0x0 0x0>;
>
> --
> 2.34.1
>
>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v20 2/6] pwm: driver for qualcomm ipq6018 pwm block
From: Uwe Kleine-König @ 2026-04-04 21:09 UTC (permalink / raw)
To: George Moussalem
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Baruch Siach,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, linux-pwm,
devicetree, linux-kernel, Devi Priya, Baruch Siach
In-Reply-To: <DS7PR19MB8883555F6B620250D1CB55689D5EA@DS7PR19MB8883.namprd19.prod.outlook.com>
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Hello George,
On Fri, Apr 03, 2026 at 12:40:32PM +0200, George Moussalem wrote:
> On 4/2/2026 5:35 PM, Uwe Kleine-König wrote:
> > diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c
> > index b944ecb456d5..4818d0170d53 100644
> > --- a/drivers/pwm/pwm-ipq.c
> > +++ b/drivers/pwm/pwm-ipq.c
> > @@ -97,9 +97,10 @@ static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> > if (state->polarity != PWM_POLARITY_NORMAL)
> > return -EINVAL;
> >
> > - if (!ipq_chip->clk_rate)
> > - return -EINVAL;
> > -
> > + /*
> > + * XXX Why? A comment please. (Is this already covered by the checks
> > + * below?)
> > + */
>
> This check can be safely removed as it is indeed covered by the check
> where the period_ns is limited to IPQ_PWM_MAX_PERIOD_NS which equals to
> NSEC_PER_SEC as per macro definition above.
>
> > if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC,
> > ipq_chip->clk_rate))
> > return -ERANGE;
> > @@ -107,18 +108,29 @@ static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> > period_ns = min(state->period, IPQ_PWM_MAX_PERIOD_NS);
> > duty_ns = min(state->duty_cycle, period_ns);
> >
> > + /*
> > + * Pick the maximal value for PWM_DIV that still allows a
> > + * 100% relative duty cycle. This allows a fine grained
> > + * selection of duty cycles.
> > + */
> > pwm_div = IPQ_PWM_MAX_DIV - 1;
> > +
> > + /*
> > + * XXX mul_u64_u64_div_u64 returns an u64, this might overflow the
> > + * unsigned int pre_div.
> > + */
>
> Theoretically, yes, but in practice it won't due to above constraints.
> Take the max period of 10^9 (NSEC_PER_SEC) * max clock rate of 10^9 (1
> GHz), then the numerator becomes 10^18. Divide that by 10^9
> (NSEC_PER_SEC) * 65,535 (IPQ_PWM_MAX_DIV) and that fits well into a
> 32-bit integer.
OK, please put that in a comment.
> Do you want me to send a v21 or can you apply the diff in your tree with
> above deletion and comment?
Yes, please send a v21.
Best regards
Uwe
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^ permalink raw reply
* Re: [PATCH 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
From: Dmitry Baryshkov @ 2026-04-04 21:20 UTC (permalink / raw)
To: jsandom
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260404-rb5gen2-dts-v1-5-895f8fc494fc@axon.com>
On Sat, Apr 04, 2026 at 10:50:58AM +0100, Joe Sandom via B4 Relay wrote:
> From: Joe Sandom <jsandom@axon.com>
>
> The RB5gen2 is an embedded development platform for the
> QCS8550, based on the Snapdragon 8 Gen 2 SoC (SM8550).
>
> This change implements the main board, the vision mezzanine
> will be supported in a follow up patch.
>
> The main board has the following features:
> - Qualcomm Dragonwing QCS8550 SoC
> - Adreno GPU 740
> - Spectra ISP
> - Adreno VPU 8550
> - Adreno DPU 1295
> - 1 x 1GbE Ethernet (USB Ethernet)
> - WIFI 7 + Bluetooth 5.4
> - 1 x USB 2.0 Micro B (Debug)
> - 1 x USB 3.0 Type C (ADB, DP out)
> - 2 x USB 3.0 Type A
> - 1 x HDMI 1.4 Type A
> - 1 x DP 1.4 Type C
> - 2 x WSA8845 Speaker amplifiers
> - 2 x Speaker connectors
> - 1 x On Board PDM MIC
> - Accelerometer + Gyro Sensor
> - 96Boards compatible low-speed and high-speed connectors [1]
> - 7 x LED indicators (4 user, 2 radio, 1 power)
> - Buttons for power, volume up/down, force USB boot
> - 3 x Dip switches
>
> On-Board PMICs:
> - PMK8550 2.1
> - PM8550 2.0
> - PM8550VS 2.0 x4
> - PM8550VE 2.0
> - PM8550B 2.0
> - PMR735D 2.0
> - PM8010 1.1 x2
>
> Product Page: [2]
>
> [1] https://www.96boards.org/specifications/
> [2] https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit
>
> Signed-off-by: Joe Sandom <jsandom@axon.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 1610 ++++++++++++++++++++++++++
> 2 files changed, 1611 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 4ba8e73064194926096b98b9556a3207e8f24d72..f8c65771f76629d7fafee15ac8d7bb62cd24a20f 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -184,6 +184,7 @@ qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo
>
> dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += qcs8550-rb5gen2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..280fbd3a09997e3e2613498e25ac188680484cc4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
> @@ -0,0 +1,1610 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2026 Axon Enterprise, Inc.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include "qcs8550.dtsi"
> +#include "pm8010.dtsi"
> +#include "pm8550.dtsi"
> +#include "pm8550b.dtsi"
> +#define PMK8550VE_SID 5
> +#include "pm8550ve.dtsi"
> +#include "pm8550vs.dtsi"
> +#include "pmk8550.dtsi"
> +#include "pmr735d_a.dtsi"
> +#include "pmr735d_b.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. QCS8550 RB5Gen2";
> + compatible = "qcom,qcs8550-rb5gen2", "qcom,qcs8550", "qcom,sm8550";
> + chassis-type = "embedded";
> +
> + aliases {
> + serial0 = &uart7;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + clocks {
> + clk40m: can-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <40000000>;
> + #clock-cells = <0>;
> + };
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + pinctrl-0 = <&volume_up_n>;
> + pinctrl-names = "default";
> +
> + key-volume-up {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
> + debounce-interval = <15>;
> + linux,can-disable;
> + wakeup-source;
> + };
> + };
> +
> + hdmi-connector {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con: endpoint {
> + remote-endpoint = <<9611_out>;
> + };
> + };
> + };
> +
> + /* Lontium LT9611UXC fails FW upgrade and has timeouts with geni-i2c */
> + /* Workaround is to use bit-banged I2C */
> + i2c_hub_3_gpio: i2c {
> + compatible = "i2c-gpio";
> +
> + sda-gpios = <&tlmm 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + scl-gpios = <&tlmm 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + led-0 {
> + label = "green:status-3";
> + function = LED_FUNCTION_STATUS;
> + color = <LED_COLOR_ID_GREEN>;
> + gpios = <&pm8550_gpios 2 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> +
> + led-1 {
> + label = "blue:bt-power";
> + function = LED_FUNCTION_BLUETOOTH;
> + color = <LED_COLOR_ID_BLUE>;
> + gpios = <&pm8550b_gpios 7 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "bluetooth-power";
> + default-state = "off";
> + };
> +
> + led-2 {
> + label = "yellow:wlan";
> + function = LED_FUNCTION_WLAN;
> + color = <LED_COLOR_ID_YELLOW>;
> + gpios = <&pm8550b_gpios 9 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "phy0tx";
> + default-state = "off";
> + };
> + };
> +
> + lt9611_1v2: lt9611-regulator-1v2 {
> + compatible = "regulator-fixed";
> + regulator-name = "LT9611_1V2";
> +
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> +
> + vin-supply = <&vreg_l14b_3p2>;
> + };
> +
> + lt9611_3v3: lt9611-regulator-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "LT9611_3V3";
> +
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + vin-supply = <&vreg_l14b_3p2>;
> + };
> +
> + pmic-glink {
> + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + connector@0 {
> + compatible = "usb-c-connector";
> + reg = <0>;
> + power-role = "dual";
> + data-role = "dual";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + pmic_glink_hs_in: endpoint {
> + remote-endpoint = <&usb_1_dwc3_hs>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + pmic_glink_ss_in: endpoint {
> + remote-endpoint = <&redriver_usb_con_ss>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + pmic_glink_sbu_in: endpoint {
> + remote-endpoint = <&redriver_usb_con_sbu>;
> + };
> + };
> + };
> + };
> + };
> +
> + pcie_upd_1p05: regulator-pcie-upd-1p05 {
> + compatible = "regulator-fixed";
> + regulator-name = "PCIE_UPD_1P05";
> + gpio = <&tlmm 179 GPIO_ACTIVE_HIGH>;
> + vin-supply = <&vdd_ntn_0p9>;
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + enable-active-high;
> + regulator-enable-ramp-delay = <5000>;
> + pinctrl-0 = <&upd_1p05_en>;
> + pinctrl-names = "default";
> + };
> +
> + pcie_upd_3p3: regulator-pcie-upd-3p3 {
> + compatible = "regulator-fixed";
> + regulator-name = "PCIE_UPD_3P3";
> + gpio = <&tlmm 13 GPIO_ACTIVE_HIGH>;
> + vin-supply = <&pcie_upd_1p05>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + regulator-enable-ramp-delay = <10000>;
> + pinctrl-0 = <&upd_3p3_en>;
> + pinctrl-names = "default";
> + };
> +
> + upd_reset: regulator-upd-reset {
> + compatible = "regulator-fixed";
> + regulator-name = "UPD_RESET";
Reset usually isn't a regulator.
> + gpio = <&tlmm 182 GPIO_ACTIVE_HIGH>;
> + vin-supply = <&pcie_upd_3p3>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + regulator-enable-ramp-delay = <10000>;
> + regulator-boot-on;
> + regulator-always-on;
Especially since it's not controlled.
> + pinctrl-0 = <&upd_ponrst>;
> + pinctrl-names = "default";
> + };
> +
> + usbhub_reset: regulator-usbhub-reset {
> + compatible = "regulator-fixed";
> + regulator-name = "USBHUB_RESET";
Same here.
> + gpio = <&tlmm 41 GPIO_ACTIVE_LOW>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + startup-delay-us = <1500>;
> + off-on-delay-us = <1500>;
> + pinctrl-0 = <&usbhub_rst>;
> + pinctrl-names = "default";
> + };
> +
> + vdd_ntn_0p9: regulator-vdd-ntn-0p9 {
> + compatible = "regulator-fixed";
> + regulator-name = "VDD_NTN_0P9";
> + vin-supply = <&vdd_ntn_1p8>;
> + regulator-min-microvolt = <899400>;
> + regulator-max-microvolt = <899400>;
> + regulator-enable-ramp-delay = <4300>;
> + };
> +
> + vdd_ntn_1p8: regulator-vdd-ntn-1p8 {
> + compatible = "regulator-fixed";
> + regulator-name = "VDD_NTN_1P8";
> + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + enable-active-high;
> + pinctrl-0 = <&ntn0_en>;
> + pinctrl-names = "default";
> + regulator-enable-ramp-delay = <10000>;
> + };
> +
> + vdd_ntn1_0p9: regulator-vdd-ntn1-0p9 {
> + compatible = "regulator-fixed";
> + regulator-name = "VDD_NTN1_0P9";
> + vin-supply = <&vdd_ntn1_1p8>;
> + regulator-min-microvolt = <899400>;
> + regulator-max-microvolt = <899400>;
> + regulator-enable-ramp-delay = <4300>;
> + };
> +
> + vdd_ntn1_1p8: regulator-vdd-ntn1-1p8 {
> + compatible = "regulator-fixed";
> + regulator-name = "VDD_NTN1_1P8";
> + gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + enable-active-high;
> + pinctrl-0 = <&ntn1_en>;
> + pinctrl-names = "default";
> + regulator-enable-ramp-delay = <10000>;
> + };
> +
> + vph_pwr: regulator-vph-pwr {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + sound {
> + compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
> + model = "QCS8550-RB5Gen2";
> + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
> + "SpkrRight IN", "WSA_SPK2 OUT",
> + "VA DMIC0", "vdd-micb",
> + "VA DMIC1", "vdd-micb";
> +
> + wsa-dai-link {
> + link-name = "WSA Playback";
> +
> + cpu {
> + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
> + };
> +
> + codec {
> + sound-dai = <&left_spkr>, <&right_spkr>,
> + <&swr0 0>, <&lpass_wsamacro 0>;
> + };
> +
> + platform {
> + sound-dai = <&q6apm>;
> + };
> + };
> +
> + va-dai-link {
> + link-name = "VA Capture";
> +
> + cpu {
> + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
> + };
> +
> + codec {
> + sound-dai = <&lpass_vamacro 0>;
> + };
> +
> + platform {
> + sound-dai = <&q6apm>;
> + };
> + };
> + };
> +
> + wcn7850-pmu {
> + compatible = "qcom,wcn7850-pmu";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&wlan_en>, <&bt_default>, <&pmk8550_sleep_clk>;
swctrl?
> +
> + wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
> + bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
swctrl?
> +
> + vdd-supply = <&vreg_s5g_0p85>;
> + vddio-supply = <&vreg_l15b_1p8>;
> + vddaon-supply = <&vreg_s2g_0p852>;
> + vdddig-supply = <&vreg_s4e_0p95>;
> + vddrfa1p2-supply = <&vreg_s4g_1p25>;
> + vddrfa1p8-supply = <&vreg_s6g_1p86>;
[...]
> +
> +&gpi_dma1 {
> + status = "okay";
> +};
> +
> +&gpi_dma2 {
> + status = "okay";
> +};
> +
> +&gpu {
> + status = "okay";
> +};
> +
> +&gpu_zap_shader {
> + firmware-name = "qcom/qcs8550/a740_zap.mbn";
> +};
> +
> +&i2c_hub_2 {
> + clock-frequency = <100000>;
> +
> + status = "okay";
> +
> + typec-mux@1c {
> + compatible = "onnn,nb7vpq904m";
> + reg = <0x1c>;
> +
> + vcc-supply = <&vreg_l15b_1p8>;
> +
> + retimer-switch;
> + orientation-switch;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + redriver_usb_con_ss: endpoint {
> + remote-endpoint = <&pmic_glink_ss_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + redriver_phy_con_ss: endpoint {
> + remote-endpoint = <&usb_dp_qmpphy_out>;
> + data-lanes = <0 1 2 3>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + redriver_usb_con_sbu: endpoint {
> + remote-endpoint = <&pmic_glink_sbu_in>;
> + };
> + };
> + };
> + };
> +};
> +
> +&i2c_hub_3_gpio {
> + clock-frequency = <400000>;
> +
> + status = "okay";
> +
> + lt9611_codec: hdmi-bridge@2b {
> + compatible = "lontium,lt9611uxc";
> + reg = <0x2b>;
> +
> + interrupts-extended = <&tlmm 40 IRQ_TYPE_EDGE_FALLING>;
> + reset-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
> +
> + vdd-supply = <<9611_1v2>;
> + vcc-supply = <<9611_3v3>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + lt9611_a: endpoint {
> + remote-endpoint = <&mdss_dsi0_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + lt9611_out: endpoint {
> + remote-endpoint = <&hdmi_con>;
> + };
> + };
> + };
> + };
> +};
> +
> +&i2c_hub_4 {
> + status = "okay";
> +};
> +
> +&i2c_master_hub_0 {
> + status = "okay";
> +};
> +
> +&ipa {
> + qcom,gsi-loader = "self";
> + memory-region = <&ipa_fw_mem>;
These two should be a part of sm8550.dtsi
> + firmware-name = "qcom/qcs8550/ipa_fws.mbn";
> +
> + status = "okay";
> +};
> +
> +&iris {
> + status = "okay";
> +};
> +
> +&lpass_vamacro {
> + pinctrl-0 = <&dmic01_default>;
> + pinctrl-names = "default";
> +
> + qcom,dmic-sample-rate = <4800000>;
> +
> + vdd-micb-supply = <&vreg_l15b_1p8>;
> +};
> +
> +&mdss {
> + status = "okay";
> +};
> +
> +&mdss_dsi0 {
> + vdda-supply = <&vreg_l3e_1p2>;
> +
> + status = "okay";
> +};
> +
> +&mdss_dsi0_out {
> + remote-endpoint = <<9611_a>;
> + data-lanes = <0 1 2 3>;
> +};
> +
> +&mdss_dsi0_phy {
> + vdds-supply = <&vreg_l1e_0p88>;
> +
> + status = "okay";
> +};
> +
> +&mdss_dp0 {
> + status = "okay";
> +};
> +
> +&pcie0 {
> + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
> + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
> +
> + pinctrl-0 = <&pcie0_default_state>;
> + pinctrl-names = "default";
> +
> + iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
> + <0x100 &apps_smmu 0x1401 0x1>,
> + <0x208 &apps_smmu 0x1402 0x1>,
> + <0x210 &apps_smmu 0x1403 0x1>,
> + <0x218 &apps_smmu 0x1404 0x1>,
> + <0x300 &apps_smmu 0x1407 0x1>,
> + <0x400 &apps_smmu 0x1408 0x1>,
> + <0x500 &apps_smmu 0x140c 0x1>,
> + <0x501 &apps_smmu 0x140e 0x1>;
> +
> + /delete-property/ msi-map;
Why?
> +
> + status = "okay";
> +};
> +
[...]
> +
> +&pcie1 {
> + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
> + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
> +
> + pinctrl-0 = <&pcie1_default_state>;
> + pinctrl-names = "default";
> +
> + iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
> + <0x100 &apps_smmu 0x1481 0x1>,
> + <0x208 &apps_smmu 0x1482 0x1>,
> + <0x210 &apps_smmu 0x1483 0x1>,
> + <0x218 &apps_smmu 0x1484 0x1>,
> + <0x300 &apps_smmu 0x1487 0x1>,
> + <0x400 &apps_smmu 0x1488 0x1>,
> + <0x500 &apps_smmu 0x148c 0x1>,
> + <0x501 &apps_smmu 0x148e 0x1>;
> +
> + /delete-property/ msi-map;
Why?
> +
> + status = "okay";
> +};
> +
> +&pcie1_phy {
> + vdda-phy-supply = <&vreg_l3c_0p9>;
> + vdda-pll-supply = <&vreg_l3e_1p2>;
> + vdda-qref-supply = <&vreg_l1e_0p88>;
> +
> + status = "okay";
> +};
> +
[...]
> +
> +&remoteproc_adsp {
> + firmware-name = "qcom/qcs8550/adsp.mdt",
> + "qcom/qcs8550/adsp_dtb.mdt";
MBN, please align vertically on the quote mark. The same for CDSP and
modem.
> + status = "okay";
> +};
> +
> +&remoteproc_cdsp {
> + firmware-name = "qcom/qcs8550/cdsp.mdt",
> + "qcom/qcs8550/cdsp_dtb.mdt";
> + status = "okay";
> +};
> +
> +&remoteproc_mpss {
> + firmware-name = "qcom/qcs8550/modem.mdt",
> + "qcom/qcs8550/modem_dtb.mdt";
> + status = "okay";
> +};
> +
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH RFC 2/4] arm64: dts: qcom: glymur: Add GPU smmu node
From: Dmitry Baryshkov @ 2026-04-04 21:21 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, linux-arm-msm, devicetree, linux-kernel,
dri-devel, freedreno, Rajendra Nayak, Rajendra Nayak
In-Reply-To: <20260405-glymur-gpu-dt-v1-2-2135eb11c562@oss.qualcomm.com>
On Sun, Apr 05, 2026 at 02:33:15AM +0530, Akhil P Oommen wrote:
> From: Rajendra Nayak <quic_rjendra@quicinc.com>
>
> Add the nodes to describe the GPU SMMU node.
>
> Signed-off-by: Rajendra Nayak <rajendra.nayak@oss.qualcomm.com>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 40 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH RFC 4/4] arm64: dts: qcom: Enable GPU & GMU on Glymur CRD
From: Dmitry Baryshkov @ 2026-04-04 21:44 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, linux-arm-msm, devicetree, linux-kernel,
dri-devel, freedreno
In-Reply-To: <20260405-glymur-gpu-dt-v1-4-2135eb11c562@oss.qualcomm.com>
On Sun, Apr 05, 2026 at 02:33:17AM +0530, Akhil P Oommen wrote:
> Enable the necessary DT nodes to add support for GPU on the Glymur CRD.
> The Glymur CRD boots Linux at EL2, which means it doesn't require the
> secure GPU firmware (zap fw).
Is this going to be a default mode for other laptops too? Otherwise it
might be better to keep ZAP node enabled by default and disable it here.
>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> index 51ea23a49b9e..a579df902323 100644
> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> @@ -110,6 +110,14 @@ vreg_misc_3p3: regulator-misc-3p3 {
> };
> };
>
> +&gpu {
> + status = "okay";
> +};
> +
> +&gmu {
> + status = "okay";
> +};
> +
> &i2c0 {
> clock-frequency = <400000>;
>
>
> --
> 2.51.0
>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 2/2] pmdomain: qcom: rpmhpd: Add power domains for Hawi SoC
From: Dmitry Baryshkov @ 2026-04-04 21:48 UTC (permalink / raw)
To: Fenglin Wu
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Ulf Hansson, Konrad Dybcio, Subbaraman Narayanamurthy,
linux-arm-msm, devicetree, linux-kernel, linux-pm, kernel,
Taniya Das
In-Reply-To: <20260402-haw-rpmhpd-v2-2-2bce0767f2ca@oss.qualcomm.com>
On Thu, Apr 02, 2026 at 05:35:22PM -0700, Fenglin Wu wrote:
> Add the RPMh power domains required for the Hawi SoC. This includes
> new definitions for domains supplying specific hardware components:
> - DCX: supplies VDD_DISP
> - GBX: supplies VDD_GFX_BX
>
> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com>
> ---
> drivers/pmdomain/qcom/rpmhpd.c | 38 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v1] arm64: dts: qcom: qcs6490-rb3gen2: Enable CAN bus controller
From: Dmitry Baryshkov @ 2026-04-04 21:54 UTC (permalink / raw)
To: Viken Dadhaniya
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260403-can-spi-kodiak-dtsi-v1-1-4055e67dd3fc@oss.qualcomm.com>
On Fri, Apr 03, 2026 at 12:10:34PM +0530, Viken Dadhaniya wrote:
> Enable the MCP2518FD CAN controller on the QCS6490 RB3 Gen2 platform.
> The controller is connected via SPI3 and uses a 40 MHz oscillator.
>
> Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 2/2] arm64: dts: qcom: Add Motorola Edge 30 (dubai) DTS
From: Dmitry Baryshkov @ 2026-04-04 21:54 UTC (permalink / raw)
To: Val Packett
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kees Cook, Tony Luck, Guilherme G. Piccoli,
~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel
In-Reply-To: <20260403054417.167917-2-val@packett.cool>
On Fri, Apr 03, 2026 at 02:33:09AM -0300, Val Packett wrote:
> The Motorola Edge 30 is a smartphone released in 2022.
>
> This commit has the following features working:
> - Display (simplefb)
> - Touchscreen
> - Power and volume buttons
> - Storage (UFS 3.1)
> - Battery (ADSP battmgr)
> - USB (Type-C, 2.0, dual-role)
> - Wi-Fi and Bluetooth (WCN6750 hw1.0)
>
> Signed-off-by: Val Packett <val@packett.cool>
> ---
> v2: Apply suggestions from Konrad
> v1: https://lore.kernel.org/all/20260329103055.96649-2-val@packett.cool/
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> .../boot/dts/qcom/sm7325-motorola-dubai.dts | 1456 +++++++++++++++++
> 2 files changed, 1457 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 2/2] spmi: spmi-pmic-arb: add support for PMIC arbiter v8.5
From: Dmitry Baryshkov @ 2026-04-04 21:56 UTC (permalink / raw)
To: Fenglin Wu
Cc: Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Konrad Dybcio, Subbaraman Narayanamurthy, David Collins,
linux-arm-msm, linux-kernel, devicetree, kernel
In-Reply-To: <20260402-hawi-spmi-v2-2-0bbe811fe3f4@oss.qualcomm.com>
On Thu, Apr 02, 2026 at 05:55:12PM -0700, Fenglin Wu wrote:
> PMIC arbiter v8.5 is an extension of PMIC arbiter v8 that updated
> the definition of the channel status register bit fields. Add support
> to handle this difference.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com>
> ---
> drivers/spmi/spmi-pmic-arb.c | 69 ++++++++++++++++++++++++++++++++++++++------
> 1 file changed, 60 insertions(+), 9 deletions(-)
>
Please leave at least some time between replying to previous comments
and posting new series. Let's continue discussion in v1 first.
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH RFC v2 6/6] arm64: dts: qcom: milos: Add Adreno 810 GPU and GMU nodes
From: Dmitry Baryshkov @ 2026-04-04 21:57 UTC (permalink / raw)
To: Alexander Koskovich
Cc: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Akhil P Oommen,
Bjorn Andersson, Luca Weiss, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, Konrad Dybcio
In-Reply-To: <20260402-adreno-810-v2-6-ce337ca87a9e@pm.me>
On Thu, Apr 02, 2026 at 11:09:52PM +0000, Alexander Koskovich wrote:
> Add GPU and GMU devicetree nodes for the Adreno 810 GPU found on
> Qualcomm SM7635 (Milos) based devices.
>
> The qcom,kaanapali-gxclkctl.h header can be reused here because
> Milos uses the same driver and the GX_CLKCTL_GX_GDSC definition
> is identical.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
> arch/arm64/boot/dts/qcom/milos.dtsi | 148 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 148 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 2/7] dt-bindings: display/msm: dp-controller: Allow DAI on SM8650
From: Dmitry Baryshkov @ 2026-04-04 22:04 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Neil Armstrong,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, Krzysztof Kozlowski
In-Reply-To: <20260402-dts-qcom-display-regs-v1-2-daa54ab448a3@oss.qualcomm.com>
On Thu, Apr 02, 2026 at 01:45:13PM +0200, Krzysztof Kozlowski wrote:
> DisplayPort on Qualcomm SM8650 (and compatible SM8750) supports audio
> and there is DTS already having cells and sound-name-prefix. Add SM8650
> to the list of SoCs referencing the dai-common.yaml schema to solve
> dtbs_check warnings like:
>
> sm8650-hdk-display-card-rear-camera-card.dtb:
> displayport-controller@af54000 (qcom,sm8650-dp): Unevaluated properties are not allowed ('sound-name-prefix' was unexpected)
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> index e4f17d29343b..f8daaee8d065 100644
> --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
> @@ -210,6 +210,7 @@ allOf:
> enum:
> - qcom,glymur-dp
> - qcom,sa8775p-dp
> + - qcom,sm8650-dp
> - qcom,x1e80100-dp
> then:
> $ref: /schemas/sound/dai-common.yaml#
This clause is for the platforms which can work either with the eDP
(aux-bus) or DP (sound-dai-cells) setup. Instead please extend the else
clause to $ref dai-common.yaml.
>
> --
> 2.51.0
>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 3/7] dt-bindings: display/msm: sm8650: Correct VBIF range in example
From: Dmitry Baryshkov @ 2026-04-04 22:04 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Neil Armstrong,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, Krzysztof Kozlowski
In-Reply-To: <20260402-dts-qcom-display-regs-v1-3-daa54ab448a3@oss.qualcomm.com>
On Thu, Apr 02, 2026 at 01:45:14PM +0200, Krzysztof Kozlowski wrote:
> VBIF register range is 0x3000 long, so correct the example. No
> practical impact, except when existing code is being re-used in new
> contributions.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 2 +-
> Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 4/7] dt-bindings: display/msm: qcom,sm8750-mdss: Correct DPU and DP ranges in example
From: Dmitry Baryshkov @ 2026-04-04 22:05 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Neil Armstrong,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, Krzysztof Kozlowski
In-Reply-To: <20260402-dts-qcom-display-regs-v1-4-daa54ab448a3@oss.qualcomm.com>
On Thu, Apr 02, 2026 at 01:45:15PM +0200, Krzysztof Kozlowski wrote:
> VBIF register range is 0x3000 long. DisplayPort block has few too short
> ranges and misses four more address spaces.
>
> No practical impact, except when existing code is being re-used in new
> contributions.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
> .../bindings/display/msm/qcom,sm8750-mdss.yaml | 16 ++++++++++------
> 1 file changed, 10 insertions(+), 6 deletions(-)
>
Nit: the subject differs in the style from the previous commit. With
that small issue fixed:
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 1/7] dt-bindings: display/msm: dp-controller: Correct SM8650 IO range
From: Dmitry Baryshkov @ 2026-04-04 23:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Neil Armstrong,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, Krzysztof Kozlowski
In-Reply-To: <20260402-dts-qcom-display-regs-v1-1-daa54ab448a3@oss.qualcomm.com>
On Thu, Apr 02, 2026 at 01:45:12PM +0200, Krzysztof Kozlowski wrote:
> DP on Qualcomm SM8650 come with nine address ranges, so describe the
> remaining ones as optional to keep ABI backwards compatible. Driver
> also does not need them to operate correctly.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
> .../bindings/display/msm/dp-controller.yaml | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 5/7] arm64: dts: qcom: sm8650: Correct and complete DP address spaces
From: Dmitry Baryshkov @ 2026-04-04 23:09 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kuogee Hsieh, Neil Armstrong,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, dri-devel,
freedreno, devicetree, linux-kernel, Krzysztof Kozlowski
In-Reply-To: <20260402-dts-qcom-display-regs-v1-5-daa54ab448a3@oss.qualcomm.com>
On Thu, Apr 02, 2026 at 01:45:16PM +0200, Krzysztof Kozlowski wrote:
> DisplayPort block on Qualcomm SM8650 has few too short address space
> ranges and misses four more spaces. Complete the hardware description,
> which in the future might be important for full feature support.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>
> ---
>
> dtbs_check success depends on the binding change (first commit).
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 1/4] dt-bindings: platform: introduce EC for Dell XPS 13 9345
From: Bryan O'Donoghue @ 2026-04-05 0:05 UTC (permalink / raw)
To: Aleksandrs Vinarskis, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Hans de Goede,
Ilpo Järvinen
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
laurentiu.tudor1, Abel Vesa, Tobias Heider, Val Packett,
Krzysztof Kozlowski
In-Reply-To: <20260404-dell-xps-9345-ec-v2-1-c977c3caa81f@vinarskis.com>
On 04/04/2026 13:55, Aleksandrs Vinarskis wrote:
> Add bindings for Embedded Controller (EC) in Dell XPS 13 9345 (platform
> codename 'tributo'). It may be partially or fully compatible with EC
> found in Snapdragon-based Dell Latitude, Inspiron ('thena').
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> Signed-off-by: Aleksandrs Vinarskis <alex@vinarskis.com>
> ---
> .../embedded-controller/dell,xps13-9345-ec.yaml | 91 ++++++++++++++++++++++
> MAINTAINERS | 5 ++
> 2 files changed, 96 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..e14dbf2f1a6af8cc7511890fbef08c6c717c0aa6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml
I believe the part name of this embedded controller is the "mec5200" so
instead of calling it dell,xps13-9345-ec suggest "dell,mec5200"
> @@ -0,0 +1,91 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/embedded-controller/dell,xps13-9345-ec.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Dell XPS 13 9345 Embedded Controller
> +
> +maintainers:
> + - Aleksandrs Vinarskis <alex@vinarskis.com>
> +
> +description:
> + The Dell XPS 13 9345 has an Embedded Controller (EC) which handles thermal
> + and power management. It is communicating with SoC over multiple i2c busses.
> + Among other things, it handles fan speed control, thermal shutdown, peripheral
> + power supply including trackpad, touch-row, display. For these functions, it
> + requires frequently updated thermal readings from onboard thermistors.
> +
> +properties:
> + compatible:
> + const: dell,xps13-9345-ec
Ditto the compat - name it after the IC not the laptop its a "mec5200"
or "mec5200-ec" - I suspect the -ec postfix is a tautology the ec bit in
"mec" probably captures.
> +
> + reg:
> + const: 0x3b
> +
> + interrupts:
> + maxItems: 1
> +
> + io-channels:
> + description:
> + ADC channels connected to the 7 onboard thermistors on PMK8550.
> + EC requires frequent thermal readings of these channels to perform
> + automated fan speed control.
> + items:
> + - description: ADC channel for sys_therm0
> + - description: ADC channel for sys_therm1
> + - description: ADC channel for sys_therm2
> + - description: ADC channel for sys_therm3
> + - description: ADC channel for sys_therm4
> + - description: ADC channel for sys_therm5
> + - description: ADC channel for sys_therm6
> +
> + io-channel-names:
> + items:
> + - const: sys_therm0
> + - const: sys_therm1
> + - const: sys_therm2
> + - const: sys_therm3
> + - const: sys_therm4
> + - const: sys_therm5
> + - const: sys_therm6
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - io-channels
> + - io-channel-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
> + i2c {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + embedded-controller@3b {
> + compatible = "dell,xps13-9345-ec";
> + reg = <0x3b>;
> + interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_LOW>;
> +
> + io-channels = <&pmk8550_vadc PM8350_ADC7_GPIO3_100K_PU(1)>,
> + <&pmk8550_vadc PM8350_ADC7_GPIO4_100K_PU(1)>,
> + <&pmk8550_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>,
> + <&pmk8550_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>,
> + <&pmk8550_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>,
> + <&pmk8550_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>,
> + <&pmk8550_vadc PM8350_ADC7_AMUX_THM5_100K_PU(1)>;
> + io-channel-names = "sys_therm0",
> + "sys_therm1",
> + "sys_therm2",
> + "sys_therm3",
> + "sys_therm4",
> + "sys_therm5",
> + "sys_therm6";
> + };
> + };
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 96e0781f2201b41b976dfa69efd44d62c4ff0058..a5d175559f4468dfe363b319a1b08d3425f4d712 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -7236,6 +7236,11 @@ S: Maintained
> F: Documentation/ABI/testing/sysfs-class-firmware-attributes
> F: drivers/platform/x86/dell/dell-wmi-sysman/
>
> +DELL XPS EMBEDDED CONTROLLER DRIVER
> +M: Aleksandrs Vinarskis <alex@vinarskis.com>
> +S: Maintained
> +F: Documentation/devicetree/bindings/embedded-controller/dell,xps13-9345-ec.yaml
> +
> DELTA AHE-50DC FAN CONTROL MODULE DRIVER
> M: Zev Weiss <zev@bewilderbeest.net>
> L: linux-hwmon@vger.kernel.org
>
^ permalink raw reply
* Re: [PATCH v2 1/4] dt-bindings: platform: introduce EC for Dell XPS 13 9345
From: Bryan O'Donoghue @ 2026-04-05 0:15 UTC (permalink / raw)
To: Aleksandrs Vinarskis, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Hans de Goede,
Ilpo Järvinen
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
laurentiu.tudor1, Abel Vesa, Tobias Heider, Val Packett,
Krzysztof Kozlowski
In-Reply-To: <20260404-dell-xps-9345-ec-v2-1-c977c3caa81f@vinarskis.com>
On 04/04/2026 13:55, Aleksandrs Vinarskis wrote:
> + items:
> + - description: ADC channel for sys_therm0
> + - description: ADC channel for sys_therm1
> + - description: ADC channel for sys_therm2
> + - description: ADC channel for sys_therm3
> + - description: ADC channel for sys_therm4
> + - description: ADC channel for sys_therm5
> + - description: ADC channel for sys_therm6
> +
> + io-channel-names:
> + items:
> + - const: sys_therm0
> + - const: sys_therm1
> + - const: sys_therm2
> + - const: sys_therm3
> + - const: sys_therm4
> + - const: sys_therm5
> + - const: sys_therm6
I agree with the number of io-channels but, having fixed names is I feel
not correct.
io-channel-names:
minItems: 7
maxItems: 7
Does the same thing but lets you name the channels at the source and the
sync wrt what they do.
^ permalink raw reply
* Re: [PATCH v2 4/4] arm64: dts: qcom: x1e80100-dell-xps13-9345: introduce EC
From: Bryan O'Donoghue @ 2026-04-05 0:21 UTC (permalink / raw)
To: Aleksandrs Vinarskis, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Hans de Goede,
Ilpo Järvinen
Cc: linux-arm-msm, devicetree, linux-kernel, platform-driver-x86,
laurentiu.tudor1, Abel Vesa, Tobias Heider, Val Packett
In-Reply-To: <20260404-dell-xps-9345-ec-v2-4-c977c3caa81f@vinarskis.com>
On 04/04/2026 13:55, Aleksandrs Vinarskis wrote:
> + io-channel-names = "sys_therm0",
> + "sys_therm1",
> + "sys_therm2",
> + "sys_therm3",
> + "sys_therm4",
> + "sys_therm5",
> + "sys_therm6";
io-channels-names = "lpddr5x-therm", "charger-left-therm",
"charger-right-therm", "ssd-therm", "keyboard-therm"
> + };
> };
>
> &i2c7 {
> @@ -1025,6 +1050,64 @@ rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state {
> };
> };
>
> +&pmk8550_vadc {
> + /* Around DRAM */
> + channel@14c {
> + reg = <PM8350_ADC7_GPIO3_100K_PU(1)>;
> + qcom,hw-settle-time = <200>;
> + qcom,ratiometric;
> + label = "sys_therm0";
You might as well use the same name for the label "lpddr5-therm"
> + };
On thena the list is:
- "OPT temp"
- "CPU VR"
- "GPU VR"
- "Charging-1"
- "Charging-2"
- "WLAN"
- "WLAN (EE)"
So I think both the source and the sink should describe and be allowed
to describe what it is io-channel-names = "fixed list" is too restrictive.
Much more useful to userspace to see a string "lpddr5-therm" than
"sys_therm0".
---
bod
^ permalink raw reply
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