* [PATCH v2 4/5] dt-bindings: arm: qcom: document QCS8550 RB5Gen2 board
From: Joe Sandom via B4 Relay @ 2026-04-07 15:46 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom,
Krzysztof Kozlowski
In-Reply-To: <20260407-rb5gen2-dts-v2-0-d0c7f447ee73@axon.com>
From: Joe Sandom <jsandom@axon.com>
Document the Qualcomm RB5gen2 from Thundercomm based on the
QCS8550 chipset from Qualcomm.
[1] https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit/
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 1335a7bee397c46e8dc62806091531e32b7327d4..f9f8001e3e6b66e3a926255bdb15363f4c7c2b66 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -1093,6 +1093,12 @@ properties:
- const: qcom,qcs8550
- const: qcom,sm8550
+ - items:
+ - enum:
+ - qcom,qcs8550-rb5gen2
+ - const: qcom,qcs8550
+ - const: qcom,sm8550
+
- items:
- enum:
- ayaneo,pocket-s2
--
2.34.1
^ permalink raw reply related
* [PATCH v2 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
From: Joe Sandom via B4 Relay @ 2026-04-07 15:46 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom
In-Reply-To: <20260407-rb5gen2-dts-v2-0-d0c7f447ee73@axon.com>
From: Joe Sandom <jsandom@axon.com>
The RB5gen2 is an embedded development platform for the
QCS8550, based on the Snapdragon 8 Gen 2 SoC (SM8550).
This change implements the main board, the vision mezzanine
will be supported in a follow up patch.
The main board has the following features:
- Qualcomm Dragonwing QCS8550 SoC
- Adreno GPU 740
- Spectra ISP
- Adreno VPU 8550
- Adreno DPU 1295
- 1 x 1GbE Ethernet (USB Ethernet)
- WIFI 7 + Bluetooth 5.4
- 1 x USB 2.0 Micro B (Debug)
- 1 x USB 3.0 Type C (ADB, DP out)
- 2 x USB 3.0 Type A
- 1 x HDMI 1.4 Type A
- 1 x DP 1.4 Type C
- 2 x WSA8845 Speaker amplifiers
- 2 x Speaker connectors
- 1 x On Board PDM MIC
- Accelerometer + Gyro Sensor
- 96Boards compatible low-speed and high-speed connectors [1]
- 7 x LED indicators (4 user, 2 radio, 1 power)
- Buttons for power, volume up/down, force USB boot
- 3 x Dip switches
On-Board PMICs:
- PMK8550 2.1
- PM8550 2.0
- PM8550VS 2.0 x4
- PM8550VE 2.0
- PM8550B 2.0
- PMR735D 2.0
- PM8010 1.1 x2
Product Page: [2]
[1] https://www.96boards.org/specifications/
[2] https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit
Note that the default msi-map from sm8550.dtsi is deleted for both pcie0
and pcie1 because this results in ITS MAPD command timeouts when enabled.
Despite extending the msi-map to match the iommu-map the behaviour is
the same. If we delete the msi-map property, the DWC PCIe controller
will fall back to its internal iMSI-RX module which appears to work
without issues.
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 1574 ++++++++++++++++++++++++++
2 files changed, 1575 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 4ba8e73064194926096b98b9556a3207e8f24d72..f8c65771f76629d7fafee15ac8d7bb62cd24a20f 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -184,6 +184,7 @@ qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcs8550-rb5gen2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
new file mode 100644
index 0000000000000000000000000000000000000000..2a7197bc47abb8d62f2fdbae693fdd72bbe470aa
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
@@ -0,0 +1,1574 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2026 Axon Enterprise, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "qcs8550.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+#include "pmr735d_a.dtsi"
+#include "pmr735d_b.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCS8550 RB5Gen2";
+ compatible = "qcom,qcs8550-rb5gen2", "qcom,qcs8550", "qcom,sm8550";
+ chassis-type = "embedded";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ clk40m: can-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
+ /* Lontium LT9611UXC fails FW upgrade and has timeouts with geni-i2c */
+ /* Workaround is to use bit-banged I2C */
+ i2c_hub_3_gpio: i2c {
+ compatible = "i2c-gpio";
+
+ sda-gpios = <&tlmm 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&tlmm 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "green:status-3";
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pm8550_gpios 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-1 {
+ label = "blue:bt-power";
+ function = LED_FUNCTION_BLUETOOTH;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pm8550b_gpios 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ default-state = "off";
+ };
+
+ led-2 {
+ label = "yellow:wlan";
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_YELLOW>;
+ gpios = <&pm8550b_gpios 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+ };
+
+ lt9611_1v2: lt9611-regulator-1v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_1V2";
+
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ vin-supply = <&vreg_l14b_3p2>;
+ };
+
+ lt9611_3v3: lt9611-regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_3V3";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ vin-supply = <&vreg_l14b_3p2>;
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&redriver_usb_con_ss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu_in: endpoint {
+ remote-endpoint = <&redriver_usb_con_sbu>;
+ };
+ };
+ };
+ };
+ };
+
+ pcie_upd_1p05: regulator-pcie-upd-1p05 {
+ compatible = "regulator-fixed";
+ regulator-name = "PCIE_UPD_1P05";
+ gpio = <&tlmm 179 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vdd_ntn_0p9>;
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ enable-active-high;
+ regulator-enable-ramp-delay = <5000>;
+ pinctrl-0 = <&upd_1p05_en>;
+ pinctrl-names = "default";
+ };
+
+ pcie_upd_3p3: regulator-pcie-upd-3p3 {
+ compatible = "regulator-fixed";
+ regulator-name = "PCIE_UPD_3P3";
+ gpio = <&tlmm 13 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&pcie_upd_1p05>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-enable-ramp-delay = <10000>;
+ pinctrl-0 = <&upd_3p3_en>;
+ pinctrl-names = "default";
+ };
+
+ vdd_ntn_0p9: regulator-vdd-ntn-0p9 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN_0P9";
+ vin-supply = <&vdd_ntn_1p8>;
+ regulator-min-microvolt = <899400>;
+ regulator-max-microvolt = <899400>;
+ regulator-enable-ramp-delay = <4300>;
+ };
+
+ vdd_ntn_1p8: regulator-vdd-ntn-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN_1P8";
+ gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ pinctrl-0 = <&ntn0_en>;
+ pinctrl-names = "default";
+ regulator-enable-ramp-delay = <10000>;
+ };
+
+ vdd_ntn1_0p9: regulator-vdd-ntn1-0p9 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN1_0P9";
+ vin-supply = <&vdd_ntn1_1p8>;
+ regulator-min-microvolt = <899400>;
+ regulator-max-microvolt = <899400>;
+ regulator-enable-ramp-delay = <4300>;
+ };
+
+ vdd_ntn1_1p8: regulator-vdd-ntn1-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN1_1P8";
+ gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ pinctrl-0 = <&ntn1_en>;
+ pinctrl-names = "default";
+ regulator-enable-ramp-delay = <10000>;
+ };
+
+ vph_pwr: regulator-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sound {
+ compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
+ model = "QCS8550-RB5Gen2";
+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA DMIC0", "vdd-micb",
+ "VA DMIC1", "vdd-micb";
+
+ wsa-dai-link {
+ link-name = "WSA Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+ };
+
+ codec {
+ sound-dai = <&left_spkr>, <&right_spkr>,
+ <&swr0 0>, <&lpass_wsamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ va-dai-link {
+ link-name = "VA Capture";
+
+ cpu {
+ sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+ };
+
+ codec {
+ sound-dai = <&lpass_vamacro 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
+ wcn7850-pmu {
+ compatible = "qcom,wcn7850-pmu";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_en>, <&bt_default>, <&sw_ctrl_default>,
+ <&pmk8550_sleep_clk>;
+
+ wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
+ bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+ swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <&vreg_s5g_0p85>;
+ vddio-supply = <&vreg_l15b_1p8>;
+ vddaon-supply = <&vreg_s2g_0p852>;
+ vdddig-supply = <&vreg_s4e_0p95>;
+ vddrfa1p2-supply = <&vreg_s4g_1p25>;
+ vddrfa1p8-supply = <&vreg_s6g_1p86>;
+
+ regulators {
+ vreg_pmu_rfa_cmn: ldo0 {
+ regulator-name = "vreg_pmu_rfa_cmn";
+ };
+
+ vreg_pmu_aon_0p59: ldo1 {
+ regulator-name = "vreg_pmu_aon_0p59";
+ };
+
+ vreg_pmu_wlcx_0p8: ldo2 {
+ regulator-name = "vreg_pmu_wlcx_0p8";
+ };
+
+ vreg_pmu_wlmx_0p85: ldo3 {
+ regulator-name = "vreg_pmu_wlmx_0p85";
+ };
+
+ vreg_pmu_btcmx_0p85: ldo4 {
+ regulator-name = "vreg_pmu_btcmx_0p85";
+ };
+
+ vreg_pmu_rfa_0p8: ldo5 {
+ regulator-name = "vreg_pmu_rfa_0p8";
+ };
+
+ vreg_pmu_rfa_1p2: ldo6 {
+ regulator-name = "vreg_pmu_rfa_1p2";
+ };
+
+ vreg_pmu_rfa_1p8: ldo7 {
+ regulator-name = "vreg_pmu_rfa_1p8";
+ };
+
+ vreg_pmu_pcie_0p9: ldo8 {
+ regulator-name = "vreg_pmu_pcie_0p9";
+ };
+
+ vreg_pmu_pcie_1p8: ldo9 {
+ regulator-name = "vreg_pmu_pcie_1p8";
+ };
+ };
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s4g_1p25>;
+ vdd-l12-supply = <&vreg_s6g_1p86>;
+ vdd-l15-supply = <&vreg_s6g_1p86>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1760000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_l3c_0p9: ldo3 {
+ regulator-name = "vreg_l3c_0p9";
+ regulator-min-microvolt = <835000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <958000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2d_0p752: ldo2 {
+ regulator-name = "vreg_l2d_0p752";
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <808000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4d_0p628: smps4 {
+ regulator-name = "vreg_s4d_0p628";
+ regulator-min-microvolt = <572000>;
+ regulator-max-microvolt = <988000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5d_0p728: smps5 {
+ regulator-name = "vreg_s5d_0p728";
+ regulator-min-microvolt = <572000>;
+ regulator-max-microvolt = <988000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_l1e_0p88: ldo1 {
+ regulator-name = "vreg_l1e_0p88";
+ regulator-min-microvolt = <831000>;
+ regulator-max-microvolt = <904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2e_0p9: ldo2 {
+ regulator-name = "vreg_l2e_0p9";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s1e_0p72: smps1 {
+ regulator-name = "vreg_s1e_0p72";
+ regulator-min-microvolt = <532000>;
+ regulator-max-microvolt = <852000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3e_0p75: smps3 {
+ regulator-name = "vreg_s3e_0p75";
+ regulator-min-microvolt = <716000>;
+ regulator-max-microvolt = <884000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4e_0p95: smps4 {
+ regulator-name = "vreg_s4e_0p95";
+ regulator-min-microvolt = <870100>;
+ regulator-max-microvolt = <1152000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5e_1p08: smps5 {
+ regulator-name = "vreg_s5e_1p08";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1120000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6e_0p728: smps6 {
+ regulator-name = "vreg_s6e_0p728";
+ regulator-min-microvolt = <528000>;
+ regulator-max-microvolt = <904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s4e_0p95>;
+ vdd-l2-supply = <&vreg_s4e_0p95>;
+ vdd-l3-supply = <&vreg_s4e_0p95>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+
+ vreg_l1f_0p9: ldo1 {
+ regulator-name = "vreg_l1f_0p9";
+ regulator-min-microvolt = <866000>;
+ regulator-max-microvolt = <958000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_0p88: ldo2 {
+ regulator-name = "vreg_l2f_0p88";
+ regulator-min-microvolt = <866000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_0p88: ldo3 {
+ regulator-name = "vreg_l3f_0p88";
+ regulator-min-microvolt = <830000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s1f_0p728: smps1 {
+ regulator-name = "vreg_s1f_0p728";
+ regulator-min-microvolt = <516000>;
+ regulator-max-microvolt = <904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3f_0p852: smps3 {
+ regulator-name = "vreg_s3f_0p852";
+ regulator-min-microvolt = <688000>;
+ regulator-max-microvolt = <952000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4f_0p5: smps4 {
+ regulator-name = "vreg_s4f_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <500000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5f_0p752: smps5 {
+ regulator-name = "vreg_s5f_0p752";
+ regulator-min-microvolt = <716000>;
+ regulator-max-microvolt = <884000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s7f_0p628: smps7 {
+ regulator-name = "vreg_s7f_0p628";
+ regulator-min-microvolt = <516000>;
+ regulator-max-microvolt = <812000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+ qcom,pmic-id = "g";
+
+ vdd-l1-supply = <&vreg_s4g_1p25>;
+ vdd-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-supply = <&vreg_s4g_1p25>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vreg_l1g_1p2: ldo1 {
+ regulator-name = "vreg_l1g_1p2";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s1g_1p256: smps1 {
+ regulator-name = "vreg_s1g_1p256";
+ regulator-min-microvolt = <1172000>;
+ regulator-max-microvolt = <1388000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2g_0p852: smps2 {
+ regulator-name = "vreg_s2g_0p852";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1053200>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_0p752: smps3 {
+ regulator-name = "vreg_s3g_0p752";
+ regulator-min-microvolt = <532000>;
+ regulator-max-microvolt = <1148000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_1p25: smps4 {
+ regulator-name = "vreg_s4g_1p25";
+ regulator-min-microvolt = <1172000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5g_0p85: smps5 {
+ regulator-name = "vreg_s5g_0p85";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1002600>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6g_1p86: smps6 {
+ regulator-name = "vreg_s6g_1p86";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2192000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ vdd-l1-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6g_1p86>;
+ vdd-l6-supply = <&vreg_s6g_1p86>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ qcom,pmic-id = "m";
+
+ vreg_l1m_1p056: ldo1 {
+ regulator-name = "vreg_l1m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_1p8: ldo6 {
+ regulator-name = "vreg_l6m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p9: ldo7 {
+ regulator-name = "vreg_l7m_2p9";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+
+ vdd-l1-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6g_1p86>;
+ vdd-l6-supply = <&vreg_bob1>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ qcom,pmic-id = "n";
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p1: ldo2 {
+ regulator-name = "vreg_l2n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_2p8: ldo3 {
+ regulator-name = "vreg_l3n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_2p8: ldo4 {
+ regulator-name = "vreg_l4n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_1p8: ldo5 {
+ regulator-name = "vreg_l5n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_3p3: ldo6 {
+ regulator-name = "vreg_l6n_3p3";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_2p96: ldo7 {
+ regulator-name = "vreg_l7n_2p96";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpi_dma2 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/qcs8550/a740_zap.mbn";
+};
+
+&i2c_hub_2 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+
+ typec-mux@1c {
+ compatible = "onnn,nb7vpq904m";
+ reg = <0x1c>;
+
+ vcc-supply = <&vreg_l15b_1p8>;
+
+ retimer-switch;
+ orientation-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ redriver_usb_con_ss: endpoint {
+ remote-endpoint = <&pmic_glink_ss_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ redriver_phy_con_ss: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_out>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ redriver_usb_con_sbu: endpoint {
+ remote-endpoint = <&pmic_glink_sbu_in>;
+ };
+ };
+ };
+ };
+};
+
+&i2c_hub_3_gpio {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+
+ interrupts-extended = <&tlmm 40 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <<9611_1v2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&i2c_hub_4 {
+ status = "okay";
+};
+
+&i2c_master_hub_0 {
+ status = "okay";
+};
+
+&ipa {
+ firmware-name = "qcom/qcs8550/ipa_fws.mbn";
+
+ status = "okay";
+};
+
+&iris {
+ status = "okay";
+};
+
+&lpass_vamacro {
+ pinctrl-0 = <&dmic01_default>;
+ pinctrl-names = "default";
+
+ qcom,dmic-sample-rate = <4800000>;
+
+ vdd-micb-supply = <&vreg_l15b_1p8>;
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1e_0p88>;
+
+ status = "okay";
+};
+
+&mdss_dp0 {
+ status = "okay";
+};
+
+&pcie0 {
+ vddpe-3v3-supply = <&pcie_upd_3p3>;
+
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
+ <0x100 &apps_smmu 0x1401 0x1>,
+ <0x208 &apps_smmu 0x1402 0x1>,
+ <0x210 &apps_smmu 0x1403 0x1>,
+ <0x218 &apps_smmu 0x1404 0x1>,
+ <0x300 &apps_smmu 0x1407 0x1>,
+ <0x400 &apps_smmu 0x1408 0x1>,
+ <0x500 &apps_smmu 0x140c 0x1>,
+ <0x501 &apps_smmu 0x140e 0x1>;
+
+ /delete-property/ msi-map;
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pcie0_port0 {
+ pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x2 0xff>;
+
+ vddc-supply = <&vdd_ntn_0p9>;
+ vdd18-supply = <&vdd_ntn_1p8>;
+ vdd09-supply = <&vdd_ntn_0p9>;
+ vddio1-supply = <&vdd_ntn_1p8>;
+ vddio2-supply = <&vdd_ntn_1p8>;
+ vddio18-supply = <&vdd_ntn_1p8>;
+
+ i2c-parent = <&i2c_hub_4 0x77>;
+
+ resx-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&tc9563_0_rst &upd_ponrst>;
+ pinctrl-names = "default";
+
+ pcie@1,0 {
+ reg = <0x20800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x3 0xff>;
+ };
+
+ pcie@2,0 {
+ reg = <0x21000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x4 0xff>;
+ };
+
+ pcie@3,0 {
+ reg = <0x21800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ bus-range = <0x5 0xff>;
+
+ pci@0,0 {
+ reg = <0x50000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+
+ pci@0,1 {
+ reg = <0x50100 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+ };
+ };
+};
+
+&pcie1 {
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+
+ iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
+ <0x100 &apps_smmu 0x1481 0x1>,
+ <0x208 &apps_smmu 0x1482 0x1>,
+ <0x210 &apps_smmu 0x1483 0x1>,
+ <0x218 &apps_smmu 0x1484 0x1>,
+ <0x300 &apps_smmu 0x1487 0x1>,
+ <0x400 &apps_smmu 0x1488 0x1>,
+ <0x500 &apps_smmu 0x148c 0x1>,
+ <0x501 &apps_smmu 0x148e 0x1>;
+
+ /delete-property/ msi-map;
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l3c_0p9>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ vdda-qref-supply = <&vreg_l1e_0p88>;
+
+ status = "okay";
+};
+
+&pcie1_port0 {
+ pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x2 0xff>;
+
+ vddc-supply = <&vdd_ntn1_0p9>;
+ vdd18-supply = <&vdd_ntn1_1p8>;
+ vdd09-supply = <&vdd_ntn1_0p9>;
+ vddio1-supply = <&vdd_ntn1_1p8>;
+ vddio2-supply = <&vdd_ntn1_1p8>;
+ vddio18-supply = <&vdd_ntn1_1p8>;
+
+ i2c-parent = <&i2c_hub_3_gpio 0x77>;
+
+ resx-gpios = <&tlmm 65 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&tc9563_1_rst>;
+ pinctrl-names = "default";
+
+ pcie@1,0 {
+ reg = <0x20800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x3 0xff>;
+ };
+
+ pcie@2,0 {
+ reg = <0x21000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x4 0xff>;
+
+ wifi@0 {
+ compatible = "pci17cb,1107";
+ reg = <0x40000 0x0 0x0 0x0 0x0>;
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+ vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+ };
+ };
+
+ pcie@3,0 {
+ reg = <0x21800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ bus-range = <0x5 0xff>;
+ };
+ };
+};
+
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+
+ sdc2_card_det_n: sdc2-card-det-state {
+ pins = "gpio12";
+ function = "normal";
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pm8550_pwm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <0>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <2>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pmk8550_gpios {
+ pmk8550_sleep_clk: sleep-clk-state {
+ pins = "gpio3";
+ function = "func1";
+ input-disable;
+ output-enable;
+ bias-disable;
+ power-source = <0>;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/qcs8550/adsp.mbn",
+ "qcom/qcs8550/adsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/qcs8550/cdsp.mbn",
+ "qcom/qcs8550/cdsp_dtb.mbn";
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/qcs8550/modem.mbn",
+ "qcom/qcs8550/modem_dtb.mbn";
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+
+ max-sd-hs-hz = <37000000>;
+
+ no-sdio;
+ no-mmc;
+
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32764>;
+};
+
+&spi11 {
+ status = "okay";
+
+ can@0 {
+ compatible = "microchip,mcp2518fd";
+ reg = <0>;
+ interrupts-extended = <&tlmm 55 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk40m>;
+ spi-max-frequency = <10000000>;
+ vdd-supply = <&vreg_l14b_3p2>;
+ xceiver-supply = <&vreg_l14b_3p2>;
+ };
+};
+
+&swr0 {
+ status = "okay";
+
+ left_spkr: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrLeft";
+ qcom,port-mapping = <1 2 3 7 10 13>;
+ };
+
+ right_spkr: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l15b_1p8>;
+
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrRight";
+ qcom,port-mapping = <4 5 6 7 11 13>;
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 8>;
+
+ bt_default: bt-default-state {
+ pins = "gpio81";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sw_ctrl_default: sw-ctrl-default-state {
+ pins = "gpio82";
+ function = "gpio";
+ bias-pull-down;
+ };
+
+ lt9611_irq_pin: lt9611-irq-state {
+ pins = "gpio40";
+ function = "gpio";
+ bias-disable;
+ };
+
+ lt9611_rst_pin: lt9611-rst-state {
+ pins = "gpio7";
+ function = "gpio";
+ output-high;
+ };
+
+ ntn0_en: ntn0-en-state {
+ pins = "gpio67";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ntn1_en: ntn1-en-state {
+ pins = "gpio42";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ upd_1p05_en: upd-1p05-en-state {
+ pins = "gpio179";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ upd_3p3_en: upd-3p3-en-state {
+ pins = "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ upd_ponrst: upd-ponrst-state {
+ pins = "gpio182";
+ function = "gpio";
+ drive-strength = <2>;
+ output-high;
+ };
+
+ tc9563_0_rst: tc9563-0-rst-state {
+ pins = "gpio64";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tc9563_1_rst: tc9563-1-rst-state {
+ pins = "gpio65";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wlan_en: wlan-en-state {
+ pins = "gpio80";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&uart14 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+
+ vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+ vddaon-supply = <&vreg_pmu_aon_0p59>;
+ vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+ vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+ vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+ vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+ };
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1g_1p2>;
+ vccq-max-microamp = <1200000>;
+ vdd-hba-supply = <&vreg_l3g_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1e_0p88>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ phys = <&pm8550b_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3e_1p2>;
+ vdda-pll-supply = <&vreg_l3f_0p88>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+ remote-endpoint = <&redriver_phy_con_ss>;
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
--
2.34.1
^ permalink raw reply related
* [PATCH v2 3/5] arm64: dts: qcom: sm8550: move IPA properties to SoC device tree
From: Joe Sandom via B4 Relay @ 2026-04-07 15:46 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom
In-Reply-To: <20260407-rb5gen2-dts-v2-0-d0c7f447ee73@axon.com>
From: Joe Sandom <jsandom@axon.com>
Move qcom,gsi-loader and memory-region properties from individual board
DTS files into the SoC DTSI, since these are common to all SM8550-based
boards.
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 --
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 --
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 ++
3 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index e821b731bdc496c872703723df02ae9b9b0233b5..b795589385520acd74eecc7701cab82f4f7da200 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -939,8 +939,6 @@ &i2c_master_hub_0 {
};
&ipa {
- qcom,gsi-loader = "self";
- memory-region = <&ipa_fw_mem>;
firmware-name = "qcom/sm8550/ipa_fws.mbn";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index cf63109ff7bf7b6fc827f108e22e82b8b04273c1..f2effa55d8197819175bfd5a89d2fddb20561548 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -818,8 +818,6 @@ fsa4480_sbu_mux: endpoint {
};
&ipa {
- qcom,gsi-loader = "self";
- memory-region = <&ipa_fw_mem>;
firmware-name = "qcom/sm8550/ipa_fws.mbn";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 54308cbde40732da072177eab533582c155df590..d292dfce6b66fff6cff918b8bd6ac0b9cd22c4b3 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2730,6 +2730,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
qcom,smem-state-names = "ipa-clock-enabled-valid",
"ipa-clock-enabled";
+ qcom,gsi-loader = "self";
+ memory-region = <&ipa_fw_mem>;
sram = <&ipa_modem_tables>;
status = "disabled";
--
2.34.1
^ permalink raw reply related
* [PATCH v2 2/5] arm64: dts: qcom: sm8550: add PCIe port labels
From: Joe Sandom via B4 Relay @ 2026-04-07 15:46 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom
In-Reply-To: <20260407-rb5gen2-dts-v2-0-d0c7f447ee73@axon.com>
From: Joe Sandom <jsandom@axon.com>
Add labels to the root port nodes (pcie0_port0, pcie1_port0) to
allow board DTS files to reference them for adding endpoint devices
to each pcie root port.
Update the pcieport0 reference to pcie0_port0 in sm8550-hdk.dts and
sm8550-qrd.dts to match the label rename in sm8550.dtsi.
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index ee13e6136a8259d28540e718851e094f74ead278..e821b731bdc496c872703723df02ae9b9b0233b5 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -1012,7 +1012,7 @@ &pcie0 {
status = "okay";
};
-&pcieport0 {
+&pcie0_port0 {
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 2fb2e0be5e4c6b597f20f332cdf063daa2664205..cf63109ff7bf7b6fc827f108e22e82b8b04273c1 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -912,7 +912,7 @@ &pcie0 {
status = "okay";
};
-&pcieport0 {
+&pcie0_port0 {
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 055ca931c04859f3a312eb9921aeb7a8cc676822..54308cbde40732da072177eab533582c155df590 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2098,7 +2098,7 @@ opp-16000000-3 {
};
};
- pcieport0: pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2300,7 +2300,7 @@ opp-32000000-4 {
};
};
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
--
2.34.1
^ permalink raw reply related
* [PATCH v2 0/5] arm64: dts: qcom: add QCS8550 RB5Gen2 support
From: Joe Sandom via B4 Relay @ 2026-04-07 15:46 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom,
Krzysztof Kozlowski
This series adds device tree support for the Thundercomm RB5Gen2
development kit, based on the Qualcomm QCS8550 chipset.
Patches 1-3 prepares for the RB5gen2 device tree by adding MHI register
regions and port labels to the PCIe controller nodes, as well as moving
common IPA properties into sm8550.dtsi. Then update the existing HDK
and QRD board files accordingly.
Patches 4-5 add the dt-bindings documentation and the board device tree
for the RB5Gen2. This initial submission covers the main board; the vision
mezzanine will be supported in a follow-up series.
Product page:
https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
Changes in v2:
- Lowercase hex in MHI region definitions for pcie0 and pcie1 nodes +
vertical alignment
- Change pcie0 and pcie1 reg-names for one entry per line
- Ensured pcie port labels + changes to sm8550-hdk.dts and sm8550-qrd.dts
are done in a single commit
- Moved IPA gsi-loader and memory-region to sm8550.dtsi since they are common
properties. Reflect changes in sm8550-hdk.dts and sm8550-qrd.dts
- Removed usbhub_reset since this is not required
- Added swctrl-gpios property to wcn7850-pmu
- Split sw_ctrl_default gpio from bt_default grouping and referenced the
pinctrl separately
- Replaced upd_reset regulator-fixed with pinctrl and vddpe-3v3-supply
on pcie0
- Aligned firmware-name values vertically on the quote mark
- Changed cdsp, adsp and modem remoteprocs to .mbn file type instead of
.mdt
- Added remark in rb5gen2 dts commit explaining the rationale for
deleting msi-map in pcie0 and pcie1 nodes
- Link to v1: https://lore.kernel.org/r/20260404-rb5gen2-dts-v1-0-895f8fc494fc@axon.com
---
Joe Sandom (5):
arm64: dts: qcom: sm8550: add PCIe MHI register regions
arm64: dts: qcom: sm8550: add PCIe port labels
arm64: dts: qcom: sm8550: move IPA properties to SoC device tree
dt-bindings: arm: qcom: document QCS8550 RB5Gen2 board
arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
Documentation/devicetree/bindings/arm/qcom.yaml | 6 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 1574 +++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 +-
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 4 +-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 +-
6 files changed, 1603 insertions(+), 12 deletions(-)
---
base-commit: af241225893ac4933bb8f0615f2dfda8ea2326ce
change-id: 20260404-rb5gen2-dts-180cde0b716c
Best regards,
--
Joe Sandom <jsandom@axon.com>
^ permalink raw reply
* [PATCH v2 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions
From: Joe Sandom via B4 Relay @ 2026-04-07 15:46 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Joe Sandom
In-Reply-To: <20260407-rb5gen2-dts-v2-0-d0c7f447ee73@axon.com>
From: Joe Sandom <jsandom@axon.com>
Add the MHI register regions to the pcie0 and pcie1 controller nodes
so that the MHI bus layer can access controller registers directly.
Signed-off-by: Joe Sandom <jsandom@axon.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 912525e9bca6f5e1cbb8887ee0bf9e39650dc4ff..055ca931c04859f3a312eb9921aeb7a8cc676822 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1964,8 +1964,14 @@ pcie0: pcie@1c00000 {
<0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>,
<0 0x60001000 0 0x1000>,
- <0 0x60100000 0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0 0x60100000 0 0x100000>,
+ <0 0x01c03000 0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
@@ -2138,8 +2144,14 @@ pcie1: pcie@1c08000 {
<0x0 0x40000000 0x0 0xf1d>,
<0x0 0x40000f20 0x0 0xa8>,
<0x0 0x40001000 0x0 0x1000>,
- <0x0 0x40100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0x0 0x40100000 0x0 0x100000>,
+ <0x0 0x01c0b000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
--
2.34.1
^ permalink raw reply related
* Re: [RFC PATCH 10/15] fdtdump: Handle unknown tags
From: Luca Ceresoli @ 2026-04-07 15:46 UTC (permalink / raw)
To: Herve Codina
Cc: David Gibson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Ayush Singh, Geert Uytterhoeven, devicetree-compiler, devicetree,
linux-kernel, devicetree-spec, Hui Pu, Ian Ray, Thomas Petazzoni
In-Reply-To: <20260407160345.5adad916@bootlin.com>
On Tue Apr 7, 2026 at 4:03 PM CEST, Herve Codina wrote:
> Hi Luca,
>
> On Wed, 01 Apr 2026 17:15:09 +0200
> "Luca Ceresoli" <luca.ceresoli@bootlin.com> wrote:
>
>> On Tue Feb 10, 2026 at 6:33 PM CET, Herve Codina wrote:
>> > The structured tag value definition introduced recently gives the
>> > ability to ignore unknown tags without any error when they are read.
>> >
>> > Handle those structured tag.
>>
>> How? This sentence is vague, what about:
>>
>> Allow dumping the unknown tags or not based on a command line flag.
>
> Hum indeed but I don't fully agree with your proposal.
>
> The patch adds support for structured tag in fdtdump and introduce the '-u'
> option to dump unknown tags which can be safely ignored.
>
> What do you think about:
>
> The structured tag value definition introduced recently gives the
> ability to ignore unknown tags without any error when they are read.
>
> Add support for those structured tags in fdtdump and introduce a
> command line option to dump unknown tags that should be ignored.
Looks way better now, thanks!
Luca
--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH 5/5] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support
From: Joe Sandom @ 2026-04-07 15:43 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <s4g54pra266y6p2j3f4fps56naw4hm4vzuai5sgpf7sdbbewj2@3j2tkqd3qgdn>
On Tue, Apr 07, 2026 at 06:01:34PM +0300, Dmitry Baryshkov wrote:
> On Tue, Apr 07, 2026 at 12:39:25PM +0100, Joe Sandom wrote:
> > On Sun, Apr 05, 2026 at 12:20:23AM +0300, Dmitry Baryshkov wrote:
> > > On Sat, Apr 04, 2026 at 10:50:58AM +0100, Joe Sandom via B4 Relay wrote:
> > > > +
> > > > + wcn7850-pmu {
> > > > + compatible = "qcom,wcn7850-pmu";
> > > > +
> > > > + pinctrl-names = "default";
> > > > + pinctrl-0 = <&wlan_en>, <&bt_default>, <&pmk8550_sleep_clk>;
> > >
> > > swctrl?
> > Bundled into bt_default since it's tied to BT
>
> It's not. It's either WiFi or BT.
Ack. Will fix in v2.
>
> > >
> > > > +
> > > > + wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
> > > > + bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
> > >
>
> [...]
>
> > > > + iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
> > > > + <0x100 &apps_smmu 0x1401 0x1>,
> > > > + <0x208 &apps_smmu 0x1402 0x1>,
> > > > + <0x210 &apps_smmu 0x1403 0x1>,
> > > > + <0x218 &apps_smmu 0x1404 0x1>,
> > > > + <0x300 &apps_smmu 0x1407 0x1>,
> > > > + <0x400 &apps_smmu 0x1408 0x1>,
> > > > + <0x500 &apps_smmu 0x140c 0x1>,
> > > > + <0x501 &apps_smmu 0x140e 0x1>;
> > > > +
> > > > + /delete-property/ msi-map;
> > >
> > > Why?
> > I tried extending the msi-map to cover the RIDs from the QPS615
> > PCIe switch (matching the iommu-map entries), but this caused
> > ITS MAPD command timeouts. From what I could gather, deleting
> > msi-map forces the PCIe controller to fall back to the internal
> > iMSI-RX module, where this worked properly.
> >
> > For reference, I checked the RB3gen2 since it also uses a QPS615
> > and there doesn't seem to be any msi-map defined (in kodiak.dtsi).
> >
> > Any recommendations to resolve this properly?
>
> Maybe Mani knows. Please mention this in the commit message at least.
>
Will do.
> > >
> > > > +
> > > > + status = "okay";
> > > > +};
> > > > +
>
> --
> With best wishes
> Dmitry
Thanks for the review Dmitry
^ permalink raw reply
* Re: [PATCH v1 12/13] soc: starfive: Add socinfo driver for JHB100 SoC
From: Conor Dooley @ 2026-04-07 15:43 UTC (permalink / raw)
To: Changhuang Liang
Cc: Michael Turquette, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Philipp Zabel, Emil Renner Berthing, Chen Wang,
Inochi Amaoto, Alexey Charkov, Thomas Bogendoerfer, Keguang Zhang,
linux-clk, linux-kernel, devicetree, linux-riscv, Ley Foon Tan
In-Reply-To: <20260403054945.467700-13-changhuang.liang@starfivetech.com>
[-- Attachment #1: Type: text/plain, Size: 4083 bytes --]
On Thu, Apr 02, 2026 at 10:49:44PM -0700, Changhuang Liang wrote:
> Add socinfo driver for JHB100 SoC. Currently available for distinguishing
> between the two reversions, A0 and A1.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> MAINTAINERS | 6 ++
> drivers/soc/Kconfig | 1 +
> drivers/soc/Makefile | 1 +
> drivers/soc/starfive/Kconfig | 6 ++
> drivers/soc/starfive/Makefile | 2 +
> drivers/soc/starfive/socinfo/Kconfig | 11 +++
> drivers/soc/starfive/socinfo/Makefile | 2 +
> drivers/soc/starfive/socinfo/jhb100-socinfo.c | 90 +++++++++++++++++++
> 8 files changed, 119 insertions(+)
> create mode 100644 drivers/soc/starfive/Kconfig
> create mode 100644 drivers/soc/starfive/Makefile
> create mode 100644 drivers/soc/starfive/socinfo/Kconfig
> create mode 100644 drivers/soc/starfive/socinfo/Makefile
> create mode 100644 drivers/soc/starfive/socinfo/jhb100-socinfo.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index eb5f6a383146..32bd94a0b94c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -25325,6 +25325,12 @@ S: Maintained
> F: drivers/reset/starfive/reset-starfive-jhb1*
> F: include/dt-bindings/reset/starfive,jhb1*.h
>
> +STARFIVE JHB100 SOCINFO DRIVER
> +M: Changhuang Liang <changhuang.liang@starfivetech.com>
> +S: Maintained
> +F: Documentation/devicetree/bindings/hwinfo/starfive,jhb100-socinfo.yaml
> +F: drivers/soc/starfive/socinfo/jhb100-socinfo.c
Make sure you add the drivers/soc/starfive directory back to the
starfive soc drivers entry.
> +
> STARFIVE JHB100 SYSCON
> M: Changhuang Liang <changhuang.liang@starfivetech.com>
> S: Maintained
> diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
> index a2d65adffb80..b3b01fc38139 100644
> --- a/drivers/soc/Kconfig
> +++ b/drivers/soc/Kconfig
> @@ -24,6 +24,7 @@ source "drivers/soc/renesas/Kconfig"
> source "drivers/soc/rockchip/Kconfig"
> source "drivers/soc/samsung/Kconfig"
> source "drivers/soc/sophgo/Kconfig"
> +source "drivers/soc/starfive/Kconfig"
> source "drivers/soc/sunxi/Kconfig"
> source "drivers/soc/tegra/Kconfig"
> source "drivers/soc/ti/Kconfig"
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index c9e689080ceb..009f85ff891a 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -30,6 +30,7 @@ obj-y += renesas/
> obj-y += rockchip/
> obj-$(CONFIG_SOC_SAMSUNG) += samsung/
> obj-y += sophgo/
> +obj-y += starfive/
> obj-y += sunxi/
> obj-$(CONFIG_ARCH_TEGRA) += tegra/
> obj-y += ti/
> diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig
> new file mode 100644
> index 000000000000..04b020083d3e
> --- /dev/null
> +++ b/drivers/soc/starfive/Kconfig
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +menu "StarFive SoC (System On Chip) specific Drivers"
> +
> +source "drivers/soc/starfive/socinfo/Kconfig"
> +
> +endmenu
> diff --git a/drivers/soc/starfive/Makefile b/drivers/soc/starfive/Makefile
> new file mode 100644
> index 000000000000..ca1e609b8104
> --- /dev/null
> +++ b/drivers/soc/starfive/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-y += socinfo/
> diff --git a/drivers/soc/starfive/socinfo/Kconfig b/drivers/soc/starfive/socinfo/Kconfig
> new file mode 100644
> index 000000000000..0a20382da5d3
> --- /dev/null
> +++ b/drivers/soc/starfive/socinfo/Kconfig
> @@ -0,0 +1,11 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +config STARFIVE_JHB100_SOCINFO
> + tristate "StarFive JHB100 SoC Information"
> + depends on ARCH_STARFIVE || COMPILE_TEST
> + select SOC_BUS
> + default ARCH_STARFIVE
This can just be default y, since it depends on ARCH_STARFIVE.
> + help
> + Include support for the SoC bus socinfo for the StarFive JHB100 SoC
> + platforms to provide information about the SoC family and variant
> + to user space.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [RFC PATCH 14/15] libfdt: Handle unknown tags on dtb modifications
From: Herve Codina @ 2026-04-07 15:41 UTC (permalink / raw)
To: Luca Ceresoli
Cc: David Gibson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Ayush Singh, Geert Uytterhoeven, devicetree-compiler, devicetree,
linux-kernel, devicetree-spec, Hui Pu, Ian Ray, Thomas Petazzoni
In-Reply-To: <DHHX3IN0BKD7.1CGJV0WXP7P2E@bootlin.com>
Hi Luca,
On Wed, 01 Apr 2026 17:18:54 +0200
"Luca Ceresoli" <luca.ceresoli@bootlin.com> wrote:
...
> > - An unknown tag out of any node (i.e located before the first
> > FDT_BEGIN_NODE or after the last FDT_END_NODE is a global tag
> ^
> missing ')'
> > related to the dtb itself.
>
> Out of curiosity, is there a real use case for global tags after
> FDT_END_NODE?
Well what could be use cases in the future?
We talk about unknown tag and nothing prevent an unknown tag to be after
the last FDT_END_NODE tag in the future.
In my RFC series adding support for addons, I added FDT_IMPORT_SYM tags at
the end of the addon dtb and so a global tags were available after a
FDT_END_NODE tag.
In the end of the commit log introducing FDT_IMPORT_SYM tags [0], the
location of those tags is mentioned:
--- 8< ---
If FDT_IMPORT_SYM tags are present in the dtb, they are present after
the root node definition (i.e. after the FDT_END_NODE related to the
first FDT_BEGIN_NODE).
--- 8< ---
Also in tests related to import symbols [0], you can have a look look at
the tests/metadata_importsyms.dtb.expect file and you will find:
--- 8< ---
--- /dev/null
+++ b/tests/metadata_importsyms.dtb.expect
@@ -0,0 +1,8 @@
+/dts-v1/;
+/addon/;
+
+/ {
+ prop = <0x00000001>;
+};
+// [FDT_IMPORT_SYM] 'base_a' (foo,bar)
+// [FDT_IMPORT_SYM] 'base_b' (foo,baz)
--- 8< ---
This is the expected result when the metadata_importsyms.dtb is dumped using
fdtdump.
fdtdump dumps a dtb in a linear way starting from the beginning to the end
of file.
The FDT_END_NODE tag is represented by the '};' sequence (end of node).
FDT_IMPORT_SYM tags are present after the end of node and so between the
FDT_END_NODE tag and the FDT_END tag.
Not sure I will keep those tags at the end of dtb when I rework the series
on top of "structured tags" but well, this was a real use case.
[0] https://lore.kernel.org/devicetree-compiler/20260112142009.1006236-36-herve.codina@bootlin.com/
[1] https://lore.kernel.org/devicetree-compiler/20260112142009.1006236-37-herve.codina@bootlin.com/
Best regards,
Hervé
^ permalink raw reply
* [PATCH 3/3] riscv: dts: microchip: sort pic64gx i2c nodes alphanumerically
From: Conor Dooley @ 2026-04-07 15:36 UTC (permalink / raw)
To: linux-riscv
Cc: conor, Conor Dooley, Daire McNamara, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, devicetree, linux-kernel
In-Reply-To: <20260407-rely-speculate-dae3a81ea1fc@spud>
From: Conor Dooley <conor.dooley@microchip.com>
The i2c nodes are out of place, sort them where they should be.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../boot/dts/microchip/pic64gx-curiosity-kit.dts | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
index ed3ff03f3b11b..ef5bff3093fc3 100644
--- a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
+++ b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
@@ -89,6 +89,14 @@ &gpio2 {
"DIP4", "USR_IO11", "", "", "SWITCH1", "", "", "";
};
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
&irqmux {
interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
@@ -134,14 +142,6 @@ &mbox {
status = "okay";
};
-&i2c0 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-};
-
&mmc {
bus-width = <4>;
disable-wp;
--
2.53.0
^ permalink raw reply related
* [PATCH 2/3] riscv: dts: microchip: update pic64gx gpio interrupts to better match the SoC
From: Conor Dooley @ 2026-04-07 15:36 UTC (permalink / raw)
To: linux-riscv
Cc: conor, Conor Dooley, Daire McNamara, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, devicetree, linux-kernel
In-Reply-To: <20260407-rely-speculate-dae3a81ea1fc@spud>
From: Conor Dooley <conor.dooley@microchip.com>
Just like PolarFire SoC, the same issues with GPIO interrupts exist in
the pic64gx, due to their similarity. Yoinking from the commit message
for the same change for PolarFire SoC:
There are 3 GPIO controllers on this SoC, of which:
- GPIO controller 0 has 14 GPIOs
- GPIO controller 1 has 24 GPIOs
- GPIO controller 2 has 32 GPIOs
All GPIOs are capable of generating interrupts, for a total of 70.
There are only 41 IRQs available however, so a configurable mux is used
to ensure all GPIOs can be used for interrupt generation.
38 of the 41 interrupts are in what the documentation calls "direct
mode", as they provide an exclusive connection from a GPIO to the PLIC.
The 3 remaining interrupts are used to mux the interrupts which do not
have a exclusive connection, one for each GPIO controller.
The mux was overlooked when the bindings and driver were originally
written for the GPIO controllers on Polarfire SoC, and the interrupts
property in the GPIO nodes used to try and convey what the mapping was.
Instead, the mux should be a device in its own right, and the GPIO
controllers should be connected to it, rather than to the PLIC.
Now that a binding exists for that mux, fix the inaccurate description
of the interrupt controller hierarchy.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../dts/microchip/pic64gx-curiosity-kit.dts | 47 ++++++++++++-------
arch/riscv/boot/dts/microchip/pic64gx.dtsi | 32 +++++++++++--
2 files changed, 58 insertions(+), 21 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
index 2f2ccd77af30a..ed3ff03f3b11b 100644
--- a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
+++ b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
@@ -63,10 +63,6 @@ hss: hss-buffer@bfc00000 {
};
&gpio0 {
- interrupts = <13>, <14>, <15>, <16>,
- <17>, <18>, <19>, <20>,
- <21>, <22>, <23>, <24>,
- <25>, <26>;
status ="okay";
gpio-line-names =
"", "", "", "", "", "", "", "",
@@ -74,12 +70,6 @@ &gpio0 {
};
&gpio1 {
- interrupts = <27>, <28>, <29>, <30>,
- <31>, <32>, <33>, <34>,
- <35>, <36>, <37>, <38>,
- <39>, <40>, <41>, <42>,
- <43>, <44>, <45>, <46>,
- <47>, <48>, <49>, <50>;
status ="okay";
gpio-line-names =
"", "", "LED1", "LED2", "LED3", "LED4", "LED5", "LED6",
@@ -88,14 +78,6 @@ &gpio1 {
};
&gpio2 {
- interrupts = <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>;
pinctrl-names = "default";
pinctrl-0 = <&mdio1_gpio>, <&spi0_gpio>, <&can0_gpio>, <&pcie_gpio>,
<&qspi_gpio>, <&uart3_gpio>, <&uart4_gpio>, <&can1_gpio>;
@@ -107,6 +89,35 @@ &gpio2 {
"DIP4", "USR_IO11", "", "", "SWITCH1", "", "", "";
};
+&irqmux {
+ interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
+ <3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
+ <6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
+ <9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
+ <12 &plic 25>, <13 &plic 26>,
+
+ <32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
+ <35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
+ <38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
+ <41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
+ <44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
+ <47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
+ <50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
+ <53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
+
+ <64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
+ <67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
+ <70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
+ <73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
+ <76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
+ <79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
+ <82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
+ <85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
+ <88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
+ <91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
+ <94 &plic 53>, <95 &plic 53>;
+};
+
&mac0 {
status = "okay";
phy-mode = "sgmii";
diff --git a/arch/riscv/boot/dts/microchip/pic64gx.dtsi b/arch/riscv/boot/dts/microchip/pic64gx.dtsi
index e9ec376b1776b..5cf3e3de0e067 100644
--- a/arch/riscv/boot/dts/microchip/pic64gx.dtsi
+++ b/arch/riscv/boot/dts/microchip/pic64gx.dtsi
@@ -295,6 +295,14 @@ mss_top_sysreg: syscon@20002000 {
#size-cells = <1>;
#reset-cells = <1>;
+ irqmux: interrupt-controller@54 {
+ compatible = "microchip,pic64gx-irqmux", "microchip,mpfs-irqmux";
+ reg = <0x54 0x4>;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x7f>;
+ };
+
iomux0: pinctrl@200 {
compatible = "microchip,pic64gx-pinctrl-iomux0",
"microchip,mpfs-pinctrl-iomux0";
@@ -484,9 +492,13 @@ mac1: ethernet@20112000 {
gpio0: gpio@20120000 {
compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
reg = <0x0 0x20120000 0x0 0x1000>;
- interrupt-parent = <&plic>;
+ interrupt-parent = <&irqmux>;
interrupt-controller;
#interrupt-cells = <1>;
+ interrupts = <0>, <1>, <2>, <3>,
+ <4>, <5>, <6>, <7>,
+ <8>, <9>, <10>, <11>,
+ <12>, <13>;
clocks = <&clkcfg CLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
@@ -497,9 +509,15 @@ gpio0: gpio@20120000 {
gpio1: gpio@20121000 {
compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
reg = <0x0 0x20121000 0x0 0x1000>;
- interrupt-parent = <&plic>;
+ interrupt-parent = <&irqmux>;
interrupt-controller;
#interrupt-cells = <1>;
+ interrupts = <32>, <33>, <34>, <35>,
+ <36>, <37>, <38>, <39>,
+ <40>, <41>, <42>, <43>,
+ <44>, <45>, <46>, <47>,
+ <48>, <49>, <50>, <51>,
+ <52>, <53>, <54>, <55>;
clocks = <&clkcfg CLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
@@ -510,9 +528,17 @@ gpio1: gpio@20121000 {
gpio2: gpio@20122000 {
compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
reg = <0x0 0x20122000 0x0 0x1000>;
- interrupt-parent = <&plic>;
+ interrupt-parent = <&irqmux>;
interrupt-controller;
#interrupt-cells = <1>;
+ interrupts = <64>, <65>, <66>, <67>,
+ <68>, <69>, <70>, <71>,
+ <72>, <73>, <74>, <75>,
+ <76>, <77>, <78>, <79>,
+ <80>, <81>, <82>, <83>,
+ <84>, <85>, <86>, <87>,
+ <88>, <89>, <90>, <91>,
+ <92>, <93>, <94>, <95>;
clocks = <&clkcfg CLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
--
2.53.0
^ permalink raw reply related
* [PATCH 1/3] riscv: dts: microchip: add tsu clock to macb on pic64gx
From: Conor Dooley @ 2026-04-07 15:36 UTC (permalink / raw)
To: linux-riscv
Cc: conor, Conor Dooley, Daire McNamara, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, devicetree, linux-kernel
In-Reply-To: <20260407-rely-speculate-dae3a81ea1fc@spud>
From: Conor Dooley <conor.dooley@microchip.com>
In increment mode, the tsu clock for the macb is provided separately to
the pck, usually the same clock as the reference to the rtc provided by
an off-chip oscillator. pclk is 150 MHz typically, and the reference is
either 100 MHz or 125 MHz, so having the tsu clock is required for
correct rate selection.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/pic64gx.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/pic64gx.dtsi b/arch/riscv/boot/dts/microchip/pic64gx.dtsi
index c164d7bc270a2..e9ec376b1776b 100644
--- a/arch/riscv/boot/dts/microchip/pic64gx.dtsi
+++ b/arch/riscv/boot/dts/microchip/pic64gx.dtsi
@@ -459,8 +459,8 @@ mac0: ethernet@20110000 {
interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
/* Filled in by a bootloader */
local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
- clock-names = "pclk", "hclk";
+ clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>;
+ clock-names = "pclk", "hclk", "tsu_clk";
resets = <&mss_top_sysreg CLK_MAC0>;
status = "disabled";
};
@@ -475,8 +475,8 @@ mac1: ethernet@20112000 {
interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
/* Filled in by a bootloader */
local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
- clock-names = "pclk", "hclk";
+ clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>;
+ clock-names = "pclk", "hclk", "tsu_clk";
resets = <&mss_top_sysreg CLK_MAC1>;
status = "disabled";
};
--
2.53.0
^ permalink raw reply related
* [PATCH 0/3] pic64gx semantic conflict "fixes"
From: Conor Dooley @ 2026-04-07 15:36 UTC (permalink / raw)
To: linux-riscv
Cc: conor, Conor Dooley, Daire McNamara, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, devicetree, linux-kernel
From: Conor Dooley <conor.dooley@microchip.com>
CC: Conor Dooley <conor.dooley@microchip.com>
CC: Daire McNamara <daire.mcnamara@microchip.com>
CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
CC: Paul Walmsley <pjw@kernel.org>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: Albert Ou <aou@eecs.berkeley.edu>
CC: Alexandre Ghiti <alex@ghiti.fr>
CC: linux-riscv@lists.infradead.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
Conor Dooley (3):
riscv: dts: microchip: add tsu clock to macb on pic64gx
riscv: dts: microchip: update pic64gx gpio interrupts to better match
the SoC
riscv: dts: microchip: sort pic64gx i2c nodes alphanumerically
.../dts/microchip/pic64gx-curiosity-kit.dts | 63 +++++++++++--------
arch/riscv/boot/dts/microchip/pic64gx.dtsi | 40 +++++++++---
2 files changed, 70 insertions(+), 33 deletions(-)
--
2.53.0
^ permalink raw reply
* [PATCH 2/2] arm64: dts: renesas: r9a09g056: Add #mux-state-cells to usb20phyrst
From: Tommaso Merciai @ 2026-04-07 15:34 UTC (permalink / raw)
To: tomm.merciai, peda, p.zabel
Cc: linux-renesas-soc, biju.das.jz, Tommaso Merciai,
Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, linux-kernel
In-Reply-To: <cover.1775575276.git.tommaso.merciai.xr@bp.renesas.com>
The renesas,rzv2h-usb2phy-reset binding schema defines #mux-state-cells
as a required property. Add it to the usb20phyrst node to fix the
following warnings:
"arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-emmc.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-sd.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property"
Fixes: 6a1b6f7e56dc ("dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property")
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
index 40525470194e..7ccddd6a4a9a 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -1327,6 +1327,7 @@ usb20phyrst: usb20phy-reset@15830000 {
resets = <&cpg 0xaf>;
power-domains = <&cpg>;
#reset-cells = <0>;
+ #mux-state-cells = <1>;
status = "disabled";
};
--
2.43.0
^ permalink raw reply related
* [PATCH 1/2] arm64: dts: renesas: r9a09g057: Add #mux-state-cells to usb2{0,1}phyrst
From: Tommaso Merciai @ 2026-04-07 15:34 UTC (permalink / raw)
To: tomm.merciai, peda, p.zabel
Cc: linux-renesas-soc, biju.das.jz, Tommaso Merciai,
Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, linux-kernel
In-Reply-To: <cover.1775575276.git.tommaso.merciai.xr@bp.renesas.com>
The renesas,rzv2h-usb2phy-reset binding schema defines #mux-state-cells
as a required property. Add it to the usb20phyrst and usb21phyrst nodes
to fix the following warnings:
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-emmc.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-emmc.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-sd.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-sd.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
Fixes: 6a1b6f7e56dc ("dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property")
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 9581af58024e..6f6fe5f36bef 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -1345,6 +1345,7 @@ usb20phyrst: usb20phy-reset@15830000 {
resets = <&cpg 0xaf>;
power-domains = <&cpg>;
#reset-cells = <0>;
+ #mux-state-cells = <1>;
status = "disabled";
};
@@ -1355,6 +1356,7 @@ usb21phyrst: usb21phy-reset@15840000 {
resets = <&cpg 0xaf>;
power-domains = <&cpg>;
#reset-cells = <0>;
+ #mux-state-cells = <1>;
status = "disabled";
};
--
2.43.0
^ permalink raw reply related
* [PATCH 0/2] arm64: dts: renesas: Add missing #mux-state-cells to usb2phy-reset nodes
From: Tommaso Merciai @ 2026-04-07 15:34 UTC (permalink / raw)
To: tomm.merciai, peda, p.zabel
Cc: linux-renesas-soc, biju.das.jz, Tommaso Merciai,
Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, linux-kernel
Dear All,
The renesas,rzv2h-usb2phy-reset binding schema defines #mux-state-cells as a
required property. Add it to the USB2 PHY reset nodes in the RZ/V2H and RZ/V2N
device trees to fix dtbs_check warnings.
"arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-emmc.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk-cn15-sd.dtb: usb20phy-reset@15830000 (renesas,r9a09g056-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-emmc.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-emmc.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-sd.dtb: usb20phy-reset@15830000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
"arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk-cn15-sd.dtb: usb21phy-reset@15840000 (renesas,r9a09g057-usb2phy-reset): '#mux-state-cells' is a required property"
Kind Regards,
Tommaso
Tommaso Merciai (2):
arm64: dts: renesas: r9a09g057: Add #mux-state-cells to
usb2{0,1}phyrst
arm64: dts: renesas: r9a09g056: Add #mux-state-cells to usb20phyrst
arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 1 +
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 2 ++
2 files changed, 3 insertions(+)
--
2.43.0
^ permalink raw reply
* [PATCH v1] dt-bindings: soc: microchip: document irqmux on pic64gx
From: Conor Dooley @ 2026-04-07 15:29 UTC (permalink / raw)
To: linux-riscv
Cc: conor, Conor Dooley, Daire McNamara, Rob Herring,
Krzysztof Kozlowski, devicetree, linux-kernel
From: Conor Dooley <conor.dooley@microchip.com>
Being practically identical to PolarFire SoC, pic64gx has a irqmux
that's entirely compatible with that on mpfs.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
CC: Conor Dooley <conor.dooley@microchip.com>
CC: Daire McNamara <daire.mcnamara@microchip.com>
CC: Rob Herring <robh@kernel.org>
CC: Krzysztof Kozlowski <krzk+dt@kernel.org>
CC: linux-riscv@lists.infradead.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org
---
.../bindings/soc/microchip/microchip,mpfs-irqmux.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml
index 51164772724f5..419b32e2df936 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml
@@ -26,7 +26,11 @@ description: |
properties:
compatible:
- const: microchip,mpfs-irqmux
+ oneOf:
+ - items:
+ - const: microchip,pic64gx-irqmux
+ - const: microchip,mpfs-irqmux
+ - const: microchip,mpfs-irqmux
reg:
maxItems: 1
--
2.53.0
^ permalink raw reply related
* [PATCH v10 2/3] riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2
From: Han Gao @ 2026-04-07 15:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao,
Vincent Legoll
In-Reply-To: <cover.1775575436.git.gaohan@iscas.ac.cn>
Define the DC power input and the 4v power as fixed regulator supplies.
Define the SpacemiT P1 PMIC voltage regulators and their constraints.
Co-developed-by: Chukun Pan <amadeus@jmu.edu.cn>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Tested-by: Vincent Legoll <legoll@online.fr> # OrangePi-RV2
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/spacemit/k1-orangepi-rv2.dts | 131 ++++++++++++++++++
1 file changed, 131 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
index 57ec1cc32b03..f7a1dadaa95f 100644
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
@@ -23,6 +23,25 @@ chosen {
stdout-path = "serial0";
};
+ vcc_5v0: regulator-vcc-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_5v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc4v0: regulator-vcc4v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc4v0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ vin-supply = <&vcc_5v0>;
+ };
+
leds {
compatible = "gpio-leds";
@@ -91,6 +110,118 @@ &i2c8 {
pinctrl-names = "default";
pinctrl-0 = <&i2c8_cfg>;
status = "okay";
+
+ pmic@41 {
+ compatible = "spacemit,p1";
+ reg = <0x41>;
+ interrupts = <64>;
+ vin1-supply = <&vcc4v0>;
+ vin2-supply = <&vcc4v0>;
+ vin3-supply = <&vcc4v0>;
+ vin4-supply = <&vcc4v0>;
+ vin5-supply = <&vcc4v0>;
+ vin6-supply = <&vcc4v0>;
+ aldoin-supply = <&vcc4v0>;
+ dldoin1-supply = <&buck5>;
+ dldoin2-supply = <&buck5>;
+
+ regulators {
+ buck1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck3_1v8: buck3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck4_3v3: buck4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck5: buck5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ aldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ aldo2 {
+ /* not connected */
+ };
+
+ aldo3 {
+ /* not connected */
+ };
+
+ aldo4 {
+ /* not connected */
+ };
+
+ dldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ dldo2 {
+ /* not connected */
+ };
+
+ dldo3 {
+ /* not connected */
+ };
+
+ dldo4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo7 {
+ /* not connected */
+ };
+ };
+ };
};
&uart0 {
--
2.47.3
^ permalink raw reply related
* [PATCH v10 3/3] riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2
From: Han Gao @ 2026-04-07 15:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao,
Vincent Legoll
In-Reply-To: <cover.1775575436.git.gaohan@iscas.ac.cn>
Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the
OrangePi RV2 board.
The board utilizes a Genesys Logic GL3523 USB3.0 hub.
Define a 3.3v fixed voltage regulator for PCIe and enable PCIe and
PHY-related Device Tree nodes for the OrangePi RV2.
Co-developed-by: Chukun Pan <amadeus@jmu.edu.cn>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Tested-by: Vincent Legoll <legoll@online.fr> # OrangePi-RV2
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/spacemit/k1-orangepi-rv2.dts | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
index f7a1dadaa95f..3a829e3c9cbc 100644
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
@@ -23,6 +23,16 @@ chosen {
stdout-path = "serial0";
};
+ pcie_vcc3v3: regulator-pcie-vcc3v3 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio K1_GPIO(116) GPIO_ACTIVE_HIGH>;
+ regulator-name = "pcie_vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_5v0>;
+ };
+
vcc_5v0: regulator-vcc-5v0 {
compatible = "regulator-fixed";
regulator-name = "vcc_5v0";
@@ -42,6 +52,16 @@ vcc4v0: regulator-vcc4v0 {
vin-supply = <&vcc_5v0>;
};
+ vcc5v0_usb30: regulator-vcc5v0-usb30 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc5v0_usb30";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_5v0>;
+ };
+
leds {
compatible = "gpio-leds";
@@ -54,6 +74,10 @@ led1 {
};
};
+&combo_phy {
+ status = "okay";
+};
+
ð0 {
phy-handle = <&rgmii0>;
phy-mode = "rgmii-id";
@@ -224,8 +248,64 @@ dldo7 {
};
};
+&pcie1_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_3_cfg>;
+ status = "okay";
+};
+
+&pcie1_port {
+ phys = <&pcie1_phy>;
+ vpcie3v3-supply = <&pcie_vcc3v3>;
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_4_cfg>;
+ status = "okay";
+};
+
+&pcie2_port {
+ phys = <&pcie2_phy>;
+ vpcie3v3-supply = <&pcie_vcc3v3>;
+};
+
+&pcie2 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
+
+&usbphy2 {
+ status = "okay";
+};
+
+&usb_dwc3 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ vbus-supply = <&vcc5v0_usb30>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb5e3,610";
+ reg = <0x1>;
+ peer-hub = <&hub_3_0>;
+ vdd-supply = <&vcc_5v0>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb5e3,620";
+ reg = <0x2>;
+ peer-hub = <&hub_2_0>;
+ vdd-supply = <&vcc_5v0>;
+ };
+};
--
2.47.3
^ permalink raw reply related
* [PATCH v10 1/3] riscv: dts: spacemit: Enable i2c8 adapter for OrangePi RV2
From: Han Gao @ 2026-04-07 15:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao,
Vincent Legoll
In-Reply-To: <cover.1775575436.git.gaohan@iscas.ac.cn>
The adapter is used to access the SpacemiT P1 PMIC present in this board.
Tested-by: Vincent Legoll <legoll@online.fr> # OrangePi-RV2
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
index 7b7331cb3c72..57ec1cc32b03 100644
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
@@ -87,6 +87,12 @@ &pdma {
status = "okay";
};
+&i2c8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c8_cfg>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
--
2.47.3
^ permalink raw reply related
* [PATCH v10 0/3] riscv: dts: spacemit: Add PMIC regulators usb pcie
From: Han Gao @ 2026-04-07 15:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan, Chukun Pan
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Han Gao, Han Gao
Changes in v10:
- patch 3:
add vin-supply in pcie_vcc3v3
reorder vcc5v0_usb30
remove vpcie3v3-supply form pcie1
- Link to v9: https://lore.kernel.org/linux-riscv/cover.1775417019.git.gaohan@iscas.ac.cn
Han Gao (3):
riscv: dts: spacemit: Enable i2c8 adapter for OrangePi RV2
riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2
riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2
.../boot/dts/spacemit/k1-orangepi-rv2.dts | 217 ++++++++++++++++++
1 file changed, 217 insertions(+)
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
prerequisite-patch-id: ef6e9c7b5854d0c08066b72f9a7868db8c2140eb
prerequisite-patch-id: cfe3800f8c791ec4c63e070af9628e88e0fc31b9
prerequisite-patch-id: b76493e625ae257c8adcd67874178458420e4d47
prerequisite-patch-id: 88e01dc92c83bd88ddeb78891d3088209fed8d6b
prerequisite-patch-id: 60336d10ab8322c70596d0f046b6b5c54bb24b54
prerequisite-patch-id: 68c4d869548687dc115dd91e2ffb8f4c11482d86
prerequisite-patch-id: fdadcf964c2cb3406160edb579d99a8d5695f8e6
prerequisite-patch-id: 73b9e745338b0499b849fa4f7f9508987ab39a59
prerequisite-patch-id: cd26770c2160c3c31a406bd8a6b01ab666180ae0
prerequisite-patch-id: e5dfddc32cefae195692da8b80e19adf086e4ad7
prerequisite-patch-id: 7fd53cbe4977598f26148a4bb1cf692bbdb79a09
prerequisite-patch-id: 96ebac57bb29619b97fe95422206a685825618e9
prerequisite-patch-id: 00fac16b52f60383db3140e2885f3f7f8d14dd1a
prerequisite-patch-id: 3b7a60047b922c48e93599f621cb738856f42354
prerequisite-patch-id: 275c030b963be05dd1041451f539a130ce614277
prerequisite-patch-id: 93963424b0871e64276af0e0b2199b52e29b4603
prerequisite-patch-id: 8383188b1c01ed6280629faaa29c37d699ade241
prerequisite-patch-id: 5f8126b912b924d63d4a1e0c5eb42d212eb0d369
prerequisite-patch-id: e80af628a2e0b5f2eeb3cb1b5e7133d08bdd2c4e
prerequisite-patch-id: 0234a6dca15eb91f98a45a46604ce5b4935048a5
--
2.47.3
^ permalink raw reply
* Re: [PATCH v3] arm64: dts: imx8mp: Add DT overlays for DH i.MX8M Plus DHCOM SoM and boards
From: Marek Vasut @ 2026-04-07 15:26 UTC (permalink / raw)
To: linux-arm-kernel, Frank Li
Cc: Christoph Niedermaier, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, devicetree, imx, kernel, linux-kernel
In-Reply-To: <20260326044411.222907-1-marex@nabladev.com>
On 3/26/26 5:43 AM, Marek Vasut wrote:
> Add DT overlays to support DH i.MX8M Plus DHCOM SoM variants and carrier
> board expansion modules. The following DT overlays are implemented:
> - SoM:
> - DH 660-x00 SoM with 1xRMII PHY
> - DH 660-x00 SoM with 2xRMII PHY
> - PDK2:
> - DH 505-200 Display board in edge connector X12 via direct LVDS
> - DH 531-100 SPI/I2C board in header X21
> - DH 531-200 SPI/I2C board in header X22
> - DH 560-200 Display board in edge connector X12
> - PDK3:
> - DH 505-200 Display board in edge connector X36 via direct LVDS
> - DH 531-100 SPI/I2C board in header X40
> - DH 531-200 SPI/I2C board in header X41
> - DH 560-300 Display board in edge connector X36
> - EA muRata 2AE M.2 A/E-Key card in connector X20
> - NXP SPF-29853-C1 MINISASTOCSI with OV5640 sensor in connector X31
> - NXP SPF-29853-C1 MINISASTOCSI with OV5640 sensor in connector X29
> - PicoITX:
> - DH 626-100 Display board in edge connector X2
Hello Frank,
I know I was sending quite a few DTOs recently. Is this set still on
your review list, or was this one missed ?
Thank you for reviewing the DTOs so actively, it really helps a lot !
^ permalink raw reply
* Re: [PATCH RFC 0/2] arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A
From: Xilin Wu @ 2026-04-07 15:22 UTC (permalink / raw)
To: Andriy Sharandakov, Konrad Dybcio, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong,
Viken Dadhaniya, Ram Kumar Dwivedi
In-Reply-To: <9f04ae8e-e15a-414f-a436-987d02d31cdd@gmail.com>
On 4/7/2026 6:16 PM, Andriy Sharandakov wrote:
> On 12.09.2025 11:15, Konrad Dybcio wrote:
>> On 9/12/25 11:04 AM, Xilin Wu wrote:
>>> On 2025/9/12 16:56:04, Konrad Dybcio wrote:
>>>> On 9/12/25 10:03 AM, Xilin Wu wrote:
>>>>> Radxa Dragon Q6A (https://docs.radxa.com/en/dragon/q6a) is a single
>>>>> board
>>>>> computer, based on the Qualcomm QCS6490 platform.
>>>>>
>>>>> The board ships with a modified version of the Qualcomm Linux boot
>>>>> firmware, which is stored on the onboard SPI NOR flash. This allows
>>>>> booting standard EFI-based bootloaders from SD/eMMC/USB/UFS/NVMe. It
>>>>> supports replaceable UFS 3.1/eMMC modules for easy user upgrades.
>>>>>
>>>>> The board schematic is available at [1].
>>>>>
>>>>> Features enabled and working:
>>>>>
>>>>> - USB-A 3.0 port (depends on [2])
>>>>> - Three USB-A 2.0 ports
>>>>> - RTL8111K Ethernet connected to PCIe0
>>>>> - UFS 3.1 module (depends on [3])
>>>>> - eMMC module
>>>>> - SD card
>>>>> - M.2 M-Key 2230 PCIe 3.0 x2
>>>>> - HDMI 2.0 port including audio (depends on [2])
>>>>> - Configurable I2C/SPI/UART from 40-Pin GPIO (depends on [4])
>>>>> - Headphone jack
>>>>> - Onboard thermal sensors
>>>>> - QSPI controller for updating boot firmware
>>>>> - ADSP remoteproc (Type-C and charging features disabled in firmware)
>>>>> - CDSP remoteproc (for AI applications using QNN)
>>>>> - Venus video encode and decode accelerator
>>>>
>>>> You have a number of features that depend on several other series, and
>>>> as Krzysztof pointed out this is difficult to merge/review.. Could you
>>>> please create a "linux-next/master-ready" version of this series and
>>>> separate the changes for which the dependencies are unmet, putting them
>>>> at the end? This way we can take at least some of your diff.
>>>>
>>>> If you still want review on them, you can also send them as [PATCH DNM]
>>>> or so
>>>>
>>>> Konrad
>>>>
>>>
>>> Thanks for the suggestion. I think I can separate the changes that
>>> have unmet dependencies, and mark them as DNM. Can I send the new
>>> series now, or am I supposed to wait for a few days?
>>
>> Since we can't do much with this one, please apply Krzysztof's review
>> comments and tags and feel free to resend
>>
>> Konrad
>
> Xilin,
>
> The prerequisite for the "USB-A 3.0 port (depends on [2])" feature has
> been added - https://github.com/torvalds/linux/commit/
> f842daf740114a8783be566219db34c6a0f1d02c
>
> Could you please check and resend the USB 3.0 port feature?
>
> Thanks.
>
> Best regards,
> Andriy
>
>
Hi Andriy,
Thanks for reminding me. A new series has been sent just now.
--
Best regards,
Xilin Wu <sophon@radxa.com>
^ permalink raw reply
* [PATCH 11/12] ASoC: dt-bindings: google,sc7280-herobrine: Add Radxa Dragon Q6A sound card
From: Xilin Wu @ 2026-04-07 15:20 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Dmitry Baryshkov, Liam Girdwood, Mark Brown,
Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound, Xilin Wu
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-0-14aca49dde3d@radxa.com>
The Radxa Dragon Q6A can boot in EL2, allowing the kernel to access the
LPASS hardware directly. Add the compatible for it to the bindings.
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
.../devicetree/bindings/sound/google,sc7280-herobrine.yaml | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml b/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml
index cdcd7c6f21eb..cd87dfe20618 100644
--- a/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml
+++ b/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml
@@ -17,8 +17,13 @@ allOf:
properties:
compatible:
- enum:
- - google,sc7280-herobrine
+ oneOf:
+ - enum:
+ - google,sc7280-herobrine
+ - items:
+ - enum:
+ - radxa,dragon-q6a-sndcard
+ - const: google,sc7280-herobrine
"#address-cells":
const: 1
--
2.53.0
^ permalink raw reply related
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