* [PATCH 0/4] arm64: dts: qcom: sdm845-lg: Devicetree followup
From: Paul Sajna @ 2026-04-09 2:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jeff Johnson, Dmitry Baryshkov, David Heidelberg
Cc: linux-arm-msm, devicetree, linux-kernel, phone-devel,
~postmarketos/upstreaming, Paul Sajna, Konrad Dybcio
Re-send 3 patches that got dropped from 20260331-judyln-dts-v7-0-87217b15fefb@postmarketos.org
(https://lore.kernel.org/linux-arm-msm/177541802142.2061229.9094394728986735362.b4-ty@kernel.org/)
Re-enable qcom,snoc-host-cap-skip-quirk
To:
Signed-off-by: Paul Sajna <sajattack@postmarketos.org>
---
Paul Sajna (4):
arm64: dts: qcom: sdm845-lg-common: Add camera flash
arm64: dts: qcom: sdm845-lg-common: Change ipa gsi-loader to 'self', add memory-region
arm64: dts: qcom: sdm845-lg-{judyln, judyp}: Reference memory region in fb
arm64: dts: qcom: sdm845-lg: Enable qcom,snoc-host-cap-skip-quirk
arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 22 +++++++++++++++++++---
arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts | 4 ++--
arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts | 4 ++--
3 files changed, 23 insertions(+), 7 deletions(-)
---
base-commit: db7efce4ae23ad5e42f5f55428f529ff62b86fab
change-id: 20260408-judyln-followup-e0201f3d27e9
prerequisite-message-id: 20260407-skip-host-cam-qmi-req-v5-0-dfa8a05c6538@ixit.cz
prerequisite-patch-id: ac24dd000a2ecf55cb4da9fbc62e4834530036fd
prerequisite-patch-id: 9c69ab29256c15a0e8ac1c3b9ef64b27661c7815
prerequisite-patch-id: bd62d277785dc0a3bed4beff8d22d7bfd7e491fb
Best regards,
--
Paul Sajna <sajattack@postmarketos.org>
^ permalink raw reply
* Re: Re: [PATCH v1] dt-bindings: usb: Fix EIC7700 USB reset's issue
From: Hang Cao @ 2026-04-09 2:41 UTC (permalink / raw)
To: Krzysztof Kozlowski, Conor Dooley
Cc: gregkh, robh, krzk+dt, conor+dt, Thinh.Nguyen, p.zabel,
linux-kernel, linux-usb, devicetree, ningyu, linmin,
pinkesh.vaghela
In-Reply-To: <20260408-designed-broadband-332044a2d1fb@spud>
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Hi, Krzysztof & Conor
No, U-Boot will NOT be affected. Sorry for the misunderstanding due to the
inaccurate commit message.
I will send the next version with the improved commit message below:
The EIC7700 USB requires a USB PHY reset operation; otherwise, the USB will
not work. The reason why the USB driver that was applied can work properly is
that the USB PHY has already been reset in ESWIN's U-Boot.
However, the proper functioning of the USB driver should not be dependent on
the bootloader. Therefore, it is necessary to incorporate the USB PHY reset
signal into the DT bindings.
This patch does not introduce any backward incompatibility since the dts is
not upstream yet. As array of reset operations are used in the driver,
no modifications to the USB controller driver are needed.
Best regards,
Hang
> -----Original Messages-----
> From: "Conor Dooley" <conor@kernel.org>
> Send time:Thursday, 09/04/2026 01:24:34
> To: "Krzysztof Kozlowski" <krzk@kernel.org>
> Cc: caohang@eswincomputing.com, gregkh@linuxfoundation.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Thinh.Nguyen@synopsys.com, p.zabel@pengutronix.de, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com
> Subject: Re: [PATCH v1] dt-bindings: usb: Fix EIC7700 USB reset's issue
>
> On Wed, Apr 08, 2026 at 09:48:43AM +0200, Krzysztof Kozlowski wrote:
> > On Tue, Apr 07, 2026 at 02:17:02PM +0800, caohang@eswincomputing.com wrote:
> > > From: Hang Cao <caohang@eswincomputing.com>
> > >
> > > The EIC7700 USB controller requires a USB PHY RESET operation.PHY RESET
> >
> > Missing space after full stop.
> >
> > > operation was missed in the verification version, as it was performed in
> > > ESWIN's U-Boot.
> > >
> > > If a non-ESWIN provided loader is used, this issue will occur, resulting
> > > in USB not work.This patch does not introduce any backward incompatibility
> > > since the dts is not upstream yet.
> >
> > So U-Boot will be affected, no?
>
> Is it even really affected? I don't think there's any bootloader for this
> other than what ESWIN is shipping downstream, outside of people's development
> trees. And any software that expected two resets will work just as badly as
> it always did when a third one is added.
>
> > And even if DTS is not upstreamed, what about all out of tree DTS?
> > This is an already released ABI, so at least explain that driver does
> > not care about resets here and grabs them all.
> >
> > >
> > > Fixes: c640a4239db5 ("dt-bindings: usb: Add ESWIN EIC7700 USB controller")
> >
> >
> > Best regards,
> > Krzysztof
> >
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^ permalink raw reply
* RE: [PATCH V11 04/12] PCI: imx6: Add support for parsing the reset property in new Root Port binding
From: Sherry Sun @ 2026-04-09 2:40 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
Frank Li, s.hauer@pengutronix.de, kernel@pengutronix.de,
festevam@gmail.com, lpieralisi@kernel.org, kwilczynski@kernel.org,
bhelgaas@google.com, Hongxing Zhu, l.stach@pengutronix.de,
imx@lists.linux.dev, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <t5x45nyn6lw7cofzj2rec5j6z2ml6kve2hvzeeastdrv4hilsu@ujhkmltpp5ky>
> Subject: Re: [PATCH V11 04/12] PCI: imx6: Add support for parsing the reset
> property in new Root Port binding
>
> On Wed, Apr 08, 2026 at 08:34:03AM +0000, Sherry Sun wrote:
> > > On Tue, Apr 07, 2026 at 06:41:46PM +0800, Sherry Sun wrote:
> > > > The current DT binding for pci-imx6 specifies the 'reset-gpios'
> > > > property in the host bridge node. However, the PERST# signal
> > > > logically belongs to individual Root Ports rather than the host bridge
> itself.
> > > > This becomes important when supporting PCIe KeyE connector and PCI
> > > > power control framework for pci-imx6 driver, which requires
> > > > properties to be specified in Root Port nodes.
> > > >
> > > > Add support for parsing 'reset-gpios' from Root Port child nodes
> > > > using the common helper pci_host_common_parse_ports(), and update
> > > > the reset GPIO handling to use the parsed port list from
> > > > bridge->ports. To maintain DT backwards compatibility, fallback to
> > > > the legacy method of parsing the host bridge node if the reset
> > > > property is not present in the Root Port node.
> > > >
> > > > Since now the reset GPIO is obtained with GPIOD_ASIS flag, it may
> > > > be in input mode, using gpiod_direction_output() instead of
> > > > gpiod_set_value_cansleep() to ensure the reset GPIO is properly
> > > > configured as output before setting its value.
> > > >
> > > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > > > ---
> > > > drivers/pci/controller/dwc/pci-imx6.c | 75
> > > > +++++++++++++++++++++------
> > > > 1 file changed, 60 insertions(+), 15 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > > > b/drivers/pci/controller/dwc/pci-imx6.c
> > > > index d99da7e42590..dd8f9c0fcec4 100644
> > > > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > > > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > > > @@ -34,6 +34,7 @@
> > > > #include <linux/pm_runtime.h>
> > > >
> > > > #include "../../pci.h"
> > > > +#include "../pci-host-common.h"
> > > > #include "pcie-designware.h"
> > > >
> > > > #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
> > > > @@ -152,7 +153,6 @@ struct imx_lut_data {
> > > >
> > > > struct imx_pcie {
> > > > struct dw_pcie *pci;
> > > > - struct gpio_desc *reset_gpiod;
> > > > struct clk_bulk_data *clks;
> > > > int num_clks;
> > > > bool supports_clkreq;
> > > > @@ -1224,6 +1224,32 @@ static void imx_pcie_disable_device(struct
> > > pci_host_bridge *bridge,
> > > > imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); }
> > > >
> > > > +static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie) {
> > > > + struct device *dev = pcie->pci->dev;
> > > > + struct pci_host_bridge *bridge = pcie->pci->pp.bridge;
> > > > + struct pci_host_port *port;
> > > > + struct gpio_desc *reset;
> > > > +
> > > > + reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
> > > > + if (IS_ERR(reset))
> > > > + return PTR_ERR(reset);
> > > > +
> > > > + if (!reset)
> > > > + return 0;
> > > > +
> > > > + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> > > > + if (!port)
> > > > + return -ENOMEM;
> > > > +
> > > > + port->reset = reset;
> > > > + INIT_LIST_HEAD(&port->list);
> > > > + list_add_tail(&port->list, &bridge->ports);
> > > > +
> > > > + return devm_add_action_or_reset(dev,
> > > pci_host_common_delete_ports,
> > > > + &bridge->ports);
> > > > +}
> > > > +
> > > > static void imx_pcie_vpcie_aux_disable(void *data) {
> > > > struct regulator *vpcie_aux = data; @@ -1233,13 +1259,22 @@
> > > > static void imx_pcie_vpcie_aux_disable(void
> > > > *data)
> > > >
> > > > static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool
> > > > assert) {
> > > > - if (assert) {
> > > > - gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);
> > > > - } else {
> > > > - if (imx_pcie->reset_gpiod) {
> > > > - msleep(PCIE_T_PVPERL_MS);
> > > > - gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0);
> > > > - msleep(PCIE_RESET_CONFIG_WAIT_MS);
> > > > + struct dw_pcie *pci = imx_pcie->pci;
> > > > + struct pci_host_bridge *bridge = pci->pp.bridge;
> > > > + struct pci_host_port *port;
> > > > +
> > > > + if (!bridge)
> > > > + return;
> > > > +
> > > > + list_for_each_entry(port, &bridge->ports, list) {
> > > > + if (assert) {
> > > > + gpiod_direction_output(port->reset, 1);
> > > > + } else {
> > > > + if (port->reset) {
> > > > + msleep(PCIE_T_PVPERL_MS);
> > > > + gpiod_direction_output(port->reset, 0);
> > > > + msleep(PCIE_RESET_CONFIG_WAIT_MS);
> > > > + }
> > >
> > > Sashiko flagged this loop:
> > >
> > > ```
> > > Does this loop multiply the initialization delays?
> > > If a controller has multiple Root Ports, the msleep calls will run
> > > sequentially for each port, linearly increasing the delay. Could we
> > > optimize this by asserting all reset GPIOs, waiting the pre-delay
> > > once, de-asserting all GPIOs, and waiting the post-delay once for the entire
> bus?
> > > ```
> > >
> > > Maybe you should do:
> > >
> > > if (!list_empty(&bridge->ports) && !assert)
> > > msleep(PCIE_T_PVPERL_MS);
> > >
> > > list_for_each_entry(port, &bridge->ports, list) {
> > > ...
> > > gpiod_direction_output(port->reset, 0);
> > > ...
> > > }
> > >
> > > if (!list_empty(&bridge->ports) && !assert)
> > > msleep(PCIE_RESET_CONFIG_WAIT_MS);
> > >
> >
> > Hi Mani, I think the code below looks clearer, is that ok for you?
> >
> > if (assert) {
> > list_for_each_entry(port, &bridge->ports, list)
> > gpiod_direction_output(port->reset, 1);
> > } else {
> > if (list_empty(&bridge->ports))
> > return;
> >
>
> This check should be moved out of the if() condition. Other than this, the
> change looks good.
Ok, will do.
>
> > msleep(PCIE_T_PVPERL_MS);
> > list_for_each_entry(port, &bridge->ports, list)
> > gpiod_direction_output(port->reset, 0);
> > msleep(PCIE_RESET_CONFIG_WAIT_MS);
> > }
> >
> > > And then this:
> > >
> > > ```
> > > Also, since this function is called from imx_pcie_resume_noirq,
> > > which executes with hardware interrupts disabled, does the use of
> > > msleep here trigger a 'sleeping while atomic' bug?
> > > ```
> > >
> > > This is a valid concern. You should use mdelay(). But I'd recommend
> > > switching to IRQ enabled callback, resume() instead. There is no
> > > complelling reason to use resume_noirq() in this driver and adding
> > > delays in noirq() callbacks is not recommended as it may increase the
> overall system resume time.
> > >
> > > I will submit a separate series to convert dw_pcie_resume_noirq()
> > > and its callers to IRQ enabled callbacks since this
> > > dw_pcie_resume_noirq() could potentially cause delay up to 1sec.
> >
> > Yes, this is not a new bug introduced by this patch. I agree we should
> > covert the convert dw_pcie_resume_noirq() and the caller to IRQ
> > enabled callbacks to fix this in a separate patch series.
> > For now, should I leave it as is, or switch to mdelay in this patch?
> >
>
> Just use mdelay() in your patch for now.
Ok, thanks!
Best Regards
Sherry
^ permalink raw reply
* [PATCH] of: unittest: fix use-after-free in of_unittest_changeset()
From: Wentao Liang @ 2026-04-09 2:22 UTC (permalink / raw)
To: robh, saravanak; +Cc: devicetree, linux-kernel, Wentao Liang, stable
The variable 'parent' is assigned the value of 'nchangeset' earlier in the
function, meaning both point to the same struct device_node. The call to
of_node_put(nchangeset) can decrement the reference count to zero and
free the node if there are no other holders. After that, the code still
uses 'parent' to check for the presence of a property and to read a
string property, leading to a use-after-free.
Fix this by moving the of_node_put() call after the last access to
'parent', avoiding the UAF.
Fixes: 1c668ea65506 ("of: unittest: Use of_property_present()")
Cc: stable@vger.kernel.org
Signed-off-by: Wentao Liang <vulab@iscas.ac.cn>
---
drivers/of/unittest.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
index 2940295843e6..eae7ebdf5130 100644
--- a/drivers/of/unittest.c
+++ b/drivers/of/unittest.c
@@ -896,8 +896,6 @@ static void __init of_unittest_changeset(void)
unittest(!of_changeset_apply(&chgset), "apply failed\n");
- of_node_put(nchangeset);
-
/* Make sure node names are constructed correctly */
unittest((np = of_find_node_by_path("/testcase-data/changeset/n2/n21")),
"'%pOF' not added\n", n21);
@@ -919,6 +917,7 @@ static void __init of_unittest_changeset(void)
if (!ret)
unittest(strcmp(propstr, "hello") == 0, "original value not in updated property after revert");
+ of_node_put(nchangeset);
of_changeset_destroy(&chgset);
of_node_put(n1);
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v2 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add support for glymur Gen5 x8 bifurcation mode
From: Qiang Yu @ 2026-04-09 2:19 UTC (permalink / raw)
To: Rob Herring
Cc: Vinod Koul, Neil Armstrong, Krzysztof Kozlowski, Conor Dooley,
Philipp Zabel, Bjorn Andersson, Konrad Dybcio, linux-arm-msm,
linux-phy, devicetree, linux-kernel
In-Reply-To: <20260407161311.GA2666255-robh@kernel.org>
On Tue, Apr 07, 2026 at 11:13:11AM -0500, Rob Herring wrote:
> On Mon, Mar 23, 2026 at 12:15:28AM -0700, Qiang Yu wrote:
> > The Glymur SoC has pcie3a and pcie3b PHYs that can operate in two modes:
> >
> > 1. Independent 4-lane mode: Each PHY operates as a separate PCIe Gen5
> > 4-lane interface, compatible with qcom,glymur-qmp-gen5x4-pcie-phy
> > 2. Bifurcation mode (8-lane): pcie3a phy acts as leader and pcie3b phy as
> > follower to form a single 8-lane PCIe Gen5 interface
> >
> > In bifurcation mode, the hardware design requires controlling additional
> > resources beyond the standard pcie3a PHY configuration:
> >
> > - pcie3b's aux_clk (phy_b_aux)
> > - pcie3b's phy_gdsc power domain
> > - pcie3b's bcr/nocsr reset
> >
> > Add qcom,glymur-qmp-gen5x8-pcie-phy compatible string to document this
> > 8-lane bifurcation configuration.
> >
> > The phy_b_aux clock is used as the 6th clock instead of pipediv2,
> > requiring the clock-names enum to be extended to support both
> > [phy_b_aux, pipediv2] options at index 5. This follows the existing
> > pattern used for [rchng, refgen] clocks at index 3.
> >
> > Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> > ---
> > .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 45 ++++++++++++++++++----
> > 1 file changed, 37 insertions(+), 8 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> > index 3a35120a77ec0ceb814a1cdcacff32fef32b4f7b..25717bc9be98824e38f3c27c3299fbd1f2e7e299 100644
> > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
> > @@ -18,6 +18,7 @@ properties:
> > enum:
> > - qcom,glymur-qmp-gen4x2-pcie-phy
> > - qcom,glymur-qmp-gen5x4-pcie-phy
> > + - qcom,glymur-qmp-gen5x8-pcie-phy
> > - qcom,kaanapali-qmp-gen3x2-pcie-phy
> > - qcom,qcs615-qmp-gen3x1-pcie-phy
> > - qcom,qcs8300-qmp-gen4x2-pcie-phy
> > @@ -68,20 +69,23 @@ properties:
> > - const: ref
> > - enum: [rchng, refgen]
> > - const: pipe
> > - - const: pipediv2
> > + - enum: [phy_b_aux, pipediv2]
> >
> > power-domains:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 2
>
> Once there is more than 1, you have to define the order and what each
> one is for.
>
Okay, will add - description for each power-domains.
> >
> > resets:
> > minItems: 1
> > - maxItems: 2
> > + maxItems: 4
> >
> > reset-names:
> > minItems: 1
> > items:
> > - const: phy
> > - const: phy_nocsr
> > + - const: phy_b
> > + - const: phy_b_nocsr
> >
> > vdda-phy-supply: true
> >
> > @@ -183,6 +187,7 @@ allOf:
> > enum:
> > - qcom,glymur-qmp-gen4x2-pcie-phy
> > - qcom,glymur-qmp-gen5x4-pcie-phy
> > + - qcom,glymur-qmp-gen5x8-pcie-phy
> > - qcom,qcs8300-qmp-gen4x2-pcie-phy
> > - qcom,sa8775p-qmp-gen4x2-pcie-phy
> > - qcom,sa8775p-qmp-gen4x4-pcie-phy
> > @@ -201,6 +206,17 @@ allOf:
> > clock-names:
> > minItems: 6
> >
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,glymur-qmp-gen5x8-pcie-phy
> > + then:
> > + properties:
> > + power-domains:
> > + minItems: 2
>
> else:
> maxItems: 1
>
Will add this.
- Qiang Yu
> > +
> > - if:
> > properties:
> > compatible:
> > @@ -223,11 +239,24 @@ allOf:
> > reset-names:
> > minItems: 2
> > else:
> > - properties:
> > - resets:
> > - maxItems: 1
> > - reset-names:
> > - maxItems: 1
> > + if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - qcom,glymur-qmp-gen5x8-pcie-phy
> > + then:
> > + properties:
> > + resets:
> > + minItems: 4
> > + reset-names:
> > + minItems: 4
> > + else:
> > + properties:
> > + resets:
> > + maxItems: 1
> > + reset-names:
> > + maxItems: 1
> >
> > - if:
> > properties:
> >
> > --
> > 2.34.1
> >
^ permalink raw reply
* Re: [PATCH] arm64: dts: imx93-9x9-qsb: Add tianma,tm050rdh03 panel
From: Liu Ying @ 2026-04-09 2:19 UTC (permalink / raw)
To: Frank Li
Cc: Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, imx, linux-arm-kernel,
devicetree, linux-kernel
In-Reply-To: <adYy9xesCKsYWNBg@lizhi-Precision-Tower-5810>
On Wed, Apr 08, 2026 at 06:50:31AM -0400, Frank Li wrote:
> On Wed, Apr 08, 2026 at 04:40:37PM +0800, Liu Ying wrote:
>> On Wed, Apr 08, 2026 at 04:28:40AM -0400, Frank Li wrote:
> ...
>>>>>>>
>>>>>>> Is it possible to appply this overlay file and kd50g21-40nt-a1 overlay file
>>>>>>>
>>>>>>> to imx93-9x9-qsb.dtb, so needn't create dtsi.
>>>>>>
>>>>>> I'm sorry, I don't get your question here.
>>>>>> Anyway, the DT overlays are needed, because the 40-pin EXP/PRI interface on
>>>>>> the i.MX93 9x9 QSB board can not only connect to a DPI panel adapter board
>>>>>> but also to an audio hat[2], and maybe more. The newly introduced .dtsi
>>>>>> file just aims to avoid duplicated code.
>>>>>
>>>>> My means apply two overlay files to dtb
>>>>>
>>>>> imx93-9x9-qsb-tianma-tm050rdh03-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtbo imx93-9x9-qsb-tianma-tm050rdh03.dtbo
>>
>> This ...
>>
>>>>>
>>>>> In imx93-9x9-qsb-tianma-tm050rdh03.dtbo, only include
>>>>> &{/} {
>>>>> panel {
>>>>> compatible = "tianma,tm050rdh03";
>>>>> enable-gpios = <&pcal6524 8 GPIO_ACTIVE_HIGH>;
>>>>> };
>>>>> };
>>>>
>>>> If an user wants to use imx93-9x9-qsb.dtb and the DT overlay blob
>>>> imx93-9x9-qsb-tianma-tm050rdh03.dtbo to enable the tianma,tm050rdh03
>>>> DPI panel, then it won't work unless the user also apply
>>>> imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtbo, right?
>>>>
>>>>>
>>>
>>> Yes, imx93-9x9-qsb-tianma-tm050rdh03.dtb already created, which already
>>> applied both overlay file.
>>
>> .... indicates that imx93-9x9-qsb-tianma-tm050rdh03.dtb is generated by
>> applying both imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtbo and
>> imx93-9x9-qsb-tianma-tm050rdh03.dtbo to imx93-9x9-qsb.dtb.
>> While, imx93-9x9-qsb-tianma-tm050rdh03.dtbo(a DT overlay blob) just contains
>> the panel node, which means that an user __cannot_ enable the tianma,tm050rdh03
>> DPI panel by only applying it to imx93-9x9-qsb.dtb, unless the user also
>> applies imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtbo. That's why the .dtsi
>> file is needed.
>
> what's problem if we require user do that? Makefile already create finial
> imx93-9x9-qsb-tianma-tm050rdh03.dtb.
The problem is that the user would apply imx93-9x9-qsb-tianma-tm050rdh03.dtbo
to imx93-9x9-qsb.dtb to enable the tianma,tm050rdh03 DPI panel, say in the
U-boot stage with the 'fdt' command, which is fairly a typical usecase, just
like the user would apply imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtbo to
imx93-9x9-qsb.dtb to enable the ontat,kd50g21-40nt-a1 DPI panel. We cannot
ask the user to additionally apply imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtbo
to enable the tianma,tm050rdh03 DPI panel, because that's very confusing.
Note that imx93-9x9-qsb-tianma-tm050rdh03.dtb certainly can be used to
enable the tianma,tm050rdh03 DPI panel, but in addition to that,
imx93-9x9-qsb.dtb + imx93-9x9-qsb-tianma-tm050rdh03.dtbo can also be
used to enable the panel.
>
> Any user really apply dtso manaully without use kernel's Makefile?
That's not relevant.
The point is that imx93-9x9-qsb-tianma-tm050rdh03.dtbo would be generated
and applied by the user to imx93-9x9-qsb.dtb to enable the tianma,tm050rdh03
DPI panel.
>
>>
>>>
>>> can the same board be use for imx91 or other evk boards?
>>
>> Yes, both tianma,tm050rdh03 and ontat,kd50g21-40nt-a1 DPI panels can be
>> connected to i.MX91/93 11x11 EVK and 9x9 QSB boards.
>
> Is it possible to use one overlay files for all imx91/imx93 boards?
No, that's impossible, because they use GPIO backlight or PWM backlight,
different GPIOs to enable DPI panels and different GPIO hogs.
>
> Frank
>>
>>>
>>> Frank
>>>
>>>>> Frank
>>>>>>
>>>>>> [2] https://www.nxp.com/design/design-center/development-boards-and-designs/mx93aud-hat-audio-board:MX93AUD-HAT
>>>>>>
>>>>>>>
>>>>>>> Frank
>>>>>>>>
>>>>>>>> ---
>>>>>>>> base-commit: 816f193dd0d95246f208590924dd962b192def78
>>>>>>>> change-id: 20260407-tianma-tm050rdh03-imx93-9x9-qsb-6e4bbbde3d08
>>>>>>>>
>>>>>>>> Best regards,
>>>>>>>> --
>>>>>>>> Liu Ying <victor.liu@nxp.com>
>>>>>>>>
>>>>>>
>>>>>> --
>>>>>> Regards,
>>>>>> Liu Ying
>>>>
>>>> --
>>>> Regards,
>>>> Liu Ying
>>
>> --
>> Regards,
>> Liu Ying
--
Regards,
Liu Ying
^ permalink raw reply
* Re: (subset) [PATCH 0/7] clk: qcom: add support for the clock controllers on Nord platforms
From: Bjorn Andersson @ 2026-04-09 2:07 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Taniya Das, Taniya Das, Richard Cochran, Shawn Guo,
Deepti Jaggi, Bartosz Golaszewski
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, netdev,
Prasanna Tolety
In-Reply-To: <20260403-nord-clks-v1-0-018af14979fd@oss.qualcomm.com>
On Fri, 03 Apr 2026 16:10:48 +0200, Bartosz Golaszewski wrote:
> This documents the gcc, tcsr and rpmhcc support in Nord platforms and
> adds corresponding drivers as well as enables them in arm64 defconfig.
>
>
Applied, thanks!
[1/7] dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
commit: 31fcf6995e74117fe235a7a07a6e13077070b4a2
[2/7] dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
commit: 8a108047245780ca17667b05a7af600d118ec1d6
[3/7] dt-bindings: clock: qcom: Add Nord Global Clock Controller
commit: 06498d59bb4e10032b1495762a999d640fe4a8dc
[4/7] clk: qcom: Add TCSR clock driver for Nord SoC
commit: 9d13c7bbee5f789738a645df5868b69da5ae3879
[5/7] clk: qcom: rpmh: Add support for Nord rpmh clocks
commit: cf6e6ac63c62cb9f60f981dbaebe591bdbee2f46
[6/7] clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
commit: a4f780cd5c7aa8c0d2d044ffd153f7a3a13ca81e
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply
* Re: [PATCH 01/12] firmware: qcom: scm: Allow QSEECOM for Radxa Dragon Q6A
From: Dmitry Baryshkov @ 2026-04-09 1:54 UTC (permalink / raw)
To: Xilin Wu
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Liam Girdwood, Mark Brown, Judy Hsiao,
linux-arm-msm, linux-kernel, devicetree, Konrad Dybcio,
linux-sound
In-Reply-To: <20260407-dragon-q6a-feat-fixes-v1-1-14aca49dde3d@radxa.com>
On Tue, Apr 07, 2026 at 11:19:53PM +0800, Xilin Wu wrote:
> add "radxa,dragon-q6a" as compatible device for QSEECOM
>
> This is required to get access to efivars and uefi boot loader support.
>
> Signed-off-by: Xilin Wu <sophon@radxa.com>
> ---
> drivers/firmware/qcom/qcom_scm.c | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 2/2] soc: qcom: socinfo: add SoC ID for IPQ9650 family
From: Dmitry Baryshkov @ 2026-04-09 1:53 UTC (permalink / raw)
To: Kathiravan Thirumoorthy
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260408-ipq9650_soc_ids-v1-2-e76faac33f77@oss.qualcomm.com>
On Wed, Apr 08, 2026 at 03:28:35PM +0530, Kathiravan Thirumoorthy wrote:
> Add SoC IDs for Qualcomm's IPQ9650 family.
>
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
> drivers/soc/qcom/socinfo.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 2/2] pinctrl: qcom: Add Hawi pinctrl driver
From: Bjorn Andersson @ 2026-04-09 1:50 UTC (permalink / raw)
To: Mukesh Ojha
Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, linux-gpio, devicetree, linux-kernel,
Konrad Dybcio
In-Reply-To: <20260408-hawi-pinctrl-v2-2-fd7f681f5e05@oss.qualcomm.com>
On Wed, Apr 08, 2026 at 07:45:48PM +0530, Mukesh Ojha wrote:
> Add pinctrl driver for TLMM block found in the Hawi SoC.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Thanks for updating those functions.
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Regards,
Bjorn
> ---
> drivers/pinctrl/qcom/Kconfig.msm | 10 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-hawi.c | 1610 +++++++++++++++++++++++++++++++++++
> 3 files changed, 1621 insertions(+)
>
> diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm
> index 17416dce8e70..836cdeca1006 100644
> --- a/drivers/pinctrl/qcom/Kconfig.msm
> +++ b/drivers/pinctrl/qcom/Kconfig.msm
> @@ -35,6 +35,16 @@ config PINCTRL_GLYMUR
> Say Y here to compile statically, or M here to compile it as a module.
> If unsure, say N.
>
> +config PINCTRL_HAWI
> + tristate "Qualcomm Technologies Inc Hawi pin controller driver"
> + depends on ARM64 || COMPILE_TEST
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> + Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
> + block found on the Qualcomm Technologies Inc Hawi platform.
> + Say Y here to compile statically, or M here to compile it as a module.
> + If unsure, say N.
> +
> config PINCTRL_IPQ4019
> tristate "Qualcomm IPQ4019 pin controller driver"
> depends on ARM || COMPILE_TEST
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 4c585bad813c..84bda3ada874 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
> obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
> obj-$(CONFIG_PINCTRL_ELIZA) += pinctrl-eliza.o
> obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o
> +obj-$(CONFIG_PINCTRL_HAWI) += pinctrl-hawi.o
> obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
> obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
> obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-hawi.c b/drivers/pinctrl/qcom/pinctrl-hawi.c
> new file mode 100644
> index 000000000000..5c7894f3b9cb
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-hawi.c
> @@ -0,0 +1,1610 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +
> +#include "pinctrl-msm.h"
> +
> +#define REG_SIZE 0x1000
> +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
> + { \
> + .grp = PINCTRL_PINGROUP("gpio" #id, \
> + gpio##id##_pins, \
> + ARRAY_SIZE(gpio##id##_pins)), \
> + .funcs = (int[]){ \
> + msm_mux_gpio, /* gpio mode */ \
> + msm_mux_##f1, \
> + msm_mux_##f2, \
> + msm_mux_##f3, \
> + msm_mux_##f4, \
> + msm_mux_##f5, \
> + msm_mux_##f6, \
> + msm_mux_##f7, \
> + msm_mux_##f8, \
> + msm_mux_##f9, \
> + msm_mux_##f10, \
> + msm_mux_##f11 /* egpio mode */ \
> + }, \
> + .nfuncs = 12, \
> + .ctl_reg = REG_SIZE * id, \
> + .io_reg = 0x4 + REG_SIZE * id, \
> + .intr_cfg_reg = 0x8 + REG_SIZE * id, \
> + .intr_status_reg = 0xc + REG_SIZE * id, \
> + .mux_bit = 2, \
> + .pull_bit = 0, \
> + .drv_bit = 6, \
> + .egpio_enable = 12, \
> + .egpio_present = 11, \
> + .oe_bit = 9, \
> + .in_bit = 0, \
> + .out_bit = 1, \
> + .intr_enable_bit = 0, \
> + .intr_status_bit = 0, \
> + .intr_wakeup_present_bit = 6, \
> + .intr_wakeup_enable_bit = 7, \
> + .intr_target_bit = 8, \
> + .intr_target_kpss_val = 3, \
> + .intr_raw_status_bit = 4, \
> + .intr_polarity_bit = 1, \
> + .intr_detection_bit = 2, \
> + .intr_detection_width = 2, \
> + }
> +
> +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
> + { \
> + .grp = PINCTRL_PINGROUP(#pg_name, \
> + pg_name##_pins, \
> + ARRAY_SIZE(pg_name##_pins)), \
> + .ctl_reg = ctl, \
> + .io_reg = 0, \
> + .intr_cfg_reg = 0, \
> + .intr_status_reg = 0, \
> + .intr_target_reg = 0, \
> + .mux_bit = -1, \
> + .pull_bit = pull, \
> + .drv_bit = drv, \
> + .oe_bit = -1, \
> + .in_bit = -1, \
> + .out_bit = -1, \
> + .intr_enable_bit = -1, \
> + .intr_status_bit = -1, \
> + .intr_target_bit = -1, \
> + .intr_raw_status_bit = -1, \
> + .intr_polarity_bit = -1, \
> + .intr_detection_bit = -1, \
> + .intr_detection_width = -1, \
> + }
> +
> +#define UFS_RESET(pg_name, ctl, io) \
> + { \
> + .grp = PINCTRL_PINGROUP(#pg_name, \
> + pg_name##_pins, \
> + ARRAY_SIZE(pg_name##_pins)), \
> + .ctl_reg = ctl, \
> + .io_reg = io, \
> + .intr_cfg_reg = 0, \
> + .intr_status_reg = 0, \
> + .intr_target_reg = 0, \
> + .mux_bit = -1, \
> + .pull_bit = 3, \
> + .drv_bit = 0, \
> + .oe_bit = -1, \
> + .in_bit = -1, \
> + .out_bit = 0, \
> + .intr_enable_bit = -1, \
> + .intr_status_bit = -1, \
> + .intr_target_bit = -1, \
> + .intr_raw_status_bit = -1, \
> + .intr_polarity_bit = -1, \
> + .intr_detection_bit = -1, \
> + .intr_detection_width = -1, \
> + }
> +
> +static const struct pinctrl_pin_desc hawi_pins[] = {
> + PINCTRL_PIN(0, "GPIO_0"),
> + PINCTRL_PIN(1, "GPIO_1"),
> + PINCTRL_PIN(2, "GPIO_2"),
> + PINCTRL_PIN(3, "GPIO_3"),
> + PINCTRL_PIN(4, "GPIO_4"),
> + PINCTRL_PIN(5, "GPIO_5"),
> + PINCTRL_PIN(6, "GPIO_6"),
> + PINCTRL_PIN(7, "GPIO_7"),
> + PINCTRL_PIN(8, "GPIO_8"),
> + PINCTRL_PIN(9, "GPIO_9"),
> + PINCTRL_PIN(10, "GPIO_10"),
> + PINCTRL_PIN(11, "GPIO_11"),
> + PINCTRL_PIN(12, "GPIO_12"),
> + PINCTRL_PIN(13, "GPIO_13"),
> + PINCTRL_PIN(14, "GPIO_14"),
> + PINCTRL_PIN(15, "GPIO_15"),
> + PINCTRL_PIN(16, "GPIO_16"),
> + PINCTRL_PIN(17, "GPIO_17"),
> + PINCTRL_PIN(18, "GPIO_18"),
> + PINCTRL_PIN(19, "GPIO_19"),
> + PINCTRL_PIN(20, "GPIO_20"),
> + PINCTRL_PIN(21, "GPIO_21"),
> + PINCTRL_PIN(22, "GPIO_22"),
> + PINCTRL_PIN(23, "GPIO_23"),
> + PINCTRL_PIN(24, "GPIO_24"),
> + PINCTRL_PIN(25, "GPIO_25"),
> + PINCTRL_PIN(26, "GPIO_26"),
> + PINCTRL_PIN(27, "GPIO_27"),
> + PINCTRL_PIN(28, "GPIO_28"),
> + PINCTRL_PIN(29, "GPIO_29"),
> + PINCTRL_PIN(30, "GPIO_30"),
> + PINCTRL_PIN(31, "GPIO_31"),
> + PINCTRL_PIN(32, "GPIO_32"),
> + PINCTRL_PIN(33, "GPIO_33"),
> + PINCTRL_PIN(34, "GPIO_34"),
> + PINCTRL_PIN(35, "GPIO_35"),
> + PINCTRL_PIN(36, "GPIO_36"),
> + PINCTRL_PIN(37, "GPIO_37"),
> + PINCTRL_PIN(38, "GPIO_38"),
> + PINCTRL_PIN(39, "GPIO_39"),
> + PINCTRL_PIN(40, "GPIO_40"),
> + PINCTRL_PIN(41, "GPIO_41"),
> + PINCTRL_PIN(42, "GPIO_42"),
> + PINCTRL_PIN(43, "GPIO_43"),
> + PINCTRL_PIN(44, "GPIO_44"),
> + PINCTRL_PIN(45, "GPIO_45"),
> + PINCTRL_PIN(46, "GPIO_46"),
> + PINCTRL_PIN(47, "GPIO_47"),
> + PINCTRL_PIN(48, "GPIO_48"),
> + PINCTRL_PIN(49, "GPIO_49"),
> + PINCTRL_PIN(50, "GPIO_50"),
> + PINCTRL_PIN(51, "GPIO_51"),
> + PINCTRL_PIN(52, "GPIO_52"),
> + PINCTRL_PIN(53, "GPIO_53"),
> + PINCTRL_PIN(54, "GPIO_54"),
> + PINCTRL_PIN(55, "GPIO_55"),
> + PINCTRL_PIN(56, "GPIO_56"),
> + PINCTRL_PIN(57, "GPIO_57"),
> + PINCTRL_PIN(58, "GPIO_58"),
> + PINCTRL_PIN(59, "GPIO_59"),
> + PINCTRL_PIN(60, "GPIO_60"),
> + PINCTRL_PIN(61, "GPIO_61"),
> + PINCTRL_PIN(62, "GPIO_62"),
> + PINCTRL_PIN(63, "GPIO_63"),
> + PINCTRL_PIN(64, "GPIO_64"),
> + PINCTRL_PIN(65, "GPIO_65"),
> + PINCTRL_PIN(66, "GPIO_66"),
> + PINCTRL_PIN(67, "GPIO_67"),
> + PINCTRL_PIN(68, "GPIO_68"),
> + PINCTRL_PIN(69, "GPIO_69"),
> + PINCTRL_PIN(70, "GPIO_70"),
> + PINCTRL_PIN(71, "GPIO_71"),
> + PINCTRL_PIN(72, "GPIO_72"),
> + PINCTRL_PIN(73, "GPIO_73"),
> + PINCTRL_PIN(74, "GPIO_74"),
> + PINCTRL_PIN(75, "GPIO_75"),
> + PINCTRL_PIN(76, "GPIO_76"),
> + PINCTRL_PIN(77, "GPIO_77"),
> + PINCTRL_PIN(78, "GPIO_78"),
> + PINCTRL_PIN(79, "GPIO_79"),
> + PINCTRL_PIN(80, "GPIO_80"),
> + PINCTRL_PIN(81, "GPIO_81"),
> + PINCTRL_PIN(82, "GPIO_82"),
> + PINCTRL_PIN(83, "GPIO_83"),
> + PINCTRL_PIN(84, "GPIO_84"),
> + PINCTRL_PIN(85, "GPIO_85"),
> + PINCTRL_PIN(86, "GPIO_86"),
> + PINCTRL_PIN(87, "GPIO_87"),
> + PINCTRL_PIN(88, "GPIO_88"),
> + PINCTRL_PIN(89, "GPIO_89"),
> + PINCTRL_PIN(90, "GPIO_90"),
> + PINCTRL_PIN(91, "GPIO_91"),
> + PINCTRL_PIN(92, "GPIO_92"),
> + PINCTRL_PIN(93, "GPIO_93"),
> + PINCTRL_PIN(94, "GPIO_94"),
> + PINCTRL_PIN(95, "GPIO_95"),
> + PINCTRL_PIN(96, "GPIO_96"),
> + PINCTRL_PIN(97, "GPIO_97"),
> + PINCTRL_PIN(98, "GPIO_98"),
> + PINCTRL_PIN(99, "GPIO_99"),
> + PINCTRL_PIN(100, "GPIO_100"),
> + PINCTRL_PIN(101, "GPIO_101"),
> + PINCTRL_PIN(102, "GPIO_102"),
> + PINCTRL_PIN(103, "GPIO_103"),
> + PINCTRL_PIN(104, "GPIO_104"),
> + PINCTRL_PIN(105, "GPIO_105"),
> + PINCTRL_PIN(106, "GPIO_106"),
> + PINCTRL_PIN(107, "GPIO_107"),
> + PINCTRL_PIN(108, "GPIO_108"),
> + PINCTRL_PIN(109, "GPIO_109"),
> + PINCTRL_PIN(110, "GPIO_110"),
> + PINCTRL_PIN(111, "GPIO_111"),
> + PINCTRL_PIN(112, "GPIO_112"),
> + PINCTRL_PIN(113, "GPIO_113"),
> + PINCTRL_PIN(114, "GPIO_114"),
> + PINCTRL_PIN(115, "GPIO_115"),
> + PINCTRL_PIN(116, "GPIO_116"),
> + PINCTRL_PIN(117, "GPIO_117"),
> + PINCTRL_PIN(118, "GPIO_118"),
> + PINCTRL_PIN(119, "GPIO_119"),
> + PINCTRL_PIN(120, "GPIO_120"),
> + PINCTRL_PIN(121, "GPIO_121"),
> + PINCTRL_PIN(122, "GPIO_122"),
> + PINCTRL_PIN(123, "GPIO_123"),
> + PINCTRL_PIN(124, "GPIO_124"),
> + PINCTRL_PIN(125, "GPIO_125"),
> + PINCTRL_PIN(126, "GPIO_126"),
> + PINCTRL_PIN(127, "GPIO_127"),
> + PINCTRL_PIN(128, "GPIO_128"),
> + PINCTRL_PIN(129, "GPIO_129"),
> + PINCTRL_PIN(130, "GPIO_130"),
> + PINCTRL_PIN(131, "GPIO_131"),
> + PINCTRL_PIN(132, "GPIO_132"),
> + PINCTRL_PIN(133, "GPIO_133"),
> + PINCTRL_PIN(134, "GPIO_134"),
> + PINCTRL_PIN(135, "GPIO_135"),
> + PINCTRL_PIN(136, "GPIO_136"),
> + PINCTRL_PIN(137, "GPIO_137"),
> + PINCTRL_PIN(138, "GPIO_138"),
> + PINCTRL_PIN(139, "GPIO_139"),
> + PINCTRL_PIN(140, "GPIO_140"),
> + PINCTRL_PIN(141, "GPIO_141"),
> + PINCTRL_PIN(142, "GPIO_142"),
> + PINCTRL_PIN(143, "GPIO_143"),
> + PINCTRL_PIN(144, "GPIO_144"),
> + PINCTRL_PIN(145, "GPIO_145"),
> + PINCTRL_PIN(146, "GPIO_146"),
> + PINCTRL_PIN(147, "GPIO_147"),
> + PINCTRL_PIN(148, "GPIO_148"),
> + PINCTRL_PIN(149, "GPIO_149"),
> + PINCTRL_PIN(150, "GPIO_150"),
> + PINCTRL_PIN(151, "GPIO_151"),
> + PINCTRL_PIN(152, "GPIO_152"),
> + PINCTRL_PIN(153, "GPIO_153"),
> + PINCTRL_PIN(154, "GPIO_154"),
> + PINCTRL_PIN(155, "GPIO_155"),
> + PINCTRL_PIN(156, "GPIO_156"),
> + PINCTRL_PIN(157, "GPIO_157"),
> + PINCTRL_PIN(158, "GPIO_158"),
> + PINCTRL_PIN(159, "GPIO_159"),
> + PINCTRL_PIN(160, "GPIO_160"),
> + PINCTRL_PIN(161, "GPIO_161"),
> + PINCTRL_PIN(162, "GPIO_162"),
> + PINCTRL_PIN(163, "GPIO_163"),
> + PINCTRL_PIN(164, "GPIO_164"),
> + PINCTRL_PIN(165, "GPIO_165"),
> + PINCTRL_PIN(166, "GPIO_166"),
> + PINCTRL_PIN(167, "GPIO_167"),
> + PINCTRL_PIN(168, "GPIO_168"),
> + PINCTRL_PIN(169, "GPIO_169"),
> + PINCTRL_PIN(170, "GPIO_170"),
> + PINCTRL_PIN(171, "GPIO_171"),
> + PINCTRL_PIN(172, "GPIO_172"),
> + PINCTRL_PIN(173, "GPIO_173"),
> + PINCTRL_PIN(174, "GPIO_174"),
> + PINCTRL_PIN(175, "GPIO_175"),
> + PINCTRL_PIN(176, "GPIO_176"),
> + PINCTRL_PIN(177, "GPIO_177"),
> + PINCTRL_PIN(178, "GPIO_178"),
> + PINCTRL_PIN(179, "GPIO_179"),
> + PINCTRL_PIN(180, "GPIO_180"),
> + PINCTRL_PIN(181, "GPIO_181"),
> + PINCTRL_PIN(182, "GPIO_182"),
> + PINCTRL_PIN(183, "GPIO_183"),
> + PINCTRL_PIN(184, "GPIO_184"),
> + PINCTRL_PIN(185, "GPIO_185"),
> + PINCTRL_PIN(186, "GPIO_186"),
> + PINCTRL_PIN(187, "GPIO_187"),
> + PINCTRL_PIN(188, "GPIO_188"),
> + PINCTRL_PIN(189, "GPIO_189"),
> + PINCTRL_PIN(190, "GPIO_190"),
> + PINCTRL_PIN(191, "GPIO_191"),
> + PINCTRL_PIN(192, "GPIO_192"),
> + PINCTRL_PIN(193, "GPIO_193"),
> + PINCTRL_PIN(194, "GPIO_194"),
> + PINCTRL_PIN(195, "GPIO_195"),
> + PINCTRL_PIN(196, "GPIO_196"),
> + PINCTRL_PIN(197, "GPIO_197"),
> + PINCTRL_PIN(198, "GPIO_198"),
> + PINCTRL_PIN(199, "GPIO_199"),
> + PINCTRL_PIN(200, "GPIO_200"),
> + PINCTRL_PIN(201, "GPIO_201"),
> + PINCTRL_PIN(202, "GPIO_202"),
> + PINCTRL_PIN(203, "GPIO_203"),
> + PINCTRL_PIN(204, "GPIO_204"),
> + PINCTRL_PIN(205, "GPIO_205"),
> + PINCTRL_PIN(206, "GPIO_206"),
> + PINCTRL_PIN(207, "GPIO_207"),
> + PINCTRL_PIN(208, "GPIO_208"),
> + PINCTRL_PIN(209, "GPIO_209"),
> + PINCTRL_PIN(210, "GPIO_210"),
> + PINCTRL_PIN(211, "GPIO_211"),
> + PINCTRL_PIN(212, "GPIO_212"),
> + PINCTRL_PIN(213, "GPIO_213"),
> + PINCTRL_PIN(214, "GPIO_214"),
> + PINCTRL_PIN(215, "GPIO_215"),
> + PINCTRL_PIN(216, "GPIO_216"),
> + PINCTRL_PIN(217, "GPIO_217"),
> + PINCTRL_PIN(218, "GPIO_218"),
> + PINCTRL_PIN(219, "GPIO_219"),
> + PINCTRL_PIN(220, "GPIO_220"),
> + PINCTRL_PIN(221, "GPIO_221"),
> + PINCTRL_PIN(222, "GPIO_222"),
> + PINCTRL_PIN(223, "GPIO_223"),
> + PINCTRL_PIN(224, "GPIO_224"),
> + PINCTRL_PIN(225, "GPIO_225"),
> + PINCTRL_PIN(226, "UFS_RESET"),
> + PINCTRL_PIN(227, "SDC2_CLK"),
> + PINCTRL_PIN(228, "SDC2_CMD"),
> + PINCTRL_PIN(229, "SDC2_DATA"),
> +};
> +
> +#define DECLARE_MSM_GPIO_PINS(pin) \
> + static const unsigned int gpio##pin##_pins[] = { pin }
> +DECLARE_MSM_GPIO_PINS(0);
> +DECLARE_MSM_GPIO_PINS(1);
> +DECLARE_MSM_GPIO_PINS(2);
> +DECLARE_MSM_GPIO_PINS(3);
> +DECLARE_MSM_GPIO_PINS(4);
> +DECLARE_MSM_GPIO_PINS(5);
> +DECLARE_MSM_GPIO_PINS(6);
> +DECLARE_MSM_GPIO_PINS(7);
> +DECLARE_MSM_GPIO_PINS(8);
> +DECLARE_MSM_GPIO_PINS(9);
> +DECLARE_MSM_GPIO_PINS(10);
> +DECLARE_MSM_GPIO_PINS(11);
> +DECLARE_MSM_GPIO_PINS(12);
> +DECLARE_MSM_GPIO_PINS(13);
> +DECLARE_MSM_GPIO_PINS(14);
> +DECLARE_MSM_GPIO_PINS(15);
> +DECLARE_MSM_GPIO_PINS(16);
> +DECLARE_MSM_GPIO_PINS(17);
> +DECLARE_MSM_GPIO_PINS(18);
> +DECLARE_MSM_GPIO_PINS(19);
> +DECLARE_MSM_GPIO_PINS(20);
> +DECLARE_MSM_GPIO_PINS(21);
> +DECLARE_MSM_GPIO_PINS(22);
> +DECLARE_MSM_GPIO_PINS(23);
> +DECLARE_MSM_GPIO_PINS(24);
> +DECLARE_MSM_GPIO_PINS(25);
> +DECLARE_MSM_GPIO_PINS(26);
> +DECLARE_MSM_GPIO_PINS(27);
> +DECLARE_MSM_GPIO_PINS(28);
> +DECLARE_MSM_GPIO_PINS(29);
> +DECLARE_MSM_GPIO_PINS(30);
> +DECLARE_MSM_GPIO_PINS(31);
> +DECLARE_MSM_GPIO_PINS(32);
> +DECLARE_MSM_GPIO_PINS(33);
> +DECLARE_MSM_GPIO_PINS(34);
> +DECLARE_MSM_GPIO_PINS(35);
> +DECLARE_MSM_GPIO_PINS(36);
> +DECLARE_MSM_GPIO_PINS(37);
> +DECLARE_MSM_GPIO_PINS(38);
> +DECLARE_MSM_GPIO_PINS(39);
> +DECLARE_MSM_GPIO_PINS(40);
> +DECLARE_MSM_GPIO_PINS(41);
> +DECLARE_MSM_GPIO_PINS(42);
> +DECLARE_MSM_GPIO_PINS(43);
> +DECLARE_MSM_GPIO_PINS(44);
> +DECLARE_MSM_GPIO_PINS(45);
> +DECLARE_MSM_GPIO_PINS(46);
> +DECLARE_MSM_GPIO_PINS(47);
> +DECLARE_MSM_GPIO_PINS(48);
> +DECLARE_MSM_GPIO_PINS(49);
> +DECLARE_MSM_GPIO_PINS(50);
> +DECLARE_MSM_GPIO_PINS(51);
> +DECLARE_MSM_GPIO_PINS(52);
> +DECLARE_MSM_GPIO_PINS(53);
> +DECLARE_MSM_GPIO_PINS(54);
> +DECLARE_MSM_GPIO_PINS(55);
> +DECLARE_MSM_GPIO_PINS(56);
> +DECLARE_MSM_GPIO_PINS(57);
> +DECLARE_MSM_GPIO_PINS(58);
> +DECLARE_MSM_GPIO_PINS(59);
> +DECLARE_MSM_GPIO_PINS(60);
> +DECLARE_MSM_GPIO_PINS(61);
> +DECLARE_MSM_GPIO_PINS(62);
> +DECLARE_MSM_GPIO_PINS(63);
> +DECLARE_MSM_GPIO_PINS(64);
> +DECLARE_MSM_GPIO_PINS(65);
> +DECLARE_MSM_GPIO_PINS(66);
> +DECLARE_MSM_GPIO_PINS(67);
> +DECLARE_MSM_GPIO_PINS(68);
> +DECLARE_MSM_GPIO_PINS(69);
> +DECLARE_MSM_GPIO_PINS(70);
> +DECLARE_MSM_GPIO_PINS(71);
> +DECLARE_MSM_GPIO_PINS(72);
> +DECLARE_MSM_GPIO_PINS(73);
> +DECLARE_MSM_GPIO_PINS(74);
> +DECLARE_MSM_GPIO_PINS(75);
> +DECLARE_MSM_GPIO_PINS(76);
> +DECLARE_MSM_GPIO_PINS(77);
> +DECLARE_MSM_GPIO_PINS(78);
> +DECLARE_MSM_GPIO_PINS(79);
> +DECLARE_MSM_GPIO_PINS(80);
> +DECLARE_MSM_GPIO_PINS(81);
> +DECLARE_MSM_GPIO_PINS(82);
> +DECLARE_MSM_GPIO_PINS(83);
> +DECLARE_MSM_GPIO_PINS(84);
> +DECLARE_MSM_GPIO_PINS(85);
> +DECLARE_MSM_GPIO_PINS(86);
> +DECLARE_MSM_GPIO_PINS(87);
> +DECLARE_MSM_GPIO_PINS(88);
> +DECLARE_MSM_GPIO_PINS(89);
> +DECLARE_MSM_GPIO_PINS(90);
> +DECLARE_MSM_GPIO_PINS(91);
> +DECLARE_MSM_GPIO_PINS(92);
> +DECLARE_MSM_GPIO_PINS(93);
> +DECLARE_MSM_GPIO_PINS(94);
> +DECLARE_MSM_GPIO_PINS(95);
> +DECLARE_MSM_GPIO_PINS(96);
> +DECLARE_MSM_GPIO_PINS(97);
> +DECLARE_MSM_GPIO_PINS(98);
> +DECLARE_MSM_GPIO_PINS(99);
> +DECLARE_MSM_GPIO_PINS(100);
> +DECLARE_MSM_GPIO_PINS(101);
> +DECLARE_MSM_GPIO_PINS(102);
> +DECLARE_MSM_GPIO_PINS(103);
> +DECLARE_MSM_GPIO_PINS(104);
> +DECLARE_MSM_GPIO_PINS(105);
> +DECLARE_MSM_GPIO_PINS(106);
> +DECLARE_MSM_GPIO_PINS(107);
> +DECLARE_MSM_GPIO_PINS(108);
> +DECLARE_MSM_GPIO_PINS(109);
> +DECLARE_MSM_GPIO_PINS(110);
> +DECLARE_MSM_GPIO_PINS(111);
> +DECLARE_MSM_GPIO_PINS(112);
> +DECLARE_MSM_GPIO_PINS(113);
> +DECLARE_MSM_GPIO_PINS(114);
> +DECLARE_MSM_GPIO_PINS(115);
> +DECLARE_MSM_GPIO_PINS(116);
> +DECLARE_MSM_GPIO_PINS(117);
> +DECLARE_MSM_GPIO_PINS(118);
> +DECLARE_MSM_GPIO_PINS(119);
> +DECLARE_MSM_GPIO_PINS(120);
> +DECLARE_MSM_GPIO_PINS(121);
> +DECLARE_MSM_GPIO_PINS(122);
> +DECLARE_MSM_GPIO_PINS(123);
> +DECLARE_MSM_GPIO_PINS(124);
> +DECLARE_MSM_GPIO_PINS(125);
> +DECLARE_MSM_GPIO_PINS(126);
> +DECLARE_MSM_GPIO_PINS(127);
> +DECLARE_MSM_GPIO_PINS(128);
> +DECLARE_MSM_GPIO_PINS(129);
> +DECLARE_MSM_GPIO_PINS(130);
> +DECLARE_MSM_GPIO_PINS(131);
> +DECLARE_MSM_GPIO_PINS(132);
> +DECLARE_MSM_GPIO_PINS(133);
> +DECLARE_MSM_GPIO_PINS(134);
> +DECLARE_MSM_GPIO_PINS(135);
> +DECLARE_MSM_GPIO_PINS(136);
> +DECLARE_MSM_GPIO_PINS(137);
> +DECLARE_MSM_GPIO_PINS(138);
> +DECLARE_MSM_GPIO_PINS(139);
> +DECLARE_MSM_GPIO_PINS(140);
> +DECLARE_MSM_GPIO_PINS(141);
> +DECLARE_MSM_GPIO_PINS(142);
> +DECLARE_MSM_GPIO_PINS(143);
> +DECLARE_MSM_GPIO_PINS(144);
> +DECLARE_MSM_GPIO_PINS(145);
> +DECLARE_MSM_GPIO_PINS(146);
> +DECLARE_MSM_GPIO_PINS(147);
> +DECLARE_MSM_GPIO_PINS(148);
> +DECLARE_MSM_GPIO_PINS(149);
> +DECLARE_MSM_GPIO_PINS(150);
> +DECLARE_MSM_GPIO_PINS(151);
> +DECLARE_MSM_GPIO_PINS(152);
> +DECLARE_MSM_GPIO_PINS(153);
> +DECLARE_MSM_GPIO_PINS(154);
> +DECLARE_MSM_GPIO_PINS(155);
> +DECLARE_MSM_GPIO_PINS(156);
> +DECLARE_MSM_GPIO_PINS(157);
> +DECLARE_MSM_GPIO_PINS(158);
> +DECLARE_MSM_GPIO_PINS(159);
> +DECLARE_MSM_GPIO_PINS(160);
> +DECLARE_MSM_GPIO_PINS(161);
> +DECLARE_MSM_GPIO_PINS(162);
> +DECLARE_MSM_GPIO_PINS(163);
> +DECLARE_MSM_GPIO_PINS(164);
> +DECLARE_MSM_GPIO_PINS(165);
> +DECLARE_MSM_GPIO_PINS(166);
> +DECLARE_MSM_GPIO_PINS(167);
> +DECLARE_MSM_GPIO_PINS(168);
> +DECLARE_MSM_GPIO_PINS(169);
> +DECLARE_MSM_GPIO_PINS(170);
> +DECLARE_MSM_GPIO_PINS(171);
> +DECLARE_MSM_GPIO_PINS(172);
> +DECLARE_MSM_GPIO_PINS(173);
> +DECLARE_MSM_GPIO_PINS(174);
> +DECLARE_MSM_GPIO_PINS(175);
> +DECLARE_MSM_GPIO_PINS(176);
> +DECLARE_MSM_GPIO_PINS(177);
> +DECLARE_MSM_GPIO_PINS(178);
> +DECLARE_MSM_GPIO_PINS(179);
> +DECLARE_MSM_GPIO_PINS(180);
> +DECLARE_MSM_GPIO_PINS(181);
> +DECLARE_MSM_GPIO_PINS(182);
> +DECLARE_MSM_GPIO_PINS(183);
> +DECLARE_MSM_GPIO_PINS(184);
> +DECLARE_MSM_GPIO_PINS(185);
> +DECLARE_MSM_GPIO_PINS(186);
> +DECLARE_MSM_GPIO_PINS(187);
> +DECLARE_MSM_GPIO_PINS(188);
> +DECLARE_MSM_GPIO_PINS(189);
> +DECLARE_MSM_GPIO_PINS(190);
> +DECLARE_MSM_GPIO_PINS(191);
> +DECLARE_MSM_GPIO_PINS(192);
> +DECLARE_MSM_GPIO_PINS(193);
> +DECLARE_MSM_GPIO_PINS(194);
> +DECLARE_MSM_GPIO_PINS(195);
> +DECLARE_MSM_GPIO_PINS(196);
> +DECLARE_MSM_GPIO_PINS(197);
> +DECLARE_MSM_GPIO_PINS(198);
> +DECLARE_MSM_GPIO_PINS(199);
> +DECLARE_MSM_GPIO_PINS(200);
> +DECLARE_MSM_GPIO_PINS(201);
> +DECLARE_MSM_GPIO_PINS(202);
> +DECLARE_MSM_GPIO_PINS(203);
> +DECLARE_MSM_GPIO_PINS(204);
> +DECLARE_MSM_GPIO_PINS(205);
> +DECLARE_MSM_GPIO_PINS(206);
> +DECLARE_MSM_GPIO_PINS(207);
> +DECLARE_MSM_GPIO_PINS(208);
> +DECLARE_MSM_GPIO_PINS(209);
> +DECLARE_MSM_GPIO_PINS(210);
> +DECLARE_MSM_GPIO_PINS(211);
> +DECLARE_MSM_GPIO_PINS(212);
> +DECLARE_MSM_GPIO_PINS(213);
> +DECLARE_MSM_GPIO_PINS(214);
> +DECLARE_MSM_GPIO_PINS(215);
> +DECLARE_MSM_GPIO_PINS(216);
> +DECLARE_MSM_GPIO_PINS(217);
> +DECLARE_MSM_GPIO_PINS(218);
> +DECLARE_MSM_GPIO_PINS(219);
> +DECLARE_MSM_GPIO_PINS(220);
> +DECLARE_MSM_GPIO_PINS(221);
> +DECLARE_MSM_GPIO_PINS(222);
> +DECLARE_MSM_GPIO_PINS(223);
> +DECLARE_MSM_GPIO_PINS(224);
> +DECLARE_MSM_GPIO_PINS(225);
> +
> +static const unsigned int ufs_reset_pins[] = { 226 };
> +static const unsigned int sdc2_clk_pins[] = { 227 };
> +static const unsigned int sdc2_cmd_pins[] = { 228 };
> +static const unsigned int sdc2_data_pins[] = { 229 };
> +
> +enum hawi_functions {
> + msm_mux_gpio,
> + msm_mux_aoss_cti,
> + msm_mux_atest_char,
> + msm_mux_atest_usb,
> + msm_mux_audio_ext_mclk,
> + msm_mux_audio_ref_clk,
> + msm_mux_cam_mclk,
> + msm_mux_cci_async_in,
> + msm_mux_cci_i2c0,
> + msm_mux_cci_i2c1,
> + msm_mux_cci_i2c2,
> + msm_mux_cci_i2c3,
> + msm_mux_cci_i2c4,
> + msm_mux_cci_i2c5,
> + msm_mux_cci_timer,
> + msm_mux_coex_espmi,
> + msm_mux_coex_uart1_rx,
> + msm_mux_coex_uart1_tx,
> + msm_mux_dbg_out_clk,
> + msm_mux_ddr_bist,
> + msm_mux_ddr_pxi,
> + msm_mux_dp_hot,
> + msm_mux_egpio,
> + msm_mux_gcc_gp,
> + msm_mux_gnss_adc,
> + msm_mux_host_rst,
> + msm_mux_i2chub0_se0,
> + msm_mux_i2chub0_se1,
> + msm_mux_i2chub0_se2,
> + msm_mux_i2chub0_se3,
> + msm_mux_i2chub0_se4,
> + msm_mux_i2s0,
> + msm_mux_i2s1,
> + msm_mux_ibi_i3c,
> + msm_mux_jitter_bist,
> + msm_mux_mdp_esync0,
> + msm_mux_mdp_esync1,
> + msm_mux_mdp_esync2,
> + msm_mux_mdp_vsync,
> + msm_mux_mdp_vsync_e,
> + msm_mux_mdp_vsync_p,
> + msm_mux_mdp_vsync0_out,
> + msm_mux_mdp_vsync1_out,
> + msm_mux_mdp_vsync2_out,
> + msm_mux_mdp_vsync3_out,
> + msm_mux_mdp_vsync5_out,
> + msm_mux_modem_pps_in,
> + msm_mux_modem_pps_out,
> + msm_mux_nav_gpio,
> + msm_mux_nav_gpio0,
> + msm_mux_nav_gpio3,
> + msm_mux_nav_rffe,
> + msm_mux_pcie0_clk_req_n,
> + msm_mux_pcie0_rst_n,
> + msm_mux_pcie1_clk_req_n,
> + msm_mux_phase_flag,
> + msm_mux_pll_bist_sync,
> + msm_mux_pll_clk_aux,
> + msm_mux_qdss_cti,
> + msm_mux_qlink,
> + msm_mux_qspi,
> + msm_mux_qspi_clk,
> + msm_mux_qspi_cs,
> + msm_mux_qup1_se0,
> + msm_mux_qup1_se1,
> + msm_mux_qup1_se2,
> + msm_mux_qup1_se3,
> + msm_mux_qup1_se4,
> + msm_mux_qup1_se5,
> + msm_mux_qup1_se6,
> + msm_mux_qup1_se7,
> + msm_mux_qup2_se0,
> + msm_mux_qup2_se1,
> + msm_mux_qup2_se2,
> + msm_mux_qup2_se3,
> + msm_mux_qup2_se4_01,
> + msm_mux_qup2_se4_23,
> + msm_mux_qup3_se0_01,
> + msm_mux_qup3_se0_23,
> + msm_mux_qup3_se1,
> + msm_mux_qup3_se2,
> + msm_mux_qup3_se3,
> + msm_mux_qup3_se4,
> + msm_mux_qup3_se5,
> + msm_mux_qup4_se0,
> + msm_mux_qup4_se1,
> + msm_mux_qup4_se2,
> + msm_mux_qup4_se3_01,
> + msm_mux_qup4_se3_23,
> + msm_mux_qup4_se3_l3,
> + msm_mux_qup4_se4_01,
> + msm_mux_qup4_se4_23,
> + msm_mux_qup4_se4_l3,
> + msm_mux_rng_rosc,
> + msm_mux_sd_write_protect,
> + msm_mux_sdc4_clk,
> + msm_mux_sdc4_cmd,
> + msm_mux_sdc4_data,
> + msm_mux_sys_throttle,
> + msm_mux_tb_trig_sdc,
> + msm_mux_tmess_rng,
> + msm_mux_tsense_clm,
> + msm_mux_tsense_pwm,
> + msm_mux_uim0,
> + msm_mux_uim1,
> + msm_mux_usb0_hs,
> + msm_mux_usb_phy,
> + msm_mux_vfr,
> + msm_mux_vsense_trigger_mirnat,
> + msm_mux_wcn_sw_ctrl,
> + msm_mux__,
> +};
> +
> +static const char *const gpio_groups[] = {
> + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
> + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
> + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
> + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
> + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
> + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
> + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
> + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
> + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
> + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59",
> + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
> + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71",
> + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
> + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
> + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89",
> + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
> + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101",
> + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
> + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113",
> + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119",
> + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
> + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131",
> + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137",
> + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
> + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149",
> + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155",
> + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161",
> + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167",
> + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173",
> + "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179",
> + "gpio180", "gpio181", "gpio182", "gpio183", "gpio184", "gpio185",
> + "gpio186", "gpio187", "gpio188", "gpio189", "gpio190", "gpio191",
> + "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197",
> + "gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203",
> + "gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209",
> + "gpio210", "gpio211", "gpio212", "gpio213", "gpio214", "gpio215",
> + "gpio216", "gpio217", "gpio218", "gpio219", "gpio220", "gpio221",
> + "gpio222", "gpio223", "gpio224", "gpio225",
> +};
> +
> +static const char *const aoss_cti_groups[] = {
> + "gpio74", "gpio75", "gpio76", "gpio77",
> +};
> +
> +static const char *const atest_char_groups[] = {
> + "gpio126", "gpio127", "gpio128", "gpio129", "gpio133",
> +};
> +
> +static const char *const atest_usb_groups[] = {
> + "gpio70", "gpio71", "gpio72", "gpio73", "gpio129",
> +};
> +
> +static const char *const audio_ext_mclk_groups[] = {
> + "gpio120", "gpio121",
> +};
> +
> +static const char *const audio_ref_clk_groups[] = {
> + "gpio120",
> +};
> +
> +static const char *const cam_mclk_groups[] = {
> + "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94",
> + "gpio95", "gpio96",
> +};
> +
> +static const char *const cci_async_in_groups[] = {
> + "gpio15", "gpio109", "gpio110",
> +};
> +
> +static const char *const cci_i2c0_groups[] = {
> + "gpio109", "gpio110",
> +};
> +
> +static const char *const cci_i2c1_groups[] = {
> + "gpio111", "gpio112",
> +};
> +
> +static const char *const cci_i2c2_groups[] = {
> + "gpio113", "gpio114",
> +};
> +
> +static const char *const cci_i2c3_groups[] = {
> + "gpio107", "gpio160",
> +};
> +
> +static const char *const cci_i2c4_groups[] = {
> + "gpio108", "gpio149",
> +};
> +
> +static const char *const cci_i2c5_groups[] = {
> + "gpio115", "gpio116",
> +};
> +
> +static const char *const cci_timer_groups[] = {
> + "gpio105", "gpio106", "gpio107", "gpio159", "gpio160",
> +};
> +
> +static const char *const coex_espmi_groups[] = {
> + "gpio144", "gpio145",
> +};
> +
> +static const char *const coex_uart1_rx_groups[] = {
> + "gpio144",
> +};
> +
> +static const char *const coex_uart1_tx_groups[] = {
> + "gpio145",
> +};
> +
> +static const char *const dbg_out_clk_groups[] = {
> + "gpio82",
> +};
> +
> +static const char *const ddr_bist_groups[] = {
> + "gpio40", "gpio41", "gpio44", "gpio45",
> +};
> +
> +static const char *const ddr_pxi_groups[] = {
> + "gpio43", "gpio44", "gpio45", "gpio46",
> + "gpio52", "gpio53", "gpio54", "gpio55",
> +};
> +
> +static const char *const dp_hot_groups[] = {
> + "gpio47",
> +};
> +
> +static const char *const egpio_groups[] = {
> + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
> + "gpio6", "gpio7", "gpio28", "gpio29", "gpio30", "gpio31",
> + "gpio48", "gpio49", "gpio50", "gpio51", "gpio163", "gpio164",
> + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
> + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
> + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182",
> + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188",
> + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194",
> + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200",
> + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206",
> + "gpio207", "gpio208", "gpio209", "gpio212", "gpio213", "gpio214",
> + "gpio215", "gpio216", "gpio217", "gpio218",
> +};
> +
> +static const char *const gcc_gp_groups[] = {
> + "gpio86", "gpio87", "gpio130", "gpio131", "gpio132", "gpio158",
> +};
> +
> +static const char *const gnss_adc_groups[] = {
> + "gpio40", "gpio41", "gpio42", "gpio77",
> +};
> +
> +static const char *const host_rst_groups[] = {
> + "gpio106",
> +};
> +
> +static const char *const i2chub0_se0_groups[] = {
> + "gpio66", "gpio67",
> +};
> +
> +static const char *const i2chub0_se1_groups[] = {
> + "gpio78", "gpio79",
> +};
> +
> +static const char *const i2chub0_se2_groups[] = {
> + "gpio68", "gpio69",
> +};
> +
> +static const char *const i2chub0_se3_groups[] = {
> + "gpio70", "gpio71",
> +};
> +
> +static const char *const i2chub0_se4_groups[] = {
> + "gpio72", "gpio73",
> +};
> +
> +static const char *const i2s0_groups[] = {
> + "gpio122", "gpio123", "gpio124", "gpio125",
> +};
> +
> +static const char *const i2s1_groups[] = {
> + "gpio117", "gpio118", "gpio119", "gpio120",
> +};
> +
> +static const char *const ibi_i3c_groups[] = {
> + "gpio0", "gpio1", "gpio4", "gpio5", "gpio8", "gpio9",
> + "gpio12", "gpio13", "gpio28", "gpio29", "gpio32", "gpio33",
> + "gpio36", "gpio37", "gpio48", "gpio49", "gpio60", "gpio61",
> +};
> +
> +static const char *const jitter_bist_groups[] = {
> + "gpio73",
> +};
> +
> +static const char *const mdp_esync0_groups[] = {
> + "gpio88", "gpio100",
> +};
> +
> +static const char *const mdp_esync1_groups[] = {
> + "gpio86", "gpio100",
> +};
> +
> +static const char *const mdp_esync2_groups[] = {
> + "gpio87", "gpio97",
> +};
> +
> +static const char *const mdp_vsync_groups[] = {
> + "gpio86", "gpio87", "gpio88", "gpio97",
> +};
> +
> +static const char *const mdp_vsync_e_groups[] = {
> + "gpio98",
> +};
> +
> +static const char *const mdp_vsync_p_groups[] = {
> + "gpio98",
> +};
> +
> +static const char *const mdp_vsync0_out_groups[] = {
> + "gpio86",
> +};
> +
> +static const char *const mdp_vsync1_out_groups[] = {
> + "gpio86",
> +};
> +
> +static const char *const mdp_vsync2_out_groups[] = {
> + "gpio87",
> +};
> +
> +static const char *const mdp_vsync3_out_groups[] = {
> + "gpio87",
> +};
> +
> +static const char *const mdp_vsync5_out_groups[] = {
> + "gpio87",
> +};
> +
> +static const char *const modem_pps_in_groups[] = {
> + "gpio151",
> +};
> +
> +static const char *const modem_pps_out_groups[] = {
> + "gpio151",
> +};
> +
> +static const char *const nav_gpio_groups[] = {
> + "gpio146", "gpio147", "gpio148", "gpio151",
> +};
> +
> +static const char *const nav_gpio0_groups[] = {
> + "gpio150",
> +};
> +
> +static const char *const nav_gpio3_groups[] = {
> + "gpio150",
> +};
> +
> +static const char *const nav_rffe_groups[] = {
> + "gpio134", "gpio135", "gpio138", "gpio139",
> +};
> +
> +static const char *const pcie0_clk_req_n_groups[] = {
> + "gpio103",
> +};
> +
> +static const char *const pcie0_rst_n_groups[] = {
> + "gpio102",
> +};
> +
> +static const char *const pcie1_clk_req_n_groups[] = {
> + "gpio221",
> +};
> +
> +static const char *const phase_flag_groups[] = {
> + "gpio117", "gpio118", "gpio119", "gpio123", "gpio124", "gpio125",
> + "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", "gpio175",
> + "gpio176", "gpio179", "gpio180", "gpio181", "gpio184", "gpio185",
> + "gpio192", "gpio196", "gpio197", "gpio198", "gpio199", "gpio204",
> + "gpio206", "gpio207", "gpio208", "gpio210", "gpio211", "gpio214",
> + "gpio215", "gpio216",
> +};
> +
> +static const char *const pll_bist_sync_groups[] = {
> + "gpio104",
> +};
> +
> +static const char *const pll_clk_aux_groups[] = {
> + "gpio94",
> +};
> +
> +static const char *const qdss_cti_groups[] = {
> + "gpio27", "gpio31", "gpio72", "gpio73", "gpio82", "gpio83",
> + "gpio152", "gpio158",
> +};
> +
> +static const char *const qlink_groups[] = {
> + "gpio152", "gpio153", "gpio154",
> +};
> +
> +static const char *const qspi_groups[] = {
> + "gpio80", "gpio81", "gpio82", "gpio147",
> +};
> +
> +static const char *const qspi_clk_groups[] = {
> + "gpio83",
> +};
> +
> +static const char *const qspi_cs_groups[] = {
> + "gpio146", "gpio148",
> +};
> +
> +static const char *const qup1_se0_groups[] = {
> + "gpio80", "gpio81", "gpio82", "gpio83",
> +};
> +
> +static const char *const qup1_se1_groups[] = {
> + "gpio74", "gpio75", "gpio76", "gpio77",
> +};
> +
> +static const char *const qup1_se2_groups[] = {
> + "gpio40", "gpio41", "gpio42", "gpio43", "gpio130", "gpio131", "gpio132",
> +};
> +
> +static const char *const qup1_se3_groups[] = {
> + "gpio44", "gpio45", "gpio46", "gpio47",
> +};
> +
> +static const char *const qup1_se4_groups[] = {
> + "gpio36", "gpio37", "gpio38", "gpio39",
> +};
> +
> +static const char *const qup1_se5_groups[] = {
> + "gpio52", "gpio53", "gpio54", "gpio55",
> +};
> +
> +static const char *const qup1_se6_groups[] = {
> + "gpio56", "gpio57", "gpio58", "gpio59",
> +};
> +
> +static const char *const qup1_se7_groups[] = {
> + "gpio60", "gpio61", "gpio62", "gpio63",
> +};
> +
> +static const char *const qup2_se0_groups[] = {
> + "gpio0", "gpio1", "gpio2", "gpio3",
> +};
> +
> +static const char *const qup2_se1_groups[] = {
> + "gpio4", "gpio5", "gpio6", "gpio7",
> +};
> +
> +static const char *const qup2_se2_groups[] = {
> + "gpio117", "gpio118", "gpio119", "gpio120",
> +};
> +
> +static const char *const qup2_se3_groups[] = {
> + "gpio97", "gpio122", "gpio123", "gpio124", "gpio125",
> +};
> +
> +static const char *const qup2_se4_01_groups[] = {
> + "gpio208", "gpio209",
> +};
> +
> +static const char *const qup2_se4_23_groups[] = {
> + "gpio208", "gpio209",
> +};
> +
> +static const char *const qup3_se0_01_groups[] = {
> + "gpio64", "gpio65",
> +};
> +
> +static const char *const qup3_se0_23_groups[] = {
> + "gpio64", "gpio65",
> +};
> +
> +static const char *const qup3_se1_groups[] = {
> + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio15",
> +};
> +
> +static const char *const qup3_se2_groups[] = {
> + "gpio12", "gpio13", "gpio14", "gpio15",
> +};
> +
> +static const char *const qup3_se3_groups[] = {
> + "gpio16", "gpio17", "gpio18", "gpio19",
> +};
> +
> +static const char *const qup3_se4_groups[] = {
> + "gpio20", "gpio21", "gpio22", "gpio23",
> +};
> +
> +static const char *const qup3_se5_groups[] = {
> + "gpio24", "gpio25", "gpio26", "gpio27",
> +};
> +
> +static const char *const qup4_se0_groups[] = {
> + "gpio48", "gpio49", "gpio50", "gpio51",
> +};
> +
> +static const char *const qup4_se1_groups[] = {
> + "gpio28", "gpio29", "gpio30", "gpio31",
> +};
> +
> +static const char *const qup4_se2_groups[] = {
> + "gpio32", "gpio33", "gpio34", "gpio35",
> +};
> +
> +static const char *const qup4_se3_01_groups[] = {
> + "gpio84", "gpio121",
> +};
> +
> +static const char *const qup4_se3_23_groups[] = {
> + "gpio84", "gpio121",
> +};
> +
> +static const char *const qup4_se3_l3_groups[] = {
> + "gpio98",
> +};
> +
> +static const char *const qup4_se4_01_groups[] = {
> + "gpio161", "gpio162",
> +};
> +
> +static const char *const qup4_se4_23_groups[] = {
> + "gpio161", "gpio162",
> +};
> +
> +static const char *const qup4_se4_l3_groups[] = {
> + "gpio88",
> +};
> +
> +static const char *const rng_rosc_groups[] = {
> + "gpio64", "gpio65", "gpio66", "gpio84",
> +};
> +
> +static const char *const sd_write_protect_groups[] = {
> + "gpio85",
> +};
> +
> +static const char *const sdc4_clk_groups[] = {
> + "gpio83",
> +};
> +
> +static const char *const sdc4_cmd_groups[] = {
> + "gpio148",
> +};
> +
> +static const char *const sdc4_data_groups[] = {
> + "gpio80", "gpio81", "gpio82", "gpio147",
> +};
> +
> +static const char *const sys_throttle_groups[] = {
> + "gpio99",
> +};
> +
> +static const char *const tb_trig_sdc_groups[] = {
> + "gpio88", "gpio146",
> +};
> +
> +static const char *const tmess_rng_groups[] = {
> + "gpio64", "gpio65", "gpio66", "gpio84",
> +};
> +
> +static const char *const tsense_clm_groups[] = {
> + "gpio10", "gpio87", "gpio97", "gpio99", "gpio105", "gpio106",
> + "gpio159",
> +};
> +
> +static const char *const tsense_pwm_groups[] = {
> + "gpio10", "gpio87", "gpio97", "gpio99", "gpio223", "gpio224",
> + "gpio225",
> +};
> +
> +static const char *const uim0_groups[] = {
> + "gpio126", "gpio127", "gpio128", "gpio129",
> +};
> +
> +static const char *const uim1_groups[] = {
> + "gpio36", "gpio37", "gpio39", "gpio54", "gpio55", "gpio56",
> + "gpio70", "gpio71", "gpio72", "gpio130", "gpio131", "gpio132",
> + "gpio133",
> +};
> +
> +static const char *const usb0_hs_groups[] = {
> + "gpio79",
> +};
> +
> +static const char *const usb_phy_groups[] = {
> + "gpio59", "gpio60",
> +};
> +
> +static const char *const vfr_groups[] = {
> + "gpio146", "gpio151",
> +};
> +
> +static const char *const vsense_trigger_mirnat_groups[] = {
> + "gpio59",
> +};
> +
> +static const char *const wcn_sw_ctrl_groups[] = {
> + "gpio18", "gpio19", "gpio155", "gpio156",
> +};
> +
> +static const struct pinfunction hawi_functions[] = {
> + MSM_GPIO_PIN_FUNCTION(gpio),
> + MSM_PIN_FUNCTION(aoss_cti),
> + MSM_PIN_FUNCTION(atest_char),
> + MSM_PIN_FUNCTION(atest_usb),
> + MSM_PIN_FUNCTION(audio_ext_mclk),
> + MSM_PIN_FUNCTION(audio_ref_clk),
> + MSM_PIN_FUNCTION(cam_mclk),
> + MSM_PIN_FUNCTION(cci_async_in),
> + MSM_PIN_FUNCTION(cci_i2c0),
> + MSM_PIN_FUNCTION(cci_i2c1),
> + MSM_PIN_FUNCTION(cci_i2c2),
> + MSM_PIN_FUNCTION(cci_i2c3),
> + MSM_PIN_FUNCTION(cci_i2c4),
> + MSM_PIN_FUNCTION(cci_i2c5),
> + MSM_PIN_FUNCTION(cci_timer),
> + MSM_PIN_FUNCTION(coex_espmi),
> + MSM_PIN_FUNCTION(coex_uart1_rx),
> + MSM_PIN_FUNCTION(coex_uart1_tx),
> + MSM_PIN_FUNCTION(dbg_out_clk),
> + MSM_PIN_FUNCTION(ddr_bist),
> + MSM_PIN_FUNCTION(ddr_pxi),
> + MSM_PIN_FUNCTION(dp_hot),
> + MSM_PIN_FUNCTION(egpio),
> + MSM_PIN_FUNCTION(gcc_gp),
> + MSM_PIN_FUNCTION(gnss_adc),
> + MSM_PIN_FUNCTION(host_rst),
> + MSM_PIN_FUNCTION(i2chub0_se0),
> + MSM_PIN_FUNCTION(i2chub0_se1),
> + MSM_PIN_FUNCTION(i2chub0_se2),
> + MSM_PIN_FUNCTION(i2chub0_se3),
> + MSM_PIN_FUNCTION(i2chub0_se4),
> + MSM_PIN_FUNCTION(i2s0),
> + MSM_PIN_FUNCTION(i2s1),
> + MSM_PIN_FUNCTION(ibi_i3c),
> + MSM_PIN_FUNCTION(jitter_bist),
> + MSM_PIN_FUNCTION(mdp_esync0),
> + MSM_PIN_FUNCTION(mdp_esync1),
> + MSM_PIN_FUNCTION(mdp_esync2),
> + MSM_PIN_FUNCTION(mdp_vsync),
> + MSM_PIN_FUNCTION(mdp_vsync_e),
> + MSM_PIN_FUNCTION(mdp_vsync_p),
> + MSM_PIN_FUNCTION(mdp_vsync0_out),
> + MSM_PIN_FUNCTION(mdp_vsync1_out),
> + MSM_PIN_FUNCTION(mdp_vsync2_out),
> + MSM_PIN_FUNCTION(mdp_vsync3_out),
> + MSM_PIN_FUNCTION(mdp_vsync5_out),
> + MSM_PIN_FUNCTION(modem_pps_in),
> + MSM_PIN_FUNCTION(modem_pps_out),
> + MSM_PIN_FUNCTION(nav_gpio),
> + MSM_PIN_FUNCTION(nav_gpio0),
> + MSM_PIN_FUNCTION(nav_gpio3),
> + MSM_PIN_FUNCTION(nav_rffe),
> + MSM_PIN_FUNCTION(pcie0_clk_req_n),
> + MSM_PIN_FUNCTION(pcie0_rst_n),
> + MSM_PIN_FUNCTION(pcie1_clk_req_n),
> + MSM_PIN_FUNCTION(phase_flag),
> + MSM_PIN_FUNCTION(pll_bist_sync),
> + MSM_PIN_FUNCTION(pll_clk_aux),
> + MSM_PIN_FUNCTION(qdss_cti),
> + MSM_PIN_FUNCTION(qlink),
> + MSM_PIN_FUNCTION(qspi),
> + MSM_PIN_FUNCTION(qspi_clk),
> + MSM_PIN_FUNCTION(qspi_cs),
> + MSM_PIN_FUNCTION(qup1_se0),
> + MSM_PIN_FUNCTION(qup1_se1),
> + MSM_PIN_FUNCTION(qup1_se2),
> + MSM_PIN_FUNCTION(qup1_se3),
> + MSM_PIN_FUNCTION(qup1_se4),
> + MSM_PIN_FUNCTION(qup1_se5),
> + MSM_PIN_FUNCTION(qup1_se6),
> + MSM_PIN_FUNCTION(qup1_se7),
> + MSM_PIN_FUNCTION(qup2_se0),
> + MSM_PIN_FUNCTION(qup2_se1),
> + MSM_PIN_FUNCTION(qup2_se2),
> + MSM_PIN_FUNCTION(qup2_se3),
> + MSM_PIN_FUNCTION(qup2_se4_01),
> + MSM_PIN_FUNCTION(qup2_se4_23),
> + MSM_PIN_FUNCTION(qup3_se0_01),
> + MSM_PIN_FUNCTION(qup3_se0_23),
> + MSM_PIN_FUNCTION(qup3_se1),
> + MSM_PIN_FUNCTION(qup3_se2),
> + MSM_PIN_FUNCTION(qup3_se3),
> + MSM_PIN_FUNCTION(qup3_se4),
> + MSM_PIN_FUNCTION(qup3_se5),
> + MSM_PIN_FUNCTION(qup4_se0),
> + MSM_PIN_FUNCTION(qup4_se1),
> + MSM_PIN_FUNCTION(qup4_se2),
> + MSM_PIN_FUNCTION(qup4_se3_01),
> + MSM_PIN_FUNCTION(qup4_se3_23),
> + MSM_PIN_FUNCTION(qup4_se3_l3),
> + MSM_PIN_FUNCTION(qup4_se4_01),
> + MSM_PIN_FUNCTION(qup4_se4_23),
> + MSM_PIN_FUNCTION(qup4_se4_l3),
> + MSM_PIN_FUNCTION(rng_rosc),
> + MSM_PIN_FUNCTION(sd_write_protect),
> + MSM_PIN_FUNCTION(sdc4_clk),
> + MSM_PIN_FUNCTION(sdc4_cmd),
> + MSM_PIN_FUNCTION(sdc4_data),
> + MSM_PIN_FUNCTION(sys_throttle),
> + MSM_PIN_FUNCTION(tb_trig_sdc),
> + MSM_PIN_FUNCTION(tmess_rng),
> + MSM_PIN_FUNCTION(tsense_clm),
> + MSM_PIN_FUNCTION(tsense_pwm),
> + MSM_PIN_FUNCTION(uim0),
> + MSM_PIN_FUNCTION(uim1),
> + MSM_PIN_FUNCTION(usb0_hs),
> + MSM_PIN_FUNCTION(usb_phy),
> + MSM_PIN_FUNCTION(vfr),
> + MSM_PIN_FUNCTION(vsense_trigger_mirnat),
> + MSM_PIN_FUNCTION(wcn_sw_ctrl),
> +};
> +
> +/*
> + * Every pin is maintained as a single group, and missing or non-existing pin
> + * would be maintained as dummy group to synchronize pin group index with
> + * pin descriptor registered with pinctrl core.
> + * Clients would not be able to request these dummy pin groups.
> + */
> +static const struct msm_pingroup hawi_groups[] = {
> + [0] = PINGROUP(0, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [1] = PINGROUP(1, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, egpio),
> + [3] = PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, egpio),
> + [4] = PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [5] = PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [6] = PINGROUP(6, qup2_se1, _, _, _, _, _, _, _, _, _, egpio),
> + [7] = PINGROUP(7, qup2_se1, _, _, _, _, _, _, _, _, _, egpio),
> + [8] = PINGROUP(8, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),
> + [9] = PINGROUP(9, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),
> + [10] = PINGROUP(10, qup3_se1, _, tsense_clm, tsense_pwm, _, _, _, _, _, _, _),
> + [11] = PINGROUP(11, qup3_se1, _, _, _, _, _, _, _, _, _, _),
> + [12] = PINGROUP(12, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _),
> + [13] = PINGROUP(13, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _),
> + [14] = PINGROUP(14, qup3_se2, _, _, _, _, _, _, _, _, _, _),
> + [15] = PINGROUP(15, qup3_se2, cci_async_in, qup3_se1, _, _, _, _, _, _, _, _),
> + [16] = PINGROUP(16, qup3_se3, _, _, _, _, _, _, _, _, _, _),
> + [17] = PINGROUP(17, qup3_se3, _, _, _, _, _, _, _, _, _, _),
> + [18] = PINGROUP(18, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _),
> + [19] = PINGROUP(19, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _),
> + [20] = PINGROUP(20, qup3_se4, _, _, _, _, _, _, _, _, _, _),
> + [21] = PINGROUP(21, qup3_se4, _, _, _, _, _, _, _, _, _, _),
> + [22] = PINGROUP(22, qup3_se4, _, _, _, _, _, _, _, _, _, _),
> + [23] = PINGROUP(23, qup3_se4, _, _, _, _, _, _, _, _, _, _),
> + [24] = PINGROUP(24, qup3_se5, _, _, _, _, _, _, _, _, _, _),
> + [25] = PINGROUP(25, qup3_se5, _, _, _, _, _, _, _, _, _, _),
> + [26] = PINGROUP(26, qup3_se5, _, _, _, _, _, _, _, _, _, _),
> + [27] = PINGROUP(27, qup3_se5, qdss_cti, _, _, _, _, _, _, _, _, _),
> + [28] = PINGROUP(28, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [29] = PINGROUP(29, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [30] = PINGROUP(30, qup4_se1, _, _, _, _, _, _, _, _, _, egpio),
> + [31] = PINGROUP(31, qup4_se1, qdss_cti, _, _, _, _, _, _, _, _, egpio),
> + [32] = PINGROUP(32, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _),
> + [33] = PINGROUP(33, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _),
> + [34] = PINGROUP(34, qup4_se2, _, _, _, _, _, _, _, _, _, _),
> + [35] = PINGROUP(35, qup4_se2, _, _, _, _, _, _, _, _, _, _),
> + [36] = PINGROUP(36, qup1_se4, uim1, ibi_i3c, _, _, _, _, _, _, _, _),
> + [37] = PINGROUP(37, qup1_se4, uim1, ibi_i3c, _, _, _, _, _, _, _, _),
> + [38] = PINGROUP(38, qup1_se4, _, _, _, _, _, _, _, _, _, _),
> + [39] = PINGROUP(39, qup1_se4, uim1, _, _, _, _, _, _, _, _, _),
> + [40] = PINGROUP(40, qup1_se2, ddr_bist, _, gnss_adc, _, _, _, _, _, _, _),
> + [41] = PINGROUP(41, qup1_se2, ddr_bist, _, gnss_adc, _, _, _, _, _, _, _),
> + [42] = PINGROUP(42, qup1_se2, gnss_adc, _, _, _, _, _, _, _, _, _),
> + [43] = PINGROUP(43, qup1_se2, _, ddr_pxi, _, _, _, _, _, _, _, _),
> + [44] = PINGROUP(44, qup1_se3, ddr_bist, ddr_pxi, _, _, _, _, _, _, _, _),
> + [45] = PINGROUP(45, qup1_se3, ddr_bist, ddr_pxi, _, _, _, _, _, _, _, _),
> + [46] = PINGROUP(46, qup1_se3, ddr_pxi, _, _, _, _, _, _, _, _, _),
> + [47] = PINGROUP(47, qup1_se3, dp_hot, _, _, _, _, _, _, _, _, _),
> + [48] = PINGROUP(48, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [49] = PINGROUP(49, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
> + [50] = PINGROUP(50, qup4_se0, _, _, _, _, _, _, _, _, _, egpio),
> + [51] = PINGROUP(51, qup4_se0, _, _, _, _, _, _, _, _, _, egpio),
> + [52] = PINGROUP(52, qup1_se5, ddr_pxi, _, _, _, _, _, _, _, _, _),
> + [53] = PINGROUP(53, qup1_se5, _, ddr_pxi, _, _, _, _, _, _, _, _),
> + [54] = PINGROUP(54, qup1_se5, uim1, ddr_pxi, _, _, _, _, _, _, _, _),
> + [55] = PINGROUP(55, qup1_se5, uim1, ddr_pxi, _, _, _, _, _, _, _, _),
> + [56] = PINGROUP(56, qup1_se6, uim1, _, _, _, _, _, _, _, _, _),
> + [57] = PINGROUP(57, qup1_se6, _, _, _, _, _, _, _, _, _, _),
> + [58] = PINGROUP(58, qup1_se6, _, _, _, _, _, _, _, _, _, _),
> + [59] = PINGROUP(59, qup1_se6, usb_phy, vsense_trigger_mirnat, _, _, _, _, _, _, _, _),
> + [60] = PINGROUP(60, qup1_se7, usb_phy, ibi_i3c, _, _, _, _, _, _, _, _),
> + [61] = PINGROUP(61, qup1_se7, ibi_i3c, _, _, _, _, _, _, _, _, _),
> + [62] = PINGROUP(62, qup1_se7, _, _, _, _, _, _, _, _, _, _),
> + [63] = PINGROUP(63, qup1_se7, _, _, _, _, _, _, _, _, _, _),
> + [64] = PINGROUP(64, qup3_se0_01, qup3_se0_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _),
> + [65] = PINGROUP(65, qup3_se0_01, qup3_se0_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _),
> + [66] = PINGROUP(66, i2chub0_se0, rng_rosc, tmess_rng, _, _, _, _, _, _, _, _),
> + [67] = PINGROUP(67, i2chub0_se0, _, _, _, _, _, _, _, _, _, _),
> + [68] = PINGROUP(68, i2chub0_se2, _, _, _, _, _, _, _, _, _, _),
> + [69] = PINGROUP(69, i2chub0_se2, _, _, _, _, _, _, _, _, _, _),
> + [70] = PINGROUP(70, i2chub0_se3, uim1, _, atest_usb, _, _, _, _, _, _, _),
> + [71] = PINGROUP(71, i2chub0_se3, uim1, _, atest_usb, _, _, _, _, _, _, _),
> + [72] = PINGROUP(72, i2chub0_se4, uim1, qdss_cti, _, atest_usb, _, _, _, _, _, _),
> + [73] = PINGROUP(73, i2chub0_se4, qdss_cti, jitter_bist, atest_usb, _, _, _, _, _, _, _),
> + [74] = PINGROUP(74, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),
> + [75] = PINGROUP(75, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),
> + [76] = PINGROUP(76, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),
> + [77] = PINGROUP(77, qup1_se1, aoss_cti, gnss_adc, _, _, _, _, _, _, _, _),
> + [78] = PINGROUP(78, i2chub0_se1, _, _, _, _, _, _, _, _, _, _),
> + [79] = PINGROUP(79, i2chub0_se1, usb0_hs, _, _, _, _, _, _, _, _, _),
> + [80] = PINGROUP(80, qup1_se0, sdc4_data, qspi, _, _, _, _, _, _, _, _),
> + [81] = PINGROUP(81, qup1_se0, sdc4_data, qspi, _, _, _, _, _, _, _, _),
> + [82] = PINGROUP(82, qup1_se0, sdc4_data, qdss_cti, qspi, dbg_out_clk, _, _, _, _, _, _),
> + [83] = PINGROUP(83, qup1_se0, sdc4_clk, qdss_cti, qspi_clk, _, _, _, _, _, _, _),
> + [84] = PINGROUP(84, qup4_se3_01, qup4_se3_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _),
> + [85] = PINGROUP(85, sd_write_protect, _, _, _, _, _, _, _, _, _, _),
> + [86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_esync1, gcc_gp,
> + _, _, _, _, _, _),
> + [87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,
> + mdp_esync2, gcc_gp, _, tsense_clm, tsense_pwm, _, _),
> + [88] = PINGROUP(88, mdp_esync0, mdp_vsync, qup4_se4_l3, tb_trig_sdc, _, _, _, _, _, _, _),
> + [89] = PINGROUP(89, cam_mclk, _, _, _, _, _, _, _, _, _, _),
> + [90] = PINGROUP(90, cam_mclk, _, _, _, _, _, _, _, _, _, _),
> + [91] = PINGROUP(91, cam_mclk, _, _, _, _, _, _, _, _, _, _),
> + [92] = PINGROUP(92, cam_mclk, _, _, _, _, _, _, _, _, _, _),
> + [93] = PINGROUP(93, cam_mclk, _, _, _, _, _, _, _, _, _, _),
> + [94] = PINGROUP(94, cam_mclk, pll_clk_aux, _, _, _, _, _, _, _, _, _),
> + [95] = PINGROUP(95, cam_mclk, _, _, _, _, _, _, _, _, _, _),
> + [96] = PINGROUP(96, cam_mclk, _, _, _, _, _, _, _, _, _, _),
> + [97] = PINGROUP(97, mdp_esync2, qup2_se3, mdp_vsync, tsense_clm, tsense_pwm, _, _,
> + _, _, _, _),
> + [98] = PINGROUP(98, mdp_vsync_e, qup4_se3_l3, mdp_vsync_p, _, _, _, _, _, _, _, _),
> + [99] = PINGROUP(99, sys_throttle, tsense_clm, tsense_pwm, _, _, _, _, _, _, _, _),
> + [100] = PINGROUP(100, mdp_esync1, mdp_esync0, _, _, _, _, _, _, _, _, _),
> + [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _),
> + [102] = PINGROUP(102, pcie0_rst_n, _, _, _, _, _, _, _, _, _, _),
> + [103] = PINGROUP(103, pcie0_clk_req_n, _, _, _, _, _, _, _, _, _, _),
> + [104] = PINGROUP(104, pll_bist_sync, _, _, _, _, _, _, _, _, _, _),
> + [105] = PINGROUP(105, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _),
> + [106] = PINGROUP(106, host_rst, cci_timer, tsense_clm, _, _, _, _, _, _, _, _),
> + [107] = PINGROUP(107, cci_i2c3, cci_timer, _, _, _, _, _, _, _, _, _),
> + [108] = PINGROUP(108, cci_i2c4, _, _, _, _, _, _, _, _, _, _),
> + [109] = PINGROUP(109, cci_i2c0, cci_async_in, _, _, _, _, _, _, _, _, _),
> + [110] = PINGROUP(110, cci_i2c0, cci_async_in, _, _, _, _, _, _, _, _, _),
> + [111] = PINGROUP(111, cci_i2c1, _, _, _, _, _, _, _, _, _, _),
> + [112] = PINGROUP(112, cci_i2c1, _, _, _, _, _, _, _, _, _, _),
> + [113] = PINGROUP(113, cci_i2c2, _, _, _, _, _, _, _, _, _, _),
> + [114] = PINGROUP(114, cci_i2c2, _, _, _, _, _, _, _, _, _, _),
> + [115] = PINGROUP(115, cci_i2c5, _, _, _, _, _, _, _, _, _, _),
> + [116] = PINGROUP(116, cci_i2c5, _, _, _, _, _, _, _, _, _, _),
> + [117] = PINGROUP(117, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),
> + [118] = PINGROUP(118, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),
> + [119] = PINGROUP(119, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),
> + [120] = PINGROUP(120, i2s1, qup2_se2, audio_ext_mclk, audio_ref_clk, _, _,
> + _, _, _, _, _),
> + [121] = PINGROUP(121, audio_ext_mclk, qup4_se3_01, qup4_se3_23, _, _, _, _, _, _, _, _),
> + [122] = PINGROUP(122, i2s0, qup2_se3, _, _, _, _, _, _, _, _, _),
> + [123] = PINGROUP(123, i2s0, qup2_se3, _, phase_flag, _, _, _, _, _, _, _),
> + [124] = PINGROUP(124, i2s0, qup2_se3, _, phase_flag, _, _, _, _, _, _, _),
> + [125] = PINGROUP(125, i2s0, qup2_se3, phase_flag, _, _, _, _, _, _, _, _),
> + [126] = PINGROUP(126, uim0, atest_char, _, _, _, _, _, _, _, _, _),
> + [127] = PINGROUP(127, uim0, atest_char, _, _, _, _, _, _, _, _, _),
> + [128] = PINGROUP(128, uim0, atest_char, _, _, _, _, _, _, _, _, _),
> + [129] = PINGROUP(129, uim0, atest_usb, atest_char, _, _, _, _, _, _, _, _),
> + [130] = PINGROUP(130, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),
> + [131] = PINGROUP(131, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),
> + [132] = PINGROUP(132, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),
> + [133] = PINGROUP(133, uim1, atest_char, _, _, _, _, _, _, _, _, _),
> + [134] = PINGROUP(134, _, _, nav_rffe, _, _, _, _, _, _, _, _),
> + [135] = PINGROUP(135, _, _, nav_rffe, _, _, _, _, _, _, _, _),
> + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _),
> + [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _),
> + [138] = PINGROUP(138, _, _, nav_rffe, _, _, _, _, _, _, _, _),
> + [139] = PINGROUP(139, _, _, nav_rffe, _, _, _, _, _, _, _, _),
> + [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _, _, _),
> + [141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, _),
> + [142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, _),
> + [143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, _),
> + [144] = PINGROUP(144, coex_uart1_rx, coex_espmi, _, _, _, _, _, _, _, _, _),
> + [145] = PINGROUP(145, coex_uart1_tx, coex_espmi, _, _, _, _, _, _, _, _, _),
> + [146] = PINGROUP(146, _, vfr, nav_gpio, tb_trig_sdc, qspi_cs, _, _, _, _, _, _),
> + [147] = PINGROUP(147, _, nav_gpio, sdc4_data, qspi, _, _, _, _, _, _, _),
> + [148] = PINGROUP(148, nav_gpio, _, sdc4_cmd, qspi_cs, _, _, _, _, _, _, _),
> + [149] = PINGROUP(149, cci_i2c4, _, _, _, _, _, _, _, _, _, _),
> + [150] = PINGROUP(150, nav_gpio0, nav_gpio3, _, _, _, _, _, _, _, _, _),
> + [151] = PINGROUP(151, nav_gpio, vfr, modem_pps_in, modem_pps_out, _, _, _, _, _, _, _),
> + [152] = PINGROUP(152, qlink, qdss_cti, _, _, _, _, _, _, _, _, _),
> + [153] = PINGROUP(153, qlink, _, _, _, _, _, _, _, _, _, _),
> + [154] = PINGROUP(154, qlink, _, _, _, _, _, _, _, _, _, _),
> + [155] = PINGROUP(155, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _),
> + [156] = PINGROUP(156, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _),
> + [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _),
> + [158] = PINGROUP(158, qdss_cti, gcc_gp, _, _, _, _, _, _, _, _, _),
> + [159] = PINGROUP(159, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _),
> + [160] = PINGROUP(160, cci_timer, cci_i2c3, _, _, _, _, _, _, _, _, _),
> + [161] = PINGROUP(161, qup4_se4_01, qup4_se4_23, _, _, _, _, _, _, _, _, _),
> + [162] = PINGROUP(162, qup4_se4_01, qup4_se4_23, _, _, _, _, _, _, _, _, _),
> + [163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, egpio),
> + [164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, egpio),
> + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, egpio),
> + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, egpio),
> + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _, _, egpio),
> + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _, _, egpio),
> + [169] = PINGROUP(169, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [170] = PINGROUP(170, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [171] = PINGROUP(171, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [172] = PINGROUP(172, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [173] = PINGROUP(173, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _, _, egpio),
> + [175] = PINGROUP(175, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [176] = PINGROUP(176, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _, _, egpio),
> + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _, _, egpio),
> + [179] = PINGROUP(179, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [180] = PINGROUP(180, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [181] = PINGROUP(181, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _, _, egpio),
> + [183] = PINGROUP(183, _, _, _, _, _, _, _, _, _, _, egpio),
> + [184] = PINGROUP(184, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [185] = PINGROUP(185, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _, _, egpio),
> + [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _, _, egpio),
> + [188] = PINGROUP(188, _, _, _, _, _, _, _, _, _, _, egpio),
> + [189] = PINGROUP(189, _, _, _, _, _, _, _, _, _, _, egpio),
> + [190] = PINGROUP(190, _, _, _, _, _, _, _, _, _, _, egpio),
> + [191] = PINGROUP(191, _, _, _, _, _, _, _, _, _, _, egpio),
> + [192] = PINGROUP(192, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [193] = PINGROUP(193, _, _, _, _, _, _, _, _, _, _, egpio),
> + [194] = PINGROUP(194, _, _, _, _, _, _, _, _, _, _, egpio),
> + [195] = PINGROUP(195, _, _, _, _, _, _, _, _, _, _, egpio),
> + [196] = PINGROUP(196, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [197] = PINGROUP(197, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [198] = PINGROUP(198, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [199] = PINGROUP(199, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [200] = PINGROUP(200, _, _, _, _, _, _, _, _, _, _, egpio),
> + [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _, _, egpio),
> + [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _, _, egpio),
> + [203] = PINGROUP(203, _, _, _, _, _, _, _, _, _, _, egpio),
> + [204] = PINGROUP(204, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [205] = PINGROUP(205, _, _, _, _, _, _, _, _, _, _, egpio),
> + [206] = PINGROUP(206, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [207] = PINGROUP(207, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [208] = PINGROUP(208, qup2_se4_01, qup2_se4_23, phase_flag, _, _, _, _, _, _, _, egpio),
> + [209] = PINGROUP(209, qup2_se4_01, qup2_se4_23, _, _, _, _, _, _, _, _, egpio),
> + [210] = PINGROUP(210, phase_flag, _, _, _, _, _, _, _, _, _, _),
> + [211] = PINGROUP(211, phase_flag, _, _, _, _, _, _, _, _, _, _),
> + [212] = PINGROUP(212, _, _, _, _, _, _, _, _, _, _, egpio),
> + [213] = PINGROUP(213, _, _, _, _, _, _, _, _, _, _, egpio),
> + [214] = PINGROUP(214, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [215] = PINGROUP(215, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [216] = PINGROUP(216, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
> + [217] = PINGROUP(217, _, _, _, _, _, _, _, _, _, _, egpio),
> + [218] = PINGROUP(218, _, _, _, _, _, _, _, _, _, _, egpio),
> + [219] = PINGROUP(219, _, _, _, _, _, _, _, _, _, _, _),
> + [220] = PINGROUP(220, _, _, _, _, _, _, _, _, _, _, _),
> + [221] = PINGROUP(221, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _),
> + [222] = PINGROUP(222, _, _, _, _, _, _, _, _, _, _, _),
> + [223] = PINGROUP(223, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
> + [224] = PINGROUP(224, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
> + [225] = PINGROUP(225, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
> + [226] = UFS_RESET(ufs_reset, 0xf1004, 0xf2000),
> + [227] = SDC_QDSD_PINGROUP(sdc2_clk, 0xe6000, 14, 6),
> + [228] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xe6000, 11, 3),
> + [229] = SDC_QDSD_PINGROUP(sdc2_data, 0xe6000, 9, 0),
> +};
> +
> +static const struct msm_gpio_wakeirq_map hawi_pdc_map[] = {
> + { 0, 105 }, { 3, 113 }, { 4, 106 }, { 7, 107 }, { 8, 108 }, { 11, 109 },
> + { 12, 115 }, { 15, 131 }, { 16, 116 }, { 17, 141 }, { 18, 143 }, { 19, 112 },
> + { 23, 117 }, { 24, 118 }, { 27, 119 }, { 28, 125 }, { 31, 126 }, { 32, 127 },
> + { 35, 101 }, { 36, 128 }, { 39, 129 }, { 43, 130 }, { 47, 154 }, { 48, 135 },
> + { 51, 114 }, { 55, 104 }, { 57, 136 }, { 58, 137 }, { 59, 138 }, { 60, 139 },
> + { 61, 145 }, { 63, 124 }, { 64, 110 }, { 65, 123 }, { 67, 132 }, { 68, 146 },
> + { 69, 147 }, { 75, 151 }, { 77, 148 }, { 78, 149 }, { 79, 155 }, { 80, 156 },
> + { 81, 157 }, { 82, 158 }, { 84, 134 }, { 85, 159 }, { 86, 160 }, { 87, 161 },
> + { 88, 162 }, { 95, 163 }, { 96, 164 }, { 97, 133 }, { 98, 150 }, { 99, 111 },
> + { 101, 165 }, { 102, 166 }, { 103, 167 }, { 104, 168 }, { 120, 169 }, { 123, 170 },
> + { 125, 171 }, { 129, 153 }, { 133, 100 }, { 144, 172 }, { 146, 173 }, { 151, 174 },
> + { 152, 175 }, { 155, 122 }, { 158, 120 }, { 162, 142 }, { 164, 176 }, { 165, 177 },
> + { 167, 178 }, { 168, 179 }, { 174, 180 }, { 177, 181 }, { 179, 182 }, { 183, 183 },
> + { 184, 184 }, { 185, 185 }, { 186, 152 }, { 188, 144 }, { 202, 102 }, { 203, 103 },
> + { 205, 140 }, { 209, 186 }, { 213, 121 }, { 216, 187 }, { 221, 188 }, { 222, 189 },
> + { 223, 190 }, { 224, 191 }, { 225, 192 },
> +};
> +
> +static const struct msm_pinctrl_soc_data hawi_tlmm = {
> + .pins = hawi_pins,
> + .npins = ARRAY_SIZE(hawi_pins),
> + .functions = hawi_functions,
> + .nfunctions = ARRAY_SIZE(hawi_functions),
> + .groups = hawi_groups,
> + .ngroups = ARRAY_SIZE(hawi_groups),
> + .ngpios = 227,
> + .wakeirq_map = hawi_pdc_map,
> + .nwakeirq_map = ARRAY_SIZE(hawi_pdc_map),
> + .egpio_func = 11,
> +};
> +
> +static int hawi_tlmm_probe(struct platform_device *pdev)
> +{
> + return msm_pinctrl_probe(pdev, &hawi_tlmm);
> +}
> +
> +static const struct of_device_id hawi_tlmm_of_match[] = {
> + { .compatible = "qcom,hawi-tlmm", },
> + {},
> +};
> +
> +static struct platform_driver hawi_tlmm_driver = {
> + .driver = {
> + .name = "hawi-tlmm",
> + .of_match_table = hawi_tlmm_of_match,
> + },
> + .probe = hawi_tlmm_probe,
> +};
> +
> +static int __init hawi_tlmm_init(void)
> +{
> + return platform_driver_register(&hawi_tlmm_driver);
> +}
> +arch_initcall(hawi_tlmm_init);
> +
> +static void __exit hawi_tlmm_exit(void)
> +{
> + platform_driver_unregister(&hawi_tlmm_driver);
> +}
> +module_exit(hawi_tlmm_exit);
> +
> +MODULE_DESCRIPTION("QTI Hawi TLMM driver");
> +MODULE_LICENSE("GPL");
> +MODULE_DEVICE_TABLE(of, hawi_tlmm_of_match);
>
> --
> 2.53.0
>
^ permalink raw reply
* Re: [PATCH v2 3/5] arm64: dts: qcom: sm8550: move IPA properties to SoC device tree
From: Dmitry Baryshkov @ 2026-04-09 1:45 UTC (permalink / raw)
To: Joe Sandom
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260407-rb5gen2-dts-v2-3-d0c7f447ee73@axon.com>
On Tue, Apr 07, 2026 at 04:46:46PM +0100, Joe Sandom wrote:
> Move qcom,gsi-loader and memory-region properties from individual board
> DTS files into the SoC DTSI, since these are common to all SM8550-based
> boards.
>
> Signed-off-by: Joe Sandom <jsandom@axon.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 --
> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 --
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 ++
> 3 files changed, 2 insertions(+), 4 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 2/5] arm64: dts: qcom: sm8550: add PCIe port labels
From: Dmitry Baryshkov @ 2026-04-09 1:45 UTC (permalink / raw)
To: Joe Sandom
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260407-rb5gen2-dts-v2-2-d0c7f447ee73@axon.com>
On Tue, Apr 07, 2026 at 04:46:45PM +0100, Joe Sandom wrote:
> Add labels to the root port nodes (pcie0_port0, pcie1_port0) to
> allow board DTS files to reference them for adding endpoint devices
> to each pcie root port.
>
> Update the pcieport0 reference to pcie0_port0 in sm8550-hdk.dts and
> sm8550-qrd.dts to match the label rename in sm8550.dtsi.
>
> Signed-off-by: Joe Sandom <jsandom@axon.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 +-
> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 +-
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++--
> 3 files changed, 4 insertions(+), 4 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 19/19] gpio: add GPIO controller found on Waveshare DSI TOUCH panels
From: Dmitry Baryshkov @ 2026-04-09 1:26 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: dri-devel, devicetree, linux-kernel, linux-gpio, Neil Armstrong,
Jessica Zhang, David Airlie, Simona Vetter, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij
In-Reply-To: <CAMRc=Mcusnm-k76e6jTiwrw5xJL7f-nWBsg4=QpD08cv8pPgMw@mail.gmail.com>
On Fri, Apr 03, 2026 at 08:30:22AM -0400, Bartosz Golaszewski wrote:
> On Wed, 1 Apr 2026 09:26:38 +0200, Dmitry Baryshkov
> <dmitry.baryshkov@oss.qualcomm.com> said:
> > The Waveshare DSI TOUCH family of panels has separate on-board GPIO
> > controller, which controls power supplies to the panel and the touch
> > screen and provides reset pins for both the panel and the touchscreen.
> > Also it provides a simple PWM controller for panel backlight. Add
> > support for this GPIO controller.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > ---
> > drivers/gpio/Kconfig | 10 ++
> > drivers/gpio/Makefile | 1 +
> > drivers/gpio/gpio-waveshare-dsi.c | 220 ++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 231 insertions(+)
> >
> > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> > index 4c3f6ec336c1..f0bb5cdebf9b 100644
> > --- a/drivers/gpio/Kconfig
> > +++ b/drivers/gpio/Kconfig
> > @@ -804,6 +804,16 @@ config GPIO_VISCONTI
> > help
> > Say yes here to support GPIO on Tohisba Visconti.
> >
> > +config GPIO_WAVESHARE_DSI_TOUCH
> > + tristate "Waveshare GPIO controller for DSI panels"
> > + depends on BACKLIGHT_CLASS_DEVICE
> > + depends on I2C
> > + select REGMAP_I2C
> > + help
> > + Enable support for the GPIO and PWM controller found on Waveshare DSI
> > + TOUCH panel kits. It provides GPIOs (used for regulator control and
> > + resets) and backlight support.
> > +
> > config GPIO_WCD934X
> > tristate "Qualcomm Technologies Inc WCD9340/WCD9341 GPIO controller driver"
> > depends on MFD_WCD934X
> > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> > index 20d4a57afdaa..75ce89fc3b93 100644
> > --- a/drivers/gpio/Makefile
> > +++ b/drivers/gpio/Makefile
> > @@ -207,6 +207,7 @@ obj-$(CONFIG_GPIO_VIRTUSER) += gpio-virtuser.o
> > obj-$(CONFIG_GPIO_VIRTIO) += gpio-virtio.o
> > obj-$(CONFIG_GPIO_VISCONTI) += gpio-visconti.o
> > obj-$(CONFIG_GPIO_VX855) += gpio-vx855.o
> > +obj-$(CONFIG_GPIO_WAVESHARE_DSI_TOUCH) += gpio-waveshare-dsi.o
> > obj-$(CONFIG_GPIO_WCD934X) += gpio-wcd934x.o
> > obj-$(CONFIG_GPIO_WHISKEY_COVE) += gpio-wcove.o
> > obj-$(CONFIG_GPIO_WINBOND) += gpio-winbond.o
> > diff --git a/drivers/gpio/gpio-waveshare-dsi.c b/drivers/gpio/gpio-waveshare-dsi.c
> > new file mode 100644
> > index 000000000000..30fe7569c150
> > --- /dev/null
> > +++ b/drivers/gpio/gpio-waveshare-dsi.c
> > @@ -0,0 +1,220 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2024 Waveshare International Limited
> > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> > + */
> > +
> > +#include <linux/backlight.h>
> > +#include <linux/err.h>
> > +#include <linux/fb.h>
> > +#include <linux/gpio/driver.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/regmap.h>
> > +
> > +/* I2C registers of the microcontroller. */
> > +#define REG_TP 0x94
> > +#define REG_LCD 0x95
> > +#define REG_PWM 0x96
> > +#define REG_SIZE 0x97
> > +#define REG_ID 0x98
> > +#define REG_VERSION 0x99
> > +
> > +enum {
> > + GPIO_AVDD = 0,
> > + GPIO_PANEL_RESET = 1,
> > + GPIO_BL_ENABLE = 2,
> > + GPIO_IOVCC = 4,
> > + GPIO_VCC = 8,
> > + GPIO_TS_RESET = 9,
> > + NUM_GPIO = 16,
>
> Why is this part of an enum?
I'll move this out of the enum.
>
> > +static int waveshare_gpio_set(struct waveshare_gpio *state, unsigned int offset, int value)
> > +{
> > + u16 last_val;
> > +
> > + mutex_lock(&state->pwr_lock);
>
> Can you use guards for locks?
Yes
>
> > +
> > + last_val = state->poweron_state;
> > + if (value)
> > + last_val |= BIT(offset);
> > + else
> > + last_val &= ~BIT(offset);
> > +
> > + state->poweron_state = last_val;
> > +
> > + regmap_write(state->regmap, REG_TP, last_val >> 8);
> > + regmap_write(state->regmap, REG_LCD, last_val & 0xff);
>
> I2C regmap writes can fail and their return value should be checked.
Ack.
>
> > +
> > + mutex_unlock(&state->pwr_lock);
> > +
> > + return 0;
> > +}
> > +
[...]
> > +
> > +static int waveshare_gpio_update_status(struct backlight_device *bl)
> > +{
> > + struct waveshare_gpio *state = bl_get_data(bl);
> > + int brightness = backlight_get_brightness(bl);
> > +
> > + waveshare_gpio_set(state, GPIO_BL_ENABLE, brightness);
> > +
> > + return regmap_write(state->regmap, REG_PWM, brightness);
> > +}
> > +
[...]
> > +static int waveshare_gpio_probe(struct i2c_client *i2c)
> > +{
[...]
> > +
> > + dev_dbg(dev, "waveshare panel mcu version = 0x%x\n", data);
> > +
> > + state->poweron_state = BIT(GPIO_TS_RESET);
> > + regmap_write(regmap, REG_TP, state->poweron_state >> 8);
> > + regmap_write(regmap, REG_LCD, state->poweron_state & 0xff);
And this can become waveshare_gpio_set().
> > + msleep(20);
> > +
> > + state->regmap = regmap;
> > + state->gc.parent = dev;
> > + state->gc.label = i2c->name;
> > + state->gc.owner = THIS_MODULE;
> > + state->gc.base = -1;
> > + state->gc.ngpio = NUM_GPIO;
> > +
> > + /* it is output only */
> > + state->gc.get = waveshare_gpio_gpio_get;
> > + state->gc.set = waveshare_gpio_gpio_set;
> > + state->gc.get_direction = waveshare_gpio_gpio_get_direction;
> > + state->gc.can_sleep = true;
> > +
> > + ret = devm_gpiochip_add_data(dev, &state->gc, state);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "Failed to create gpiochip\n");
> > +
>
> This driver looks like it could be easily converted to use gpio-regmap and
> become much shorter in the process. Could you please take a look at
> linux/gpio/regmap.h?
I took a glance. It is a nice wrapper, but I think being able to call
waveshare_gpio_set() internally without extra troubles overweights the
bonuses of the wrapper. Also, I'd agree if there were extra complexity
here (e.g. the stride or the in/out handling), but having just the out
GPIOs doesn't seem to warrant it.
An alternative would be to split away the backlight into a separate
pwm-backlight device. Then having waveshare_gpio_set() isn't that
important and thus I could switch to GPIO_REGMAP. But then... We don't
have real control over the PWM. We are really programming some values,
with the actual PWM duty cycle calculations being handled internally.
With all that in mind, unless you really insist, I'd prefer to leave
this part the driver as is.
>
> > + props.type = BACKLIGHT_RAW;
> > + props.max_brightness = 255;
> > + props.brightness = 255;
> > + bl = devm_backlight_device_register(dev, dev_name(dev), dev, state,
> > + &waveshare_gpio_bl, &props);
> > + return PTR_ERR_OR_ZERO(bl);
> > +}
> > +
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2] net: dsa: microchip: implement KSZ87xx Module 3 low-loss cable errata
From: Marek Vasut @ 2026-04-09 1:04 UTC (permalink / raw)
To: Fidelio Lawson, Woojung Huh, UNGLinuxDriver, Andrew Lunn,
Vladimir Oltean, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Marek Vasut, Maxime Chevallier
Cc: netdev, devicetree, linux-kernel, Fidelio Lawson
In-Reply-To: <20260408-ksz87xx_errata_low_loss_connections-v2-1-9cfe38691713@exotec.com>
On 4/8/26 1:57 PM, Fidelio Lawson wrote:
> Implement the "Module 3: Equalizer fix for short cables" erratum from
> Microchip document DS80000687C for KSZ87xx switches.
>
> The issue affects short or low-loss cable links (e.g. CAT5e/CAT6),
> where the PHY receiver equalizer may amplify high-amplitude signals
> excessively, resulting in internal distortion and link establishment
> failures.
>
> KSZ87xx devices require a workaround for the Module 3 low-loss cable
> condition, controlled through the switch TABLE_LINK_MD_V indirect
> registers.
>
> The affected registers are part of the switch address space and are not
> directly accessible from the PHY driver. To keep the PHY-facing API
> clean and avoid leaking switch-specific details, model this errata
> control as vendor-specific Clause 22 PHY registers.
>
> Two vendor-defined bits are introduced in PHY_REG_LOW_LOSS_CTRL,
> and ksz8_r_phy() / ksz8_w_phy() translate accesses to these bits
> into the appropriate indirect TABLE_LINK_MD_V accesses.
>
> The control register defines the following modes:
> bits [1:0]:
> 00 = workaround disabled
> 01 = workaround 1 (DSP EQ training adjustment, LinkMD reg 0x3c)
> 10 = workaround 2 (receiver LPF bandwidth, LinkMD reg 0x4c)
>
> Workaround 1: Adjusts the DSP EQ training behavior via LinkMD register
> 0x3C. Widens and optimizes the DSP EQ compensation range,
> and is expected to solve most short/low-loss cable issues.
>
> Workaround 2: for the cases where Workaround 1 is not sufficient.
> This one adjusts the receiver low-pass filter bandwidth, effectively
> reducing the high-frequency component of the received signal
>
> The register is accessible through standard PHY read/write operations
> (e.g. phytool), without requiring any switch-specific userspace
> interface. This allows robust link establishment on short or
> low-loss cabling without requiring DTS properties and without
> constraining hardware design choices.
>
> The erratum affects the shared PHY analog front-end and therefore
> applies globally to the switch.
>
> Signed-off-by: Fidelio Lawson <fidelio.lawson@exotec.com>
> ---
> Hello,
>
> This patch implements the “Module 3: Equalizer fix for short cables” erratum
> described in Microchip document DS80000687C for KSZ87xx switches.
>
> According to the erratum, the embedded PHY receiver in KSZ87xx switches is
> tuned by default for long, high-loss Ethernet cables. When operating with
> short or low-loss cables (for example CAT5e or CAT6), the PHY equalizer may
> over-amplify the incoming signal, leading to internal distortion and link
> establishment failures.
>
> Microchip provides two workarounds, each requiring a write to a different
> indirect PHY register access mechanism.
>
> The workaround requires programming internal PHY/DSP registers located in the
> LinkMD table, accessed through the KSZ8 indirect register mechanism. Since these
> registers belong to the switch address space and are not directly accessible
> from a standalone PHY driver, the erratum control is modeled as a vendor-specific
> Clause 22 PHY register, virtualized by the KSZ8 DSA driver.
>
> Reads and writes to this register are intercepted by ksz8_r_phy() /
> ksz8_w_phy() and translated into the required TABLE_LINK_MD_V indirect accesses.
> The erratum affects the shared PHY analog front-end and therefore applies
> globally to the switch.
>
> The register defines three modes:
> - 0x0: workaround disabled
> - 0x1: workaround 1 (DSP EQ training adjustment)
> - 0x2: workaround 2 (receiver low-pass filter bandwidth reduction)
>
> The register can be read and written from userspace via standard Clause 22 PHY
> accesses (for example using phytool) on DSA user ports.
>
> This series is based on Linux v7.0-rc1.
> ---
> Changes in v2:
> - Dropped the device tree approache based on review feedback
> - Modeled the errata control as a vendor-specific Clause 22 PHY register
> - Added KSZ87xx-specific guards and replaced magic values with named macros
> - Rebased on Linux v7.0-rc1
> - Link to v1: https://patch.msgid.link/20260326-ksz87xx_errata_low_loss_connections-v1-0-79a698f43626@exotec.com
> ---
> drivers/net/dsa/microchip/ksz8.c | 33 +++++++++++++++++++++++++++++++++
> drivers/net/dsa/microchip/ksz8_reg.h | 20 +++++++++++++++++++-
> drivers/net/dsa/microchip/ksz_common.h | 3 +++
> 3 files changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/dsa/microchip/ksz8.c b/drivers/net/dsa/microchip/ksz8.c
> index c354abdafc1b..d11da6e9ff54 100644
> --- a/drivers/net/dsa/microchip/ksz8.c
> +++ b/drivers/net/dsa/microchip/ksz8.c
> @@ -1058,6 +1058,11 @@ int ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
> if (ret)
> return ret;
>
> + break;
> + case PHY_REG_KSZ87XX_LOW_LOSS:
> + if (!ksz_is_ksz87xx(dev))
> + return -EOPNOTSUPP;
> + data = dev->low_loss_wa_mode;
> break;
> default:
> processed = false;
> @@ -1271,6 +1276,34 @@ int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
> if (ret)
> return ret;
> break;
> + case PHY_REG_KSZ87XX_LOW_LOSS:
> + if (!ksz_is_ksz87xx(dev))
> + return -EOPNOTSUPP;
> +
> + switch (val & PHY_KSZ87XX_LOW_LOSS_MASK) {
> + case PHY_LOW_LOSS_ERRATA_DISABLED:
> + ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_EQ_TRAIN,
> + KSZ87XX_EQ_TRAIN_DEFAULT);
> + if (!ret)
> + ret = ksz8_ind_write8(dev, TABLE_LINK_MD,
> + KSZ87XX_REG_PHY_LPF,
> + KSZ87XX_PHY_LPF_DEFAULT);
> + break;
> + case KSZ87XX_LOW_LOSS_WA_EQ:
> + ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_EQ_TRAIN,
> + KSZ87XX_EQ_TRAIN_LOW_LOSS);
> + break;
> + case KSZ87XX_LOW_LOSS_WA_LPF:
> + ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_PHY_LPF,
> + KSZ87XX_PHY_LPF_62MHZ);
Please adjust this and make the low pass filter bandwidth actually
configurable according to the values supported by the hardware, see this
article:
https://microchip.my.site.com/s/article/Solution-for-Using-CAT-5E-or-CAT-6-Short-Cable-with-a-Link-Issue-for-the-KSZ8795-Family
The indirect register (0x4C) is an 8-bit register. The bits [7:6] are
described in the table below.
Low pass filter bandwidth
00 = 90MHz
01 = 62MHz
10 = 55MHz
11 = 44MHz
...
^ permalink raw reply
* Re: [PATCH 14/19] drm/panel: jadard-jd9365da-h3: support Waveshare DSI panels
From: Dmitry Baryshkov @ 2026-04-09 0:49 UTC (permalink / raw)
To: Linus Walleij
Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Bartosz Golaszewski, dri-devel, devicetree, linux-kernel,
linux-gpio
In-Reply-To: <CAD++jL=jUd4sQ1bhwcBRYpFFApP6vdJw2BoQwxoWShUKdEb9oA@mail.gmail.com>
On Wed, Apr 08, 2026 at 10:24:17AM +0200, Linus Walleij wrote:
> Hi Dmitry,
>
> thanks for your patch!
>
> On Wed, Apr 1, 2026 at 9:27 AM Dmitry Baryshkov
> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>
> > Add configuration for Waveshare DSI panels using JD9365 controller.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>
> Some more words with details on all the panels added perhaps?
:D
>
> > - desc = of_device_get_match_data(dev);
> > + jd9365da_switch_page(&dsi_ctx, 0x01);
> > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);
> > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x41);
>
> Predictably I'm not very happy with all the unexplained magic and nonestisting
> defines used here. Do you have some info/defines?
No, unfortunately.
>
> But there is also one more thing, this looks like a big "jam table"
> with just register+value tuples, so construct something like:
>
> struct jadard_jam_tbl_entry {
> u8 reg;
> u8 val;
> };
>
> static const struct jadard_jam_tbl_entry jd_3_4_c_init_jam[] = {
> {0x00, 0x00}, {0x01, 0x41}, ...};
>
> (Ideas taken from drivers/net/dsa/realtek/rtl8366rb.c, take a look
> for code and all, you get the picture.)
Few months ago the code was moved exactly in the opposite direction. We
added all _multi() functions and made shure that the code is as
efficient as the register tables. On the other hand, having it as a code
allows better control. E.g. handling 2/4 lane case would require extra
hacks to the register tables, while the code handles that without extra
hacks and without loosing effectiveness.
>
> Yours,
> Linus Walleij
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH 2/2] pwm: pxa: Add optional bus clock
From: Yixun Lan @ 2026-04-09 0:45 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Duje Mihanović
Cc: linux-pwm, devicetree, linux-kernel, linux-riscv, spacemit,
Yixun Lan
In-Reply-To: <20260409-03-k3-pwm-drv-v1-0-1307a06fba38@kernel.org>
Add one secondary optional bus clock for the PWM PXA driver, also keep it
compatible with old single clock.
The SpacemiT K3 SoC require one bus clock for PWM controller, acquire
and enable it during probe phase.
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
drivers/pwm/pwm-pxa.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c
index 0f5bdb0e395e..2ace31405c2d 100644
--- a/drivers/pwm/pwm-pxa.c
+++ b/drivers/pwm/pwm-pxa.c
@@ -53,6 +53,7 @@ struct pxa_pwm_chip {
struct device *dev;
struct clk *clk;
+ struct clk *bus_clk;
void __iomem *mmio_base;
};
@@ -177,7 +178,12 @@ static int pwm_probe(struct platform_device *pdev)
return PTR_ERR(chip);
pc = to_pxa_pwm_chip(chip);
- pc->clk = devm_clk_get(dev, NULL);
+ pc->bus_clk = devm_clk_get_optional_enabled(dev, "bus");
+ if (IS_ERR(pc->bus_clk))
+ return dev_err_probe(dev, PTR_ERR(pc->bus_clk), "Failed to get bus clock\n");
+
+ /* Get named func clk if bus clock is valid */
+ pc->clk = devm_clk_get(dev, pc->bus_clk ? "func" : NULL);
if (IS_ERR(pc->clk))
return dev_err_probe(dev, PTR_ERR(pc->clk), "Failed to get clock\n");
--
2.53.0
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K3 PWM support
From: Yixun Lan @ 2026-04-09 0:45 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Duje Mihanović
Cc: linux-pwm, devicetree, linux-kernel, linux-riscv, spacemit,
Yixun Lan
In-Reply-To: <20260409-03-k3-pwm-drv-v1-0-1307a06fba38@kernel.org>
The PWM controller in SpacemiT K3 SoC reuse the same IP as previous K1
generation, while the difference is that one additional bus clock is
added.
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
.../devicetree/bindings/pwm/marvell,pxa-pwm.yaml | 53 ++++++++++++++++++++--
1 file changed, 50 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml
index 8df327e52810..3427c8ef3945 100644
--- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml
@@ -15,7 +15,9 @@ allOf:
properties:
compatible:
contains:
- const: spacemit,k1-pwm
+ enum:
+ - spacemit,k1-pwm
+ - spacemit,k3-pwm
then:
properties:
"#pwm-cells":
@@ -26,6 +28,38 @@ allOf:
const: 1
description: |
Used for specifying the period length in nanoseconds.
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - spacemit,k3-pwm
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: func
+ - const: bus
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - spacemit,k3-pwm
+ then:
+ required:
+ - clock-names
+ properties:
+ clocks:
+ minItems: 2
+ clock-names:
+ minItems: 2
+ else:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ maxItems: 1
properties:
compatible:
@@ -36,7 +70,9 @@ properties:
- marvell,pxa168-pwm
- marvell,pxa910-pwm
- items:
- - const: spacemit,k1-pwm
+ - enum:
+ - spacemit,k1-pwm
+ - spacemit,k3-pwm
- const: marvell,pxa910-pwm
reg:
@@ -47,7 +83,18 @@ properties:
description: Number of cells in a pwm specifier.
clocks:
- maxItems: 1
+ minItems: 1
+ items:
+ - description: The function clock
+ - description: An optional bus clock
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ oneOf:
+ - items:
+ - const: func
+ - const: bus
resets:
maxItems: 1
--
2.53.0
^ permalink raw reply related
* [PATCH 0/2] pwm: spacemit: Add Support for K3 SoC
From: Yixun Lan @ 2026-04-09 0:45 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Duje Mihanović
Cc: linux-pwm, devicetree, linux-kernel, linux-riscv, spacemit,
Yixun Lan
The PWM controller in SpacemiT K3 SoC reuse the same IP as previous K1
generation, while the difference is that one additional bus clock is
added. Introduce a new compatible string and also adjust driver code to
support it.
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Yixun Lan (2):
dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K3 PWM support
pwm: pxa: Add optional bus clock
.../devicetree/bindings/pwm/marvell,pxa-pwm.yaml | 53 ++++++++++++++++++++--
drivers/pwm/pwm-pxa.c | 8 +++-
2 files changed, 57 insertions(+), 4 deletions(-)
---
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
change-id: 20260401-03-k3-pwm-drv-4ea99ae355d6
Best regards,
--
Yixun Lan <dlan@kernel.org>
^ permalink raw reply
* Re: [PATCH v6 6/6] clk: fsl-sai: Add MCLK generation support
From: Brian Masney @ 2026-04-09 0:41 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-clk, Michael Walle, Conor Dooley, Krzysztof Kozlowski,
Michael Turquette, Michael Walle, Rob Herring, Stephen Boyd,
devicetree, linux-kernel
In-Reply-To: <20260409002952.319668-6-marex@nabladev.com>
On Thu, Apr 09, 2026 at 02:29:06AM +0200, Marek Vasut wrote:
> The driver currently supports generating BCLK. There are systems which
> require generation of MCLK instead. Register new MCLK clock and handle
> clock-cells = <1> to differentiate between BCLK and MCLK. In case of a
> legacy system with clock-cells = <0>, the driver behaves as before, i.e.
> always returns BCLK.
>
> Note that it is not possible re-use the current SAI audio driver to
> generate MCLK and correctly enable and disable the MCLK.
>
> If SAI (audio driver) is used to control the MCLK enablement, then MCLK
> clock is not always enabled, and it is not necessarily enabled when the
> codec may need the clock to be enabled. There is also no way for the
> codec node to specify phandle to clock provider in DT, because the SAI
> (audio driver) is not clock provider.
>
> If SAI (clock driver) is used to control the MCLK enablement, then MCLK
> clock is enabled when the codec needs the clock enabled, because the
> codec is the clock consumer and the SAI (clock driver) is the clock
> provider, and the codec driver can request the clock to be enabled when
> needed. There is also the usual phandle to clock provider in DT, because
> the SAI (clock driver) is clock provider.
>
> Acked-by: Michael Walle <mwalle@kernel.org>
> Signed-off-by: Marek Vasut <marex@nabladev.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
^ permalink raw reply
* Re: [PATCH v6 5/6] clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()
From: Brian Masney @ 2026-04-09 0:41 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-clk, Conor Dooley, Krzysztof Kozlowski, Michael Turquette,
Michael Walle, Rob Herring, Stephen Boyd, devicetree,
linux-kernel
In-Reply-To: <20260409002952.319668-5-marex@nabladev.com>
On Thu, Apr 09, 2026 at 02:29:05AM +0200, Marek Vasut wrote:
> Create helper function fsl_sai_clk_register() to set up and register
> SAI clock. Rename BCLK specific struct fsl_sai_clk members with bclk_
> prefix. Use of_node_full_name(dev->of_node) and clock name to register
> uniquely named clock. This is done in preparation for the follow up
> patch, which adds MCLK support.
>
> Signed-off-by: Marek Vasut <marex@nabladev.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
^ permalink raw reply
* Re: [PATCH 12/19] drm/panel: jadard-jd9365da-h3: support variable DSI configuration
From: Dmitry Baryshkov @ 2026-04-09 0:35 UTC (permalink / raw)
To: Linus Walleij
Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Bartosz Golaszewski, dri-devel, devicetree, linux-kernel,
linux-gpio
In-Reply-To: <CAD++jLnAaUzHun-i7PBLzFQmsKCXXfRO+4hAgTFCZtLm_Bu6iw@mail.gmail.com>
On Wed, Apr 08, 2026 at 10:15:13AM +0200, Linus Walleij wrote:
> Hi Dmitry,
>
> thanks for your patch!
>
> On Wed, Apr 1, 2026 at 9:27 AM Dmitry Baryshkov
> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>
> > Several panels support attachment either using 4 DSI lanes or just 2. In
> > some cases, this requires a different panel mode to fulfill clock
> > requirements. Extend the driver to handle such cases by letting the
> > panel description to omit lanes specification and parsing number of
> > lanes from the DT.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> (...)
>
> > + if (dsi_ctx->dsi->lanes == 2)
> > + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x01);
> > + else
> > + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x03);
>
> If lanes 2 we do unexplicable magic A else we do unexplicable magic B?
>
> Do we know more about what is actually going on here?
>
> Can you check the datasheet?
The datasheet (you can find it) is pretty useless here. Unfortunately I
don't have a second source of information. As far as I know, this
value maps directly to the number of lanes and nothing else.
>
> The patch is nice anyway and no big deal so, so +/- that fixup:
> Reviewed-by: Linus Walleij <linusw@kernel.org>
>
> Yours,
> Linus Walleij
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 10/19] drm/panel: himax-hx8394: support Waveshare DSI panels
From: Dmitry Baryshkov @ 2026-04-09 0:33 UTC (permalink / raw)
To: Linus Walleij
Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Bartosz Golaszewski, dri-devel, devicetree, linux-kernel,
linux-gpio
In-Reply-To: <CAD++jLmG_y2dunkyzH7KDtphN6WORzt87f5CpqzAtCUtALv8CA@mail.gmail.com>
On Wed, Apr 08, 2026 at 10:10:13AM +0200, Linus Walleij wrote:
> On Wed, Apr 1, 2026 at 9:27 AM Dmitry Baryshkov
> <dmitry.baryshkov@oss.qualcomm.com> wrote:
>
> > Enable support for Waveshare 5.0" and 5.5" DSI TOUCH-A panels.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>
> This looks excellent, good documentation and references to (incomplete...)
> datasheet. Maybe this datasheet has the defs I was complaining about
> in the other patch?
No :-(
> Reviewed-by: Linus Walleij <linusw@kernel.org>
>
> Yours,
> Linus Walleij
--
With best wishes
Dmitry
^ permalink raw reply
* [PATCH v6 6/6] clk: fsl-sai: Add MCLK generation support
From: Marek Vasut @ 2026-04-09 0:29 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Michael Walle, Brian Masney, Conor Dooley,
Krzysztof Kozlowski, Michael Turquette, Michael Walle,
Rob Herring, Stephen Boyd, devicetree, linux-kernel
In-Reply-To: <20260409002952.319668-1-marex@nabladev.com>
The driver currently supports generating BCLK. There are systems which
require generation of MCLK instead. Register new MCLK clock and handle
clock-cells = <1> to differentiate between BCLK and MCLK. In case of a
legacy system with clock-cells = <0>, the driver behaves as before, i.e.
always returns BCLK.
Note that it is not possible re-use the current SAI audio driver to
generate MCLK and correctly enable and disable the MCLK.
If SAI (audio driver) is used to control the MCLK enablement, then MCLK
clock is not always enabled, and it is not necessarily enabled when the
codec may need the clock to be enabled. There is also no way for the
codec node to specify phandle to clock provider in DT, because the SAI
(audio driver) is not clock provider.
If SAI (clock driver) is used to control the MCLK enablement, then MCLK
clock is enabled when the codec needs the clock enabled, because the
codec is the clock consumer and the SAI (clock driver) is the clock
provider, and the codec driver can request the clock to be enabled when
needed. There is also the usual phandle to clock provider in DT, because
the SAI (clock driver) is clock provider.
Acked-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Marek Vasut <marex@nabladev.com>
---
Cc: Brian Masney <bmasney@redhat.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Rob Herring <robh@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
V2: No change
V3: - Rebase on current next, update mail address
- Update commit message according to clarify the difference between
SAI audio and SAI clock driver
- Pick ancient AB from Michael, although this may be outdated
https://patchwork.kernel.org/project/alsa-devel/patch/20241226162234.40141-4-marex@denx.de/
V4: Use the fsl_sai_clk_register() helper.
V5: - Move include clk.h into 3/6
- Validate clock cells in fsl_sai_of_clk_get()
V6: No change
---
drivers/clk/clk-fsl-sai.c | 34 +++++++++++++++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
index c595d340e00f1..eded6a5fac216 100644
--- a/drivers/clk/clk-fsl-sai.c
+++ b/drivers/clk/clk-fsl-sai.c
@@ -16,19 +16,27 @@
#define I2S_CSR 0x00
#define I2S_CR2 0x08
+#define I2S_MCR 0x100
#define CSR_BCE_BIT 28
+#define CSR_TE_BIT 31
#define CR2_BCD BIT(24)
#define CR2_DIV_SHIFT 0
#define CR2_DIV_WIDTH 8
+#define MCR_MOE BIT(30)
struct fsl_sai_data {
unsigned int offset; /* Register offset */
+ bool have_mclk; /* Have MCLK control */
};
struct fsl_sai_clk {
+ const struct fsl_sai_data *data;
struct clk_divider bclk_div;
+ struct clk_divider mclk_div;
struct clk_gate bclk_gate;
+ struct clk_gate mclk_gate;
struct clk_hw *bclk_hw;
+ struct clk_hw *mclk_hw;
spinlock_t lock;
};
@@ -37,7 +45,17 @@ fsl_sai_of_clk_get(struct of_phandle_args *clkspec, void *data)
{
struct fsl_sai_clk *sai_clk = data;
- return sai_clk->bclk_hw;
+ if (clkspec->args_count == 0)
+ return sai_clk->bclk_hw;
+
+ if (clkspec->args_count == 1) {
+ if (clkspec->args[0] == 0)
+ return sai_clk->bclk_hw;
+ if (sai_clk->data->have_mclk && clkspec->args[0] == 1)
+ return sai_clk->mclk_hw;
+ }
+
+ return ERR_PTR(-EINVAL);
}
static int fsl_sai_clk_register(struct device *dev, void __iomem *base,
@@ -104,6 +122,7 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
if (IS_ERR(clk_bus))
return PTR_ERR(clk_bus);
+ sai_clk->data = data;
spin_lock_init(&sai_clk->lock);
ret = fsl_sai_clk_register(dev, base, &sai_clk->lock,
@@ -113,15 +132,28 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
if (ret)
return ret;
+ if (data->have_mclk) {
+ ret = fsl_sai_clk_register(dev, base, &sai_clk->lock,
+ &sai_clk->mclk_div,
+ &sai_clk->mclk_gate,
+ &sai_clk->mclk_hw,
+ CSR_TE_BIT, MCR_MOE, I2S_MCR,
+ "MCLK");
+ if (ret)
+ return ret;
+ }
+
return devm_of_clk_add_hw_provider(dev, fsl_sai_of_clk_get, sai_clk);
}
static const struct fsl_sai_data fsl_sai_vf610_data = {
.offset = 0,
+ .have_mclk = false,
};
static const struct fsl_sai_data fsl_sai_imx8mq_data = {
.offset = 8,
+ .have_mclk = true,
};
static const struct of_device_id of_fsl_sai_clk_ids[] = {
--
2.53.0
^ permalink raw reply related
* [PATCH v6 5/6] clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()
From: Marek Vasut @ 2026-04-09 0:29 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Brian Masney, Conor Dooley, Krzysztof Kozlowski,
Michael Turquette, Michael Walle, Rob Herring, Stephen Boyd,
devicetree, linux-kernel
In-Reply-To: <20260409002952.319668-1-marex@nabladev.com>
Create helper function fsl_sai_clk_register() to set up and register
SAI clock. Rename BCLK specific struct fsl_sai_clk members with bclk_
prefix. Use of_node_full_name(dev->of_node) and clock name to register
uniquely named clock. This is done in preparation for the follow up
patch, which adds MCLK support.
Signed-off-by: Marek Vasut <marex@nabladev.com>
---
Cc: Brian Masney <bmasney@redhat.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Rob Herring <robh@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
V4: New patch
V5: - Include fsl_sai_of_clk_get() which returns only BCLK in here already
- s/hw/chw/ in fsl_sai_clk_register
V6: Move register initialization before devm_clk_hw_register_composite_pdata()
---
drivers/clk/clk-fsl-sai.c | 90 +++++++++++++++++++++++++++------------
1 file changed, 63 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
index 27925893c4c27..c595d340e00f1 100644
--- a/drivers/clk/clk-fsl-sai.c
+++ b/drivers/clk/clk-fsl-sai.c
@@ -26,20 +26,71 @@ struct fsl_sai_data {
};
struct fsl_sai_clk {
- struct clk_divider div;
- struct clk_gate gate;
+ struct clk_divider bclk_div;
+ struct clk_gate bclk_gate;
+ struct clk_hw *bclk_hw;
spinlock_t lock;
};
+static struct clk_hw *
+fsl_sai_of_clk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct fsl_sai_clk *sai_clk = data;
+
+ return sai_clk->bclk_hw;
+}
+
+static int fsl_sai_clk_register(struct device *dev, void __iomem *base,
+ spinlock_t *lock, struct clk_divider *div,
+ struct clk_gate *gate, struct clk_hw **hw,
+ const int gate_bit, const int dir_bit,
+ const int div_reg, char *name)
+{
+ const struct fsl_sai_data *data = device_get_match_data(dev);
+ struct clk_parent_data pdata = { .index = 0 };
+ struct clk_hw *chw;
+ char *cname;
+
+ gate->reg = base + data->offset + I2S_CSR;
+ gate->bit_idx = gate_bit;
+ gate->lock = lock;
+
+ div->reg = base + div_reg;
+ div->shift = CR2_DIV_SHIFT;
+ div->width = CR2_DIV_WIDTH;
+ div->lock = lock;
+
+ cname = devm_kasprintf(dev, GFP_KERNEL, "%s.%s",
+ of_node_full_name(dev->of_node), name);
+ if (!cname)
+ return -ENOMEM;
+
+ /* Set clock direction */
+ writel(dir_bit, base + div_reg);
+
+ chw = devm_clk_hw_register_composite_pdata(dev, cname,
+ &pdata, 1, NULL, NULL,
+ &div->hw,
+ &clk_divider_ops,
+ &gate->hw,
+ &clk_gate_ops,
+ CLK_SET_RATE_GATE);
+ if (IS_ERR(chw))
+ return PTR_ERR(chw);
+
+ *hw = chw;
+
+ return 0;
+}
+
static int fsl_sai_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct fsl_sai_data *data = device_get_match_data(dev);
struct fsl_sai_clk *sai_clk;
- struct clk_parent_data pdata = { .index = 0 };
struct clk *clk_bus;
void __iomem *base;
- struct clk_hw *hw;
+ int ret;
sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL);
if (!sai_clk)
@@ -55,29 +106,14 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
spin_lock_init(&sai_clk->lock);
- sai_clk->gate.reg = base + data->offset + I2S_CSR;
- sai_clk->gate.bit_idx = CSR_BCE_BIT;
- sai_clk->gate.lock = &sai_clk->lock;
-
- sai_clk->div.reg = base + data->offset + I2S_CR2;
- sai_clk->div.shift = CR2_DIV_SHIFT;
- sai_clk->div.width = CR2_DIV_WIDTH;
- sai_clk->div.lock = &sai_clk->lock;
-
- /* set clock direction, we are the BCLK master */
- writel(CR2_BCD, base + data->offset + I2S_CR2);
-
- hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name,
- &pdata, 1, NULL, NULL,
- &sai_clk->div.hw,
- &clk_divider_ops,
- &sai_clk->gate.hw,
- &clk_gate_ops,
- CLK_SET_RATE_GATE);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
-
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
+ ret = fsl_sai_clk_register(dev, base, &sai_clk->lock,
+ &sai_clk->bclk_div, &sai_clk->bclk_gate,
+ &sai_clk->bclk_hw, CSR_BCE_BIT, CR2_BCD,
+ data->offset + I2S_CR2, "BCLK");
+ if (ret)
+ return ret;
+
+ return devm_of_clk_add_hw_provider(dev, fsl_sai_of_clk_get, sai_clk);
}
static const struct fsl_sai_data fsl_sai_vf610_data = {
--
2.53.0
^ permalink raw reply related
* [PATCH v6 4/6] dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
From: Marek Vasut @ 2026-04-09 0:29 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Conor Dooley, Brian Masney, Conor Dooley,
Krzysztof Kozlowski, Michael Turquette, Michael Walle,
Rob Herring, Stephen Boyd, devicetree, linux-kernel
In-Reply-To: <20260409002952.319668-1-marex@nabladev.com>
The driver now supports generation of both BCLK and MCLK, document
support for #clock-cells = <0> for legacy case and #clock-cells = <1>
for the new case which can differentiate between BCLK and MCLK.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Marek Vasut <marex@nabladev.com>
---
Cc: Brian Masney <bmasney@redhat.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Rob Herring <robh@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
V2: Update commit message, align it with the bindings one
V3: - Rebase on current next, update mail address
- Pick ancient AB from Conor, although this may be outdated
https://patchwork.kernel.org/project/alsa-devel/patch/20241226162234.40141-3-marex@denx.de/
V4: No change
V5: No change
V6: No change
---
Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
index 90799b3b505ee..041a63fa2d2b0 100644
--- a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
@@ -10,7 +10,7 @@ maintainers:
- Michael Walle <michael@walle.cc>
description: |
- It is possible to use the BCLK pin of a SAI module as a generic
+ It is possible to use the BCLK or MCLK pin of a SAI module as a generic
clock output. Some SoC are very constrained in their pin multiplexer
configuration. E.g. pins can only be changed in groups. For example, on
the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
@@ -47,7 +47,7 @@ properties:
- const: mclk1
'#clock-cells':
- const: 0
+ maximum: 1
allOf:
- if:
--
2.53.0
^ permalink raw reply related
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