* [PATCH 0/4] arm64: dts: qcom: sdm845-lg: Devicetree followup
From: Paul Sajna @ 2026-04-09 2:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jeff Johnson, Dmitry Baryshkov, David Heidelberg
Cc: linux-arm-msm, devicetree, linux-kernel, phone-devel,
~postmarketos/upstreaming, Paul Sajna, Konrad Dybcio
Re-send 3 patches that got dropped from 20260331-judyln-dts-v7-0-87217b15fefb@postmarketos.org
(https://lore.kernel.org/linux-arm-msm/177541802142.2061229.9094394728986735362.b4-ty@kernel.org/)
Re-enable qcom,snoc-host-cap-skip-quirk
To:
Signed-off-by: Paul Sajna <sajattack@postmarketos.org>
---
Paul Sajna (4):
arm64: dts: qcom: sdm845-lg-common: Add camera flash
arm64: dts: qcom: sdm845-lg-common: Change ipa gsi-loader to 'self', add memory-region
arm64: dts: qcom: sdm845-lg-{judyln, judyp}: Reference memory region in fb
arm64: dts: qcom: sdm845-lg: Enable qcom,snoc-host-cap-skip-quirk
arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 22 +++++++++++++++++++---
arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts | 4 ++--
arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts | 4 ++--
3 files changed, 23 insertions(+), 7 deletions(-)
---
base-commit: db7efce4ae23ad5e42f5f55428f529ff62b86fab
change-id: 20260408-judyln-followup-e0201f3d27e9
prerequisite-message-id: 20260407-skip-host-cam-qmi-req-v5-0-dfa8a05c6538@ixit.cz
prerequisite-patch-id: ac24dd000a2ecf55cb4da9fbc62e4834530036fd
prerequisite-patch-id: 9c69ab29256c15a0e8ac1c3b9ef64b27661c7815
prerequisite-patch-id: bd62d277785dc0a3bed4beff8d22d7bfd7e491fb
Best regards,
--
Paul Sajna <sajattack@postmarketos.org>
^ permalink raw reply
* [PATCH 1/4] arm64: dts: qcom: sdm845-lg-common: Add camera flash
From: Paul Sajna @ 2026-04-09 2:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jeff Johnson, Dmitry Baryshkov, David Heidelberg
Cc: linux-arm-msm, devicetree, linux-kernel, phone-devel,
~postmarketos/upstreaming, Paul Sajna, Konrad Dybcio
In-Reply-To: <20260408-judyln-followup-v1-0-823467519b59@postmarketos.org>
Camera doesn't work yet (imx351), but we can use the flash as a flashlight.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Paul Sajna <sajattack@postmarketos.org>
---
arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
index 71d070619ad7..9d82961d527e 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
@@ -496,6 +496,19 @@ &pm8998_resin {
status = "okay";
};
+&pmi8998_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <1>, <2>;
+ led-max-microamp = <100000>;
+ flash-max-microamp = <500000>;
+ flash-max-timeout-us = <500000>;
+ };
+};
+
&pmi8998_lpg {
status = "okay";
--
2.53.0
^ permalink raw reply related
* [PATCH 2/4] arm64: dts: qcom: sdm845-lg-common: Change ipa gsi-loader to 'self', add memory-region
From: Paul Sajna @ 2026-04-09 2:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jeff Johnson, Dmitry Baryshkov, David Heidelberg
Cc: linux-arm-msm, devicetree, linux-kernel, phone-devel,
~postmarketos/upstreaming, Paul Sajna, Konrad Dybcio
In-Reply-To: <20260408-judyln-followup-v1-0-823467519b59@postmarketos.org>
The modem firmware for this device doesn't preload the IPA firmware
and requires the OS handles that instead. Set qcom,gsi-loader = "self"
to reflect that.
Ensure the ipa uses the correct memory.
ipa 1e40000.ipa: channel 4 limited to 256 TREs
ipa 1e40000.ipa: IPA driver initialized
ipa 1e40000.ipa: received modem starting event
ipa 1e40000.ipa: received modem running event
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Paul Sajna <sajattack@postmarketos.org>
---
arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
index 9d82961d527e..85dc4468b6c4 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
@@ -473,7 +473,9 @@ &gpu {
};
&ipa {
- qcom,gsi-loader = "modem";
+ qcom,gsi-loader = "self";
+ memory-region = <&ipa_fw_mem>;
+
status = "okay";
};
--
2.53.0
^ permalink raw reply related
* [PATCH 3/4] arm64: dts: qcom: sdm845-lg-{judyln, judyp}: Reference memory region in fb
From: Paul Sajna @ 2026-04-09 2:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jeff Johnson, Dmitry Baryshkov, David Heidelberg
Cc: linux-arm-msm, devicetree, linux-kernel, phone-devel,
~postmarketos/upstreaming, Paul Sajna, Konrad Dybcio
In-Reply-To: <20260408-judyln-followup-v1-0-823467519b59@postmarketos.org>
To prevent duplicating the framebuffer address and size point out the
existing framebuffer memory region instead of specifying the address
manually.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Paul Sajna <sajattack@postmarketos.org>
---
arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 3 +--
arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts | 4 ++--
arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts | 4 ++--
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
index 85dc4468b6c4..86cf4eb44084 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
@@ -98,8 +98,7 @@ spss_mem: memory@99000000 {
no-map;
};
- /* Framebuffer region */
- memory@9d400000 {
+ framebuffer_mem: memory@9d400000 {
reg = <0x0 0x9d400000 0x0 0x2400000>;
no-map;
};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts
index adf41aa0146a..349faa123ff1 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts
@@ -14,9 +14,9 @@ / {
compatible = "lg,judyln", "qcom,sdm845";
chosen {
- framebuffer@9d400000 {
+ framebuffer {
compatible = "simple-framebuffer";
- reg = <0x0 0x9d400000 0x0 (1440 * 3120 * 4)>;
+ memory-region = <&framebuffer_mem>;
width = <1440>;
height = <3120>;
stride = <(1440 * 4)>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts
index d244ebdd17be..44e762f78e95 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts
@@ -14,9 +14,9 @@ / {
compatible = "lg,judyp", "qcom,sdm845";
chosen {
- framebuffer@9d400000 {
+ framebuffer {
compatible = "simple-framebuffer";
- reg = <0x0 0x9d400000 0x0 (1440 * 2880 * 4)>;
+ memory-region = <&framebuffer_mem>;
width = <1440>;
height = <2880>;
stride = <(1440 * 4)>;
--
2.53.0
^ permalink raw reply related
* [PATCH 4/4] arm64: dts: qcom: sdm845-lg: Enable qcom,snoc-host-cap-skip-quirk
From: Paul Sajna @ 2026-04-09 2:41 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jeff Johnson, Dmitry Baryshkov, David Heidelberg
Cc: linux-arm-msm, devicetree, linux-kernel, phone-devel,
~postmarketos/upstreaming, Paul Sajna
In-Reply-To: <20260408-judyln-followup-v1-0-823467519b59@postmarketos.org>
The WCN3990 firmware for judyln does not respond to the request for
host capabilities. Add the devicetree quirk to skip this request.
Signed-off-by: Paul Sajna <sajattack@postmarketos.org>
---
arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
index 86cf4eb44084..e0c3566761bf 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi
@@ -694,5 +694,7 @@ &wifi {
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
+ qcom,snoc-host-cap-skip-quirk;
+
status = "okay";
};
--
2.53.0
^ permalink raw reply related
* 回复: [net-next v1 v1 3/5] dt-bindings: net: starfive,jh7110-dwmac: Add JHB100 sgmii rx clk
From: Minda Chen @ 2026-04-09 2:46 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin,
Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
devicetree@vger.kernel.org
In-Reply-To: <c69cf692-87be-43b5-93ee-38040d5cb1bf@lunn.ch>
>
> > + - description: SGMII RX clock
> >
> > clock-names:
> > - items:
> > - - const: stmmaceth
> > - - const: pclk
> > - - const: ptp_ref
> > - - const: tx
> > - - const: gtx
> > + minItems: 5
> > + maxItems: 6
> > + contains:
> > + enum:
> > + - stmmaceth
> > + - pclk
> > + - ptp_ref
> > + - tx
> > + - gtx
> > + - rx
>
> If this is only used for sgmii, maybe it should have sgmii in the name?
>
> Andrew
Okay. I will change to "sgmii_rx". Thanks
^ permalink raw reply
* Re: [net-next v1 v1 4/5] net: stmmac: starfive: Add JHB100 SGMII interface
From: Minda Chen @ 2026-04-09 2:55 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin,
Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
devicetree@vger.kernel.org
In-Reply-To: <49407bd8-f20b-46f7-9b98-8c88fc45e0f0@lunn.ch>
>
> > + dwmac->sgmii_rx = devm_clk_get_optional(&pdev->dev, "rx");
> > + if (IS_ERR(dwmac->sgmii_rx))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->sgmii_rx),
> > + "error getting sgmii rx clock\n");
> > +
>
> The SGMII clock is optional...
>
Yes. RGMII do not have this clock.
> > /* Generally, the rgmii_tx clock is provided by the internal clock,
> > * which needs to match the corresponding clock frequency according
> > * to different speeds. If the rgmii_tx clock is provided by the
> > * external rgmii_rxin, there is no need to configure the clock
> > * internally, because rgmii_rxin will be adaptively adjusted.
> > */
> > - if (!device_property_read_bool(&pdev->dev, "starfive,tx-use-rgmii-clk"))
> > - plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate;
> > + if (!device_property_read_bool(&pdev->dev, "starfive,tx-use-rgmii-clk")) {
> > + if (plat_dat->phy_interface == PHY_INTERFACE_MODE_SGMII)
> > + plat_dat->set_clk_tx_rate =
> stmmac_starfive_sgmii_set_clk_rate;
>
> So you probably want to return an error here if it is missing.
>
No. RGMII still using stmmac_set_clk_tx_rate
> Or you might want to look at the compatible, and make the clock mandatory for
> this device.
>
> Andrew
Okay I will check the rx clock whether exist .
^ permalink raw reply
* RE: [PATCH V11 02/12] PCI: host-generic: Add common helpers for parsing Root Port properties
From: Sherry Sun @ 2026-04-09 2:58 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
Frank Li, s.hauer@pengutronix.de, kernel@pengutronix.de,
festevam@gmail.com, lpieralisi@kernel.org, kwilczynski@kernel.org,
bhelgaas@google.com, Hongxing Zhu, l.stach@pengutronix.de,
imx@lists.linux.dev, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <yijf6mwclpx6n7giucgykxvrm73baicy2urhzns34sxgloli3z@ygose2qrgvuz>
> On Wed, Apr 08, 2026 at 06:34:02AM +0000, Sherry Sun wrote:
>
> [...]
>
> > > > +/**
> > > > + * pci_host_common_parse_port - Parse a single Root Port node
> > > > + * @dev: Device pointer
> > > > + * @bridge: PCI host bridge
> > > > + * @node: Device tree node of the Root Port
> > > > + *
> > > > + * Returns: 0 on success, negative error code on failure */
> > > > +static int pci_host_common_parse_port(struct device *dev,
> > > > + struct pci_host_bridge *bridge,
> > > > + struct device_node *node) {
> > > > + struct pci_host_port *port;
> > > > + struct gpio_desc *reset;
> > > > +
> > > > + reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
> > > > + "reset", GPIOD_ASIS, "PERST#");
> > >
> > > Sorry, I missed this earlier.
> > >
> > > Since PERST# is optional, you cannot reliably detect whether the
> > > Root Port binding intentionally skipped the PERST# GPIO or legacy
> > > binding is used, just by checking for PERST# in Root Port node.
> > >
> > > So this helper should do 3 things:
> > >
> > > 1. If PERST# is found in Root Port node, use it.
> > > 2. If not, check the RC node and if present, return -ENOENT to
> > > fallback to the legacy binding.
> > > 3. If not found in both nodes, assume that the PERST# is not present
> > > in the design, and proceed with parsing Root Port binding further.
> >
> > Hi Mani, understand, does the following code looks ok for above three
> cases?
> >
> > /* Check if PERST# is present in Root Port node */
> > reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
> > "reset", GPIOD_ASIS, "PERST#");
> > if (IS_ERR(reset)) {
> > /* If error is not -ENOENT, it's a real error */
> > if (PTR_ERR(reset) != -ENOENT)
> > return PTR_ERR(reset);
> >
> > /* PERST# not found in Root Port node, check RC node */
> > rc_has_reset = of_property_read_bool(dev->of_node, "reset-gpios") ||
> > of_property_read_bool(dev->of_node, "reset-gpio");
>
> Just:
> if (of_property_read_bool(dev->of_node, "reset-gpios") ||
> of_property_read_bool(dev->of_node, "reset-gpio")) {
> return -ENOENT;
> }
Ok, will do.
>
> > if (rc_has_reset)
> > return -ENOENT;
> >
> > /* No PERST# in either node, assume not present in design */
> > reset = NULL;
> > }
> >
> > port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> > if (!port)
> > return -ENOMEM;
> > ...
> >
> > >
> > > But there is one more important limitation here. Right now, this API
> > > only handles PERST#. But if another vendor tries to use it and if
> > > they need other properties such as PHY, clocks etc... those
> > > resources should be fetched optionally only by this helper. But if
> > > the controller has a hard dependency on those resources, the driver will
> fail to operate.
> > >
> > > I don't think we can fix this limitation though and those platforms
> > > should ensure that the resource dependency is correctly modeled in
> > > DT binding and the DTS is validated properly. It'd be good to
> > > mention this in the kernel doc of this API.
> >
> > Ok, I will add a NOTE for this in this API description.
> >
> > >
> > > > + if (IS_ERR(reset))
> > > > + return PTR_ERR(reset);
> > > > +
> > > > + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> > > > + if (!port)
> > > > + return -ENOMEM;
> > > > +
> > > > + port->reset = reset;
> > > > + INIT_LIST_HEAD(&port->list);
> > > > + list_add_tail(&port->list, &bridge->ports);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +/**
> > > > + * pci_host_common_parse_ports - Parse Root Port nodes from
> > > > +device tree
> > > > + * @dev: Device pointer
> > > > + * @bridge: PCI host bridge
> > > > + *
> > > > + * This function iterates through child nodes of the host bridge
> > > > +and parses
> > > > + * Root Port properties (currently only reset GPIO).
> > > > + *
> > > > + * Returns: 0 on success, -ENOENT if no ports found, other
> > > > +negative error codes
> > > > + * on failure
> > > > + */
> > > > +int pci_host_common_parse_ports(struct device *dev, struct
> > > > +pci_host_bridge *bridge) {
> > > > + int ret = -ENOENT;
> > > > +
> > > > + for_each_available_child_of_node_scoped(dev->of_node, of_port) {
> > > > + if (!of_node_is_type(of_port, "pci"))
> > > > + continue;
> > > > + ret = pci_host_common_parse_port(dev, bridge, of_port);
> > > > + if (ret)
> > > > + return ret;
> > >
> > > As Sashiko flagged, you need to make sure that
> > > devm_add_action_or_reset() is added even during the error path:
> >
> > Yes, it needs to be fixed. We can handle it with the following two methods, I
> am not sure which method is better or more preferable?
> >
> > #1: register cleanup action after first successful port parse and use
> cleanup_registered flag to avoid duplicate register.
> > int ret = -ENOENT;
> > bool cleanup_registered = false;
> >
> > for_each_available_child_of_node_scoped(dev->of_node, of_port) {
> > if (!of_node_is_type(of_port, "pci"))
> > continue;
> > ret = pci_host_common_parse_port(dev, bridge, of_port);
> > if (ret)
> > return ret;
> >
> > /* Register cleanup action after first successful port parse */
> > if (!cleanup_registered) {
> > ret = devm_add_action_or_reset(dev,
> > pci_host_common_delete_ports,
> > &bridge->ports);
>
> Even if you register devm_add_action_or_reset(), it won't be called when
> pci_host_common_parse_port() fails since the legacy fallback will be used.
>
> So you need to manually call pci_host_common_delete_ports() in the error
> path.
Get your point, so seems I should just add the err_cleanup handle path like this, right?
for_each_available_child_of_node_scoped(dev->of_node, of_port) {
if (!of_node_is_type(of_port, "pci"))
continue;
ret = pci_host_common_parse_port(dev, bridge, of_port);
if (ret)
goto err_cleanup;
}
if (ret)
return ret;
return devm_add_action_or_reset(dev, pci_host_common_delete_ports,
&bridge->ports);
err_cleanup:
pci_host_common_delete_ports(&bridge->ports);
return ret;
Best Regards
Sherry
^ permalink raw reply
* Re: [net-next v1 v1 1/5] dt-bindings: net: starfive,jh7110-dwmac: Remove JH8100
From: Minda Chen @ 2026-04-09 2:44 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin,
Emil Renner Berthing, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
devicetree@vger.kernel.org
In-Reply-To: <ad9ee916-6f8a-4cb9-8016-54a02b00c7ab@lunn.ch>
>
> On Wed, Apr 08, 2026 at 04:44:12PM +0800, Minda Chen wrote:
> > Remove JH8100 dt-bindings because do not support it now.
>
> Could you expand on that. If there are devices out in the field, we don't just drop
> support for it because the vendor has something newer.
>
> If the device never made it outside of the vendors lab, then we might consider
> dropping it.
>
> Please explain in detail why this is being dropped.
>
> Andrew
Yes.
We (StarFive) stop developing on JH8100 now, And do NOT release the SoC outside.
Hi Krzysztof
Could you review this series patch 1 -3 which is dt -binding doc changes? I sorry
I have sent you to old e-mail address.
^ permalink raw reply
* [PATCH v5 0/2] arm64: dts: qcom: QCS615 Talos EVK audio support
From: Le Qi @ 2026-04-09 3:01 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, kernel, Le Qi
This series adds initial audio support for the QCS615-based Talos EVK
platform. It introduces the GPR (Generic Pack Router) node in the SoC
device tree and enables a sound card node with the DA7212 codec on the
Talos EVK board.
With these changes, playback through headphones and capture from the
headset microphone have been tested and verified to work.
---
Changelog:
v5:
- Moved mclk support to codec since Krystof does not agree to include
it within the DAI node. Link: https://lore.kernel.org/all/5941830f-5892-4e75-bc27-04095b5ca28f@kernel.org/
- v4-link: https://lore.kernel.org/all/20260324060405.3098891-1-le.qi@oss.qualcomm.com/
v4:
- Added mclk support for recording to fix clipping issue.
- v3-link: https://lore.kernel.org/all/20251204083225.1190017-1-le.qi@oss.qualcomm.com/
v3:
- Updated sound card model name to "TALOS-EVK".
- v2-link: https://lore.kernel.org/all/20251125033311.254869-1-le.qi@oss.qualcomm.com/
v2:
- Address Konrad's comment to modify the commit message and
group GPIO pins together into a single entry, moved to the
SoC-level DTSI for reuse.
- v1-link: https://lore.kernel.org/all/20251024023720.3928547-1-le.qi@oss.qualcomm.com/
Le Qi (2):
arm64: dts: qcom: talos: Add GPR node, audio services, and MI2S1 TLMM
pins
arm64: dts: qcom: talos-evk: Add sound card support with DA7212 codec
arch/arm64/boot/dts/qcom/talos-evk.dts | 56 ++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/talos.dtsi | 54 +++++++++++++++++++++++++
2 files changed, 110 insertions(+)
base-commit: db7efce4ae23ad5e42f5f55428f529ff62b86fab
--
2.34.1
^ permalink raw reply
* [PATCH v5 2/2] arm64: dts: qcom: talos-evk: Add sound card support with DA7212 codec
From: Le Qi @ 2026-04-09 3:01 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, kernel, Le Qi,
Dmitry Baryshkov, Konrad Dybcio
In-Reply-To: <20260409030156.155455-1-le.qi@oss.qualcomm.com>
Add the sound card node for QCS615 Talos EVK with DA7212 codec
connected over the Primary MI2S interface. The configuration enables
headphone playback and headset microphone capture, both of which have
been tested to work.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Le Qi <le.qi@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/talos-evk.dts | 56 ++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/talos-evk.dts b/arch/arm64/boot/dts/qcom/talos-evk.dts
index af100e22beee..b7f514fbc7b2 100644
--- a/arch/arm64/boot/dts/qcom/talos-evk.dts
+++ b/arch/arm64/boot/dts/qcom/talos-evk.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "talos-evk-som.dtsi"
+#include <dt-bindings/sound/qcom,q6afe.h>
/ {
model = "Qualcomm QCS615 IQ 615 EVK";
@@ -40,6 +41,46 @@ hdmi_con_out: endpoint {
};
};
+ sound {
+ compatible = "qcom,qcs615-sndcard";
+ model = "TALOS-EVK";
+
+ pinctrl-0 = <&mi2s1_pins>, <&mi2s_mclk>;
+ pinctrl-names = "default";
+
+ pri-mi2s-capture-dai-link {
+ link-name = "Primary MI2S Capture";
+
+ codec {
+ sound-dai = <&codec_da7212>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai PRIMARY_MI2S_TX>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ pri-mi2s-playback-dai-link {
+ link-name = "Primary MI2S Playback";
+
+ codec {
+ sound-dai = <&codec_da7212>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
vreg_v1p8_out: regulator-v1p8-out {
compatible = "regulator-fixed";
regulator-name = "vreg-v1p8-out";
@@ -109,6 +150,21 @@ adv7535_out: endpoint {
};
};
+&i2c5 {
+ status = "okay";
+
+ codec_da7212: codec@1a {
+ compatible = "dlg,da7212";
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+ clocks = <&q6prmcc LPASS_CLK_ID_MCLK_2 LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "mclk";
+ VDDA-supply = <&vreg_v1p8_out>;
+ VDDIO-supply = <&vreg_v1p8_out>;
+ VDDMIC-supply = <&vreg_v3p3_out>;
+ };
+};
+
&mdss_dsi0_out {
remote-endpoint = <&adv7535_in>;
data-lanes = <0 1 2 3>;
--
2.34.1
^ permalink raw reply related
* [PATCH v5 1/2] arm64: dts: qcom: talos: Add GPR node, audio services, and MI2S1 TLMM pins
From: Le Qi @ 2026-04-09 3:01 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, kernel, Le Qi,
Konrad Dybcio
In-Reply-To: <20260409030156.155455-1-le.qi@oss.qualcomm.com>
This patch adds the Generic Pack Router (GPR) node together with
Audio Process Manager (APM) and Proxy Resource Manager (PRM)
audio service nodes to the Talos device tree description.
It also introduces MI2S1 pinctrl states for data0, data1, sck,
and ws lines, grouped into a single entry at the SoC-level DTSI
for better reuse and clarity.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Le Qi <le.qi@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/talos.dtsi | 54 +++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index ff5afbfce2a4..64121316ffc5 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -18,6 +18,7 @@
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
@@ -1610,6 +1611,20 @@ cci_i2c1_default: cci-i2c1-default-state {
bias-pull-up;
};
+ mi2s1_pins: mi2s1-state {
+ pins = "gpio108", "gpio109", "gpio110", "gpio111";
+ function = "mi2s_1";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ mi2s_mclk: mi2s-mclk-state {
+ pins = "gpio122";
+ function = "mclk2";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
qup_i2c1_data_clk: qup-i2c1-data-clk-state {
pins = "gpio4", "gpio5";
function = "qup0";
@@ -5132,6 +5147,45 @@ compute-cb@6 {
dma-coherent;
};
};
+
+ gpr: gpr {
+ compatible = "qcom,gpr";
+ qcom,glink-channels = "adsp_apps";
+ qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+ qcom,intents = <512 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ q6apm: service@1 {
+ compatible = "qcom,q6apm";
+ reg = <GPR_APM_MODULE_IID>;
+ #sound-dai-cells = <0>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6apmbedai: bedais {
+ compatible = "qcom,q6apm-lpass-dais";
+ #sound-dai-cells = <1>;
+ };
+
+ q6apmdai: dais {
+ compatible = "qcom,q6apm-dais";
+ iommus = <&apps_smmu 0x1721 0x0>;
+ };
+ };
+
+ q6prm: service@2 {
+ compatible = "qcom,q6prm";
+ reg = <GPR_PRM_MODULE_IID>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6prmcc: clock-controller {
+ compatible = "qcom,q6prm-lpass-clocks";
+ #clock-cells = <2>;
+ };
+ };
+ };
};
};
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v1 1/3] dt-bindings: arm: fsl: add Variscite VAR-SOM-MX91 Boards
From: Peng Fan @ 2026-04-09 3:05 UTC (permalink / raw)
To: Stefano Radaelli
Cc: linux-kernel, devicetree, imx, linux-arm-kernel, pierluigi.p,
Stefano Radaelli, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Shawn Guo, Dario Binacchi, Markus Niebel, Maud Spierings,
Alexander Stein, Ernest Van Hoecke, Josua Mayer,
Francesco Dolcini, Primoz Fiser
In-Reply-To: <86635091cd5db0ecb7f07c5ad9d6f735ec349485.1775669847.git.stefano.r@variscite.com>
On Wed, Apr 08, 2026 at 07:39:44PM +0200, Stefano Radaelli wrote:
>From: Stefano Radaelli <stefano.r@variscite.com>
>
>Add DT compatible strings for Variscite VAR-SOM-MX91 SoM and Symphony
>development carrier Board.
>
>Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply
* RE: [PATCH 2/2] PCI: amd-mdb: Add amd,versal2-cpm6-host compatible
From: Musham, Sai Krishna @ 2026-04-09 3:09 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
cassel@kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Simek, Michal, Gogada, Bharat Kumar, Havalige, Thippeswamy
In-Reply-To: <iruxyxjoaozkt5xigchqnqvik5blbxxy7vubmadtcn5jyjnwzn@lvdnttblbx3f>
[Public]
Hi Krzysztof/Manivannan,
> -----Original Message-----
> From: Manivannan Sadhasivam <mani@kernel.org>
> Sent: Saturday, April 4, 2026 8:46 AM
> To: Musham, Sai Krishna <sai.krishna.musham@amd.com>
> Cc: bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com;
> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> cassel@kernel.org; linux-pci@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; Simek, Michal <michal.simek@amd.com>;
> Gogada, Bharat Kumar <bharat.kumar.gogada@amd.com>; Havalige,
> Thippeswamy <thippeswamy.havalige@amd.com>
> Subject: Re: [PATCH 2/2] PCI: amd-mdb: Add amd,versal2-cpm6-host
> compatible
>
> On Thu, Apr 02, 2026 at 11:30:06PM +0530, Sai Krishna Musham wrote:
> > Add "amd,versal2-cpm6-host" to the OF match table of the AMD MDB PCIe
> > host controller driver.
> >
> > The Versal2 CPM6 host controller is DesignWare-based and supports
> > PCIe Gen6 operation at up to 64 GT/s per lane. It is currently
> > handled by the same driver and match data (NULL) as the existing
> > MDB host controller, but CPM6 uses a newer IP revision and differs
> > in legacy INTx register offsets.
> >
> > Use a separate compatible to allow CPM6-specific handling once legacy
> > interrupt support is validated.
> >
> > Signed-off-by: Sai Krishna Musham <sai.krishna.musham@amd.com>
> > ---
> > drivers/pci/controller/dwc/pcie-amd-mdb.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-amd-mdb.c
> b/drivers/pci/controller/dwc/pcie-amd-mdb.c
> > index 3c6e837465bb..325bf7aad657 100644
> > --- a/drivers/pci/controller/dwc/pcie-amd-mdb.c
> > +++ b/drivers/pci/controller/dwc/pcie-amd-mdb.c
> > @@ -511,6 +511,9 @@ static const struct of_device_id
> amd_mdb_pcie_of_match[] = {
> > {
> > .compatible = "amd,versal2-mdb-host",
> > },
> > + {
> > + .compatible = "amd,versal2-cpm6-host",
>
> As Krzysztof commented, if the PCIe IP is compatible with an older version,
> 'amd,versal2-mdb-host' in this case, you don't need to add the new
> compatible
> to the driver. Just document the new one with fallback to the old compatible
> in
> the binding and let the driver work with the old compatible.
>
Thanks for the review. CPM6 uses a different DesignWare IP revision and
has differences in legacy interrupt register offsets. I will send a follow-up
patch to address these.
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
Regards,
Sai Krishna
^ permalink raw reply
* Re: [PATCH v1 2/3] arm64: dts: freescale: Add support for Variscite VAR-SOM-MX91
From: Frank Li @ 2026-04-09 3:30 UTC (permalink / raw)
To: Stefano Radaelli
Cc: linux-kernel, devicetree, imx, linux-arm-kernel, pierluigi.p,
Stefano Radaelli, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Shawn Guo,
Dario Binacchi, Markus Niebel, Maud Spierings, Alexander Stein,
Ernest Van Hoecke, Josua Mayer, Francesco Dolcini, Primoz Fiser
In-Reply-To: <1ed7e2100e3feb74c9f0006d5b88e1bba1ad4339.1775669847.git.stefano.r@variscite.com>
On Wed, Apr 08, 2026 at 07:39:45PM +0200, Stefano Radaelli wrote:
> From: Stefano Radaelli <stefano.r@variscite.com>
>
> Add device tree support for the Variscite VAR-SOM-MX91 system on module.
> This SOM is designed to be used with various carrier boards.
>
> The module includes:
> - NXP i.MX91 MPU processor
> - Up to 2GB of LPDDR4 memory
> - Up to 128GB of eMMC storage memory
> - Integrated 10/100/1000 Mbps Ethernet Transceiver
> - Codec audio WM8904
> - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth
>
> Only SOM-specific peripherals are enabled by default. Carrier board
> specific interfaces are left disabled to be enabled in the respective
> carrier board device trees.
>
> Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/var-som-mx91/
> Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
> ---
> .../boot/dts/freescale/imx91-var-som.dtsi | 456 ++++++++++++++++++
what' difference with imx93-var-som ? Can you reuse it?
Frank
>
^ permalink raw reply
* Re: [PATCH 02/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller
From: Xilin Wu @ 2026-04-09 3:38 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Dmitry Baryshkov,
Liam Girdwood, Mark Brown, Judy Hsiao
Cc: linux-arm-msm, linux-kernel, devicetree, linux-sound
In-Reply-To: <bb21b9b3-7432-401a-a0d0-1b1970f27770@oss.qualcomm.com>
On 4/8/2026 4:59 PM, Konrad Dybcio wrote:
> On 4/7/26 5:19 PM, Xilin Wu wrote:
>> Add and enable UFS related nodes for this board.
>>
>> Note that UFS Gear-4 Rate-B is unstable due to board and UFS module design
>> limitations. UFS on this board is stable when working at Gear-4 Rate-A.
>>
>> Signed-off-by: Xilin Wu <sophon@radxa.com>
>> ---
>> .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 23 ++++++++++++++++++++++
>> 1 file changed, 23 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
>> index bb5a42b038f1..c961d3ec625f 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
>> +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
>> @@ -959,6 +959,29 @@ &uart5 {
>> status = "okay";
>> };
>>
>> +&ufs_mem_hc {
>> + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
>> + vcc-supply = <&vreg_l7b_2p96>;
>> + vcc-max-microamp = <800000>;
>> + vccq-supply = <&vreg_l9b_1p2>;
>> + vccq-max-microamp = <900000>;
>> + vccq2-supply = <&vreg_l9b_1p2>;
>> + vccq2-max-microamp = <1300000>;
>> +
>> + /* Gear-4 Rate-B is unstable due to board */
>> + /* and UFS module design limitations */
>
> /* it's a bit weird to add two single-line */
> /* comments near one another for a single paragraph */
Ack. I'll change the comment to single-line in v2.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> Konrad
>
--
Best regards,
Xilin Wu <sophon@radxa.com>
^ permalink raw reply
* Re: [PATCH v10 0/3] riscv: dts: spacemit: Add PMIC regulators usb pcie
From: Yixun Lan @ 2026-04-09 3:39 UTC (permalink / raw)
To: Han Gao
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chukun Pan,
devicetree, linux-riscv, spacemit, linux-kernel, Han Gao
In-Reply-To: <cover.1775575436.git.gaohan@iscas.ac.cn>
Hi Han,
On 23:28 Tue 07 Apr , Han Gao wrote:
> Changes in v10:
> - patch 3:
> add vin-supply in pcie_vcc3v3
> reorder vcc5v0_usb30
> remove vpcie3v3-supply form pcie1
> - Link to v9: https://lore.kernel.org/linux-riscv/cover.1775417019.git.gaohan@iscas.ac.cn
You should keep all ChangeLog versions, which easy for people to review
backwards, but this isn't a big problem..
>
> Han Gao (3):
> riscv: dts: spacemit: Enable i2c8 adapter for OrangePi RV2
> riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2
> riscv: dts: spacemit: Enable USB3.0/PCIe on OrangePi RV2
>
> .../boot/dts/spacemit/k1-orangepi-rv2.dts | 217 ++++++++++++++++++
> 1 file changed, 217 insertions(+)
>
>
> base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
> prerequisite-patch-id: ef6e9c7b5854d0c08066b72f9a7868db8c2140eb
> prerequisite-patch-id: cfe3800f8c791ec4c63e070af9628e88e0fc31b9
> prerequisite-patch-id: b76493e625ae257c8adcd67874178458420e4d47
> prerequisite-patch-id: 88e01dc92c83bd88ddeb78891d3088209fed8d6b
> prerequisite-patch-id: 60336d10ab8322c70596d0f046b6b5c54bb24b54
> prerequisite-patch-id: 68c4d869548687dc115dd91e2ffb8f4c11482d86
> prerequisite-patch-id: fdadcf964c2cb3406160edb579d99a8d5695f8e6
> prerequisite-patch-id: 73b9e745338b0499b849fa4f7f9508987ab39a59
> prerequisite-patch-id: cd26770c2160c3c31a406bd8a6b01ab666180ae0
> prerequisite-patch-id: e5dfddc32cefae195692da8b80e19adf086e4ad7
> prerequisite-patch-id: 7fd53cbe4977598f26148a4bb1cf692bbdb79a09
> prerequisite-patch-id: 96ebac57bb29619b97fe95422206a685825618e9
> prerequisite-patch-id: 00fac16b52f60383db3140e2885f3f7f8d14dd1a
> prerequisite-patch-id: 3b7a60047b922c48e93599f621cb738856f42354
> prerequisite-patch-id: 275c030b963be05dd1041451f539a130ce614277
> prerequisite-patch-id: 93963424b0871e64276af0e0b2199b52e29b4603
> prerequisite-patch-id: 8383188b1c01ed6280629faaa29c37d699ade241
> prerequisite-patch-id: 5f8126b912b924d63d4a1e0c5eb42d212eb0d369
> prerequisite-patch-id: e80af628a2e0b5f2eeb3cb1b5e7133d08bdd2c4e
> prerequisite-patch-id: 0234a6dca15eb91f98a45a46604ce5b4935048a5
I beliew all dependencies are queued already, and those "prerequisite-patch-id"
are rather hard for people to review (I know it's b4 do this conversion),
I would prefer listing them directly in the cover letter
Anyway, I'm ok with this version, so here
Reviewed-by: Yixun Lan <dlan@kernel.org>
--
Yixun Lan (dlan)
^ permalink raw reply
* [PATCH] of: unittest: fix use-after-free in testdrv_probe()
From: Wentao Liang @ 2026-04-09 3:48 UTC (permalink / raw)
To: robh, saravanak; +Cc: devicetree, linux-kernel, Wentao Liang, stable
The function testdrv_probe() retrieves the device_node from the PCI
device, applies an overlay, and then immediately calls of_node_put(dn).
This releases the reference held by the PCI core, potentially freeing
the node if the reference count drops to zero. Later, the same freed
pointer 'dn' is passed to of_platform_default_populate(), leading to a
use-after-free.
The reference to pdev->dev.of_node is owned by the device model and
should not be released by the driver. Remove the erroneous of_node_put()
to prevent premature freeing.
Fixes: 26409dd04589 ("of: unittest: Add pci_dt_testdrv pci driver")
Cc: stable@vger.kernel.org
Signed-off-by: Wentao Liang <vulab@iscas.ac.cn>
---
drivers/of/unittest.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
index eae7ebdf5130..4078569a0f96 100644
--- a/drivers/of/unittest.c
+++ b/drivers/of/unittest.c
@@ -4317,7 +4317,6 @@ static int testdrv_probe(struct pci_dev *pdev, const struct pci_device_id *id)
size = info->dtbo_end - info->dtbo_begin;
ret = of_overlay_fdt_apply(info->dtbo_begin, size, &ovcs_id, dn);
- of_node_put(dn);
if (ret)
return ret;
--
2.34.1
^ permalink raw reply related
* Re: [PATCH 2/2] arm64: dts: qcom: eliza: Add QCE crypto
From: Kuldeep Singh @ 2026-04-09 4:08 UTC (permalink / raw)
To: Krzysztof Kozlowski, Thara Gopinath, Herbert Xu, David S. Miller,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, linux-crypto, devicetree, linux-kernel
In-Reply-To: <20260407-crypto-qcom-eliza-v1-2-40f61a1454a2@oss.qualcomm.com>
On 4/7/2026 7:21 PM, Krzysztof Kozlowski wrote:
> Add nodes for the BAM DAM and QCE crypto engine.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
--
Regards
Kuldeep
^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: qcom: milos: Add QCrypto nodes
From: Kuldeep Singh @ 2026-04-09 4:15 UTC (permalink / raw)
To: Alexander Koskovich, Thara Gopinath, Herbert Xu, David S. Miller,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: linux-crypto, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260405-milos-qce-v1-2-6996fb0b8a9c@pm.me>
On 4/6/2026 7:40 AM, Alexander Koskovich wrote:
> Add the QCE and Crypto BAM DMA nodes.
>
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
--
Regards
Kuldeep
^ permalink raw reply
* Re: [PATCH 0/3] Add support for the Iris codec on Milos
From: Vishnu Reddy @ 2026-04-09 4:34 UTC (permalink / raw)
To: Alexander Koskovich, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Bryan O'Donoghue, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: Luca Weiss, linux-media, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260406-milos-iris-v1-0-17ed0167ba6f@pm.me>
On 4/6/2026 3:49 PM, Alexander Koskovich wrote:
> This series adds the bindings, nodes and platform data for the Milos platform
> for the Iris video codec, allowing Milos to use hardware‑accelerated video
> encoding and decoding.
>
> Ran v4l2-compliance and some fluster tests, though a concerning amount of them
> failed. Attaching v4l2-compliance output and the full fluster results below.
>
> ~ # v4l2-compliance -d /dev/video0
> v4l2-compliance 1.32.0, 64 bits, 64-bit time_t
>
> Compliance test for iris_driver device /dev/video0:
>
> Driver Info:
> Driver name : iris_driver
> Card type : Iris Decoder
> Bus info : platform:aa00000.video-codec
> Driver version : 7.0.0
> Capabilities : 0x84204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Device Capabilities
> Device Caps : 0x04204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Detected Stateful Decoder
>
> Required ioctls:
> test VIDIOC_QUERYCAP: OK
> test invalid ioctls: OK
>
> Allow for multiple opens:
> test second /dev/video0 open: OK
> test VIDIOC_QUERYCAP: OK
> test VIDIOC_G/S_PRIORITY: OK
> test for unlimited opens: OK
>
> Debug ioctls:
> test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> test VIDIOC_LOG_STATUS: OK (Not Supported)
>
> Input ioctls:
> test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> test VIDIOC_ENUMAUDIO: OK (Not Supported)
> test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDIO: OK (Not Supported)
> Inputs: 0 Audio Inputs: 0 Tuners: 0
>
> Output ioctls:
> test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> Outputs: 0 Audio Outputs: 0 Modulators: 0
>
> Input/Output configuration ioctls:
> test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> test VIDIOC_G/S_EDID: OK (Not Supported)
>
> Control ioctls:
> test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> test VIDIOC_QUERYCTRL: OK
> test VIDIOC_G/S_CTRL: OK
> test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> Standard Controls: 10 Private Controls: 0
>
> Format ioctls:
> test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> test VIDIOC_G/S_PARM: OK (Not Supported)
> test VIDIOC_G_FBUF: OK (Not Supported)
> test VIDIOC_G_FMT: OK
> test VIDIOC_TRY_FMT: OK
> test VIDIOC_S_FMT: OK
> test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> test Cropping: OK
> test Composing: OK
> test Scaling: OK (Not Supported)
>
> Codec ioctls:
> test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
> test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> test VIDIOC_(TRY_)DECODER_CMD: OK
>
> Buffer ioctls:
> test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> test CREATE_BUFS maximum buffers: OK
> test VIDIOC_REMOVE_BUFS: OK
> test VIDIOC_EXPBUF: OK
> test Requests: OK (Not Supported)
> test blocking wait: OK
>
> Total for iris_driver device /dev/video0: 48, Succeeded: 48, Failed: 0, Warnings: 0
>
> ~ # v4l2-compliance -d /dev/video1
> v4l2-compliance 1.32.0, 64 bits, 64-bit time_t
>
> Compliance test for iris_driver device /dev/video1:
>
> Driver Info:
> Driver name : iris_driver
> Card type : Iris Encoder
> Bus info : platform:aa00000.video-codec
> Driver version : 7.0.0
> Capabilities : 0x84204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Device Capabilities
> Device Caps : 0x04204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Detected Stateful Encoder
>
> Required ioctls:
> test VIDIOC_QUERYCAP: OK
> test invalid ioctls: OK
>
> Allow for multiple opens:
> test second /dev/video1 open: OK
> test VIDIOC_QUERYCAP: OK
> test VIDIOC_G/S_PRIORITY: OK
> test for unlimited opens: OK
>
> Debug ioctls:
> test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> test VIDIOC_LOG_STATUS: OK (Not Supported)
>
> Input ioctls:
> test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> test VIDIOC_ENUMAUDIO: OK (Not Supported)
> test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDIO: OK (Not Supported)
> Inputs: 0 Audio Inputs: 0 Tuners: 0
>
> Output ioctls:
> test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> Outputs: 0 Audio Outputs: 0 Modulators: 0
>
> Input/Output configuration ioctls:
> test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> test VIDIOC_G/S_EDID: OK (Not Supported)
>
> Control ioctls:
> test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> test VIDIOC_QUERYCTRL: OK
> test VIDIOC_G/S_CTRL: OK
> test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> Standard Controls: 43 Private Controls: 0
>
> Format ioctls:
> test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> test VIDIOC_G/S_PARM: OK
> test VIDIOC_G_FBUF: OK (Not Supported)
> test VIDIOC_G_FMT: OK
> test VIDIOC_TRY_FMT: OK
> test VIDIOC_S_FMT: OK
> test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> test Cropping: OK
> test Composing: OK (Not Supported)
> test Scaling: OK (Not Supported)
>
> Codec ioctls:
> test VIDIOC_(TRY_)ENCODER_CMD: OK
> test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
>
> Buffer ioctls:
> test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> test CREATE_BUFS maximum buffers: OK
> test VIDIOC_REMOVE_BUFS: OK
> test VIDIOC_EXPBUF: OK
> test Requests: OK (Not Supported)
> test blocking wait: OK
>
> Total for iris_driver device /dev/video1: 48, Succeeded: 48, Failed: 0, Warnings: 0
You can run the streaming tests also using -s option.
v4l2-compliance -d /dev/video0 -s <clip>
v4l2-compliance -d /dev/video1 -s
> -------------------------------
>
> H264:
> |Test|FFmpeg-H.264-v4l2m2m|
> |-|-|
> |TOTAL|36/135|
> |TOTAL TIME|23.574s|
> |-|-|
> |AUD_MW_E|Pass|
> |BA1_FT_C|Fail|
> |BA1_Sony_D|Pass|
> |BA2_Sony_F|Pass|
> |BA3_SVA_C|Error|
> |BA_MW_D|Fail|
> |BAMQ1_JVC_C|Fail|
> |BAMQ2_JVC_C|Fail|
> |BANM_MW_D|Fail|
> |BASQP1_Sony_C|Fail|
> |CABA1_Sony_D|Fail|
> |CABA1_SVA_B|Pass|
> |CABA2_Sony_E|Pass|
> |CABA2_SVA_B|Pass|
> |CABA3_Sony_C|Fail|
> |CABA3_SVA_B|Pass|
> |CABA3_TOSHIBA_E|Fail|
> |cabac_mot_fld0_full|Fail|
> |cabac_mot_frm0_full|Pass|
> |cabac_mot_mbaff0_full|Fail|
> |cabac_mot_picaff0_full|Fail|
> |CABACI3_Sony_B|Pass|
> |CABAST3_Sony_E|Pass|
> |CABASTBR3_Sony_B|Pass|
> |CABREF3_Sand_D|Fail|
> |CACQP3_Sony_D|Pass|
> |CAFI1_SVA_C|Fail|
> |CAMA1_Sony_C|Fail|
> |CAMA1_TOSHIBA_B|Fail|
> |cama1_vtc_c|Fail|
> |cama2_vtc_b|Fail|
> |CAMA3_Sand_E|Fail|
> |cama3_vtc_b|Fail|
> |CAMACI3_Sony_C|Fail|
> |CAMANL1_TOSHIBA_B|Fail|
> |CAMANL2_TOSHIBA_B|Fail|
> |CAMANL3_Sand_E|Fail|
> |CAMASL3_Sony_B|Fail|
> |CAMP_MOT_MBAFF_L30|Fail|
> |CAMP_MOT_MBAFF_L31|Fail|
> |CANL1_Sony_E|Pass|
> |CANL1_SVA_B|Pass|
> |CANL1_TOSHIBA_G|Fail|
> |CANL2_Sony_E|Fail|
> |CANL2_SVA_B|Fail|
> |CANL3_Sony_C|Fail|
> |CANL3_SVA_B|Fail|
> |CANL4_SVA_B|Fail|
> |CANLMA2_Sony_C|Fail|
> |CANLMA3_Sony_C|Fail|
> |CAPA1_TOSHIBA_B|Fail|
> |CAPAMA3_Sand_F|Fail|
> |CAPCM1_Sand_E|Pass|
> |CAPCMNL1_Sand_E|Fail|
> |CAPM3_Sony_D|Fail|
> |CAQP1_Sony_B|Pass|
> |cavlc_mot_fld0_full_B|Fail|
> |cavlc_mot_frm0_full_B|Pass|
> |cavlc_mot_mbaff0_full_B|Fail|
> |cavlc_mot_picaff0_full_B|Fail|
> |CAWP1_TOSHIBA_E|Pass|
> |CAWP5_TOSHIBA_E|Pass|
> |CI1_FT_B|Pass|
> |CI_MW_D|Pass|
> |CVBS3_Sony_C|Pass|
> |CVCANLMA2_Sony_C|Fail|
> |CVFC1_Sony_C|Fail|
> |CVFI1_Sony_D|Fail|
> |CVFI1_SVA_C|Fail|
> |CVFI2_Sony_H|Fail|
> |CVFI2_SVA_C|Fail|
> |CVMA1_Sony_D|Fail|
> |CVMA1_TOSHIBA_B|Fail|
> |CVMANL1_TOSHIBA_B|Fail|
> |CVMANL2_TOSHIBA_B|Fail|
> |CVMAPAQP3_Sony_E|Fail|
> |CVMAQP2_Sony_G|Fail|
> |CVMAQP3_Sony_D|Fail|
> |CVMP_MOT_FLD_L30_B|Fail|
> |CVMP_MOT_FRM_L31_B|Fail|
> |CVNLFI1_Sony_C|Fail|
> |CVNLFI2_Sony_H|Fail|
> |CVPA1_TOSHIBA_B|Fail|
> |CVPCMNL1_SVA_C|Fail|
> |CVPCMNL2_SVA_C|Pass|
> |CVSE2_Sony_B|Fail|
> |CVSE3_Sony_H|Pass|
> |CVSEFDFT3_Sony_E|Fail|
> |CVWP1_TOSHIBA_E|Fail|
> |CVWP2_TOSHIBA_E|Pass|
> |CVWP3_TOSHIBA_E|Pass|
> |CVWP5_TOSHIBA_E|Fail|
> |FI1_Sony_E|Fail|
> |FM1_BT_B|Error|
> |FM1_FT_E|Error|
> |FM2_SVA_C|Error|
> |HCBP1_HHI_A|Pass|
> |HCBP2_HHI_A|Fail|
> |HCMP1_HHI_A|Fail|
> |LS_SVA_D|Fail|
> |MIDR_MW_D|Fail|
> |MPS_MW_A|Pass|
> |MR1_BT_A|Pass|
> |MR1_MW_A|Fail|
> |MR2_MW_A|Fail|
> |MR2_TANDBERG_E|Pass|
> |MR3_TANDBERG_B|Fail|
> |MR4_TANDBERG_C|Fail|
> |MR5_TANDBERG_C|Fail|
> |MR6_BT_B|Error|
> |MR7_BT_B|Error|
> |MR8_BT_B|Error|
> |MR9_BT_B|Fail|
> |MV1_BRCM_D|Pass|
> |NL1_Sony_D|Fail|
> |NL2_Sony_H|Pass|
> |NL3_SVA_E|Fail|
> |NLMQ1_JVC_C|Fail|
> |NLMQ2_JVC_C|Pass|
> |NRF_MW_E|Fail|
> |Sharp_MP_Field_1_B|Fail|
> |Sharp_MP_Field_2_B|Fail|
> |Sharp_MP_Field_3_B|Fail|
> |Sharp_MP_PAFF_1r2|Fail|
> |Sharp_MP_PAFF_2r|Fail|
> |SL1_SVA_B|Pass|
> |SP1_BT_A|Error|
> |sp2_bt_b|Error|
> |SVA_BA1_B|Pass|
> |SVA_BA2_D|Pass|
> |SVA_Base_B|Fail|
> |SVA_CL1_E|Fail|
> |SVA_FM1_E|Fail|
> |SVA_NL1_B|Fail|
> |SVA_NL2_E|Fail|
> |-|-|
> |Test|FFmpeg-H.264-v4l2m2m|
> |TOTAL|36/135|
> |TOTAL TIME|23.574s|
>
> |-|-|
> |Profile|FFmpeg-H.264-v4l2m2m|
> |CONSTRAINED_BASELINE|12/33|
> |BASELINE|1/7|
> |EXTENDED|0/6|
> |MAIN|23/89|
>
> |TOTALS|FFmpeg-H.264-v4l2m2m|
> |-|-|
> |TOTAL|36/135|
> |TOTAL TIME|23.574s|
> |-|-|
> |Profile|FFmpeg-H.264-v4l2m2m|
> |BASELINE|1/7|
> |CONSTRAINED_BASELINE|12/33|
> |EXTENDED|0/6|
> |MAIN|23/89|
> |-|-|
>
> -------------------------------
>
> |Test|FFmpeg-H.265-v4l2m2m|
> |-|-|
> |TOTAL|109/147|
> |TOTAL TIME|38.547s|
> |-|-|
> |AMP_A_Samsung_7|Pass|
> |AMP_B_Samsung_7|Pass|
> |AMP_D_Hisilicon_3|Pass|
> |AMP_E_Hisilicon_3|Pass|
> |AMP_F_Hisilicon_3|Pass|
> |AMVP_A_MTK_4|Pass|
> |AMVP_B_MTK_4|Fail|
> |AMVP_C_Samsung_7|Pass|
> |BUMPING_A_ericsson_1|Fail|
> |CAINIT_A_SHARP_4|Pass|
> |CAINIT_B_SHARP_4|Pass|
> |CAINIT_C_SHARP_3|Pass|
> |CAINIT_D_SHARP_3|Pass|
> |CAINIT_E_SHARP_3|Pass|
> |CAINIT_F_SHARP_3|Pass|
> |CAINIT_G_SHARP_3|Pass|
> |CAINIT_H_SHARP_3|Pass|
> |CIP_A_Panasonic_3|Pass|
> |cip_B_NEC_3|Pass|
> |CIP_C_Panasonic_2|Pass|
> |CONFWIN_A_Sony_1|Fail|
> |DBLK_A_MAIN10_VIXS_4|Fail|
> |DBLK_A_SONY_3|Pass|
> |DBLK_B_SONY_3|Pass|
> |DBLK_C_SONY_3|Pass|
> |DBLK_D_VIXS_2|Pass|
> |DBLK_E_VIXS_2|Pass|
> |DBLK_F_VIXS_2|Pass|
> |DBLK_G_VIXS_2|Pass|
> |DELTAQP_A_BRCM_4|Pass|
> |DELTAQP_B_SONY_3|Pass|
> |DELTAQP_C_SONY_3|Pass|
> |DSLICE_A_HHI_5|Pass|
> |DSLICE_B_HHI_5|Pass|
> |DSLICE_C_HHI_5|Pass|
> |ENTP_A_QUALCOMM_1|Pass|
> |ENTP_B_Qualcomm_1|Pass|
> |ENTP_C_Qualcomm_1|Pass|
> |EXT_A_ericsson_4|Pass|
> |FILLER_A_Sony_1|Pass|
> |HRD_A_Fujitsu_3|Pass|
> |INITQP_A_Sony_1|Pass|
> |INITQP_B_Main10_Sony_1|Fail|
> |ipcm_A_NEC_3|Fail|
> |ipcm_B_NEC_3|Pass|
> |ipcm_C_NEC_3|Pass|
> |ipcm_D_NEC_3|Pass|
> |ipcm_E_NEC_2|Pass|
> |IPRED_A_docomo_2|Pass|
> |IPRED_B_Nokia_3|Pass|
> |IPRED_C_Mitsubishi_3|Pass|
> |LS_A_Orange_2|Pass|
> |LS_B_Orange_4|Pass|
> |LTRPSPS_A_Qualcomm_1|Fail|
> |MAXBINS_A_TI_5|Pass|
> |MAXBINS_B_TI_5|Pass|
> |MAXBINS_C_TI_5|Pass|
> |MERGE_A_TI_3|Pass|
> |MERGE_B_TI_3|Pass|
> |MERGE_C_TI_3|Fail|
> |MERGE_D_TI_3|Fail|
> |MERGE_E_TI_3|Pass|
> |MERGE_F_MTK_4|Pass|
> |MERGE_G_HHI_4|Pass|
> |MVCLIP_A_qualcomm_3|Fail|
> |MVDL1ZERO_A_docomo_4|Pass|
> |MVEDGE_A_qualcomm_3|Fail|
> |NoOutPrior_A_Qualcomm_1|Fail|
> |NoOutPrior_B_Qualcomm_1|Fail|
> |NUT_A_ericsson_5|Fail|
> |OPFLAG_A_Qualcomm_1|Pass|
> |OPFLAG_B_Qualcomm_1|Fail|
> |OPFLAG_C_Qualcomm_1|Fail|
> |PICSIZE_A_Bossen_1|Error|
> |PICSIZE_B_Bossen_1|Error|
> |PICSIZE_C_Bossen_1|Error|
> |PICSIZE_D_Bossen_1|Error|
> |PMERGE_A_TI_3|Pass|
> |PMERGE_B_TI_3|Pass|
> |PMERGE_C_TI_3|Pass|
> |PMERGE_D_TI_3|Pass|
> |PMERGE_E_TI_3|Pass|
> |POC_A_Bossen_3|Pass|
> |PPS_A_qualcomm_7|Pass|
> |PS_B_VIDYO_3|Pass|
> |RAP_A_docomo_6|Fail|
> |RAP_B_Bossen_2|Fail|
> |RPLM_A_qualcomm_4|Pass|
> |RPLM_B_qualcomm_4|Pass|
> |RPS_A_docomo_5|Pass|
> |RPS_B_qualcomm_5|Pass|
> |RPS_C_ericsson_5|Pass|
> |RPS_D_ericsson_6|Pass|
> |RPS_E_qualcomm_5|Pass|
> |RPS_F_docomo_2|Pass|
> |RQT_A_HHI_4|Pass|
> |RQT_B_HHI_4|Pass|
> |RQT_C_HHI_4|Pass|
> |RQT_D_HHI_4|Pass|
> |RQT_E_HHI_4|Pass|
> |RQT_F_HHI_4|Pass|
> |RQT_G_HHI_4|Pass|
> |SAO_A_MediaTek_4|Fail|
> |SAO_B_MediaTek_5|Pass|
> |SAO_C_Samsung_5|Pass|
> |SAO_D_Samsung_5|Pass|
> |SAO_E_Canon_4|Pass|
> |SAO_F_Canon_3|Pass|
> |SAO_G_Canon_3|Pass|
> |SAO_H_Parabola_1|Pass|
> |SAODBLK_A_MainConcept_4|Pass|
> |SAODBLK_B_MainConcept_4|Pass|
> |SDH_A_Orange_4|Pass|
> |SLICES_A_Rovi_3|Pass|
> |SLIST_A_Sony_5|Pass|
> |SLIST_B_Sony_9|Pass|
> |SLIST_C_Sony_4|Pass|
> |SLIST_D_Sony_9|Pass|
> |SLPPLP_A_VIDYO_2|Pass|
> |STRUCT_A_Samsung_7|Pass|
> |STRUCT_B_Samsung_7|Pass|
> |TILES_A_Cisco_2|Pass|
> |TILES_B_Cisco_1|Pass|
> |TMVP_A_MS_3|Pass|
> |TSCL_A_VIDYO_5|Fail|
> |TSCL_B_VIDYO_4|Pass|
> |TSKIP_A_MS_3|Pass|
> |TSUNEQBD_A_MAIN10_Technicolor_2|Error|
> |TUSIZE_A_Samsung_1|Pass|
> |VPSID_A_VIDYO_2|Pass|
> |VPSSPSPPS_A_MainConcept_1|Fail|
> |WP_A_MAIN10_Toshiba_3|Fail|
> |WP_A_Toshiba_3|Pass|
> |WP_B_Toshiba_3|Pass|
> |WP_MAIN10_B_Toshiba_3|Fail|
> |WPP_A_ericsson_MAIN10_2|Fail|
> |WPP_A_ericsson_MAIN_2|Pass|
> |WPP_B_ericsson_MAIN10_2|Fail|
> |WPP_B_ericsson_MAIN_2|Fail|
> |WPP_C_ericsson_MAIN10_2|Fail|
> |WPP_C_ericsson_MAIN_2|Fail|
> |WPP_D_ericsson_MAIN10_2|Error|
> |WPP_D_ericsson_MAIN_2|Error|
> |WPP_E_ericsson_MAIN10_2|Fail|
> |WPP_E_ericsson_MAIN_2|Fail|
> |WPP_F_ericsson_MAIN10_2|Fail|
> |WPP_F_ericsson_MAIN_2|Pass|
> |-|-|
> |Test|FFmpeg-H.265-v4l2m2m|
> |TOTAL|109/147|
> |TOTAL TIME|38.547s|
>
> |-|-|
> |Profile|FFmpeg-H.265-v4l2m2m|
> |MAIN|108/135|
> |MAIN_10|0/11|
> |MAIN_STILL_PICTURE|1/1|
>
> |TOTALS|FFmpeg-H.265-v4l2m2m|
> |-|-|
> |TOTAL|109/147|
> |TOTAL TIME|38.547s|
> |-|-|
> |Profile|FFmpeg-H.265-v4l2m2m|
> |MAIN|108/135|
> |MAIN_10|0/11|
> |MAIN_STILL_PICTURE|1/1|
> |-|-|
>
> -------------------------------
>
> |Test|FFmpeg-VP9-v4l2m2m|
> |-|-|
> |TOTAL|111/305|
> |TOTAL TIME|77.260s|
> |-|-|
> |vp90-2-00-quantizer-00.webm|Pass|
> |vp90-2-00-quantizer-01.webm|Pass|
> |vp90-2-00-quantizer-02.webm|Pass|
> |vp90-2-00-quantizer-03.webm|Fail|
> |vp90-2-00-quantizer-04.webm|Fail|
> |vp90-2-00-quantizer-05.webm|Pass|
> |vp90-2-00-quantizer-06.webm|Pass|
> |vp90-2-00-quantizer-07.webm|Pass|
> |vp90-2-00-quantizer-08.webm|Fail|
> |vp90-2-00-quantizer-09.webm|Pass|
> |vp90-2-00-quantizer-10.webm|Pass|
> |vp90-2-00-quantizer-11.webm|Pass|
> |vp90-2-00-quantizer-12.webm|Pass|
> |vp90-2-00-quantizer-13.webm|Pass|
> |vp90-2-00-quantizer-14.webm|Pass|
> |vp90-2-00-quantizer-15.webm|Pass|
> |vp90-2-00-quantizer-16.webm|Fail|
> |vp90-2-00-quantizer-17.webm|Pass|
> |vp90-2-00-quantizer-18.webm|Pass|
> |vp90-2-00-quantizer-19.webm|Pass|
> |vp90-2-00-quantizer-20.webm|Pass|
> |vp90-2-00-quantizer-21.webm|Pass|
> |vp90-2-00-quantizer-22.webm|Pass|
> |vp90-2-00-quantizer-23.webm|Pass|
> |vp90-2-00-quantizer-24.webm|Pass|
> |vp90-2-00-quantizer-25.webm|Fail|
> |vp90-2-00-quantizer-26.webm|Fail|
> |vp90-2-00-quantizer-27.webm|Pass|
> |vp90-2-00-quantizer-28.webm|Pass|
> |vp90-2-00-quantizer-29.webm|Fail|
> |vp90-2-00-quantizer-30.webm|Pass|
> |vp90-2-00-quantizer-31.webm|Pass|
> |vp90-2-00-quantizer-32.webm|Fail|
> |vp90-2-00-quantizer-33.webm|Pass|
> |vp90-2-00-quantizer-34.webm|Pass|
> |vp90-2-00-quantizer-35.webm|Pass|
> |vp90-2-00-quantizer-36.webm|Pass|
> |vp90-2-00-quantizer-37.webm|Pass|
> |vp90-2-00-quantizer-38.webm|Pass|
> |vp90-2-00-quantizer-39.webm|Pass|
> |vp90-2-00-quantizer-40.webm|Pass|
> |vp90-2-00-quantizer-41.webm|Pass|
> |vp90-2-00-quantizer-42.webm|Pass|
> |vp90-2-00-quantizer-43.webm|Pass|
> |vp90-2-00-quantizer-44.webm|Fail|
> |vp90-2-00-quantizer-45.webm|Pass|
> |vp90-2-00-quantizer-46.webm|Pass|
> |vp90-2-00-quantizer-47.webm|Pass|
> |vp90-2-00-quantizer-48.webm|Pass|
> |vp90-2-00-quantizer-49.webm|Pass|
> |vp90-2-00-quantizer-50.webm|Fail|
> |vp90-2-00-quantizer-51.webm|Pass|
> |vp90-2-00-quantizer-52.webm|Pass|
> |vp90-2-00-quantizer-53.webm|Pass|
> |vp90-2-00-quantizer-54.webm|Pass|
> |vp90-2-00-quantizer-55.webm|Pass|
> |vp90-2-00-quantizer-56.webm|Pass|
> |vp90-2-00-quantizer-57.webm|Pass|
> |vp90-2-00-quantizer-58.webm|Pass|
> |vp90-2-00-quantizer-59.webm|Fail|
> |vp90-2-00-quantizer-60.webm|Pass|
> |vp90-2-00-quantizer-61.webm|Pass|
> |vp90-2-00-quantizer-62.webm|Pass|
> |vp90-2-00-quantizer-63.webm|Fail|
> |vp90-2-01-sharpness-1.webm|Pass|
> |vp90-2-01-sharpness-2.webm|Pass|
> |vp90-2-01-sharpness-3.webm|Pass|
> |vp90-2-01-sharpness-4.webm|Pass|
> |vp90-2-01-sharpness-5.webm|Pass|
> |vp90-2-01-sharpness-6.webm|Pass|
> |vp90-2-01-sharpness-7.webm|Pass|
> |vp90-2-02-size-08x08.webm|Error|
> |vp90-2-02-size-08x10.webm|Error|
> |vp90-2-02-size-08x16.webm|Error|
> |vp90-2-02-size-08x18.webm|Error|
> |vp90-2-02-size-08x32.webm|Error|
> |vp90-2-02-size-08x34.webm|Error|
> |vp90-2-02-size-08x64.webm|Error|
> |vp90-2-02-size-08x66.webm|Error|
> |vp90-2-02-size-10x08.webm|Error|
> |vp90-2-02-size-10x10.webm|Error|
> |vp90-2-02-size-10x16.webm|Error|
> |vp90-2-02-size-10x18.webm|Error|
> |vp90-2-02-size-10x32.webm|Error|
> |vp90-2-02-size-10x34.webm|Error|
> |vp90-2-02-size-10x64.webm|Error|
> |vp90-2-02-size-10x66.webm|Error|
> |vp90-2-02-size-130x132.webm|Fail|
> |vp90-2-02-size-132x130.webm|Pass|
> |vp90-2-02-size-132x132.webm|Pass|
> |vp90-2-02-size-16x08.webm|Error|
> |vp90-2-02-size-16x10.webm|Error|
> |vp90-2-02-size-16x16.webm|Error|
> |vp90-2-02-size-16x18.webm|Error|
> |vp90-2-02-size-16x32.webm|Error|
> |vp90-2-02-size-16x34.webm|Error|
> |vp90-2-02-size-16x64.webm|Error|
> |vp90-2-02-size-16x66.webm|Error|
> |vp90-2-02-size-178x180.webm|Fail|
> |vp90-2-02-size-180x178.webm|Pass|
> |vp90-2-02-size-180x180.webm|Fail|
> |vp90-2-02-size-18x08.webm|Error|
> |vp90-2-02-size-18x10.webm|Error|
> |vp90-2-02-size-18x16.webm|Error|
> |vp90-2-02-size-18x18.webm|Error|
> |vp90-2-02-size-18x32.webm|Error|
> |vp90-2-02-size-18x34.webm|Error|
> |vp90-2-02-size-18x64.webm|Error|
> |vp90-2-02-size-18x66.webm|Error|
> |vp90-2-02-size-32x08.webm|Error|
> |vp90-2-02-size-32x10.webm|Error|
> |vp90-2-02-size-32x16.webm|Error|
> |vp90-2-02-size-32x18.webm|Error|
> |vp90-2-02-size-32x32.webm|Error|
> |vp90-2-02-size-32x34.webm|Error|
> |vp90-2-02-size-32x64.webm|Error|
> |vp90-2-02-size-32x66.webm|Error|
> |vp90-2-02-size-34x08.webm|Error|
> |vp90-2-02-size-34x10.webm|Error|
> |vp90-2-02-size-34x16.webm|Error|
> |vp90-2-02-size-34x18.webm|Error|
> |vp90-2-02-size-34x32.webm|Error|
> |vp90-2-02-size-34x34.webm|Error|
> |vp90-2-02-size-34x64.webm|Error|
> |vp90-2-02-size-34x66.webm|Error|
> |vp90-2-02-size-64x08.webm|Error|
> |vp90-2-02-size-64x10.webm|Error|
> |vp90-2-02-size-64x16.webm|Error|
> |vp90-2-02-size-64x18.webm|Error|
> |vp90-2-02-size-64x32.webm|Error|
> |vp90-2-02-size-64x34.webm|Error|
> |vp90-2-02-size-64x64.webm|Error|
> |vp90-2-02-size-64x66.webm|Error|
> |vp90-2-02-size-66x08.webm|Error|
> |vp90-2-02-size-66x10.webm|Error|
> |vp90-2-02-size-66x16.webm|Error|
> |vp90-2-02-size-66x18.webm|Error|
> |vp90-2-02-size-66x32.webm|Error|
> |vp90-2-02-size-66x34.webm|Error|
> |vp90-2-02-size-66x64.webm|Error|
> |vp90-2-02-size-66x66.webm|Error|
> |vp90-2-02-size-lf-1920x1080.webm|Fail|
> |vp90-2-03-deltaq.webm|Fail|
> |vp90-2-03-size-196x196.webm|Pass|
> |vp90-2-03-size-196x198.webm|Pass|
> |vp90-2-03-size-196x200.webm|Pass|
> |vp90-2-03-size-196x202.webm|Pass|
> |vp90-2-03-size-196x208.webm|Fail|
> |vp90-2-03-size-196x210.webm|Fail|
> |vp90-2-03-size-196x224.webm|Pass|
> |vp90-2-03-size-196x226.webm|Fail|
> |vp90-2-03-size-198x196.webm|Fail|
> |vp90-2-03-size-198x198.webm|Pass|
> |vp90-2-03-size-198x200.webm|Pass|
> |vp90-2-03-size-198x202.webm|Pass|
> |vp90-2-03-size-198x208.webm|Pass|
> |vp90-2-03-size-198x210.webm|Fail|
> |vp90-2-03-size-198x224.webm|Pass|
> |vp90-2-03-size-198x226.webm|Fail|
> |vp90-2-03-size-200x196.webm|Fail|
> |vp90-2-03-size-200x198.webm|Fail|
> |vp90-2-03-size-200x200.webm|Fail|
> |vp90-2-03-size-200x202.webm|Pass|
> |vp90-2-03-size-200x208.webm|Fail|
> |vp90-2-03-size-200x210.webm|Fail|
> |vp90-2-03-size-200x224.webm|Pass|
> |vp90-2-03-size-200x226.webm|Fail|
> |vp90-2-03-size-202x196.webm|Fail|
> |vp90-2-03-size-202x198.webm|Fail|
> |vp90-2-03-size-202x200.webm|Fail|
> |vp90-2-03-size-202x202.webm|Fail|
> |vp90-2-03-size-202x208.webm|Pass|
> |vp90-2-03-size-202x210.webm|Fail|
> |vp90-2-03-size-202x224.webm|Fail|
> |vp90-2-03-size-202x226.webm|Pass|
> |vp90-2-03-size-208x196.webm|Pass|
> |vp90-2-03-size-208x198.webm|Pass|
> |vp90-2-03-size-208x200.webm|Pass|
> |vp90-2-03-size-208x202.webm|Pass|
> |vp90-2-03-size-208x208.webm|Pass|
> |vp90-2-03-size-208x210.webm|Pass|
> |vp90-2-03-size-208x224.webm|Pass|
> |vp90-2-03-size-208x226.webm|Pass|
> |vp90-2-03-size-210x196.webm|Pass|
> |vp90-2-03-size-210x198.webm|Pass|
> |vp90-2-03-size-210x200.webm|Fail|
> |vp90-2-03-size-210x202.webm|Pass|
> |vp90-2-03-size-210x208.webm|Pass|
> |vp90-2-03-size-210x210.webm|Fail|
> |vp90-2-03-size-210x224.webm|Pass|
> |vp90-2-03-size-210x226.webm|Fail|
> |vp90-2-03-size-224x196.webm|Fail|
> |vp90-2-03-size-224x198.webm|Pass|
> |vp90-2-03-size-224x200.webm|Pass|
> |vp90-2-03-size-224x202.webm|Fail|
> |vp90-2-03-size-224x208.webm|Pass|
> |vp90-2-03-size-224x210.webm|Fail|
> |vp90-2-03-size-224x224.webm|Pass|
> |vp90-2-03-size-224x226.webm|Pass|
> |vp90-2-03-size-226x196.webm|Pass|
> |vp90-2-03-size-226x198.webm|Fail|
> |vp90-2-03-size-226x200.webm|Fail|
> |vp90-2-03-size-226x202.webm|Fail|
> |vp90-2-03-size-226x208.webm|Pass|
> |vp90-2-03-size-226x210.webm|Pass|
> |vp90-2-03-size-226x224.webm|Fail|
> |vp90-2-03-size-226x226.webm|Fail|
> |vp90-2-03-size-352x288.webm|Pass|
> |vp90-2-05-resize.ivf|Fail|
> |vp90-2-06-bilinear.webm|Pass|
> |vp90-2-07-frame_parallel-1.webm|Pass|
> |vp90-2-07-frame_parallel.webm|Fail|
> |vp90-2-08-tile_1x2_frame_parallel.webm|Fail|
> |vp90-2-08-tile_1x2.webm|Fail|
> |vp90-2-08-tile_1x4_frame_parallel.webm|Fail|
> |vp90-2-08-tile_1x4.webm|Fail|
> |vp90-2-08-tile_1x8_frame_parallel.webm|Pass|
> |vp90-2-08-tile_1x8.webm|Pass|
> |vp90-2-08-tile-4x1.webm|Pass|
> |vp90-2-08-tile-4x4.webm|Pass|
> |vp90-2-09-aq2.webm|Fail|
> |vp90-2-09-lf_deltas.webm|Fail|
> |vp90-2-09-subpixel-00.ivf|Fail|
> |vp90-2-10-show-existing-frame2.webm|Fail|
> |vp90-2-10-show-existing-frame.webm|Fail|
> |vp90-2-11-size-351x287.webm|Fail|
> |vp90-2-11-size-351x288.webm|Fail|
> |vp90-2-11-size-352x287.webm|Fail|
> |vp90-2-12-droppable_1.ivf|Pass|
> |vp90-2-12-droppable_2.ivf|Pass|
> |vp90-2-12-droppable_3.ivf|Pass|
> |vp90-2-14-resize-10frames-fp-tiles-1-2-4-8.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-1-2.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-1-4.webm|Fail|
> |vp90-2-14-resize-10frames-fp-tiles-1-8.webm|Fail|
> |vp90-2-14-resize-10frames-fp-tiles-2-1.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-2-4.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-2-8.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-4-1.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-4-2.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-4-8.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-8-1.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-8-2.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-8-4-2-1.webm|Timeout|
> |vp90-2-14-resize-10frames-fp-tiles-8-4.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-1-16.webm|Fail|
> |vp90-2-14-resize-fp-tiles-1-2-4-8-16.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-1-2.webm|Fail|
> |vp90-2-14-resize-fp-tiles-1-4.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-16-1.webm|Error|
> |vp90-2-14-resize-fp-tiles-16-2.webm|Error|
> |vp90-2-14-resize-fp-tiles-16-4.webm|Error|
> |vp90-2-14-resize-fp-tiles-16-8-4-2-1.webm|Error|
> |vp90-2-14-resize-fp-tiles-16-8.webm|Error|
> |vp90-2-14-resize-fp-tiles-1-8.webm|Fail|
> |vp90-2-14-resize-fp-tiles-2-16.webm|Error|
> |vp90-2-14-resize-fp-tiles-2-1.webm|Fail|
> |vp90-2-14-resize-fp-tiles-2-4.webm|Fail|
> |vp90-2-14-resize-fp-tiles-2-8.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-4-16.webm|Error|
> |vp90-2-14-resize-fp-tiles-4-1.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-4-2.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-4-8.webm|Fail|
> |vp90-2-14-resize-fp-tiles-8-16.webm|Error|
> |vp90-2-14-resize-fp-tiles-8-1.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-8-2.webm|Timeout|
> |vp90-2-14-resize-fp-tiles-8-4.webm|Timeout|
> |vp90-2-15-segkey_adpq.webm|Fail|
> |vp90-2-15-segkey.webm|Pass|
> |vp90-2-16-intra-only.webm|Fail|
> |vp90-2-17-show-existing-frame.webm|Pass|
> |vp90-2-18-resize.ivf|Fail|
> |vp90-2-19-skip-01.webm|Fail|
> |vp90-2-19-skip-02.webm|Fail|
> |vp90-2-19-skip.webm|Pass|
> |vp90-2-20-big_superframe-01.webm|Fail|
> |vp90-2-20-big_superframe-02.webm|Fail|
> |vp90-2-21-resize_inter_1280x720_5_1-2.webm|Timeout|
> |vp90-2-21-resize_inter_1280x720_5_3-4.webm|Timeout|
> |vp90-2-21-resize_inter_1280x720_7_1-2.webm|Fail|
> |vp90-2-21-resize_inter_1280x720_7_3-4.webm|Timeout|
> |vp90-2-21-resize_inter_1920x1080_5_1-2.webm|Timeout|
> |vp90-2-21-resize_inter_1920x1080_5_3-4.webm|Timeout|
> |vp90-2-21-resize_inter_1920x1080_7_1-2.webm|Timeout|
> |vp90-2-21-resize_inter_1920x1080_7_3-4.webm|Timeout|
> |vp90-2-21-resize_inter_320x180_5_1-2.webm|Fail|
> |vp90-2-21-resize_inter_320x180_5_3-4.webm|Fail|
> |vp90-2-21-resize_inter_320x180_7_1-2.webm|Fail|
> |vp90-2-21-resize_inter_320x180_7_3-4.webm|Fail|
> |vp90-2-21-resize_inter_320x240_5_1-2.webm|Timeout|
> |vp90-2-21-resize_inter_320x240_5_3-4.webm|Fail|
> |vp90-2-21-resize_inter_320x240_7_1-2.webm|Fail|
> |vp90-2-21-resize_inter_320x240_7_3-4.webm|Timeout|
> |vp90-2-21-resize_inter_640x360_5_1-2.webm|Fail|
> |vp90-2-21-resize_inter_640x360_5_3-4.webm|Timeout|
> |vp90-2-21-resize_inter_640x360_7_1-2.webm|Fail|
> |vp90-2-21-resize_inter_640x360_7_3-4.webm|Fail|
> |vp90-2-21-resize_inter_640x480_5_1-2.webm|Timeout|
> |vp90-2-21-resize_inter_640x480_5_3-4.webm|Fail|
> |vp90-2-21-resize_inter_640x480_7_1-2.webm|Timeout|
> |vp90-2-21-resize_inter_640x480_7_3-4.webm|Timeout|
> |vp90-2-22-svc_1280x720_1.webm|Pass|
> |vp90-2-22-svc_1280x720_3.ivf|Timeout|
> |vp91-2-04-yuv422.webm|Error|
> |vp91-2-04-yuv444.webm|Error|
> |-|-|
> |Test|FFmpeg-VP9-v4l2m2m|
> |TOTAL|111/305|
> |TOTAL TIME|77.260s|
>
> |TOTALS|FFmpeg-VP9-v4l2m2m|
> |-|-|
> |TOTAL|111/305|
> |TOTAL TIME|77.260s|
> |-|-|
>
> Signed-off-by: Alexander Koskovich<akoskovich@pm.me>
> ---
> Alexander Koskovich (3):
> dt-bindings: media: qcom,milos-iris: Add Milos video codec
> media: iris: Add support for Milos (VPU v2.0)
> arm64: dts: qcom: milos: Add Iris VPU v2.0
>
> .../devicetree/bindings/media/qcom,milos-iris.yaml | 166 ++++++
> arch/arm64/boot/dts/qcom/milos.dtsi | 85 +++
> .../platform/qcom/iris/iris_platform_common.h | 1 +
> .../media/platform/qcom/iris/iris_platform_gen2.c | 106 ++++
> .../media/platform/qcom/iris/iris_platform_milos.h | 655 +++++++++++++++++++++
> drivers/media/platform/qcom/iris/iris_probe.c | 4 +
> 6 files changed, 1017 insertions(+)
> ---
> base-commit: 591cd656a1bf5ea94a222af5ef2ee76df029c1d2
> change-id: 20260406-milos-iris-d1a854e4cb75
>
> Best regards,
^ permalink raw reply
* Re: [PATCH 2/3] media: iris: Add support for Milos (VPU v2.0)
From: Vishnu Reddy @ 2026-04-09 4:34 UTC (permalink / raw)
To: Alexander Koskovich, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Bryan O'Donoghue, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio
Cc: Luca Weiss, linux-media, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260406-milos-iris-v1-2-17ed0167ba6f@pm.me>
On 4/6/2026 3:49 PM, Alexander Koskovich wrote:
> Add support for the Milos Iris codec. This only supports the variant
> found on the SM7635-AB that has half of it's pipes disabled via efuse.
>
> Signed-off-by: Alexander Koskovich<akoskovich@pm.me>
> ---
> .../platform/qcom/iris/iris_platform_common.h | 1 +
> .../media/platform/qcom/iris/iris_platform_gen2.c | 106 ++++
> .../media/platform/qcom/iris/iris_platform_milos.h | 655 +++++++++++++++++++++
> drivers/media/platform/qcom/iris/iris_probe.c | 4 +
> 4 files changed, 766 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index 5a489917580e..c8a9f122952e 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -41,6 +41,7 @@ enum pipe_type {
> PIPE_4 = 4,
> };
>
> +extern const struct iris_platform_data milos_data;
> extern const struct iris_platform_data qcs8300_data;
> extern const struct iris_platform_data sc7280_data;
> extern const struct iris_platform_data sm8250_data;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index 5da90d47f9c6..78cd4656b981 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -12,6 +12,7 @@
> #include "iris_vpu_buffer.h"
> #include "iris_vpu_common.h"
>
> +#include "iris_platform_milos.h"
> #include "iris_platform_qcs8300.h"
> #include "iris_platform_sm8650.h"
> #include "iris_platform_sm8750.h"
> @@ -1317,3 +1318,108 @@ const struct iris_platform_data qcs8300_data = {
> .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
> .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
> };
> +
> +/*
> + * Shares most of SM8550 data except:
> + * - vpu_ops to iris_vpu2_ops
> + * - icc_tbl to milos_icc_table
> + * - clk_rst_tbl to sm8650_clk_reset_table
> + * - opp_pd_tbl to milos_opp_pd_table
> + * - fwname to "qcom/vpu/vpu20_2v.mbn"
> + * - inst_iris_fmts to platform_fmts_milos_dec
> + * - inst_caps to platform_inst_cap_milos
> + * - inst_fw_caps_dec to inst_fw_cap_milos_dec
> + * - inst_fw_caps_enc to inst_fw_cap_milos_enc
> + * - ubwc_config to ubwc_config_milos
> + * - num_vpp_pipe to 2
> + * - max_core_mbpf scaled for 4k@30fps dec/enc
> + * - max_core_mbps scaled for 4k@30fps dec & 1080p@30 enc
> + */
> +const struct iris_platform_data milos_data = {
> + .get_instance = iris_hfi_gen2_get_instance,
> + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
> + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
> + .get_vpu_buffer_size = iris_vpu_buf_size,
> + .vpu_ops = &iris_vpu2_ops,
> + .set_preset_registers = iris_set_sm8550_preset_registers,
> + .icc_tbl = milos_icc_table,
> + .icc_tbl_size = ARRAY_SIZE(milos_icc_table),
> + .clk_rst_tbl = sm8650_clk_reset_table,
> + .clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table),
> + .bw_tbl_dec = sm8550_bw_table_dec,
> + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
> + .pmdomain_tbl = sm8550_pmdomain_table,
> + .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
> + .opp_pd_tbl = milos_opp_pd_table,
> + .opp_pd_tbl_size = ARRAY_SIZE(milos_opp_pd_table),
> + .clk_tbl = sm8550_clk_table,
> + .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table),
> + .opp_clk_tbl = sm8550_opp_clk_table,
> + /* Upper bound of DMA address range */
> + .dma_mask = 0xe0000000 - 1,
> + .fwname = "qcom/vpu/vpu20_2v.mbn",
can you check how firmware names are added for earlier platforms.
It should be like this vpu20_p2.mbn
> + .pas_id = IRIS_PAS_ID,
> + .inst_iris_fmts = platform_fmts_milos_dec,
> + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_milos_dec),
> + .inst_caps = &platform_inst_cap_milos,
> + .inst_fw_caps_dec = inst_fw_cap_milos_dec,
> + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_milos_dec),
> + .inst_fw_caps_enc = inst_fw_cap_milos_enc,
> + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_milos_enc),
> + .tz_cp_config_data = tz_cp_config_sm8550,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550),
> + .core_arch = VIDEO_ARCH_LX,
> + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
> + .ubwc_config = &ubwc_config_milos,
> + .num_vpp_pipe = 2,
> + .max_session_count = 16,
> + .max_core_mbpf = ((4096 * 2176) / 256) * 2,
> + .max_core_mbps = ((3840 * 2176) / 256) * 30 + ((1920 * 1088) / 256) * 30,
> + .dec_input_config_params_default =
> + sm8550_vdec_input_config_params_default,
> + .dec_input_config_params_default_size =
> + ARRAY_SIZE(sm8550_vdec_input_config_params_default),
> + .dec_input_config_params_hevc =
> + sm8550_vdec_input_config_param_hevc,
> + .dec_input_config_params_hevc_size =
> + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
> + .dec_input_config_params_vp9 =
> + sm8550_vdec_input_config_param_vp9,
> + .dec_input_config_params_vp9_size =
> + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
> + .dec_output_config_params =
> + sm8550_vdec_output_config_params,
> + .dec_output_config_params_size =
> + ARRAY_SIZE(sm8550_vdec_output_config_params),
> +
> + .enc_input_config_params =
> + sm8550_venc_input_config_params,
> + .enc_input_config_params_size =
> + ARRAY_SIZE(sm8550_venc_input_config_params),
> + .enc_output_config_params =
> + sm8550_venc_output_config_params,
> + .enc_output_config_params_size =
> + ARRAY_SIZE(sm8550_venc_output_config_params),
> +
> + .dec_input_prop = sm8550_vdec_subscribe_input_properties,
> + .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
> + .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
> + .dec_output_prop_avc_size =
> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
> + .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
> + .dec_output_prop_hevc_size =
> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
> + .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
> + .dec_output_prop_vp9_size =
> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
> +
> + .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
> + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
> + .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
> + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
> +
> + .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl,
> + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl),
> + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
> + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
> +};
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_milos.h b/drivers/media/platform/qcom/iris/iris_platform_milos.h
> new file mode 100644
> index 000000000000..dacd3ad5aa7e
> --- /dev/null
> +++ b/drivers/media/platform/qcom/iris/iris_platform_milos.h
> @@ -0,0 +1,655 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __IRIS_PLATFORM_MILOS_H__
> +#define __IRIS_PLATFORM_MILOS_H__
> +
> +#define MILOS_V1_MAX_BITRATE 100000000
> +#define MILOS_V1_MAX_FPS 240
> +
> +static struct iris_fmt platform_fmts_milos_dec[] = {
> + [IRIS_FMT_H264] = {
> + .pixfmt = V4L2_PIX_FMT_H264,
> + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> + },
> + [IRIS_FMT_HEVC] = {
> + .pixfmt = V4L2_PIX_FMT_HEVC,
> + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> + },
> + [IRIS_FMT_VP9] = {
> + .pixfmt = V4L2_PIX_FMT_VP9,
> + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE,
> + },
> +};
> +
> +static const struct platform_inst_fw_cap inst_fw_cap_milos_dec[] = {
> + {
> + .cap_id = PROFILE_H264,
> + .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> + .max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
> + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
> + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
> + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) |
> + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH),
> + .value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
> + .hfi_id = HFI_PROP_PROFILE,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_u32_enum,
> + },
> + {
> + .cap_id = PROFILE_HEVC,
> + .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> + .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
> + .value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> + .hfi_id = HFI_PROP_PROFILE,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_u32_enum,
> + },
> + {
> + .cap_id = PROFILE_VP9,
> + .min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
> + .max = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0) |
> + BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_2),
> + .value = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
> + .hfi_id = HFI_PROP_PROFILE,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_u32_enum,
> + },
> + {
> + .cap_id = LEVEL_H264,
> + .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
> + .max = V4L2_MPEG_VIDEO_H264_LEVEL_5_1,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
> + .value = V4L2_MPEG_VIDEO_H264_LEVEL_5_1,
> + .hfi_id = HFI_PROP_LEVEL,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_u32_enum,
> + },
> + {
> + .cap_id = LEVEL_HEVC,
> + .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> + .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5),
> + .value = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
> + .hfi_id = HFI_PROP_LEVEL,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_u32_enum,
> + },
> + {
> + .cap_id = LEVEL_VP9,
> + .min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
> + .max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_0,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) |
> + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) |
> + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) |
> + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) |
> + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) |
> + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) |
> + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) |
> + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1) |
> + BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_5_0),
> + .value = V4L2_MPEG_VIDEO_VP9_LEVEL_5_0,
> + .hfi_id = HFI_PROP_LEVEL,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_u32_enum,
> + },
> + {
> + .cap_id = TIER,
> + .min = V4L2_MPEG_VIDEO_HEVC_TIER_MAIN,
> + .max = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH),
> + .value = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
> + .hfi_id = HFI_PROP_TIER,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_u32_enum,
> + },
> + {
> + .cap_id = INPUT_BUF_HOST_MAX_COUNT,
> + .min = DEFAULT_MAX_HOST_BUF_COUNT,
> + .max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
> + .step_or_mask = 1,
> + .value = DEFAULT_MAX_HOST_BUF_COUNT,
> + .hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
> + .flags = CAP_FLAG_INPUT_PORT,
> + .set = iris_set_u32,
> + },
> + {
> + .cap_id = STAGE,
> + .min = STAGE_1,
> + .max = STAGE_2,
> + .step_or_mask = 1,
> + .value = STAGE_2,
> + .hfi_id = HFI_PROP_STAGE,
> + .set = iris_set_stage,
> + },
> + {
> + .cap_id = PIPE,
> + /* .max, .min and .value are set via platform data */
> + .step_or_mask = 1,
> + .hfi_id = HFI_PROP_PIPE,
> + .set = iris_set_pipe,
> + },
> + {
> + .cap_id = POC,
> + .min = 0,
> + .max = 2,
> + .step_or_mask = 1,
> + .value = 1,
> + .hfi_id = HFI_PROP_PIC_ORDER_CNT_TYPE,
> + },
> + {
> + .cap_id = CODED_FRAMES,
> + .min = CODED_FRAMES_PROGRESSIVE,
> + .max = CODED_FRAMES_PROGRESSIVE,
> + .step_or_mask = 0,
> + .value = CODED_FRAMES_PROGRESSIVE,
> + .hfi_id = HFI_PROP_CODED_FRAMES,
> + },
> + {
> + .cap_id = BIT_DEPTH,
> + .min = BIT_DEPTH_8,
> + .max = BIT_DEPTH_8,
> + .step_or_mask = 1,
> + .value = BIT_DEPTH_8,
> + .hfi_id = HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
> + },
> + {
> + .cap_id = RAP_FRAME,
> + .min = 0,
> + .max = 1,
> + .step_or_mask = 1,
> + .value = 1,
> + .hfi_id = HFI_PROP_DEC_START_FROM_RAP_FRAME,
> + .flags = CAP_FLAG_INPUT_PORT,
> + .set = iris_set_u32,
> + },
> +};
> +
> +static const struct platform_inst_fw_cap inst_fw_cap_milos_enc[] = {
> + {
> + .cap_id = PROFILE_H264,
> + .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> + .max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
> + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) |
> + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
> + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
> + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH),
> + .value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
> + .hfi_id = HFI_PROP_PROFILE,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_profile,
> + },
> + {
> + .cap_id = PROFILE_HEVC,
> + .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> + .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10),
> + .value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> + .hfi_id = HFI_PROP_PROFILE,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_profile,
> + },
> + {
> + .cap_id = LEVEL_H264,
> + .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
> + .max = V4L2_MPEG_VIDEO_H264_LEVEL_5_1,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1),
> + .value = V4L2_MPEG_VIDEO_H264_LEVEL_5_0,
> + .hfi_id = HFI_PROP_LEVEL,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_level,
> + },
> + {
> + .cap_id = LEVEL_HEVC,
> + .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> + .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5),
> + .value = V4L2_MPEG_VIDEO_HEVC_LEVEL_5,
> + .hfi_id = HFI_PROP_LEVEL,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_level,
> + },
> + {
> + .cap_id = STAGE,
> + .min = STAGE_1,
> + .max = STAGE_2,
> + .step_or_mask = 1,
> + .value = STAGE_2,
> + .hfi_id = HFI_PROP_STAGE,
> + .set = iris_set_stage,
> + },
> + {
> + .cap_id = HEADER_MODE,
> + .min = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
> + .max = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) |
> + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME),
> + .value = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
> + .hfi_id = HFI_PROP_SEQ_HEADER_MODE,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_header_mode_gen2,
> + },
> + {
> + .cap_id = PREPEND_SPSPPS_TO_IDR,
> + .min = 0,
> + .max = 1,
> + .step_or_mask = 1,
> + .value = 0,
> + },
> + {
> + .cap_id = BITRATE,
> + .min = 1,
> + .max = MILOS_V1_MAX_BITRATE,
> + .step_or_mask = 1,
> + .value = BITRATE_DEFAULT,
> + .hfi_id = HFI_PROP_TOTAL_BITRATE,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> + CAP_FLAG_DYNAMIC_ALLOWED,
> + .set = iris_set_bitrate,
> + },
> + {
> + .cap_id = BITRATE_PEAK,
> + .min = 1,
> + .max = MILOS_V1_MAX_BITRATE,
> + .step_or_mask = 1,
> + .value = BITRATE_DEFAULT,
> + .hfi_id = HFI_PROP_TOTAL_PEAK_BITRATE,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> + CAP_FLAG_DYNAMIC_ALLOWED,
> + .set = iris_set_peak_bitrate,
> + },
> + {
> + .cap_id = BITRATE_MODE,
> + .min = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
> + .max = V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) |
> + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR),
> + .value = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
> + .hfi_id = HFI_PROP_RATE_CONTROL,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_bitrate_mode_gen2,
> + },
> + {
> + .cap_id = FRAME_SKIP_MODE,
> + .min = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
> + .max = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) |
> + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) |
> + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT),
> + .value = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + },
> + {
> + .cap_id = FRAME_RC_ENABLE,
> + .min = 0,
> + .max = 1,
> + .step_or_mask = 1,
> + .value = 1,
> + },
> + {
> + .cap_id = GOP_SIZE,
> + .min = 0,
> + .max = INT_MAX,
> + .step_or_mask = 1,
> + .value = 2 * DEFAULT_FPS - 1,
> + .hfi_id = HFI_PROP_MAX_GOP_FRAMES,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> + CAP_FLAG_DYNAMIC_ALLOWED,
> + .set = iris_set_u32,
> + },
> + {
> + .cap_id = ENTROPY_MODE,
> + .min = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
> + .max = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) |
> + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC),
> + .value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
> + .hfi_id = HFI_PROP_CABAC_SESSION,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_entropy_mode_gen2,
> + },
> + {
> + .cap_id = MIN_FRAME_QP_H264,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MIN_QP_8BIT,
> + .hfi_id = HFI_PROP_MIN_QP_PACKED,
> + .flags = CAP_FLAG_OUTPUT_PORT,
> + .set = iris_set_min_qp,
> + },
> + {
> + .cap_id = MIN_FRAME_QP_HEVC,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MIN_QP_8BIT,
> + .hfi_id = HFI_PROP_MIN_QP_PACKED,
> + .flags = CAP_FLAG_OUTPUT_PORT,
> + .set = iris_set_min_qp,
> + },
> + {
> + .cap_id = MAX_FRAME_QP_H264,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MAX_QP,
> + .hfi_id = HFI_PROP_MAX_QP_PACKED,
> + .flags = CAP_FLAG_OUTPUT_PORT,
> + .set = iris_set_max_qp,
> + },
> + {
> + .cap_id = MAX_FRAME_QP_HEVC,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MAX_QP,
> + .hfi_id = HFI_PROP_MAX_QP_PACKED,
> + .flags = CAP_FLAG_OUTPUT_PORT,
> + .set = iris_set_max_qp,
> + },
> + {
> + .cap_id = I_FRAME_MIN_QP_H264,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MIN_QP_8BIT,
> + },
> + {
> + .cap_id = I_FRAME_MIN_QP_HEVC,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MIN_QP_8BIT,
> + },
> + {
> + .cap_id = P_FRAME_MIN_QP_H264,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MIN_QP_8BIT,
> + },
> + {
> + .cap_id = P_FRAME_MIN_QP_HEVC,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MIN_QP_8BIT,
> + },
> + {
> + .cap_id = B_FRAME_MIN_QP_H264,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MIN_QP_8BIT,
> + },
> + {
> + .cap_id = B_FRAME_MIN_QP_HEVC,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MIN_QP_8BIT,
> + },
> + {
> + .cap_id = I_FRAME_MAX_QP_H264,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MAX_QP,
> + },
> + {
> + .cap_id = I_FRAME_MAX_QP_HEVC,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MAX_QP,
> + },
> + {
> + .cap_id = P_FRAME_MAX_QP_H264,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MAX_QP,
> + },
> + {
> + .cap_id = P_FRAME_MAX_QP_HEVC,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MAX_QP,
> + },
> + {
> + .cap_id = B_FRAME_MAX_QP_H264,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MAX_QP,
> + },
> + {
> + .cap_id = B_FRAME_MAX_QP_HEVC,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MAX_QP,
> + },
> + {
> + .cap_id = I_FRAME_QP_H264,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = DEFAULT_QP,
> + .hfi_id = HFI_PROP_QP_PACKED,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> + CAP_FLAG_DYNAMIC_ALLOWED,
> + .set = iris_set_frame_qp,
> + },
> + {
> + .cap_id = I_FRAME_QP_HEVC,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = DEFAULT_QP,
> + .hfi_id = HFI_PROP_QP_PACKED,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> + CAP_FLAG_DYNAMIC_ALLOWED,
> + .set = iris_set_frame_qp,
> + },
> + {
> + .cap_id = P_FRAME_QP_H264,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = DEFAULT_QP,
> + .hfi_id = HFI_PROP_QP_PACKED,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> + CAP_FLAG_DYNAMIC_ALLOWED,
> + .set = iris_set_frame_qp,
> + },
> + {
> + .cap_id = P_FRAME_QP_HEVC,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = DEFAULT_QP,
> + .hfi_id = HFI_PROP_QP_PACKED,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> + CAP_FLAG_DYNAMIC_ALLOWED,
> + .set = iris_set_frame_qp,
> + },
> + {
> + .cap_id = B_FRAME_QP_H264,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = DEFAULT_QP,
> + .hfi_id = HFI_PROP_QP_PACKED,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> + CAP_FLAG_DYNAMIC_ALLOWED,
> + .set = iris_set_frame_qp,
> + },
> + {
> + .cap_id = B_FRAME_QP_HEVC,
> + .min = MIN_QP_8BIT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = DEFAULT_QP,
> + .hfi_id = HFI_PROP_QP_PACKED,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> + CAP_FLAG_DYNAMIC_ALLOWED,
> + .set = iris_set_frame_qp,
> + },
> + {
> + .cap_id = INPUT_BUF_HOST_MAX_COUNT,
> + .min = DEFAULT_MAX_HOST_BUF_COUNT,
> + .max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
> + .step_or_mask = 1,
> + .value = DEFAULT_MAX_HOST_BUF_COUNT,
> + .hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
> + .flags = CAP_FLAG_INPUT_PORT,
> + .set = iris_set_u32,
> + },
> + {
> + .cap_id = OUTPUT_BUF_HOST_MAX_COUNT,
> + .min = DEFAULT_MAX_HOST_BUF_COUNT,
> + .max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
> + .step_or_mask = 1,
> + .value = DEFAULT_MAX_HOST_BUF_COUNT,
> + .hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
> + .flags = CAP_FLAG_OUTPUT_PORT,
> + .set = iris_set_u32,
> + },
> + {
> + .cap_id = ROTATION,
> + .min = 0,
> + .max = 270,
> + .step_or_mask = 90,
> + .value = 0,
> + .hfi_id = HFI_PROP_ROTATION,
> + .flags = CAP_FLAG_OUTPUT_PORT,
> + .set = iris_set_rotation,
> + },
> + {
> + .cap_id = HFLIP,
> + .min = 0,
> + .max = 1,
> + .step_or_mask = 1,
> + .value = 0,
> + .hfi_id = HFI_PROP_FLIP,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> + CAP_FLAG_DYNAMIC_ALLOWED,
> + .set = iris_set_flip,
> + },
> + {
> + .cap_id = VFLIP,
> + .min = 0,
> + .max = 1,
> + .step_or_mask = 1,
> + .value = 0,
> + .hfi_id = HFI_PROP_FLIP,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> + CAP_FLAG_DYNAMIC_ALLOWED,
> + .set = iris_set_flip,
> + },
> + {
> + .cap_id = IR_TYPE,
> + .min = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
> + .max = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
> + .step_or_mask = BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM),
> + .value = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + },
> + {
> + .cap_id = IR_PERIOD,
> + .min = 0,
> + .max = INT_MAX,
> + .step_or_mask = 1,
> + .value = 0,
> + .flags = CAP_FLAG_OUTPUT_PORT |
> + CAP_FLAG_DYNAMIC_ALLOWED,
> + .set = iris_set_ir_period,
> + },
> +};
> +
> +static struct platform_inst_caps platform_inst_cap_milos = {
> + .min_frame_width = 96,
> + .max_frame_width = 4096,
> + .min_frame_height = 96,
> + .max_frame_height = 4096,
> + .max_mbpf = (4096 * 2176) / 256,
> + .mb_cycles_vpp = 200,
> + .mb_cycles_fw = 326389,
> + .mb_cycles_fw_vpp = 44156,
> + .num_comv = 0,
> + .max_frame_rate = MILOS_V1_MAX_FPS,
> + .max_operating_rate = MILOS_V1_MAX_FPS,
> +};
> +
> +static const struct icc_info milos_icc_table[] = {
> + { "cpu-cfg", 1000, 1000 },
> + { "video-mem", 1000, 10000000 },
> +};
> +
> +static const char * const milos_opp_pd_table[] = { "cx", "mx" };
> +
> +static struct ubwc_config_data ubwc_config_milos = {
> + .max_channels = 8,
> + .mal_length = 32,
> + .highest_bank_bit = 15,
> + .bank_swzl_level = 0,
> + .bank_swz2_level = 1,
> + .bank_swz3_level = 1,
> + .bank_spreading = 1,
> +};
> +
> +#endif
> diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
> index ddaacda523ec..ff3f4f1dc2ff 100644
> --- a/drivers/media/platform/qcom/iris/iris_probe.c
> +++ b/drivers/media/platform/qcom/iris/iris_probe.c
> @@ -348,6 +348,10 @@ static const struct dev_pm_ops iris_pm_ops = {
> };
>
> static const struct of_device_id iris_dt_match[] = {
> + {
> + .compatible = "qcom,milos-iris",
> + .data = &milos_data,
> + },
> {
> .compatible = "qcom,qcs8300-iris",
> .data = &qcs8300_data,
>
^ permalink raw reply
* Re: [PATCH v3] dt-bindings: timer: Add SiFive CLINT2
From: Nick Hu @ 2026-04-09 5:33 UTC (permalink / raw)
To: Conor Dooley
Cc: Charles Perry, Daniel Lezcano, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Samuel Holland,
Palmer Dabbelt, Anup Patel, linux-kernel, devicetree, linux-riscv
In-Reply-To: <20260330-relative-hardened-5ce35fe1ef57@spud>
On Tue, Mar 31, 2026 at 12:16 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Thu, Mar 26, 2026 at 01:55:38PM -0700, Charles Perry wrote:
> > On Fri, Mar 21, 2025 at 04:35:06PM +0800, Nick Hu wrote:
> > > Add compatible string and property for the SiFive CLINT v2. The SiFive
> > > CLINT v2 is incompatible with the SiFive CLINT v0 due to differences
> > > in their control methods.
> >
> > Hello Nick,
> >
> > Can you help me understand what is this different control method? I've
> > found that both OpenSBI [1] and U-Boot [2] use the same match data in their
> > clint driver which would indicate that they are compatible.
>
> Hmm, good point. I didn't see that the drivers were not doing anything
> different. I guess really the clintv2 should fall back to the clintv0,
> and the difference in hardware should be elaborated on.
>
> I think I also dropped the ball on sifive,fine-ctr-bits, and that should
> be removed and the counter width determined from the compatible.
> There's no users for that yet I think, and there's no valid users of the
> clintv2 compatible /at all/ so maybe it can just get culled.
>
Thanks for pointing that out, I'll send a patch to remove the
sifive,fine-ctr-bits property.
> >
> > Also, do you know if there's an easy way to tell if a sifive clint is a v0
> > or v2?
> >
> > Thanks,
> > Charles
> >
> > [1]: https://elixir.bootlin.com/opensbi/v1.8.1/source/lib/utils/timer/fdt_timer_mtimer.c#L163
> > [2]: https://elixir.bootlin.com/u-boot/v2026.01/source/drivers/timer/riscv_aclint_timer.c#L86
> >
> > >
> > > Signed-off-by: Nick Hu <nick.hu@sifive.com>
> > > Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> > > ---
> > > - v3 changes:
> > > - Add the reason for the incompatibility between sifive,clint2 and
> > > sifive,clint0.
> > > - v2 changes:
> > > - Don't allow sifive,clint2 by itself. Add '-{}' to the first entry
> > > - Mark the sifive,fine-ctr-bits as the required property when
> > > the compatible includes the sifive,clint2
> > >
> > > .../bindings/timer/sifive,clint.yaml | 22 +++++++++++++++++++
> > > 1 file changed, 22 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > > index 76d83aea4e2b..34684cda8b15 100644
> > > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > > @@ -36,6 +36,12 @@ properties:
> > > - starfive,jh7110-clint # StarFive JH7110
> > > - starfive,jh8100-clint # StarFive JH8100
> > > - const: sifive,clint0 # SiFive CLINT v0 IP block
> > > + - items:
> > > + - {}
> > > + - const: sifive,clint2 # SiFive CLINT v2 IP block
> > > + description:
> > > + SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
> > > + differs from that of sifive,clint0, making them incompatible.
> > > - items:
> > > - enum:
> > > - allwinner,sun20i-d1-clint
> > > @@ -62,6 +68,22 @@ properties:
> > > minItems: 1
> > > maxItems: 4095
> > >
> > > + sifive,fine-ctr-bits:
> > > + maximum: 15
> > > + description: The width in bits of the fine counter.
> > > +
> > > +if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + const: sifive,clint2
> > > +then:
> > > + required:
> > > + - sifive,fine-ctr-bits
> > > +else:
> > > + properties:
> > > + sifive,fine-ctr-bits: false
> > > +
> > > additionalProperties: false
> > >
> > > required:
> > > --
> > > 2.17.1
> > >
> > >
^ permalink raw reply
* Re: [PATCH v3] dt-bindings: timer: Add SiFive CLINT2
From: Nick Hu @ 2026-04-09 5:37 UTC (permalink / raw)
To: Charles Perry
Cc: Daniel Lezcano, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Samuel Holland, Palmer Dabbelt,
Anup Patel, linux-kernel, devicetree, linux-riscv
In-Reply-To: <adZo84i4jfoWZnb2@bby-cbu-swbuild03.eng.microchip.com>
On Wed, Apr 8, 2026 at 10:41 PM Charles Perry
<charles.perry@microchip.com> wrote:
>
> On Wed, Apr 08, 2026 at 02:15:19PM +0800, Nick Hu wrote:
> > On Fri, Mar 27, 2026 at 4:56 AM Charles Perry
> > <charles.perry@microchip.com> wrote:
> > >
> > > On Fri, Mar 21, 2025 at 04:35:06PM +0800, Nick Hu wrote:
> > > > Add compatible string and property for the SiFive CLINT v2. The SiFive
> > > > CLINT v2 is incompatible with the SiFive CLINT v0 due to differences
> > > > in their control methods.
> > >
> > > Hello Nick,
> > >
> > > Can you help me understand what is this different control method? I've
> > > found that both OpenSBI [1] and U-Boot [2] use the same match data in their
> > > clint driver which would indicate that they are compatible.
> > >
> > Sorry for the late reply.
>
> Hello Nick, no worries.
>
> > Unlike v0, v2 requires a write to the mtime register to kick the timer.
>
> A kick once at the beginning or every time a machine timer interrupt fires?
>
A kick once at the beginning
> >
> > > Also, do you know if there's an easy way to tell if a sifive clint is a v0
> > > or v2?
> > >
> > sifive,clint2 introduces additional MMIO registers
>
> Is that the high resolution timers (HRT) mentionned in the description?
>
> And last question, would you happen to know if sifive made a clint v1 that
> does NOT require the mtime kick but does have the HRT?
>
Yes, that's correct.
> I'm trying to figure out what should be the compatible for PIC64-HPSC.
> Some code from a repository called "FSFM" used "sifive,clint1" for the
> compatible. I'm wondering if I should add the clint v1 to this file.
>
> Thanks,
> Charles
>
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sm8750-mtp: Set sufficient voltage for panel nt37801
From: Ayushi Makhija @ 2026-04-09 5:44 UTC (permalink / raw)
To: Bjorn Andersson
Cc: konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, conor+dt,
dmitry.baryshkov, linux-arm-msm, devicetree, linux-kernel,
linux-arm-kernel, quic_rajeevny, quic_vproddut
In-Reply-To: <acVWseivbxLQ_uDM@baldur>
On 3/26/2026 9:28 PM, Bjorn Andersson wrote:
> On Thu, Mar 26, 2026 at 03:06:52PM +0530, Ayushi Makhija wrote:
>> On 3/24/2026 7:34 AM, Bjorn Andersson wrote:
>>> On Mon, Mar 23, 2026 at 03:52:29PM +0530, Ayushi Makhija wrote:
>>>> The NT37801 Sepc V1.0 chapter "5.7.1 Power On Sequence" states
>>>> VDDI=1.65V~1.95V, so set sufficient voltage for panel nt37801.
>>>>
>>>
>>> Please add Fixes: tag.
>>>
>>
>> Hi Bjorn,
>>
>> Sure, will add in new patchset.
>>
>>>> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
>>>
>>> Please start using your oss.qualcomm.com address.
>>>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
>>>> index 3837f6785320..6ba4e69bf377 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
>>>> +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
>>>> @@ -462,7 +462,7 @@ vreg_l11b_1p0: ldo11 {
>>>>
>>>> vreg_l12b_1p8: ldo12 {
>>>> regulator-name = "vreg_l12b_1p8";
>>>> - regulator-min-microvolt = <1200000>;
>>>> + regulator-min-microvolt = <1650000>;
>>>
>>> Are you sure it's not supposed to be 1.8V, given the name of the rail?
>>>
>>> Regards,
>>> Bjorn
>>
>> There was already discussion regarding the minimum voltage for this regulator on sm8550 target
>> on other upstream patch.
>>
>> Link: https://lore.kernel.org/all/aQQdQoCLeKhYtY7W@yuanjiey.ap.qualcomm.com/
>>
>> This values is according to the NT37801 panel sec
>> "The NT37801 Sepc V1.0 chapter "5.7.1 Power On Sequence" states
>> VDDI=1.65V~1.95V."
>>
>
> Yes, so the panel requires 1.65V, so regulator-min-microvolt needs to be
> at least that. But regulator-min-microvolt should account for all the
> consumers of the rail, are there any others?
>
> Which leads me to my question, the people designing the board named the
> rail VREG_L12B_1P8 in the schematics, why didn't they name it
> VREG_L12B_1P65?
>
> Please check all the consumers and make the regulator-min-microvolt work
> for all of them - if that's 1.65V, then your change is good.
>
> Regards,
> Bjorn
Hi Bjorn,
There is only one consumer of VREG_L12B_1P8 rail, i.e. NT37801 panel.
So regulator-min-microvolt as 1.65V should be fine for VREG_L12B_1P8 rail.
Thanks,
Ayushi
^ permalink raw reply
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