* [PATCH 22/35] arm64: dts: qcom: sar2130p: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sar2130p.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
index d65ad0df6865..c4d48f657e5d 100644
--- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
@@ -2417,7 +2417,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sar2130p-pdc", "qcom,pdc";
- reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
+ reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x174000f0 0x0 0x64>;
qcom,pdc-ranges = <0 480 94>,
<94 609 31>,
<125 63 1>,
--
2.53.0
^ permalink raw reply related
* [PATCH 21/35] arm64: dts: qcom: sm6350: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 9f9b9f9af0da..3b78835ca41b 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -2489,7 +2489,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm6350-pdc", "qcom,pdc";
- reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x17c000f0 0x0 0x64>;
+ reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x17c000f0 0x0 0x64>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>,
<125 63 1>, <126 655 12>, <138 139 15>;
#interrupt-cells = <2>;
--
2.53.0
^ permalink raw reply related
* [PATCH 20/35] arm64: dts: qcom: x1e80100: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index 4b0784af4bd3..d8b171fb0fbc 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -6014,7 +6014,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,x1e80100-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
+ reg = <0 0x0b220000 0 0x10000>, <0 0x174000f0 0 0x64>;
qcom,pdc-ranges = <0 480 42>, <42 251 5>,
<47 522 52>, <99 609 32>,
--
2.53.0
^ permalink raw reply related
* [PATCH 19/35] arm64: dts: qcom: sm4450: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm4450.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index d217d922811e..b84dd1a8311b 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -464,7 +464,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm4450-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
+ reg = <0 0x0b220000 0 0x10000>, <0 0x174000f0 0 0x64>;
qcom,pdc-ranges = <0 480 94>, <94 494 31>,
<125 63 1>;
#interrupt-cells = <2>;
--
2.53.0
^ permalink raw reply related
* [PATCH 18/35] arm64: dts: qcom: sm8650: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 357e43b90740..349e19b429f2 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -5987,7 +5987,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8650-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
+ reg = <0 0x0b220000 0 0x10000>, <0 0x174000f0 0 0x64>;
interrupt-parent = <&intc>;
--
2.53.0
^ permalink raw reply related
* [PATCH 17/35] arm64: dts: qcom: sm8550: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index e3f93f4f412d..975382cf4066 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -4222,7 +4222,7 @@ usb_1_dwc3_ss: endpoint {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8550-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
+ reg = <0 0x0b220000 0 0x10000>, <0 0x174000f0 0 0x64>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>,
<125 63 1>, <126 716 12>,
<138 251 5>;
--
2.53.0
^ permalink raw reply related
* [PATCH 16/35] arm64: dts: qcom: sm8450: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 920a2d1c04d0..8aa60aa524a6 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -3728,7 +3728,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8450-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
+ reg = <0 0x0b220000 0 0x10000>, <0 0x174000f0 0 0x64>;
qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
<94 609 31>, <125 63 1>, <126 716 12>;
#interrupt-cells = <2>;
--
2.53.0
^ permalink raw reply related
* [PATCH 15/35] arm64: dts: qcom: sm8350: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 5c8fe213f5e4..a183212b12c2 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3172,7 +3172,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8350-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
+ reg = <0 0x0b220000 0 0x10000>, <0 0x17c000f0 0 0x60>;
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
<59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
<69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
--
2.53.0
^ permalink raw reply related
* [PATCH 14/35] arm64: dts: qcom: sm8250: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index c7dffa440074..e6dfaf47fa41 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -5048,7 +5048,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8250-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
+ reg = <0 0x0b220000 0 0x10000>, <0 0x17c000f0 0 0x60>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>,
<125 63 1>, <126 716 12>;
#interrupt-cells = <2>;
--
2.53.0
^ permalink raw reply related
* [PATCH 13/35] arm64: dts: qcom: sc8280xp: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 706eb1309d3f..2c6e48495d20 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -5095,7 +5095,7 @@ dispcc0: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
+ reg = <0 0x0b220000 0 0x10000>, <0 0x17c000f0 0 0x60>;
qcom,pdc-ranges = <0 480 40>,
<40 140 14>,
<54 263 1>,
--
2.53.0
^ permalink raw reply related
* [PATCH 12/35] arm64: dts: qcom: sm8150: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 97ca5275d740..805fa76e6647 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -4174,7 +4174,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8150-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>;
+ reg = <0 0x0b220000 0 0x10000>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>,
<125 63 1>;
#interrupt-cells = <2>;
--
2.53.0
^ permalink raw reply related
* [PATCH 11/35] arm64: dts: qcom: sc8180x: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 8319d892c6e4..319b93c66107 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -3554,7 +3554,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc8180x-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>;
+ reg = <0 0x0b220000 0 0x10000>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
--
2.53.0
^ permalink raw reply related
* [PATCH 10/35] arm64: dts: qcom: sc7280: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 6079e67ea829..e3c0c876368f 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -5629,7 +5629,7 @@ opp-810000000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>;
+ reg = <0 0x0b220000 0 0x10000>;
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
<55 306 4>, <59 312 3>, <62 374 2>,
<64 434 2>, <66 438 3>, <69 86 1>,
--
2.53.0
^ permalink raw reply related
* [PATCH 09/35] arm64: dts: qcom: sc7180: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 45b9864e3304..52bc7d1aedb2 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3505,7 +3505,7 @@ dispcc: clock-controller@af00000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7180-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>;
+ reg = <0 0x0b220000 0 0x10000>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
--
2.53.0
^ permalink raw reply related
* [PATCH 08/35] arm64: dts: qcom: sdm670: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sdm670.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 746e9deba526..e4dd1fff7444 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -1607,7 +1607,7 @@ usb_1_dwc3: usb@a600000 {
pdc: interrupt-controller@b220000 {
compatible = "qcom,sdm670-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>;
+ reg = <0 0x0b220000 0 0x10000>;
qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
<54 534 24>, <79 559 15>, <94 609 15>,
<115 630 7>;
--
2.53.0
^ permalink raw reply related
* [PATCH 07/35] arm64: dts: qcom: sdm845: Fix PDC reg size to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC reg size was 0x30000, covering three DRV regions. Linux only
needs the APSS DRV region which is a single 0x10000 window. Reduce
the size to 0x10000 to describe only the region actually used.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index bf2f9c04adba..09eec9ae03b0 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -5044,7 +5044,7 @@ dispcc: clock-controller@af00000 {
pdc_intc: interrupt-controller@b220000 {
compatible = "qcom,sdm845-pdc", "qcom,pdc";
- reg = <0 0x0b220000 0 0x30000>;
+ reg = <0 0x0b220000 0 0x10000>;
qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
--
2.53.0
^ permalink raw reply related
* [PATCH 06/35] irqchip/qcom-pdc: Use FIELD_GET() to extract bank index and bit position
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The IRQ_ENABLE_BANK register is a bank of 32-bit words where each bit
represents one PDC pin. The bank index and bit position within the bank
are encoded in the flat pin number as bits [31:5] and [4:0] respectively.
Replace the open-coded division and modulo with FIELD_GET() and GENMASK()
to make the bit extraction self-documenting and consistent with the
FIELD_PREP() style already used in the PDC_VERSION() macro.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
drivers/irqchip/qcom-pdc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index 5e1553334103..638b5d89a141 100644
--- a/drivers/irqchip/qcom-pdc.c
+++ b/drivers/irqchip/qcom-pdc.c
@@ -110,8 +110,8 @@ static void pdc_enable_intr_bank(int pin_out, bool on)
unsigned long enable;
u32 index, mask;
- index = pin_out / 32;
- mask = pin_out % 32;
+ index = FIELD_GET(GENMASK(31, 5), pin_out);
+ mask = FIELD_GET(GENMASK(4, 0), pin_out);
enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
__assign_bit(mask, &enable, on);
--
2.53.0
^ permalink raw reply related
* [PATCH 05/35] irqchip/qcom-pdc: Add PDC_VERSION() macro to describe version register fields
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC hardware version register encodes major, minor and step fields
in byte-sized fields at bits [23:16], [15:8] and [7:0] respectively.
The existing PDC_VERSION_3_2 constant was a bare magic number (0x30200)
with no indication of this encoding.
Add GENMASK-based field definitions for each sub-field and a
PDC_VERSION(maj, min, step) constructor macro using FIELD_PREP, making
the encoding self-documenting. Replace the magic constant with
PDC_VERSION(3, 2, 0).
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
drivers/irqchip/qcom-pdc.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index 734576cdce0c..5e1553334103 100644
--- a/drivers/irqchip/qcom-pdc.c
+++ b/drivers/irqchip/qcom-pdc.c
@@ -3,6 +3,7 @@
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
*/
+#include <linux/bitfield.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
@@ -34,9 +35,16 @@
#define IRQ_i_CFG_TYPE_MASK GENMASK(2, 0)
#define PDC_VERSION_REG 0x1000
+#define PDC_VERSION_MAJOR GENMASK(23, 16)
+#define PDC_VERSION_MINOR GENMASK(15, 8)
+#define PDC_VERSION_STEP GENMASK(7, 0)
+#define PDC_VERSION(maj, min, step) \
+ (FIELD_PREP(PDC_VERSION_MAJOR, (maj)) | \
+ FIELD_PREP(PDC_VERSION_MINOR, (min)) | \
+ FIELD_PREP(PDC_VERSION_STEP, (step)))
/* Notable PDC versions */
-#define PDC_VERSION_3_2 0x30200
+#define PDC_VERSION_3_2 PDC_VERSION(3, 2, 0)
struct pdc_pin_region {
u32 pin_base;
--
2.53.0
^ permalink raw reply related
* [PATCH 04/35] irqchip/qcom-pdc: Replace pdc_version global with a function pointer
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
Now that the two enable paths are separate functions, replace the
pdc_version global with a __pdc_enable_intr function pointer. The
pointer is assigned once at probe time based on the version register,
moving the version comparison out of the interrupt enable/disable hot
path entirely.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
drivers/irqchip/qcom-pdc.c | 13 +++----------
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index 21e2b4b884ee..734576cdce0c 100644
--- a/drivers/irqchip/qcom-pdc.c
+++ b/drivers/irqchip/qcom-pdc.c
@@ -51,7 +51,7 @@ static void __iomem *pdc_base;
static void __iomem *pdc_prev_base;
static struct pdc_pin_region *pdc_region;
static int pdc_region_cnt;
-static unsigned int pdc_version;
+static void (*__pdc_enable_intr)(int pin_out, bool on);
static bool pdc_x1e_quirk;
static void pdc_base_reg_write(void __iomem *base, int reg, u32 i, u32 val)
@@ -123,14 +123,6 @@ static void pdc_enable_intr_cfg(int pin_out, bool on)
pdc_reg_write(IRQ_i_CFG, pin_out, enable);
}
-static void __pdc_enable_intr(int pin_out, bool on)
-{
- if (pdc_version < PDC_VERSION_3_2)
- pdc_enable_intr_bank(pin_out, on);
- else
- pdc_enable_intr_cfg(pin_out, on);
-}
-
static void pdc_enable_intr(struct irq_data *d, bool on)
{
unsigned long flags;
@@ -400,7 +392,8 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare
goto fail;
}
- pdc_version = pdc_reg_read(PDC_VERSION_REG, 0);
+ __pdc_enable_intr = (pdc_reg_read(PDC_VERSION_REG, 0) < PDC_VERSION_3_2) ?
+ pdc_enable_intr_bank : pdc_enable_intr_cfg;
parent_domain = irq_find_host(parent);
if (!parent_domain) {
--
2.53.0
^ permalink raw reply related
* [PATCH 03/35] irqchip/qcom-pdc: Tighten ioremap clamp to single DRV region size
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The QCOM_PDC_SIZE constant (0x30000) was introduced to work around old
sm8150 DTs that described a too-small PDC register region, causing the
driver to silently expand the ioremap to cover three DRV regions. Now
that the preceding DT fixes have corrected all platforms to describe only
the APSS DRV region (0x10000), the oversized clamp is no longer needed.
Replace QCOM_PDC_SIZE with PDC_DRV_SIZE (0x10000) in the clamp so the
minimum mapped size matches a single DRV region. The clamp and warning
are intentionally kept to preserve backward compatibility with any old
DTs that may still describe a smaller region.
While at it, rename PDC_DRV_OFFSET to PDC_DRV_SIZE since the constant
represents the size of a DRV region and is used as both the ioremap
minimum size and the offset to the previous DRV region.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
drivers/irqchip/qcom-pdc.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index a72e32896e64..21e2b4b884ee 100644
--- a/drivers/irqchip/qcom-pdc.c
+++ b/drivers/irqchip/qcom-pdc.c
@@ -21,7 +21,7 @@
#include <linux/types.h>
#define PDC_MAX_GPIO_IRQS 256
-#define PDC_DRV_OFFSET 0x10000
+#define PDC_DRV_SIZE 0x10000
/* Valid only on HW version < 3.2 */
#define IRQ_ENABLE_BANK 0x10
@@ -358,7 +358,6 @@ static int pdc_setup_pin_mapping(struct device_node *np)
return 0;
}
-#define QCOM_PDC_SIZE 0x30000
static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *parent)
{
@@ -372,7 +371,7 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare
if (of_address_to_resource(node, 0, &res))
return -EINVAL;
- res_size = max_t(resource_size_t, resource_size(&res), QCOM_PDC_SIZE);
+ res_size = max_t(resource_size_t, resource_size(&res), PDC_DRV_SIZE);
if (res_size > resource_size(&res))
pr_warn("%pOF: invalid reg size, please fix DT\n", node);
@@ -385,7 +384,7 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare
* region with the expected offset to preserve support for old DTs.
*/
if (of_device_is_compatible(node, "qcom,x1e80100-pdc")) {
- pdc_prev_base = ioremap(res.start - PDC_DRV_OFFSET, IRQ_ENABLE_BANK_MAX);
+ pdc_prev_base = ioremap(res.start - PDC_DRV_SIZE, IRQ_ENABLE_BANK_MAX);
if (!pdc_prev_base) {
pr_err("%pOF: unable to map previous PDC DRV region\n", node);
return -ENXIO;
--
2.53.0
^ permalink raw reply related
* [PATCH 02/35] irqchip/qcom-pdc: Split __pdc_enable_intr() into per-version helpers
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The __pdc_enable_intr() function contains a version branch that selects
between two distinct enable mechanisms: a bank-based IRQ_ENABLE_BANK
register for HW < 3.2, and a per-pin enable bit in IRQ_i_CFG for
HW >= 3.2. These two paths share no code and serve different hardware.
Split them into two focused static functions: pdc_enable_intr_bank()
for HW < 3.2 and pdc_enable_intr_cfg() for HW >= 3.2. No functional
change.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
drivers/irqchip/qcom-pdc.c | 42 +++++++++++++++++++++++---------------
1 file changed, 26 insertions(+), 16 deletions(-)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index 32b77fa93f73..a72e32896e64 100644
--- a/drivers/irqchip/qcom-pdc.c
+++ b/drivers/irqchip/qcom-pdc.c
@@ -97,28 +97,38 @@ static void pdc_x1e_irq_enable_write(u32 bank, u32 enable)
pdc_base_reg_write(base, IRQ_ENABLE_BANK, bank, enable);
}
-static void __pdc_enable_intr(int pin_out, bool on)
+static void pdc_enable_intr_bank(int pin_out, bool on)
{
unsigned long enable;
+ u32 index, mask;
- if (pdc_version < PDC_VERSION_3_2) {
- u32 index, mask;
+ index = pin_out / 32;
+ mask = pin_out % 32;
- index = pin_out / 32;
- mask = pin_out % 32;
+ enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
+ __assign_bit(mask, &enable, on);
- enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
- __assign_bit(mask, &enable, on);
+ if (pdc_x1e_quirk)
+ pdc_x1e_irq_enable_write(index, enable);
+ else
+ pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
+}
- if (pdc_x1e_quirk)
- pdc_x1e_irq_enable_write(index, enable);
- else
- pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
- } else {
- enable = pdc_reg_read(IRQ_i_CFG, pin_out);
- __assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on);
- pdc_reg_write(IRQ_i_CFG, pin_out, enable);
- }
+static void pdc_enable_intr_cfg(int pin_out, bool on)
+{
+ unsigned long enable;
+
+ enable = pdc_reg_read(IRQ_i_CFG, pin_out);
+ __assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on);
+ pdc_reg_write(IRQ_i_CFG, pin_out, enable);
+}
+
+static void __pdc_enable_intr(int pin_out, bool on)
+{
+ if (pdc_version < PDC_VERSION_3_2)
+ pdc_enable_intr_bank(pin_out, on);
+ else
+ pdc_enable_intr_cfg(pin_out, on);
}
static void pdc_enable_intr(struct irq_data *d, bool on)
--
2.53.0
^ permalink raw reply related
* [PATCH 01/35] dt-bindings: qcom,pdc: Tighten reg to single APSS DRV region
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com>
The PDC has multiple DRV regions, each sized 0x10000, where each region
serves a specific client in the system. Linux only needs access to the
APSS DRV region, so the reg property should describe exactly one DRV
region of size 0x10000.
The example was using 0x30000 (three DRV regions) which is incorrect.
Fix it to use 0x10000 to match the single APSS DRV region that the
driver actually maps, consistent with the DT fixes applied across all
platforms in this series.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
.../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
index f9321366cae4..786709f2d13e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
@@ -96,7 +96,7 @@ examples:
pdc: interrupt-controller@b220000 {
compatible = "qcom,sdm845-pdc", "qcom,pdc";
- reg = <0xb220000 0x30000>;
+ reg = <0xb220000 0x10000>;
qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
--
2.53.0
^ permalink raw reply related
* [PATCH 00/35] irqchip/qcom-pdc: Clean up register mapping and DT descriptions
From: Mukesh Ojha @ 2026-04-10 18:40 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree,
Mukesh Ojha
The Qualcomm PDC (Power Domain Controller) hardware exposes multiple DRV
(Driver) regions, each 0x10000 bytes in size, where each region serves a
specific client in the system . Linux only needs access to the APSS DRV
region.
Despite this, the driver was mapping up to 0x30000 bytes (three DRV
regions) via a QCOM_PDC_SIZE clamp introduced as a workaround for old
sm8150 DTs that described a too-small register window. Correspondingly,
most platform DTS files described the PDC reg as 0x30000 in size, and
several also carried a second, entirely unused reg entry pointing at an
unrelated register region that the driver never maps.
This series cleans all of that up in three logical steps:
1. (patches 2-6):
Split __pdc_enable_intr() into two focused per-version helpers
to separate the HW < 3.2 bank-based path from the HW >= 3.2 per-pin
path. Replace the pdc_version global with a function pointer assigned
once at probe time, moving the version check out of the hot path.
Tighten the ioremap clamp from QCOM_PDC_SIZE (0x30000) to PDC_DRV_SIZE
(0x10000) now that the DT fixes below make the workaround unnecessary.
Also add a PDC_VERSION() constructor macro and use FIELD_GET() for bank
index extraction to make the bit encoding self-documenting.
2. (patches 1, 7-28):
All 28 platform DTS files that described the PDC reg window as 0x30000
are corrected to 0x10000, reflecting the single APSS DRV region that
Linux actually maps.
3. (patches 29-35):
Seven platform DTS files (kaanapali, lemans, milos, monaco, sc8280xp,
sdx75, talos) carried a second reg entry pointing at an unrelated
hardware block. The driver only ever calls of_address_to_resource(node,
0, ...) so this second entry was never mapped or accessed. Remove it.
The net result is that every PDC node in the tree now describes exactly
one register region of exactly 0x10000 bytes — the APSS DRV region that
the driver actually uses — and the driver's ioremap clamp matches that
reality.
Mukesh Ojha (35):
dt-bindings: qcom,pdc: Tighten reg to single APSS DRV region
irqchip/qcom-pdc: Split __pdc_enable_intr() into per-version helpers
irqchip/qcom-pdc: Tighten ioremap clamp to single DRV region size
irqchip/qcom-pdc: Replace pdc_version global with a function pointer
irqchip/qcom-pdc: Add PDC_VERSION() macro to describe version register
fields
irqchip/qcom-pdc: Use FIELD_GET() to extract bank index and bit
position
arm64: dts: qcom: sdm845: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sdm670: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sc7180: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sc7280: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sc8180x: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sm8150: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sc8280xp: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sm8250: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sm8350: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sm8450: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sm8550: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sm8650: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sm4450: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: x1e80100: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sm6350: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sar2130p: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: qcs615: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: qcs8300: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sa8775p: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: sdx75: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: milos: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: qdu1000: Fix PDC reg size to single APSS DRV region
arm64: dts: qcom: kaanapali: Drop unused second PDC reg entry
arm64: dts: qcom: lemans: Drop unused second PDC reg entry
arm64: dts: qcom: milos: Drop unused second PDC reg entry
arm64: dts: qcom: monaco: Drop unused second PDC reg entry
arm64: dts: qcom: sc8280xp: Drop unused second PDC reg entry
arm64: dts: qcom: sdx75: Drop unused second PDC reg entry
arm64: dts: qcom: talos: Drop unused second PDC reg entry
.../interrupt-controller/qcom,pdc.yaml | 2 +-
arch/arm64/boot/dts/qcom/hamoa.dtsi | 2 +-
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 3 +-
arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 +-
arch/arm64/boot/dts/qcom/lemans.dtsi | 3 +-
arch/arm64/boot/dts/qcom/milos.dtsi | 3 +-
arch/arm64/boot/dts/qcom/monaco.dtsi | 3 +-
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sar2130p.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm670.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdx75.dtsi | 3 +-
arch/arm64/boot/dts/qcom/sm4450.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +-
arch/arm64/boot/dts/qcom/talos.dtsi | 3 +-
drivers/irqchip/qcom-pdc.c | 56 +++++++++++--------
25 files changed, 57 insertions(+), 53 deletions(-)
--
2.53.0
^ permalink raw reply
* Re: [PATCH v2] dt-binding: leds: publish common bindings under dual license
From: Jacek Anaszewski @ 2026-04-10 18:06 UTC (permalink / raw)
To: Corvin Köhne, linux-kernel
Cc: open list:LED SUBSYSTEM, Pavel Machek,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Corvin Köhne, Ashley Towns, Gergo Koteles, INAGAKI Hiroshi,
Olliver Schinagl, Pavel Machek, Rafał Miłecki,
Roderick Colenbrander, Krzysztof Kozlowski
In-Reply-To: <20260408062942.7128-1-corvin.koehne@gmail.com>
On 4/8/26 8:29 AM, Corvin Köhne wrote:
> From: Corvin Köhne <c.koehne@beckhoff.com>
>
> Changes leds/common.h DT binding header file to be published under GPLv2
> or BSD-2-Clause license terms. This change allows this common LED
> bindings header file to be used in software components as bootloaders
> and OSes that are not published under GPLv2 terms.
>
> All contributors to leds/common.h file in copy.
>
> Cc: Ashley Towns <mail@ashleytowns.id.au>
> Cc: Dan Murphy <dmurphy@ti.com>
> Cc: Gergo Koteles <soyer@irl.hu>
> Cc: INAGAKI Hiroshi <musashino.open@gmail.com>
> Cc: Jacek Anaszewski <jacek.anaszewski@gmail.com>
> Cc: Olliver Schinagl <oliver@schinagl.nl>
> Cc: Pavel Machek <pavel@ucw.cz>
> Cc: Rafał Miłecki <rafal@milecki.pl>
> Cc: Roderick Colenbrander <roderick@gaikai.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> Signed-off-by: Corvin Köhne <c.koehne@beckhoff.com>
> ---
> include/dt-bindings/leds/common.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/dt-bindings/leds/common.h b/include/dt-bindings/leds/common.h
> index 4f017bea0123..b7bafbaf7df3 100644
> --- a/include/dt-bindings/leds/common.h
> +++ b/include/dt-bindings/leds/common.h
> @@ -1,4 +1,4 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
> /*
> * This header provides macros for the common LEDs device tree bindings.
> *
Acked-by: Jacek Anaszewski <jacek.anaszewski@gmail.com>
--
Best regards,
Jacek Anaszewski
^ permalink raw reply
* Re: [PATCH v4 1/2] dt-bindings: hwmon/pmbus: Add Infineon XDP720
From: Conor Dooley @ 2026-04-10 17:57 UTC (permalink / raw)
To: ASHISH YADAV
Cc: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-hwmon, devicetree, linux-kernel, Ashish Yadav
In-Reply-To: <20260410070154.3313-2-Ashish.Yadav@infineon.com>
[-- Attachment #1: Type: text/plain, Size: 329 bytes --]
On Fri, Apr 10, 2026 at 12:31:53PM +0530, ASHISH YADAV wrote:
> From: Ashish Yadav <ashish.yadav@infineon.com>
>
> Add documentation for the device tree binding of the XDP720 eFuse.
>
> Signed-off-by: Ashish Yadav <ashish.yadav@infineon.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox