* Re: [PATCH v1 1/4] arm64: dts: qcom: Enable secondary mi2s
From: Konrad Dybcio @ 2026-04-14 11:58 UTC (permalink / raw)
To: Kumar Anurag, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Srinivas Kandagatla,
Liam Girdwood, Mark Brown, Jaroslav Kysela, Takashi Iwai
Cc: linux-arm-msm, devicetree, linux-kernel, linux-sound
In-Reply-To: <20260413091937.134469-2-kumar.singh@oss.qualcomm.com>
On 4/13/26 11:19 AM, Kumar Anurag wrote:
> Enable secondary mi2s to support HDMI audio.
>
> Signed-off-by: Kumar Anurag <kumar.singh@oss.qualcomm.com>
> ---
[...]
> +&mi2s1_data0 {
> + drive-strength = <8>;
> + bias-disable;
> +};
> +
> +&mi2s1_mclk {
> + drive-strength = <8>;
> + bias-disable;
> + output-high;
> +};
> +
> +&mi2s1_sclk {
> + drive-strength = <8>;
> + bias-disable;
> + output-high;
> +};
> +
> +&mi2s1_ws {
> + drive-strength = <8>;
> + bias-disable;
> + output-high;
For these pins in their "mission mode" function, do we expect these
pincfg settings to ever change (i.e. across boards, will the drive-strength/
bias/output properties differ?)
Konrad
^ permalink raw reply
* Re: [PATCH v3 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions
From: Konrad Dybcio @ 2026-04-14 11:53 UTC (permalink / raw)
To: jsandom, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260409-rb5gen2-dts-v3-1-be736355d4b4@axon.com>
On 4/9/26 5:26 PM, Joe Sandom via B4 Relay wrote:
> From: Joe Sandom <jsandom@axon.com>
>
> Add the MHI register regions to the pcie0 and pcie1 controller nodes
> to expose link power state transition counters (L0s/L1/L1.1/L1.2/L2)
> via debugfs. The PCIe host driver uses this region to read the
> link_transition_count from the MHI registers.
>
> Signed-off-by: Joe Sandom <jsandom@axon.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* [PATCH 3/3] arm64: dts: mediatek: mt8395-genio-common: add MT6360 PMIC supplies
From: Louis-Alexis Eyraud @ 2026-04-14 11:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Liam Girdwood, Mark Brown, Gene Chen
Cc: kernel, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Louis-Alexis Eyraud
In-Reply-To: <20260414-mtk-g1200-pmic-cleanup-v1-0-2a7193ed4e93@collabora.com>
The Mediatek Genio 1200-EVK board has a MT6360 PMIC, powered by the
board system power rail (VSYS) and an additional system power rail
(VSYS_BUCK).
In the board devicetree, the power supply inputs for its buck and ldo
regulators are either incorrect (LDO_VIN3) or missing (LDO_VIN1/2,
BUCK_VIN1/2).
So, add VSYS_BUCK regulator node and the proper supply inputs for this
PMIC.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi
index 01e153137a6f..21dbcabe5e72 100644
--- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi
@@ -209,6 +209,14 @@ reg_vsys: regulator-vsys {
regulator-always-on;
regulator-boot-on;
};
+
+ reg_vsys_buck: regulator-vsys-buck {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_buck";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_vsys>;
+ };
};
&adsp {
@@ -486,7 +494,11 @@ otg_vbus_regulator: usb-otg-vbus-regulator {
regulator {
compatible = "mediatek,mt6360-regulator";
- LDO_VIN3-supply = <&mt6360_buck2>;
+ BUCK1_VIN-supply = <®_vsys>;
+ BUCK2_VIN-supply = <®_vsys>;
+ LDO_VIN1-supply = <®_vsys_buck>;
+ LDO_VIN2-supply = <®_vsys_buck>;
+ LDO_VIN3-supply = <®_vsys>;
mt6360_buck1: buck1 {
regulator-name = "emi_vdd2";
--
2.53.0
^ permalink raw reply related
* [PATCH 2/3] arm64: dts: mediatek: mt8395-genio-common: add MT6315 PMIC supplies
From: Louis-Alexis Eyraud @ 2026-04-14 11:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Liam Girdwood, Mark Brown, Gene Chen
Cc: kernel, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Louis-Alexis Eyraud
In-Reply-To: <20260414-mtk-g1200-pmic-cleanup-v1-0-2a7193ed4e93@collabora.com>
Mediatek Genio 1200-EVK board has two MT6315 PMICs, powered by the
board system power rail (VSYS) and connected to the SPMI interface.
Add VSYS regulator node for system power rail and the supply inputs of
these two PMICs.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi
index 62c336e21500..01e153137a6f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi
@@ -201,6 +201,14 @@ wifi_fixed_3v3: regulator-2 {
enable-active-high;
regulator-always-on;
};
+
+ /* system wide 4.2V power rail */
+ reg_vsys: regulator-vsys {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys";
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&adsp {
@@ -1238,6 +1246,11 @@ mt6315_6: pmic@6 {
compatible = "mediatek,mt6315-regulator";
reg = <0x6 SPMI_USID>;
+ pvdd1-supply = <®_vsys>;
+ pvdd2-supply = <®_vsys>;
+ pvdd3-supply = <®_vsys>;
+ pvdd4-supply = <®_vsys>;
+
regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-name = "Vbcpu";
@@ -1254,6 +1267,11 @@ mt6315_7: pmic@7 {
compatible = "mediatek,mt6315-regulator";
reg = <0x7 SPMI_USID>;
+ pvdd1-supply = <®_vsys>;
+ pvdd2-supply = <®_vsys>;
+ pvdd3-supply = <®_vsys>;
+ pvdd4-supply = <®_vsys>;
+
regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-name = "Vgpu";
--
2.53.0
^ permalink raw reply related
* [PATCH 1/3] regulator: dt-bindings: mt6360: add buck regulator supplies
From: Louis-Alexis Eyraud @ 2026-04-14 11:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Liam Girdwood, Mark Brown, Gene Chen
Cc: kernel, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Louis-Alexis Eyraud
In-Reply-To: <20260414-mtk-g1200-pmic-cleanup-v1-0-2a7193ed4e93@collabora.com>
MT6360 PMIC provides 2 buck and 6 ldo regulators, that have each one a
separate supply.
Currently, the supplies for the ldo regulators are described in the
dt-bindings but the ones for the buck regulators are not.
Add the descriptions for these missing supplies.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml
index 9c879bc3c360..cbb74e8e875d 100644
--- a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml
@@ -17,6 +17,10 @@ properties:
compatible:
const: mediatek,mt6360-regulator
+ BUCK1_VIN-supply:
+ description: Input supply phandle(s) for BUCK1
+ BUCK2_VIN-supply:
+ description: Input supply phandle(s) for BUCK2
LDO_VIN1-supply:
description: Input supply phandle(s) for LDO1/2/3
LDO_VIN2-supply:
--
2.53.0
^ permalink raw reply related
* [PATCH 0/3] Mediatek Genio 1200-EVK: MT6315/MT6360 PMIC regulator supply cleanup
From: Louis-Alexis Eyraud @ 2026-04-14 11:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Liam Girdwood, Mark Brown, Gene Chen
Cc: kernel, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Louis-Alexis Eyraud
This series goal is to cleanup the power supplies of MT6315 and MT6360
PMIC regulators, that are either missing or incorrect in the Mediatek
Genio 1200-EVK board devicetree.
Patch 1 completes the MT6360 dt-bindings by adding the missing power
supply descriptions for its buck regulators, that already handled by
the mt6360 regulator driver.
Patch 2 adds for the board the MT6315 regulator supply properties, that
were added in the dt-bindings by [1].
Patch 3 adds for the board the MT6360 regulator supply properties and
fixes the existing one.
The series has been tested on Genio 1200-EVK board with a kernel based
on linux-next (tag: next-20260410).
[1]: https://lore.kernel.org/linux-mediatek/20260326081050.1115201-1-wenst@chromium.org/
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
Louis-Alexis Eyraud (3):
regulator: dt-bindings: mt6360: add buck regulator supplies
arm64: dts: mediatek: mt8395-genio-common: add MT6315 PMIC supplies
arm64: dts: mediatek: mt8395-genio-common: add MT6360 PMIC supplies
.../bindings/regulator/mt6360-regulator.yaml | 4 +++
.../boot/dts/mediatek/mt8395-genio-common.dtsi | 32 +++++++++++++++++++++-
2 files changed, 35 insertions(+), 1 deletion(-)
---
base-commit: f244905cd8cff7a7249cd3dac8a366e02d61ad4f
change-id: 20260413-mtk-g1200-pmic-cleanup-666643b85b52
Best regards,
--
Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
^ permalink raw reply
* Re: [PATCH v1 4/4] ASoC: qcom: sc8280xp: don't force S16_LE in hw_params fixup
From: Mark Brown @ 2026-04-14 11:40 UTC (permalink / raw)
To: Kumar Anurag
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Srinivas Kandagatla, Liam Girdwood, Jaroslav Kysela,
Takashi Iwai, linux-arm-msm, devicetree, linux-kernel,
linux-sound
In-Reply-To: <20260413091937.134469-5-kumar.singh@oss.qualcomm.com>
[-- Attachment #1: Type: text/plain, Size: 872 bytes --]
On Mon, Apr 13, 2026 at 02:19:37AM -0700, Kumar Anurag wrote:
> The machine driver was unconditionally forcing S16_LE in
> sc8280xp_be_hw_params_fixup(), which prevents links (e.g. HDMI bridges)
> that require 32-bit formats from working. Drop the format override and
> keep only the fixed rate/channels constraints.
> struct snd_interval *channels = hw_param_interval(params,
> SNDRV_PCM_HW_PARAM_CHANNELS);
> - struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
>
> rate->min = rate->max = 48000;
> - snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
This breaks compressed playback, for compressed streams we need to
override the format since the DSP will be converting an input compressed
stream to a PCM one. See 9565c9d53c5b (ASoC: qcom: sc8280xp: explicitly
set S16LE format in sc8280xp_be_hw_params_fixup()).
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH v1 3/4] ASoC: qcom: q6dsp: Update bit format support for secondary i2s
From: Mark Brown @ 2026-04-14 11:38 UTC (permalink / raw)
To: Kumar Anurag
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Srinivas Kandagatla, Liam Girdwood, Jaroslav Kysela,
Takashi Iwai, linux-arm-msm, devicetree, linux-kernel,
linux-sound
In-Reply-To: <20260413091937.134469-4-kumar.singh@oss.qualcomm.com>
[-- Attachment #1: Type: text/plain, Size: 342 bytes --]
On Mon, Apr 13, 2026 at 02:19:36AM -0700, Kumar Anurag wrote:
> Add 32bit for playback and capture over secondary mi2s.
> - .formats = SNDRV_PCM_FMTBIT_S16_LE,
> + .formats = SNDRV_PCM_FMTBIT_S16_LE |
> + SNDRV_PCM_FMTBIT_S24_LE |
> + SNDRV_PCM_FMTBIT_S32_LE,
The commit message said 32 bit but this is both 24 and 32 bit.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* [PATCH v2 7/7] arm64: dts: qcom: hamoa: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:36 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan, Konrad Dybcio
In-Reply-To: <20260414-add-label-to-coresight-device-v2-0-5017d07358f2@oss.qualcomm.com>
Add label properties to TPDM and CTI nodes in the hamoa device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index 051dee076416..f10af9db8bd4 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -6882,6 +6882,7 @@ tpdm@10003000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dcc";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -6939,6 +6940,7 @@ tpdm@1000f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -7077,6 +7079,7 @@ tpdm@10800000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rpdm_mxa";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7096,6 +7099,7 @@ tpdm@1082c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_gcc";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7115,6 +7119,7 @@ tpdm@10841000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_prng";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -7134,6 +7139,7 @@ tpdm@10844000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_lpass";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7177,6 +7183,7 @@ cti@1098b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_cdsp_cscti";
};
tpdm@109d0000 {
@@ -7185,6 +7192,7 @@ tpdm@109d0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_qm";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7205,6 +7213,7 @@ tpdm@10ac0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dl_south_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7225,6 +7234,7 @@ tpdm@10ac1000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dl_south_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7459,6 +7469,7 @@ tpdm@10b09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7478,6 +7489,7 @@ tpdm@10b0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7497,6 +7509,7 @@ tpdm@10b0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7516,6 +7529,7 @@ tpdm@10b0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7535,6 +7549,7 @@ tpdm@10b0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7554,6 +7569,7 @@ tpdm@10b20000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ddr_lpi";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7624,6 +7640,7 @@ tpdm@10c08000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dlmm";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7672,6 +7689,7 @@ tpdm@10c28000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dlct";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7691,6 +7709,7 @@ tpdm@10c29000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7824,6 +7843,7 @@ tpdm@10c38000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7843,6 +7863,7 @@ tpdm@10c39000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_mx";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7939,6 +7960,7 @@ tpdm@10cc1000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_tmess_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -8043,6 +8065,7 @@ tpdm@10d08000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_0";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -8062,6 +8085,7 @@ tpdm@10d09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_1";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -8081,6 +8105,7 @@ tpdm@10d0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_2";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -8100,6 +8125,7 @@ tpdm@10d0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_3";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -8119,6 +8145,7 @@ tpdm@10d0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_4";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -8138,6 +8165,7 @@ tpdm@10d0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_5";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -8157,6 +8185,7 @@ tpdm@10d0e000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_6";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -8176,6 +8205,7 @@ tpdm@10d0f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_7";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
--
2.34.1
^ permalink raw reply related
* [PATCH v2 6/7] arm64: dts: qcom: sm8750: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:36 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan
In-Reply-To: <20260414-add-label-to-coresight-device-v2-0-5017d07358f2@oss.qualcomm.com>
Add label properties to TPDM and CTI nodes in the sm8750 device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 18fb52c14acd..fee7f28e44e4 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -4112,6 +4112,7 @@ tpdm@1000f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_spdm";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -4176,6 +4177,7 @@ tpdm@10800000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_modem_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4256,6 +4258,7 @@ cti@1080b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_mss_qdsp6";
};
tpdm@1082c000 {
@@ -4264,6 +4267,7 @@ tpdm@1082c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_gcc";
qcom,dsb-msrs-num = <32>;
@@ -4282,6 +4286,7 @@ tpdm@10841000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_prng";
qcom,cmb-msrs-num = <32>;
@@ -4300,6 +4305,7 @@ tpdm@1084e000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_mm_bcv";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -4319,6 +4325,7 @@ tpdm@1084f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_mm_lmh";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -4338,6 +4345,7 @@ tpdm@10850000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_mm_dpm";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -4402,6 +4410,7 @@ tpdm@10980000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4490,6 +4499,7 @@ cti@1098b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_cdsp_qdsp";
};
tpdm@109a3000 {
@@ -4498,6 +4508,7 @@ tpdm@109a3000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_pmu";
qcom,cmb-msrs-num = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4517,6 +4528,7 @@ tpdm@109a4000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc";
qcom,cmb-msrs-num = <32>;
@@ -4535,6 +4547,7 @@ tpdm@109a5000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dlmm";
qcom,dsb-msrs-num = <32>;
@@ -4553,6 +4566,7 @@ tpdm@109a6000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_north_dsb";
qcom,dsb-msrs-num = <32>;
@@ -4571,6 +4585,7 @@ tpdm@109a7000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_south_dsb";
qcom,dsb-msrs-num = <32>;
@@ -4589,6 +4604,7 @@ tpdm@109a8000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_cmb0";
qcom,cmb-msrs-num = <32>;
@@ -4607,6 +4623,7 @@ tpdm@109a9000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_cmb1";
qcom,cmb-msrs-num = <32>;
@@ -4625,6 +4642,7 @@ tpdm@109aa000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_cmb2";
qcom,cmb-msrs-num = <32>;
@@ -4776,6 +4794,7 @@ tpdm@109d0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_qm";
qcom,dsb-msrs-num = <32>;
@@ -4909,6 +4928,7 @@ tpdm@10b09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -4928,6 +4948,7 @@ tpdm@10b0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -4947,6 +4968,7 @@ tpdm@10b0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -4966,6 +4988,7 @@ tpdm@10b0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -4985,6 +5008,7 @@ tpdm@10b0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -6801,6 +6825,7 @@ timer {
tpdm-cdsp-llm {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_cdsp_llm";
qcom,cmb-element-bits = <32>;
out-ports {
@@ -6814,6 +6839,7 @@ tpdm_cdsp_llm_out: endpoint {
tpdm-cdsp-llm2 {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_cdsp_llm2";
qcom,cmb-element-bits = <32>;
out-ports {
@@ -6827,6 +6853,7 @@ tpdm_cdsp_llm2_out: endpoint {
tpdm-modem1 {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_modem_1";
qcom,dsb-element-bits = <32>;
out-ports {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 5/7] arm64: dts: qcom: kaanapali: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:36 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan, Konrad Dybcio
In-Reply-To: <20260414-add-label-to-coresight-device-v2-0-5017d07358f2@oss.qualcomm.com>
Add label properties to TPDM nodes in the kaanapali device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 35 +++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 7cc326aa1a1a..0d5714ddef9d 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -4201,6 +4201,7 @@ tpdm@10003000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dcc";
qcom,cmb-element-bits = <32>;
@@ -4256,6 +4257,7 @@ tpdm@1000f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
@@ -4319,6 +4321,7 @@ tpdm@11000000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_modem_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4407,6 +4410,7 @@ tpdm@1102c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_gcc";
qcom,dsb-msrs-num = <32>;
@@ -4425,6 +4429,7 @@ tpdm@11180000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4444,6 +4449,7 @@ tpdm@11183000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp_cmsr1";
qcom,dsb-element-bits = <32>;
qcom,cmb-element-bits = <32>;
@@ -4463,6 +4469,7 @@ tpdm@11184000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp_cmsr2";
qcom,dsb-element-bits = <32>;
qcom,cmb-element-bits = <32>;
@@ -4482,6 +4489,7 @@ tpdm@11185000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp_dpm1";
qcom,cmb-element-bits = <64>;
@@ -4500,6 +4508,7 @@ tpdm@11186000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp_dpm2";
qcom,cmb-element-bits = <64>;
@@ -4619,6 +4628,7 @@ tpdm@111a3000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_pmu";
qcom,dsb-msrs-num = <32>;
@@ -4637,6 +4647,7 @@ tpdm@111a4000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_qrng";
out-ports {
port {
@@ -4653,6 +4664,7 @@ tpdm@111a5000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dlmm";
qcom,dsb-msrs-num = <32>;
@@ -4671,6 +4683,7 @@ tpdm@111a6000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_north_dsb";
qcom,dsb-msrs-num = <32>;
@@ -4689,6 +4702,7 @@ tpdm@111a7000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_south_dsb";
qcom,dsb-msrs-num = <32>;
@@ -4707,6 +4721,7 @@ tpdm@111a8000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_cx";
out-ports {
port {
@@ -4723,6 +4738,7 @@ tpdm@111a9000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_mxa";
out-ports {
port {
@@ -4739,6 +4755,7 @@ tpdm@111aa000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_mxc";
out-ports {
port {
@@ -4755,6 +4772,7 @@ tpdm@111ab000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc_cmb0";
out-ports {
port {
@@ -4771,6 +4789,7 @@ tpdm@111ac000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc_cmb1";
out-ports {
port {
@@ -4787,6 +4806,7 @@ tpdm@111ad000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc_cmb2";
out-ports {
port {
@@ -4803,6 +4823,7 @@ tpdm@111ae000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc_cmb3";
out-ports {
port {
@@ -4819,6 +4840,7 @@ tpdm@111af000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc_cmb4";
out-ports {
port {
@@ -4835,6 +4857,7 @@ tpdm@111b3000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_pcie_rscc";
out-ports {
port {
@@ -5024,6 +5047,7 @@ tpdm@111d0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_qm";
out-ports {
port {
@@ -5040,6 +5064,7 @@ tpdm@11303000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_4";
qcom,cmb-element-bits = <64>;
@@ -5181,6 +5206,7 @@ tpdm@11309000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
@@ -5199,6 +5225,7 @@ tpdm@1130a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
@@ -5217,6 +5244,7 @@ tpdm@1130b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
@@ -5235,6 +5263,7 @@ tpdm@1130c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
@@ -5253,6 +5282,7 @@ tpdm@1130d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -5272,6 +5302,7 @@ tpdm@11422000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipa";
qcom,dsb-msrs-num = <32>;
@@ -6958,6 +6989,7 @@ timer {
tpdm-cdsp-llm {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_cdsp_llm";
qcom,cmb-element-bits = <32>;
out-ports {
@@ -6971,6 +7003,7 @@ tpdm_cdsp_llm_out: endpoint {
tpdm-cdsp-llm2 {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_cdsp_llm2";
qcom,cmb-element-bits = <32>;
out-ports {
@@ -6984,6 +7017,7 @@ tpdm_cdsp_llm2_out: endpoint {
tpdm-modem1 {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_modem_1";
qcom,cmb-element-bits = <32>;
out-ports {
@@ -6997,6 +7031,7 @@ tpdm_modem1_out: endpoint {
tpdm-modem2 {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_modem_2";
qcom,cmb-element-bits = <64>;
out-ports {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 4/7] arm64: dts: qcom: kodiak: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:36 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan, Konrad Dybcio
In-Reply-To: <20260414-add-label-to-coresight-device-v2-0-5017d07358f2@oss.qualcomm.com>
Add label properties to TPDM and CTI nodes in the kodiak device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 988ca5f7c8a0..3a2c28752e31 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -3513,6 +3513,7 @@ tpdm@600f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3532,6 +3533,7 @@ cti@6010000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss";
};
funnel@6041000 {
@@ -3681,6 +3683,7 @@ cti@6b00000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao";
};
cti@6b01000 {
@@ -3689,6 +3692,7 @@ cti@6b01000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao_1";
};
cti@6b02000 {
@@ -3697,6 +3701,7 @@ cti@6b02000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao_2";
};
cti@6b03000 {
@@ -3705,6 +3710,7 @@ cti@6b03000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao_3";
};
funnel@6b04000 {
@@ -3859,6 +3865,7 @@ tpdm@6b09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3878,6 +3885,7 @@ tpdm@6b0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3897,6 +3905,7 @@ tpdm@6b0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3916,6 +3925,7 @@ tpdm@6b0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3935,6 +3945,7 @@ tpdm@6b0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3954,6 +3965,7 @@ cti@6b11000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_aoss";
};
etm@7040000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 2/7] arm64: dts: qcom: talos: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:36 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan, Konrad Dybcio
In-Reply-To: <20260414-add-label-to-coresight-device-v2-0-5017d07358f2@oss.qualcomm.com>
Add label properties to CTI and TPDM nodes in the talos device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/talos.dtsi | 59 +++++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index ff5afbfce2a4..019911f3f923 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -2180,6 +2180,7 @@ cti@6010000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss";
};
cti@6011000 {
@@ -2188,6 +2189,7 @@ cti@6011000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_1";
};
cti@6012000 {
@@ -2196,6 +2198,7 @@ cti@6012000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_2";
};
cti@6013000 {
@@ -2204,6 +2207,7 @@ cti@6013000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_3";
};
cti@6014000 {
@@ -2212,6 +2216,7 @@ cti@6014000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_4";
};
cti@6015000 {
@@ -2220,6 +2225,7 @@ cti@6015000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_5";
};
cti@6016000 {
@@ -2228,6 +2234,7 @@ cti@6016000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_6";
};
cti@6017000 {
@@ -2236,6 +2243,7 @@ cti@6017000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_7";
};
cti@6018000 {
@@ -2244,6 +2252,7 @@ cti@6018000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_8";
};
cti@6019000 {
@@ -2252,6 +2261,7 @@ cti@6019000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_9";
};
cti@601a000 {
@@ -2260,6 +2270,7 @@ cti@601a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_10";
};
cti@601b000 {
@@ -2268,6 +2279,7 @@ cti@601b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_11";
};
cti@601c000 {
@@ -2276,6 +2288,7 @@ cti@601c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_12";
};
cti@601d000 {
@@ -2284,6 +2297,7 @@ cti@601d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_13";
};
cti@601e000 {
@@ -2292,6 +2306,7 @@ cti@601e000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_14";
};
cti@601f000 {
@@ -2300,6 +2315,7 @@ cti@601f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_15";
};
funnel@6041000 {
@@ -2532,6 +2548,7 @@ cti@683b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdsp6";
};
tpdm@6840000 {
@@ -2540,6 +2557,7 @@ tpdm@6840000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_vsense";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -2560,6 +2578,7 @@ tpdm@684c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_prng";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -2579,6 +2598,7 @@ tpdm@6850000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_pimem";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -2600,6 +2620,7 @@ tpdm@6860000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -2643,6 +2664,7 @@ cti@6867000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_cdsp";
};
tpdm@6870000 {
@@ -2651,6 +2673,7 @@ tpdm@6870000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dcc";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -2671,6 +2694,7 @@ tpdm@699c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_wcss";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -2693,6 +2717,7 @@ tpdm@69c0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_monaq";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -2736,6 +2761,7 @@ tpdm@69d0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_qm";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -2756,6 +2782,7 @@ tpdm@6a00000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ddr";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -2776,6 +2803,7 @@ cti@6a02000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_ddr_dl0";
};
cti@6a03000 {
@@ -2784,6 +2812,7 @@ cti@6a03000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_ddr_dl0_1";
};
cti@6a10000 {
@@ -2792,6 +2821,7 @@ cti@6a10000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_ddr_dl1";
};
cti@6a11000 {
@@ -2800,6 +2830,7 @@ cti@6a11000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_ddr_dl1_1";
};
funnel@6a05000 {
@@ -2870,6 +2901,7 @@ tpdm@6b02000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -2890,6 +2922,7 @@ tpdm@6b03000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -2910,6 +2943,7 @@ cti@6b04000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao";
};
cti@6b05000 {
@@ -2918,6 +2952,7 @@ cti@6b05000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao_1";
};
cti@6b06000 {
@@ -2926,6 +2961,7 @@ cti@6b06000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao_2";
};
cti@6b07000 {
@@ -2934,6 +2970,7 @@ cti@6b07000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao_3";
};
funnel@6b08000 {
@@ -3040,6 +3077,7 @@ cti@6b21000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_aop_m3";
};
tpdm@6b48000 {
@@ -3048,6 +3086,7 @@ tpdm@6b48000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_west";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3067,6 +3106,7 @@ cti@6c13000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_titan";
/* Not all required clocks can be enabled from the OS */
status = "fail";
@@ -3078,6 +3118,7 @@ cti@6c20000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_venus";
status = "disabled";
};
@@ -3087,6 +3128,7 @@ tpdm@6c28000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_center";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3106,6 +3148,7 @@ cti@6c29000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_dlct";
};
cti@6c2a000 {
@@ -3114,6 +3157,7 @@ cti@6c2a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_dlct_1";
};
cti@7020000 {
@@ -3122,6 +3166,7 @@ cti@7020000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_2";
};
etm@7040000 {
@@ -3150,6 +3195,7 @@ cti@7120000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_3";
};
etm@7140000 {
@@ -3178,6 +3224,7 @@ cti@7220000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_4";
};
etm@7240000 {
@@ -3206,6 +3253,7 @@ cti@7320000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_5";
};
etm@7340000 {
@@ -3234,6 +3282,7 @@ cti@7420000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_6";
};
etm@7440000 {
@@ -3262,6 +3311,7 @@ cti@7520000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_7";
};
etm@7540000 {
@@ -3290,6 +3340,7 @@ cti@7620000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_8";
};
etm@7640000 {
@@ -3318,6 +3369,7 @@ cti@7720000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_9";
};
etm@7740000 {
@@ -3492,6 +3544,7 @@ tpdm@7830000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_olc";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3535,6 +3588,7 @@ tpdm@7860000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_apss";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3578,6 +3632,7 @@ tpdm@78a0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llm_silver";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3597,6 +3652,7 @@ tpdm@78b0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llm_gold";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3664,6 +3720,7 @@ cti@78e0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss";
};
cti@78f0000 {
@@ -3672,6 +3729,7 @@ cti@78f0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_1";
};
cti@7900000 {
@@ -3680,6 +3738,7 @@ cti@7900000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_2";
};
remoteproc_cdsp: remoteproc@8300000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 3/7] arm64: dts: qcom: monaco: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:36 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan, Konrad Dybcio
In-Reply-To: <20260414-add-label-to-coresight-device-v2-0-5017d07358f2@oss.qualcomm.com>
Add label properties to TPDM and CTI nodes in the monaco device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/monaco.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 7b1d57460f1e..3e076a1df1b9 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -3045,6 +3045,7 @@ tpdm@400f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3307,6 +3308,7 @@ tpdm@4841000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_prng";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3326,6 +3328,7 @@ tpdm@4850000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_pimem";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3347,6 +3350,7 @@ tpdm@4860000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dl_ch_south";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3440,6 +3444,7 @@ tpdm@4980000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3483,6 +3488,7 @@ tpdm@4ac0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_mmnoc_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3555,6 +3561,7 @@ tpdm@4ad0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dlct";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3807,6 +3814,7 @@ tpdm@4b09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3826,6 +3834,7 @@ tpdm@4b0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3845,6 +3854,7 @@ tpdm@4b0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3864,6 +3874,7 @@ tpdm@4b0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3883,6 +3894,7 @@ tpdm@4b0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3902,6 +3914,7 @@ cti@4b13000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_aoss";
};
tpdm@4b80000 {
@@ -3910,6 +3923,7 @@ tpdm@4b80000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3977,6 +3991,7 @@ cti@4b8b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_cdsp_1";
};
tpdm@4c40000 {
@@ -3985,6 +4000,7 @@ tpdm@4c40000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_gpdsp_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4078,6 +4094,7 @@ tpdm@4c50000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dl_south";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4150,6 +4167,7 @@ tpdm@4e00000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ddr";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4240,6 +4258,7 @@ tpdm@4e10000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ddr_ch0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4283,6 +4302,7 @@ tpdm@4e20000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ddr_ch1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4608,6 +4628,7 @@ cti@682b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss";
};
tpdm@6860000 {
@@ -4616,6 +4637,7 @@ tpdm@6860000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_actpm";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -4635,6 +4657,7 @@ tpdm@6861000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_apss";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4715,6 +4738,7 @@ tpdm@68a0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llm_gold";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -4734,6 +4758,7 @@ tpdm@68b0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llm_silver";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -4753,6 +4778,7 @@ tpdm@68c0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ext_dsb";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4772,6 +4798,7 @@ cti@68e0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_llm_gold";
};
cti@68f0000 {
@@ -4780,6 +4807,7 @@ cti@68f0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_llm_silver";
};
cti@6900000 {
@@ -4788,6 +4816,7 @@ cti@6900000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_ext_dsb";
};
sdhc_1: mmc@87c4000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 1/7] arm64: dts: qcom: lemans: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:35 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan, Konrad Dybcio
In-Reply-To: <20260414-add-label-to-coresight-device-v2-0-5017d07358f2@oss.qualcomm.com>
Add label properties to TPDM and CTI nodes in the lemans device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index fe6e76351823..7cdca20708cc 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -2847,6 +2847,7 @@ tpdm@4003000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dcc";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -2906,6 +2907,7 @@ tpdm@400f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3374,6 +3376,7 @@ tpdm@4b09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3394,6 +3397,7 @@ tpdm@4b0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3414,6 +3418,7 @@ tpdm@4b0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3434,6 +3439,7 @@ tpdm@4b0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3454,6 +3460,7 @@ tpdm@4b0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3474,6 +3481,7 @@ aoss_cti: cti@4b13000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_aoss";
};
funnel@4b83000 {
@@ -3795,6 +3803,7 @@ tpdm@6860000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_actpm";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3815,6 +3824,7 @@ tpdm@6861000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_apss";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3897,6 +3907,7 @@ tpdm@68a0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llm_silver";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3917,6 +3928,7 @@ tpdm@68b0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llm_gold";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3937,6 +3949,7 @@ tpdm@68c0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llm_ext";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -8590,6 +8603,7 @@ arch_timer: timer {
turing-llm-tpdm {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_cdsp_llm_0";
qcom,cmb-element-bits = <32>;
--
2.34.1
^ permalink raw reply related
* [PATCH v2 0/7] arm64: dts: qcom: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:35 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan, Konrad Dybcio
The CoreSight framework and userspace tools identify trace devices by
their base address, which is not human-readable. The label property
provides a stable, descriptive name for each TPDM and CTI device,
allowing tools to refer to devices by name rather than address.
This series adds label properties to TPDM and CTI nodes across seven
Qualcomm platforms:
lemans
talos
monaco
kodiak
kaanapali
sm8750
hamoa
With the change, we will have a sysfs node for each Coresight device:
root@qemuarm64:/sys/bus/coresight/devices/tpdm0# cat label
tpdm_spdm
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Changes in v2:
- fix the extra tab format issue in patch 6 (sm8750).
- Link to v1: https://lore.kernel.org/r/20260410-add-label-to-coresight-device-v1-0-d71a6759dbc2@oss.qualcomm.com
---
Jie Gan (7):
arm64: dts: qcom: lemans: Add label properties to CoreSight devices
arm64: dts: qcom: talos: Add label properties to CoreSight devices
arm64: dts: qcom: monaco: Add label properties to CoreSight devices
arm64: dts: qcom: kodiak: Add label properties to CoreSight devices
arm64: dts: qcom: kaanapali: Add label properties to CoreSight devices
arm64: dts: qcom: sm8750: Add label properties to CoreSight devices
arm64: dts: qcom: hamoa: Add label properties to CoreSight devices
arch/arm64/boot/dts/qcom/hamoa.dtsi | 30 +++++++++++++++++
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 35 +++++++++++++++++++
arch/arm64/boot/dts/qcom/kodiak.dtsi | 12 +++++++
arch/arm64/boot/dts/qcom/lemans.dtsi | 14 ++++++++
arch/arm64/boot/dts/qcom/monaco.dtsi | 29 ++++++++++++++++
arch/arm64/boot/dts/qcom/sm8750.dtsi | 27 +++++++++++++++
arch/arm64/boot/dts/qcom/talos.dtsi | 59 +++++++++++++++++++++++++++++++++
7 files changed, 206 insertions(+)
---
base-commit: f3e6330d7fe42b204af05a2dbc68b379e0ad179e
change-id: 20260409-add-label-to-coresight-device-b17a2ba6030e
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH 6/7] arm64: dts: qcom: sm8750: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:29 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <6187fa72-d14c-40a1-bc03-ba43860d0e27@oss.qualcomm.com>
On 4/14/2026 6:19 PM, Konrad Dybcio wrote:
> On 4/10/26 5:08 AM, Jie Gan wrote:
>> Add label properties to TPDM and CTI nodes in the sm8750 device tree to
>> provide human-readable identifiers for each CoreSight device. These
>> labels allow userspace tools and the CoreSight framework to identify
>> devices by name rather than by base address.
>>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>
> [...]
>
>> tpdm-cdsp-llm {
>> compatible = "qcom,coresight-static-tpdm";
>> + label = "tpdm_cdsp_llm";
>> qcom,cmb-element-bits = <32>;
>>
>> out-ports {
>> @@ -6814,6 +6839,7 @@ tpdm_cdsp_llm_out: endpoint {
>>
>> tpdm-cdsp-llm2 {
>> compatible = "qcom,coresight-static-tpdm";
>> + label = "tpdm_cdsp_llm2";
>> qcom,cmb-element-bits = <32>;
>>
>> out-ports {
>> @@ -6827,6 +6853,7 @@ tpdm_cdsp_llm2_out: endpoint {
>>
>> tpdm-modem1 {
>> compatible = "qcom,coresight-static-tpdm";
>> + label = "tpdm_modem_1";
>
> Please fix the extra \t
noted.
Thanks,
Jie
>
> Konrad
^ permalink raw reply
* Re: [PATCH v11 2/4] crypto: spacc - Add SPAcc ahash support
From: Herbert Xu @ 2026-04-14 11:16 UTC (permalink / raw)
To: Pavitrakumar Managutte
Cc: linux-crypto, linux-kernel, devicetree, robh, conor+dt,
Ruud.Derwig, manjunath.hadli, adityak, navami.telsang, bhoomikak
In-Reply-To: <CALxtO0kj4JfL94qY-radGcLwMeTnq4NQF7vPqs6giuhBinvALw@mail.gmail.com>
On Tue, Apr 14, 2026 at 03:58:16PM +0530, Pavitrakumar Managutte wrote:
> Hi Herbert,
> If the above snip looks good, I can push that and some more code
> clean-ups/improvements as part of V12 patchset. Do let me know.
>
> Below are the code fixes and improvements
> 1. Multi-device safety handling - All packed up inside priv
> 2. Minor code polishes
> 3. memzero_explicit inside setkey, spacc_compute_xcbc_key etc.
> 4. Algo registration clean-ups
I would prefer if you left out sm3 for now. If it really mattered
someone would move it to lib/crypto.
Thanks,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH 31/35] arm64: dts: qcom: milos: Drop unused second PDC reg entry
From: Krzysztof Kozlowski @ 2026-04-14 10:57 UTC (permalink / raw)
To: Mukesh Ojha, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree
In-Reply-To: <20260410184124.1068210-32-mukesh.ojha@oss.qualcomm.com>
On 10/04/2026 20:41, Mukesh Ojha wrote:
> The PDC driver only maps the first register region (APSS DRV) via
> of_address_to_resource(node, 0, ...). The second reg entry was never
> accessed by the driver and can be removed.
>
> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/milos.dtsi | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
> index 71941e6f49bf..a3c2ac8ca675 100644
> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
> @@ -1564,8 +1564,7 @@ dispcc: clock-controller@af00000 {
>
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,milos-pdc", "qcom,pdc";
> - reg = <0x0 0x0b220000 0x0 0x10000>,
You already changed this line in previous patch. Fixing one property in
DTS to match hardware is one commit.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 35/35] arm64: dts: qcom: talos: Drop unused second PDC reg entry
From: Krzysztof Kozlowski @ 2026-04-14 10:55 UTC (permalink / raw)
To: Mukesh Ojha, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree
In-Reply-To: <20260410184124.1068210-36-mukesh.ojha@oss.qualcomm.com>
On 10/04/2026 20:41, Mukesh Ojha wrote:
> The PDC driver only maps the first register region (APSS DRV) via
> of_address_to_resource(node, 0, ...). The second reg entry was never
> accessed by the driver and can be removed.
>
> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> ---
Same comment as for other patches like that. This is not a valid reason
or at least not sufficiently explained. Either hardware has it or has
not. Why is driver relevant here? That must be explained in commit msg.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 32/35] arm64: dts: qcom: monaco: Drop unused second PDC reg entry
From: Krzysztof Kozlowski @ 2026-04-14 10:54 UTC (permalink / raw)
To: Mukesh Ojha, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree
In-Reply-To: <20260410184124.1068210-33-mukesh.ojha@oss.qualcomm.com>
On 10/04/2026 20:41, Mukesh Ojha wrote:
> The PDC driver only maps the first register region (APSS DRV) via
> of_address_to_resource(node, 0, ...). The second reg entry was never
> accessed by the driver and can be removed.
This is not a correct reason, see writing bindings.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 1/6] ASoC: renesas: fsi: Add shared SPU clock support
From: Bui Duc Phuc @ 2026-04-14 10:53 UTC (permalink / raw)
To: Kuninori Morimoto
Cc: broonie, lgirdwood, robh, krzk+dt, conor+dt, geert+renesas,
magnus.damm, perex, tiwai, linux-sound, linux-renesas-soc,
devicetree, linux-kernel
In-Reply-To: <87v7dupfx6.wl-kuninori.morimoto.gx@renesas.com>
Hi,
Thanks for the review and explanation.
> You added clk_spu in this patch, but not touched.
> When I checked whole patch-set, you initialize it at [4/6], but [2/6] is
> using it. Maybe it works, but is strange.
You are right, clk_spu is used before being initialized.
I was not careful with the patch ordering and only ensured the series
worked as a whole.
I understand now and will fix the ordering accordingly.
Best regards,
Phuc
^ permalink raw reply
* Re: [PATCH v2 1/2] mmc: dw_mmc: implement option for configuring DMA threshold
From: Kaustabh Chakraborty @ 2026-04-14 10:49 UTC (permalink / raw)
To: Shawn Lin, Kaustabh Chakraborty, Ulf Hansson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jaehoon Chung,
Krzysztof Kozlowski, Alim Akhtar
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-samsung-soc
In-Reply-To: <cec99f99-5ac4-7f0d-8e2a-947edfef8930@rock-chips.com>
On 2026-04-14 16:50 +08:00, Shawn Lin wrote:
> 在 2026/04/14 星期二 16:36, Kaustabh Chakraborty 写道:
>> Some controllers, such as certain Exynos SDIO ones, are unable to
>> perform DMA transfers of small amount of bytes properly. Following the
>> device tree schema, implement the property to define the DMA transfer
>> threshold (from a hard coded value of 16 bytes) so that lesser number of
>> bytes can be transferred safely skipping DMA in such controllers. The
>> value of 16 bytes stays as the default for controllers which do not
>> define it. This value can be overridden by implementation-specific init
>> sequences.
>>
>> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
>> ---
>> drivers/mmc/host/dw_mmc.c | 5 +++--
>> drivers/mmc/host/dw_mmc.h | 2 ++
>> 2 files changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
>> index 20193ee7b73eb..9dd9fed4ccf49 100644
>> --- a/drivers/mmc/host/dw_mmc.c
>> +++ b/drivers/mmc/host/dw_mmc.c
>> @@ -40,7 +40,6 @@
>> SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
>> #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
>> DW_MCI_CMD_ERROR_FLAGS)
>> -#define DW_MCI_DMA_THRESHOLD 16
>>
>> #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
>> #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
>> @@ -821,7 +820,7 @@ static int dw_mci_pre_dma_transfer(struct dw_mci *host,
>> * non-word-aligned buffers or lengths. Also, we don't bother
>> * with all the DMA setup overhead for short transfers.
>> */
>> - if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
>> + if (data->blocks * data->blksz < host->dma_threshold)
>> return -EINVAL;
>>
>> if (data->blksz & 3)
>> @@ -3245,6 +3244,8 @@ int dw_mci_probe(struct dw_mci *host)
>> goto err_clk_ciu;
>> }
>>
>> + host->dma_threshold = 16;
>
> I'd prefer to set it in dw_mci_alloc_host() instead of picking up
> a random place to put it, for better code management.
Okay, that function is in -next I see.
>
>> +
>> if (host->rstc) {
>> reset_control_assert(host->rstc);
>> usleep_range(10, 50);
>> diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
>> index 42e58be74ce09..fc7601fba849f 100644
>> --- a/drivers/mmc/host/dw_mmc.h
>> +++ b/drivers/mmc/host/dw_mmc.h
>> @@ -164,6 +164,8 @@ struct dw_mci {
>> void __iomem *fifo_reg;
>> u32 data_addr_override;
>> bool wm_aligned;
>> + /* Configurable data byte threshold value for DMA transfer. */
>
> No here, there is a long section of comment before struct dw_mci{ } that
> describes each member of it, please add it there.
Ah, you mean the documenting comment. Shouldn't have missed in either
way.
>
>> + u32 dma_threshold;
>>
>> struct scatterlist *sg;
>> struct sg_mapping_iter sg_miter;
>>
^ permalink raw reply
* Re: [PATCH 01/35] dt-bindings: qcom,pdc: Tighten reg to single APSS DRV region
From: Konrad Dybcio @ 2026-04-14 10:47 UTC (permalink / raw)
To: Mukesh Ojha
Cc: Dmitry Baryshkov, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree
In-Reply-To: <20260414082426.fhkgwpjth7a6hzxe@hu-mojha-hyd.qualcomm.com>
On 4/14/26 10:24 AM, Mukesh Ojha wrote:
> On Mon, Apr 13, 2026 at 10:23:59AM +0200, Konrad Dybcio wrote:
>> On 4/11/26 4:32 PM, Dmitry Baryshkov wrote:
>>> On Sat, Apr 11, 2026 at 12:10:38AM +0530, Mukesh Ojha wrote:
>>>> The PDC has multiple DRV regions, each sized 0x10000, where each region
>>>> serves a specific client in the system. Linux only needs access to the
>>>
>>> Nit: there are other OS than Linux. Would you rather point out that
>>> other DRV regions are to be used by ... what?
>>
>> TZ, HYP, HLOS, CPUCP..
>
> Thanks for pitching in..
>
>>
>> I'm wondering if we can make use of the HYP one on e.g. Glymur, to
>> parallelize accesses (and whether that would bring any practical
>> benefit).
>
> I mean, Ideally, It makes sense to utilize extra 0x10000 to use or just
> to use the hypervisor one for Glymur.
Which one does the UEFI use?
Konrad
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: reset: imx8mq: Add _N suffix to IMX8MQ_RESET_MIPI_CSI*_RESET
From: Robby Cai @ 2026-04-14 10:46 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: p.zabel, robh, krzk+dt, conor+dt, Frank.Li, s.hauer, festevam,
devicetree, kernel, imx, linux-arm-kernel, linux-kernel,
aisheng.dong
In-Reply-To: <20260401-simple-dragonfly-of-will-fedc8c@quoll>
On Wed, Apr 01, 2026 at 09:41:48AM +0200, Krzysztof Kozlowski wrote:
> On Tue, Mar 31, 2026 at 06:13:30PM +0800, Robby Cai wrote:
> > The assert logic of the MIPI CSI reset signals is active-low on i.MX8MQ,
> > but the existing names do not indicate this explicitly. To improve
> > consistency and clarity, append the _N suffix to all
> > IMX8MQ_RESET_MIPI_CSI*_RESET definitions. The deprecated
> > IMX8MQ_RESET_MIPI_CSI*_RESET versions remain temporarily for DT ABI
> > compatibility and will be removed at an appropriate time in the future.
> >
> > Signed-off-by: Robby Cai <robby.cai@nxp.com>
> > ---
> > include/dt-bindings/reset/imx8mq-reset.h | 18 ++++++++++++------
> > 1 file changed, 12 insertions(+), 6 deletions(-)
> >
> > diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h
> > index 705870693ec2..83a155dbbd4a 100644
> > --- a/include/dt-bindings/reset/imx8mq-reset.h
> > +++ b/include/dt-bindings/reset/imx8mq-reset.h
> > @@ -46,12 +46,18 @@
> > #define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */
> > #define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */
> > #define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */
> > -#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */
> > -#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */
> > -#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */
> > -#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */
> > -#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */
> > -#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */
> > +#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* Deprecated. Use *_RESET_N instead */
> > +#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET_N 38 /* i.MX8MM/i.MX8MN does NOT support */
>
> That's quite a churn for no need. The entire point of these values being
> the binding is that it describes the ABI for SW and DTS, not your
> hardware registers.
>
> Whether signal is active low or high is kind of irrelevant. Linux uses
> it exactly the same way.
>
The original naming was taken from the reference manual at the time.
The upcoming RM revision will clarify that these resets are active-low and
use the _N suffix, consistent with MIPI DSI.
However, I agree that the DT binding and naming need not be changed.
I'll keep the existing binding and naming, and address this in v2 by fixing the
reset logic in the driver only.
Regards,
Robby
^ permalink raw reply
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