* [PATCH 26/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588-rock-5-itx
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO4_B1 line to control the voltage bias on the
HDMI1 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the HDMI1 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
index f7dd01d6fa0a..1f4c1eb7a8c6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
@@ -347,7 +347,8 @@ &gpu {
&hdmi1 {
pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
- &hdmim1_tx1_scl &hdmim1_tx1_sda>;
+ &hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_frl_en>;
+ frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -696,6 +697,12 @@ &pd_gpu {
};
&pinctrl {
+ hdmi {
+ hdmi1_frl_en: hdmi1-frl-en {
+ rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
hym8563 {
rtc_int: rtc-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.53.0
^ permalink raw reply related
* [PATCH 27/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588-rock-5b-5bp-5t
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO4_B1 and GPIO4_A1 lines to control the voltage
bias on the data lines for the HDMI0 and HDMI1 ports. These lines must
be asserted when operating in HDMI 2.1 FRL mode and deasserted for HDMI
1.4/2.0 TMDS mode.
Wire up both HDMI ports to their respective GPIO lines using the
frl-enable-gpios property to allow adjusting the bias when transitioning
between TMDS and FRL operating modes.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
index bf4a1d2e55ca..924de5a69570 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
@@ -183,6 +183,9 @@ &gpu {
};
&hdmi0 {
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_frl_en>;
+ frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -204,7 +207,8 @@ &hdmi0_sound {
&hdmi1 {
pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
- &hdmim1_tx1_scl &hdmim1_tx1_sda>;
+ &hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_frl_en>;
+ frl-enable-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -505,6 +509,16 @@ &pd_npu {
};
&pinctrl {
+ hdmi {
+ hdmi0_frl_en: hdmi0-frl-en {
+ rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ hdmi1_frl_en: hdmi1-frl-en {
+ rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.53.0
^ permalink raw reply related
* [PATCH 28/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588-tiger
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO0_D3 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts | 3 ++-
arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 9 ++++++++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts
index caa43d1abf17..8401f7bebe86 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts
@@ -173,7 +173,8 @@ &hdmi0 {
* connected on Haikou itself.
*/
pinctrl-names = "default";
- pinctrl-0 = <&hdmim0_tx0_hpd &hdmim1_tx0_scl &hdmim1_tx0_sda>;
+ pinctrl-0 = <&hdmim0_tx0_hpd &hdmim1_tx0_scl &hdmim1_tx0_sda
+ &hdmi0_frl_en>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
index a0e97481afb7..ea0be7b6c935 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
@@ -150,7 +150,8 @@ &gpu {
&hdmi0 {
pinctrl-names = "default";
pinctrl-0 = <&hdmim1_tx0_cec &hdmim0_tx0_hpd &hdmim1_tx0_scl
- &hdmim1_tx0_sda>;
+ &hdmim1_tx0_sda &hdmi0_frl_en>;
+ frl-enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
};
&i2c1 {
@@ -349,6 +350,12 @@ eth_reset: eth-reset {
};
};
+ hdmi {
+ hdmi0_frl_en: hdmi0-frl-en {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
leds {
module_led_pin: module-led-pin {
rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.53.0
^ permalink raw reply related
* [PATCH 29/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-coolpi-4b
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO4_B6 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts
index 189444d20779..af8b386603f7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts
@@ -251,6 +251,9 @@ &gpu {
};
&hdmi0 {
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_frl_en>;
+ frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -396,6 +399,12 @@ &pd_gpu {
};
&pinctrl {
+ hdmi {
+ hdmi0_frl_en: hdmi0-frl-en {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
--
2.53.0
^ permalink raw reply related
* [PATCH 30/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-gameforce-ace
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO4_B3 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property and drop the line from hdmi0-con to allow adjusting the bias
when transitioning between TMDS and FRL operating modes.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts
index 89618394c0bf..0270e5b046eb 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts
@@ -302,9 +302,6 @@ amp_headphone: headphone-amplifier {
hdmi0-con {
compatible = "hdmi-connector";
- ddc-en-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&hdmi0_en>;
- pinctrl-names = "default";
type = "d";
port {
@@ -515,8 +512,9 @@ &gpu {
&hdmi0 {
no-hpd;
pinctrl-0 = <&hdmim0_tx0_cec>, <&hdmim0_tx0_scl>,
- <&hdmim0_tx0_sda>;
+ <&hdmim0_tx0_sda>, <&hdmi0_frl_en>;
pinctrl-names = "default";
+ frl-enable-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -893,7 +891,7 @@ charger_int_h: charger-int-h {
};
hdmi {
- hdmi0_en: hdmi0-en {
+ hdmi0_frl_en: hdmi0-frl-en {
rockchip,pins =
<4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
--
2.53.0
^ permalink raw reply related
* [PATCH 31/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-indiedroid-nova
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO4_B6 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
index 174d299cc6bb..9a98574ecf7d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
@@ -278,8 +278,10 @@ &gpu {
&hdmi0 {
pinctrl-0 = <&hdmim0_tx0_scl>, <&hdmim0_tx0_sda>,
- <&hdmim0_tx0_hpd>, <&hdmim0_tx0_cec>;
+ <&hdmim0_tx0_hpd>, <&hdmim0_tx0_cec>,
+ <&hdmi0_frl_en>;
pinctrl-names = "default";
+ frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -517,6 +519,12 @@ bt_wake_host: bt-wake-host {
};
};
+ hdmi {
+ hdmi0_frl_en: hdmi0-frl-en {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
hym8563 {
hym8563_int: hym8563-int {
--
2.53.0
^ permalink raw reply related
* [PATCH 32/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-khadas-edge2
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO4_B1 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.
While at it, remove the duplicated &hdmi0_sound node.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
index 2c22abaf40a8..2076c050cd69 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
@@ -194,6 +194,9 @@ &gpu {
};
&hdmi0 {
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_frl_en>;
+ frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -217,10 +220,6 @@ &hdptxphy0 {
status = "okay";
};
-&hdmi0_sound {
- status = "okay";
-};
-
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
@@ -282,6 +281,12 @@ &pd_gpu {
};
&pinctrl {
+ hdmi {
+ hdmi0_frl_en: hdmi0-frl-en {
+ rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
vdd_sd {
vdd_sd_en: vdd-sd-en {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
--
2.53.0
^ permalink raw reply related
* [PATCH 33/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-nanopi-r6
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO4_B6 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
index 1b6a59f7cabc..d4560c0d6cd1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
@@ -236,6 +236,9 @@ &gpu {
};
&hdmi0 {
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_frl_en>;
+ frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -404,6 +407,12 @@ lan2_led_pin: lan2-led-pin {
};
};
+ hdmi {
+ hdmi0_frl_en: hdmi0-frl-en {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
hym8563 {
rtc_int: rtc-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
--
2.53.0
^ permalink raw reply related
* [PATCH 34/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-odroid-m2
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO4_B6 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts
index a72063c55140..2ec3bb6d682e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts
@@ -249,6 +249,9 @@ &gpu {
};
&hdmi0 {
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_frl_en>;
+ frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -438,6 +441,12 @@ &pd_gpu {
};
&pinctrl {
+ hdmi {
+ hdmi0_frl_en: hdmi0-frl-en {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
lcd {
lcd_pwren: lcd-pwren {
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.53.0
^ permalink raw reply related
* [PATCH 35/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-orangepi-5
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO4_B6 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi
index dafad29f9854..2fb1362ee15c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi
@@ -181,6 +181,9 @@ &gpu {
};
&hdmi0 {
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_frl_en>;
+ frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -381,6 +384,12 @@ &pd_npu {
};
&pinctrl {
+ hdmi {
+ hdmi0_frl_en: hdmi0-frl-en {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.53.0
^ permalink raw reply related
* [PATCH 36/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-orangepi-cm5-base
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO4_B5 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts
index 06120b2db690..a7b47670195c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts
@@ -147,6 +147,7 @@ &hdmi0 {
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda
&hdmi_frl_pin>;
+ frl-enable-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -246,7 +247,7 @@ key1_pin: key1-pin {
hdmi {
hdmi_frl_pin: hdmi-frl-pin {
- rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
--
2.53.0
^ permalink raw reply related
* [PATCH 37/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-radxa-cm5-io
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO4_B6 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts
index f80d5a00a4bd..339df05c6d71 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts
@@ -120,6 +120,9 @@ &gmac1 {
};
&hdmi0 {
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_frl_en>;
+ frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -217,6 +220,12 @@ usbc0_int: usbc0-int {
};
};
+ hdmi {
+ hdmi0_frl_en: hdmi0-frl-en {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.53.0
^ permalink raw reply related
* [PATCH 38/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-roc-pc
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO4_B2 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.
While at it, move hym8563 down to fix the ordering of &pinctrl entries.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts
index 7e179862da6e..a54d1aac284f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts
@@ -224,6 +224,9 @@ &gpu {
};
&hdmi0 {
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_frl_en>;
+ frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -367,9 +370,9 @@ &pd_gpu {
};
&pinctrl {
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ hdmi {
+ hdmi0_frl_en: hdmi0-frl-en {
+ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -379,6 +382,12 @@ hp_detect: hp-detect {
};
};
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
leds {
led_pins: led-pins {
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
--
2.53.0
^ permalink raw reply related
* [PATCH 39/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-rock-5a
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO4_B6 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
index 0991f6a21190..b3afbdd7119d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
@@ -327,7 +327,9 @@ &hdmi0 {
pinctrl-0 = <&hdmim0_tx0_cec
&hdmim1_tx0_hpd
&hdmim0_tx0_scl
- &hdmim0_tx0_sda>;
+ &hdmim0_tx0_sda
+ &hdmi0_frl_en>;
+ frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -373,6 +375,12 @@ &pd_gpu {
};
&pinctrl {
+ hdmi {
+ hdmi0_frl_en: hdmi0-frl-en {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
leds {
io_led: io-led {
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.53.0
^ permalink raw reply related
* [PATCH 40/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-rock-5c
From: Cristian Ciocaltea @ 2026-04-17 9:25 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
The board exposes the GPIO4_B6 line to control the voltage bias on the
HDMI0 data lines. It must be asserted when operating in HDMI 2.1 FRL
mode and deasserted for HDMI 1.4/2.0 TMDS mode.
Wire up the HDMI0 node to the GPIO line using the frl-enable-gpios
property to allow adjusting the bias when transitioning between TMDS and
FRL operating modes.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
index 7fe42f4ff827..8ffbbc5f9b6c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
@@ -262,7 +262,9 @@ &hdmi0 {
pinctrl-0 = <&hdmim0_tx0_cec
&hdmim1_tx0_hpd
&hdmim0_tx0_scl
- &hdmim0_tx0_sda>;
+ &hdmim0_tx0_sda
+ &hdmi0_frl_en>;
+ frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -461,6 +463,12 @@ &pd_gpu {
};
&pinctrl {
+ hdmi {
+ hdmi0_frl_en: hdmi0-frl-en {
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
leds {
led_pins: led-pins {
rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v2 1/8] dt-bindings: mfd: khadas: Add new compatible for Khadas VIM4 MCU
From: Ronald Claveau @ 2026-04-17 9:31 UTC (permalink / raw)
To: Neil Armstrong, Rob Herring
Cc: Lee Jones, Krzysztof Kozlowski, Conor Dooley, Andi Shyti,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Beniamino Galvani, Rafael J. Wysocki, Daniel Lezcano, Zhang Rui,
Lukasz Luba, Liam Girdwood, Mark Brown, linux-amlogic, devicetree,
linux-kernel, linux-i2c, linux-arm-kernel, linux-pm
In-Reply-To: <6758aaa2-ac1a-4751-aece-2b445b84f2bc@linaro.org>
On 4/17/26 9:53 AM, Neil Armstrong wrote:
> On 4/16/26 10:25, Ronald Claveau wrote:
>> On 4/15/26 11:48 PM, Rob Herring wrote:
>>> On Fri, Apr 03, 2026 at 06:08:34PM +0200, Ronald Claveau wrote:
>>>> The Khadas VIM4 MCU register is slightly different
>>>> from previous boards' MCU.
>>>> This board also features a switchable power source for its fan.
>>>>
>>>> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
>>>> ---
>>>> Documentation/devicetree/bindings/mfd/khadas,mcu.yaml | 5 +++++
>>>> 1 file changed, 5 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
>>>> b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
>>>> index 084960fd5a1fd..67769ef5d58b1 100644
>>>> --- a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
>>>> +++ b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
>>>> @@ -18,6 +18,7 @@ properties:
>>>> compatible:
>>>> enum:
>>>> - khadas,mcu # MCU revision is discoverable
>>>
>>> The revision is no longer discoverable as was claimed?
>>>
>>
>> The firmware revision is still discoverable, and via the same register,
>> but the VIM4 MCU has a different register layout (eg: no DEVICE_NO
>> register). The new compatible is needed to describe a different MCU
>> variant, not a different revision of the same MCU.
>> I will remove the comment as it is confusing with new boards.
>
> Yes basically it was discoverable for earlier MCU version, but is not
> for this particular board version.
>
> Keep the comment, but add a comment on the vim4 entry saying this variant
> is not discoverable.
>
> Neil
>
Ok make sense, I will do that.
>>
>>>> + - khadas,vim4-mcu
>>>> "#cooling-cells": # Only needed for boards having FAN control
>>>> feature
>>>> const: 2
>>>> @@ -25,6 +26,10 @@ properties:
>>>> reg:
>>>> maxItems: 1
>>>> + fan-supply:
>>>> + description: Phandle to the regulator that powers the fan.
>>>> + $ref: /schemas/types.yaml#/definitions/phandle
>>>> +
>>>> required:
>>>> - compatible
>>>> - reg
>>>>
>>>> --
>>>> 2.49.0
>>>>
>>
>>
>
--
Best regards,
Ronald
^ permalink raw reply
* [PATCH v1] arm64: dts: qcom: qcs6490-rb3gen2: Add WCD headset playback and record for qcs6490-rb3gen2 industrial mezzanine
From: Karthik S @ 2026-04-17 9:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Karthik S
Add WCD playback and capture DAI link to sound node. Add WCD
codec node and corresponding soundwire nodes to perform
headset playback and record.
Signed-off-by: Karthik S <karthik.s@qss.qualcomm.com>
---
.../qcs6490-rb3gen2-industrial-mezzanine.dtso | 133 ++++++++++++++++++
1 file changed, 133 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index 83908db335af..d2503fce352c 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -6,6 +6,7 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
@@ -30,6 +31,29 @@ vreg_1p8: regulator-1v8 {
regulator-always-on;
regulator-boot-on;
};
+
+ wcd9370: audio-codec-0 {
+ compatible = "qcom,wcd9370-codec";
+
+ pinctrl-0 = <&wcd_default>;
+ pinctrl-names = "default";
+
+ reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
+ vdd-buck-supply = <&vph_pwr>;
+ vdd-rxtx-supply = <&vph_pwr>;
+ vdd-px-supply = <&vph_pwr>;
+ vdd-mic-bias-supply = <&vph_pwr>;
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,hphl-jack-type-normally-closed = <1>;
+ qcom,ground-jack-type-normally-closed = <1>;
+ qcom,rx-device = <&wcd937x_rx>;
+ qcom,tx-device = <&wcd937x_tx>;
+
+ #sound-dai-cells = <1>;
+ };
};
&remoteproc_wpss {
@@ -283,8 +307,117 @@ pcie1_tc9563_resx_n: pcie1-tc9563-resx-state {
output-enable;
};
+ wcd_default: wcd-reset-n-active-state {
+ pins = "gpio83";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
};
&wifi {
status = "disabled";
};
+
+&swr0 {
+ status = "okay";
+
+ wcd937x_rx: codec@0,4 {
+ compatible = "sdw20217010a00";
+ reg = <0 4>;
+
+ /*
+ * WCD9370 RX Port 1 (HPH_L/R) <==> SWR1 Port 1 (HPH_L/R)
+ * WCD9370 RX Port 2 (CLSH) <==> SWR1 Port 2 (CLSH)
+ * WCD9370 RX Port 3 (COMP_L/R) <==> SWR1 Port 3 (COMP_L/R)
+ * WCD9370 RX Port 4 (LO) <==> SWR1 Port 4 (LO)
+ * WCD9370 RX Port 5 (DSD_L/R) <==> SWR1 Port 5 (DSD)
+ */
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+
+ /*
+ * Static channels mapping between slave and master rx port channels.
+ * In the order of slave port channels, which is
+ * hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l.
+ */
+ qcom,rx-channel-mapping = /bits/ 8 <1 2 1 1 2 1 1 2>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+ wcd937x_tx: codec@0,3 {
+ compatible = "sdw20217010a00";
+ reg = <0 3>;
+
+ /*
+ * WCD9370 TX Port 1 (ADC1) <=> SWR2 Port 2
+ * WCD9370 TX Port 2 (ADC2, 3) <=> SWR2 Port 2
+ * WCD9370 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3
+ * WCD9370 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4
+ */
+ qcom,tx-port-mapping = <1 1 2 3>;
+
+ /*
+ * Static channel mapping between slave and master tx port channels.
+ * In the order of slave port channels which is adc1, adc2, adc3,
+ * mic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7.
+ */
+ qcom,tx-channel-mapping = /bits/ 8 <1 2 1 1 2 3 3 4 1 2 3 4>;
+ };
+};
+
+&lpass_tx_macro {
+ status = "okay";
+};
+
+&lpass_rx_macro {
+ status = "okay";
+};
+
+&sound {
+ model = "qcs6490-rb3gen2-ia-snd-card";
+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC2", "MIC BIAS2",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "VA DMIC0", "vdd-micb",
+ "VA DMIC1", "vdd-micb",
+ "VA DMIC2", "vdd-micb",
+ "VA DMIC3", "vdd-micb";
+
+ wcd-capture-dai-link {
+ link-name = "WCD Capture";
+
+ codec {
+ sound-dai = <&wcd9370 1>, <&swr1 0>, <&lpass_tx_macro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wcd-playback-dai-link {
+ link-name = "WCD Playback";
+
+ codec {
+ sound-dai = <&wcd9370 0>, <&swr0 0>, <&lpass_rx_macro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+};
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v2 1/2] dt-bindings: input: Add PixArt PAJ7620 gesture sensor
From: Krzysztof Kozlowski @ 2026-04-17 9:34 UTC (permalink / raw)
To: Harpreet Saini
Cc: Dmitry Torokhov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
David Lechner, devicetree, linux-input, linux-kernel
In-Reply-To: <20260417052527.62535-2-sainiharpreet29@yahoo.com>
On Fri, Apr 17, 2026 at 01:25:26AM -0400, Harpreet Saini wrote:
> Signed-off-by: Harpreet Saini <sainiharpreet29@yahoo.com>
> ---
> .../bindings/input/pixart,paj7620.yaml | 70 +++++++++++++++++++
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> 2 files changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/input/pixart,paj7620.yaml
>
Comments from v1 apply. Respond to the instead of ignoring.
> diff --git a/Documentation/devicetree/bindings/input/pixart,paj7620.yaml b/Documentation/devicetree/bindings/input/pixart,paj7620.yaml
> new file mode 100644
> index 000000000000..d4f58b712810
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/input/pixart,paj7620.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org
> +$schema: http://devicetree.org
There is no such syntax. Don't invent own coding style.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH RFC 3/4] clk: qcom: tcsrcc-glymur: Migrate tcsr_pcie_N_clkref_en to clk_ref common helper
From: Manivannan Sadhasivam @ 2026-04-17 9:39 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Qiang Yu, Bjorn Andersson, Taniya Das, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Konrad Dybcio, johan, linux-arm-msm, linux-clk, devicetree,
linux-kernel
In-Reply-To: <3d4a12f1-a9ba-4955-b018-f1c271aab766@oss.qualcomm.com>
On Mon, Apr 13, 2026 at 01:18:16PM +0200, Konrad Dybcio wrote:
> On 4/13/26 9:06 AM, Qiang Yu wrote:
> > On Thu, Apr 09, 2026 at 08:19:41AM -0500, Bjorn Andersson wrote:
> >> On Wed, Apr 01, 2026 at 09:47:38PM -0700, Qiang Yu wrote:
> >>> On Wed, Apr 01, 2026 at 10:05:12PM +0530, Taniya Das wrote:
> >>>> On 4/1/2026 12:05 PM, Qiang Yu wrote:
> >>>>> diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-glymur.c
> >> [..]
> >>>>> +static const char * const tcsr_pcie_4_regulators[] = {
> >>>>> + "vdda-refgen-0p9",
> >>>>> + "vdda-refgen-1p2",
> >>>>> + "vdda-qreftx1-0p9",
> >>>>> + "vdda-qrefrpt0-0p9",
> >>>>> + "vdda-qrefrpt1-0p9",
> >>>>> + "vdda-qrefrpt2-0p9",
> >>>>> + "vdda-qrefrx2-0p9",
> >>>>> +};
> >>>>> +
> >>>>
> >>>> TCSR clock refs are just not for PCIe alone, they would have supplies
> >>>> for all the ref clocks. These supplies can also be shared across other
> >>>> clock refs. I think it is not the correct way to handle the supplies, as
> >>>> TCSR does not have the complete supplies map.
> >>>>
> >>> We have complete supplies map. You can get it on ipcatlog. Here is example
> >>> for other instances eg USB and EDP:
> >>> - Glymur (eDP): CXO PAD -> TX0 -> RPT0 -> RX0 -> eDP
> >>> - Glymur (USB4_2): CXO PAD -> TX0 -> RPT0 -> RPT1 -> RX1 -> USB4_2
> >>> - Glymur (USB3): CXO PAD -> TX0 -> RPT3 -> RPT4 -> RX4 -> USB3_SS3
> >>>
> >>> I only add supplies for PCIe in this series because USB and EDP vote these
> >>> LDO in their PHY driver. They can remove them in PHY dts node and add same
> >>> regulator list here.
> >>>
> >>
> >> The regulators are reference counted. Can't we add the USB and eDP
> >> handling here as well now, and then after they are voted here we remove
> >> them from the PHY?
> >>
> >
> > For USB, I’m not yet sure which tcsr_*_clkref_en each USB instance in the
> > QREF diagram is tied to. I need to confirm that mapping first, I'm
> > checking with Wesley Cheng.
>
> I think on at least some platforms the reference clock for the primary
> USB controller is not sw-controllable (so we wouldn't get a handle to
> toggle the regulator this way).. please check that
>
I would suggest we move forward with atleast PCIe regulators for now. Since USB
and eDP are voting for these regulators on their own, we can work with relevant
teams later to switch to this model and this is not going to cause any
regression for them.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply
* Re: [PATCH v2 2/2] input: misc: Add PixArt PAJ7620 gesture sensor driver
From: Krzysztof Kozlowski @ 2026-04-17 9:39 UTC (permalink / raw)
To: Harpreet Saini
Cc: Dmitry Torokhov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
David Lechner, devicetree, linux-input, linux-kernel
In-Reply-To: <20260417052527.62535-3-sainiharpreet29@yahoo.com>
On Fri, Apr 17, 2026 at 01:25:27AM -0400, Harpreet Saini wrote:
> +
> +static int paj7620_init(struct paj7620_data *data)
> +{
> + int state = 0, ret, i;
> +
> + /* 1. Wake-up sequence: Read register 0x00 until it returns 0x20 */
> + for (i = 0; i < 10; i++) {
> + ret = regmap_read(data->regmap, 0x00, &state);
> + if (ret >= 0 && state == 0x20)
> + break;
> + usleep_range(1000, 2000);
> + }
> +
> + if (state != 0x20) {
> + dev_err(&data->client->dev, "Sensor wake-up failed (0x%02x)\n", state);
> + return -ENODEV;
> + }
> +
> + /* 2. Blast full register array into PAJ7620 instantly */
> + ret = regmap_multi_reg_write(data->regmap, Init_Register,
> + ARRAY_SIZE(Init_Register));
> + if (ret < 0) {
> + dev_err(&data->client->dev, "Multi-reg write failed (%d)\n", ret);
> + return ret;
> + }
> +
> + ret = regmap_write(data->regmap, PAJ7620_REG_BANK_SEL, 0x00);
> + if (ret < 0)
> + return ret;
> +
> + ret = regmap_multi_reg_write(data->regmap, Init_Gesture_Array,
> + ARRAY_SIZE(Init_Gesture_Array));
> + if (ret < 0) {
> + dev_err(&data->client->dev, "Multi-reg write failed (%d)\n", ret);
> + return ret;
> + }
> +
> + dev_info(&data->client->dev, "Gesture Sensor Registers Initialized\n");
Drop, driver should be silent.
...
> + data->client = client;
> + i2c_set_clientdata(client, data);
> +
> + data->supplies[0].supply = "vdd";
> + data->supplies[1].supply = "vbus";
> + data->supplies[2].supply = "vled";
> +
> + ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(data->supplies), data->supplies);
> + if (ret)
> + return dev_err_probe(&client->dev, ret, "Failed to get regulators\n");
> +
> + ret = regulator_bulk_enable(ARRAY_SIZE(data->supplies), data->supplies);
> + if (ret)
> + return ret;
> +
> + data->regmap = devm_regmap_init_i2c(client, &paj7620_reg_config);
> + if (IS_ERR(data->regmap))
> + return PTR_ERR(data->regmap);
Leaking regulator enable.
> +
> + ret = paj7620_init(data);
> + if (ret)
> + goto err_reg;
> +
> + data->idev = devm_input_allocate_device(&client->dev);
> + if (!data->idev) {
> + ret = -ENOMEM; goto err_reg;
Messed syntax/wrapped lines.
And you must not print error msg on ENOMEM error.
> + }
> +
> + data->idev->name = "PAJ7620 Gesture Sensor";
> + data->idev->id.bustype = BUS_I2C;
> +
> + input_set_capability(data->idev, EV_KEY, KEY_UP);
> + input_set_capability(data->idev, EV_KEY, KEY_DOWN);
> + input_set_capability(data->idev, EV_KEY, KEY_LEFT);
> + input_set_capability(data->idev, EV_KEY, KEY_RIGHT);
> + input_set_capability(data->idev, EV_KEY, KEY_ENTER);
> + input_set_capability(data->idev, EV_KEY, KEY_BACK);
> + input_set_capability(data->idev, EV_KEY, KEY_NEXT);
> + input_set_capability(data->idev, EV_KEY, KEY_PREVIOUS);
> + input_set_capability(data->idev, EV_KEY, KEY_MENU);
> +
> + ret = input_register_device(data->idev);
> + if (ret)
> + goto err_reg;
> +
> + pm_runtime_set_active(&client->dev);
> + pm_runtime_enable(&client->dev);
> + pm_runtime_set_autosuspend_delay(&client->dev, 2000);
> + pm_runtime_use_autosuspend(&client->dev);
> +
> + ret = devm_request_threaded_irq(&client->dev, client->irq, NULL,
> + paj7620_irq_thread, IRQF_ONESHOT,
> + "paj7620", data);
> + if (ret)
> + goto err_reg;
> +
> + dev_info(&client->dev, "Gesture Sensor Initialized\n");
Pointless message, drop. Driver should be silent on success.
> + return 0;
> +
> +err_reg:
> + dev_err_probe(&client->dev, ret, "%s: failed with error %d\n", __func__, ret);
No, move it to individual errors, but only where applicable. For example
devm_request_threaded_irq() must not have it.
Neither devm_input_allocate_device.
> + if (pm_runtime_enabled(&client->dev)) {
> + pm_runtime_disable(&client->dev);
> + pm_runtime_dont_use_autosuspend(&client->dev);
> + }
> + regulator_bulk_disable(ARRAY_SIZE(data->supplies), data->supplies);
> + return ret;
> +}
> +
> +static void paj7620_remove(struct i2c_client *client)
> +{
> + int ret;
> + struct paj7620_data *data = i2c_get_clientdata(client);
> +
> + pm_runtime_get_sync(&client->dev);
> + pm_runtime_disable(&client->dev);
> + pm_runtime_dont_use_autosuspend(&client->dev);
> + pm_runtime_put_noidle(&client->dev);
> +
> + ret = paj7620_power_down(data);
> + if (ret)
> + dev_err(&data->client->dev, "Sensor power down failed\n");
> +
> + ret = regulator_bulk_disable(ARRAY_SIZE(data->supplies), data->supplies);
> + if (ret)
> + dev_err(&data->client->dev, "Sensor regulator disable failed\n");
> +}
> +
> +static const struct of_device_id paj7620_of_match[] = {
> + { .compatible = "pixart,paj7620" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, paj7620_of_match);
> +
> +static struct i2c_driver paj7620_driver = {
> + .driver = {
> + .name = "paj7620",
> + .of_match_table = paj7620_of_match,
> + .pm = &paj7620_pm_ops,
> + },
> + .probe = paj7620_probe,
> + .remove = paj7620_remove,
> +};
> +module_i2c_driver(paj7620_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Harpreet Saini");
> +MODULE_DESCRIPTION("PAJ7620 Gesture Input Driver");
> --
> 2.43.0
>
^ permalink raw reply
* Re: [PATCH v1] arm64: dts: qcom: qcs6490-rb3gen2: Add WCD headset playback and record for qcs6490-rb3gen2 industrial mezzanine
From: Krzysztof Kozlowski @ 2026-04-17 9:42 UTC (permalink / raw)
To: Karthik S, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260417093327.3251203-1-karthik.s@qss.qualcomm.com>
On 17/04/2026 11:33, Karthik S wrote:
> Add WCD playback and capture DAI link to sound node. Add WCD
> codec node and corresponding soundwire nodes to perform
> headset playback and record.
>
> Signed-off-by: Karthik S <karthik.s@qss.qualcomm.com>
> ---
> .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 133 ++++++++++++++++++
> 1 file changed, 133 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> index 83908db335af..d2503fce352c 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
> @@ -6,6 +6,7 @@
> /dts-v1/;
> /plugin/;
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/sound/qcom,q6afe.h>
> #include <dt-bindings/clock/qcom,gcc-sc7280.h>
> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
>
> @@ -30,6 +31,29 @@ vreg_1p8: regulator-1v8 {
> regulator-always-on;
> regulator-boot-on;
> };
> +
> + wcd9370: audio-codec-0 {
Why 'audio-codec' goes after 'regulator'? And is there audio-codec-1? If
so, where?
> + compatible = "qcom,wcd9370-codec";
> +
> + pinctrl-0 = <&wcd_default>;
> + pinctrl-names = "default";
> +
> + reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
> + vdd-buck-supply = <&vph_pwr>;
> + vdd-rxtx-supply = <&vph_pwr>;
> + vdd-px-supply = <&vph_pwr>;
> + vdd-mic-bias-supply = <&vph_pwr>;
> + qcom,micbias1-microvolt = <1800000>;
> + qcom,micbias2-microvolt = <1800000>;
> + qcom,micbias3-microvolt = <1800000>;
> + qcom,micbias4-microvolt = <1800000>;
> + qcom,hphl-jack-type-normally-closed = <1>;
> + qcom,ground-jack-type-normally-closed = <1>;
> + qcom,rx-device = <&wcd937x_rx>;
> + qcom,tx-device = <&wcd937x_tx>;
> +
> + #sound-dai-cells = <1>;
> + };
> };
>
> &remoteproc_wpss {
> @@ -283,8 +307,117 @@ pcie1_tc9563_resx_n: pcie1-tc9563-resx-state {
> output-enable;
> };
>
> + wcd_default: wcd-reset-n-active-state {
Messed indentation.
> + pins = "gpio83";
> + function = "gpio";
> + drive-strength = <16>;
> + bias-disable;
> + };
> +
> };
>
> &wifi {
> status = "disabled";
> };
> +
> +&swr0 {
What sort of sorting is this?
> + status = "okay";
> +
> + wcd937x_rx: codec@0,4 {
> + compatible = "sdw20217010a00";
> + reg = <0 4>;
Even worse here.
And finally:
Please run scripts/checkpatch.pl on the patches and fix reported
warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
patches and (probably) fix more warnings. Some warnings can be ignored,
especially from --strict run, but the code here looks like it needs a
fix. Feel free to get in touch if the warning is not clear.
Undocumented ABI (without any reference in changelog where to find
posted patch).
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v6 0/2] Add Support for LTC3220 18 Channel LED Driver
From: Edelweise Escala @ 2026-04-17 9:42 UTC (permalink / raw)
To: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-leds, devicetree, linux-kernel, Edelweise Escala,
Conor Dooley
The LTC3220/LTC3220-1 is a multi-display LED driver, which contains a
high-efficiency, low-noise charge pump to provide power to up to
18 LED current sources. The LEDs are individually configurable to
64-step linear brightness control, blinking and gradation control
via 2-wire I2C interface. The blinking and gradation configuration
is shared across all LED.
LTC3220 has a quick write function which allows changing the brightness
on all LEDS simultaneously when the brightness is changed on led 1.
For this leds are aggregated in the device tree and on probe we check
if led-sources exist to enable quick write.
We would like to know if this approach is alright?
Another way we might want to know is, is it alright to just make a
virtual led for the quick write function. Changing brightness on
the virtual led will change the brightness for all.
Signed-off-by: Edelweise Escala <edelweise.escala@analog.com>
---
Changes in v6:
- Fix commit message
- Add manufacturer on Kconfig and improve description
- Rearrange register map and bitmask and improve naming
- Use regmap, also use update bits of regmap to avoid unnecessary
structs
- Alignment and spacing fixes
- Use Define for magic naumbers
- Fix blink calculation
- Add comments on aggregated LED
- Fix variable name to something more understandable like i to led_index
- Link to v5: https://lore.kernel.org/r/20260126-ltc3220-driver-v5-0-152a30e98ab7@analog.com
Changes in v5:
- Missed rename on bindings filename in MAINTAINERS file
- Link to v4: https://lore.kernel.org/linux-leds/20260126-ltc3220-driver-v4-0-c59517206c24@analog.com
Changes in v4:
- Rename leds-ltc3220.yaml to adi,ltc3220.yaml
- Add Reviewed-by: Conor Dooley <conor.dooley@microchip.com> on
adi,ltc3220.yaml
Other V1 comments I think already addressed
- Subject commit message was already changed to match hardware
- Fixed wrapping after description
- Dropped "Bindings for" in descriptions and improved description to match hardware
- Dropped adi,ltc3220-1
- Dropped redundant description on reset-gpios
- Dropped adi,force-cpo-level
- Dropped adi,quick-write in favor of aggregated LED
- Used consistent quotes ^led@([1-9]|1[0-8])$
- Fixed wrapping on error messages
- Link to v3: https://lore.kernel.org/r/20260120-ltc3220-driver-v3-0-fef612ec4faa@analog.com
Changes in v3:
- Dropped quick-write on bindings and added aggregated led instead.
- Add aggregated led example.
- Modify quick write to check if there is aggregated led, if there is
aggregated led enable quick write.
- Use DEFINE_SIMPLE_DEV_PM_OPS instead of SIMPLE_DEV_PM_OPS.
- Link to v2: https://lore.kernel.org/r/20260112-ltc3220-driver-v2-0-d043058fc4df@analog.com
Changes in v2:
leds-ltc3220.yaml changes
- Fix wrapping on description
- Improve description and commit messge to describe hardware
- Drop ltc3220-1
- Drop charge pump
ltc3220.c changes
- Fix wrapping
- Drop ltc3220-1
- Drop devname_mandatory
- Link to v1: https://lore.kernel.org/r/20260106-ltc3220-driver-v1-0-73601d6f1649@analog.com
---
Edelweise Escala (2):
dt-bindings: leds: Add LTC3220 18 channel LED Driver
leds: ltc3220: Add Support for LTC3220 18 channel LED Driver
.../devicetree/bindings/leds/adi,ltc3220.yaml | 120 ++++++
MAINTAINERS | 8 +
drivers/leds/Kconfig | 12 +
drivers/leds/Makefile | 1 +
drivers/leds/leds-ltc3220.c | 418 +++++++++++++++++++++
5 files changed, 559 insertions(+)
---
base-commit: 8856d7fe1758937ac528770f552ec58c388c255b
change-id: 20260106-ltc3220-driver-f9ab6cc9d1e4
Best regards,
--
Edelweise Escala <edelweise.escala@analog.com>
^ permalink raw reply
* [PATCH v6 1/2] dt-bindings: leds: Add LTC3220 18 channel LED Driver
From: Edelweise Escala @ 2026-04-17 9:42 UTC (permalink / raw)
To: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-leds, devicetree, linux-kernel, Edelweise Escala,
Conor Dooley
In-Reply-To: <20260417-ltc3220-driver-v6-0-18157871eddd@analog.com>
LTC3220 is a multi-display LED driver with I2C interface.
The LTC3220 provides individual brightness control (64-step),
blinking, and gradation features for up to 18 LED outputs.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Edelweise Escala <edelweise.escala@analog.com>
---
.../devicetree/bindings/leds/adi,ltc3220.yaml | 120 +++++++++++++++++++++
MAINTAINERS | 7 ++
2 files changed, 127 insertions(+)
diff --git a/Documentation/devicetree/bindings/leds/adi,ltc3220.yaml b/Documentation/devicetree/bindings/leds/adi,ltc3220.yaml
new file mode 100644
index 000000000000..62f760d517aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/adi,ltc3220.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/adi,ltc3220.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices LTC3220 LED Driver
+
+maintainers:
+ - Edelweise Escala <edelweise.escala@analog.com>
+
+description:
+ The LTC3220 is a multi-display LED driver, which contains a high-efficiency,
+ low-noise charge pump to provide power to up to 18 LED current sources.
+ The LEDs are individually configurable to 64-step linear brightness control,
+ blinking and gradation control via 2-wire I2C interface.
+
+ For more product information please see the link below
+ https://www.analog.com/en/products/ltc3220.html
+
+properties:
+ compatible:
+ const: adi,ltc3220
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ reset-gpios:
+ maxItems: 1
+
+patternProperties:
+ '^led@([1-9]|1[0-8])$':
+ type: object
+ $ref: /schemas/leds/common.yaml#
+ unevaluatedProperties: false
+ properties:
+ reg:
+ description:
+ Output channel for the LED (1-18 maps to LED outputs D1-D18).
+ For aggregated LED control, define only one LED node with reg = <1>
+ and use led-sources to list all controlled outputs. Only reg 1 should
+ be present when using led-sources.
+ minimum: 1
+ maximum: 18
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ // Independent LEDs
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led-controller@1c {
+ compatible = "adi,ltc3220";
+ reg = <0x1c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+
+ led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <1>;
+ };
+
+ led@2 {
+ reg = <2>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <2>;
+ };
+
+ led@3 {
+ reg = <3>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <3>;
+ };
+ };
+ };
+
+ - |
+ // Aggregated LED
+ #include <dt-bindings/leds/common.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led-controller@1c {
+ compatible = "adi,ltc3220";
+ reg = <0x1c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ led-sources = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18>;
+ function = LED_FUNCTION_BACKLIGHT;
+ };
+ };
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 327d74ca7ecb..5c10cc3e3022 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14955,6 +14955,13 @@ W: https://ez.analog.com/linux-software-drivers
F: Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml
F: drivers/iio/temperature/ltc2983.c
+LTC3220 LED DRIVER
+M: Edelweise Escala <edelweise.escala@analog.com>
+L: linux-leds@vger.kernel.org
+S: Maintained
+W: https://ez.analog.com/linux-software-drivers
+F: Documentation/devicetree/bindings/leds/adi,ltc3220.yaml
+
LTC4282 HARDWARE MONITOR DRIVER
M: Nuno Sa <nuno.sa@analog.com>
L: linux-hwmon@vger.kernel.org
--
2.43.0
^ permalink raw reply related
* [PATCH v6 2/2] leds: ltc3220: Add Support for LTC3220 18 channel LED Driver
From: Edelweise Escala @ 2026-04-17 9:42 UTC (permalink / raw)
To: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-leds, devicetree, linux-kernel, Edelweise Escala
In-Reply-To: <20260417-ltc3220-driver-v6-0-18157871eddd@analog.com>
Add driver for the LTC3220 18-channel LED driver
with I2C interface, individual brightness control, and hardware-assisted
blink/gradation features.
Signed-off-by: Edelweise Escala <edelweise.escala@analog.com>
---
MAINTAINERS | 1 +
drivers/leds/Kconfig | 12 ++
drivers/leds/Makefile | 1 +
drivers/leds/leds-ltc3220.c | 418 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 432 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5c10cc3e3022..7467537938bf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14961,6 +14961,7 @@ L: linux-leds@vger.kernel.org
S: Maintained
W: https://ez.analog.com/linux-software-drivers
F: Documentation/devicetree/bindings/leds/adi,ltc3220.yaml
+F: drivers/leds/leds-ltc3220.c
LTC4282 HARDWARE MONITOR DRIVER
M: Nuno Sa <nuno.sa@analog.com>
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 597d7a79c988..f00cdc11c978 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -1001,6 +1001,18 @@ config LEDS_ST1202
Say Y to enable support for LEDs connected to LED1202
LED driver chips accessed via the I2C bus.
+config LEDS_LTC3220
+ tristate "LED Driver for Analog Devices Inc. LTC3220"
+ depends on I2C && LEDS_CLASS
+ help
+ Say Y to enable support for the Analog Devices LTC3220
+ 18-channel LED controller with I2C interface.
+ The driver supports individual LED brightness control (64 steps),
+ hardware-assisted blinking and gradation effects.
+
+ To compile this driver as a module, choose M here: the module will
+ be called leds-ltc3220.
+
config LEDS_TPS6105X
tristate "LED support for TI TPS6105X"
depends on LEDS_CLASS
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 8fdb45d5b439..5301568d9e00 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_LEDS_LP8788) += leds-lp8788.o
obj-$(CONFIG_LEDS_LP8860) += leds-lp8860.o
obj-$(CONFIG_LEDS_LP8864) += leds-lp8864.o
obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o
+obj-$(CONFIG_LEDS_LTC3220) += leds-ltc3220.o
obj-$(CONFIG_LEDS_MAX5970) += leds-max5970.o
obj-$(CONFIG_LEDS_MAX77650) += leds-max77650.o
obj-$(CONFIG_LEDS_MAX77705) += leds-max77705.o
diff --git a/drivers/leds/leds-ltc3220.c b/drivers/leds/leds-ltc3220.c
new file mode 100644
index 000000000000..5e1f994cc35b
--- /dev/null
+++ b/drivers/leds/leds-ltc3220.c
@@ -0,0 +1,418 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * LTC3220 18-Channel LED Driver
+ *
+ * Copyright 2026 Analog Devices Inc.
+ *
+ * Author: Edelweise Escala <edelweise.escala@analog.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/leds.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+/* LTC3220 Registers */
+#define LTC3220_COMMAND_REG 0x00
+#define LTC3220_QUICK_WRITE_MASK BIT(0)
+#define LTC3220_SHUTDOWN_MASK BIT(3)
+
+#define LTC3220_ULED_REG(x) (0x01 + (x))
+#define LTC3220_LED_CURRENT_MASK GENMASK(5, 0)
+#define LTC3220_LED_MODE_MASK GENMASK(7, 6)
+
+#define LTC3220_GRAD_BLINK_REG 0x13
+#define LTC3220_GRADATION_MASK GENMASK(2, 0)
+#define LTC3220_GRADATION_DIRECTION_MASK BIT(0)
+#define LTC3220_GRADATION_PERIOD_MASK GENMASK(2, 1)
+#define LTC3220_BLINK_MASK GENMASK(4, 3)
+
+#define LTC3220_NUM_LEDS 18
+
+#define LTC3220_GRADATION_START_VALUE 128
+#define LTC3220_GRADATION_RAMP_TIME_240MS 240
+#define LTC3220_GRADATION_RAMP_TIME_480MS 480
+
+#define LTC3220_BLINK_ON_156MS 156
+#define LTC3220_BLINK_ON_625MS 625
+#define LTC3220_BLINK_PERIOD_1250MS 1250
+#define LTC3220_BLINK_PERIOD_2500MS 2500
+
+#define LTC3220_BLINK_SHORT_ON_TIME BIT(0)
+#define LTC3220_BLINK_LONG_PERIOD BIT(1)
+
+enum ltc3220_blink_mode {
+ LTC3220_BLINK_MODE_625MS_1250MS,
+ LTC3220_BLINK_MODE_156MS_1250MS,
+ LTC3220_BLINK_MODE_625MS_2500MS,
+ LTC3220_BLINK_MODE_156MS_2500MS
+};
+
+enum ltc3220_gradation_mode {
+ LTC3220_GRADATION_MODE_DISABLED,
+ LTC3220_GRADATION_MODE_240MS_RAMP_TIME,
+ LTC3220_GRADATION_MODE_480MS_RAMP_TIME,
+ LTC3220_GRADATION_MODE_960MS_RAMP_TIME
+};
+
+static const struct regmap_config ltc3220_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = LTC3220_GRAD_BLINK_REG,
+};
+
+struct ltc3220_uled_cfg {
+ struct ltc3220_state *ltc3220_state;
+ struct led_classdev led_cdev;
+ u8 reg_value;
+ u8 led_index;
+};
+
+struct ltc3220_state {
+ struct ltc3220_uled_cfg uled_cfg[LTC3220_NUM_LEDS];
+ struct regmap *regmap;
+ bool is_aggregated;
+};
+
+static int ltc3220_shutdown(struct ltc3220_state *ltc3220_state)
+{
+ return regmap_update_bits(ltc3220_state->regmap, LTC3220_COMMAND_REG,
+ LTC3220_SHUTDOWN_MASK, LTC3220_SHUTDOWN_MASK);
+}
+
+static int ltc3220_resume_from_shutdown(struct ltc3220_state *ltc3220_state)
+{
+ return regmap_update_bits(ltc3220_state->regmap, LTC3220_COMMAND_REG,
+ LTC3220_SHUTDOWN_MASK, 0);
+}
+
+/*
+ * Set LED brightness and mode.
+ * The brightness value determines both the LED current and operating mode:
+ * 0-63: Normal mode - LED current from 0-63 (off to full brightness)
+ * 64-127: Blink mode - LED blinks with current level (brightness - 64)
+ * 128-191: Gradation mode - LED gradually changes brightness (brightness - 128)
+ * 192-255: GPO mode - LED operates as general purpose output (brightness - 192)
+ */
+static int ltc3220_set_led_data(struct led_classdev *led_cdev,
+ enum led_brightness brightness)
+{
+ struct ltc3220_state *ltc3220_state;
+ struct ltc3220_uled_cfg *uled_cfg;
+ int ret;
+ int i;
+
+ uled_cfg = container_of(led_cdev, struct ltc3220_uled_cfg, led_cdev);
+ ltc3220_state = uled_cfg->ltc3220_state;
+
+ ret = regmap_write(ltc3220_state->regmap, LTC3220_ULED_REG(uled_cfg->led_index),
+ brightness);
+ if (ret < 0)
+ return ret;
+
+ uled_cfg->reg_value = brightness;
+
+ /*
+ * When aggregated LED mode is enabled, writing to LED 1 updates all
+ * LEDs simultaneously via quick-write mode. Update cached values for
+ * all LEDs to reflect the synchronized state.
+ * See Documentation/devicetree/bindings/leds/adi,ltc3220.yaml for how
+ * to configure aggregated LED mode.
+ */
+ if (ltc3220_state->is_aggregated && uled_cfg->led_index == 0) {
+ for (i = 0; i < LTC3220_NUM_LEDS; i++)
+ ltc3220_state->uled_cfg[i].reg_value = brightness;
+ }
+
+ return 0;
+}
+
+static enum led_brightness ltc3220_get_led_data(struct led_classdev *led_cdev)
+{
+ struct ltc3220_uled_cfg *uled_cfg = container_of(led_cdev,
+ struct ltc3220_uled_cfg, led_cdev);
+
+ return uled_cfg->reg_value;
+}
+
+/*
+ * LTC3220 pattern support for hardware-assisted breathing/gradation.
+ * The hardware supports 3 gradation ramp time 240ms, 480ms, 960ms)
+ * and can ramp up or down.
+ *
+ * Pattern array interpretation:
+ * pattern[0].brightness = start brightness (0-63)
+ * pattern[0].delta_t = ramp time in milliseconds
+ * pattern[1].brightness = end brightness (0-63)
+ * pattern[1].delta_t = (optional, can be 0 or same as pattern[0].delta_t)
+ */
+static int ltc3220_pattern_set(struct led_classdev *led_cdev,
+ struct led_pattern *pattern,
+ u32 len, int repeat)
+{
+ struct ltc3220_uled_cfg *uled_cfg = container_of(led_cdev, struct ltc3220_uled_cfg,
+ led_cdev);
+ struct ltc3220_state *ltc3220_state = uled_cfg->ltc3220_state;
+ u8 gradation_period;
+ u8 start_brightness;
+ u8 end_brightness;
+ u8 reg_val;
+ bool is_increasing;
+ int ret;
+
+ if (len != 2)
+ return -EINVAL;
+
+ start_brightness = pattern[0].brightness & LTC3220_LED_CURRENT_MASK;
+ end_brightness = pattern[1].brightness & LTC3220_LED_CURRENT_MASK;
+
+ is_increasing = end_brightness > start_brightness;
+
+ if (pattern[0].delta_t == 0)
+ gradation_period = LTC3220_GRADATION_MODE_DISABLED;
+ else if (pattern[0].delta_t <= LTC3220_GRADATION_RAMP_TIME_240MS)
+ gradation_period = LTC3220_GRADATION_MODE_240MS_RAMP_TIME;
+ else if (pattern[0].delta_t <= LTC3220_GRADATION_RAMP_TIME_480MS)
+ gradation_period = LTC3220_GRADATION_MODE_480MS_RAMP_TIME;
+ else
+ gradation_period = LTC3220_GRADATION_MODE_960MS_RAMP_TIME;
+
+ reg_val = FIELD_PREP(LTC3220_GRADATION_PERIOD_MASK, gradation_period);
+ reg_val |= FIELD_PREP(LTC3220_GRADATION_DIRECTION_MASK, is_increasing);
+
+ ret = regmap_update_bits(ltc3220_state->regmap, LTC3220_GRAD_BLINK_REG,
+ LTC3220_GRADATION_MASK, reg_val);
+ if (ret < 0)
+ return ret;
+
+ ret = ltc3220_set_led_data(led_cdev, start_brightness);
+ if (ret < 0)
+ return ret;
+
+ return ltc3220_set_led_data(led_cdev, LTC3220_GRADATION_START_VALUE + end_brightness);
+}
+
+static int ltc3220_pattern_clear(struct led_classdev *led_cdev)
+{
+ struct ltc3220_uled_cfg *uled_cfg = container_of(led_cdev, struct ltc3220_uled_cfg,
+ led_cdev);
+ struct ltc3220_state *ltc3220_state = uled_cfg->ltc3220_state;
+
+ return regmap_update_bits(ltc3220_state->regmap, LTC3220_GRAD_BLINK_REG,
+ LTC3220_GRADATION_MASK, 0);
+}
+
+/*
+ * LTC3220 has a global blink configuration that affects all LEDs.
+ * This implementation allows per-LED blink requests, but the blink timing
+ * will be shared across all LEDs. The delay values are mapped to the
+ * hardware's discrete blink rates.
+ */
+static int ltc3220_blink_set(struct led_classdev *led_cdev,
+ unsigned long *delay_on,
+ unsigned long *delay_off)
+{
+ struct ltc3220_uled_cfg *uled_cfg = container_of(led_cdev, struct ltc3220_uled_cfg,
+ led_cdev);
+ struct ltc3220_state *ltc3220_state = uled_cfg->ltc3220_state;
+ u8 blink_mode = 0;
+
+ if (*delay_on <= LTC3220_BLINK_ON_156MS)
+ blink_mode = LTC3220_BLINK_SHORT_ON_TIME;
+
+ if (*delay_on + *delay_off > LTC3220_BLINK_PERIOD_1250MS)
+ blink_mode |= LTC3220_BLINK_LONG_PERIOD;
+
+ switch (blink_mode) {
+ case LTC3220_BLINK_MODE_625MS_1250MS:
+ *delay_on = LTC3220_BLINK_ON_625MS;
+ *delay_off = LTC3220_BLINK_PERIOD_1250MS - LTC3220_BLINK_ON_625MS;
+ break;
+ case LTC3220_BLINK_MODE_156MS_1250MS:
+ *delay_on = LTC3220_BLINK_ON_156MS;
+ *delay_off = LTC3220_BLINK_PERIOD_1250MS - LTC3220_BLINK_ON_156MS;
+ break;
+ case LTC3220_BLINK_MODE_625MS_2500MS:
+ *delay_on = LTC3220_BLINK_ON_625MS;
+ *delay_off = LTC3220_BLINK_PERIOD_2500MS - LTC3220_BLINK_ON_625MS;
+ break;
+ case LTC3220_BLINK_MODE_156MS_2500MS:
+ *delay_on = LTC3220_BLINK_ON_156MS;
+ *delay_off = LTC3220_BLINK_PERIOD_2500MS - LTC3220_BLINK_ON_156MS;
+ break;
+ }
+
+ return regmap_update_bits(ltc3220_state->regmap, LTC3220_GRAD_BLINK_REG,
+ LTC3220_BLINK_MASK, blink_mode);
+}
+
+static void ltc3220_reset_gpio_action(void *data)
+{
+ struct gpio_desc *reset_gpio = data;
+
+ gpiod_set_value_cansleep(reset_gpio, 1);
+}
+
+static int ltc3220_reset(struct ltc3220_state *ltc3220_state, struct i2c_client *client)
+{
+ struct gpio_desc *reset_gpio;
+ int ret;
+ int i;
+
+ reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(reset_gpio))
+ return dev_err_probe(&client->dev, PTR_ERR(reset_gpio), "Failed on reset GPIO\n");
+
+ if (reset_gpio) {
+ gpiod_set_value_cansleep(reset_gpio, 0);
+
+ return devm_add_action_or_reset(&client->dev, ltc3220_reset_gpio_action,
+ reset_gpio);
+ }
+
+ ret = regmap_write(ltc3220_state->regmap, LTC3220_COMMAND_REG, 0);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < LTC3220_NUM_LEDS; i++) {
+ ret = regmap_write(ltc3220_state->regmap, LTC3220_ULED_REG(i), 0);
+ if (ret < 0)
+ return ret;
+ }
+
+ return regmap_write(ltc3220_state->regmap, LTC3220_GRAD_BLINK_REG, 0);
+}
+
+static int ltc3220_suspend(struct device *dev)
+{
+ struct ltc3220_state *ltc3220_state = i2c_get_clientdata(to_i2c_client(dev));
+
+ return ltc3220_shutdown(ltc3220_state);
+}
+
+static int ltc3220_resume(struct device *dev)
+{
+ struct ltc3220_state *ltc3220_state = i2c_get_clientdata(to_i2c_client(dev));
+
+ return ltc3220_resume_from_shutdown(ltc3220_state);
+}
+
+static DEFINE_SIMPLE_DEV_PM_OPS(ltc3220_pm_ops, ltc3220_suspend, ltc3220_resume);
+
+static int ltc3220_probe(struct i2c_client *client)
+{
+ struct ltc3220_state *ltc3220_state;
+ bool aggregated_led_found = false;
+ int num_leds = 0;
+ u8 led_index = 0;
+ int ret;
+
+ ltc3220_state = devm_kzalloc(&client->dev, sizeof(*ltc3220_state), GFP_KERNEL);
+ if (!ltc3220_state)
+ return -ENOMEM;
+
+ ltc3220_state->regmap = devm_regmap_init_i2c(client, <c3220_regmap_config);
+ if (IS_ERR(ltc3220_state->regmap))
+ return dev_err_probe(&client->dev, PTR_ERR(ltc3220_state->regmap),
+ "Failed to initialize regmap\n");
+
+ i2c_set_clientdata(client, ltc3220_state);
+
+ ret = ltc3220_reset(ltc3220_state, client);
+ if (ret)
+ return dev_err_probe(&client->dev, ret, "Failed to reset device\n");
+
+ device_for_each_child_node_scoped(&client->dev, child) {
+ struct led_init_data init_data = {};
+ struct ltc3220_uled_cfg *led;
+ u32 source;
+
+ ret = fwnode_property_read_u32(child, "reg", &source);
+ if (ret)
+ return dev_err_probe(&client->dev, ret, "Couldn't read LED address\n");
+
+ if (!source || source > LTC3220_NUM_LEDS)
+ return dev_err_probe(&client->dev, -EINVAL, "LED address out of range\n");
+
+ init_data.fwnode = child;
+ init_data.devicename = "ltc3220";
+
+ if (fwnode_property_present(child, "led-sources")) {
+ if (source != 1)
+ return dev_err_probe(&client->dev, -EINVAL,
+ "Aggregated LED out of range\n");
+
+ if (aggregated_led_found)
+ return dev_err_probe(&client->dev, -EINVAL,
+ "One Aggregated LED only\n");
+
+ aggregated_led_found = true;
+ ltc3220_state->is_aggregated = true;
+
+ ret = regmap_update_bits(ltc3220_state->regmap,
+ LTC3220_COMMAND_REG,
+ LTC3220_QUICK_WRITE_MASK,
+ LTC3220_QUICK_WRITE_MASK);
+ if (ret < 0)
+ return dev_err_probe(&client->dev, ret,
+ "Failed to set quick write mode\n");
+ }
+
+ num_leds++;
+
+ /* LED node reg/index/address goes from 1 to 18 */
+ led_index = source - 1;
+ led = <c3220_state->uled_cfg[led_index];
+ led->led_index = led_index;
+ led->reg_value = 0;
+ led->ltc3220_state = ltc3220_state;
+ led->led_cdev.brightness_set_blocking = ltc3220_set_led_data;
+ led->led_cdev.brightness_get = ltc3220_get_led_data;
+ led->led_cdev.max_brightness = 255;
+ led->led_cdev.blink_set = ltc3220_blink_set;
+ led->led_cdev.pattern_set = ltc3220_pattern_set;
+ led->led_cdev.pattern_clear = ltc3220_pattern_clear;
+
+ ret = devm_led_classdev_register_ext(&client->dev, &led->led_cdev, &init_data);
+ if (ret)
+ return dev_err_probe(&client->dev, ret, "Failed to register LED class\n");
+ }
+
+ /*
+ * Aggregated LED mode uses hardware quick-write to control all 18 LEDs
+ * simultaneously. This is mutually exclusive with individual LED control.
+ * See Documentation/devicetree/bindings/leds/adi,ltc3220.yaml for details
+ * on how to configure aggregated LED mode.
+ */
+ if (aggregated_led_found && num_leds > 1)
+ return dev_err_probe(&client->dev, -EINVAL,
+ "Aggregated LED must be the only LED node\n");
+
+ return 0;
+}
+
+static const struct of_device_id ltc3220_of_match[] = {
+ { .compatible = "adi,ltc3220" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ltc3220_of_match);
+
+static struct i2c_driver ltc3220_led_driver = {
+ .driver = {
+ .name = "ltc3220",
+ .of_match_table = ltc3220_of_match,
+ .pm = pm_sleep_ptr(<c3220_pm_ops),
+ },
+ .probe = ltc3220_probe,
+};
+module_i2c_driver(ltc3220_led_driver);
+
+MODULE_AUTHOR("Edelweise Escala <edelweise.escala@analog.com>");
+MODULE_DESCRIPTION("LED driver for LTC3220 controllers");
+MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply related
* Re: [PATCH 5/5] media: synopsys: Add support for i.MX95
From: Frank Li @ 2026-04-17 9:45 UTC (permalink / raw)
To: Guoniu Zhou
Cc: Michael Riesch, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Laurent Pinchart, linux-media, linux-kernel, devicetree, imx,
linux-arm-kernel, linux-rockchip
In-Reply-To: <20260415-csi2_imx95-v1-5-7d63f3508719@oss.nxp.com>
On Wed, Apr 15, 2026 at 11:46:56AM +0800, Guoniu Zhou wrote:
> Add support for the i.MX95 MIPI CSI-2 receiver. The i.MX95 variant is
> nearly identical to i.MX93, with the main difference being the use of
> IDI (Image Data Interface) instead of IPI (Image Pixel Interface).
> However, the IDI interface is transparent to software, requiring only
> a different register map definition while sharing the same PHY control
> functions with i.MX93.
>
> Signed-off-by: Guoniu Zhou <guoniu.zhou@oss.nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> drivers/media/platform/synopsys/dw-mipi-csi2rx.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> index 27e4c1027816..bbb41baf789e 100644
> --- a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> +++ b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> @@ -154,6 +154,17 @@ static const u32 imx93_regs[DW_MIPI_CSI2RX_MAX] = {
> [DW_MIPI_CSI2RX_IPI_SOFTRSTN] = DW_REG(0xa0),
> };
>
> +static const u32 imx95_regs[DW_MIPI_CSI2RX_MAX] = {
> + [DW_MIPI_CSI2RX_N_LANES] = DW_REG(0x4),
> + [DW_MIPI_CSI2RX_RESETN] = DW_REG(0x8),
> + [DW_MIPI_CSI2RX_PHY_SHUTDOWNZ] = DW_REG(0x40),
> + [DW_MIPI_CSI2RX_DPHY_RSTZ] = DW_REG(0x44),
> + [DW_MIPI_CSI2RX_PHY_STATE] = DW_REG(0x48),
> + [DW_MIPI_CSI2RX_PHY_STOPSTATE] = DW_REG(0x4c),
> + [DW_MIPI_CSI2RX_PHY_TST_CTRL0] = DW_REG(0x50),
> + [DW_MIPI_CSI2RX_PHY_TST_CTRL1] = DW_REG(0x54),
> +};
> +
> static const struct v4l2_mbus_framefmt default_format = {
> .width = 3840,
> .height = 2160,
> @@ -901,11 +912,22 @@ static const struct dw_mipi_csi2rx_drvdata imx93_drvdata = {
> .wait_for_phy_stopstate = imx93_csi2rx_wait_for_phy_stopstate,
> };
>
> +static const struct dw_mipi_csi2rx_drvdata imx95_drvdata = {
> + .regs = imx95_regs,
> + .dphy_assert_reset = imx93_csi2rx_dphy_assert_reset,
> + .dphy_deassert_reset = imx93_csi2rx_dphy_deassert_reset,
> + .wait_for_phy_stopstate = imx93_csi2rx_wait_for_phy_stopstate,
> +};
> +
> static const struct of_device_id dw_mipi_csi2rx_of_match[] = {
> {
> .compatible = "fsl,imx93-mipi-csi2",
> .data = &imx93_drvdata,
> },
> + {
> + .compatible = "fsl,imx95-mipi-csi2",
> + .data = &imx95_drvdata,
> + },
> {
> .compatible = "rockchip,rk3568-mipi-csi2",
> .data = &rk3568_drvdata,
>
> --
> 2.34.1
>
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