* Re: [PATCH 5/5] media: synopsys: Add support for i.MX95
From: Frank Li @ 2026-04-17 9:45 UTC (permalink / raw)
To: Guoniu Zhou
Cc: Michael Riesch, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Laurent Pinchart, linux-media, linux-kernel, devicetree, imx,
linux-arm-kernel, linux-rockchip
In-Reply-To: <20260415-csi2_imx95-v1-5-7d63f3508719@oss.nxp.com>
On Wed, Apr 15, 2026 at 11:46:56AM +0800, Guoniu Zhou wrote:
> Add support for the i.MX95 MIPI CSI-2 receiver. The i.MX95 variant is
> nearly identical to i.MX93, with the main difference being the use of
> IDI (Image Data Interface) instead of IPI (Image Pixel Interface).
> However, the IDI interface is transparent to software, requiring only
> a different register map definition while sharing the same PHY control
> functions with i.MX93.
>
> Signed-off-by: Guoniu Zhou <guoniu.zhou@oss.nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> drivers/media/platform/synopsys/dw-mipi-csi2rx.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> index 27e4c1027816..bbb41baf789e 100644
> --- a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> +++ b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> @@ -154,6 +154,17 @@ static const u32 imx93_regs[DW_MIPI_CSI2RX_MAX] = {
> [DW_MIPI_CSI2RX_IPI_SOFTRSTN] = DW_REG(0xa0),
> };
>
> +static const u32 imx95_regs[DW_MIPI_CSI2RX_MAX] = {
> + [DW_MIPI_CSI2RX_N_LANES] = DW_REG(0x4),
> + [DW_MIPI_CSI2RX_RESETN] = DW_REG(0x8),
> + [DW_MIPI_CSI2RX_PHY_SHUTDOWNZ] = DW_REG(0x40),
> + [DW_MIPI_CSI2RX_DPHY_RSTZ] = DW_REG(0x44),
> + [DW_MIPI_CSI2RX_PHY_STATE] = DW_REG(0x48),
> + [DW_MIPI_CSI2RX_PHY_STOPSTATE] = DW_REG(0x4c),
> + [DW_MIPI_CSI2RX_PHY_TST_CTRL0] = DW_REG(0x50),
> + [DW_MIPI_CSI2RX_PHY_TST_CTRL1] = DW_REG(0x54),
> +};
> +
> static const struct v4l2_mbus_framefmt default_format = {
> .width = 3840,
> .height = 2160,
> @@ -901,11 +912,22 @@ static const struct dw_mipi_csi2rx_drvdata imx93_drvdata = {
> .wait_for_phy_stopstate = imx93_csi2rx_wait_for_phy_stopstate,
> };
>
> +static const struct dw_mipi_csi2rx_drvdata imx95_drvdata = {
> + .regs = imx95_regs,
> + .dphy_assert_reset = imx93_csi2rx_dphy_assert_reset,
> + .dphy_deassert_reset = imx93_csi2rx_dphy_deassert_reset,
> + .wait_for_phy_stopstate = imx93_csi2rx_wait_for_phy_stopstate,
> +};
> +
> static const struct of_device_id dw_mipi_csi2rx_of_match[] = {
> {
> .compatible = "fsl,imx93-mipi-csi2",
> .data = &imx93_drvdata,
> },
> + {
> + .compatible = "fsl,imx95-mipi-csi2",
> + .data = &imx95_drvdata,
> + },
> {
> .compatible = "rockchip,rk3568-mipi-csi2",
> .data = &rk3568_drvdata,
>
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: crypto: qcom-qce: Document the Glymur crypto engine
From: Krzysztof Kozlowski @ 2026-04-17 9:47 UTC (permalink / raw)
To: Harshal Dev
Cc: Thara Gopinath, Herbert Xu, David S. Miller, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, Neeraj Soni, Kuldeep Singh, Abel Vesa,
linux-arm-msm, linux-crypto, devicetree, linux-kernel
In-Reply-To: <20260416-glymur_crypto_enablement-v1-1-75e768c1417c@oss.qualcomm.com>
On Thu, Apr 16, 2026 at 06:37:20PM +0530, Harshal Dev wrote:
> Document the crypto engine on Glymur platform.
>
> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Poor commit msg, but none of previous patches were doing it better, so:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 4/4] arm64: dts: amlogic: t7: Add clk measure support
From: Ronald Claveau @ 2026-04-17 9:48 UTC (permalink / raw)
To: Jian Hu
Cc: devicetree, linux-arm-kernel, linux-amlogic, linux-kernel,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl
In-Reply-To: <20260415-clkmsr_a1_t7-v2-4-02b6314427e6@amlogic.com>
Hello Jian,
On 4/15/26 10:33 AM, Jian Hu via B4 Relay wrote:
> From: Jian Hu <jian.hu@amlogic.com>
>
> Add the clock measure device to the T7 SoC family.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> index 7fe72c94ed62..cec2ea74850d 100644
> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> @@ -701,6 +701,11 @@ pwm_ao_cd: pwm@60000 {
> status = "disabled";
> };
>
> + clock-measurer@48000 {
> + compatible = "amlogic,t7-clk-measure";
> + reg = <0x0 0x48000 0x0 0x1c>;
> + };
> +
Can you please order by reg, it should be between pwm_ao_gh and pwm_ab.
Thank you.
> sd_emmc_a: mmc@88000 {
> compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
> reg = <0x0 0x88000 0x0 0x800>;
>
--
Best regards,
Ronald
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: crypto: qcom-qce: Document the Glymur crypto engine
From: Harshal Dev @ 2026-04-17 9:54 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Thara Gopinath, Herbert Xu, David S. Miller, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, Neeraj Soni, Kuldeep Singh, Abel Vesa,
linux-arm-msm, linux-crypto, devicetree, linux-kernel
In-Reply-To: <20260417-portable-proud-dragonfly-6bdd9a@quoll>
On 4/17/2026 3:17 PM, Krzysztof Kozlowski wrote:
> On Thu, Apr 16, 2026 at 06:37:20PM +0530, Harshal Dev wrote:
>> Document the crypto engine on Glymur platform.
>>
>> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
>> ---
>> Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>
> Poor commit msg, but none of previous patches were doing it better, so:
Noted, I'll try to do better next time.
Regards,
Harshal
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply
* [PATCH v7 2/3] dt-bindings: media: mediatek-jpeg-encoder: add MT8189 compatible string
From: Jianhua Lin @ 2026-04-17 10:05 UTC (permalink / raw)
To: nicolas, mchehab, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno
Cc: devicetree, linux-kernel, linux-media, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, Jianhua Lin
In-Reply-To: <20260417100519.1043-1-jianhua.lin@mediatek.com>
Add the compatible string for the JPEG encoder block found in the
MediaTek MT8189 SoC.
Unlike some previous SoCs, the MT8189 JPEG encoder requires 34-bit IOVA
address space support. Therefore, it is added as a standalone compatible
string without falling back to the generic "mediatek,mtk-jpgenc" to
ensure the driver applies the correct hardware-specific configurations.
Signed-off-by: Jianhua Lin <jianhua.lin@mediatek.com>
---
.../bindings/media/mediatek-jpeg-encoder.yaml | 29 +++++++++++++++----
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
index 5b15f8977f67..690775dbb1ec 100644
--- a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
@@ -14,13 +14,16 @@ description: |-
properties:
compatible:
- items:
+ oneOf:
- enum:
- - mediatek,mt2701-jpgenc
- - mediatek,mt8183-jpgenc
- - mediatek,mt8186-jpgenc
- - mediatek,mt8188-jpgenc
- - const: mediatek,mtk-jpgenc
+ - mediatek,mt8189-jpgenc
+ - items:
+ - enum:
+ - mediatek,mt2701-jpgenc
+ - mediatek,mt8183-jpgenc
+ - mediatek,mt8186-jpgenc
+ - mediatek,mt8188-jpgenc
+ - const: mediatek,mtk-jpgenc
reg:
maxItems: 1
@@ -34,6 +37,10 @@ properties:
items:
- const: jpgenc
+ mediatek,larb:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: a phandle to the smi_larb node.
+
power-domains:
maxItems: 1
@@ -54,6 +61,16 @@ required:
- power-domains
- iommus
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8189-jpgenc
+ then:
+ required:
+ - mediatek,larb
+
additionalProperties: false
examples:
--
2.45.2
^ permalink raw reply related
* [PATCH v7 3/3] media: mediatek: jpeg: add compatible for MT8189 SoC
From: Jianhua Lin @ 2026-04-17 10:05 UTC (permalink / raw)
To: nicolas, mchehab, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno
Cc: devicetree, linux-kernel, linux-media, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, Jianhua Lin
In-Reply-To: <20260417100519.1043-1-jianhua.lin@mediatek.com>
Compared to the previous generation ICs, the MT8189 uses a 34-bit IOVA
address space (16GB) and requires a single clock configuration.
Therefore, add new compatible strings ("mediatek,mt8189-jpgenc" and
"mediatek,mt8189-jpgdec") along with their specific driver data to
support the JPEG encoder and decoder of the MT8189 SoC.
Signed-off-by: Jianhua Lin <jianhua.lin@mediatek.com>
---
.../platform/mediatek/jpeg/mtk_jpeg_core.c | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
index 8c684756d5fc..786cc2942c3a 100644
--- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c
@@ -1867,6 +1867,10 @@ static struct clk_bulk_data mt8173_jpeg_dec_clocks[] = {
{ .id = "jpgdec" },
};
+static struct clk_bulk_data mtk_jpeg_dec_clocks[] = {
+ { .id = "jpgdec" },
+};
+
static const struct mtk_jpeg_variant mt8173_jpeg_drvdata = {
.clks = mt8173_jpeg_dec_clocks,
.num_clks = ARRAY_SIZE(mt8173_jpeg_dec_clocks),
@@ -1898,6 +1902,38 @@ static const struct mtk_jpeg_variant mtk_jpeg_drvdata = {
.multi_core = false,
};
+static const struct mtk_jpeg_variant mtk8189_jpegenc_drvdata = {
+ .clks = mtk_jpeg_clocks,
+ .num_clks = ARRAY_SIZE(mtk_jpeg_clocks),
+ .formats = mtk_jpeg_enc_formats,
+ .num_formats = MTK_JPEG_ENC_NUM_FORMATS,
+ .qops = &mtk_jpeg_enc_qops,
+ .irq_handler = mtk_jpeg_enc_irq,
+ .hw_reset = mtk_jpeg_enc_reset,
+ .m2m_ops = &mtk_jpeg_enc_m2m_ops,
+ .dev_name = "mtk-jpeg-enc",
+ .ioctl_ops = &mtk_jpeg_enc_ioctl_ops,
+ .out_q_default_fourcc = V4L2_PIX_FMT_YUYV,
+ .cap_q_default_fourcc = V4L2_PIX_FMT_JPEG,
+ .support_34bit = true,
+};
+
+static const struct mtk_jpeg_variant mtk8189_jpegdec_drvdata = {
+ .clks = mtk_jpeg_dec_clocks,
+ .num_clks = ARRAY_SIZE(mtk_jpeg_dec_clocks),
+ .formats = mtk_jpeg_dec_formats,
+ .num_formats = MTK_JPEG_DEC_NUM_FORMATS,
+ .qops = &mtk_jpeg_dec_qops,
+ .irq_handler = mtk_jpeg_dec_irq,
+ .hw_reset = mtk_jpeg_dec_reset,
+ .m2m_ops = &mtk_jpeg_dec_m2m_ops,
+ .dev_name = "mtk-jpeg-dec",
+ .ioctl_ops = &mtk_jpeg_dec_ioctl_ops,
+ .out_q_default_fourcc = V4L2_PIX_FMT_JPEG,
+ .cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M,
+ .support_34bit = true,
+};
+
static struct mtk_jpeg_variant mtk8195_jpegenc_drvdata = {
.formats = mtk_jpeg_enc_formats,
.num_formats = MTK_JPEG_ENC_NUM_FORMATS,
@@ -1937,6 +1973,14 @@ static const struct of_device_id mtk_jpeg_match[] = {
.compatible = "mediatek,mtk-jpgenc",
.data = &mtk_jpeg_drvdata,
},
+ {
+ .compatible = "mediatek,mt8189-jpgenc",
+ .data = &mtk8189_jpegenc_drvdata,
+ },
+ {
+ .compatible = "mediatek,mt8189-jpgdec",
+ .data = &mtk8189_jpegdec_drvdata,
+ },
{
.compatible = "mediatek,mt8195-jpgenc",
.data = &mtk8195_jpegenc_drvdata,
--
2.45.2
^ permalink raw reply related
* [PATCH v7 1/3] dt-bindings: media: mediatek-jpeg-decoder: add MT8189 compatible string
From: Jianhua Lin @ 2026-04-17 10:05 UTC (permalink / raw)
To: nicolas, mchehab, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno
Cc: devicetree, linux-kernel, linux-media, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, Jianhua Lin
In-Reply-To: <20260417100519.1043-1-jianhua.lin@mediatek.com>
Add the compatible string for the JPEG decoder block found in the
MediaTek MT8189 SoC.
Compared to previous generation ICs, the MT8189 JPEG decoder requires
34-bit IOVA address space support and only needs a single clock
("jpgdec") instead of two. Therefore, it is added as a standalone
compatible string without falling back to older SoCs.
Update the binding schema to include the new compatible string and add
an `allOf` block with conditional checks. This enforces the single clock
requirement for MT8189 while preserving the two-clock requirement
("jpgdec-smi", "jpgdec") for older SoCs.
Signed-off-by: Jianhua Lin <jianhua.lin@mediatek.com>
---
.../bindings/media/mediatek-jpeg-decoder.yaml | 48 +++++++++++++++----
1 file changed, 40 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
index a4aacd3eb189..fd895688a038 100644
--- a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
@@ -15,10 +15,10 @@ description: |-
properties:
compatible:
oneOf:
- - items:
- - enum:
- - mediatek,mt8173-jpgdec
- - mediatek,mt2701-jpgdec
+ - enum:
+ - mediatek,mt2701-jpgdec
+ - mediatek,mt8173-jpgdec
+ - mediatek,mt8189-jpgdec
- items:
- enum:
- mediatek,mt7623-jpgdec
@@ -32,13 +32,20 @@ properties:
maxItems: 1
clocks:
+ minItems: 1
maxItems: 2
- minItems: 2
clock-names:
- items:
- - const: jpgdec-smi
- - const: jpgdec
+ oneOf:
+ - items:
+ - const: jpgdec
+ - items:
+ - const: jpgdec-smi
+ - const: jpgdec
+
+ mediatek,larb:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: a phandle to the smi_larb node.
power-domains:
maxItems: 1
@@ -60,6 +67,31 @@ required:
- power-domains
- iommus
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8189-jpgdec
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ minItems: 1
+ maxItems: 1
+ required:
+ - mediatek,larb
+ else:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ minItems: 2
+ maxItems: 2
+
additionalProperties: false
examples:
--
2.45.2
^ permalink raw reply related
* [PATCH v7 0/3] Mediatek MT8189 JPEG support
From: Jianhua Lin @ 2026-04-17 10:05 UTC (permalink / raw)
To: nicolas, mchehab, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno
Cc: devicetree, linux-kernel, linux-media, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, sirius.wang,
vince-wl.liu, jh.hsu, Jianhua Lin
This series is based on tag: next-20260410, linux-next/master
Changes compared with v6:
- Patches 1/3 (dt-bindings: decoder):
update the existing `allOf` condition for mediatek,mt8189-jpgdec to
make the 'mediatek,larb' property strictly required for MT8189 SoC.
- Patches 2/3 (dt-bindings: encoder):
Add an `allOf` condition to enforce that the `mediatek,larb` property
is strictly required when the compatible string contains
mediatek,mt8189-jpgenc.
Changes compared with v5:
- Patches 1/3 (dt-bindings: decoder):
- Drop top-level minItems/maxItems for clock-names per Krzysztof's
review.
- Refine allOf block to strictly enforce clock constraints.
Changes compared with v4:
- Refines the device tree bindings for JPEG decoder and encoder.
- Patches 1/3 (dt-bindings: decoder):
Moved the standalone compatible string mediatek,mt8189-jpgdec
into the first oneOf entry along with mt2701 and mt8173, as
suggested by Rob Herring. This correctly groups all independent
ICs and removes the redundant items wrapper.
- Patches 2/3 (dt-bindings: encoder):
Applied the same logic suggested by Rob Herring to the encoder
binding. Restructured the compatible property to clearly
distinguish between the standalone IC (mediatek,mt8189-jpgenc)
and the ICs that must fallback to mediatek,mtk-jpgenc.
Changes compared with v3:
- The v4 is resending the cover-letter, because the v3 cover-letter was
not sent successfully.
Changes compared with v2:
- Dropped the dts patch (arm64: dts: mt8188: update JPEG encoder/decoder
compatible) as it belongs to a different tree/series.
- Patches 1/3 (dt-bindings: decoder):
- Changed the MT8189 compatible to be a standalone `const` instead of
an `enum`.
- Added an `allOf` block with conditional checks to enforce the single
clock ("jpgdec") requirement for MT8189, while preserving the
two-clock requirement for older SoCs.
- Updated commit message to reflect the schema structure changes and
hardware differences.
- Patches 2/3 (dt-bindings: encoder):
- Changed the MT8189 compatible to be a standalone `const` instead of
an `enum` inside the `items` list, as it does not fallback to
"mediatek,mtk-jpgenc" due to 34-bit IOVA requirements.
- Updated commit message to explain the standalone compatible design.
- Patches 3/3 (media: mediatek: jpeg):
- Refined commit message for better clarity regarding 34-bit IOVA and
single clock configuration.
Changes compared with v1:
- Patches 1/4:
- Updating commit message
- Patches 2/4, 3/4:
- Updating commit message
- Adjusted property descriptions acorrding to hardware requirements
- Improved formatting for better readability and consistency
- Patches 4/4:
- Updating commit message
Jianhua Lin (3):
dt-bindings: media: mediatek-jpeg-decoder: add MT8189 compatible
string
dt-bindings: media: mediatek-jpeg-encoder: add MT8189 compatible
string
media: mediatek: jpeg: add compatible for MT8189 SoC
.../bindings/media/mediatek-jpeg-decoder.yaml | 48 +++++++++++++++----
.../bindings/media/mediatek-jpeg-encoder.yaml | 29 ++++++++---
.../platform/mediatek/jpeg/mtk_jpeg_core.c | 44 +++++++++++++++++
3 files changed, 107 insertions(+), 14 deletions(-)
--
2.45.2
^ permalink raw reply
* Re: [PATCH v1] arm64: dts: qcom: qcs6490-rb3gen2: Add WCD headset playback and record for qcs6490-rb3gen2 industrial mezzanine
From: Krzysztof Kozlowski @ 2026-04-17 10:12 UTC (permalink / raw)
To: Karthik S, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <b6600312-3667-472b-9b76-c9977355115a@kernel.org>
On 17/04/2026 11:42, Krzysztof Kozlowski wrote:
>
> And finally:
>
> Please run scripts/checkpatch.pl on the patches and fix reported
> warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
> patches and (probably) fix more warnings. Some warnings can be ignored,
> especially from --strict run, but the code here looks like it needs a
> fix. Feel free to get in touch if the warning is not clear.
As you pointed correctly after offline talk, checkpatch does not report
undocumented compatible for the sound card qcs6490-rb3gen2-ia-snd-card.
Unfortunately this patch did not go through internal toolset fully
(PatchWise), which could have flag the issue. Let's discuss it
internally next week.
>
> Undocumented ABI (without any reference in changelog where to find
> posted patch).
You still need to solve the undocumented sound card ABI - new
compatible. If it is already sent to mailing lists, then provide link in
patch changelog (---).
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH RFC 3/4] clk: qcom: tcsrcc-glymur: Migrate tcsr_pcie_N_clkref_en to clk_ref common helper
From: Konrad Dybcio @ 2026-04-17 10:30 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Qiang Yu, Bjorn Andersson, Taniya Das, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Konrad Dybcio, johan, linux-arm-msm, linux-clk, devicetree,
linux-kernel
In-Reply-To: <z4h53al3dcy5u63zglu4rdavm3cse6sy2bbha2kxxepplawnho@4pwg7fx3cmnj>
On 4/17/26 11:39 AM, Manivannan Sadhasivam wrote:
> On Mon, Apr 13, 2026 at 01:18:16PM +0200, Konrad Dybcio wrote:
>> On 4/13/26 9:06 AM, Qiang Yu wrote:
>>> On Thu, Apr 09, 2026 at 08:19:41AM -0500, Bjorn Andersson wrote:
>>>> On Wed, Apr 01, 2026 at 09:47:38PM -0700, Qiang Yu wrote:
>>>>> On Wed, Apr 01, 2026 at 10:05:12PM +0530, Taniya Das wrote:
>>>>>> On 4/1/2026 12:05 PM, Qiang Yu wrote:
>>>>>>> diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-glymur.c
>>>> [..]
>>>>>>> +static const char * const tcsr_pcie_4_regulators[] = {
>>>>>>> + "vdda-refgen-0p9",
>>>>>>> + "vdda-refgen-1p2",
>>>>>>> + "vdda-qreftx1-0p9",
>>>>>>> + "vdda-qrefrpt0-0p9",
>>>>>>> + "vdda-qrefrpt1-0p9",
>>>>>>> + "vdda-qrefrpt2-0p9",
>>>>>>> + "vdda-qrefrx2-0p9",
>>>>>>> +};
>>>>>>> +
>>>>>>
>>>>>> TCSR clock refs are just not for PCIe alone, they would have supplies
>>>>>> for all the ref clocks. These supplies can also be shared across other
>>>>>> clock refs. I think it is not the correct way to handle the supplies, as
>>>>>> TCSR does not have the complete supplies map.
>>>>>>
>>>>> We have complete supplies map. You can get it on ipcatlog. Here is example
>>>>> for other instances eg USB and EDP:
>>>>> - Glymur (eDP): CXO PAD -> TX0 -> RPT0 -> RX0 -> eDP
>>>>> - Glymur (USB4_2): CXO PAD -> TX0 -> RPT0 -> RPT1 -> RX1 -> USB4_2
>>>>> - Glymur (USB3): CXO PAD -> TX0 -> RPT3 -> RPT4 -> RX4 -> USB3_SS3
>>>>>
>>>>> I only add supplies for PCIe in this series because USB and EDP vote these
>>>>> LDO in their PHY driver. They can remove them in PHY dts node and add same
>>>>> regulator list here.
>>>>>
>>>>
>>>> The regulators are reference counted. Can't we add the USB and eDP
>>>> handling here as well now, and then after they are voted here we remove
>>>> them from the PHY?
>>>>
>>>
>>> For USB, I’m not yet sure which tcsr_*_clkref_en each USB instance in the
>>> QREF diagram is tied to. I need to confirm that mapping first, I'm
>>> checking with Wesley Cheng.
>>
>> I think on at least some platforms the reference clock for the primary
>> USB controller is not sw-controllable (so we wouldn't get a handle to
>> toggle the regulator this way).. please check that
>>
>
> I would suggest we move forward with atleast PCIe regulators for now. Since USB
> and eDP are voting for these regulators on their own, we can work with relevant
> teams later to switch to this model and this is not going to cause any
> regression for them.
I think we can do that, yeah
Konrad
^ permalink raw reply
* Re: [PATCH 4/5] media: dt-bindings: add NXP i.MX95 compatible string
From: Frank Li @ 2026-04-17 10:30 UTC (permalink / raw)
To: G.N. Zhou (OSS)
Cc: Krzysztof Kozlowski, Michael Riesch, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Laurent Pinchart, linux-media@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
In-Reply-To: <DU2PR04MB9081CE0130B8924A2B3C9E14FA222@DU2PR04MB9081.eurprd04.prod.outlook.com>
On Wed, Apr 15, 2026 at 09:21:44AM +0000, G.N. Zhou (OSS) wrote:
> Hi Krzysztof Kozlowski
>
> Thanks for your review.
>
> > -----Original Message-----
> > From: Krzysztof Kozlowski <krzk@kernel.org>
> > Sent: Wednesday, April 15, 2026 4:10 PM
> > To: G.N. Zhou (OSS) <guoniu.zhou@oss.nxp.com>
> > Cc: Michael Riesch <michael.riesch@collabora.com>; Mauro Carvalho Chehab
> > <mchehab@kernel.org>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> > <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Heiko Stuebner
> > <heiko@sntech.de>; Laurent Pinchart <laurent.pinchart@ideasonboard.com>;
> > Frank Li <frank.li@nxp.com>; linux-media@vger.kernel.org; linux-
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; imx@lists.linux.dev; linux-
> > arm-kernel@lists.infradead.org; linux-rockchip@lists.infradead.org
> > Subject: Re: [PATCH 4/5] media: dt-bindings: add NXP i.MX95 compatible string
> >
> > On Wed, Apr 15, 2026 at 11:46:55AM +0800, Guoniu Zhou wrote:
> > > The i.MX95 CSI-2 controller is nearly identical to i.MX93, with the
> > > only difference being the use of IDI (Image Data Interface) instead of
> > > IPI (Image Pixel Interface). The binding constraints are otherwise the
> > > same.
> >
> > Nearly identical with some difference really, really suggests they are
> > compatible. Express compatibility or explain why they are not compatible
> > (difference between IDI and IPI unfortunately does not help me).
>
> You're right that they are very similar. The key difference between IDI and IPI
> is in the software interface:
>
> - IPI (Image Pixel Interface) on i.MX93 requires software configuration through
> a set of registers to enable the interface and configure data routing.
>
> - IDI (Image Data Interface) on i.MX95 is software transparent - it requires no
> register configuration and the data routing is handled automatically by hardware.
>
> Because of this difference in register layout and initialization requirements,
> they cannot share the same compatible string. The driver needs to know which
> interface is present
Just include these key information into commit message to do judgement
it is not compatible with imx93.
Frank
>
> >
> > Best regards,
> > Krzysztof
>
^ permalink raw reply
* [PATCH v2 0/2] Add support for Zhunyi Z40046 LCD panel
From: Luca Leonardo Scorcia @ 2026-04-17 10:46 UTC (permalink / raw)
To: dri-devel
Cc: Luca Leonardo Scorcia, Jagan Teki, Neil Armstrong, Jessica Zhang,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Marek Vasut, Lad Prabhakar, Kael D'Alcamo,
devicetree, linux-kernel
The Zhunyi Z40046 is a 480x800 24-bit WVGA DSI panel based on the
Fitipower JD9161Z DSI controller found in the Xiaomi Mi Smart Clock
x04g, apparently in two different variants.
The Fitipower JD9161Z LCD driver IC is very similar to the Jadard
JD9365DA-H3, it just uses different initialization sequences. A
partial data sheet is available at [1].
The two initialization sequences for the panel have been extracted from
Android original firmware for the Xiaomi Smart Clock.
Variant -ctc tested on device. Variant -boe not tested.
Changes in v2:
- Double checked and fixed some mistakes in the reverse engineered
initialization sequences
- Changed the generic variant names -v1, -v2 into -ctc and -boe, as
they're described in the Android logs
- Fix alphabetical order in bindings and correct company name
v1:
https://lore.kernel.org/all/20260305195650.119196-1-l.scorcia@gmail.com/
[1] https://github.com/QuecPython/QuecPython_lib_bundles/blob/master/libraries/LCD/JD91651z/JD9161Z_DS_Preliminary_V0.01_20180803(1).pdf
Luca Leonardo Scorcia (2):
dt-bindings: display: panel: Add compatibles for Zhunyi Z40046
drm/panel: jd9365da: Support for Zhunyi Z40046 panels
.../display/panel/jadard,jd9365da-h3.yaml | 2 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
.../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 313 ++++++++++++++++++
3 files changed, 317 insertions(+)
--
2.43.0
^ permalink raw reply
* [PATCH v2 1/2] dt-bindings: display: panel: Add compatibles for Zhunyi Z40046
From: Luca Leonardo Scorcia @ 2026-04-17 10:46 UTC (permalink / raw)
To: dri-devel
Cc: Luca Leonardo Scorcia, Jagan Teki, Neil Armstrong, Jessica Zhang,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Marek Vasut, Kael D'Alcamo, Lad Prabhakar,
devicetree, linux-kernel
In-Reply-To: <20260417104740.259689-1-l.scorcia@gmail.com>
The Zhunyi Z40046 is a 480x800 24-bit WVGA DSI panel based on the
Fitipower JD9161Z DSI controller found in the Xiaomi Mi Smart Clock
x04g, apparently in two different variants.
The Fitipower JD9161Z LCD driver IC is very similar to the Jadard
JD9365DA-H3, it just uses a different initialization sequence.
Since this is the first supported device from this vendor, document its
name to the vendor-prefixes.yaml file as well.
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
---
.../devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml | 2 ++
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
2 files changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
index e39efb44ed42..158388a284d9 100644
--- a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
+++ b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
@@ -24,6 +24,8 @@ properties:
- radxa,display-10hd-ad001
- radxa,display-8hd-ad002
- taiguanck,xti05101-01a
+ - zhunyikeji,z40046-ctc
+ - zhunyikeji,z40046-boe
- const: jadard,jd9365da-h3
reg:
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 6339988e3805..debaec59e9a0 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1923,6 +1923,8 @@ patternProperties:
description: Zealz
"^zeitec,.*":
description: ZEITEC Semiconductor Co., LTD.
+ "^zhunyikeji,.*":
+ description: Shenzhen Zhunyi Technology Co., Ltd.
"^zidoo,.*":
description: Shenzhen Zidoo Technology Co., Ltd.
"^zii,.*":
--
2.43.0
^ permalink raw reply related
* [PATCH v2 2/2] drm/panel: jd9365da: Support for Zhunyi Z40046 panels
From: Luca Leonardo Scorcia @ 2026-04-17 10:46 UTC (permalink / raw)
To: dri-devel
Cc: Luca Leonardo Scorcia, Jagan Teki, Neil Armstrong, Jessica Zhang,
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Marek Vasut, Kael D'Alcamo, Lad Prabhakar,
devicetree, linux-kernel
In-Reply-To: <20260417104740.259689-1-l.scorcia@gmail.com>
The Zhunyi Z40046 is a 480x800 24-bit WVGA DSI panel based on the
Fitipower JD9161Z DSI controller found in the Xiaomi Mi Smart Clock
x04g, apparently in two different variants.
The Fitipower JD9161Z LCD driver IC is very similar to the Jadard
JD9365DA-H3, it just uses different initialization sequences.
The two initialization sequences for the panel have been extracted from
Android original firmware for the Xiaomi Smart Clock.
Variant -ctc uses a CTC LCD panel and has been tested on device.
Variant -boe uses a BOE LCD panel and has not been tested.
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
---
.../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 313 ++++++++++++++++++
1 file changed, 313 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
index c33c611e03c0..7da064567248 100644
--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
@@ -46,11 +46,22 @@ struct jadard {
struct gpio_desc *reset;
};
+#define JD9161Z_DCS_SWITCH_PAGE 0xde
+
+#define jd9161z_switch_page(dsi_ctx, page) \
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, JD9161Z_DCS_SWITCH_PAGE, (page))
+
#define JD9365DA_DCS_SWITCH_PAGE 0xe0
#define jd9365da_switch_page(dsi_ctx, page) \
mipi_dsi_dcs_write_seq_multi(dsi_ctx, JD9365DA_DCS_SWITCH_PAGE, (page))
+static void jd9161z_enable_standard_cmds(struct mipi_dsi_multi_context *dsi_ctx)
+{
+ // Enable access to DCS and internal commands
+ mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xdf, 0x91, 0x62, 0xf3);
+}
+
static void jadard_enable_standard_cmds(struct mipi_dsi_multi_context *dsi_ctx)
{
mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe1, 0x93);
@@ -1606,6 +1617,300 @@ static const struct jadard_panel_desc taiguan_xti05101_01a_desc = {
.enter_sleep_to_reset_down_delay_ms = 100,
};
+// Sequence retrieved from Xiaomi Mi Smart Clock x04g kernel in boot.bin
+static int zhunyi_z40046_init_cmds_ctc(struct jadard *jadard_data)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard_data->dsi };
+
+ // Init configuration sequence
+ jd9161z_switch_page(&dsi_ctx, 0x00);
+ jd9161z_enable_standard_cmds(&dsi_ctx);
+
+ // GAMMA_SET (pos/neg voltage of gamma power)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb7,
+ 0x10, 0x04, 0x86, 0x00, 0x1b, 0x35);
+
+ // DCDC_SEL (power mode and charge pump settings)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbb,
+ 0x69, 0x0b, 0x30, 0xb2, 0xb2, 0xc0, 0xe0, 0x20,
+ 0xf0, 0x50, 0x60);
+
+ mipi_dsi_msleep(&dsi_ctx, 1);
+
+ // VDDD_CTRL (control logic voltage setting)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbc,
+ 0x73, 0x14);
+
+ mipi_dsi_msleep(&dsi_ctx, 1);
+
+ // SETRGBCYC (display waveform cycle of RGB mode)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc3,
+ 0x74, 0x04, 0x08, 0x0e, 0x00, 0x0e, 0x0c, 0x08,
+ 0x0e, 0x00, 0x0e, 0x82, 0x0a, 0x82);
+
+ // SET_TCON (timing control setting)
+ // param[0][5:4] + param[1]: number of panel lines / 2
+ // 400 = 01 1001 0000 -> 0x10, 0x90
+ // param[2]: scan line time width
+ // param[3]: vfp: 14
+ // param[4]: vs + vbp - 1: 11
+ // param[5]: hbp: 4
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc4,
+ 0x10, 0x90, 0x92, 0x0e, 0x0b, 0x04);
+
+ mipi_dsi_msleep(&dsi_ctx, 1);
+
+ // SET_R_GAMMA (set red gamma output voltage)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc8,
+ 0x7e, 0x76, 0x68, 0x57, 0x4c, 0x39, 0x3a, 0x23,
+ 0x3d, 0x3d, 0x40, 0x61, 0x54, 0x64, 0x5d, 0x62,
+ 0x5a, 0x50, 0x32, 0x7e, 0x76, 0x68, 0x57, 0x4c,
+ 0x39, 0x3a, 0x23, 0x3d, 0x3d, 0x40, 0x61, 0x54,
+ 0x64, 0x5d, 0x62, 0x5a, 0x50, 0x32);
+
+ // SET_GIP_L (CGOUTx_L signal mapping, gs_panel = 0)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd0,
+ 0x1f, 0x0a, 0x08, 0x06, 0x04, 0x1f, 0x00, 0x1f,
+ 0x17, 0x1f, 0x18, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f);
+
+ // SET_GIP_R (CGOUTx_R signal mapping, gs_panel = 0)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd1,
+ 0x1f, 0x0b, 0x09, 0x07, 0x05, 0x1f, 0x01, 0x1f,
+ 0x17, 0x1f, 0x18, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f);
+
+ // SETGIP1 (GIP signal timing 1)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd4,
+ 0x10, 0x00, 0x00, 0x03, 0x60, 0x05, 0x10, 0x00,
+ 0x02, 0x06, 0x68, 0x00, 0x6c, 0x00, 0x00, 0x00,
+ 0x00, 0x06, 0x78, 0x71, 0x07, 0x06, 0x68, 0x0c,
+ 0x25, 0x00, 0x63, 0x03, 0x00);
+
+ // SETGIP2 (GIP signal timing 1)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd5,
+ 0x20, 0x10, 0x8c, 0x18, 0x00, 0x80, 0x00, 0x08,
+ 0x00, 0x00, 0x06, 0x60, 0x00, 0x81, 0x70, 0x02,
+ 0x30, 0x01, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00,
+ 0x03, 0x60, 0x83, 0x90, 0x00, 0x00, 0x03, 0x4f,
+ 0x03, 0x00, 0x1f, 0x3f, 0x00, 0x00, 0x00, 0x00);
+
+ jd9161z_switch_page(&dsi_ctx, 0x04);
+
+ mipi_dsi_msleep(&dsi_ctx, 1);
+
+ // Unknown command
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0,
+ 0x24, 0x01);
+
+ mipi_dsi_msleep(&dsi_ctx, 1);
+
+ jd9161z_switch_page(&dsi_ctx, 0x02);
+
+ mipi_dsi_msleep(&dsi_ctx, 1);
+
+ // SETRGBCYC2 (RGB IF source switch control timing)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc1,
+ 0x71);
+
+ mipi_dsi_msleep(&dsi_ctx, 1);
+
+ // Unknown command
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2,
+ 0x00, 0x18, 0x08, 0x1e, 0x25, 0x7c, 0xc7);
+
+ mipi_dsi_msleep(&dsi_ctx, 1);
+
+ jd9161z_switch_page(&dsi_ctx, 0x00);
+
+ mipi_dsi_msleep(&dsi_ctx, 1);
+
+ mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+
+ mipi_dsi_msleep(&dsi_ctx, 1);
+
+ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+
+ mipi_dsi_msleep(&dsi_ctx, 120);
+
+ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+
+ mipi_dsi_msleep(&dsi_ctx, 5);
+
+ return dsi_ctx.accum_err;
+};
+
+static const struct jadard_panel_desc zhunyi_z40046_ctc_desc = {
+ .mode = {
+ .clock = (480 + 20 + 20 + 20) * (800 + 14 + 4 + 8) * 60 / 1000,
+
+ .hdisplay = 480,
+ .hsync_start = 480 + 20,
+ .hsync_end = 480 + 20 + 20,
+ .htotal = 480 + 20 + 20 + 20,
+
+ .vdisplay = 800,
+ .vsync_start = 800 + 14,
+ .vsync_end = 800 + 14 + 4,
+ .vtotal = 800 + 14 + 4 + 8,
+
+ .width_mm = 52,
+ .height_mm = 86,
+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ .lanes = 2,
+ .format = MIPI_DSI_FMT_RGB888,
+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_LPM,
+ .lp11_before_reset = true,
+ .reset_before_power_off_vcioo = true,
+ .vcioo_to_lp11_delay_ms = 5,
+ .lp11_to_reset_delay_ms = 10,
+ .backlight_off_to_display_off_delay_ms = 100,
+ .display_off_to_enter_sleep_delay_ms = 50,
+ .enter_sleep_to_reset_down_delay_ms = 100,
+ .init = zhunyi_z40046_init_cmds_ctc,
+};
+
+// Sequence retrieved from Xiaomi Mi Smart Clock x04g kernel in boot.bin
+static int zhunyi_z40046_init_cmds_boe(struct jadard *jadard_data)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard_data->dsi };
+
+ // Init configuration sequence
+ jd9161z_switch_page(&dsi_ctx, 0x00);
+ jd9161z_enable_standard_cmds(&dsi_ctx);
+
+ // GAMMA_SET (pos/neg voltage of gamma power)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb7,
+ 0x10, 0x08, 0x42, 0x00, 0x56, 0x42);
+
+ // DCDC_SEL (power mode and charge pump settings)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbb,
+ 0x52, 0x0f, 0xb2, 0xb2, 0xb2, 0xc0, 0xd0, 0x50,
+ 0xf0, 0x40, 0x50);
+
+ // VDDD_CTRL (control logic voltage setting)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbc,
+ 0x73, 0x14);
+
+ // SETRGBCYC (display waveform cycle of RGB mode)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc3,
+ 0x04, 0x07, 0x0b, 0x17, 0x00, 0x17, 0x04, 0x17,
+ 0x17, 0x00, 0x17, 0x82, 0x0b, 0x82);
+
+ // SET_TCON (timing control setting)
+ // param[0][5:4] + param[1]: number of panel lines / 2
+ // 400 = 01 1001 0000 -> 0x10, 0x90
+ // param[2]: scan line time width
+ // param[3]: vfp: 14
+ // param[4]: vs + vbp - 1: 11
+ // param[5]: hbp: 6
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc4,
+ 0x10, 0x90, 0x92, 0x0e, 0x06);
+
+ // SET_R_GAMMA (set red gamma output voltage)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc8,
+ 0x7f, 0x78, 0x69, 0x56, 0x47, 0x33, 0x34, 0x1e,
+ 0x3b, 0x3e, 0x43, 0x67, 0x5d, 0x6f, 0x68, 0x70,
+ 0x6a, 0x61, 0x3c, 0x7f, 0x78, 0x69, 0x56, 0x47,
+ 0x33, 0x34, 0x1e, 0x3b, 0x3e, 0x43, 0x67, 0x5d,
+ 0x6f, 0x68, 0x70, 0x6a, 0x61, 0x3c);
+
+ // SET_GIP_L (CGOUTx_L signal mapping, gs_panel = 0)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd0,
+ 0x1f, 0x1e, 0x07, 0x05, 0x01, 0x1f, 0x1f, 0x1f,
+ 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f);
+
+ // SET_GIP_R (CGOUTx_R signal mapping, gs_panel = 0)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd1,
+ 0x1f, 0x1e, 0x06, 0x04, 0x00, 0x1f, 0x1f, 0x1f,
+ 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f);
+
+ // SET_GIP_L_GS (CGOUTx_L signal mapping, gs_panel = 1)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd2,
+ 0x1f, 0x1f, 0x04, 0x06, 0x00, 0x1e, 0x1f, 0x1f,
+ 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f);
+
+ // SET_GIP_R_GS (CGOUTx_R signal mapping, gs_panel = 1)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd3,
+ 0x1f, 0x1f, 0x05, 0x07, 0x01, 0x1e, 0x1f, 0x1f,
+ 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f);
+
+ // SETGIP1 (GIP signal timing 1)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd4,
+ 0x30, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00,
+ 0x03, 0x03, 0x68, 0x03, 0x40, 0x05, 0x00, 0x00,
+ 0x00, 0xcc, 0x2d, 0x31, 0x02, 0x03, 0x68, 0x0c,
+ 0x25, 0x00, 0x63, 0x03, 0x00);
+
+ // SETGIP2 (GIP signal timing 1)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd5,
+ 0x30, 0x08, 0x80, 0x18, 0x00, 0x00, 0x00, 0x18,
+ 0x00, 0x00, 0x06, 0x60, 0x00, 0x07, 0x50, 0x00,
+ 0x33, 0xc0, 0x00, 0x60, 0xc0, 0x00, 0x00, 0x00,
+ 0x03, 0x60, 0x06, 0x10, 0x00, 0x00, 0x0f, 0x4f,
+ 0x00, 0x10, 0x1f, 0x3f);
+
+ jd9161z_switch_page(&dsi_ctx, 0x02);
+
+ // SETRGBCYC2 (RGB IF source switch control timing)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc1,
+ 0x60);
+
+ // Unknown command
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2,
+ 0x00, 0x18, 0x08, 0x1e, 0x25, 0x7c, 0xc7);
+
+ jd9161z_switch_page(&dsi_ctx, 0x00);
+
+ // GAS_CTRL (GAS function control)
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbe,
+ 0x4e);
+
+ mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+
+ mipi_dsi_msleep(&dsi_ctx, 120);
+
+ mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+
+ mipi_dsi_msleep(&dsi_ctx, 10);
+
+ return dsi_ctx.accum_err;
+};
+
+static const struct jadard_panel_desc zhunyi_z40046_boe_desc = {
+ .mode = {
+ .clock = (480 + 20 + 20 + 20) * (800 + 14 + 4 + 8) * 60 / 1000,
+
+ .hdisplay = 480,
+ .hsync_start = 480 + 20,
+ .hsync_end = 480 + 20 + 20,
+ .htotal = 480 + 20 + 20 + 20,
+
+ .vdisplay = 800,
+ .vsync_start = 800 + 14,
+ .vsync_end = 800 + 14 + 4,
+ .vtotal = 800 + 14 + 4 + 8,
+
+ .width_mm = 52,
+ .height_mm = 86,
+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ .lanes = 2,
+ .format = MIPI_DSI_FMT_RGB888,
+ .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_LPM,
+ .lp11_before_reset = true,
+ .reset_before_power_off_vcioo = true,
+ .vcioo_to_lp11_delay_ms = 5,
+ .lp11_to_reset_delay_ms = 10,
+ .backlight_off_to_display_off_delay_ms = 100,
+ .display_off_to_enter_sleep_delay_ms = 50,
+ .enter_sleep_to_reset_down_delay_ms = 100,
+ .init = zhunyi_z40046_init_cmds_boe,
+};
+
static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
{
struct device *dev = &dsi->dev;
@@ -1707,6 +2012,14 @@ static const struct of_device_id jadard_of_match[] = {
.compatible = "taiguanck,xti05101-01a",
.data = &taiguan_xti05101_01a_desc
},
+ {
+ .compatible = "zhunyikeji,z40046-ctc",
+ .data = &zhunyi_z40046_ctc_desc
+ },
+ {
+ .compatible = "zhunyikeji,z40046-boe",
+ .data = &zhunyi_z40046_boe_desc
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jadard_of_match);
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v2 2/3] pwm: rp1: Add RP1 PWM controller driver
From: Uwe Kleine-König @ 2026-04-17 10:50 UTC (permalink / raw)
To: Andrea della Porta
Cc: linux-pwm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Florian Fainelli, Broadcom internal kernel review list,
devicetree, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Naushir Patuck, Stanimir Varbanov, mbrugger
In-Reply-To: <aeH373a_xmr6fnAy@apocalypse>
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Hello Andrea,
On Fri, Apr 17, 2026 at 11:05:51AM +0200, Andrea della Porta wrote:
> On 15:48 Thu 16 Apr , Uwe Kleine-König wrote:
> > one thing I forgot to ask: Is there a public reference manual covering
> > the hardware. If yes, please add a link at the top of the driver.
>
> Sort of, it's already reported in this driver top comment (Datasheet: tag).
> The PWM controller is part of the RP1 chipset and you can find its description
> under the PWM section. This is not a full-fledged datasheet but the registers
> for the controller are somewhow documented.
Ah, then I missed something different than I thought :-)
> > On Thu, Apr 16, 2026 at 12:30:43PM +0200, Andrea della Porta wrote:
> > > On 19:31 Fri 10 Apr , Uwe Kleine-König wrote:
> > > > I assume there is a glitch if I update two channels and the old
> > > > configuration of the first channel ends while I'm in the middle of
> > > > configuring the second?
> > >
> > > The configuration registers are per-channel but the update flag is global.
> > > I don't have details of the hw insights, my best guess is that anything that
> > > you set in the registers before updating the flag will take effect, so there
> > > should be no glitches.
> >
> > Would be great if you could test that. (Something along the lines of:
> > configure a very short period and wait a bit to be sure the short
> > configuration is active. Configure something with a long period and wait
> > shortly to be sure that the long period started, then change the duty,
> > toggle the update bit and modify a 2nd channel without toggling update
> > again. Then check the output of the 2nd channel after the first
> > channel's period ended.
>
> I stand corrected here: after some more investigation it seems that only the
> enable/disable (plus osme other not currently used registers) depends on the
> global update flag, while the period and duty per-channel registers are
> independtly updatable while they are latched on the end of (specific channel)
> period strobe.
> I'd say that this should avoid any cross-channel glitches since they are managed
> independently. Unfortunately I'm not able to test this with my current (and
> rather old) equipment, this would require at least an external trigger channel.
> Regarding the setup of a new value exactly during the strobe: I think this is
> quite hard to achieve.
To sum up: period and duty_cycle changes might result in glitches unless
the channel is disabled. This is ok, please just document it.
The purpose of the update flag then is only to start several channels in
sync? What happens if sync is asserted while a disabled channel didn't
complete the last period yet?
Maybe it's worth to test the following procedure for updating duty and
period:
disable channel
configure duty
configure period
enable
set update flag
Assumint disable is delayed until the end of the currently running
period, the effect of this procedure might be that no glitch happens if
the update flag is asserted before the currently running period ends and
the anormality is reduced to a longer inactive state if the updates are
not that lucky (in contrast to more severe glitches).
If you can configure a short and a long period that is distinguishable
"manually" with an LED I think this should be testable even without
further equipment.
> > > > > + if (ticks > U32_MAX)
> > > > > + ticks = U32_MAX;
> > > > > + wfhw->period_ticks = ticks;
> > > >
> > > > What happens if wf->period_length_ns > 0 but ticks == 0?
> > >
> > > I've added a check, returning 1 to signal teh round-up, and a minimum tick of 1
> > > in this case.
> >
> > Sounds good. Are you able to verify that there is no +1 missing in the
> > calculation, e.g. using 1 as register value really gives you a period of
> > 1 tick and not 2?
>
> You are right. The scope reveals there's always one extra (low signal) tick at the
> end of each period.
So the hardware cannot do 100% relative duty, right? Please document
that.
> Let's say that teh user want 10 tick period, we have to use
> 9 instead to account for the extra tick at the end, so that the complete period
> contains that extra tick?
I would describe that a bit differently, but in general: yes.
The more straight forward description is that setting
RP1_PWM_RANGE(pwm->hwpwm) := x
results in a period of x + 1 ticks.
> This also means that if we ask for 100% duty cycle, the output waveform will
> have the high part of the signal lasting one tick less than expected.a I guess
> this is the accepted compromise.
I assume you considered something like:
RP1_PWM_RANGE(pwm->hwpwm) := 17
RP1_PWM_DUTY(pwm->hwpwm) := 18
to get a 100% relative duty?
If this doesn't work that means that this has to be formalized in the
callbacks. That is the fromhw function has to always report
duty_length_ns less than period_length_ns.
> OTOH, the minimum tick period would be 2 tick, less than that will otherwise
> degenerate in a disabled channel.
It's expected that in general for a period_length of 1 tick you can only
have 0% and 100% relative duty. IIUC for this hardware you cannot do the
100% case so there is only a single valid duty_length for period_length
= 1 tick.
I think it would be more complicated to consistently filter out
period_length = 1 tick in the driver than to just accept the conceptual
limitations. (Otherwise: What would you report in the fromhw callback if
period_length = 1 tick is configured in wfhw? Would you refuse to commit
that wfhw to hardware in .write_waveform()? The pwm core handles that
just fine and consumers have all the means to detect and prevent that if
they care enough.)
> > > > On remove you miss to balance the call to clk_prepare_enable() (if no
> > > > failed call to clk_prepare_enable() in rp1_pwm_resume() happend).
> > >
> > > Since this driver now exports a syscon, it's only builtin (=Y) so
> > > it cannot be unloaded.
> > > I've also avoided the .remove callback via .suppress_bind_attrs.
> >
> > Oh no, please work cleanly here and make the driver unbindable. This
> > yields better code quality and also helps during development and
> > debugging.
>
> I wish to, but the issue here is that this driver exports a syscon via
> of_syscon_register_regmap() which I think doesn't have the unregister
> counterpart. So the consumer will break in case we can unbind/unload
> the module and the syscon will leak.
> If you have any alternative I'll be glad to discuss.
My (not so well articulated) point is: Please be stringent about clock
handling to not bank up technical dept more than necessary and such that
the driver can be made unbindable if and when syscons grow
that feature. Optionally wail at the syscon guys :-)
Best regards
Uwe
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^ permalink raw reply
* [PATCH 0/2] Enable dual OV5640 cameras on i.MX8MQ EVK board
From: Robby Cai @ 2026-04-17 11:01 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, festevam, shawnguo,
martin.kepplinger
Cc: kernel, devicetree, imx, linux-arm-kernel, linux-kernel
This series adds dual-camera support for the i.MX8MQ EVK board.
Patch 1 fixes the MIPI CSI clock configuration in the i.MX8MQ device tree.
The previous configuration violated a timing constraint defined in the
i.MX8MQ Reference Manual:
"The frequency of clk must be exactly equal to or greater than the RX
byte clock coming from the RX DPHY."
This mismatch could lead to unstable operation, observed as intermittent
capture failures. The updated clock ratios align with those used in NXP��s
downstream BSP and were verified to resolve the issue.
Patch 2 enables full MIPI CSI support and dual OV5640 camera operation on
the i.MX8MQ EVK. This includes enabling both CSI controllers and their
corresponding MIPI CSI-2 host interfaces, as well as adding two OV5640
sensor nodes on I2C1 and I2C2.
Note:
This series depends on patch [1] currently under review, as well as commit
6d79bb8fd2aa ("media: imx8mq-mipi-csi2: Explicitly release reset").
[1] https://lore.kernel.org/imx/20260417080851.489303-1-robby.cai@nxp.com/
Robby Cai (2):
arm64: dts: imx8mq: Correct MIPI CSI clocks
arm64: dts: imx8mq-evk: Enable MIPI CSI and dual OV5640 cameras
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 149 +++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 4 +-
2 files changed, 151 insertions(+), 2 deletions(-)
--
2.37.1
^ permalink raw reply
* [PATCH 1/2] arm64: dts: imx8mq: Correct MIPI CSI clocks
From: Robby Cai @ 2026-04-17 11:01 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, festevam, shawnguo,
martin.kepplinger
Cc: kernel, devicetree, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <20260417110200.753678-1-robby.cai@nxp.com>
CSI capture may intermittently fail due to mismatched clock rates. The
previous configuration violated the timing requirement stated in the
i.MX8MQ Reference Manual:
"The frequency of clk must be exactly equal to or greater than the RX
byte clock coming from the RX DPHY."
Update the clock configuration to ensure that the CSI core clock rate is
equal to or greater than the incoming DPHY byte clock. The updated clock
ratios are consistent with those used in NXP's downstream BSP.
Fixes: bcadd5f66c2a ("arm64: dts: imx8mq: add mipi csi phy and csi bridge descriptions")
Cc: stable@vger.kernel.org
Signed-off-by: Robby Cai <robby.cai@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 6a25e219832c..165716d08e64 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1377,7 +1377,7 @@ mipi_csi1: csi@30a70000 {
assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
<&clk IMX8MQ_CLK_CSI1_PHY_REF>,
<&clk IMX8MQ_CLK_CSI1_ESC>;
- assigned-clock-rates = <266000000>, <333000000>, <66000000>;
+ assigned-clock-rates = <133000000>, <100000000>, <66000000>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_SYS2_PLL_1000M>,
<&clk IMX8MQ_SYS1_PLL_800M>;
@@ -1429,7 +1429,7 @@ mipi_csi2: csi@30b60000 {
assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
<&clk IMX8MQ_CLK_CSI2_PHY_REF>,
<&clk IMX8MQ_CLK_CSI2_ESC>;
- assigned-clock-rates = <266000000>, <333000000>, <66000000>;
+ assigned-clock-rates = <133000000>, <100000000>, <66000000>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_SYS2_PLL_1000M>,
<&clk IMX8MQ_SYS1_PLL_800M>;
--
2.37.1
^ permalink raw reply related
* [PATCH 2/2] arm64: dts: imx8mq-evk: Enable MIPI CSI and dual OV5640 cameras
From: Robby Cai @ 2026-04-17 11:02 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, festevam, shawnguo,
martin.kepplinger
Cc: kernel, devicetree, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <20260417110200.753678-1-robby.cai@nxp.com>
Enable CSI1/CSI2 bridges and the MIPI-CSI host interfaces, and add
two OV5640 MIPI camera sensor nodes on I2C1 and I2C2.
The resulting camera pipelines are as follows:
- OV5640 on I2C2 -> MIPI CSI1 -> CSI1
- OV5640 on I2C1 -> MIPI CSI2 -> CSI2
Signed-off-by: Robby Cai <robby.cai@nxp.com>
---
Tested with following commands:
On CSI1:
media-ctl -d 0 -l "'ov5640 1-003c':0 -> 'imx8mq-mipi-csi2 30a70000.csi':0 [1]"
media-ctl -d 0 -V "'ov5640 1-003c':0 [fmt:YUYV8_1X16/640x480 field:none]"
media-ctl -d 0 -V "'imx8mq-mipi-csi2 30a70000.csi':0 [fmt:YUYV8_1X16/640x480 field:none]"
media-ctl -d 0 -V "'csi':0 [fmt:YUYV8_1X16/640x480 field:none]"
v4l2-ctl -d 0 --set-fmt-video=width=640,height=480,pixelformat=YUYV --stream-mmap
On CSI2:
media-ctl -d 1 -l "'ov5640 0-003c':0 -> 'imx8mq-mipi-csi2 30b60000.csi':0 [1]"
media-ctl -d 1 -V "'ov5640 0-003c':0 [fmt:YUYV8_1X16/640x480 field:none]"
media-ctl -d 1 -V "'imx8mq-mipi-csi2 30b60000.csi':0 [fmt:YUYV8_1X16/640x480 field:none]"
media-ctl -d 1 -V "'csi':0 [fmt:YUYV8_1X16/640x480 field:none]"
v4l2-ctl -d 1 --set-fmt-video=width=640,height=480,pixelformat=YUYV --stream-mmap
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 149 +++++++++++++++++++
1 file changed, 149 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index d48f901487d4..8bdfbfebfcc9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -6,6 +6,8 @@
/dts-v1/;
+#include <dt-bindings/media/video-interfaces.h>
+
#include "imx8mq.dtsi"
/ {
@@ -50,6 +52,20 @@ reg_usdhc2_vmmc: regulator-vsd-3v3 {
enable-active-high;
};
+ reg_1v5: regulator-1v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_1V5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ reg_2v8: regulator-2v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_2V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
buck2_reg: regulator-buck2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_buck2>;
@@ -172,6 +188,14 @@ &A53_3 {
cpu-supply = <&buck2_reg>;
};
+&csi1 {
+ status = "okay";
+};
+
+&csi2 {
+ status = "okay";
+};
+
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
status = "okay";
@@ -330,12 +354,101 @@ vgen6_reg: vgen6 {
};
};
};
+
+ camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_camera2_pwdn>;
+ clocks = <&clk IMX8MQ_CLK_CLKO2>;
+ clock-names = "xclk";
+ assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
+ assigned-clock-rates = <20000000>;
+ powerdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ DOVDD-supply = <&sw4_reg>;
+ AVDD-supply = <®_2v8>;
+ DVDD-supply = <®_1v5>;
+ status = "okay";
+
+ port {
+ camera2_ep: endpoint {
+ remote-endpoint = <&mipi_csi2_in_ep>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_camera1_pwdn>, <&pinctrl_camera_rst>;
+ clocks = <&clk IMX8MQ_CLK_CLKO2>;
+ clock-names = "xclk";
+ assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
+ assigned-clock-rates = <20000000>;
+ powerdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ DOVDD-supply = <&sw4_reg>;
+ AVDD-supply = <®_2v8>;
+ DVDD-supply = <®_1v5>;
+ status = "okay";
+
+ port {
+ camera1_ep: endpoint {
+ remote-endpoint = <&mipi_csi1_in_ep>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
};
&lcdif {
status = "okay";
};
+&mipi_csi1 {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+
+ mipi_csi1_in_ep: endpoint {
+ remote-endpoint = <&camera1_ep>;
+ data-lanes = <1 2>;
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+ };
+ };
+ };
+};
+
+&mipi_csi2 {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+
+ mipi_csi2_in_ep: endpoint {
+ remote-endpoint = <&camera2_ep>;
+ data-lanes = <1 2>;
+ bus-type = <4>;
+ };
+ };
+ };
+};
+
&mipi_dsi {
#address-cells = <1>;
#size-cells = <0>;
@@ -532,12 +645,41 @@ &wdog1 {
};
&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ /* MCLK for cameras on both CSI1 and CSI2 */
+ MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59
+ >;
+ };
+
pinctrl_buck2: vddarmgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
>;
};
+ pinctrl_camera1_pwdn: camera1pwdngrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
+ >;
+ };
+
+ pinctrl_camera2_pwdn: camera2pwdngrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19
+ >;
+ };
+
+ pinctrl_camera_rst: camerarstgrp {
+ fsl,pins = <
+ /* Reset PIN for cameras on both CSI1 and CSI2 */
+ MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
+ >;
+ };
+
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
@@ -565,6 +707,13 @@ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
+ >;
+ };
+
pinctrl_ir: irgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f
--
2.37.1
^ permalink raw reply related
* [PATCH v2] ASoC: dt-bindings: cdns: Convert xtfpga I2S to dt-schema
From: Chaitanya Sabnis @ 2026-04-17 11:04 UTC (permalink / raw)
To: Max Filippov, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-sound, devicetree, linux-kernel, Chaitanya Sabnis
Convert the xtfpga I2S controller plain-text binding
documentation to standard dt-schema (YAML).
The hardware requires exactly one memory region, one interrupt line,
and one phandle to the master clock. Verified these constraints against
the driver source in sound/soc/xtensa/xtfpga-i2s.c.
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chaitanya Sabnis <chaitanya.msabnis@gmail.com>
---
.../bindings/sound/cdns,xtfpga-i2s.txt | 18 -------
.../bindings/sound/cdns,xtfpga-i2s.yaml | 48 +++++++++++++++++++
2 files changed, 48 insertions(+), 18 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt
create mode 100644 Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml
diff --git a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt
deleted file mode 100644
index 860fc0da39c0..000000000000
--- a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-Bindings for I2S controller built into xtfpga Xtensa bitstreams.
-
-Required properties:
-- compatible: shall be "cdns,xtfpga-i2s".
-- reg: memory region (address and length) with device registers.
-- interrupts: interrupt for the device.
-- clocks: phandle to the clk used as master clock. I2S bus clock
- is derived from it.
-
-Examples:
-
- i2s0: xtfpga-i2s@d080000 {
- #sound-dai-cells = <0>;
- compatible = "cdns,xtfpga-i2s";
- reg = <0x0d080000 0x40>;
- interrupts = <2 1>;
- clocks = <&cdce706 4>;
- };
diff --git a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml
new file mode 100644
index 000000000000..9617acef3f0c
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/cdns,xtfpga-i2s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: I2S controller built into xtfpga Xtensa bitstreams
+
+maintainers:
+ - Max Filippov <jcmvbkbc@gmail.com>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: cdns,xtfpga-i2s
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: phandle to the clk used as master clock. I2S bus clock is derived from it.
+
+ "#sound-dai-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2s@d080000 {
+ compatible = "cdns,xtfpga-i2s";
+ reg = <0x0d080000 0x40>;
+ interrupts = <2 1>;
+ clocks = <&cdce706 4>;
+ #sound-dai-cells = <0>;
+ };
--
2.43.0
^ permalink raw reply related
* Re: [PATCH 2/2] arm64: dts: qcom: glymur: Add crypto engine
From: Konrad Dybcio @ 2026-04-17 11:06 UTC (permalink / raw)
To: Harshal Dev, Thara Gopinath, Herbert Xu, David S. Miller,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio, Dmitry Baryshkov, johannes.goede
Cc: Neeraj Soni, Kuldeep Singh, Abel Vesa, linux-arm-msm,
linux-crypto, devicetree, linux-kernel
In-Reply-To: <b8f781b0-f7ba-407e-8603-ca504535a894@oss.qualcomm.com>
On 4/17/26 11:22 AM, Harshal Dev wrote:
> Hi,
>
> On 4/16/2026 7:10 PM, Konrad Dybcio wrote:
>> On 4/16/26 3:07 PM, Harshal Dev wrote:
>>> On Glymur, there is a crypto engine IP block similar to the ones found on
>>> SM8x50 platforms.
>>>
>>> Describe the crypto engine and its BAM.
>>>
>>> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/glymur.dtsi | 26 ++++++++++++++++++++++++++
>>> 1 file changed, 26 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>> index f23cf81ddb77..e8c796f2c572 100644
>>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>> @@ -3675,6 +3675,32 @@ pcie3b_phy: phy@f10000 {
>>> status = "disabled";
>>> };
>>>
>>> + cryptobam: dma-controller@1dc4000 {
>>> + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
>>> + reg = <0x0 0x01dc4000 0x0 0x28000>;
>>> + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
>>> + #dma-cells = <1>;
>>> + iommus = <&apps_smmu 0x480 0x0>,
>>> + <&apps_smmu 0x481 0x0>;
>>
>> It seems like these aren't the right SIDs on this platform.. Have you
>> tested this patch on hw?
>
> Thanks a lot for catching this Konrad. The correct SID pairs are <0x80 0x0> and <0x81 0x0>.
> (I hope I don't need to pad them?)
No, you don't
>
> Unfortunately, I could only validate driver probe on my limited ramdisk environment:
>
> [ 4.583802] qcrypto 1dfa000.crypto: Crypto device found, version 5.9.1
>
> I was waiting for Wenjia to run the full crypto user-space test suite once. I'll update the
> SIDs and wait for a Tested-by from him.
Thanks
I think you should be able to get some life out of the crypto engine
via CONFIG_EXPERT=y && CONFIG_CRYPTO_SELFTESTS=y (which btw +Hans
mentioned reports a failure on Hamoa)
Konrad
^ permalink raw reply
* Re: [PATCH 1/5] dt-bindings: interrupt-controller: Add support for secure donated SGIs
From: Sudeep Holla @ 2026-04-17 11:07 UTC (permalink / raw)
To: Rob Herring
Cc: Krzysztof Kozlowski, Conor Dooley, Marc Zyngier, Sudeep Holla,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <CAL_JsqLdSi2x-KibY7WXTEot8Bj=54XeE1VACtLTujxn0VTxRw@mail.gmail.com>
On Thu, Apr 16, 2026 at 09:02:27AM -0500, Rob Herring wrote:
> On Thu, Apr 16, 2026 at 8:09 AM Sudeep Holla <sudeep.holla@kernel.org> wrote:
> >
> > On Thu, Apr 16, 2026 at 07:11:46AM -0500, Rob Herring wrote:
> > > On Sun, Apr 12, 2026 at 06:04:37PM +0100, Sudeep Holla wrote:
> > > > In GICv3, SGI security is defined by interrupt grouping and configuration
> > > > rather than by SGI number alone. Linux conventionally reserves SGIs 0-7
> > > > for non-secure internal kernel IPIs, while higher SGIs is assumed to be
> > > > owned/stolen by the Secure world unless explicitly made available.
> > > >
> > > > Document secure donated SGI interrupt specifiers for the GICv3 binding.
> > > > It describes "arm,secure-donated-ns-sgi-ranges" for SGIs donated by the
> > > > secure world to non-secure software. It excludes SGIs 0-7, which are
> > > > already used by the kernel for internal IPI purposes.
> > > >
> > > > Signed-off-by: Sudeep Holla <sudeep.holla@kernel.org>
> > > > ---
> > > > .../bindings/interrupt-controller/arm,gic-v3.yaml | 27 +++++++++++++++++++++-
> > > > include/dt-bindings/interrupt-controller/arm-gic.h | 1 +
> > > > 2 files changed, 27 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
> > > > index bfd30aae682b..664727d071c9 100644
> > > > --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
> > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
> > > > @@ -45,17 +45,24 @@ description: |
> > > >
> > > > The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
> > > > interrupts, 2 for interrupts in the Extended SPI range, 3 for the
> > > > - Extended PPI range. Other values are reserved for future use.
> > > > + Extended PPI range, and 4 for SGI interrupts. Other values are
> > > > + reserved for future use.
> > > >
> > > > The 2nd cell contains the interrupt number for the interrupt type.
> > > > SPI interrupts are in the range [0-987]. PPI interrupts are in the
> > > > range [0-15]. Extended SPI interrupts are in the range [0-1023].
> > > > Extended PPI interrupts are in the range [0-127].
> > > >
> > > > + SGI interrupts are in the range [8-15] which overlaps with the SGIs
> > > > + assigned to/reserved for the secure world but donated to the non
> > > > + secure world to use. Refer "arm,secure-donated-ns-sgi-ranges" for
> > > > + more details.
> > > > +
> > > > The 3rd cell is the flags, encoded as follows:
> > > > bits[3:0] trigger type and level flags.
> > > > 1 = edge triggered
> > > > 4 = level triggered
> > > > + SGIs are edge triggered and must be described as such.
> > > >
> > > > The 4th cell is a phandle to a node describing a set of CPUs this
> > > > interrupt is affine to. The interrupt must be a PPI, and the node
> > > > @@ -136,6 +143,24 @@ description: |
> > > > - $ref: /schemas/types.yaml#/definitions/uint32
> > > > - $ref: /schemas/types.yaml#/definitions/uint64
> > > >
> > > > + arm,secure-donated-ns-sgi-ranges:
> > > > + description:
> > > > + A list of pairs <sgi span>, where "sgi" is the first SGI INTID of a
> > > > + range donated by the secure side to non-secure software, and "span" is
> > > > + the size of that range. Multiple ranges can be provided.
> > > > +
> > > > + SGIs described by interrupt specifiers with type 4 (SGI) must fall
> > > > + within one of these ranges. SGIs(0-7) reserved by non-secure world
> > > > + for internal IPIs must not be listed here. "sgi" must be in the
> > > > + range [8-15], "span" must be in the range [1-8], and the range must
> > > > + not extend past SGI 15.
> > > > + $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > > > + items:
> > >
> > > As a matrix, you need:
> > >
> > > items:
> > > items:
> > > - ...
> > > - ...
> > >
> > > However, given this is at most 8 entries, I would just do an array:
> > >
> > > minItems: 1
> > > maxItems: 8
> > > uniqueItems: true
> > > items:
> > > minimum: 8
> > > maximum: 15
> > >
> >
> > Makes sense.
> >
> > > Unless we need more flexibility in GICv5?
> > >
> >
> > IIUC, there are not SGIs in GICv5 and we may need to use one software PPI
> > as a replacement for SGIs. LPIs are used for IPIs.
> >
> > I am assuming Marc will soon post his opinion/rejection on this series 😉
> > based on some offline discussion we had with respect to how it fits with
> > GICv5.
> >
> > > Is there an example we can stick this property into so it gets tested?
> > >
> >
> > Not sure if [1] serves as an example or you are looking for something else.
>
> In the binding example, but don't add a whole new example for it.
>
> Did [1] pass validation? If it did, it shouldn't have and I need to
> investigate. If you didn't run it, then that would be the reason I
> want it in the binding example.
>
By validation, do you mean `dtbs_check` ? If so, yes I didn't see any
warnings. But it is likely that I might have missed some flags as I was
doing `dtbs_check` and `dt_bindings_check` after very long time. I will
check again. But the commands did produce warnings in other files.
--
Regards,
Sudeep
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: imx8mq: Correct MIPI CSI clocks
From: Frank Li @ 2026-04-17 11:22 UTC (permalink / raw)
To: Robby Cai
Cc: robh, krzk+dt, conor+dt, s.hauer, festevam, shawnguo,
martin.kepplinger, kernel, devicetree, imx, linux-arm-kernel,
linux-kernel
In-Reply-To: <20260417110200.753678-2-robby.cai@nxp.com>
On Fri, Apr 17, 2026 at 07:01:59PM +0800, Robby Cai wrote:
> CSI capture may intermittently fail due to mismatched clock rates. The
> previous configuration violated the timing requirement stated in the
> i.MX8MQ Reference Manual:
>
> "The frequency of clk must be exactly equal to or greater than the RX
> byte clock coming from the RX DPHY."
>
> Update the clock configuration to ensure that the CSI core clock rate is
> equal to or greater than the incoming DPHY byte clock.
You reduce clock, how to make sure it >= ?
> The updated clock
> ratios are consistent with those used in NXP's downstream BSP.
"downstream BSP" is not solidate reference for clock rate, it'd better
refer to date sheet, dose datasheet require such frequecy
Frank
>
> Fixes: bcadd5f66c2a ("arm64: dts: imx8mq: add mipi csi phy and csi bridge descriptions")
> Cc: stable@vger.kernel.org
> Signed-off-by: Robby Cai <robby.cai@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 6a25e219832c..165716d08e64 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1377,7 +1377,7 @@ mipi_csi1: csi@30a70000 {
> assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
> <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
> <&clk IMX8MQ_CLK_CSI1_ESC>;
> - assigned-clock-rates = <266000000>, <333000000>, <66000000>;
> + assigned-clock-rates = <133000000>, <100000000>, <66000000>;
> assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
> <&clk IMX8MQ_SYS2_PLL_1000M>,
> <&clk IMX8MQ_SYS1_PLL_800M>;
> @@ -1429,7 +1429,7 @@ mipi_csi2: csi@30b60000 {
> assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
> <&clk IMX8MQ_CLK_CSI2_PHY_REF>,
> <&clk IMX8MQ_CLK_CSI2_ESC>;
> - assigned-clock-rates = <266000000>, <333000000>, <66000000>;
> + assigned-clock-rates = <133000000>, <100000000>, <66000000>;
> assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
> <&clk IMX8MQ_SYS2_PLL_1000M>,
> <&clk IMX8MQ_SYS1_PLL_800M>;
> --
> 2.37.1
>
^ permalink raw reply
* Re: [PATCH 05/40] arm64: dts: rockchip: Add frl-enable-gpios to rk3576-luckfox-core3576
From: Heiko Stuebner @ 2026-04-17 11:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Cristian Ciocaltea
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-5-a19c0dd8c9f6@collabora.com>
Hi Cristian,
the comments below apply sort of to all patches in that series.
Am Freitag, 17. April 2026, 11:24:39 Mitteleuropäische Sommerzeit schrieb Cristian Ciocaltea:
> The board exposes the GPIO4_C6 line to control the voltage bias on the
> HDMI data lines. It must be asserted when operating in HDMI 2.1 FRL
> mode and deasserted for HDMI 1.4/2.0 TMDS mode.
>
> Wire up the HDMI node to the GPIO line using the frl-enable-gpios
> property and drop the line from the vcc_5v0_hdmi regulator to allow
> adjusting the bias when transitioning between TMDS and FRL operating
> modes.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi
> index 749f0a54b478..93ae37699366 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi
> @@ -140,10 +140,7 @@ regulator-state-mem {
>
> vcc_5v0_hdmi: regulator-vcc-5v0-hdmi {
> compatible = "regulator-fixed";
> - enable-active-high;
> - gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&hdmi_con_en>;
> + regulator-always-on;
> regulator-min-microvolt = <5000000>;
> regulator-max-microvolt = <5000000>;
> regulator-name = "vcc_5v0_hdmi";
I think this regulator was sort of a complete hack, to set that
gpio to some sort of default state, by declaring it as hdmi-pwr-supply.
Only 2 rk3576 boards seem, to use that hack, so I think as that "regulator"
is completely functionless now, the whole thing could be removed?
> @@ -231,6 +228,8 @@ &gpu {
> };
>
> &hdmi {
> + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_frl_en>;
> + frl-enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
this should be sorted the other way around I think.
Also please provide a pinctrl-names property too. If for whatever reason
the dw-hdmi aquires a 2nd pinctrl state in the future, this makes sure
board DTs are staying in the "old" compatible mode until they are adapted.
> status = "okay";
> };
>
> @@ -655,7 +654,7 @@ &pcie0 {
>
> &pinctrl {
> hdmi {
> - hdmi_con_en: hdmi-con-en {
> + hdmi_frl_en: hdmi-frl-en {
pinctrl names should ideally match the naming in schematics, for example
the "HDMI0_TX_ON_H" for jaguar and tiger. This makes it way easier to
go from DT to schematics and back.
> rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
>
>
Heiko
^ permalink raw reply
* Re: [PATCH 00/40] arm64: dts: rockchip: Wire up frl-enable-gpios for RK3576/RK3588 boards
From: Heiko Stuebner @ 2026-04-17 11:34 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Cristian Ciocaltea
Cc: kernel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
In-Reply-To: <20260417-dts-rk-frl-enable-gpios-v1-0-a19c0dd8c9f6@collabora.com>
Hi Cristan,
Am Freitag, 17. April 2026, 11:24:34 Mitteleuropäische Sommerzeit schrieb Cristian Ciocaltea:
[...]
> Cristian Ciocaltea (40):
> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-100ask-dshanpi-a1
> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-armsom-sige5
> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-evb1-v10
> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-evb2-v10
> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-luckfox-core3576
> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-nanopi-m5
> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-nanopi-r76s
> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-roc-pc
> arm64: dts: rockchip: Add frl-enable-gpios to rk3576-rock-4d
I do think one patch per SoC (rk3576, rk3588, rk3588s) would make more
sense, because these patches really are mostly identical :-)
Heiko
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-armsom-sige7
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-armsom-w3
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-coolpi-cm5-evb
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-coolpi-cm5-genbook
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-evb1-v10
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-evb2-v10
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-firefly-itx-3588j
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-friendlyelec-cm3588-nas
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-h96-max-v58
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-jaguar
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-mnt-reform2
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-nanopc-t6
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-orangepi-5-max
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-orangepi-5-plus
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-orangepi-5-ultra
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-roc-rt
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-rock-5-itx
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-rock-5b-5bp-5t
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588-tiger
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-coolpi-4b
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-gameforce-ace
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-indiedroid-nova
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-khadas-edge2
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-nanopi-r6
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-odroid-m2
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-orangepi-5
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-orangepi-cm5-base
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-radxa-cm5-io
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-roc-pc
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-rock-5a
> arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-rock-5c
>
> .../boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts | 8 ++++++++
> arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts | 8 ++++++++
> arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts | 8 ++++++++
> arch/arm64/boot/dts/rockchip/rk3576-evb2-v10.dts | 8 ++++++++
> .../boot/dts/rockchip/rk3576-luckfox-core3576.dtsi | 9 ++++-----
> arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts | 8 ++++++++
> arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts | 9 ++++-----
> arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts | 8 ++++++++
> arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 8 ++++++++
> arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts | 9 +++++++++
> arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts | 16 ++++++++++++++++
> arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts | 17 ++++++++++++++++-
> .../boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts | 10 +++++++++-
> arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 16 ++++++++++++++++
> arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts | 9 +++++++++
> .../boot/dts/rockchip/rk3588-firefly-itx-3588j.dts | 9 +++++++++
> .../dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts | 16 ++++++++++++++++
> arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts | 9 +++++++++
> arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 10 +++++++++-
> arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts | 9 +++++++++
> arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 16 ++++++++++++++++
> arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts | 15 ++++++++++++++-
> arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts | 16 ++++++++++++++++
> .../arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts | 9 ++++++++-
> arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts | 16 ++++++++++++++++
> arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts | 9 ++++++++-
> arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 16 +++++++++++++++-
> arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts | 3 ++-
> arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 9 ++++++++-
> arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts | 9 +++++++++
> arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts | 8 +++-----
> .../arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 10 +++++++++-
> arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 13 +++++++++----
> arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 9 +++++++++
> arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts | 9 +++++++++
> arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi | 9 +++++++++
> .../boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts | 3 ++-
> arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts | 9 +++++++++
> arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts | 15 ++++++++++++---
> arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 10 +++++++++-
> arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts | 10 +++++++++-
> 41 files changed, 392 insertions(+), 35 deletions(-)
> ---
> base-commit: 452c3b1ea875276105ac90ba474f72b4cd9b77a2
> change-id: 20260417-dts-rk-frl-enable-gpios-ce9930dbf5ca
>
>
^ permalink raw reply
* [PATCH v1 0/5] media: lm3560: convert to use OF bindings
From: Svyatoslav Ryhel @ 2026-04-17 11:42 UTC (permalink / raw)
To: Lee Jones, Pavel Machek, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sakari Ailus, Mauro Carvalho Chehab,
Svyatoslav Ryhel
Cc: linux-leds, devicetree, linux-kernel, linux-media
Add missing HWEN input pin and IN supply. Fix v4l2 subdev registration.
Remove platform data and switch to OF device tree bindings.
Svyatoslav Ryhel (5):
media: lm3560: Add HWEN pin support
media: lm3560: Add IN supply support
media: lm3560: Fix v4l2 subdev registration
media: lm3560: convert to use OF bindings
dt-bindings: leds: Document TI LM3560 Synchronous Boost Flash Driver
.../devicetree/bindings/leds/ti,lm3560.yaml | 134 +++++++++++++++++
drivers/media/i2c/lm3560.c | 139 ++++++++++++++----
include/media/i2c/lm3560.h | 15 --
3 files changed, 243 insertions(+), 45 deletions(-)
create mode 100644 Documentation/devicetree/bindings/leds/ti,lm3560.yaml
--
2.51.0
^ permalink raw reply
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