* Re: [PATCH 1/2] crypto: Delete Qualcomm crypto engine driver
From: Krzysztof Kozlowski @ 2026-05-24 20:24 UTC (permalink / raw)
To: demiobenour, Herbert Xu, David S. Miller, Thara Gopinath,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio, Russell King
Cc: linux-kernel, linux-crypto, linux-arm-msm, Eric Biggers,
Ard Biesheuvel, devicetree, linux-arm-kernel
In-Reply-To: <20260523-delete-qce-v1-1-86105cd7f406@gmail.com>
On 23/05/2026 21:03, Demi Marie Obenour via B4 Relay wrote:
> From: Demi Marie Obenour <demiobenour@gmail.com>
>
> It's slower than the generic C code and causes problems.
That's really vague and incomplete. You need to make your case, provide
arguments, numbers, data. Otherwise it is just trolling.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v9 8/9] ARM: dts: sun8i-a83t: Add BananaPi M3 OV5640 camera overlay
From: Chen-Yu Tsai @ 2026-05-24 20:24 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: linux-media, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, Yong Deng, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Jernej Skrabec, Samuel Holland,
Michael Turquette, Stephen Boyd, Brian Masney, Maxime Ripard,
Paul Kocialkowski
In-Reply-To: <20260518153339.619947-9-paulk@sys-base.io>
On Mon, May 18, 2026 at 6:15 PM Paul Kocialkowski <paulk@sys-base.io> wrote:
>
> From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
>
> Add an overlay supporting the OV5640 from the BananaPi Camera v3
> peripheral board. The board has two sensors (OV5640 and OV8865)
> which cannot be supported in parallel as they share the same reset
> pin and the kernel currently has no support for this case.
This part is no longer true. The kernel recently gained shared GPIO
support. I've tried it on Chromebooks to describe a USB 2/3 hub.
(This is actually one chip and one pin, but has two device nodes
to model the USB 2.0 and USB 3.1 portions.)
> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> ---
> arch/arm/boot/dts/allwinner/Makefile | 3 +
> .../sun8i-a83t-bananapi-m3-camera-ov5640.dtso | 115 ++++++++++++++++++
> 2 files changed, 118 insertions(+)
> create mode 100644 arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov5640.dtso
>
> diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
> index f71392a55df8..6975df9d7b46 100644
> --- a/arch/arm/boot/dts/allwinner/Makefile
> +++ b/arch/arm/boot/dts/allwinner/Makefile
> @@ -221,6 +221,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-a33-vstar.dtb \
> sun8i-a83t-allwinner-h8homlet-v2.dtb \
> sun8i-a83t-bananapi-m3.dtb \
> + sun8i-a83t-bananapi-m3-camera-ov5640.dtb \
> sun8i-a83t-cubietruck-plus.dtb \
> sun8i-a83t-tbs-a711.dtb \
> sun8i-h2-plus-bananapi-m2-zero.dtb \
> @@ -270,6 +271,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-v3s-licheepi-zero-dock.dtb \
> sun8i-v3s-netcube-kumquat.dtb \
> sun8i-v40-bananapi-m2-berry.dtb
> +sun8i-a83t-bananapi-m3-camera-ov5640-dtbs += \
> + sun8i-a83t-bananapi-m3.dtb sun8i-a83t-bananapi-m3-camera-ov5640.dtbo
> sun8i-h2-plus-orangepi-zero-interface-board-dtbs += \
> sun8i-h2-plus-orangepi-zero.dtb sun8i-orangepi-zero-interface-board.dtbo
> sun8i-h3-orangepi-zero-plus2-interface-board-dtbs += \
> diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov5640.dtso b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov5640.dtso
> new file mode 100644
> index 000000000000..0d4de0027fea
> --- /dev/null
> +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov5640.dtso
> @@ -0,0 +1,115 @@
> +// SPDX-License-Identifier: GPL-2.0 OR X11
> +/*
> + * Copyright 2022 Bootlin
> + * Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/clock/sun8i-a83t-ccu.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +&{/} {
> + /*
> + * These regulators actually have DLDO4 tied to their EN pin, which is
> + * described as input supply here for lack of a better representation.
> + * Their actual supply is PS, which is always-on.
> + */
> +
> + ov5640_avdd: ov5640-avdd {
You should fix the device node names, as Sashiko mentioned for patch 9.
> + compatible = "regulator-fixed";
> + regulator-name = "ov5640-avdd";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + vin-supply = <®_dldo4>;
> + };
> +
> + ov5640_dovdd: ov5640-dovdd {
> + compatible = "regulator-fixed";
> + regulator-name = "ov5640-dovdd";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + vin-supply = <®_dldo4>;
> + };
> +
> + ov5640_dvdd: ov5640-dvdd {
This one as well.
> + compatible = "regulator-fixed";
> + regulator-name = "ov5640-dvdd";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + vin-supply = <®_dldo4>;
> + };
> +};
> +
> +&csi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&csi_8bit_parallel_pins>;
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + csi_in_ov5640: endpoint {
> + remote-endpoint = <&ov5640_out_csi>;
> + bus-width = <8>;
> + data-shift = <2>;
> + hsync-active = <1>;
> + vsync-active = <1>;
> + pclk-sample = <1>;
> + };
> + };
> + };
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_pe_pins>;
> + status = "okay";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ov5640: camera@3c {
> + pinctrl-names = "default";
> + pinctrl-0 = <&csi_mclk_pin>;
> +
> + compatible = "ovti,ov5640";
> + reg = <0x3c>;
Per the "new" DT coding style guide, the compatible property is always
the first oen, and reg, if present, is always the second.
Same comments also apply to patch 9.
Thanks
ChenYu
> +
> + clocks = <&ccu CLK_CSI_MCLK>;
> + clock-names = "xclk";
> + assigned-clocks = <&ccu CLK_CSI_MCLK>;
> + assigned-clock-parents = <&osc24M>;
> + assigned-clock-rates = <24000000>;
> +
> + AVDD-supply = <&ov5640_avdd>;
> + DOVDD-supply = <&ov5640_dovdd>;
> + DVDD-supply = <&ov5640_dvdd>;
> +
> + powerdown-gpios = <&pio 3 15 GPIO_ACTIVE_HIGH>; /* PD15 */
> + reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
> +
> + rotation = <180>;
> +
> + port {
> + ov5640_out_csi: endpoint {
> + remote-endpoint = <&csi_in_ov5640>;
> + bus-width = <8>;
> + data-shift = <2>;
> + hsync-active = <1>;
> + vsync-active = <1>;
> + pclk-sample = <1>;
> + };
> + };
> + };
> +};
> +
> +®_dldo4 {
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> +};
> --
> 2.54.0
>
^ permalink raw reply
* Re: [PATCH v5 2/3] counter: add GPIO-based counter driver
From: sashiko-bot @ 2026-05-24 20:14 UTC (permalink / raw)
To: Wadim Mueller; +Cc: devicetree, robh, conor+dt
In-Reply-To: <20260524193846.19216-3-wafgo01@gmail.com>
Thank you for your contribution! Sashiko AI review found 7 potential issue(s) to consider:
- [High] Concurrent sysfs writes to the 'enable' attribute cause unbalanced IRQ enables and desynchronize the hardware state.
- [High] The Quadrature X1_A and X1_B modes are fundamentally broken and form a directional feedback loop, failing to decode direction.
- [High] GPIO states are sampled outside the spinlock in ISRs, causing state machine desynchronization under rapid concurrent edges.
- [Medium] Negative error codes from gpiod_get_value() are masked and incorrectly converted into logical HIGH states.
- [Medium] The counter saturates at bounds instead of wrapping around, violating Counter subsystem `ceiling` semantics.
- [Medium] The previous GPIO states are not synchronized when the counter is re-enabled, causing missed edges or spurious counts.
- [Medium] The Quadrature X2_A and X2_B modes do not verify if the triggering signal actually changed state, leading to false counts on noisy lines.
--
commit 9297ee567bedc28c8a463a9a4d24d31a9d00cc62
Author: Wadim Mueller <wafgo01@gmail.com>
counter: add GPIO-based counter driver
Add a platform driver that turns plain GPIOs into a counter device.
Edge interrupts on the signal-a, signal-b (and optional index) lines
are decoded in software using a 2-bit Gray-code parity trick for the
quadrature X4 mode and direct edge checks for the other modes.
> diff --git a/drivers/counter/gpio-counter.c b/drivers/counter/gpio-counter.c
> new file mode 100644
> index 0000000000000..f50cec33ae366
> --- /dev/null
> +++ b/drivers/counter/gpio-counter.c
[ ... ]
> +static void gpio_counter_update(struct gpio_counter_priv *priv, int delta)
> +{
> + if (delta > 0) {
> + priv->direction = COUNTER_COUNT_DIRECTION_FORWARD;
> + if (priv->count >= priv->ceiling)
> + return;
> + priv->count++;
> + } else if (delta < 0) {
> + priv->direction = COUNTER_COUNT_DIRECTION_BACKWARD;
> + if (priv->count == 0)
> + return;
> + priv->count--;
> + }
> +}
[Severity: Medium]
Will saturating the counter at its limits break compatibility with the Counter
subsystem semantics?
The Counter ABI defines 'ceiling' as a wraparound limit for cyclic counters,
where counting past the ceiling wraps to 0, and counting below 0 wraps to the
ceiling. Saturating at the limits might cause issues for userspace
applications relying on cyclic tracking.
[ ... ]
> +static int gpio_counter_a_delta(struct gpio_counter_priv *priv, int a, int b,
> + int prev_a, int prev_b)
> +{
> + enum counter_count_direction dir;
> +
> + switch (priv->function) {
> + case COUNTER_FUNCTION_QUADRATURE_X4:
> + if (!GPIO_COUNTER_STATE_CHANGED(prev_a, prev_b, a, b))
> + return 0;
> + dir = GPIO_COUNTER_GET_DIRECTION(prev_b, a);
> + return (dir == COUNTER_COUNT_DIRECTION_FORWARD) ? 1 : -1;
> +
> + case COUNTER_FUNCTION_QUADRATURE_X2_A:
> + return (a == b) ? -1 : 1;
[Severity: Medium]
How does the X2_A mode handle noisy lines or contact bounce?
Unlike the X4 mode which checks for a state change, this mode unconditionally
returns 1 or -1 based on (a == b). If the signal line bounces, causing the ISR
to fire twice for the same logical state (where a == prev_a), it appears the
ISR will incorrectly register an additional count in the same direction.
Should there be a check to verify that the interrupted signal has actually
toggled?
> +
> + case COUNTER_FUNCTION_QUADRATURE_X1_A:
> + if (a && priv->direction == COUNTER_COUNT_DIRECTION_FORWARD)
> + return 1;
> + if (!a && priv->direction == COUNTER_COUNT_DIRECTION_BACKWARD)
> + return -1;
> + return 0;
[Severity: High]
Is it possible for the X1_A and X1_B modes to correctly decode direction?
The logic relies on checking the state against priv->direction. Since
priv->direction is initialized to forward, and only flips to backward if
delta < 0, but delta can only be < 0 if the direction is already backward,
this looks like a positive feedback loop. It seems the counter will only
ever count upward.
Should the state of the opposite phase signal be used to determine direction
instead?
[ ... ]
> +static irqreturn_t gpio_counter_a_isr(int irq, void *dev_id)
> +{
> + struct counter_device *counter = dev_id;
> + struct gpio_counter_priv *priv = counter_priv(counter);
> + unsigned long flags;
> + int a, b, delta;
> +
> + /* !! normalises away negative gpiod_get_value() errors. */
> + a = !!gpiod_get_value(priv->gpio_a);
[Severity: Medium]
What happens if gpiod_get_value() returns a negative error code?
The comment explicitly states this normalizes away errors, but treating
hardware read failures (like -EINVAL) as valid logical HIGH states could
inject phantom edges into the quadrature decoder, corrupting the absolute
count value.
Should the ISR explicitly check for negative returns and exit instead of
masking the error?
> + b = !!gpiod_get_value(priv->gpio_b);
> +
> + spin_lock_irqsave(&priv->lock, flags);
[Severity: High]
If A and B edges occur in quick succession on an SMP system, could different
CPUs handle the interrupts concurrently and sample the GPIOs out-of-order
relative to when they acquire the spinlock?
This could cause the internal software state machine to evaluate transitions
that are out of sequence with the actual hardware, leading to missed counts or
interpreting forward motion as backwards counting.
Since these are non-sleeping GPIOs, should the reads be moved inside the lock
to ensure atomic transition evaluation?
[ ... ]
> +static int gpio_counter_enable_write(struct counter_device *counter,
> + struct counter_count *count, u8 enable)
> +{
> + struct gpio_counter_priv *priv = counter_priv(counter);
> + unsigned long flags;
> + bool want = enable;
> + bool changed;
> +
> + spin_lock_irqsave(&priv->lock, flags);
> + changed = priv->enabled != want;
> + if (changed)
> + priv->enabled = want;
> + spin_unlock_irqrestore(&priv->lock, flags);
> +
> + if (!changed)
> + return 0;
> +
> + if (want) {
> + enable_irq(priv->irq_a);
[Severity: High]
If two threads write to the 'enable' attribute concurrently, could the
hardware toggles be reordered relative to the lock acquisitions?
Thread A writes 0 and Thread B writes 1. Both check the state under the lock,
but Thread B could call enable_irq() before Thread A calls disable_irq(). This
would trigger an 'Unbalanced enable for IRQ' warning since enable_irq() is
called on an already-enabled IRQ.
Should the physical enable_irq() and disable_irq() calls be moved inside the
spinlock, or should another synchronization mechanism be used to prevent this
race?
[Severity: Medium]
Are the previous GPIO states synchronized when the counter is re-enabled?
priv->prev_a and priv->prev_b are initialized during probe(). If the hardware
moves while the counter is disabled, the first edge interrupt after re-enabling
will compare the new GPIO levels against stale 'prev' states. This could lead
to misinterpreting the first transition, resulting in false direction
evaluations or dropped counts.
Should priv->prev_a and priv->prev_b be sampled and updated inside this
function before enabling the IRQs?
> + enable_irq(priv->irq_b);
> + if (priv->irq_index)
> + enable_irq(priv->irq_index);
> + } else {
> + disable_irq(priv->irq_a);
> + disable_irq(priv->irq_b);
> + if (priv->irq_index)
> + disable_irq(priv->irq_index);
> + }
> +
> + return 0;
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260524193846.19216-1-wafgo01@gmail.com?part=2
^ permalink raw reply
* Re: [PATCH 1/2] crypto: Delete Qualcomm crypto engine driver
From: Demi Marie Obenour @ 2026-05-24 20:12 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Herbert Xu, David S. Miller, Thara Gopinath, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
Russell King, linux-kernel, linux-crypto, linux-arm-msm,
Eric Biggers, Ard Biesheuvel, devicetree, linux-arm-kernel
In-Reply-To: <7rgfuvv3hai7g4wt4accbkejtzdt5dnb6mkj6x7ox5sz35q4n2@h7j6rr7extuj>
[-- Attachment #1.1.1: Type: text/plain, Size: 1145 bytes --]
On 5/24/26 12:42, Dmitry Baryshkov wrote:
> On Sat, May 23, 2026 at 03:03:56PM -0400, Demi Marie Obenour via B4 Relay wrote:
>> From: Demi Marie Obenour <demiobenour@gmail.com>
>>
>> It's slower than the generic C code and causes problems.
>
> Which problems?
See https://lore.kernel.org/all/20260522024912.GC5937@quark/.
Also, if there are no systems in which the QCE driver is actually
the highest priority, then unless someone adjusts priorities manually
it's unused code.
> Also in the security world faster and safer are two orthogonal axis with
> very limited correlation.
If by "safer" you mean protection against physical side-channel
attacks, then my understanding is that all operations on secret keys
need to be masked. This includes copying and storage.
Linux only supports this for protected keys, and even then sometimes
uses the kernel's own RNG for key generation. There is no support
for using the QCE for protected keys.
Linux does support using hardware-wrapped keys with inline crypto
engines, which are what are actually used on Android.
--
Sincerely,
Demi Marie Obenour (she/her/hers)
[-- Attachment #1.1.2: OpenPGP public key --]
[-- Type: application/pgp-keys, Size: 7253 bytes --]
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH v2] ASoC: dt-bindings: sound: atmel_ac97c: Convert to DT schema
From: sashiko-bot @ 2026-05-24 20:02 UTC (permalink / raw)
To: Manish Baing; +Cc: devicetree, conor+dt, robh
In-Reply-To: <20260524195318.112398-1-manishbaing2789@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The YAML schema conversion incorrectly modifies the list of required properties compared to the original text binding by omitting `ac97-gpios` and adding `clocks` and `clock-names` without justification.
--
commit 78a24354563be69b55ed4c3cb505afc48e0f2156
Author: Manish Baing <manishbaing2789@gmail.com>
ASoC: dt-bindings: sound: atmel_ac97c: Convert to DT schema
Convert the Atmel AC97 controller binding from text format to YAML schema.
> diff --git a/Documentation/devicetree/bindings/sound/atmel,at91sam9263-ac97c.yaml b/Documentation/devicetree/bindings/sound/atmel,at91sam9263-ac97c.yaml
> new file mode 100644
> index 0000000000000..5f4ebe81bf907
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/atmel,at91sam9263-ac97c.yaml
[ ... ]
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
[Severity: Medium]
Are clocks and clock-names strictly required now, and is the omission of
ac97-gpios intentional?
The original text binding listed ac97-gpios under the required properties
section, but did not document clocks or clock-names as required. Altering
binding constraints during a text-to-YAML conversion without explaining the
changes in the commit message can cause dtbs_check to fail for existing
device trees or weaken validation.
Could the commit message be updated to explain these constraint changes, or
should the required list be adjusted to match the original text binding?
> diff --git a/Documentation/devicetree/bindings/sound/atmel_ac97c.txt b/Documentation/devicetree/bindings/sound/atmel_ac97c.txt
> deleted file mode 100644
> index b151bd902ce3d..0000000000000
> --- a/Documentation/devicetree/bindings/sound/atmel_ac97c.txt
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -* Atmel AC97 controller
> -
> -Required properties:
> - - compatible: "atmel,at91sam9263-ac97c"
> - - reg: Address and length of the register set for the device
> - - interrupts: Should contain AC97 interrupt
> - - ac97-gpios: Please refer to soc-ac97link.txt, only ac97-reset is used
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260524195318.112398-1-manishbaing2789@gmail.com?part=1
^ permalink raw reply
* Re: (subset) [PATCH v3 08/17] arm64: dts: exynos: Add EL2 virtual timer interrupt
From: Krzysztof Kozlowski @ 2026-05-24 20:00 UTC (permalink / raw)
To: linux-arm-kernel, linux-acpi, linux-kernel, devicetree,
Marc Zyngier
Cc: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber, Yu-Chun Lin [林祐君],
Heiko Stuebner, Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <20260523140242.586031-9-maz@kernel.org>
On Sat, 23 May 2026 15:02:33 +0100, Marc Zyngier wrote:
> A bunch of Samsung SoCs are missing the EL2 virtual timer interrupt
> despite using ARMv8.1+ CPUs. Add the missing interrupt, except for
> those broken designs where the interrupt is documented as not being
> wired.
Applied, thanks!
[08/17] arm64: dts: exynos: Add EL2 virtual timer interrupt
https://git.kernel.org/krzk/linux/c/d0298724f901d45c76f1f2193225706200f565e4
Best regards,
--
Krzysztof Kozlowski <krzk@kernel.org>
^ permalink raw reply
* Re: [PATCH v3 00/17] arm64: Use EL2 virtual timer when running VHE
From: Marc Zyngier @ 2026-05-24 19:59 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-arm-kernel, linux-acpi, linux-kernel, devicetree,
Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J. Wysocki, Mark Rutland, Daniel Lezcano,
Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ge Gordon,
BST Linux Kernel Upstream Group, Jesper Nilsson, Lars Persson,
Alim Akhtar, Ivaylo Ivanov, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Matthias Brugger, AngeloGioacchino Del Regno, Thierry Reding,
Jonathan Hunter, Bjorn Andersson, Konrad Dybcio,
Andreas Färber,
"Yu-Chun Lin [林祐君]", Heiko Stuebner,
Shawn Lin, Orson Zhai, Baolin Wang, Michal Simek
In-Reply-To: <f519372e-139c-4530-98bb-dbec56af373a@kernel.org>
On Sun, 24 May 2026 19:17:05 +0100,
Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 23/05/2026 16:02, Marc Zyngier wrote:
> > This is the third version of the series initially posted at [1],
> > which
> >
> > - updates the ACPI GTDT parsing to deal the v3 layout and the EL2
> > virtual timer,
> > - moves the architected timer driver to use it when running VHE,
> > - fixes a number of DTs to reflect the reality of the HW.
> >
>
> Please mention here what do you expect SoC maintainer to do with this -
> apply individual patches, wait for dependencies, ack etc.
I only care about the first 3 patches (ACPI enablement, arm64 timer
code), and don't have any expectation for the rest, as pointed out in
the cover letter for v1.
These are all bug fixes for DTs that do not correctly describe the HW.
There is therefore no dependency on anything. The patches can either
be cherry picked by the individual SoC maintainers, applied globally
by one of the DT maintainers, or be completely ignored.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
From: sashiko-bot @ 2026-05-24 19:58 UTC (permalink / raw)
To: Biju; +Cc: robh, conor+dt, devicetree, wsa+renesas
In-Reply-To: <20260524194457.479681-2-biju.das.jz@bp.renesas.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] The compatible string 'renesas,r9a08g046-lvds-cmn' is used in the dt-binding example but is not documented.
- [Low] The parent node 'lvds-cmn' in the example lacks a 'ranges' property, breaking address translation for its child nodes.
--
commit be595c0db2d85d9ea1396f0f30ac7ad75f4101fe
Author: Biju Das <biju.das.jz@bp.renesas.com>
dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
Documents the LVDS encoder IP found on the RZ/G3L SoC. It supports
single-link mode and shares a peripheral clock and reset signal with the
MIPI-DSI interface.
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> new file mode 100644
> index 0000000000000..b1f6d020ae7b1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
[ ... ]
> +examples:
> + - |
> + #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> +
> + lvds-cmn@108a0000 {
> + compatible = "renesas,r9a08g046-lvds-cmn",
> + "simple-mfd", "syscon";
[Severity: Low]
Is this compatible string documented somewhere else? It looks like
renesas,r9a08g046-lvds-cmn isn't present in the tree, which might cause
dt_binding_check to fail when it validates the example.
> + reg = <0x108a0000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
[Severity: Low]
Does this parent node need a ranges property? Without it, address translation
for the child node's reg = <0x10 0x8> might fail, and dtc often warns about
missing ranges in simple-mfd nodes with children.
> +
> + lvds0: lvds@10 {
> + compatible = "renesas,r9a08g046-lvds";
> + reg = <0x10 0x8>;
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260524194457.479681-1-biju.das.jz@bp.renesas.com?part=1
^ permalink raw reply
* [PATCH v2] ASoC: dt-bindings: sound: atmel_ac97c: Convert to DT schema
From: Manish Baing @ 2026-05-24 19:53 UTC (permalink / raw)
To: claudiu.beznea, lgirdwood, broonie, robh, krzk+dt, conor+dt,
nicolas.ferre, alexandre.belloni
Cc: linux-sound, devicetree, linux-arm-kernel, linux-kernel,
manishbaing2789
Convert the Atmel AC97 controller binding from text
format to YAML schema.
Signed-off-by: Manish Baing <manishbaing2789@gmail.com>
---
Changes in v2:
- Added undocumented 'clocks' and 'clock-names' properties which are
unconditionally required by the driver.
- Removed 'ac97-gpios' from the required list, as the driver treats
it as optional, fixing validation for existing dtsi files.
.../sound/atmel,at91sam9263-ac97c.yaml | 70 +++++++++++++++++++
.../devicetree/bindings/sound/atmel_ac97c.txt | 20 ------
2 files changed, 70 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/atmel,at91sam9263-ac97c.yaml
delete mode 100644 Documentation/devicetree/bindings/sound/atmel_ac97c.txt
diff --git a/Documentation/devicetree/bindings/sound/atmel,at91sam9263-ac97c.yaml b/Documentation/devicetree/bindings/sound/atmel,at91sam9263-ac97c.yaml
new file mode 100644
index 000000000000..5f4ebe81bf90
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/atmel,at91sam9263-ac97c.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/atmel,at91sam9263-ac97c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel AC97 Controller
+
+maintainers:
+ - Nicolas Ferre <nicolas.ferre@microchip.com>
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+allOf:
+ - $ref: dai-common.yaml#
+
+properties:
+ compatible:
+ const: atmel,at91sam9263-ac97c
+
+ reg:
+ maxItems: 1
+ description: Address and length of the register set for the device.
+
+ interrupts:
+ maxItems: 1
+ description: Should contain the AC97 interrupt.
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: ac97_clk
+
+ ac97-gpios:
+ minItems: 3
+ maxItems: 4
+ description: |
+ AC97 link GPIOs- sync, sdata_out, reset, and optional sdata_in.
+ The driver primarily uses the reset pin.
+
+ pinctrl-0: true
+
+ pinctrl-names:
+ const: default
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/clock/at91.h>
+
+ sound@fffa0000 {
+ compatible = "atmel,at91sam9263-ac97c";
+ reg = <0xfffa0000 0x4000>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+ clock-names = "ac97_clk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ac97>;
+ ac97-gpios = <&pioB 0 0>, <&pioB 2 0>, <&pioC 29 GPIO_ACTIVE_LOW>;
+ };
diff --git a/Documentation/devicetree/bindings/sound/atmel_ac97c.txt b/Documentation/devicetree/bindings/sound/atmel_ac97c.txt
deleted file mode 100644
index b151bd902ce3..000000000000
--- a/Documentation/devicetree/bindings/sound/atmel_ac97c.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* Atmel AC97 controller
-
-Required properties:
- - compatible: "atmel,at91sam9263-ac97c"
- - reg: Address and length of the register set for the device
- - interrupts: Should contain AC97 interrupt
- - ac97-gpios: Please refer to soc-ac97link.txt, only ac97-reset is used
-Optional properties:
- - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt
-
-Example:
-sound@fffa0000 {
- compatible = "atmel,at91sam9263-ac97c";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ac97>;
- reg = <0xfffa0000 0x4000>;
- interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>;
-
- ac97-gpios = <&pioB 0 0 &pioB 2 0 &pioC 29 GPIO_ACTIVE_LOW>;
-};
--
2.43.0
^ permalink raw reply related
* [PATCH 16/16] arm64: dts: qcom: shikra: enable WiFi on EVK boards
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Miaoqing Pan
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Enable WiFi support on Shikra CQS, CQM and IQS EVK variants.
Provide board-specific WiFi configuration, including power supply
connections and calibration variant selection. The WiFi node is
enabled on each EVK according to the corresponding PMIC and board
design.
Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 11 +++++++++++
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 11 +++++++++++
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 19 +++++++++++++++++++
3 files changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index 259032bd20af..15208e1abff6 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -69,3 +69,14 @@ bluetooth {
vddch0-supply = <&pm4125_l22>;
};
};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&pm4125_l7>;
+ vdd-1.8-xo-supply = <&pm4125_l13>;
+ vdd-1.3-rfa-supply = <&pm4125_l10>;
+ vdd-3.3-ch0-supply = <&pm4125_l22>;
+ qcom,calibration-variant = "Shikra_EVK";
+ firmware-name = "cq2390";
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
index 142cc8da53ce..51267c1a86b3 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
@@ -69,3 +69,14 @@ bluetooth {
vddch0-supply = <&pm4125_l22>;
};
};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&pm4125_l7>;
+ vdd-1.8-xo-supply = <&pm4125_l13>;
+ vdd-1.3-rfa-supply = <&pm4125_l10>;
+ vdd-3.3-ch0-supply = <&pm4125_l22>;
+ qcom,calibration-variant = "Shikra_EVK";
+ firmware-name = "cq2390";
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
index 9bf52030bcc5..f4e93cfb77e3 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
@@ -30,6 +30,14 @@ vreg_bt_3p3_dummy: regulator-bt-3p3-dummy {
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
+
+ vreg_wlan_3p3_dummy: regulator-wlan-3p3-dummy {
+ compatible = "regulator-fixed";
+ regulator-name = "wlan_3p3_dummy";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
};
&remoteproc_cdsp {
@@ -77,3 +85,14 @@ bluetooth {
vddch0-supply = <&vreg_bt_3p3_dummy>;
};
};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&pm8150_s4>;
+ vdd-1.8-xo-supply = <&pm8150_l12>;
+ vdd-1.3-rfa-supply = <&pm8150_l8>;
+ vdd-3.3-ch0-supply = <&vreg_wlan_3p3_dummy>;
+ qcom,calibration-variant = "Shikra_EVK";
+ firmware-name = "cq2390";
+
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related
* [PATCH 15/16] arm64: dts: qcom: shikra: add WiFi node support
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Miaoqing Pan
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Introduce the WiFi hardware description in shikra.dtsi, including
register space, interrupts, IOMMU configuration and reserved memory.
The node is kept disabled by default and is intended to be enabled
by board-specific device trees.
Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 73681bf0e3ea..33feb6d3f73b 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -2070,6 +2070,29 @@ apps_smmu: iommu@c600000 {
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ wifi: wifi@c800000 {
+ compatible = "qcom,wcn3990-wifi";
+ reg = <0x0 0x0c800000 0x0 0x800000>;
+ reg-names = "membase";
+ memory-region = <&wlan_mem>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&apps_smmu 0x1a0 0x1>;
+ qcom,msa-fixed-perm;
+
+ status = "disabled";
+ };
+
intc: interrupt-controller@f200000 {
compatible = "arm,gic-v3";
reg = <0x0 0xf200000 0x0 0x10000>,
--
2.34.1
^ permalink raw reply related
* [PATCH 14/16] arm64: dts: qcom: shikra: Enable BT support on EVK boards
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Yepuri Siddu, Yepuri Siddu
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Yepuri Siddu <ysiddu@qti.qualcomm.com>
Enable uart8 and add WCN3988 Bluetooth node with board-specific regulator
supplies across CQM, CQS and IQS Shikra EVK boards.
Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 12 ++++++++++++
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 12 ++++++++++++
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 20 ++++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra.dtsi | 7 +++++++
4 files changed, 51 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index b112b21b1d79..259032bd20af 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -16,6 +16,7 @@ / {
aliases {
mmc0 = &sdhc_1;
serial0 = &uart0;
+ serial1 = &uart8;
};
chosen {
@@ -57,3 +58,14 @@ &sdhc_1 {
status = "okay";
};
+
+&uart8 {
+ status = "okay";
+
+ bluetooth {
+ vddio-supply = <&pm4125_l7>;
+ vddxo-supply = <&pm4125_l13>;
+ vddrf-supply = <&pm4125_l10>;
+ vddch0-supply = <&pm4125_l22>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
index e62ba5aef71f..142cc8da53ce 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
@@ -16,6 +16,7 @@ / {
aliases {
mmc0 = &sdhc_1;
serial0 = &uart0;
+ serial1 = &uart8;
};
chosen {
@@ -57,3 +58,14 @@ &sdhc_1 {
status = "okay";
};
+
+&uart8 {
+ status = "okay";
+
+ bluetooth {
+ vddio-supply = <&pm4125_l7>;
+ vddxo-supply = <&pm4125_l13>;
+ vddrf-supply = <&pm4125_l10>;
+ vddch0-supply = <&pm4125_l22>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
index 727809430fd1..9bf52030bcc5 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
@@ -16,11 +16,20 @@ / {
aliases {
mmc0 = &sdhc_1;
serial0 = &uart0;
+ serial1 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ vreg_bt_3p3_dummy: regulator-bt-3p3-dummy {
+ compatible = "regulator-fixed";
+ regulator-name = "bt_3p3_dummy";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
};
&remoteproc_cdsp {
@@ -57,3 +66,14 @@ &sdhc_1 {
status = "okay";
};
+
+&uart8 {
+ status = "okay";
+
+ bluetooth {
+ vddio-supply = <&pm8150_s4>;
+ vddxo-supply = <&pm8150_l12>;
+ vddrf-supply = <&pm8150_l8>;
+ vddch0-supply = <&vreg_bt_3p3_dummy>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 124d0f05538d..73681bf0e3ea 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -1753,6 +1753,13 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
pinctrl-names = "default";
status = "disabled";
+
+ bluetooth {
+ compatible = "qcom,wcn3988-bt";
+ enable-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+ max-speed = <3200000>;
+ };
+
};
i2c9: i2c@4aa4000 {
--
2.34.1
^ permalink raw reply related
* [PATCH 13/16] arm64: dts: qcom: shikra: Enable TSENS and thermal zones
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Gaurav Kohli
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
The shikra includes one TSENS instance, with a total of 14 thermal
sensors distributed across various locations on the SoC.
The TSENS max/reset threshold is configured to 120°C in the hardware.
Enable all TSENS instances, and define the thermal zones with a hot trip
at 110°C and critical trip at 115°C.
Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 267 +++++++++++++++++++++++++++++++++++
1 file changed, 267 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 96ec5b5c7203..124d0f05538d 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interconnect/qcom,shikra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -982,6 +983,18 @@ spmi_bus: spmi@1c40000 {
qcom,ee = <0>;
};
+ tsens0: thermal-sensor@4411000 {
+ compatible = "qcom,shikra-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x04411000 0x0 0x1000>,
+ <0x0 0x04410000 0x0 0x1000>;
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <14>;
+ #thermal-sensor-cells = <1>;
+ };
+
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0x0 0x045f0000 0x0 0x7000>;
@@ -2179,6 +2192,260 @@ cpufreq_hw: cpufreq@fd91000 {
};
};
+ thermal_zones: thermal-zones {
+ aoss0-thermal {
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ aoss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-0-thermal {
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu00-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-1-thermal {
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu01-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-0-thermal {
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu10-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-1-thermal {
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu11-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss0-thermal {
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpuss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-thermal {
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpuss-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsp-thermal {
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nsp-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss0-thermal {
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ mdmss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss1-thermal {
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ mdmss1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera-thermal {
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ camera-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ video-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-2-thermal {
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu02-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss1-thermal {
+ thermal-sensors = <&tsens0 13>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpuss1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
--
2.34.1
^ permalink raw reply related
* [PATCH 12/16] arm64: dts: qcom: shikra-iqs: Enable CDSP, LPAICP and MPSS
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Bibek Kumar Patro
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Enable CDSP, LPAICP and MPSS for Qualcomm's Shikra IQS EVK board.
Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
index 3003a47bd759..727809430fd1 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
@@ -23,6 +23,25 @@ chosen {
};
};
+&remoteproc_cdsp {
+ firmware-name = "qcom/shikra/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_lpaicp {
+ firmware-name = "qcom/shikra/lpaicp.mbn",
+ "qcom/shikra/lpaicp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
+
+ status = "okay";
+};
+
&sdhc_1 {
vmmc-supply = <&pm8150_l17>;
vqmmc-supply = <&pm8150_s4>;
--
2.34.1
^ permalink raw reply related
* [PATCH 11/16] arm64: dts: qcom: shikra-cqs: Enable CDSP, LPAICP and MPSS
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Bibek Kumar Patro
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Enable CDSP, LPAICP and MPSS for Qualcomm's Shikra CQS EVK board.
Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
index b3f19a64d7ae..e62ba5aef71f 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
@@ -23,6 +23,25 @@ chosen {
};
};
+&remoteproc_cdsp {
+ firmware-name = "qcom/shikra/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_lpaicp {
+ firmware-name = "qcom/shikra/lpaicp.mbn",
+ "qcom/shikra/lpaicp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
+
+ status = "okay";
+};
+
&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;
--
2.34.1
^ permalink raw reply related
* [PATCH 10/16] arm64: dts: qcom: shikra-cqm: Enable CDSP, LPAICP and MPSS
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Bibek Kumar Patro
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Enable CDSP, LPAICP and MPSS for Qualcomm's Shikra CQM EVK board.
Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index 0a52ab9b7a4c..b112b21b1d79 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -23,6 +23,25 @@ chosen {
};
};
+&remoteproc_cdsp {
+ firmware-name = "qcom/shikra/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_lpaicp {
+ firmware-name = "qcom/shikra/lpaicp.mbn",
+ "qcom/shikra/lpaicp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/shikra/cqm/qdsp6sw.mbn";
+
+ status = "okay";
+};
+
&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;
--
2.34.1
^ permalink raw reply related
* [PATCH 09/16] arm64: dts: qcom: shikra: Add CDSP, LPAICP, MPSS remoteproc PAS nodes
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Bibek Kumar Patro
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add nodes for remoteproc PAS loader for CDSP, LPAICP, MPSS subsystem.
Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 164 +++++++++++++++++++++++++++++++++++
1 file changed, 164 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 2ea35e4442ef..96ec5b5c7203 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -1797,6 +1797,170 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
};
};
+ remoteproc_mpss: remoteproc@6080000 {
+ compatible = "qcom,shikra-mpss-pas";
+ reg = <0x0 0x06080000 0x0 0x100>;
+
+ interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING 0>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+
+ power-domains = <&rpmpd RPMHPD_CX>;
+
+ memory-region = <&mpss_wlan_mem>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING 0>;
+ mboxes = <&apcs_glb 12>;
+ qcom,remote-pid = <1>;
+ label = "mpss";
+ };
+ };
+
+ remoteproc_cdsp: remoteproc@b300000 {
+ compatible = "qcom,shikra-cdsp-pas";
+ reg = <0x0 0x0b300000 0x0 0x100000>;
+
+ interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING 0>,
+ <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+
+ power-domains = <&rpmpd RPMHPD_CX>;
+
+ memory-region = <&cdsp_mem>;
+
+ qcom,smem-states = <&cdsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING 0>;
+ mboxes = <&apcs_glb 4>;
+ qcom,remote-pid = <5>;
+ label = "cdsp";
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "cdsp";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu 0x0201 0x0000>;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu 0x0202 0x0000>;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x0203 0x0000>;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x0204 0x0000>;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x0205 0x0000>;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu 0x0206 0x0000>;
+ };
+
+ compute-cb@9 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <9>;
+ iommus = <&apps_smmu 0x0209 0x0000>;
+ };
+ };
+ };
+ };
+
+ remoteproc_lpaicp: remoteproc@b800000 {
+ compatible = "qcom,shikra-lpaicp-pas";
+ reg = <0x0 0x0b800000 0x0 0x200000>;
+
+ interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING 0>,
+ <&lmcu_smp2p_in 0 IRQ_TYPE_NONE>,
+ <&lmcu_smp2p_in 1 IRQ_TYPE_NONE>,
+ <&lmcu_smp2p_in 2 IRQ_TYPE_NONE>,
+ <&lmcu_smp2p_in 3 IRQ_TYPE_NONE>;
+
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ memory-region = <&lmcu_mem &lmcu_dtb_mem>;
+
+ qcom,smem-states = <&lmcu_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING 0>;
+ mboxes = <&apcs_glb 9>;
+ qcom,remote-pid = <26>;
+ label = "lpaicp";
+ };
+ };
+
sram@c11e000 {
compatible = "qcom,shikra-imem", "mmio-sram";
reg = <0x0 0x0c11e000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related
* [PATCH 08/16] arm64: dts: qcom: shikra: Add SMP2P nodes
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Vishnu Santhosh
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Add SMP2P nodes for the cdsp, modem and lmcu subsystems to enable
inter-processor signalling for remoteproc state management.
Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 69 ++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index bb1821e95248..2ea35e4442ef 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -412,6 +412,75 @@ lmcu_dtb_mem: lmcu-dtb@b4702000 {
};
};
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+
+ interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING 0>;
+
+ mboxes = <&apcs_glb 6>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-lmcu {
+ compatible = "qcom,smp2p";
+ qcom,smem = <617>, <616>;
+
+ interrupts = <GIC_SPI 287 IRQ_TYPE_EDGE_RISING 0>;
+
+ mboxes = <&apcs_glb 10>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <26>;
+
+ lmcu_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ lmcu_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-mpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+
+ interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING 0>;
+
+ mboxes = <&apcs_glb 14>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
--
2.34.1
^ permalink raw reply related
* [PATCH 07/16] arm64: dts: qcom: shikra: Add CPU OPP tables to scale DDR/L3
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Sayantan Chakraborty
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Add OPP tables required to scale DDR and L3 per freq-domain on
Shikra SoC.
Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 84 ++++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index ebdb4bc15d76..bb1821e95248 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -48,6 +48,11 @@ cpu0: cpu@0 {
clocks = <&cpufreq_hw 0>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu1: cpu@100 {
@@ -61,6 +66,11 @@ cpu1: cpu@100 {
clocks = <&cpufreq_hw 0>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu2: cpu@200 {
@@ -74,6 +84,11 @@ cpu2: cpu@200 {
clocks = <&cpufreq_hw 0>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu3: cpu@300 {
@@ -87,6 +102,11 @@ cpu3: cpu@300 {
clocks = <&cpufreq_hw 1>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
l2_3: l2-cache {
compatible = "cache";
@@ -144,6 +164,70 @@ memory@80000000 {
/* We expect the bootloader to fill in the size */
reg = <0x0 0x80000000 0x0 0x0>;
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu0_opp_768mhz: opp-768000000 {
+ opp-hz = /bits/ 64 <768000000>;
+ opp-peak-kBps = <1200000 17817600>;
+ };
+
+ cpu0_opp_1017mhz: opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <2188000 25804800>;
+ };
+
+ cpu0_opp_1094mhz: opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ opp-peak-kBps = <3072000 30105600>;
+ };
+
+ cpu0_opp_1497mhz: opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <4068000 38707200>;
+ };
+
+ cpu0_opp_1612mhz: opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <6220000 43008000>;
+ };
+
+ cpu0_opp_1804mhz: opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <7216000 43622400>;
+ };
+ };
+
+ cpu3_opp_table: opp-table-cpu3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cpu3_opp_1017mhz: opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <2188000 25804800>;
+ };
+
+ cpu3_opp_1190mhz: opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-peak-kBps = <3072000 30105600>;
+ };
+
+ cpu3_opp_1497mhz: opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <4068000 38707200>;
+ };
+
+ cpu3_opp_1708mhz: opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <6220000 43008000>;
+ };
+
+ cpu3_opp_1900mhz: opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-peak-kBps = <7216000 43622400>;
+ };
+ };
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
--
2.34.1
^ permalink raw reply related
* [PATCH 06/16] arm64: dts: qcom: shikra: Add EPSS L3 interconnect provider node
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Raviteja Laggyshetty
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Add Epoch Subsystem (EPSS) L3 interconnect provider node for Shikra SoC.
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 238772f064ec..ebdb4bc15d76 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/interconnect/qcom,shikra.h>
@@ -1833,6 +1834,14 @@ frame@f42d000 {
};
};
+ epss_l3: interconnect@fd90000 {
+ compatible = "qcom,shikra-epss-l3";
+ reg = <0x0 0x0fd90000 0x0 0x1000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@fd91000 {
compatible = "qcom,shikra-epss";
reg = <0x0 0x0fd91000 0x0 0x1000>,
--
2.34.1
^ permalink raw reply related
* [PATCH 05/16] arm64: dts: qcom: shikra: Add DDR BWMON support
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Sayantan Chakraborty
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Add CPU-to-DDR BWMON nodes and their corresponding opp tables for
Shikra SoC. This is necessary to enable power management and optimize
system performance from the perspective of dynamically changing DDR
frequencies.
Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 40 ++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 35ab7072e20a..238772f064ec 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -673,6 +673,46 @@ rclk-pins {
};
};
+ pmu@c91000 {
+ compatible = "qcom,shikra-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
+ reg = <0x0 0x00c91000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <1200000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <2188000>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <3072000>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <4068000>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <6220000>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <7216000>;
+ };
+ };
+ };
+
mem_noc: interconnect@d00000 {
compatible = "qcom,shikra-mem-noc-core";
reg = <0x0 0x00d00000 0x0 0x43080>;
--
2.34.1
^ permalink raw reply related
* [PATCH 04/16] arm64: dts: qcom: shikra: Add cpufreq scaling node
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Imran Shaik, Aastha Pandey
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add cpufreq-hw node to support cpufreq scaling on Qualcomm Shikra SoCs.
Co-developed-by: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
Signed-off-by: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 2751b4f89678..35ab7072e20a 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -44,6 +44,9 @@ cpu0: cpu@0 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
};
cpu1: cpu@100 {
@@ -54,6 +57,9 @@ cpu1: cpu@100 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
};
cpu2: cpu@200 {
@@ -64,6 +70,9 @@ cpu2: cpu@200 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
};
cpu3: cpu@300 {
@@ -74,6 +83,9 @@ cpu3: cpu@300 {
next-level-cache = <&l2_3>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <489>;
+ clocks = <&cpufreq_hw 1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
l2_3: l2-cache {
compatible = "cache";
@@ -1780,6 +1792,25 @@ frame@f42d000 {
status = "disabled";
};
};
+
+ cpufreq_hw: cpufreq@fd91000 {
+ compatible = "qcom,shikra-epss";
+ reg = <0x0 0x0fd91000 0x0 0x1000>,
+ <0x0 0x0fd92000 0x0 0x1000>;
+ reg-names = "freq-domain0",
+ "freq-domain1";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "dcvsh-irq-0",
+ "dcvsh-irq-1";
+
+ #freq-domain-cells = <1>;
+ #clock-cells = <1>;
+ };
};
timer {
--
2.34.1
^ permalink raw reply related
* [PATCH 03/16] arm64: dts: qcom: Add QUPv3 configuration for Shikra
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Xueyao An
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Xueyao An <xueyao.an@oss.qualcomm.com>
Add device tree support for QUPv3 serial engine protocols on Shikra.
Shikra has 10 QUP serial engines under a single QUP wrapper, all with
support of GPI DMA engines.
Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 951 +++++++++++++++++++++++++++++++++++
1 file changed, 951 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index a4334d99c1f3..2751b4f89678 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/interconnect/qcom,shikra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -348,6 +349,161 @@ tlmm: pinctrl@500000 {
gpio-ranges = <&tlmm 0 0 165>;
wakeup-parent = <&mpm>;
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio2", "gpio3";
+ function = "qup0_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio4", "gpio5";
+ function = "qup0_se1_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio6", "gpio7";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio10", "gpio11";
+ function = "qup0_se3_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio12", "gpio13";
+ function = "qup0_se4_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio14", "gpio15";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio18", "gpio19";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio20", "gpio21";
+ function = "qup0_se7_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio22", "gpio23";
+ function = "qup0_se8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio27", "gpio26";
+ function = "qup0_se9_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio1";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio2", "gpio3", "gpio0";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_cs: qup-spi2-cs-state {
+ pins = "gpio9";
+ function = "qup0_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio6", "gpio7", "gpio8";
+ function = "qup0_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio17";
+ function = "qup0_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio14", "gpio15", "gpio16";
+ function = "qup0_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio29";
+ function = "qup0_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio18", "gpio19", "gpio28";
+ function = "qup0_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ pins = "gpio25";
+ function = "qup0_se8";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio22", "gpio23", "gpio24";
+ function = "qup0_se8";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
qup_uart0_default: qup-uart0-default-state {
pins = "gpio0", "gpio1";
function = "qup0_se0";
@@ -355,6 +511,105 @@ qup_uart0_default: qup-uart0-default-state {
bias-disable;
};
+ qup_uart1_default: qup-uart1-default-state {
+ pins = "gpio4", "gpio5";
+ function = "qup0_se1_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart2_default: qup-uart2-default-state {
+ /* TX, RX */
+ pins = "gpio8", "gpio9";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart2_cts_rts: qup-uart2-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio6", "gpio7";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart3_default: qup-uart3-default-state {
+ pins = "gpio10", "gpio11";
+ function = "qup0_se3_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart4_default: qup-uart4-default-state {
+ pins = "gpio12", "gpio13";
+ function = "qup0_se4_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart5_default: qup-uart5-default-state {
+ /* TX, RX */
+ pins = "gpio16", "gpio17";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart5_cts_rts: qup-uart5-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio14", "gpio15";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart6_default: qup-uart6-default-state {
+ /* TX, RX */
+ pins = "gpio28", "gpio29";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart6_cts_rts: qup-uart6-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio18", "gpio19";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart7_default: qup-uart7-default-state {
+ pins = "gpio20", "gpio21";
+ function = "qup0_se7_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart8_default: qup-uart8-default-state {
+ /* TX, RX */
+ pins = "gpio24", "gpio25";
+ function = "qup0_se8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart8_cts_rts: qup-uart8-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio22", "gpio23";
+ function = "qup0_se8";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart9_default: qup-uart9-default-state {
+ pins = "gpio26", "gpio27";
+ function = "qup0_se9_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
sdc1_state_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
@@ -604,6 +859,34 @@ opp-384000000 {
};
};
+ gpi_dma0: dma-controller@4a00000 {
+ compatible = "qcom,shikra-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x04a00000 0x0 0x60000>;
+
+ interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <16>;
+ dma-channel-mask = <0xff>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0xf6 0x0>;
+ };
+
qupv3_0: geniqup@4ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x04ac0000 0x0 0x2000>;
@@ -613,10 +896,75 @@ qupv3_0: geniqup@4ac0000 {
clock-names = "m-ahb",
"s-ahb";
+ iommus = <&apps_smmu 0xe3 0x0>;
+
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ status = "disabled";
+
+ i2c0: i2c@4a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi0: spi@4a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
uart0: serial@4a80000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x04a80000 0x0 0x4000>;
@@ -638,6 +986,609 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
status = "disabled";
};
+
+ i2c1: i2c@4a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@4a84000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart1_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c2: i2c@4a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a88000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ pinctrl-names = "default";
+
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi2: spi@4a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a88000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@4a88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a88000 0x0 0x4000>;
+
+ interrupts-extended = <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&tlmm 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart2_default>, <&qup_uart2_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c3: i2c@4a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart3: serial@4a8c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart3_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c4: i2c@4a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a90000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart4: serial@4a90000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a90000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart4_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c5: i2c@4a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi5: spi@4a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart5: serial@4a94000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart5_default>, <&qup_uart5_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c6: i2c@4a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi6: spi@4a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart6: serial@4a98000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart6_default>, <&qup_uart6_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c7: i2c@4a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a9c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c7_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart7: serial@4a9c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a9c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart7_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c8: i2c@4aa0000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4aa0000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 8 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 8 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi8: spi@4aa0000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4aa0000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 8 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 8 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart8: serial@4aa0000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04aa0000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart8_default>, <&qup_uart8_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c9: i2c@4aa4000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4aa4000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 9 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 9 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart9: serial@4aa4000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04aa4000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart9_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
};
sram@c11e000 {
--
2.34.1
^ permalink raw reply related
* [PATCH 02/16] dt-bindings: interconnect: qcom-bwmon: Add Shikra cpu-bwmon compatible
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Sayantan Chakraborty
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Add the Qualcomm Shikra SoC compatible string for the CPU-to-DDR
bandwidth monitor. Shikra has a BWMONv5 for CPU.
Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
index ff64225e8281..8f6c937e44ce 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
@@ -52,6 +52,7 @@ properties:
- qcom,sa8775p-llcc-bwmon
- qcom,sc7180-llcc-bwmon
- qcom,sc8280xp-llcc-bwmon
+ - qcom,shikra-cpu-bwmon
- qcom,sm6350-cpu-bwmon
- qcom,sm8250-llcc-bwmon
- qcom,sm8550-llcc-bwmon
--
2.34.1
^ permalink raw reply related
* [PATCH 01/16] dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Shikra SoC
From: Komal Bajaj @ 2026-05-24 19:49 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov, Bjorn Andersson,
Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Xueyao An
In-Reply-To: <20260525-shikra-dt-m1-v1-0-f51a9838dbaa@oss.qualcomm.com>
From: Xueyao An <xueyao.an@oss.qualcomm.com>
Document the GPI DMA engine on Shikra platform.
Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
index 8f9a552fe30e..54dca623223d 100644
--- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
+++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
@@ -37,6 +37,7 @@ properties:
- qcom,sc7280-gpi-dma
- qcom,sc8280xp-gpi-dma
- qcom,sdx75-gpi-dma
+ - qcom,shikra-gpi-dma
- qcom,sm6115-gpi-dma
- qcom,sm6375-gpi-dma
- qcom,sm8350-gpi-dma
--
2.34.1
^ permalink raw reply related
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