* Re: [PATCH 7/9] arm64: dts: qcom: hamoa: reorder csiphy power-domains for v8 CSI2-PHY
From: Bryan O'Donoghue @ 2026-06-10 12:24 UTC (permalink / raw)
To: Ramshouriesh, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mauro Carvalho Chehab,
Bryan O'Donoghue, Vladimir Zapolskiy, Loic Poulain,
Vinod Koul, Neil Armstrong
Cc: Aleksandrs Vinarskis, linux-arm-msm, devicetree, linux-kernel,
linux-media, linux-phy
In-Reply-To: <20260610-a14-himax-hm1092-v1-7-0c9907da47ed@gmail.com>
On 10/06/2026 12:09, Ramshouriesh wrote:
> The v8 phy-qcom-mipi-csi2 binding mandates power-domain-names ordered
> "mmcx", "mx" (MMCX first)
Feels like it probably shouldn't.
strings > magic indexes. Thanks for finding.
---
bod
^ permalink raw reply
* Re: [PATCH 1/4] dt-bindings: phy: qcom,qusb2: Straighten out SM6125 and MSM8996
From: sashiko-bot @ 2026-06-10 12:25 UTC (permalink / raw)
To: Konrad Dybcio
Cc: vkoul, linux-phy, neil.armstrong, olteanv, robh, conor+dt,
devicetree
In-Reply-To: <20260610-topic-8996_61x5_qusb2phy-v1-1-d7135980e78f@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Driver/Schema Mismatch: Driver unconditionally requests 'vdd' regulator while schema removes it for MSM8996
--
commit 3e28a2c0425272ba6818b0dca5f1d04b00a00662
Author: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
dt-bindings: phy: qcom,qusb2: Straighten out SM6125 and MSM8996
This commit adds a specific compatible string for SM6125 with an SM6115
fallback. It also updates the MSM8996 bindings to require power domains
and operating performance points instead of a vdd-supply.
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> index 39851ba9de436..807d64aee547c 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
[ ... ]
> @@ -182,6 +190,22 @@ allOf:
> qcom,preemphasis-width: false
> qcom,hsdisc-trim-value: false
>
> + # On MSM8996, VDD is supplied via the MX power domain
> + - if:
> + properties:
> + compatible:
> + const: qcom,msm8996-qusb2-phy
> + then:
> + required:
> + - power-domains
> + - required-opps
> + else:
> + properties:
> + power-domains: false
> + required-opps: false
> + required:
> + - vdd-supply
[ ... ]
> @@ -196,10 +220,13 @@ examples:
> <&gcc GCC_RX1_USB2_CLKREF_CLK>;
> clock-names = "cfg_ahb", "ref";
>
> - vdd-supply = <&pm8994_l28>;
[Severity: Medium]
Does this removal of vdd-supply for MSM8996 create a mismatch with the
existing qusb2 driver?
Looking at qusb2_phy_probe() in drivers/phy/qualcomm/phy-qcom-qusb2.c, the
driver unconditionally requests all regulators defined in
qusb2_phy_vreg_names, which includes the vdd supply:
drivers/phy/qualcomm/phy-qcom-qusb2.c:qusb2_phy_probe()
num = ARRAY_SIZE(qphy->vregs);
for (i = 0; i < num; i++)
qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
If a device tree omits vdd-supply to follow this new schema intent, will
the driver fail to probe with -ENODEV or log an unwanted warning when
falling back to a dummy regulator?
Should the driver be updated to handle the vdd regulator as optional for
hardware variants that use power domains?
> vdda-pll-supply = <&pm8994_l12>;
> vdda-phy-dpdm-supply = <&pm8994_l24>;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260610-topic-8996_61x5_qusb2phy-v1-0-d7135980e78f@oss.qualcomm.com?part=1
^ permalink raw reply
* Re: [PATCH v2 2/2] clk: amlogic: Add A9 AO clock controller driver
From: Jerome Brunet @ 2026-06-10 12:26 UTC (permalink / raw)
To: Jian Hu
Cc: Jian Hu via B4 Relay, Neil Armstrong, Michael Turquette,
Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Xianwei Zhao, Kevin Hilman, Martin Blumenstingl, linux-amlogic,
linux-clk, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <67fcf9bc-0ac7-4812-aa7c-4d42d8f1c162@amlogic.com>
On mer. 10 juin 2026 at 12:18, Jian Hu <jian.hu@amlogic.com> wrote:
> Hi Jerome,
>
> Thanks for your review
>
> On 6/3/2026 10:29 PM, Jerome Brunet wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On Wed 03 Jun 2026 at 20:17, Jian Hu via B4 Relay <devnull+jian.hu.amlogic.com@kernel.org> wrote:
>>
>>> From: Jian Hu <jian.hu@amlogic.com>
>>>
>>> Add the Always-on clock controller driver for the Amlogic A9 SoC family.
>>>
>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>> ---
>>> drivers/clk/meson/Kconfig | 13 ++
>>> drivers/clk/meson/Makefile | 1 +
>>> drivers/clk/meson/a9-aoclk.c | 419 +++++++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 433 insertions(+)
>>>
>>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>>> index cf8cf3f9e4ee..625e6788b940 100644
>>> --- a/drivers/clk/meson/Kconfig
>>> +++ b/drivers/clk/meson/Kconfig
>>> @@ -132,6 +132,19 @@ config COMMON_CLK_A1_PERIPHERALS
>>> device, A1 SoC Family. Say Y if you want A1 Peripherals clock
>>> controller to work.
>>>
>>> +config COMMON_CLK_A9_AO
>>> + tristate "Amlogic A9 SoC AO clock controller support"
>>> + depends on ARM64
>>> + default ARCH_MESON || COMPILE_TEST
>>> + select COMMON_CLK_MESON_REGMAP
>>> + select COMMON_CLK_MESON_CLKC_UTILS
>>> + select COMMON_CLK_MESON_DUALDIV
>>> + imply COMMON_CLK_SCMI
>>> + help
>>> + Support for the AO clock controller on Amlogic A311Y3 based
>>> + device, AKA A9.
>>> + Say Y if you want A9 AO clock controller to work.
>>> +
>>> config COMMON_CLK_C3_PLL
>>> tristate "Amlogic C3 PLL clock controller"
>>> depends on ARM64
>>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>>> index c6719694a242..f89d027c282c 100644
>>> --- a/drivers/clk/meson/Makefile
>>> +++ b/drivers/clk/meson/Makefile
>>> @@ -19,6 +19,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
>>> obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
>>> obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
>>> obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
>>> +obj-$(CONFIG_COMMON_CLK_A9_AO) += a9-aoclk.o
>>> obj-$(CONFIG_COMMON_CLK_C3_PLL) += c3-pll.o
>>> obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) += c3-peripherals.o
>>> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
>>> diff --git a/drivers/clk/meson/a9-aoclk.c b/drivers/clk/meson/a9-aoclk.c
>>> new file mode 100644
>>> index 000000000000..b7b3ca231a42
>>> --- /dev/null
>>> +++ b/drivers/clk/meson/a9-aoclk.c
>>> @@ -0,0 +1,419 @@
>>> +// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
>>> +/*
>>> + * Copyright (C) 2026 Amlogic, Inc. All rights reserved
>>> + */
>>> +
>>> +#include <dt-bindings/clock/amlogic,a9-aoclkc.h>
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/platform_device.h>
>>> +#include "clk-regmap.h"
>>> +#include "clk-dualdiv.h"
>>> +#include "meson-clkc-utils.h"
>>> +
>>> +#define AO_OSCIN_CTRL 0x00
>>> +#define AO_SYS_CLK0 0x04
>>> +#define AO_PWM_CLK_A_CTRL 0x1c
>>> +#define AO_PWM_CLK_B_CTRL 0x20
>>> +#define AO_PWM_CLK_C_CTRL 0x24
>>> +#define AO_PWM_CLK_D_CTRL 0x28
>>> +#define AO_PWM_CLK_E_CTRL 0x2c
>>> +#define AO_PWM_CLK_F_CTRL 0x30
>>> +#define AO_PWM_CLK_G_CTRL 0x34
>>> +#define AO_CEC_CTRL0 0x38
>>> +#define AO_CEC_CTRL1 0x3c
>>> +#define AO_RTC_BY_OSCIN_CTRL0 0x50
>>> +#define AO_RTC_BY_OSCIN_CTRL1 0x54
>>> +
>>> +#define A9_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
>>> + MESON_COMP_SEL(a9_ao_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
>>> +
>>> +#define A9_COMP_DIV(_name, _reg, _shift, _width) \
>>> + MESON_COMP_DIV(a9_ao_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
>>> +
>>> +#define A9_COMP_GATE(_name, _reg, _bit) \
>>> + MESON_COMP_GATE(a9_ao_, _name, _reg, _bit, CLK_SET_RATE_PARENT)
>>> +
>>> +static struct clk_regmap a9_ao_xtal_in = {
>>> + .data = &(struct clk_regmap_gate_data){
>>> + .offset = AO_OSCIN_CTRL,
>>> + .bit_idx = 3,
>>> + },
>>> + /*
>>> + * It may be ao_sys's parent clock, its child clocks mark
>>> + * CLK_IS_CRITICAL, So mark CLK_IS_CRITICAL for it.
>>> + */
>> I don't really get what you mean ... Could you rephrase ?
>
>
> The AO sys gate clock chain may be:
>
> ao_xtal_in->ao_xtal->ao_sys-> AO sys gate clocks
>
> "ao_xtal_in" is part of the parent chain of the AO sys gate clocks.
>
> Some of its downstream clocks are marked with CLK_IS_CRITICAL. To ensure
> those clocks remain functional, ao_xtal_in must not be disabled and is
> therefore marked as CLK_IS_CRITICAL as well.
If any of the downstream clocks are critical and marked as such, there is not
need to mark this one as well.
You should only mark the clocks that are actually critical with the flag
and let CCF figure out the dependencies.
>
>
> I will rephrase it like this in the next version:
>
> /*
> * ao_sys can select different clock sources. One possible clock
> path is:
> * ao_xtal_in->ao_xtal->ao_sys-> ao sys gate clocks
> *
> * ao_xtal_in is in the parent chain of AO sys gate clocks.
> * Since some downstream clocks are marked CLK_IS_CRITICAL,
> * ao_xtal_in must remain enabled and is therefore marked
> * CLK_IS_CRITICAL as well.
> */
>
>>> + .hw.init = CLK_HW_INIT_FW_NAME("ao_xtal_in", "xtal",
>>> + &clk_regmap_gate_ops, CLK_IS_CRITICAL),
>> I'm honestly not sure about this. It is correct, sure and the macro exist to be
>> used but ... It does not really help readability here, does it ?
>>
>> (I know that was a feedback you've got on v1)
>>
>> Other than that, this looks good to me.
>>
> Ok, I will use the original clk_init_data for this one.
Well my comment applies to whole thing really.
There are surely ways in which the macro but the way we statically
declare things, it adds a level of indirection that makes things harder
to review IMO.
>
>
> [ ... ]
>
>> --
>> Jerome
--
Jerome
^ permalink raw reply
* Re: [PATCH v3 2/2] clk: amlogic: Add A9 AO clock controller driver
From: Jerome Brunet @ 2026-06-10 12:30 UTC (permalink / raw)
To: Jian Hu via B4 Relay
Cc: Neil Armstrong, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Xianwei Zhao, Kevin Hilman,
Martin Blumenstingl, jian.hu, linux-amlogic, linux-clk,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20260610-a9_aoclk-v3-2-b7592d6c31e2@amlogic.com>
On mer. 10 juin 2026 at 16:23, Jian Hu via B4 Relay <devnull+jian.hu.amlogic.com@kernel.org> wrote:
> From: Jian Hu <jian.hu@amlogic.com>
>
> Add the Always-on clock controller driver for the Amlogic A9 SoC family.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
> drivers/clk/meson/Kconfig | 13 ++
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/a9-aoclk.c | 431 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 445 insertions(+)
>
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index cf8cf3f9e4ee..b71299898197 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -132,6 +132,19 @@ config COMMON_CLK_A1_PERIPHERALS
> device, A1 SoC Family. Say Y if you want A1 Peripherals clock
> controller to work.
>
> +config COMMON_CLK_A9_AO
> + tristate "Amlogic A9 SoC AO clock controller support"
> + depends on ARM64 || COMPILE_TEST
> + default ARCH_MESON
> + select COMMON_CLK_MESON_REGMAP
> + select COMMON_CLK_MESON_CLKC_UTILS
> + select COMMON_CLK_MESON_DUALDIV
> + imply COMMON_CLK_SCMI
> + help
> + Support for the AO clock controller on Amlogic A311Y3 based
> + device, AKA A9.
> + Say Y if you want A9 AO clock controller to work.
> +
> config COMMON_CLK_C3_PLL
> tristate "Amlogic C3 PLL clock controller"
> depends on ARM64
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index c6719694a242..f89d027c282c 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -19,6 +19,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
> obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
> obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
> obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
> +obj-$(CONFIG_COMMON_CLK_A9_AO) += a9-aoclk.o
> obj-$(CONFIG_COMMON_CLK_C3_PLL) += c3-pll.o
> obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) += c3-peripherals.o
> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
> diff --git a/drivers/clk/meson/a9-aoclk.c b/drivers/clk/meson/a9-aoclk.c
> new file mode 100644
> index 000000000000..dd9fd8d24702
> --- /dev/null
> +++ b/drivers/clk/meson/a9-aoclk.c
> @@ -0,0 +1,431 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
> +/*
> + * Copyright (C) 2026 Amlogic, Inc. All rights reserved
> + */
> +
> +#include <dt-bindings/clock/amlogic,a9-aoclkc.h>
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include "clk-regmap.h"
> +#include "clk-dualdiv.h"
> +#include "meson-clkc-utils.h"
> +
> +#define AO_OSCIN_CTRL 0x00
> +#define AO_SYS_CLK0 0x04
> +#define AO_PWM_CLK_A_CTRL 0x1c
> +#define AO_PWM_CLK_B_CTRL 0x20
> +#define AO_PWM_CLK_C_CTRL 0x24
> +#define AO_PWM_CLK_D_CTRL 0x28
> +#define AO_PWM_CLK_E_CTRL 0x2c
> +#define AO_PWM_CLK_F_CTRL 0x30
> +#define AO_PWM_CLK_G_CTRL 0x34
> +#define AO_CEC_CTRL0 0x38
> +#define AO_CEC_CTRL1 0x3c
> +#define AO_RTC_BY_OSCIN_CTRL0 0x50
> +#define AO_RTC_BY_OSCIN_CTRL1 0x54
> +
> +#define A9_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
> + MESON_COMP_SEL(a9_ao_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
> +
> +#define A9_COMP_DIV(_name, _reg, _shift, _width) \
> + MESON_COMP_DIV(a9_ao_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
> +
> +#define A9_COMP_GATE(_name, _reg, _bit) \
> + MESON_COMP_GATE(a9_ao_, _name, _reg, _bit, CLK_SET_RATE_PARENT)
> +
> +static struct clk_regmap a9_ao_xtal_in = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = AO_OSCIN_CTRL,
> + .bit_idx = 3,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "ao_xtal_in",
> + .ops = &clk_regmap_gate_ops,
> + .parent_data = &(const struct clk_parent_data) {
> + .fw_name = "xtal",
> + },
> + .num_parents = 1,
> + /*
> + * ao_sys can select different clock sources. One possible clock path is:
> + * ao_xtal_in->ao_xtal->ao_sys-> ao sys gate clocks
> + *
> + * ao_xtal_in is in the parent chain of AO sys gate clocks.
> + * Since some downstream clocks are marked CLK_IS_CRITICAL,
> + * ao_xtal_in must remain enabled and is therefore marked
> + * CLK_IS_CRITICAL as well.
> + */
> + .flags = CLK_IS_CRITICAL,
Please allow some time for me to reply before reposting.
See my answer on v2.
> + },
> +};
> +
> +static struct clk_regmap a9_ao_xtal = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = AO_OSCIN_CTRL,
> + .mask = 0x1,
> + .shift = 0,
> + },
> + /* ext_32k is from external PAD, do not automatically reparent */
> + .hw.init = CLK_HW_INIT_PARENTS_DATA("ao_xtal",
> + ((const struct clk_parent_data []) {
> + { .hw = &a9_ao_xtal_in.hw },
> + { .fw_name = "ext_32k" }
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_NO_REPARENT),
I hope my view on this is clear as well.
Let me know if it isn't
> +};
> +
> +static struct clk_regmap a9_ao_sys = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = AO_OSCIN_CTRL,
> + .mask = 0x1,
> + .shift = 1,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_DATA("ao_sys",
> + ((const struct clk_parent_data []) {
> + { .hw = &a9_ao_xtal.hw },
> + { .fw_name = "sys" }
> + }), &clk_regmap_mux_ops, 0),
> +};
> +
> +static const struct clk_parent_data a9_ao_pclk_parents = { .hw = &a9_ao_sys.hw };
> +
> +#define A9_AO_PCLK(_name, _bit, _flags) \
> + MESON_PCLK(a9_ao_sys_##_name, AO_SYS_CLK0, _bit, \
> + &a9_ao_pclk_parents, _flags)
> +
> +/*
> + * A9 integrates a low-power microprocessor (Always-on CPU: AOCPU). Some AO sys
> + * clocks control the AOCPU modules. Mark the AOCPU-related clocks with
> + * CLK_IS_CRITICAL to avoid them being disabled and impacting AOCPU functionality.
> + * AOCPU-related clocks list:
> + * - clktree
> + * - rst_ctrl
> + * - pad
> + * - irq
> + * - pwrctrl
> + * - aocpu
> + * - sram
> + */
> +static A9_AO_PCLK(i3c, 0, 0);
> +static A9_AO_PCLK(rtc_reg, 1, 0);
> +static A9_AO_PCLK(clktree, 2, CLK_IS_CRITICAL);
> +static A9_AO_PCLK(rst_ctrl, 3, CLK_IS_CRITICAL);
> +static A9_AO_PCLK(pad, 4, CLK_IS_CRITICAL);
> +static A9_AO_PCLK(rtc_dig, 5, 0);
> +static A9_AO_PCLK(irq, 6, CLK_IS_CRITICAL);
> +static A9_AO_PCLK(pwrctrl, 7, CLK_IS_CRITICAL);
> +static A9_AO_PCLK(pwm_a, 8, 0);
> +static A9_AO_PCLK(pwm_b, 9, 0);
> +static A9_AO_PCLK(pwm_c, 10, 0);
> +static A9_AO_PCLK(pwm_d, 11, 0);
> +static A9_AO_PCLK(pwm_e, 12, 0);
> +static A9_AO_PCLK(pwm_f, 13, 0);
> +static A9_AO_PCLK(pwm_g, 14, 0);
> +static A9_AO_PCLK(i2c_a, 15, 0);
> +static A9_AO_PCLK(i2c_b, 16, 0);
> +static A9_AO_PCLK(i2c_c, 17, 0);
> +static A9_AO_PCLK(i2c_d, 18, 0);
> +static A9_AO_PCLK(sed, 19, 0);
> +static A9_AO_PCLK(ir_ctrl, 20, 0);
> +static A9_AO_PCLK(uart_b, 21, 0);
> +static A9_AO_PCLK(uart_c, 22, 0);
> +static A9_AO_PCLK(uart_d, 23, 0);
> +static A9_AO_PCLK(uart_e, 24, 0);
> +static A9_AO_PCLK(spisg_0, 25, 0);
> +static A9_AO_PCLK(rtc_secure, 26, 0);
> +static A9_AO_PCLK(cec, 27, 0);
> +static A9_AO_PCLK(aocpu, 28, CLK_IS_CRITICAL);
> +static A9_AO_PCLK(sram, 29, CLK_IS_CRITICAL);
> +static A9_AO_PCLK(spisg_1, 30, 0);
> +static A9_AO_PCLK(spisg_2, 31, 0);
> +
> +static const struct clk_parent_data a9_ao_pwm_parents[] = {
> + { .hw = &a9_ao_xtal.hw },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", }
> +};
> +
> +static A9_COMP_SEL(pwm_a, AO_PWM_CLK_A_CTRL, 9, 0x7, a9_ao_pwm_parents);
> +static A9_COMP_DIV(pwm_a, AO_PWM_CLK_A_CTRL, 0, 8);
> +static A9_COMP_GATE(pwm_a, AO_PWM_CLK_A_CTRL, 8);
> +
> +static A9_COMP_SEL(pwm_b, AO_PWM_CLK_B_CTRL, 9, 0x7, a9_ao_pwm_parents);
> +static A9_COMP_DIV(pwm_b, AO_PWM_CLK_B_CTRL, 0, 8);
> +static A9_COMP_GATE(pwm_b, AO_PWM_CLK_B_CTRL, 8);
> +
> +static A9_COMP_SEL(pwm_c, AO_PWM_CLK_C_CTRL, 9, 0x7, a9_ao_pwm_parents);
> +static A9_COMP_DIV(pwm_c, AO_PWM_CLK_C_CTRL, 0, 8);
> +static A9_COMP_GATE(pwm_c, AO_PWM_CLK_C_CTRL, 8);
> +
> +static A9_COMP_SEL(pwm_d, AO_PWM_CLK_D_CTRL, 9, 0x7, a9_ao_pwm_parents);
> +static A9_COMP_DIV(pwm_d, AO_PWM_CLK_D_CTRL, 0, 8);
> +static A9_COMP_GATE(pwm_d, AO_PWM_CLK_D_CTRL, 8);
> +
> +static A9_COMP_SEL(pwm_e, AO_PWM_CLK_E_CTRL, 9, 0x7, a9_ao_pwm_parents);
> +static A9_COMP_DIV(pwm_e, AO_PWM_CLK_E_CTRL, 0, 8);
> +static A9_COMP_GATE(pwm_e, AO_PWM_CLK_E_CTRL, 8);
> +
> +static A9_COMP_SEL(pwm_f, AO_PWM_CLK_F_CTRL, 9, 0x7, a9_ao_pwm_parents);
> +static A9_COMP_DIV(pwm_f, AO_PWM_CLK_F_CTRL, 0, 8);
> +static A9_COMP_GATE(pwm_f, AO_PWM_CLK_F_CTRL, 8);
> +
> +static A9_COMP_SEL(pwm_g, AO_PWM_CLK_G_CTRL, 9, 0x7, a9_ao_pwm_parents);
> +static A9_COMP_DIV(pwm_g, AO_PWM_CLK_G_CTRL, 0, 8);
> +static A9_COMP_GATE(pwm_g, AO_PWM_CLK_G_CTRL, 8);
> +
> +static struct clk_regmap a9_ao_rtc_dualdiv_in = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = AO_RTC_BY_OSCIN_CTRL0,
> + .bit_idx = 31,
> + },
> + .hw.init = CLK_HW_INIT_HW("ao_rtc_dualdiv_in", &a9_ao_xtal.hw,
> + &clk_regmap_gate_ops, 0),
> +};
> +
> +static const struct meson_clk_dualdiv_param a9_ao_dualdiv_table[] = {
> + { 733, 732, 8, 11, 1 },
> + { /* sentinel */ }
> +};
> +
> +static struct clk_regmap a9_ao_rtc_dualdiv_div = {
> + .data = &(struct meson_clk_dualdiv_data){
> + .n1 = {
> + .reg_off = AO_RTC_BY_OSCIN_CTRL0,
> + .shift = 0,
> + .width = 12,
> + },
> + .n2 = {
> + .reg_off = AO_RTC_BY_OSCIN_CTRL0,
> + .shift = 12,
> + .width = 12,
> + },
> + .m1 = {
> + .reg_off = AO_RTC_BY_OSCIN_CTRL1,
> + .shift = 0,
> + .width = 12,
> + },
> + .m2 = {
> + .reg_off = AO_RTC_BY_OSCIN_CTRL1,
> + .shift = 12,
> + .width = 12,
> + },
> + .dual = {
> + .reg_off = AO_RTC_BY_OSCIN_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .table = a9_ao_dualdiv_table,
> + },
> + .hw.init = CLK_HW_INIT_HW("a9_ao_rtc_dualdiv_div", &a9_ao_rtc_dualdiv_in.hw,
> + &meson_clk_dualdiv_ops, 0),
> +};
> +
> +static struct clk_regmap a9_ao_rtc_dualdiv_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = AO_RTC_BY_OSCIN_CTRL1,
> + .mask = 0x1,
> + .shift = 24,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("ao_rtc_dualdiv_sel",
> + ((const struct clk_hw *[]) {
> + &a9_ao_rtc_dualdiv_div.hw,
> + &a9_ao_rtc_dualdiv_in.hw,
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_ao_rtc_dualdiv = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = AO_RTC_BY_OSCIN_CTRL0,
> + .bit_idx = 30,
> + },
> + .hw.init = CLK_HW_INIT_HW("ao_rtc_dualdiv", &a9_ao_rtc_dualdiv_sel.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_ao_rtc = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = AO_RTC_BY_OSCIN_CTRL1,
> + .mask = 0x1,
> + .shift = 30,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("ao_rtc",
> + ((const struct clk_hw *[]) {
> + &a9_ao_xtal.hw,
> + &a9_ao_rtc_dualdiv.hw,
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_ao_cec_dualdiv_in = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = AO_CEC_CTRL0,
> + .bit_idx = 31,
> + },
> + .hw.init = CLK_HW_INIT_HW("ao_cec_dualdiv_in", &a9_ao_xtal.hw,
> + &clk_regmap_gate_ops, 0),
> +};
> +
> +static struct clk_regmap a9_ao_cec_dualdiv_div = {
> + .data = &(struct meson_clk_dualdiv_data){
> + .n1 = {
> + .reg_off = AO_CEC_CTRL0,
> + .shift = 0,
> + .width = 12,
> + },
> + .n2 = {
> + .reg_off = AO_CEC_CTRL0,
> + .shift = 12,
> + .width = 12,
> + },
> + .m1 = {
> + .reg_off = AO_CEC_CTRL1,
> + .shift = 0,
> + .width = 12,
> + },
> + .m2 = {
> + .reg_off = AO_CEC_CTRL1,
> + .shift = 12,
> + .width = 12,
> + },
> + .dual = {
> + .reg_off = AO_CEC_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .table = a9_ao_dualdiv_table,
> + },
> + .hw.init = CLK_HW_INIT_HW("ao_cec_dualdiv_div", &a9_ao_cec_dualdiv_in.hw,
> + &meson_clk_dualdiv_ops, 0),
> +};
> +
> +static struct clk_regmap a9_ao_cec_dualdiv_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = AO_CEC_CTRL1,
> + .mask = 0x1,
> + .shift = 24,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("ao_cec_dualdiv_sel",
> + ((const struct clk_hw *[]) {
> + &a9_ao_cec_dualdiv_div.hw,
> + &a9_ao_cec_dualdiv_in.hw,
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_ao_cec_dualdiv = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = AO_CEC_CTRL0,
> + .bit_idx = 30,
> + },
> + .hw.init = CLK_HW_INIT_HW("ao_cec_dualdiv", &a9_ao_cec_dualdiv_sel.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_ao_cec = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = AO_CEC_CTRL1,
> + .mask = 0x1,
> + .shift = 30,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("ao_cec",
> + ((const struct clk_hw *[]) {
> + &a9_ao_cec_dualdiv.hw,
> + &a9_ao_rtc.hw,
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_hw *a9_ao_hw_clks[] = {
> + [CLKID_AO_XTAL_IN] = &a9_ao_xtal_in.hw,
> + [CLKID_AO_XTAL] = &a9_ao_xtal.hw,
> + [CLKID_AO_SYS] = &a9_ao_sys.hw,
> + [CLKID_AO_SYS_I3C] = &a9_ao_sys_i3c.hw,
> + [CLKID_AO_SYS_RTC_REG] = &a9_ao_sys_rtc_reg.hw,
> + [CLKID_AO_SYS_CLKTREE] = &a9_ao_sys_clktree.hw,
> + [CLKID_AO_SYS_RST_CTRL] = &a9_ao_sys_rst_ctrl.hw,
> + [CLKID_AO_SYS_PAD] = &a9_ao_sys_pad.hw,
> + [CLKID_AO_SYS_RTC_DIG] = &a9_ao_sys_rtc_dig.hw,
> + [CLKID_AO_SYS_IRQ] = &a9_ao_sys_irq.hw,
> + [CLKID_AO_SYS_PWRCTRL] = &a9_ao_sys_pwrctrl.hw,
> + [CLKID_AO_SYS_PWM_A] = &a9_ao_sys_pwm_a.hw,
> + [CLKID_AO_SYS_PWM_B] = &a9_ao_sys_pwm_b.hw,
> + [CLKID_AO_SYS_PWM_C] = &a9_ao_sys_pwm_c.hw,
> + [CLKID_AO_SYS_PWM_D] = &a9_ao_sys_pwm_d.hw,
> + [CLKID_AO_SYS_PWM_E] = &a9_ao_sys_pwm_e.hw,
> + [CLKID_AO_SYS_PWM_F] = &a9_ao_sys_pwm_f.hw,
> + [CLKID_AO_SYS_PWM_G] = &a9_ao_sys_pwm_g.hw,
> + [CLKID_AO_SYS_I2C_A] = &a9_ao_sys_i2c_a.hw,
> + [CLKID_AO_SYS_I2C_B] = &a9_ao_sys_i2c_b.hw,
> + [CLKID_AO_SYS_I2C_C] = &a9_ao_sys_i2c_c.hw,
> + [CLKID_AO_SYS_I2C_D] = &a9_ao_sys_i2c_d.hw,
> + [CLKID_AO_SYS_SED] = &a9_ao_sys_sed.hw,
> + [CLKID_AO_SYS_IR_CTRL] = &a9_ao_sys_ir_ctrl.hw,
> + [CLKID_AO_SYS_UART_B] = &a9_ao_sys_uart_b.hw,
> + [CLKID_AO_SYS_UART_C] = &a9_ao_sys_uart_c.hw,
> + [CLKID_AO_SYS_UART_D] = &a9_ao_sys_uart_d.hw,
> + [CLKID_AO_SYS_UART_E] = &a9_ao_sys_uart_e.hw,
> + [CLKID_AO_SYS_SPISG_0] = &a9_ao_sys_spisg_0.hw,
> + [CLKID_AO_SYS_RTC_SECURE] = &a9_ao_sys_rtc_secure.hw,
> + [CLKID_AO_SYS_CEC] = &a9_ao_sys_cec.hw,
> + [CLKID_AO_SYS_AOCPU] = &a9_ao_sys_aocpu.hw,
> + [CLKID_AO_SYS_SRAM] = &a9_ao_sys_sram.hw,
> + [CLKID_AO_SYS_SPISG_1] = &a9_ao_sys_spisg_1.hw,
> + [CLKID_AO_SYS_SPISG_2] = &a9_ao_sys_spisg_2.hw,
> + [CLKID_AO_PWM_A_SEL] = &a9_ao_pwm_a_sel.hw,
> + [CLKID_AO_PWM_A_DIV] = &a9_ao_pwm_a_div.hw,
> + [CLKID_AO_PWM_A] = &a9_ao_pwm_a.hw,
> + [CLKID_AO_PWM_B_SEL] = &a9_ao_pwm_b_sel.hw,
> + [CLKID_AO_PWM_B_DIV] = &a9_ao_pwm_b_div.hw,
> + [CLKID_AO_PWM_B] = &a9_ao_pwm_b.hw,
> + [CLKID_AO_PWM_C_SEL] = &a9_ao_pwm_c_sel.hw,
> + [CLKID_AO_PWM_C_DIV] = &a9_ao_pwm_c_div.hw,
> + [CLKID_AO_PWM_C] = &a9_ao_pwm_c.hw,
> + [CLKID_AO_PWM_D_SEL] = &a9_ao_pwm_d_sel.hw,
> + [CLKID_AO_PWM_D_DIV] = &a9_ao_pwm_d_div.hw,
> + [CLKID_AO_PWM_D] = &a9_ao_pwm_d.hw,
> + [CLKID_AO_PWM_E_SEL] = &a9_ao_pwm_e_sel.hw,
> + [CLKID_AO_PWM_E_DIV] = &a9_ao_pwm_e_div.hw,
> + [CLKID_AO_PWM_E] = &a9_ao_pwm_e.hw,
> + [CLKID_AO_PWM_F_SEL] = &a9_ao_pwm_f_sel.hw,
> + [CLKID_AO_PWM_F_DIV] = &a9_ao_pwm_f_div.hw,
> + [CLKID_AO_PWM_F] = &a9_ao_pwm_f.hw,
> + [CLKID_AO_PWM_G_SEL] = &a9_ao_pwm_g_sel.hw,
> + [CLKID_AO_PWM_G_DIV] = &a9_ao_pwm_g_div.hw,
> + [CLKID_AO_PWM_G] = &a9_ao_pwm_g.hw,
> + [CLKID_AO_RTC_DUALDIV_IN] = &a9_ao_rtc_dualdiv_in.hw,
> + [CLKID_AO_RTC_DUALDIV_DIV] = &a9_ao_rtc_dualdiv_div.hw,
> + [CLKID_AO_RTC_DUALDIV_SEL] = &a9_ao_rtc_dualdiv_sel.hw,
> + [CLKID_AO_RTC_DUALDIV] = &a9_ao_rtc_dualdiv.hw,
> + [CLKID_AO_RTC] = &a9_ao_rtc.hw,
> + [CLKID_AO_CEC_DUALDIV_IN] = &a9_ao_cec_dualdiv_in.hw,
> + [CLKID_AO_CEC_DUALDIV_DIV] = &a9_ao_cec_dualdiv_div.hw,
> + [CLKID_AO_CEC_DUALDIV_SEL] = &a9_ao_cec_dualdiv_sel.hw,
> + [CLKID_AO_CEC_DUALDIV] = &a9_ao_cec_dualdiv.hw,
> + [CLKID_AO_CEC] = &a9_ao_cec.hw,
> +};
> +
> +static const struct meson_clkc_data a9_ao_clkc_data = {
> + .hw_clks = {
> + .hws = a9_ao_hw_clks,
> + .num = ARRAY_SIZE(a9_ao_hw_clks),
> + },
> +};
> +
> +static const struct of_device_id a9_ao_clkc_match_table[] = {
> + {
> + .compatible = "amlogic,a9-aoclkc",
> + .data = &a9_ao_clkc_data,
> + },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, a9_ao_clkc_match_table);
> +
> +static struct platform_driver a9_ao_clkc_driver = {
> + .probe = meson_clkc_mmio_probe,
> + .driver = {
> + .name = "a9-aoclkc",
> + .of_match_table = a9_ao_clkc_match_table,
> + },
> +};
> +module_platform_driver(a9_ao_clkc_driver);
> +
> +MODULE_DESCRIPTION("Amlogic A9 Always-ON Clock Controller driver");
> +MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
> +MODULE_LICENSE("GPL");
> +MODULE_IMPORT_NS("CLK_MESON");
--
Jerome
^ permalink raw reply
* [PATCH] riscv: dts: spacemit: k3: Enable SD card support
From: Yixun Lan @ 2026-06-10 12:34 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Yixun Lan
Add the device tree node of SDHCI-0 controller which found on CoM260-IFX
board, it's currenty used for Micro SD card slot, and one GPIO pin is
configured as card insertion/removal detection pin, the slot use 4-bit
data bus, and up support to SDR104 speed mode.
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts | 18 +++++++++++
arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 44 ++++++++++++++++++++++++++
arch/riscv/boot/dts/spacemit/k3.dtsi | 13 ++++++++
3 files changed, 75 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
index 238bb03d0e9e..e7f76cd24b90 100644
--- a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
+++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts
@@ -19,3 +19,21 @@ chosen {
stdout-path = "serial0:115200n8";
};
};
+
+&sdhci0 {
+ pinctrl-names = "default","uhs";
+ pinctrl-0 = <&mmc1_cfg>;
+ pinctrl-1 = <&mmc1_uhs_cfg>;
+ bus-width = <4>;
+ cd-gpios = <&gpio K3_GPIO(4) GPIO_ACTIVE_HIGH>;
+ no-mmc;
+ no-sdio;
+ disable-wp;
+ cap-sd-highspeed;
+ vmmc-supply = <&aldo4>;
+ vqmmc-supply = <&aldo1>;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
index 3ee1471f3798..6b808f890a28 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
@@ -689,4 +689,48 @@ uart0-0-pins {
drive-strength = <25>;
};
};
+
+ mmc1_cfg: mmc1-cfg {
+ mmc1-data-cmd-pins {
+ pinmux = <K3_PADCONF(132, 0)>, /* mmc1 dat3 */
+ <K3_PADCONF(133, 0)>, /* mmc1 dat2 */
+ <K3_PADCONF(134, 0)>, /* mmc1 dat1 */
+ <K3_PADCONF(135, 0)>, /* mmc1 dat0 */
+ <K3_PADCONF(136, 0)>; /* mmc1 cmd */
+
+ bias-pull-up = <0>;
+ drive-strength = <25>;
+ power-source = <3300>;
+ };
+
+ mmc1-clk-pins {
+ pinmux = <K3_PADCONF(137, 0)>; /* mmc1 clk */
+
+ bias-pull-down;
+ drive-strength = <25>;
+ power-source = <3300>;
+ };
+ };
+
+ mmc1_uhs_cfg: mmc1-uhs-cfg {
+ mmc1-uhs-data-cmd-pins {
+ pinmux = <K3_PADCONF(132, 0)>, /* mmc1 dat3 */
+ <K3_PADCONF(133, 0)>, /* mmc1 dat2 */
+ <K3_PADCONF(134, 0)>, /* mmc1 dat1 */
+ <K3_PADCONF(135, 0)>, /* mmc1 dat0 */
+ <K3_PADCONF(136, 0)>; /* mmc1 cmd */
+
+ bias-pull-up = <0>;
+ drive-strength = <21>;
+ power-source = <1800>;
+ };
+
+ mmc1-uhs-clk-pins {
+ pinmux = <K3_PADCONF(137, 0)>; /* mmc1 clk */
+
+ bias-pull-down;
+ drive-strength = <21>;
+ power-source = <1800>;
+ };
+ };
};
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index 19fc9b49668e..dabb0d5e6bad 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -1099,6 +1099,19 @@ pll: clock-controller@d4090000 {
#clock-cells = <1>;
};
+ sdhci0: mmc@d4280000 {
+ compatible = "spacemit,k3-sdhci";
+ reg = <0x0 0xd4280000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_APMU_SDH_AXI>,
+ <&syscon_apmu CLK_APMU_SDH0>;
+ clock-names = "core", "io";
+ resets = <&syscon_apmu RESET_APMU_SDH_AXI>,
+ <&syscon_apmu RESET_APMU_SDH0>;
+ reset-names = "axi", "sdh";
+ interrupts = <99 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
syscon_apmu: system-controller@d4282800 {
compatible = "spacemit,k3-syscon-apmu";
reg = <0x0 0xd4282800 0x0 0x400>;
---
base-commit: 38d5f73d1f5af60d87047b981736b89521e49213
change-id: 20260609-07-k3-enable-sd-e1ddf090e87f
Best regards,
--
Yixun Lan <dlan@kernel.org>
^ permalink raw reply related
* [PATCH] dt-bindings: pinctrl: qcom,pmic-gpio: Add Qualcomm PMK7750
From: Krzysztof Kozlowski @ 2026-06-10 12:40 UTC (permalink / raw)
To: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, linux-gpio, devicetree, linux-kernel
Cc: Krzysztof Kozlowski, Abel Vesa
Document Qualcomm PMK7750 used with Eliza SoC. PMIC is almost the same
as (and compatible with) PMK8550.
Cc: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
index 386c31e9c52b..cd4593512f81 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
@@ -71,6 +71,7 @@ properties:
- qcom,pmih0108-gpio
- qcom,pmiv0104-gpio
- qcom,pmk8350-gpio
+ - qcom,pmk7750-gpio
- qcom,pmk8550-gpio
- qcom,pmk8850-gpio
- qcom,pmm8155au-gpio
@@ -173,6 +174,7 @@ allOf:
- qcom,pm8018-gpio
- qcom,pm8019-gpio
- qcom,pm8550vs-gpio
+ - qcom,pmk7750-gpio
- qcom,pmk8550-gpio
then:
properties:
@@ -501,6 +503,7 @@ $defs:
- gpio1-gpio10 for pmi8994
- gpio1-gpio18 for pmih0108
- gpio1-gpio4 for pmk8350
+ - gpio1-gpio6 for pmk7750
- gpio1-gpio6 for pmk8550
- gpio1-gpio8 for pmk8850
- gpio1-gpio10 for pmm8155au
--
2.53.0
^ permalink raw reply related
* [PATCH] dt-bindings: mfd: qcom,spmi-pmic: Add Qualcomm PMK7750
From: Krzysztof Kozlowski @ 2026-06-10 12:41 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Stephen Boyd, linux-arm-msm, devicetree, linux-kernel
Cc: Krzysztof Kozlowski, Abel Vesa
Document Qualcomm PMK7750 used with Eliza SoC. PMIC is almost the same
as (and compatible with) PMK8550.
Cc: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
index 644c42b5e2e5..ae7f91914b2f 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
@@ -90,6 +90,7 @@ properties:
- qcom,pmi8998
- qcom,pmih0108
- qcom,pmiv0104
+ - qcom,pmk7750
- qcom,pmk8002
- qcom,pmk8350
- qcom,pmk8550
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v3 2/2] clk: amlogic: Add A9 peripherals clock controller driver
From: Jerome Brunet @ 2026-06-10 12:49 UTC (permalink / raw)
To: Jian Hu via B4 Relay
Cc: Neil Armstrong, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Xianwei Zhao, Kevin Hilman,
Martin Blumenstingl, jian.hu, linux-amlogic, linux-clk,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20260610-a9_peripherals-v3-2-d07a78085f71@amlogic.com>
On mer. 10 juin 2026 at 16:14, Jian Hu via B4 Relay <devnull+jian.hu.amlogic.com@kernel.org> wrote:
> From: Jian Hu <jian.hu@amlogic.com>
>
> Add the peripherals clock controller driver for the Amlogic A9 SoC family.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
> drivers/clk/meson/Kconfig | 15 +
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/a9-peripherals.c | 1925 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 1941 insertions(+)
>
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index cf8cf3f9e4ee..86d2e270e1b8 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -132,6 +132,21 @@ config COMMON_CLK_A1_PERIPHERALS
> device, A1 SoC Family. Say Y if you want A1 Peripherals clock
> controller to work.
>
> +config COMMON_CLK_A9_PERIPHERALS
> + tristate "Amlogic A9 SoC peripherals clock controller support"
> + depends on ARM64 || COMPILE_TEST
> + default ARCH_MESON
> + select COMMON_CLK_MESON_REGMAP
> + select COMMON_CLK_MESON_CLKC_UTILS
> + select COMMON_CLK_MESON_DUALDIV
> + select COMMON_CLK_MESON_VID_PLL_DIV
> + imply COMMON_CLK_SCMI
> + imply COMMON_CLK_A9_PLL
> + help
> + Support for the peripherals clock controller on Amlogic A311Y3 based
> + device, AKA A9. Peripherals are required by most peripheral to operate.
> + Say Y if you want A9 peripherals clock controller to work.
> +
> config COMMON_CLK_C3_PLL
> tristate "Amlogic C3 PLL clock controller"
> depends on ARM64
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index c6719694a242..bccd9ace9201 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -19,6 +19,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
> obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
> obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
> obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
> +obj-$(CONFIG_COMMON_CLK_A9_PERIPHERALS) += a9-peripherals.o
> obj-$(CONFIG_COMMON_CLK_C3_PLL) += c3-pll.o
> obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) += c3-peripherals.o
> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
> diff --git a/drivers/clk/meson/a9-peripherals.c b/drivers/clk/meson/a9-peripherals.c
> new file mode 100644
> index 000000000000..fef48613e186
> --- /dev/null
> +++ b/drivers/clk/meson/a9-peripherals.c
> @@ -0,0 +1,1925 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
> +/*
> + * Copyright (C) 2026 Amlogic, Inc. All rights reserved
> + */
> +
> +#include <dt-bindings/clock/amlogic,a9-peripherals-clkc.h>
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include "clk-regmap.h"
> +#include "clk-dualdiv.h"
> +#include "meson-clkc-utils.h"
> +#include "vid-pll-div.h"
> +
> +#define SYS_CLK_EN0_REG0 0x30
> +#define SYS_CLK_EN0_REG1 0x34
> +#define SYS_CLK_EN0_REG2 0x38
> +#define SYS_CLK_EN0_REG3 0x3c
> +#define SD_EMMC_CLK_CTRL0 0x90
> +#define SD_EMMC_CLK_CTRL1 0x94
> +#define PWM_CLK_H_CTRL 0xbc
> +#define PWM_CLK_I_CTRL 0xc0
> +#define PWM_CLK_J_CTRL 0xc4
> +#define PWM_CLK_K_CTRL 0xc8
> +#define PWM_CLK_L_CTRL 0xcc
> +#define PWM_CLK_M_CTRL 0xd0
> +#define PWM_CLK_N_CTRL 0xd4
> +#define SPISG_CLK_CTRL 0x100
> +#define SPISG_CLK_CTRL1 0x104
> +#define SAR_CLK_CTRL 0x150
> +#define AMFC_CLK_CTRL 0x154
> +#define NNA_CLK_CTRL 0x15c
> +#define USB_CLK_CTRL 0x160
> +#define PCIE_TL_CLK_CTRL 0x164
> +#define CMPR_CLK_CTRL 0x168
> +#define DEWARP_CLK_CTRL 0x16c
> +#define SC_CLK_CTRL 0x170
> +#define DPTX_CLK_CTRL 0x178
> +#define ISP_CLK_CTRL 0x17c
> +#define CVE_CLK_CTRL 0x180
> +#define PP_CLK_CTRL 0x184
> +#define GLB_CLK_CTRL 0x188
> +#define USB_CLK_CTRL0 0x18c
> +#define USB_CLK_CTRL1 0x190
> +#define CAN_CLK_CTRL 0x194
> +#define CAN_CLK_CTRL1 0x198
> +#define I3C_CLK_CTRL 0x19c
> +#define TS_CLK_CTRL 0x1a0
> +#define ETH_CLK_CTRL 0x1a4
> +#define GEN_CLK_CTRL 0x1a8
> +#define CLK12_24_CTRL 0x1ac
> +#define MALI_CLK_CTRL 0x200
> +#define MALI_STACK_CLK_CTRL 0x204
> +#define DSPA_CLK_CTRL 0x220
> +#define HEVCF_CLK_CTRL 0x240
> +#define HCODEC_CLK_CTRL 0x244
> +#define VPU_CLK_CTRL 0x260
> +#define VAPB_CLK_CTRL 0x268
> +#define VPU_CLKB_CTRL 0x280
> +#define HDMI_CLK_CTRL 0x284
> +#define HTX_CLK_CTRL 0x28c
> +#define HTX_CLK_CTRL1 0x290
> +#define HRX_CLK_CTRL 0x294
> +#define HRX_CLK_CTRL1 0x298
> +#define HRX_CLK_CTRL2 0x29c
> +#define HRX_CLK_CTRL3 0x2a0
> +#define VID_LOCK_CLK_CTRL 0x2a4
> +#define VDIN_MEAS_CLK_CTRL 0x2a8
> +#define VID_PLL_CLK_DIV 0x2b0
> +#define VID_CLK_CTRL 0x2c0
> +#define VID_CLK_CTRL2 0x2c4
> +#define VID_CLK_DIV 0x2c8
> +#define VIID_CLK_DIV 0x2cc
> +#define VIID_CLK_CTRL 0x2d0
> +#define MIPI_CSI_PHY_CLK_CTRL 0x2e0
> +#define DSI_MEAS_CLK_CTRL 0x2f4
> +
> +#define A9_COMP_SEL(_name, _reg, _shift, _mask, _pdata, _table) \
> + MESON_COMP_SEL(a9_, _name, _reg, _shift, _mask, _pdata, _table, 0, 0)
> +
> +#define A9_COMP_DIV(_name, _reg, _shift, _width) \
> + MESON_COMP_DIV(a9_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
> +
> +#define A9_COMP_GATE(_name, _reg, _bit, _iflags) \
> + MESON_COMP_GATE(a9_, _name, _reg, _bit, CLK_SET_RATE_PARENT | (_iflags))
> +
> +static const struct clk_parent_data a9_sys_pclk_parents = { .fw_name = "sys" };
> +
> +#define A9_SYS_PCLK(_name, _reg, _bit) \
> + MESON_PCLK(a9_##_name, _reg, _bit, &a9_sys_pclk_parents, 0)
> +
> +static A9_SYS_PCLK(sys_am_axi, SYS_CLK_EN0_REG0, 0);
> +static A9_SYS_PCLK(sys_dos, SYS_CLK_EN0_REG0, 1);
> +static A9_SYS_PCLK(sys_mipi_dsi, SYS_CLK_EN0_REG0, 3);
> +static A9_SYS_PCLK(sys_eth_phy, SYS_CLK_EN0_REG0, 4);
> +static A9_SYS_PCLK(sys_amfc, SYS_CLK_EN0_REG0, 5);
> +static A9_SYS_PCLK(sys_mali, SYS_CLK_EN0_REG0, 6);
> +static A9_SYS_PCLK(sys_nna, SYS_CLK_EN0_REG0, 7);
> +static A9_SYS_PCLK(sys_eth_axi, SYS_CLK_EN0_REG0, 8);
> +static A9_SYS_PCLK(sys_dp_apb, SYS_CLK_EN0_REG0, 9);
> +static A9_SYS_PCLK(sys_edptx_apb, SYS_CLK_EN0_REG0, 10);
> +static A9_SYS_PCLK(sys_u3hsg, SYS_CLK_EN0_REG0, 11);
> +static A9_SYS_PCLK(sys_aucpu, SYS_CLK_EN0_REG0, 14);
> +static A9_SYS_PCLK(sys_glb, SYS_CLK_EN0_REG0, 15);
> +static A9_SYS_PCLK(sys_combo_dphy_apb, SYS_CLK_EN0_REG0, 17);
> +static A9_SYS_PCLK(sys_hdmirx_apb, SYS_CLK_EN0_REG0, 18);
> +static A9_SYS_PCLK(sys_hdmirx_pclk, SYS_CLK_EN0_REG0, 19);
> +static A9_SYS_PCLK(sys_mipi_dsi_phy, SYS_CLK_EN0_REG0, 20);
> +static A9_SYS_PCLK(sys_can0, SYS_CLK_EN0_REG0, 21);
> +static A9_SYS_PCLK(sys_can1, SYS_CLK_EN0_REG0, 22);
> +static A9_SYS_PCLK(sys_sd_emmc_a, SYS_CLK_EN0_REG0, 24);
> +static A9_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG0, 25);
> +static A9_SYS_PCLK(sys_sd_emmc_c, SYS_CLK_EN0_REG0, 26);
> +static A9_SYS_PCLK(sys_sc, SYS_CLK_EN0_REG0, 27);
> +static A9_SYS_PCLK(sys_acodec, SYS_CLK_EN0_REG0, 28);
> +static A9_SYS_PCLK(sys_mipi_isp, SYS_CLK_EN0_REG0, 29);
> +static A9_SYS_PCLK(sys_msr, SYS_CLK_EN0_REG0, 30);
> +static A9_SYS_PCLK(sys_audio, SYS_CLK_EN0_REG1, 0);
> +static A9_SYS_PCLK(sys_mipi_dsi_b, SYS_CLK_EN0_REG1, 1);
> +static A9_SYS_PCLK(sys_mipi_dsi1_phy, SYS_CLK_EN0_REG1, 2);
> +static A9_SYS_PCLK(sys_eth, SYS_CLK_EN0_REG1, 3);
> +static A9_SYS_PCLK(sys_eth_1g_mac, SYS_CLK_EN0_REG1, 4);
> +static A9_SYS_PCLK(sys_uart_a, SYS_CLK_EN0_REG1, 5);
> +static A9_SYS_PCLK(sys_uart_f, SYS_CLK_EN0_REG1, 10);
> +static A9_SYS_PCLK(sys_ts_a55, SYS_CLK_EN0_REG1, 11);
> +static A9_SYS_PCLK(sys_eth_1g_axi, SYS_CLK_EN0_REG1, 12);
> +static A9_SYS_PCLK(sys_ts_dos, SYS_CLK_EN0_REG1, 13);
> +static A9_SYS_PCLK(sys_u3drd_b, SYS_CLK_EN0_REG1, 14);
> +static A9_SYS_PCLK(sys_ts_core, SYS_CLK_EN0_REG1, 15);
> +static A9_SYS_PCLK(sys_ts_pll, SYS_CLK_EN0_REG1, 16);
> +static A9_SYS_PCLK(sys_csi_dig_clkin, SYS_CLK_EN0_REG1, 18);
> +static A9_SYS_PCLK(sys_cve, SYS_CLK_EN0_REG1, 19);
> +static A9_SYS_PCLK(sys_ge2d, SYS_CLK_EN0_REG1, 20);
> +static A9_SYS_PCLK(sys_spisg, SYS_CLK_EN0_REG1, 21);
> +static A9_SYS_PCLK(sys_u3drd_1, SYS_CLK_EN0_REG1, 22);
> +static A9_SYS_PCLK(sys_u2h, SYS_CLK_EN0_REG1, 23);
> +static A9_SYS_PCLK(sys_pcie_mac_a, SYS_CLK_EN0_REG1, 24);
> +static A9_SYS_PCLK(sys_u3drd_a, SYS_CLK_EN0_REG1, 25);
> +static A9_SYS_PCLK(sys_u2drd, SYS_CLK_EN0_REG1, 26);
> +static A9_SYS_PCLK(sys_pcie_phy, SYS_CLK_EN0_REG1, 27);
> +static A9_SYS_PCLK(sys_pcie_mac_b, SYS_CLK_EN0_REG1, 28);
> +static A9_SYS_PCLK(sys_periph, SYS_CLK_EN0_REG1, 29);
> +static A9_SYS_PCLK(sys_pio, SYS_CLK_EN0_REG2, 0);
> +static A9_SYS_PCLK(sys_i3c, SYS_CLK_EN0_REG2, 1);
> +static A9_SYS_PCLK(sys_i2c_m_e, SYS_CLK_EN0_REG2, 2);
> +static A9_SYS_PCLK(sys_i2c_m_f, SYS_CLK_EN0_REG2, 3);
> +static A9_SYS_PCLK(sys_hdmitx_apb, SYS_CLK_EN0_REG2, 4);
> +static A9_SYS_PCLK(sys_i2c_m_i, SYS_CLK_EN0_REG2, 5);
> +static A9_SYS_PCLK(sys_i2c_m_g, SYS_CLK_EN0_REG2, 6);
> +static A9_SYS_PCLK(sys_i2c_m_h, SYS_CLK_EN0_REG2, 7);
> +static A9_SYS_PCLK(sys_hdmi20_aes, SYS_CLK_EN0_REG2, 9);
> +static A9_SYS_PCLK(sys_csi2_host, SYS_CLK_EN0_REG2, 16);
> +static A9_SYS_PCLK(sys_csi2_adapt, SYS_CLK_EN0_REG2, 17);
> +static A9_SYS_PCLK(sys_dspa, SYS_CLK_EN0_REG2, 21);
> +static A9_SYS_PCLK(sys_pp_dma, SYS_CLK_EN0_REG2, 22);
> +static A9_SYS_PCLK(sys_pp_wrapper, SYS_CLK_EN0_REG2, 23);
> +static A9_SYS_PCLK(sys_vpu_intr, SYS_CLK_EN0_REG2, 25);
> +static A9_SYS_PCLK(sys_csi2_phy, SYS_CLK_EN0_REG2, 27);
> +static A9_SYS_PCLK(sys_saradc, SYS_CLK_EN0_REG2, 28);
> +static A9_SYS_PCLK(sys_pwm_j, SYS_CLK_EN0_REG2, 30);
> +static A9_SYS_PCLK(sys_pwm_i, SYS_CLK_EN0_REG2, 31);
> +static A9_SYS_PCLK(sys_pwm_h, SYS_CLK_EN0_REG3, 0);
> +static A9_SYS_PCLK(sys_pwm_n, SYS_CLK_EN0_REG3, 8);
> +static A9_SYS_PCLK(sys_pwm_m, SYS_CLK_EN0_REG3, 9);
> +static A9_SYS_PCLK(sys_pwm_l, SYS_CLK_EN0_REG3, 10);
> +static A9_SYS_PCLK(sys_pwm_k, SYS_CLK_EN0_REG3, 11);
> +
> +/* Channel 5 is unconnected. */
> +static u32 a9_sd_emmc_parents_val_table[] = { 0, 1, 2, 3, 4, 6, 7 };
> +static const struct clk_parent_data a9_sd_emmc_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv2", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "hifi0", },
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "gp1", },
> + { .fw_name = "gp0", }
> +};
> +
> +static A9_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL0, 9, 0x7, a9_sd_emmc_parents,
> + a9_sd_emmc_parents_val_table);
> +static A9_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL0, 0, 7);
> +static A9_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL0, 8, 0);
> +
> +static A9_COMP_SEL(sd_emmc_b, SD_EMMC_CLK_CTRL0, 25, 0x7, a9_sd_emmc_parents,
> + a9_sd_emmc_parents_val_table);
> +static A9_COMP_DIV(sd_emmc_b, SD_EMMC_CLK_CTRL0, 16, 7);
> +static A9_COMP_GATE(sd_emmc_b, SD_EMMC_CLK_CTRL0, 24, 0);
> +
> +static A9_COMP_SEL(sd_emmc_c, SD_EMMC_CLK_CTRL1, 9, 0x7, a9_sd_emmc_parents,
> + a9_sd_emmc_parents_val_table);
> +static A9_COMP_DIV(sd_emmc_c, SD_EMMC_CLK_CTRL1, 0, 7);
> +static A9_COMP_GATE(sd_emmc_c, SD_EMMC_CLK_CTRL1, 8, 0);
> +
> +static const struct clk_parent_data a9_pwm_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", }
> +};
> +
> +static A9_COMP_SEL(pwm_h, PWM_CLK_H_CTRL, 9, 0x7, a9_pwm_parents, NULL);
> +static A9_COMP_DIV(pwm_h, PWM_CLK_H_CTRL, 0, 8);
> +static A9_COMP_GATE(pwm_h, PWM_CLK_H_CTRL, 8, 0);
> +
> +static A9_COMP_SEL(pwm_i, PWM_CLK_I_CTRL, 9, 0x7, a9_pwm_parents, NULL);
> +static A9_COMP_DIV(pwm_i, PWM_CLK_I_CTRL, 0, 8);
> +static A9_COMP_GATE(pwm_i, PWM_CLK_I_CTRL, 8, 0);
> +
> +static A9_COMP_SEL(pwm_j, PWM_CLK_J_CTRL, 9, 0x7, a9_pwm_parents, NULL);
> +static A9_COMP_DIV(pwm_j, PWM_CLK_J_CTRL, 0, 8);
> +static A9_COMP_GATE(pwm_j, PWM_CLK_J_CTRL, 8, 0);
> +
> +static A9_COMP_SEL(pwm_k, PWM_CLK_K_CTRL, 9, 0x7, a9_pwm_parents, NULL);
> +static A9_COMP_DIV(pwm_k, PWM_CLK_K_CTRL, 0, 8);
> +static A9_COMP_GATE(pwm_k, PWM_CLK_K_CTRL, 8, 0);
> +
> +static A9_COMP_SEL(pwm_l, PWM_CLK_L_CTRL, 9, 0x7, a9_pwm_parents, NULL);
> +static A9_COMP_DIV(pwm_l, PWM_CLK_L_CTRL, 0, 8);
> +static A9_COMP_GATE(pwm_l, PWM_CLK_L_CTRL, 8, 0);
> +
> +static A9_COMP_SEL(pwm_m, PWM_CLK_M_CTRL, 9, 0x7, a9_pwm_parents, NULL);
> +static A9_COMP_DIV(pwm_m, PWM_CLK_M_CTRL, 0, 8);
> +static A9_COMP_GATE(pwm_m, PWM_CLK_M_CTRL, 8, 0);
> +
> +static A9_COMP_SEL(pwm_n, PWM_CLK_N_CTRL, 9, 0x7, a9_pwm_parents, NULL);
> +static A9_COMP_DIV(pwm_n, PWM_CLK_N_CTRL, 0, 8);
> +static A9_COMP_GATE(pwm_n, PWM_CLK_N_CTRL, 8, 0);
> +
> +static const struct clk_parent_data a9_spisg_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "sys", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv2", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv7", },
> + { .fw_name = "gp0", }
> +};
> +
> +static A9_COMP_SEL(spisg, SPISG_CLK_CTRL, 9, 0x7, a9_spisg_parents, NULL);
> +static A9_COMP_DIV(spisg, SPISG_CLK_CTRL, 0, 6);
> +static A9_COMP_GATE(spisg, SPISG_CLK_CTRL, 8, 0);
> +
> +static A9_COMP_SEL(spisg1, SPISG_CLK_CTRL, 25, 0x7, a9_spisg_parents, NULL);
> +static A9_COMP_DIV(spisg1, SPISG_CLK_CTRL, 16, 6);
> +static A9_COMP_GATE(spisg1, SPISG_CLK_CTRL, 24, 0);
> +
> +static A9_COMP_SEL(spisg2, SPISG_CLK_CTRL1, 9, 0x7, a9_spisg_parents, NULL);
> +static A9_COMP_DIV(spisg2, SPISG_CLK_CTRL1, 0, 6);
> +static A9_COMP_GATE(spisg2, SPISG_CLK_CTRL1, 8, 0);
> +
> +static const struct clk_parent_data a9_saradc_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "sys", }
> +};
> +
> +static A9_COMP_SEL(saradc, SAR_CLK_CTRL, 9, 0x7, a9_saradc_parents, NULL);
> +static A9_COMP_DIV(saradc, SAR_CLK_CTRL, 0, 8);
> +static A9_COMP_GATE(saradc, SAR_CLK_CTRL, 8, 0);
> +
> +static const struct clk_parent_data a9_amfc_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "sys", },
> + { .fw_name = "fdiv2", },
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv7", }
> +};
> +
> +static A9_COMP_SEL(amfc, AMFC_CLK_CTRL, 9, 0x7, a9_amfc_parents, NULL);
> +static A9_COMP_DIV(amfc, AMFC_CLK_CTRL, 0, 6);
> +static A9_COMP_GATE(amfc, AMFC_CLK_CTRL, 8, 0);
> +
> +static const struct clk_parent_data a9_nna_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv2", },
> + { .fw_name = "gp2", },
> + { .fw_name = "hifi0", }
> +};
> +
> +static A9_COMP_SEL(nna, NNA_CLK_CTRL, 9, 0x7, a9_nna_parents, NULL);
> +static A9_COMP_DIV(nna, NNA_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(nna, NNA_CLK_CTRL, 8, 0);
> +
> +/* Channel 5 and 6 are unconnected. */
> +static u32 a9_usb_250m_parents_val_table[] = { 0, 1, 2, 3, 4, 7 };
> +static const struct clk_parent_data a9_usb_250m_parents[] = {
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv2", },
> + { .fw_name = "fdiv7", },
> + { .fw_name = "fdiv2p5", }
> +};
> +
> +static A9_COMP_SEL(usb_250m, USB_CLK_CTRL, 9, 0x7, a9_usb_250m_parents,
> + a9_usb_250m_parents_val_table);
> +static A9_COMP_DIV(usb_250m, USB_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(usb_250m, USB_CLK_CTRL, 8, 0);
> +
> +static const struct clk_parent_data a9_usb_48m_pre_parents[] = {
> + { .fw_name = "gp0", },
> + { .fw_name = "gp1", },
> + { .fw_name = "gp2", },
> + { .fw_name = "fdiv2", },
> +};
> +
> +static A9_COMP_SEL(usb_48m_pre, USB_CLK_CTRL, 25, 0x3, a9_usb_48m_pre_parents,
> + NULL);
> +static A9_COMP_DIV(usb_48m_pre, USB_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(usb_48m_pre, USB_CLK_CTRL, 24, 0);
> +
> +static const struct clk_parent_data a9_pcie_tl_parents[] = {
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv2", },
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "gp0", },
> + { .fw_name = "sys", },
> + { .fw_name = "xtal", }
> +};
> +
> +static A9_COMP_SEL(pcie_tl, PCIE_TL_CLK_CTRL, 9, 0x7, a9_pcie_tl_parents,
> + NULL);
> +static A9_COMP_DIV(pcie_tl, PCIE_TL_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(pcie_tl, PCIE_TL_CLK_CTRL, 8, 0);
> +
> +static A9_COMP_SEL(pcie1_tl, PCIE_TL_CLK_CTRL, 25, 0x7, a9_pcie_tl_parents,
> + NULL);
> +static A9_COMP_DIV(pcie1_tl, PCIE_TL_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(pcie1_tl, PCIE_TL_CLK_CTRL, 24, 0);
> +
> +static const struct clk_parent_data a9_cmpr_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv7", },
> + { .fw_name = "hifi0", },
> + { .fw_name = "gp1", }
> +};
> +
> +static A9_COMP_SEL(cmpr, CMPR_CLK_CTRL, 25, 0x7, a9_cmpr_parents, NULL);
> +static A9_COMP_DIV(cmpr, CMPR_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(cmpr, CMPR_CLK_CTRL, 24, 0);
> +
> +static const struct clk_parent_data a9_dewarpa_parents[] = {
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv7", },
> + { .fw_name = "gp0", },
> + { .fw_name = "hifi0", },
> + { .fw_name = "gp1", }
> +};
> +
> +static A9_COMP_SEL(dewarpa, DEWARP_CLK_CTRL, 9, 0x7, a9_dewarpa_parents, NULL);
> +static A9_COMP_DIV(dewarpa, DEWARP_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(dewarpa, DEWARP_CLK_CTRL, 8, 0);
> +
> +static const struct clk_parent_data a9_sc_parents[] = {
> + { .fw_name = "fdiv2", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "xtal", }
> +};
> +
> +static A9_COMP_SEL(sc_pre, SC_CLK_CTRL, 9, 0x7, a9_sc_parents, NULL);
> +static A9_COMP_DIV(sc_pre, SC_CLK_CTRL, 0, 8);
> +static A9_COMP_GATE(sc_pre, SC_CLK_CTRL, 8, 0);
> +
> +static struct clk_regmap a9_sc = {
> + .data = &(struct clk_regmap_div_data) {
> + .offset = SC_CLK_CTRL,
> + .shift = 16,
> + .width = 4,
> + },
> + .hw.init = CLK_HW_INIT_HW("sc", &a9_sc_pre.hw,
> + &clk_regmap_divider_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static const struct clk_parent_data a9_dptx_apb2_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "sys", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", }
> +};
> +
> +static A9_COMP_SEL(dptx_apb2, DPTX_CLK_CTRL, 9, 0x7, a9_dptx_apb2_parents, NULL);
> +static A9_COMP_DIV(dptx_apb2, DPTX_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(dptx_apb2, DPTX_CLK_CTRL, 8, 0);
> +
> +static const struct clk_parent_data a9_dptx_aud_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "sys", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", }
> +};
> +
> +static A9_COMP_SEL(dptx_aud, DPTX_CLK_CTRL, 25, 0x7, a9_dptx_aud_parents, NULL);
> +static A9_COMP_DIV(dptx_aud, DPTX_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(dptx_aud, DPTX_CLK_CTRL, 24, 0);
> +
> +static const struct clk_parent_data a9_isp_parents[] = {
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "gp0", },
> + { .fw_name = "hifi0", },
> + { .fw_name = "fdiv2", },
> + { .fw_name = "xtal", }
> +};
> +
> +static A9_COMP_SEL(isp, ISP_CLK_CTRL, 9, 0x7, a9_isp_parents, NULL);
> +static A9_COMP_DIV(isp, ISP_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(isp, ISP_CLK_CTRL, 8, 0);
> +
> +static const struct clk_parent_data a9_cve_vge_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "hifi0", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "gp0", },
> + { .fw_name = "rtc", }
> +};
> +
> +static A9_COMP_SEL(cve, CVE_CLK_CTRL, 9, 0x7, a9_cve_vge_parents, NULL);
> +static A9_COMP_DIV(cve, CVE_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(cve, CVE_CLK_CTRL, 8, 0);
> +
> +static A9_COMP_SEL(vge, CVE_CLK_CTRL, 25, 0x7, a9_cve_vge_parents, NULL);
> +static A9_COMP_DIV(vge, CVE_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(vge, CVE_CLK_CTRL, 24, 0);
> +
> +static const struct clk_parent_data a9_pp_parents[] = {
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv2", },
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "gp0", },
> + { .fw_name = "sys", },
> + { .fw_name = "xtal", }
> +};
> +
> +static A9_COMP_SEL(pp, PP_CLK_CTRL, 9, 0x7, a9_pp_parents, NULL);
> +static A9_COMP_DIV(pp, PP_CLK_CTRL, 0, 6);
> +static A9_COMP_GATE(pp, PP_CLK_CTRL, 8, 0);
> +
> +/* Channel 6 is unconnected. */
> +static u32 a9_glb_parents_val_table[] = { 0, 1, 2, 3, 4, 5, 7 };
> +static struct clk_regmap a9_dspa;
What is this ?
> +
> +static const struct clk_parent_data a9_glb_parents[] = {
> + { .fw_name = "xtal", },
> + { .hw = &a9_dspa.hw },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", },
> + { .hw = &a9_isp.hw },
> + { .fw_name = "rtc", }
> +};
> +
> +static A9_COMP_SEL(glb, GLB_CLK_CTRL, 9, 0x7, a9_glb_parents,
> + a9_glb_parents_val_table);
> +static A9_COMP_DIV(glb, GLB_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(glb, GLB_CLK_CTRL, 8, 0);
> +
> +static struct clk_regmap a9_usb_48m_dualdiv_in = {
> + .data = &(struct clk_regmap_gate_data) {
> + .offset = USB_CLK_CTRL,
> + .bit_idx = 31,
> + },
> + .hw.init = CLK_HW_INIT_HW("usb_48m_dualdiv_in", &a9_usb_48m_pre.hw,
> + &clk_regmap_gate_ops, 0),
Same comment as on the AO controller
> +};
> +
> +static const struct meson_clk_dualdiv_param a9_usb_48m_dualdiv_div_table[] = {
> + { 733, 732, 8, 11, 1 },
> + { /* sentinel */ }
> +};
> +
> +static struct clk_regmap a9_usb_48m_dualdiv_div = {
> + .data = &(struct meson_clk_dualdiv_data) {
> + .n1 = {
> + .reg_off = USB_CLK_CTRL0,
> + .shift = 0,
> + .width = 12,
> + },
> + .n2 = {
> + .reg_off = USB_CLK_CTRL0,
> + .shift = 12,
> + .width = 12,
> + },
> + .m1 = {
> + .reg_off = USB_CLK_CTRL1,
> + .shift = 0,
> + .width = 12,
> + },
> + .m2 = {
> + .reg_off = USB_CLK_CTRL1,
> + .shift = 12,
> + .width = 12,
> + },
> + .dual = {
> + .reg_off = USB_CLK_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .table = a9_usb_48m_dualdiv_div_table,
> + },
> + .hw.init = CLK_HW_INIT_HW("usb_48m_dualdiv_div", &a9_usb_48m_dualdiv_in.hw,
> + &meson_clk_dualdiv_ops, 0),
> +};
> +
> +static struct clk_regmap a9_usb_48m_dualdiv_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = USB_CLK_CTRL1,
> + .mask = 0x1,
> + .shift = 24,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("usb_48m_dualdiv_sel",
> + ((const struct clk_hw *[]) {
> + &a9_usb_48m_dualdiv_in.hw,
> + &a9_usb_48m_dualdiv_div.hw,
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_usb_48m_dualdiv = {
> + .data = &(struct clk_regmap_gate_data) {
> + .offset = USB_CLK_CTRL0,
> + .bit_idx = 30,
> + },
> + .hw.init = CLK_HW_INIT_HW("usb_48m_dualdiv", &a9_usb_48m_dualdiv_sel.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_usb_48m = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = USB_CLK_CTRL1,
> + .mask = 0x3,
> + .shift = 30,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("usb_48m",
> + ((const struct clk_hw *[]) {
> + &a9_usb_48m_pre.hw,
> + &a9_usb_48m_dualdiv.hw,
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +/* Channel 3 is unconnected. */
You meant 3rd I guess but this is misleading and confusing with the
table bellow. Channel 2 would be more appropriate I think, since those
are 0-based.
> +static u32 a9_can_pe_parents_val_table[] = { 0, 1, 3 };
> +static const struct clk_parent_data a9_can_pe_parents[] = {
> + { .fw_name = "sys", },
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv5", }
> +};
> +
> +static A9_COMP_SEL(can_pe, CAN_CLK_CTRL, 9, 0x7, a9_can_pe_parents,
> + a9_can_pe_parents_val_table);
> +static A9_COMP_DIV(can_pe, CAN_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(can_pe, CAN_CLK_CTRL, 8, 0);
> +
> +static A9_COMP_SEL(can1_pe, CAN_CLK_CTRL, 25, 0x7, a9_can_pe_parents,
> + a9_can_pe_parents_val_table);
> +static A9_COMP_DIV(can1_pe, CAN_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(can1_pe, CAN_CLK_CTRL, 24, 0);
> +
> +static const struct clk_parent_data a9_can_filter_parents[] = {
> + { .fw_name = "sys", },
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", }
> +};
> +
> +static A9_COMP_SEL(can_filter, CAN_CLK_CTRL1, 9, 0x7, a9_can_filter_parents,
> + NULL);
> +static A9_COMP_DIV(can_filter, CAN_CLK_CTRL1, 0, 7);
> +static A9_COMP_GATE(can_filter, CAN_CLK_CTRL1, 8, 0);
> +
> +static A9_COMP_SEL(can1_filter, CAN_CLK_CTRL1, 25, 0x7, a9_can_filter_parents,
> + NULL);
> +static A9_COMP_DIV(can1_filter, CAN_CLK_CTRL1, 16, 7);
> +static A9_COMP_GATE(can1_filter, CAN_CLK_CTRL1, 24, 0);
> +
> +static const struct clk_parent_data a9_i3c_parents[] = {
> + { .fw_name = "sys", },
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv5", }
> +};
> +
> +static A9_COMP_SEL(i3c, I3C_CLK_CTRL, 9, 0x7, a9_i3c_parents, NULL);
> +static A9_COMP_DIV(i3c, I3C_CLK_CTRL, 0, 8);
> +static A9_COMP_GATE(i3c, I3C_CLK_CTRL, 8, 0);
> +
> +static struct clk_regmap a9_ts_div = {
> + .data = &(struct clk_regmap_div_data) {
> + .offset = TS_CLK_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = CLK_HW_INIT_FW_NAME("ts_div", "xtal",
> + &clk_regmap_divider_ops, 0),
> +};
> +
> +static struct clk_regmap a9_ts = {
> + .data = &(struct clk_regmap_gate_data) {
> + .offset = TS_CLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = CLK_HW_INIT_HW("ts", &a9_ts_div.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_fixed_factor a9_eth_125m_div = {
> + .mult = 1,
> + .div = 8,
> + .hw.init = CLK_HW_INIT_FW_NAME("eth_125m_div", "fdiv2",
> + &clk_fixed_factor_ops, 0),
> +};
> +
> +static struct clk_regmap a9_eth_125m = {
> + .data = &(struct clk_regmap_gate_data) {
> + .offset = ETH_CLK_CTRL,
> + .bit_idx = 7,
> + },
> + .hw.init = CLK_HW_INIT_HW("eth_125m", &a9_eth_125m_div.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +/*
> + * Channel 1, 2, 3, 4, 5 and 6 are unconnected,
> + * ext_rmii connects external PAD. Do not automatically reparent.
> + */
> +static u32 a9_eth_rmii_parents_val_table[] = { 0, 7 };
> +static const struct clk_parent_data a9_eth_rmii_parents[] = {
> + { .fw_name = "fdiv2", },
> + { .fw_name = "ext_rmii", }
> +};
> +
> +static struct clk_regmap a9_eth_rmii_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = ETH_CLK_CTRL,
> + .mask = 0x7,
> + .shift = 9,
> + .table = a9_eth_rmii_parents_val_table,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_DATA("eth_rmii_sel",
> + a9_eth_rmii_parents,
> + &clk_regmap_mux_ops, CLK_SET_RATE_NO_REPARENT),
> +};
> +
> +static struct clk_regmap a9_eth_rmii_div = {
> + .data = &(struct clk_regmap_div_data) {
> + .offset = ETH_CLK_CTRL,
> + .shift = 0,
> + .width = 7,
> + },
> + .hw.init = CLK_HW_INIT_HW("eth_rmii_div", &a9_eth_rmii_sel.hw,
> + &clk_regmap_divider_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_eth_rmii = {
> + .data = &(struct clk_regmap_gate_data) {
> + .offset = ETH_CLK_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = CLK_HW_INIT_HW("eth_rmii", &a9_eth_rmii_div.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +/*
> + * Channel 3(ddr_dpll_pt_clk) is manged by the DDR module;
> + * channel 12(msr_clk) is manged by clock measures module.
> + * channel 16(audio_dac1_clk) is manged by audio module.
Some why can't you expose those then ? gen clk is used for debugging
AFAIK. The clock above are worth debugging I think
Please be consistent with the CaSing.
> + * Channel 10, 11, 13, 14 are not connected.
> + */
> +static u32 a9_gen_parents_val_table[] = { 0, 1, 2, 4, 5, 6, 7, 8, 9, 15, 17, 18,
> + 19, 20, 21, 22, 23, 24, 25, 26};
> +static struct clk_regmap a9_vid_pll;
> +
> +static const struct clk_parent_data a9_gen_parents[] = {
> + { .fw_name = "xtal" },
> + { .fw_name = "rtc" },
> + { .fw_name = "sysplldiv16" },
> + { .hw = &a9_vid_pll.hw },
> + { .fw_name = "gp0" },
> + { .fw_name = "hifi1" },
> + { .fw_name = "hifi0" },
> + { .fw_name = "gp1" },
> + { .fw_name = "gp2" },
> + { .fw_name = "dsudiv16" },
> + { .fw_name = "cpudiv16" },
> + { .fw_name = "a78div16" },
> + { .fw_name = "fdiv2" },
> + { .fw_name = "fdiv2p5" },
> + { .fw_name = "fdiv3" },
> + { .fw_name = "fdiv4" },
> + { .fw_name = "fdiv5" },
> + { .fw_name = "fdiv7" },
> + { .fw_name = "mclk0" },
> + { .fw_name = "mclk1" }
> +};
> +
> +static A9_COMP_SEL(gen, GEN_CLK_CTRL, 12, 0x1f, a9_gen_parents,
> + a9_gen_parents_val_table);
> +static A9_COMP_DIV(gen, GEN_CLK_CTRL, 0, 11);
> +static A9_COMP_GATE(gen, GEN_CLK_CTRL, 11, 0);
> +
> +static struct clk_regmap a9_24m_in = {
> + .data = &(struct clk_regmap_gate_data) {
> + .offset = CLK12_24_CTRL,
> + .bit_idx = 11,
> + },
> + .hw.init = CLK_HW_INIT_FW_NAME("24m_in", "xtal",
> + &clk_regmap_gate_ops, 0),
> +};
> +
> +static struct clk_regmap a9_12_24m = {
> + .data = &(struct clk_regmap_div_data) {
> + .offset = CLK12_24_CTRL,
> + .shift = 10,
> + .width = 1,
> + },
> + .hw.init = CLK_HW_INIT_HW("12_24m", &a9_24m_in.hw,
> + &clk_regmap_divider_ops, 0),
> +};
> +
> +static const struct clk_parent_data a9_mali_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "gp1", },
> + { .fw_name = "fdiv2", },
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv7", }
> +};
> +
> +static A9_COMP_SEL(mali_0, MALI_CLK_CTRL, 9, 0x7, a9_mali_parents, NULL);
> +static A9_COMP_DIV(mali_0, MALI_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(mali_0, MALI_CLK_CTRL, 8, CLK_SET_RATE_GATE);
> +
> +static A9_COMP_SEL(mali_1, MALI_CLK_CTRL, 25, 0x7, a9_mali_parents, NULL);
> +static A9_COMP_DIV(mali_1, MALI_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(mali_1, MALI_CLK_CTRL, 24, CLK_SET_RATE_GATE);
> +
> +static struct clk_regmap a9_mali = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = MALI_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 31,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("mali",
> + ((const struct clk_hw *[]) {
> + &a9_mali_0.hw,
> + &a9_mali_1.hw,
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static A9_COMP_SEL(mali_stack_0, MALI_STACK_CLK_CTRL, 9, 0x7, a9_mali_parents,
> + NULL);
> +static A9_COMP_DIV(mali_stack_0, MALI_STACK_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(mali_stack_0, MALI_STACK_CLK_CTRL, 8, CLK_SET_RATE_GATE);
> +
> +static A9_COMP_SEL(mali_stack_1, MALI_STACK_CLK_CTRL, 25, 0x7, a9_mali_parents,
> + NULL);
> +static A9_COMP_DIV(mali_stack_1, MALI_STACK_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(mali_stack_1, MALI_STACK_CLK_CTRL, 24, CLK_SET_RATE_GATE);
> +
> +static struct clk_regmap a9_mali_stack = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = MALI_STACK_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 31,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("mali_stack",
> + ((const struct clk_hw *[]) {
> + &a9_mali_stack_0.hw,
> + &a9_mali_stack_1.hw,
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static const struct clk_parent_data a9_dspa_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "gp2", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "hifi0", },
> + { .fw_name = "rtc", }
> +};
> +
> +static A9_COMP_SEL(dspa_0, DSPA_CLK_CTRL, 9, 0x7, a9_dspa_parents, NULL);
> +static A9_COMP_DIV(dspa_0, DSPA_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(dspa_0, DSPA_CLK_CTRL, 8, CLK_SET_RATE_GATE);
> +
> +static A9_COMP_SEL(dspa_1, DSPA_CLK_CTRL, 25, 0x7, a9_dspa_parents, NULL);
> +static A9_COMP_DIV(dspa_1, DSPA_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(dspa_1, DSPA_CLK_CTRL, 24, CLK_SET_RATE_GATE);
> +
> +static struct clk_regmap a9_dspa = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = DSPA_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 31,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("dspa",
> + ((const struct clk_hw *[]) {
> + &a9_dspa_0.hw,
> + &a9_dspa_1.hw,
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static const struct clk_parent_data a9_hevcf_parents[] = {
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv7", },
> + { .fw_name = "hifi0", },
> + { .fw_name = "gp1", },
> + { .fw_name = "xtal", }
> +};
> +
> +static A9_COMP_SEL(hevcf_0, HEVCF_CLK_CTRL, 9, 0x7, a9_hevcf_parents, NULL);
> +static A9_COMP_DIV(hevcf_0, HEVCF_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(hevcf_0, HEVCF_CLK_CTRL, 8, CLK_SET_RATE_GATE);
> +
> +static A9_COMP_SEL(hevcf_1, HEVCF_CLK_CTRL, 25, 0x7, a9_hevcf_parents, NULL);
> +static A9_COMP_DIV(hevcf_1, HEVCF_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(hevcf_1, HEVCF_CLK_CTRL, 24, CLK_SET_RATE_GATE);
> +
> +static struct clk_regmap a9_hevcf = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = HEVCF_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 31,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("hevcf",
> + ((const struct clk_hw *[]) {
> + &a9_hevcf_0.hw,
> + &a9_hevcf_1.hw,
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static const struct clk_parent_data a9_hcodec_parents[] = {
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv7", },
> + { .fw_name = "hifi0", },
> + { .fw_name = "gp0", },
> + { .fw_name = "xtal", }
> +};
> +
> +static A9_COMP_SEL(hcodec_0, HCODEC_CLK_CTRL, 9, 0x7, a9_hcodec_parents, NULL);
> +static A9_COMP_DIV(hcodec_0, HCODEC_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(hcodec_0, HCODEC_CLK_CTRL, 8, CLK_SET_RATE_GATE);
> +
> +static A9_COMP_SEL(hcodec_1, HCODEC_CLK_CTRL, 25, 0x7, a9_hcodec_parents, NULL);
> +static A9_COMP_DIV(hcodec_1, HCODEC_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(hcodec_1, HCODEC_CLK_CTRL, 24, CLK_SET_RATE_GATE);
> +
> +static struct clk_regmap a9_hcodec = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = HCODEC_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 31,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("hcodec",
> + ((const struct clk_hw *[]) {
> + &a9_hcodec_0.hw,
> + &a9_hcodec_1.hw,
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static const struct clk_parent_data a9_vpu_parents[] = {
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "vid1", },
> + { .fw_name = "fdiv2", },
> + { .hw = &a9_vid_pll.hw },
> + { .fw_name = "vid2", },
> + { .fw_name = "gp1", }
> +};
> +
> +static A9_COMP_SEL(vpu_0, VPU_CLK_CTRL, 9, 0x7, a9_vpu_parents, NULL);
> +static A9_COMP_DIV(vpu_0, VPU_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(vpu_0, VPU_CLK_CTRL, 8, CLK_SET_RATE_GATE);
> +
> +static A9_COMP_SEL(vpu_1, VPU_CLK_CTRL, 25, 0x7, a9_vpu_parents, NULL);
> +static A9_COMP_DIV(vpu_1, VPU_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(vpu_1, VPU_CLK_CTRL, 24, CLK_SET_RATE_GATE);
> +
> +static struct clk_regmap a9_vpu = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = VPU_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 31,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("vpu",
> + ((const struct clk_hw *[]) {
> + &a9_vpu_0.hw,
> + &a9_vpu_1.hw,
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static const struct clk_parent_data a9_vapb_parents[] = {
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv7", },
> + { .fw_name = "fdiv2", },
> + { .hw = &a9_vid_pll.hw },
> + { .fw_name = "hifi0", },
> + { .fw_name = "fdiv2p5", }
> +};
> +
> +static A9_COMP_SEL(vapb_0, VAPB_CLK_CTRL, 9, 0x7, a9_vapb_parents, NULL);
> +static A9_COMP_DIV(vapb_0, VAPB_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(vapb_0, VAPB_CLK_CTRL, 8, CLK_SET_RATE_GATE);
> +
> +static A9_COMP_SEL(vapb_1, VAPB_CLK_CTRL, 25, 0x7, a9_vapb_parents, NULL);
> +static A9_COMP_DIV(vapb_1, VAPB_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(vapb_1, VAPB_CLK_CTRL, 24, CLK_SET_RATE_GATE);
> +
> +static struct clk_regmap a9_vapb = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = VAPB_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 31,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("vapb",
> + ((const struct clk_hw *[]) {
> + &a9_vapb_0.hw,
> + &a9_vapb_1.hw,
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_ge2d = {
> + .data = &(struct clk_regmap_gate_data) {
> + .offset = VAPB_CLK_CTRL,
> + .bit_idx = 30,
> + },
> + .hw.init = CLK_HW_INIT_HW("ge2d", &a9_vapb.hw,
> + &clk_regmap_gate_ops, 0),
> +};
> +
> +static const struct clk_parent_data a9_vpu_clkb_tmp_parents[] = {
> + { .hw = &a9_vpu.hw },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "fdiv7", }
> +};
> +
> +static A9_COMP_SEL(vpu_clkb_tmp, VPU_CLKB_CTRL, 25, 0x7, a9_vpu_clkb_tmp_parents,
> + NULL);
> +static A9_COMP_DIV(vpu_clkb_tmp, VPU_CLKB_CTRL, 16, 4);
> +static A9_COMP_GATE(vpu_clkb_tmp, VPU_CLKB_CTRL, 24, 0);
> +
> +static struct clk_regmap a9_vpu_clkb_div = {
> + .data = &(struct clk_regmap_div_data) {
> + .offset = VPU_CLKB_CTRL,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = CLK_HW_INIT_HW("vpu_clkb_div", &a9_vpu_clkb_tmp.hw,
> + &clk_regmap_divider_ops, 0),
> +};
> +
> +static struct clk_regmap a9_vpu_clkb = {
> + .data = &(struct clk_regmap_gate_data) {
> + .offset = VPU_CLKB_CTRL,
> + .bit_idx = 8,
> + },
> + .hw.init = CLK_HW_INIT_HW("vpu_clkb", &a9_vpu_clkb_div.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static const struct clk_parent_data a9_hdmi_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv5", }
> +};
> +
> +static A9_COMP_SEL(hdmitx_sys, HDMI_CLK_CTRL, 9, 0x7, a9_hdmi_parents, NULL);
> +static A9_COMP_DIV(hdmitx_sys, HDMI_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(hdmitx_sys, HDMI_CLK_CTRL, 8, 0);
> +
> +static A9_COMP_SEL(hdmitx_prif, HTX_CLK_CTRL, 9, 0x7, a9_hdmi_parents, NULL);
> +static A9_COMP_DIV(hdmitx_prif, HTX_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(hdmitx_prif, HTX_CLK_CTRL, 8, 0);
> +
> +static A9_COMP_SEL(hdmitx_200m, HTX_CLK_CTRL, 25, 0x7, a9_hdmi_parents, NULL);
> +static A9_COMP_DIV(hdmitx_200m, HTX_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(hdmitx_200m, HTX_CLK_CTRL, 24, 0);
> +
> +static A9_COMP_SEL(hdmitx_aud, HTX_CLK_CTRL1, 9, 0x7, a9_hdmi_parents, NULL);
> +static A9_COMP_DIV(hdmitx_aud, HTX_CLK_CTRL1, 0, 7);
> +static A9_COMP_GATE(hdmitx_aud, HTX_CLK_CTRL1, 8, 0);
> +
> +static A9_COMP_SEL(hdmirx_5m, HRX_CLK_CTRL, 9, 0x7, a9_hdmi_parents,
> + NULL);
> +static A9_COMP_DIV(hdmirx_5m, HRX_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(hdmirx_5m, HRX_CLK_CTRL, 8, 0);
> +
> +static A9_COMP_SEL(hdmirx_2m, HRX_CLK_CTRL, 25, 0x7, a9_hdmi_parents,
> + NULL);
> +static A9_COMP_DIV(hdmirx_2m, HRX_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(hdmirx_2m, HRX_CLK_CTRL, 24, 0);
> +
> +static A9_COMP_SEL(hdmirx_cfg, HRX_CLK_CTRL1, 9, 0x7, a9_hdmi_parents,
> + NULL);
> +static A9_COMP_DIV(hdmirx_cfg, HRX_CLK_CTRL1, 0, 7);
> +static A9_COMP_GATE(hdmirx_cfg, HRX_CLK_CTRL1, 8, 0);
> +
> +static A9_COMP_SEL(hdmirx_hdcp2x, HRX_CLK_CTRL1, 25, 0x7, a9_hdmi_parents,
> + NULL);
> +static A9_COMP_DIV(hdmirx_hdcp2x, HRX_CLK_CTRL1, 16, 7);
> +static A9_COMP_GATE(hdmirx_hdcp2x, HRX_CLK_CTRL1, 24, 0);
> +
> +static A9_COMP_SEL(hdmirx_acr_ref, HRX_CLK_CTRL2, 25, 0x7, a9_hdmi_parents,
> + NULL);
> +static A9_COMP_DIV(hdmirx_acr_ref, HRX_CLK_CTRL2, 16, 7);
> +static A9_COMP_GATE(hdmirx_acr_ref, HRX_CLK_CTRL2, 24, 0);
> +
> +static A9_COMP_SEL(hdmirx_meter, HRX_CLK_CTRL3, 9, 0x7, a9_hdmi_parents,
> + NULL);
> +static A9_COMP_DIV(hdmirx_meter, HRX_CLK_CTRL3, 0, 7);
> +static A9_COMP_GATE(hdmirx_meter, HRX_CLK_CTRL3, 8, 0);
> +
> +static struct clk_regmap a9_enc, a9_enc1;
What is this again ?? and please come up with better names.
> +
> +static const struct clk_parent_data a9_vid_lock_parents[] = {
> + { .fw_name = "xtal", },
> + { .hw = &a9_enc.hw },
> + { .hw = &a9_enc1.hw }
> +};
> +
> +static A9_COMP_SEL(vid_lock, VID_LOCK_CLK_CTRL, 9, 0x7, a9_vid_lock_parents,
> + NULL);
> +static A9_COMP_DIV(vid_lock, VID_LOCK_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(vid_lock, VID_LOCK_CLK_CTRL, 8, 0);
> +
> +static const struct clk_parent_data a9_vdin_meas_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv5", }
> +};
> +
> +static A9_COMP_SEL(vdin_meas, VDIN_MEAS_CLK_CTRL, 9, 0x7, a9_vdin_meas_parents,
> + NULL);
> +static A9_COMP_DIV(vdin_meas, VDIN_MEAS_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(vdin_meas, VDIN_MEAS_CLK_CTRL, 8, 0);
> +
> +static struct clk_regmap a9_vid_pll_div = {
> + .data = &(struct meson_vid_pll_div_data){
> + .val = {
> + .reg_off = VID_PLL_CLK_DIV,
> + .shift = 0,
> + .width = 15,
> + },
> + .sel = {
> + .reg_off = VID_PLL_CLK_DIV,
> + .shift = 16,
> + .width = 2,
> + },
> + },
> + .hw.init = CLK_HW_INIT_FW_NAME("vid_pll_div", "hdmiout2",
> + &meson_vid_pll_div_ro_ops, 0),
> +};
> +
> +static struct clk_regmap a9_vid_pll_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = VID_PLL_CLK_DIV,
> + .mask = 0x1,
> + .shift = 18,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_DATA("vid_pll_sel",
> + ((const struct clk_parent_data []) {
> + { .hw = &a9_vid_pll_div.hw },
> + { .fw_name = "hdmiout2" }
> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vid_pll = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_PLL_CLK_DIV,
> + .bit_idx = 19,
> + },
> + .hw.init = CLK_HW_INIT_HW("vid_pll", &a9_vid_pll_sel.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vid_pll_vclk = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = HDMI_CLK_CTRL,
> + .mask = 0x1,
> + .shift = 15,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_DATA("vid_pll_vclk",
> + ((const struct clk_parent_data []) {
> + { .hw = &a9_vid_pll.hw },
> + { .fw_name = "hdmipix" }
> + }), &clk_regmap_mux_ops, 0),
> +};
> +
> +static const struct clk_parent_data a9_vclk_parents[] = {
> + { .hw = &a9_vid_pll_vclk.hw },
> + { .fw_name = "pix0", },
> + { .fw_name = "vid1", },
> + { .fw_name = "pix1", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "vid2", }
> +};
> +
> +static struct clk_regmap a9_vclk_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = VID_CLK_CTRL,
> + .mask = 0x7,
> + .shift = 16,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_DATA("vclk_sel", a9_vclk_parents,
> + &clk_regmap_mux_ops, 0),
> +};
> +
> +static struct clk_regmap a9_vclk_in = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_CLK_DIV,
> + .bit_idx = 16,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk_in", &a9_vclk_sel.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = VID_CLK_DIV,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk_div", &a9_vclk_in.hw,
> + &clk_regmap_divider_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_CLK_CTRL,
> + .bit_idx = 19,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk", &a9_vclk_div.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk_div1_en = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_CLK_CTRL,
> + .bit_idx = 0,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk_div1_en", &a9_vclk.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk_div2_en = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_CLK_CTRL,
> + .bit_idx = 1,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk_div2_en", &a9_vclk.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
Looks to me all this div_en / div repeating pattern would be easier to review
with tiny macro .
> +
> +static struct clk_fixed_factor a9_vclk_div2 = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = CLK_HW_INIT_HW("vclk_div2", &a9_vclk_div2_en.hw,
> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk_div4_en = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_CLK_CTRL,
> + .bit_idx = 2,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk_div4_en", &a9_vclk.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_fixed_factor a9_vclk_div4 = {
> + .mult = 1,
> + .div = 4,
> + .hw.init = CLK_HW_INIT_HW("vclk_div4", &a9_vclk_div4_en.hw,
> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk_div6_en = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_CLK_CTRL,
> + .bit_idx = 3,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk_div6_en", &a9_vclk.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_fixed_factor a9_vclk_div6 = {
> + .mult = 1,
> + .div = 6,
> + .hw.init = CLK_HW_INIT_HW("vclk_div6", &a9_vclk_div6_en.hw,
> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk_div12_en = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_CLK_CTRL,
> + .bit_idx = 4,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk_div12_en", &a9_vclk.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_fixed_factor a9_vclk_div12 = {
> + .mult = 1,
> + .div = 12,
> + .hw.init = CLK_HW_INIT_HW("vclk_div12", &a9_vclk_div12_en.hw,
> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk2_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = VIID_CLK_CTRL,
> + .mask = 0x7,
> + .shift = 16,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_DATA("vclk2_sel", a9_vclk_parents,
> + &clk_regmap_mux_ops, 0),
> +};
> +
> +static struct clk_regmap a9_vclk2_in = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VIID_CLK_DIV,
> + .bit_idx = 16,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk2_in", &a9_vclk2_sel.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk2_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = VIID_CLK_DIV,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk2_div", &a9_vclk2_in.hw,
> + &clk_regmap_divider_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk2 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VIID_CLK_CTRL,
> + .bit_idx = 19,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk2", &a9_vclk2_div.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk2_div1_en = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VIID_CLK_CTRL,
> + .bit_idx = 0,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk2_div1_en", &a9_vclk2.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk2_div2_en = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VIID_CLK_CTRL,
> + .bit_idx = 1,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk2_div2_en", &a9_vclk2.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_fixed_factor a9_vclk2_div2 = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = CLK_HW_INIT_HW("vclk2_div2", &a9_vclk2_div2_en.hw,
> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk2_div4_en = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VIID_CLK_CTRL,
> + .bit_idx = 2,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk2_div4_en", &a9_vclk2.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_fixed_factor a9_vclk2_div4 = {
> + .mult = 1,
> + .div = 4,
> + .hw.init = CLK_HW_INIT_HW("vclk2_div4", &a9_vclk2_div4_en.hw,
> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk2_div6_en = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VIID_CLK_CTRL,
> + .bit_idx = 3,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk2_div6_en", &a9_vclk2.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_fixed_factor a9_vclk2_div6 = {
> + .mult = 1,
> + .div = 6,
> + .hw.init = CLK_HW_INIT_HW("vclk2_div6", &a9_vclk2_div6_en.hw,
> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_vclk2_div12_en = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VIID_CLK_CTRL,
> + .bit_idx = 4,
> + },
> + .hw.init = CLK_HW_INIT_HW("vclk2_div12_en", &a9_vclk2.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_fixed_factor a9_vclk2_div12 = {
> + .mult = 1,
> + .div = 12,
> + .hw.init = CLK_HW_INIT_HW("vclk2_div12", &a9_vclk2_div12_en.hw,
> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +/* Channel 5, 6 and 7 are unconnected */
> +static u32 a9_vid_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
> +static const struct clk_hw *a9_vid_parents[] = {
> + &a9_vclk_div1_en.hw,
> + &a9_vclk_div2.hw,
> + &a9_vclk_div4.hw,
> + &a9_vclk_div6.hw,
> + &a9_vclk_div12.hw,
> + &a9_vclk2_div1_en.hw,
> + &a9_vclk2_div2.hw,
> + &a9_vclk2_div4.hw,
> + &a9_vclk2_div6.hw,
> + &a9_vclk2_div12.hw
> +};
> +
> +static struct clk_regmap a9_vdac_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = VIID_CLK_DIV,
> + .mask = 0xf,
> + .shift = 28,
> + .table = a9_vid_parents_val_table,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("vdac_sel", a9_vid_parents
> + , &clk_regmap_mux_ops, 0),
> +};
> +
> +static struct clk_regmap a9_vdac = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_CLK_CTRL2,
> + .bit_idx = 4,
> + },
> + .hw.init = CLK_HW_INIT_HW("vdac", &a9_vdac_sel.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_enc_sel = {
Should this be enc0 then ? for consistency ?
Same applies to similar instance (it is the same discussion we already
had on the T7 I believe)
> + .data = &(struct clk_regmap_mux_data){
> + .offset = VIID_CLK_DIV,
> + .mask = 0xf,
> + .shift = 12,
> + .table = a9_vid_parents_val_table,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("enc_sel", a9_vid_parents
> + , &clk_regmap_mux_ops, 0),
> +};
> +
> +static struct clk_regmap a9_enc = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_CLK_CTRL2,
> + .bit_idx = 10,
> + },
> + .hw.init = CLK_HW_INIT_HW("enc", &a9_enc_sel.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_enc1_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = VIID_CLK_DIV,
> + .mask = 0xf,
> + .shift = 8,
> + .table = a9_vid_parents_val_table,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("enc1_sel", a9_vid_parents
> + , &clk_regmap_mux_ops, 0),
> +};
> +
> +static struct clk_regmap a9_enc1 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_CLK_CTRL2,
> + .bit_idx = 11,
> + },
> + .hw.init = CLK_HW_INIT_HW("enc1", &a9_enc1_sel.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_hdmitx_pixel_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = HDMI_CLK_CTRL,
> + .mask = 0xf,
> + .shift = 16,
> + .table = a9_vid_parents_val_table,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("hdmitx_pixel_sel", a9_vid_parents
> + , &clk_regmap_mux_ops, 0),
> +};
> +
> +static struct clk_regmap a9_hdmitx_pixel = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_CLK_CTRL2,
> + .bit_idx = 5,
> + },
> + .hw.init = CLK_HW_INIT_HW("hdmitx_pixel", &a9_hdmitx_pixel_sel.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_hdmitx_fe_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = HDMI_CLK_CTRL,
> + .mask = 0xf,
> + .shift = 20,
> + .table = a9_vid_parents_val_table,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("hdmitx_fe_sel", a9_vid_parents
> + , &clk_regmap_mux_ops, 0),
> +};
> +
> +static struct clk_regmap a9_hdmitx_fe = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_CLK_CTRL2,
> + .bit_idx = 9,
> + },
> + .hw.init = CLK_HW_INIT_HW("hdmitx_fe", &a9_hdmitx_fe_sel.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_hdmitx1_pixel_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = HDMI_CLK_CTRL,
> + .mask = 0xf,
> + .shift = 24,
> + .table = a9_vid_parents_val_table,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("hdmitx1_pixel_sel", a9_vid_parents
> + , &clk_regmap_mux_ops, 0),
> +};
> +
> +static struct clk_regmap a9_hdmitx1_pixel = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_CLK_CTRL2,
> + .bit_idx = 12,
> + },
> + .hw.init = CLK_HW_INIT_HW("hdmitx1_pixel", &a9_hdmitx1_pixel_sel.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static struct clk_regmap a9_hdmitx1_fe_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = HDMI_CLK_CTRL,
> + .mask = 0xf,
> + .shift = 28,
> + .table = a9_vid_parents_val_table,
> + },
> + .hw.init = CLK_HW_INIT_PARENTS_HW("hdmitx1_fe_sel", a9_vid_parents
> + , &clk_regmap_mux_ops, 0),
> +};
> +
> +static struct clk_regmap a9_hdmitx1_fe = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = VID_CLK_CTRL2,
> + .bit_idx = 13,
> + },
> + .hw.init = CLK_HW_INIT_HW("hdmitx1_fe", &a9_hdmitx1_fe_sel.hw,
> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
> +};
> +
> +static const struct clk_parent_data a9_csi_phy_parents[] = {
> + { .fw_name = "fdiv2p5", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv5", },
> + { .fw_name = "gp0", },
> + { .fw_name = "hifi0", },
> + { .fw_name = "fdiv2", },
> + { .fw_name = "xtal", }
> +};
> +
> +static A9_COMP_SEL(csi_phy, MIPI_CSI_PHY_CLK_CTRL, 9, 0x7,
> + a9_csi_phy_parents, NULL);
> +static A9_COMP_DIV(csi_phy, MIPI_CSI_PHY_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(csi_phy, MIPI_CSI_PHY_CLK_CTRL, 8, 0);
> +
> +static const struct clk_parent_data a9_dsi_meas_parents[] = {
> + { .fw_name = "xtal", },
> + { .fw_name = "fdiv4", },
> + { .fw_name = "fdiv3", },
> + { .fw_name = "fdiv5", },
> + { .hw = &a9_vid_pll.hw },
> + { .fw_name = "gp0", },
> + { .fw_name = "vid1", },
> + { .fw_name = "vid2", }
> +};
> +
> +static A9_COMP_SEL(dsi_meas, DSI_MEAS_CLK_CTRL, 9, 0x7,
> + a9_dsi_meas_parents, NULL);
> +static A9_COMP_DIV(dsi_meas, DSI_MEAS_CLK_CTRL, 0, 7);
> +static A9_COMP_GATE(dsi_meas, DSI_MEAS_CLK_CTRL, 8, 0);
> +
> +static A9_COMP_SEL(dsi_b_meas, DSI_MEAS_CLK_CTRL, 25, 0x7,
> + a9_dsi_meas_parents, NULL);
> +static A9_COMP_DIV(dsi_b_meas, DSI_MEAS_CLK_CTRL, 16, 7);
> +static A9_COMP_GATE(dsi_b_meas, DSI_MEAS_CLK_CTRL, 24, 0);
> +
> +static struct clk_hw *a9_peripherals_hw_clks[] = {
> + [CLKID_SYS_AM_AXI] = &a9_sys_am_axi.hw,
> + [CLKID_SYS_DOS] = &a9_sys_dos.hw,
> + [CLKID_SYS_MIPI_DSI] = &a9_sys_mipi_dsi.hw,
> + [CLKID_SYS_ETH_PHY] = &a9_sys_eth_phy.hw,
> + [CLKID_SYS_AMFC] = &a9_sys_amfc.hw,
> + [CLKID_SYS_MALI] = &a9_sys_mali.hw,
> + [CLKID_SYS_NNA] = &a9_sys_nna.hw,
> + [CLKID_SYS_ETH_AXI] = &a9_sys_eth_axi.hw,
> + [CLKID_SYS_DP_APB] = &a9_sys_dp_apb.hw,
> + [CLKID_SYS_EDPTX_APB] = &a9_sys_edptx_apb.hw,
> + [CLKID_SYS_U3HSG] = &a9_sys_u3hsg.hw,
> + [CLKID_SYS_AUCPU] = &a9_sys_aucpu.hw,
> + [CLKID_SYS_GLB] = &a9_sys_glb.hw,
> + [CLKID_SYS_COMBO_DPHY_APB] = &a9_sys_combo_dphy_apb.hw,
> + [CLKID_SYS_HDMIRX_APB] = &a9_sys_hdmirx_apb.hw,
> + [CLKID_SYS_HDMIRX_PCLK] = &a9_sys_hdmirx_pclk.hw,
> + [CLKID_SYS_MIPI_DSI_PHY] = &a9_sys_mipi_dsi_phy.hw,
> + [CLKID_SYS_CAN0] = &a9_sys_can0.hw,
> + [CLKID_SYS_CAN1] = &a9_sys_can1.hw,
> + [CLKID_SYS_SD_EMMC_A] = &a9_sys_sd_emmc_a.hw,
> + [CLKID_SYS_SD_EMMC_B] = &a9_sys_sd_emmc_b.hw,
> + [CLKID_SYS_SD_EMMC_C] = &a9_sys_sd_emmc_c.hw,
> + [CLKID_SYS_SC] = &a9_sys_sc.hw,
> + [CLKID_SYS_ACODEC] = &a9_sys_acodec.hw,
> + [CLKID_SYS_MIPI_ISP] = &a9_sys_mipi_isp.hw,
> + [CLKID_SYS_MSR] = &a9_sys_msr.hw,
> + [CLKID_SYS_AUDIO] = &a9_sys_audio.hw,
> + [CLKID_SYS_MIPI_DSI_B] = &a9_sys_mipi_dsi_b.hw,
> + [CLKID_SYS_MIPI_DSI1_PHY] = &a9_sys_mipi_dsi1_phy.hw,
> + [CLKID_SYS_ETH] = &a9_sys_eth.hw,
> + [CLKID_SYS_ETH_1G_MAC] = &a9_sys_eth_1g_mac.hw,
> + [CLKID_SYS_UART_A] = &a9_sys_uart_a.hw,
> + [CLKID_SYS_UART_F] = &a9_sys_uart_f.hw,
> + [CLKID_SYS_TS_A55] = &a9_sys_ts_a55.hw,
> + [CLKID_SYS_ETH_1G_AXI] = &a9_sys_eth_1g_axi.hw,
> + [CLKID_SYS_TS_DOS] = &a9_sys_ts_dos.hw,
> + [CLKID_SYS_U3DRD_B] = &a9_sys_u3drd_b.hw,
> + [CLKID_SYS_TS_CORE] = &a9_sys_ts_core.hw,
> + [CLKID_SYS_TS_PLL] = &a9_sys_ts_pll.hw,
> + [CLKID_SYS_CSI_DIG_CLKIN] = &a9_sys_csi_dig_clkin.hw,
> + [CLKID_SYS_CVE] = &a9_sys_cve.hw,
> + [CLKID_SYS_GE2D] = &a9_sys_ge2d.hw,
> + [CLKID_SYS_SPISG] = &a9_sys_spisg.hw,
> + [CLKID_SYS_U3DRD_1] = &a9_sys_u3drd_1.hw,
> + [CLKID_SYS_U2H] = &a9_sys_u2h.hw,
> + [CLKID_SYS_PCIE_MAC_A] = &a9_sys_pcie_mac_a.hw,
> + [CLKID_SYS_U3DRD_A] = &a9_sys_u3drd_a.hw,
> + [CLKID_SYS_U2DRD] = &a9_sys_u2drd.hw,
> + [CLKID_SYS_PCIE_PHY] = &a9_sys_pcie_phy.hw,
> + [CLKID_SYS_PCIE_MAC_B] = &a9_sys_pcie_mac_b.hw,
> + [CLKID_SYS_PERIPH] = &a9_sys_periph.hw,
> + [CLKID_SYS_PIO] = &a9_sys_pio.hw,
> + [CLKID_SYS_I3C] = &a9_sys_i3c.hw,
> + [CLKID_SYS_I2C_M_E] = &a9_sys_i2c_m_e.hw,
> + [CLKID_SYS_I2C_M_F] = &a9_sys_i2c_m_f.hw,
> + [CLKID_SYS_HDMITX_APB] = &a9_sys_hdmitx_apb.hw,
> + [CLKID_SYS_I2C_M_I] = &a9_sys_i2c_m_i.hw,
> + [CLKID_SYS_I2C_M_G] = &a9_sys_i2c_m_g.hw,
> + [CLKID_SYS_I2C_M_H] = &a9_sys_i2c_m_h.hw,
> + [CLKID_SYS_HDMI20_AES] = &a9_sys_hdmi20_aes.hw,
> + [CLKID_SYS_CSI2_HOST] = &a9_sys_csi2_host.hw,
> + [CLKID_SYS_CSI2_ADAPT] = &a9_sys_csi2_adapt.hw,
> + [CLKID_SYS_DSPA] = &a9_sys_dspa.hw,
> + [CLKID_SYS_PP_DMA] = &a9_sys_pp_dma.hw,
> + [CLKID_SYS_PP_WRAPPER] = &a9_sys_pp_wrapper.hw,
> + [CLKID_SYS_VPU_INTR] = &a9_sys_vpu_intr.hw,
> + [CLKID_SYS_CSI2_PHY] = &a9_sys_csi2_phy.hw,
> + [CLKID_SYS_SARADC] = &a9_sys_saradc.hw,
> + [CLKID_SYS_PWM_J] = &a9_sys_pwm_j.hw,
> + [CLKID_SYS_PWM_I] = &a9_sys_pwm_i.hw,
> + [CLKID_SYS_PWM_H] = &a9_sys_pwm_h.hw,
> + [CLKID_SYS_PWM_N] = &a9_sys_pwm_n.hw,
> + [CLKID_SYS_PWM_M] = &a9_sys_pwm_m.hw,
> + [CLKID_SYS_PWM_L] = &a9_sys_pwm_l.hw,
> + [CLKID_SYS_PWM_K] = &a9_sys_pwm_k.hw,
> + [CLKID_SD_EMMC_A_SEL] = &a9_sd_emmc_a_sel.hw,
> + [CLKID_SD_EMMC_A_DIV] = &a9_sd_emmc_a_div.hw,
> + [CLKID_SD_EMMC_A] = &a9_sd_emmc_a.hw,
> + [CLKID_SD_EMMC_B_SEL] = &a9_sd_emmc_b_sel.hw,
> + [CLKID_SD_EMMC_B_DIV] = &a9_sd_emmc_b_div.hw,
> + [CLKID_SD_EMMC_B] = &a9_sd_emmc_b.hw,
> + [CLKID_SD_EMMC_C_SEL] = &a9_sd_emmc_c_sel.hw,
> + [CLKID_SD_EMMC_C_DIV] = &a9_sd_emmc_c_div.hw,
> + [CLKID_SD_EMMC_C] = &a9_sd_emmc_c.hw,
> + [CLKID_PWM_H_SEL] = &a9_pwm_h_sel.hw,
> + [CLKID_PWM_H_DIV] = &a9_pwm_h_div.hw,
> + [CLKID_PWM_H] = &a9_pwm_h.hw,
> + [CLKID_PWM_I_SEL] = &a9_pwm_i_sel.hw,
> + [CLKID_PWM_I_DIV] = &a9_pwm_i_div.hw,
> + [CLKID_PWM_I] = &a9_pwm_i.hw,
> + [CLKID_PWM_J_SEL] = &a9_pwm_j_sel.hw,
> + [CLKID_PWM_J_DIV] = &a9_pwm_j_div.hw,
> + [CLKID_PWM_J] = &a9_pwm_j.hw,
> + [CLKID_PWM_K_SEL] = &a9_pwm_k_sel.hw,
> + [CLKID_PWM_K_DIV] = &a9_pwm_k_div.hw,
> + [CLKID_PWM_K] = &a9_pwm_k.hw,
> + [CLKID_PWM_L_SEL] = &a9_pwm_l_sel.hw,
> + [CLKID_PWM_L_DIV] = &a9_pwm_l_div.hw,
> + [CLKID_PWM_L] = &a9_pwm_l.hw,
> + [CLKID_PWM_M_SEL] = &a9_pwm_m_sel.hw,
> + [CLKID_PWM_M_DIV] = &a9_pwm_m_div.hw,
> + [CLKID_PWM_M] = &a9_pwm_m.hw,
> + [CLKID_PWM_N_SEL] = &a9_pwm_n_sel.hw,
> + [CLKID_PWM_N_DIV] = &a9_pwm_n_div.hw,
> + [CLKID_PWM_N] = &a9_pwm_n.hw,
> + [CLKID_SPISG_SEL] = &a9_spisg_sel.hw,
> + [CLKID_SPISG_DIV] = &a9_spisg_div.hw,
> + [CLKID_SPISG] = &a9_spisg.hw,
> + [CLKID_SPISG1_SEL] = &a9_spisg1_sel.hw,
> + [CLKID_SPISG1_DIV] = &a9_spisg1_div.hw,
> + [CLKID_SPISG1] = &a9_spisg1.hw,
> + [CLKID_SPISG2_SEL] = &a9_spisg2_sel.hw,
> + [CLKID_SPISG2_DIV] = &a9_spisg2_div.hw,
> + [CLKID_SPISG2] = &a9_spisg2.hw,
> + [CLKID_SARADC_SEL] = &a9_saradc_sel.hw,
> + [CLKID_SARADC_DIV] = &a9_saradc_div.hw,
> + [CLKID_SARADC] = &a9_saradc.hw,
> + [CLKID_AMFC_SEL] = &a9_amfc_sel.hw,
> + [CLKID_AMFC_DIV] = &a9_amfc_div.hw,
> + [CLKID_AMFC] = &a9_amfc.hw,
> + [CLKID_NNA_SEL] = &a9_nna_sel.hw,
> + [CLKID_NNA_DIV] = &a9_nna_div.hw,
> + [CLKID_NNA] = &a9_nna.hw,
> + [CLKID_USB_250M_SEL] = &a9_usb_250m_sel.hw,
> + [CLKID_USB_250M_DIV] = &a9_usb_250m_div.hw,
> + [CLKID_USB_250M] = &a9_usb_250m.hw,
> + [CLKID_USB_48M_PRE_SEL] = &a9_usb_48m_pre_sel.hw,
> + [CLKID_USB_48M_PRE_DIV] = &a9_usb_48m_pre_div.hw,
> + [CLKID_USB_48M_PRE] = &a9_usb_48m_pre.hw,
> + [CLKID_PCIE_TL_SEL] = &a9_pcie_tl_sel.hw,
> + [CLKID_PCIE_TL_DIV] = &a9_pcie_tl_div.hw,
> + [CLKID_PCIE_TL] = &a9_pcie_tl.hw,
> + [CLKID_PCIE1_TL_SEL] = &a9_pcie1_tl_sel.hw,
> + [CLKID_PCIE1_TL_DIV] = &a9_pcie1_tl_div.hw,
> + [CLKID_PCIE1_TL] = &a9_pcie1_tl.hw,
> + [CLKID_CMPR_SEL] = &a9_cmpr_sel.hw,
> + [CLKID_CMPR_DIV] = &a9_cmpr_div.hw,
> + [CLKID_CMPR] = &a9_cmpr.hw,
> + [CLKID_DEWARPA_SEL] = &a9_dewarpa_sel.hw,
> + [CLKID_DEWARPA_DIV] = &a9_dewarpa_div.hw,
> + [CLKID_DEWARPA] = &a9_dewarpa.hw,
> + [CLKID_SC_PRE_SEL] = &a9_sc_pre_sel.hw,
> + [CLKID_SC_PRE_DIV] = &a9_sc_pre_div.hw,
> + [CLKID_SC_PRE] = &a9_sc_pre.hw,
> + [CLKID_SC] = &a9_sc.hw,
> + [CLKID_DPTX_APB2_SEL] = &a9_dptx_apb2_sel.hw,
> + [CLKID_DPTX_APB2_DIV] = &a9_dptx_apb2_div.hw,
> + [CLKID_DPTX_APB2] = &a9_dptx_apb2.hw,
> + [CLKID_DPTX_AUD_SEL] = &a9_dptx_aud_sel.hw,
> + [CLKID_DPTX_AUD_DIV] = &a9_dptx_aud_div.hw,
> + [CLKID_DPTX_AUD] = &a9_dptx_aud.hw,
> + [CLKID_ISP_SEL] = &a9_isp_sel.hw,
> + [CLKID_ISP_DIV] = &a9_isp_div.hw,
> + [CLKID_ISP] = &a9_isp.hw,
> + [CLKID_CVE_SEL] = &a9_cve_sel.hw,
> + [CLKID_CVE_DIV] = &a9_cve_div.hw,
> + [CLKID_CVE] = &a9_cve.hw,
> + [CLKID_VGE_SEL] = &a9_vge_sel.hw,
> + [CLKID_VGE_DIV] = &a9_vge_div.hw,
> + [CLKID_VGE] = &a9_vge.hw,
> + [CLKID_PP_SEL] = &a9_pp_sel.hw,
> + [CLKID_PP_DIV] = &a9_pp_div.hw,
> + [CLKID_PP] = &a9_pp.hw,
> + [CLKID_GLB_SEL] = &a9_glb_sel.hw,
> + [CLKID_GLB_DIV] = &a9_glb_div.hw,
> + [CLKID_GLB] = &a9_glb.hw,
> + [CLKID_USB_48M_DUALDIV_IN] = &a9_usb_48m_dualdiv_in.hw,
> + [CLKID_USB_48M_DUALDIV_DIV] = &a9_usb_48m_dualdiv_div.hw,
> + [CLKID_USB_48M_DUALDIV_SEL] = &a9_usb_48m_dualdiv_sel.hw,
> + [CLKID_USB_48M_DUALDIV] = &a9_usb_48m_dualdiv.hw,
> + [CLKID_USB_48M] = &a9_usb_48m.hw,
> + [CLKID_CAN_PE_SEL] = &a9_can_pe_sel.hw,
> + [CLKID_CAN_PE_DIV] = &a9_can_pe_div.hw,
> + [CLKID_CAN_PE] = &a9_can_pe.hw,
> + [CLKID_CAN1_PE_SEL] = &a9_can1_pe_sel.hw,
> + [CLKID_CAN1_PE_DIV] = &a9_can1_pe_div.hw,
> + [CLKID_CAN1_PE] = &a9_can1_pe.hw,
> + [CLKID_CAN_FILTER_SEL] = &a9_can_filter_sel.hw,
> + [CLKID_CAN_FILTER_DIV] = &a9_can_filter_div.hw,
> + [CLKID_CAN_FILTER] = &a9_can_filter.hw,
> + [CLKID_CAN1_FILTER_SEL] = &a9_can1_filter_sel.hw,
> + [CLKID_CAN1_FILTER_DIV] = &a9_can1_filter_div.hw,
> + [CLKID_CAN1_FILTER] = &a9_can1_filter.hw,
> + [CLKID_I3C_SEL] = &a9_i3c_sel.hw,
> + [CLKID_I3C_DIV] = &a9_i3c_div.hw,
> + [CLKID_I3C] = &a9_i3c.hw,
> + [CLKID_TS_DIV] = &a9_ts_div.hw,
> + [CLKID_TS] = &a9_ts.hw,
> + [CLKID_ETH_125M_DIV] = &a9_eth_125m_div.hw,
> + [CLKID_ETH_125M] = &a9_eth_125m.hw,
> + [CLKID_ETH_RMII_SEL] = &a9_eth_rmii_sel.hw,
> + [CLKID_ETH_RMII_DIV] = &a9_eth_rmii_div.hw,
> + [CLKID_ETH_RMII] = &a9_eth_rmii.hw,
> + [CLKID_GEN_SEL] = &a9_gen_sel.hw,
> + [CLKID_GEN_DIV] = &a9_gen_div.hw,
> + [CLKID_GEN] = &a9_gen.hw,
> + [CLKID_CLK24M_IN] = &a9_24m_in.hw,
> + [CLKID_CLK12_24M] = &a9_12_24m.hw,
> + [CLKID_MALI_0_SEL] = &a9_mali_0_sel.hw,
> + [CLKID_MALI_0_DIV] = &a9_mali_0_div.hw,
> + [CLKID_MALI_0] = &a9_mali_0.hw,
> + [CLKID_MALI_1_SEL] = &a9_mali_1_sel.hw,
> + [CLKID_MALI_1_DIV] = &a9_mali_1_div.hw,
> + [CLKID_MALI_1] = &a9_mali_1.hw,
> + [CLKID_MALI] = &a9_mali.hw,
> + [CLKID_MALI_STACK_0_SEL] = &a9_mali_stack_0_sel.hw,
> + [CLKID_MALI_STACK_0_DIV] = &a9_mali_stack_0_div.hw,
> + [CLKID_MALI_STACK_0] = &a9_mali_stack_0.hw,
> + [CLKID_MALI_STACK_1_SEL] = &a9_mali_stack_1_sel.hw,
> + [CLKID_MALI_STACK_1_DIV] = &a9_mali_stack_1_div.hw,
> + [CLKID_MALI_STACK_1] = &a9_mali_stack_1.hw,
> + [CLKID_MALI_STACK] = &a9_mali_stack.hw,
> + [CLKID_DSPA_0_SEL] = &a9_dspa_0_sel.hw,
> + [CLKID_DSPA_0_DIV] = &a9_dspa_0_div.hw,
> + [CLKID_DSPA_0] = &a9_dspa_0.hw,
> + [CLKID_DSPA_1_SEL] = &a9_dspa_1_sel.hw,
> + [CLKID_DSPA_1_DIV] = &a9_dspa_1_div.hw,
> + [CLKID_DSPA_1] = &a9_dspa_1.hw,
> + [CLKID_DSPA] = &a9_dspa.hw,
> + [CLKID_HEVCF_0_SEL] = &a9_hevcf_0_sel.hw,
> + [CLKID_HEVCF_0_DIV] = &a9_hevcf_0_div.hw,
> + [CLKID_HEVCF_0] = &a9_hevcf_0.hw,
> + [CLKID_HEVCF_1_SEL] = &a9_hevcf_1_sel.hw,
> + [CLKID_HEVCF_1_DIV] = &a9_hevcf_1_div.hw,
> + [CLKID_HEVCF_1] = &a9_hevcf_1.hw,
> + [CLKID_HEVCF] = &a9_hevcf.hw,
> + [CLKID_HCODEC_0_SEL] = &a9_hcodec_0_sel.hw,
> + [CLKID_HCODEC_0_DIV] = &a9_hcodec_0_div.hw,
> + [CLKID_HCODEC_0] = &a9_hcodec_0.hw,
> + [CLKID_HCODEC_1_SEL] = &a9_hcodec_1_sel.hw,
> + [CLKID_HCODEC_1_DIV] = &a9_hcodec_1_div.hw,
> + [CLKID_HCODEC_1] = &a9_hcodec_1.hw,
> + [CLKID_HCODEC] = &a9_hcodec.hw,
> + [CLKID_VPU_0_SEL] = &a9_vpu_0_sel.hw,
> + [CLKID_VPU_0_DIV] = &a9_vpu_0_div.hw,
> + [CLKID_VPU_0] = &a9_vpu_0.hw,
> + [CLKID_VPU_1_SEL] = &a9_vpu_1_sel.hw,
> + [CLKID_VPU_1_DIV] = &a9_vpu_1_div.hw,
> + [CLKID_VPU_1] = &a9_vpu_1.hw,
> + [CLKID_VPU] = &a9_vpu.hw,
> + [CLKID_VAPB_0_SEL] = &a9_vapb_0_sel.hw,
> + [CLKID_VAPB_0_DIV] = &a9_vapb_0_div.hw,
> + [CLKID_VAPB_0] = &a9_vapb_0.hw,
> + [CLKID_VAPB_1_SEL] = &a9_vapb_1_sel.hw,
> + [CLKID_VAPB_1_DIV] = &a9_vapb_1_div.hw,
> + [CLKID_VAPB_1] = &a9_vapb_1.hw,
> + [CLKID_VAPB] = &a9_vapb.hw,
> + [CLKID_GE2D] = &a9_ge2d.hw,
> + [CLKID_VPU_CLKB_TMP_SEL] = &a9_vpu_clkb_tmp_sel.hw,
> + [CLKID_VPU_CLKB_TMP_DIV] = &a9_vpu_clkb_tmp_div.hw,
> + [CLKID_VPU_CLKB_TMP] = &a9_vpu_clkb_tmp.hw,
> + [CLKID_VPU_CLKB_DIV] = &a9_vpu_clkb_div.hw,
> + [CLKID_VPU_CLKB] = &a9_vpu_clkb.hw,
> + [CLKID_HDMITX_SYS_SEL] = &a9_hdmitx_sys_sel.hw,
> + [CLKID_HDMITX_SYS_DIV] = &a9_hdmitx_sys_div.hw,
> + [CLKID_HDMITX_SYS] = &a9_hdmitx_sys.hw,
> + [CLKID_HDMITX_PRIF_SEL] = &a9_hdmitx_prif_sel.hw,
> + [CLKID_HDMITX_PRIF_DIV] = &a9_hdmitx_prif_div.hw,
> + [CLKID_HDMITX_PRIF] = &a9_hdmitx_prif.hw,
> + [CLKID_HDMITX_200M_SEL] = &a9_hdmitx_200m_sel.hw,
> + [CLKID_HDMITX_200M_DIV] = &a9_hdmitx_200m_div.hw,
> + [CLKID_HDMITX_200M] = &a9_hdmitx_200m.hw,
> + [CLKID_HDMITX_AUD_SEL] = &a9_hdmitx_aud_sel.hw,
> + [CLKID_HDMITX_AUD_DIV] = &a9_hdmitx_aud_div.hw,
> + [CLKID_HDMITX_AUD] = &a9_hdmitx_aud.hw,
> + [CLKID_HDMIRX_5M_SEL] = &a9_hdmirx_5m_sel.hw,
> + [CLKID_HDMIRX_5M_DIV] = &a9_hdmirx_5m_div.hw,
> + [CLKID_HDMIRX_5M] = &a9_hdmirx_5m.hw,
> + [CLKID_HDMIRX_2M_SEL] = &a9_hdmirx_2m_sel.hw,
> + [CLKID_HDMIRX_2M_DIV] = &a9_hdmirx_2m_div.hw,
> + [CLKID_HDMIRX_2M] = &a9_hdmirx_2m.hw,
> + [CLKID_HDMIRX_CFG_SEL] = &a9_hdmirx_cfg_sel.hw,
> + [CLKID_HDMIRX_CFG_DIV] = &a9_hdmirx_cfg_div.hw,
> + [CLKID_HDMIRX_CFG] = &a9_hdmirx_cfg.hw,
> + [CLKID_HDMIRX_HDCP2X_SEL] = &a9_hdmirx_hdcp2x_sel.hw,
> + [CLKID_HDMIRX_HDCP2X_DIV] = &a9_hdmirx_hdcp2x_div.hw,
> + [CLKID_HDMIRX_HDCP2X] = &a9_hdmirx_hdcp2x.hw,
> + [CLKID_HDMIRX_ACR_REF_SEL] = &a9_hdmirx_acr_ref_sel.hw,
> + [CLKID_HDMIRX_ACR_REF_DIV] = &a9_hdmirx_acr_ref_div.hw,
> + [CLKID_HDMIRX_ACR_REF] = &a9_hdmirx_acr_ref.hw,
> + [CLKID_HDMIRX_METER_SEL] = &a9_hdmirx_meter_sel.hw,
> + [CLKID_HDMIRX_METER_DIV] = &a9_hdmirx_meter_div.hw,
> + [CLKID_HDMIRX_METER] = &a9_hdmirx_meter.hw,
> + [CLKID_VID_LOCK_SEL] = &a9_vid_lock_sel.hw,
> + [CLKID_VID_LOCK_DIV] = &a9_vid_lock_div.hw,
> + [CLKID_VID_LOCK] = &a9_vid_lock.hw,
> + [CLKID_VDIN_MEAS_SEL] = &a9_vdin_meas_sel.hw,
> + [CLKID_VDIN_MEAS_DIV] = &a9_vdin_meas_div.hw,
> + [CLKID_VDIN_MEAS] = &a9_vdin_meas.hw,
> + [CLKID_VID_PLL_DIV] = &a9_vid_pll_div.hw,
> + [CLKID_VID_PLL_SEL] = &a9_vid_pll_sel.hw,
> + [CLKID_VID_PLL] = &a9_vid_pll.hw,
> + [CLKID_VID_PLL_VCLK] = &a9_vid_pll_vclk.hw,
> + [CLKID_VCLK_SEL] = &a9_vclk_sel.hw,
> + [CLKID_VCLK_IN] = &a9_vclk_in.hw,
> + [CLKID_VCLK_DIV] = &a9_vclk_div.hw,
> + [CLKID_VCLK] = &a9_vclk.hw,
> + [CLKID_VCLK_DIV1_EN] = &a9_vclk_div1_en.hw,
> + [CLKID_VCLK_DIV2_EN] = &a9_vclk_div2_en.hw,
> + [CLKID_VCLK_DIV2] = &a9_vclk_div2.hw,
> + [CLKID_VCLK_DIV4_EN] = &a9_vclk_div4_en.hw,
> + [CLKID_VCLK_DIV4] = &a9_vclk_div4.hw,
> + [CLKID_VCLK_DIV6_EN] = &a9_vclk_div6_en.hw,
> + [CLKID_VCLK_DIV6] = &a9_vclk_div6.hw,
> + [CLKID_VCLK_DIV12_EN] = &a9_vclk_div12_en.hw,
> + [CLKID_VCLK_DIV12] = &a9_vclk_div12.hw,
> + [CLKID_VCLK2_SEL] = &a9_vclk2_sel.hw,
> + [CLKID_VCLK2_IN] = &a9_vclk2_in.hw,
> + [CLKID_VCLK2_DIV] = &a9_vclk2_div.hw,
> + [CLKID_VCLK2] = &a9_vclk2.hw,
> + [CLKID_VCLK2_DIV1_EN] = &a9_vclk2_div1_en.hw,
> + [CLKID_VCLK2_DIV2_EN] = &a9_vclk2_div2_en.hw,
> + [CLKID_VCLK2_DIV2] = &a9_vclk2_div2.hw,
> + [CLKID_VCLK2_DIV4_EN] = &a9_vclk2_div4_en.hw,
> + [CLKID_VCLK2_DIV4] = &a9_vclk2_div4.hw,
> + [CLKID_VCLK2_DIV6_EN] = &a9_vclk2_div6_en.hw,
> + [CLKID_VCLK2_DIV6] = &a9_vclk2_div6.hw,
> + [CLKID_VCLK2_DIV12_EN] = &a9_vclk2_div12_en.hw,
> + [CLKID_VCLK2_DIV12] = &a9_vclk2_div12.hw,
> + [CLKID_VDAC_SEL] = &a9_vdac_sel.hw,
> + [CLKID_VDAC] = &a9_vdac.hw,
> + [CLKID_ENC_SEL] = &a9_enc_sel.hw,
> + [CLKID_ENC] = &a9_enc.hw,
> + [CLKID_ENC1_SEL] = &a9_enc1_sel.hw,
> + [CLKID_ENC1] = &a9_enc1.hw,
> + [CLKID_HDMITX_PIXEL_SEL] = &a9_hdmitx_pixel_sel.hw,
> + [CLKID_HDMITX_PIXEL] = &a9_hdmitx_pixel.hw,
> + [CLKID_HDMITX_FE_SEL] = &a9_hdmitx_fe_sel.hw,
> + [CLKID_HDMITX_FE] = &a9_hdmitx_fe.hw,
> + [CLKID_HDMITX1_PIXEL_SEL] = &a9_hdmitx1_pixel_sel.hw,
> + [CLKID_HDMITX1_PIXEL] = &a9_hdmitx1_pixel.hw,
> + [CLKID_HDMITX1_FE_SEL] = &a9_hdmitx1_fe_sel.hw,
> + [CLKID_HDMITX1_FE] = &a9_hdmitx1_fe.hw,
> + [CLKID_CSI_PHY_SEL] = &a9_csi_phy_sel.hw,
> + [CLKID_CSI_PHY_DIV] = &a9_csi_phy_div.hw,
> + [CLKID_CSI_PHY] = &a9_csi_phy.hw,
> + [CLKID_DSI_MEAS_SEL] = &a9_dsi_meas_sel.hw,
> + [CLKID_DSI_MEAS_DIV] = &a9_dsi_meas_div.hw,
> + [CLKID_DSI_MEAS] = &a9_dsi_meas.hw,
> + [CLKID_DSI_B_MEAS_SEL] = &a9_dsi_b_meas_sel.hw,
> + [CLKID_DSI_B_MEAS_DIV] = &a9_dsi_b_meas_div.hw,
> + [CLKID_DSI_B_MEAS] = &a9_dsi_b_meas.hw,
> +};
> +
> +static const struct meson_clkc_data a9_peripherals_clkc_data = {
> + .hw_clks = {
> + .hws = a9_peripherals_hw_clks,
> + .num = ARRAY_SIZE(a9_peripherals_hw_clks),
> + },
> +};
> +
> +static const struct of_device_id a9_peripherals_clkc_match_table[] = {
> + {
> + .compatible = "amlogic,a9-peripherals-clkc",
> + .data = &a9_peripherals_clkc_data,
> + },
> + { /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, a9_peripherals_clkc_match_table);
> +
> +static struct platform_driver a9_peripherals_clkc_driver = {
> + .probe = meson_clkc_mmio_probe,
> + .driver = {
> + .name = "a9-peripherals-clkc",
> + .of_match_table = a9_peripherals_clkc_match_table,
> + },
> +};
> +module_platform_driver(a9_peripherals_clkc_driver);
> +
> +MODULE_DESCRIPTION("Amlogic A9 Peripherals Clock Controller driver");
> +MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
> +MODULE_LICENSE("GPL");
> +MODULE_IMPORT_NS("CLK_MESON");
--
Jerome
^ permalink raw reply
* Re: [PATCH 0/4] Fix up QUSB2 PHY description for MSM8996/SM61[12]5
From: Konrad Dybcio @ 2026-06-10 12:49 UTC (permalink / raw)
To: Konrad Dybcio, Vinod Koul, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Wesley Cheng, Iskren Chernev,
Greg Kroah-Hartman, Bjorn Andersson
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <20260610-topic-8996_61x5_qusb2phy-v1-0-d7135980e78f@oss.qualcomm.com>
On 6/10/26 2:04 PM, Konrad Dybcio wrote:
> The MSM8996 QUSB2PHY was not being guaranteed a power source.
> The SM6125's QUSB2PHY was believed to be idential as the 96 one. It
> wasn't. This series tackles that, freeing us of some dt checker
> errors about vdd-supply not found on MSM8996 boards.
>
> Compile-tested only, but docs confirm my findings..
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> Konrad Dybcio (4):
> dt-bindings: phy: qcom,qusb2: Straighten out SM6125 and MSM8996
> phy: qcom-qusb2: Fix SM6115 init sequence
> arm64: dts: qcom: msm8996: Add VDD_MX to QUSB2 PHYs
> arm64: dts: qcom: sm6125: Fix QUSB2 compatible
>
> .../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 31 ++++++++++++++++++++--
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 10 +++++++
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 4 +--
> 4 files changed, 43 insertions(+), 5 deletions(-)
> ---
Note that msm8996pro may need even more looking into, but that's a
story for another day
Konrad
^ permalink raw reply
* Re: [PATCH net-next v2 3/5] net: mdio: realtek-rtl9300: Make otto_emdio_read_cmd() generic
From: Maxime Chevallier @ 2026-06-10 12:49 UTC (permalink / raw)
To: Markus Stockhausen, andrew, hkallweit1, linux, davem, edumazet,
kuba, pabeni, netdev, chris.packham, daniel, robh, krzk+dt,
conor+dt, devicetree
In-Reply-To: <20260609052856.3142922-4-markus.stockhausen@gmx.de>
Hello Markus,
On 6/9/26 07:28, Markus Stockhausen wrote:
> The otto_emdio_read_cmd() helper still uses RTL9300 specific properties.
> This cannot be made generic as the I/O register has different layouts for
> the different SoCs. E.g.
>
> - RTL930x: data in bits 31-16, data out bits 15-0
> - RTL931x: data in bits 15-0, data out bits 31-16
>
> Add a mask parameter to the function signature and fill it properly
> in the callers. As the masks will always have bits set from constant
> defines, there is no need for a consistency check.
>
> Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
> ---
[...]
> static int otto_emdio_read_cmd(struct mii_bus *bus, u32 cmd,
> - struct otto_emdio_cmd_regs *cmd_data, u32 *value)
> + struct otto_emdio_cmd_regs *cmd_data, u32 mask, u32 *value)
> {
> struct otto_emdio_priv *priv = otto_emdio_bus_to_priv(bus);
> int ret;
> @@ -205,7 +205,7 @@ static int otto_emdio_read_cmd(struct mii_bus *bus, u32 cmd,
> if (ret)
> return ret;
>
> - *value = FIELD_GET(RTL9300_PHY_CTRL_DATA, *value);
> + *value = (*value & mask) >> __ffs(mask);
If I'm not mistaken, you can use field_get() when the mask isn't constexpr :
https://elixir.bootlin.com/linux/v7.1-rc7/source/include/linux/bitfield.h#L299
With this change, you may add :
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Maxime
^ permalink raw reply
* Re: [PATCH 0/3] tty: serial: Add Cortina-Access UART driver and platform support
From: Arnd Bergmann @ 2026-06-10 12:50 UTC (permalink / raw)
To: Jason Li, jason.li, Greg Kroah-Hartman, Jiri Slaby
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Catalin Marinas,
Will Deacon, linux-serial, linux-arm-kernel, devicetree,
linux-kernel
In-Reply-To: <20260610112821.3030099-2-jason.li@cortina-access.com>
On Wed, Jun 10, 2026, at 13:28, Jason Li wrote:
> This series adds Linux kernel support for the UART controller integrated
> in Cortina-Access SoCs, with CA8289 (Venus) as the first supported device.
Hi Jason,
Thanks a lot for your submission!
I'm glad to see Cortina Access is getting back to upstreaming
this support, I see that you first tries this in 2021 but
didn't get very far at the time. The last submission was v4,
so it would make sense to cound this one as v5 and continue
with v6 next time.
You have already received a number of comments, so I'll skip
looking at the details for the moment and let you work through
them.
Regarding how to split up the patch series between uart and
soc, I think sending them together during the review phase
as you do here makes sense, but as they are loosely coupled,
I think we will likely merge them separately. For simplicity,
I would then just put the MAINTAINERS entry and the bindings
for the vendor and board into the series for the soc tree.
It would also help me if you could add some more context about
the SoC into the patch description for the patch that adds
the arm64 platform, in particular:
- is this the only one you are planning to upstream at this
point, or do you already have plans for other SoCs in this
family?
- do you expect to see full support for actual end-user
products using these chips?
- is there any shared lineage with the cortina-systems
(storlink/storm, now marvell) gemini 32-bit chips that we
already support, or with any of the Realtek SoCs that
are also being upstreamed now?
Arnd
^ permalink raw reply
* [PATCH] dt-bindings: nvmem: consumer: Make 'nvmem' an array of one-item entries
From: Konrad Dybcio @ 2026-06-10 12:52 UTC (permalink / raw)
To: Srinivas Kandagatla, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: devicetree, linux-kernel, Konrad Dybcio
From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
'nvmem' unlike 'nvmem-cells', consumes references to just a single
phandle with no arguments (i.e. with 0 cells).
Constrain the schema to enforce that, so that the number of such
single-item entries can then be regulated by IP block-specific YAMLs.
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
qcom/qcs6490-rb3gen2.dtb: pmic@2 (qcom,pm8350c): pwm:nvmem: [[397, 398]] is too short
from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml
qcom/qcs6490-rb3gen2.dtb: pwm (qcom,pm8350c-pwm): nvmem: [[397, 398]] is too short
from schema $id: http://devicetree.org/schemas/leds/leds-qcom-lpg.yaml
---
Documentation/devicetree/bindings/nvmem/nvmem-consumer.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/nvmem/nvmem-consumer.yaml b/Documentation/devicetree/bindings/nvmem/nvmem-consumer.yaml
index a26633bf52db..45836308c724 100644
--- a/Documentation/devicetree/bindings/nvmem/nvmem-consumer.yaml
+++ b/Documentation/devicetree/bindings/nvmem/nvmem-consumer.yaml
@@ -16,6 +16,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
List of phandle to the nvmem providers.
+ items:
+ maxItems: 1
nvmem-cells:
$ref: /schemas/types.yaml#/definitions/phandle-array
---
base-commit: 49e02880ec0a8c378e811bc9d85da188d7c6204c
change-id: 20260610-topic-nvmem_schema_warning_fix-1e8d8d39e51c
Best regards,
--
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
^ permalink raw reply related
* Re: [PATCH 4/4] arm64: dts: qcom: sm6125: Fix QUSB2 compatible
From: Dmitry Baryshkov @ 2026-06-10 12:53 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Wesley Cheng, Iskren Chernev, Greg Kroah-Hartman,
Bjorn Andersson, linux-arm-msm, linux-phy, devicetree,
linux-kernel, Konrad Dybcio
In-Reply-To: <20260610-topic-8996_61x5_qusb2phy-v1-4-d7135980e78f@oss.qualcomm.com>
On Wed, Jun 10, 2026 at 02:04:17PM +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> There are a couple issues with the current description:
>
> 1) The msm8996 compatible is wholly reused, without a SM6125-specific
> primary compatible
> 2) MSM8996 has a different power setup (VDD powered through a RPMPD
> power-domain vs a regulator)
> 3) MSM8996 uses a different init sequence
>
> As part of fixing all of them, use a SM6125-specific compatible with a
> SM6115 fallback.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH] dt-bindings: pinctrl: qcom,pmic-gpio: Add Qualcomm PMK7750
From: sashiko-bot @ 2026-06-10 12:53 UTC (permalink / raw)
To: Krzysztof Kozlowski; +Cc: robh, conor+dt, devicetree
In-Reply-To: <20260610124048.253162-2-krzysztof.kozlowski@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The new `qcom,pmk7750-gpio` compatible string is missing from the C driver's OF match table, and the binding schema prevents using a functional fallback, making the hardware impossible to probe.
- [Medium] The top-level MFD binding for `qcom,pmk7750` is missing, preventing full device tree node validation for the new PMIC.
- [Low] The newly added compatible string 'qcom,pmk7750-gpio' violates alphabetical sorting in the enum and documentation lists.
--
commit a637ed7ee2349c673140cc49df5a55b91d3fa732
Author: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
dt-bindings: pinctrl: qcom,pmic-gpio: Add Qualcomm PMK7750
This commit documents the Qualcomm PMK7750 PMIC GPIO controller, noting
it is almost the same as the PMK8550. It updates the qcom,pmic-gpio
schema to include the new compatible string.
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
> --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
> @@ -71,6 +71,7 @@ properties:
> - qcom,pmih0108-gpio
> - qcom,pmiv0104-gpio
> - qcom,pmk8350-gpio
> + - qcom,pmk7750-gpio
[Severity: Low]
Should these compatible strings remain alphabetically sorted? It looks like
qcom,pmk7750-gpio is inserted after qcom,pmk8350-gpio here.
[Severity: High]
The commit message mentions this hardware is compatible with PMK8550.
However, the schema restricts the secondary fallback compatible string
to exactly qcom,spmi-gpio or qcom,ssbi-gpio, preventing the use of
qcom,pmk8550-gpio as a fallback:
- enum:
- qcom,spmi-gpio
- qcom,ssbi-gpio
Because the driver in drivers/pinctrl/qcom/pinctrl-spmi-gpio.c requires an
exact match on the primary string and does not generically match
qcom,spmi-gpio:
static const struct of_device_id pmic_gpio_of_match[] = {
...
{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pmk8550-gpio", .data = (void *) 6 },
...
will this device be prevented from probing? The qcom,pmk7750-gpio string
was not added to the driver's match table, and the schema restricts using
functional fallbacks.
[ ... ]
> @@ -501,6 +503,7 @@ $defs:
> - gpio1-gpio10 for pmi8994
> - gpio1-gpio18 for pmih0108
> - gpio1-gpio4 for pmk8350
> + - gpio1-gpio6 for pmk7750
[Severity: Low]
Is there an expectation to keep this documentation list alphabetically sorted
as well?
[Severity: Medium]
Since a new PMIC GPIO block is being added, is there also a need to document
the top-level MFD in Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml?
Without it, device tree nodes declaring the top-level qcom,pmk7750 PMIC might
trigger validation errors.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260610124048.253162-2-krzysztof.kozlowski@oss.qualcomm.com?part=1
^ permalink raw reply
* Re: [PATCH 2/4] phy: qcom-qusb2: Fix SM6115 init sequence
From: Abel Vesa @ 2026-06-10 12:57 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Wesley Cheng, Iskren Chernev, Greg Kroah-Hartman,
Bjorn Andersson, linux-arm-msm, linux-phy, devicetree,
linux-kernel, Konrad Dybcio
In-Reply-To: <20260610-topic-8996_61x5_qusb2phy-v1-2-d7135980e78f@oss.qualcomm.com>
On 26-06-10 14:04:15, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> I don't know where the existing one came from, but it's apparently
> wrong, according to both docs and a downstream DT [1]. Fix it up.
>
> The updated values also happen to match SM6125, which will allow us
> to fix that platform too.
>
> [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/bengal-usb.dtsi#145
> Fixes: 7756f1d6369e ("phy: qcom-qusb2: Add configuration for SM4250 and SM6115")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v2 0/2] Add psci_sys_reset2 reboot modes for Qualcomm boards
From: Loic Poulain @ 2026-06-10 12:57 UTC (permalink / raw)
To: Anurag Pateriya
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shivendra Pratap, Lorenzo Pieralisi, linux-arm-msm,
devicetree, linux-kernel, Xin Liu
In-Reply-To: <20260529-psci_sys_reset-dt-changes-for-pakala-v2-0-1964ebf1924c@oss.qualcomm.com>
Hi Anurag,
On Fri, May 29, 2026 at 4:29 PM Anurag Pateriya
<anurag.pateriya@oss.qualcomm.com> wrote:
>
> Adding PSCI SYSTEM_RESET2 reboot-modes for sm8750 and
> kaanapali based boards.
I would like to highlight that when Linux/EFI is enabled, which is a
common config, efi_reboot is used as the primary reboot path (see
machine_restart). As a result, the PSCI reboot hook is not invoked in
this scenario, assuming Qualcomm firmware provides EFI runtime
services. As a follow-up, it would therefore be beneficial to also
improve the EFI path to support such custom mode(s)...
Regards,
Loic
>
> These DT patches depend on PSCI SYSTEM_RESET2 support introduced in:
> https://lore.kernel.org/all/20260514-arm-psci-system_reset2-vendor-reboots-v22-0-28a5bde07483@oss.qualcomm.com/
>
> To: Bjorn Andersson <andersson@kernel.org>
> To: Konrad Dybcio <konradybcio@kernel.org>
> To: Rob Herring <robh@kernel.org>
> To: Krzysztof Kozlowski <krzk+dt@kernel.org>
> To: Conor Dooley <conor+dt@kernel.org>
> Cc: Shivendra Pratap <shivendra.pratap@oss.qualcomm.com>
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: linux-arm-msm@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
>
> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
> ---
> Changes in v2:
> - Fixed subject lines.
> - Link to v1: https://lore.kernel.org/r/20260529-psci_sys_reset-dt-changes-for-pakala-v1-0-7c32161cf50b@oss.qualcomm.com
>
> ---
> Anurag Pateriya (1):
> arm64: dts: qcom: sm8750: add reboot-mode support
>
> Xin Liu (1):
> arm64: dts: qcom: kaanapali: add reboot-mode support
>
> arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 7 +++++++
> arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 7 +++++++
> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 7 +++++++
> arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 7 +++++++
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 +-
> 6 files changed, 30 insertions(+), 2 deletions(-)
> ---
> base-commit: 6ee02bbf328be8a8586487e3af73b65a906cce58
> change-id: 20260529-psci_sys_reset-dt-changes-for-pakala-a09fc0e2a8a8
>
> Best regards,
> --
> Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
>
>
^ permalink raw reply
* Re: [PATCH v5 RESEND 5/5] riscv64: dts: sophgo: add initial Milk-V Duo S board support
From: Joshua Milas @ 2026-06-10 12:57 UTC (permalink / raw)
To: Shuwei Wu
Cc: tglx, robh, krzk+dt, conor+dt, pjw, samuel.holland, unicorn_wang,
inochiama, daniel.lezcano, palmer, aou, alex, liujingqi,
alexander.sverdlin, rabenda.cn, dlan, chao.wei, anup,
linux-kernel, devicetree, linux-riscv, sophgo, hanguidong02,
michael.opdenacker, linux-riscv
In-Reply-To: <aiawOUHBcKtMVEZk@sleek>
Hi Shuwei,
I was able to get the wifi chip working. It requires the proper DT and an
updated aic8800-milkv-duo-s driver [1] that has been updated to Linux 7.1.
The next patch will cover the DT part.
[1] https://gitlab.com/DeepHorizons/aic8800-milkv-duo-s
Have a great day,
- Joshua Milas
^ permalink raw reply
* Re: [PATCH v4 3/3] arm64: dts: qcom: Add Vicharak Axon Mini
From: Konrad Dybcio @ 2026-06-10 12:58 UTC (permalink / raw)
To: Ajit Singh, Bjorn Andersson, Bartosz Golaszewski
Cc: Dmitry Baryshkov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260607113658.25117-4-blfizzyy@gmail.com>
On 6/7/26 1:36 PM, Ajit Singh wrote:
> Add DTS for the Vicharak Axon Mini board based on the Qualcomm
> QCS6490 SoC.
>
> This adds debug UART, eMMC, UFS, SDIO WLAN, USB 2.0 host, PCIe
> support along with regulators.
>
> The UFS ICE block is kept disabled because enabling it currently causes
> an SError during qcom_ice_create() on this board. UFS works without ICE.
>
> Signed-off-by: Ajit Singh <blfizzyy@gmail.com>
> ---
[...]
> + vreg_l12c_1p8: ldo12 {
> + regulator-name = "vreg_l12c_1p8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +
> + /*
> + * VREG_L12C_1P8 supplies the Ampak WLAN/BT module
> + * VDDIO and the external 32.768 kHz oscillator.
> + */
Sorry for the long review timelines on the previous patch, many of us
were out for conferences..
Is the oscillator used for that WLAN module? Would you ideally like to
be able to turn it on/off?
Perhaps you could get that with a simple pwrseq driver (+Bartosz)
Konrad
^ permalink raw reply
* Re: [PATCH v4 3/3] arm64: dts: qcom: Add Vicharak Axon Mini
From: Konrad Dybcio @ 2026-06-10 13:01 UTC (permalink / raw)
To: Ajit Singh, Bjorn Andersson
Cc: Dmitry Baryshkov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260607113658.25117-4-blfizzyy@gmail.com>
On 6/7/26 1:36 PM, Ajit Singh wrote:
> Add DTS for the Vicharak Axon Mini board based on the Qualcomm
> QCS6490 SoC.
>
> This adds debug UART, eMMC, UFS, SDIO WLAN, USB 2.0 host, PCIe
> support along with regulators.
>
> The UFS ICE block is kept disabled because enabling it currently causes
> an SError during qcom_ice_create() on this board. UFS works without ICE.
>
> Signed-off-by: Ajit Singh <blfizzyy@gmail.com>
> ---
[...]
> + vreg_l16b_1p1: ldo16 {
> + regulator-name = "vreg_l16b_1p1";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vreg_l17b_1p7: ldo17 {
> + regulator-name = "vreg_l17b_1p7";
> + regulator-min-microvolt = <1700000>;
> + regulator-max-microvolt = <1900000>;
> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> + };
Any reason for these two to be always-on?
[...]
> +&usb_2 {
> + /* Routed to an onboard USB hub for two USB-A host ports. */
> + dr_mode = "host";
Do they need to be powered/power sequenced in any way?
see drivers/usb/misc/onboard_usb_dev.c and e.g. qcs6490-rb3gen2.dts
-> usb5e3,610
Konrad
^ permalink raw reply
* Re: [PATCH 0/4] Fix up QUSB2 PHY description for MSM8996/SM61[12]5
From: Dmitry Baryshkov @ 2026-06-10 13:03 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Konrad Dybcio, Vinod Koul, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Wesley Cheng, Iskren Chernev,
Greg Kroah-Hartman, Bjorn Andersson, linux-arm-msm, linux-phy,
devicetree, linux-kernel
In-Reply-To: <b05e860e-ace5-4399-bbd9-493f7bbfe74d@oss.qualcomm.com>
On Wed, Jun 10, 2026 at 02:49:31PM +0200, Konrad Dybcio wrote:
> On 6/10/26 2:04 PM, Konrad Dybcio wrote:
> > The MSM8996 QUSB2PHY was not being guaranteed a power source.
> > The SM6125's QUSB2PHY was believed to be idential as the 96 one. It
> > wasn't. This series tackles that, freeing us of some dt checker
> > errors about vdd-supply not found on MSM8996 boards.
> >
> > Compile-tested only, but docs confirm my findings..
> >
> > Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > ---
> > Konrad Dybcio (4):
> > dt-bindings: phy: qcom,qusb2: Straighten out SM6125 and MSM8996
> > phy: qcom-qusb2: Fix SM6115 init sequence
> > arm64: dts: qcom: msm8996: Add VDD_MX to QUSB2 PHYs
> > arm64: dts: qcom: sm6125: Fix QUSB2 compatible
> >
> > .../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 31 ++++++++++++++++++++--
> > arch/arm64/boot/dts/qcom/msm8996.dtsi | 10 +++++++
> > arch/arm64/boot/dts/qcom/sm6125.dtsi | 3 ++-
> > drivers/phy/qualcomm/phy-qcom-qusb2.c | 4 +--
> > 4 files changed, 43 insertions(+), 5 deletions(-)
> > ---
>
> Note that msm8996pro may need even more looking into, but that's a
> story for another day
JFYI, MSM8996 Pro is being used in the DRM / Mesa CI. If there is an
important difference, it would be nice to get it sorted out too.
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v3 0/9] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase
From: Andrew Jeffery @ 2026-06-10 13:04 UTC (permalink / raw)
To: u8813345, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
colin.huang2, Carl Lee, Rex Fu, Andy Chung, Peter Shen
In-Reply-To: <20260602-anacapa-devlop-phase-devicetree-v3-0-7c93c5df8d9b@gmail.com>
On Tue, 2026-06-02 at 21:24 +0800, Colin Huang via B4 Relay wrote:
> This series refactors the Anacapa BMC devicetree layout to better support
> development-phase hardware revisions (EVT1/EVT2/DVT) while keeping a platform
> entrypoint.
>
> Signed-off-by: Colin Huang <u8813345@gmail.com>
> ---
> Changes in v3:
> - Restructure the EVT2 devicetree to inherit from the EVT1 devicetree, making it incremental rather than standalone.
> - Add the DVT devicetree, inheriting from the EVT2 devicetree.
> - Enable MCTP and FRU support for the NIC.
> - Align PDB fan GPIO numbering.
> - Add an EEPROM device node for the NFC adaptor board.
> - Add an additional EEPROM device node for the SCM.
> - Add shunt resistor values for HSC monitors
> - Link to v2: https://lore.kernel.org/r/20260409-anacapa-devlop-phase-devicetree-v2-0-68f328671653@gmail.com
>
So just to check, the changes in patches 5-8 inclusive are applicable
to all of EVT1, EVT2 and DVT (given the way you've structured the
includes)?
> Changes in v2:
> - Fix dtbs_check fail.
> Validated by following command:
> make dt_binding_check DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml
> make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa.dtb
> make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa-evt1.dtb
> make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa-evt2.dtb
> - Link to v1: https://lore.kernel.org/r/20260407-anacapa-devlop-phase-devicetree-v1-0-97b96367cac3@gmail.com
>
> ---
> Andy Chung (1):
> ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC
>
> Carl Lee (1):
> ARM: dts: aspeed: anacapa: Add eeprom device node for NFC adaptor board
>
> Colin Huang (5):
> dt-bindings: arm: aspeed: add Anacapa EVT1 EVT2 DVT board
> ARM: dts: aspeed: anacapa: add EVT1 devicetree and point wrapper to it
> ARM: dts: aspeed: anacapa: add EVT2 devicetree inheriting EVT1
> ARM: dts: aspeed: anacapa: add DVT devicetree inheriting EVT2
> ARM: dts: aspeed: anacapa: add additional EEPROM node for SCM
If you need to respin this series for some reason, can you please
capitalise the first word of the short description (the bit after the
last ':') for the commits above and the one below?
>
> Peter Shen (1):
> ARM: dts: aspeed: anacapa: evt2: add shunt resistor values for HSC monitors
>
> Rex Fu (1):
> ARM: dts: aspeed: anacapa: Align PDB fan GPIO numbering
>
> .../devicetree/bindings/arm/aspeed/aspeed.yaml | 3 +
> .../dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts | 178 +++
> .../aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 1179 ++++++++++++++++++++
> .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 228 ++++
> .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 1077 +-----------------
> 5 files changed, 1589 insertions(+), 1076 deletions(-)
> ---
> base-commit: 7ca1caf017d34396397b19fb4de9ecef256f4acc
> change-id: 20260407-anacapa-devlop-phase-devicetree-4101d3f312c0
>
> Best regards,
Andrew
^ permalink raw reply
* Re: [PATCH 0/4] Fix up QUSB2 PHY description for MSM8996/SM61[12]5
From: Konrad Dybcio @ 2026-06-10 13:13 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Konrad Dybcio, Vinod Koul, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Wesley Cheng, Iskren Chernev,
Greg Kroah-Hartman, Bjorn Andersson, linux-arm-msm, linux-phy,
devicetree, linux-kernel
In-Reply-To: <cnyhnyoce6v4d5roijrceuzd3ujvvw7ozklulaxkibptvjancm@cqbqu2aa7bz6>
On 6/10/26 3:03 PM, Dmitry Baryshkov wrote:
> On Wed, Jun 10, 2026 at 02:49:31PM +0200, Konrad Dybcio wrote:
>> On 6/10/26 2:04 PM, Konrad Dybcio wrote:
>>> The MSM8996 QUSB2PHY was not being guaranteed a power source.
>>> The SM6125's QUSB2PHY was believed to be idential as the 96 one. It
>>> wasn't. This series tackles that, freeing us of some dt checker
>>> errors about vdd-supply not found on MSM8996 boards.
>>>
>>> Compile-tested only, but docs confirm my findings..
>>>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>> ---
>>> Konrad Dybcio (4):
>>> dt-bindings: phy: qcom,qusb2: Straighten out SM6125 and MSM8996
>>> phy: qcom-qusb2: Fix SM6115 init sequence
>>> arm64: dts: qcom: msm8996: Add VDD_MX to QUSB2 PHYs
>>> arm64: dts: qcom: sm6125: Fix QUSB2 compatible
>>>
>>> .../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 31 ++++++++++++++++++++--
>>> arch/arm64/boot/dts/qcom/msm8996.dtsi | 10 +++++++
>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 3 ++-
>>> drivers/phy/qualcomm/phy-qcom-qusb2.c | 4 +--
>>> 4 files changed, 43 insertions(+), 5 deletions(-)
>>> ---
>>
>> Note that msm8996pro may need even more looking into, but that's a
>> story for another day
>
> JFYI, MSM8996 Pro is being used in the DRM / Mesa CI. If there is an
> important difference, it would be nice to get it sorted out too.
reg 96 pro
0x80 0xF8 0xD0 [!] QUSB2PHY_PORT_TUNE1
0x84 0xB3 0xB3
0x88 0x83 0x83
0x8C 0xC0 0xC0
0x90 none 0x02 [!] QUSB2PHY_PORT_TUNE5
0x08 0x30 0x30
0x0C 0x79 0x79
0x10 0x21 0x21
0x9C 0x14 0x14
0x1C 0x9F 0x9F
0x18 0x00 0x00
apparently this is indeed SoC-specific (via docs) but also apparently
may not be very important (although should be fixed regardless as
some designs may rely on this)
Konrad
^ permalink raw reply
* Re: [PATCH 0/4] Fix up QUSB2 PHY description for MSM8996/SM61[12]5
From: Dmitry Baryshkov @ 2026-06-10 13:20 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Konrad Dybcio, Vinod Koul, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Wesley Cheng, Iskren Chernev,
Greg Kroah-Hartman, Bjorn Andersson, linux-arm-msm, linux-phy,
devicetree, linux-kernel
In-Reply-To: <852caded-eacf-4ac1-8fe5-83dd9285ef11@oss.qualcomm.com>
On Wed, Jun 10, 2026 at 03:13:01PM +0200, Konrad Dybcio wrote:
> On 6/10/26 3:03 PM, Dmitry Baryshkov wrote:
> > On Wed, Jun 10, 2026 at 02:49:31PM +0200, Konrad Dybcio wrote:
> >> On 6/10/26 2:04 PM, Konrad Dybcio wrote:
> >>> The MSM8996 QUSB2PHY was not being guaranteed a power source.
> >>> The SM6125's QUSB2PHY was believed to be idential as the 96 one. It
> >>> wasn't. This series tackles that, freeing us of some dt checker
> >>> errors about vdd-supply not found on MSM8996 boards.
> >>>
> >>> Compile-tested only, but docs confirm my findings..
> >>>
> >>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >>> ---
> >>> Konrad Dybcio (4):
> >>> dt-bindings: phy: qcom,qusb2: Straighten out SM6125 and MSM8996
> >>> phy: qcom-qusb2: Fix SM6115 init sequence
> >>> arm64: dts: qcom: msm8996: Add VDD_MX to QUSB2 PHYs
> >>> arm64: dts: qcom: sm6125: Fix QUSB2 compatible
> >>>
> >>> .../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 31 ++++++++++++++++++++--
> >>> arch/arm64/boot/dts/qcom/msm8996.dtsi | 10 +++++++
> >>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 3 ++-
> >>> drivers/phy/qualcomm/phy-qcom-qusb2.c | 4 +--
> >>> 4 files changed, 43 insertions(+), 5 deletions(-)
> >>> ---
> >>
> >> Note that msm8996pro may need even more looking into, but that's a
> >> story for another day
> >
> > JFYI, MSM8996 Pro is being used in the DRM / Mesa CI. If there is an
> > important difference, it would be nice to get it sorted out too.
>
> reg 96 pro
> 0x80 0xF8 0xD0 [!] QUSB2PHY_PORT_TUNE1
> 0x84 0xB3 0xB3
> 0x88 0x83 0x83
> 0x8C 0xC0 0xC0
> 0x90 none 0x02 [!] QUSB2PHY_PORT_TUNE5
> 0x08 0x30 0x30
> 0x0C 0x79 0x79
> 0x10 0x21 0x21
> 0x9C 0x14 0x14
> 0x1C 0x9F 0x9F
> 0x18 0x00 0x00
>
> apparently this is indeed SoC-specific (via docs) but also apparently
> may not be very important (although should be fixed regardless as
> some designs may rely on this)
Would you send a patch, please?
>
> Konrad
>
> --
> linux-phy mailing list
> linux-phy@lists.infradead.org
> https://lists.infradead.org/mailman/listinfo/linux-phy
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH 2/4] phy: qcom-qusb2: Fix SM6115 init sequence
From: Dmitry Baryshkov @ 2026-06-10 13:20 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Wesley Cheng, Iskren Chernev, Greg Kroah-Hartman,
Bjorn Andersson, linux-arm-msm, linux-phy, devicetree,
linux-kernel, Konrad Dybcio
In-Reply-To: <20260610-topic-8996_61x5_qusb2phy-v1-2-d7135980e78f@oss.qualcomm.com>
On Wed, Jun 10, 2026 at 02:04:15PM +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> I don't know where the existing one came from, but it's apparently
> wrong, according to both docs and a downstream DT [1]. Fix it up.
>
> The updated values also happen to match SM6125, which will allow us
> to fix that platform too.
>
> [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/heads/android-msm-bramble-4.19-android11-qpr1/qcom/bengal-usb.dtsi#145
> Fixes: 7756f1d6369e ("phy: qcom-qusb2: Add configuration for SM4250 and SM6115")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* Re: [PATCH v2 0/2] iio: temperature: tmp117: Support the TMP119 sensor
From: Romain Gantois @ 2026-06-10 13:20 UTC (permalink / raw)
To: Jonathan Cameron, Andy Shevchenko
Cc: Puranjay Mohan, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thomas Petazzoni,
Wil Stark, linux-iio, linux-kernel, devicetree
In-Reply-To: <aigpNx-8rbXfJecC@ashevche-desk.local>
[-- Attachment #1: Type: text/plain, Size: 892 bytes --]
On Tuesday, 9 June 2026 16:54:47 CEST Andy Shevchenko wrote:
> On Mon, Jun 08, 2026 at 06:24:12PM +0100, Jonathan Cameron wrote:
> > On Mon, 08 Jun 2026 18:00:23 +0200
> >
> > Romain Gantois <romain.gantois@bootlin.com> wrote:
> > > This is version two of my series which adds support for the TMP119,
> > > which has an identical programming model to the TMP117, but slightly
> > > different specs and electrical characteristics.
> >
> > Other than the DT indent thing Conor calls out this looks fine to me.
> > However, unless the cycle is extended IIO is effectively closed for this
> > kernel cycle. Anything I queue up now will be targeting 7.3 now.
> > On the plus side no rush for v3!
>
> Please, incorporate what I commented on. Id est add #include
> <linux/array_size.h>
ACK, I will.
Thanks,
--
Romain Gantois, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply
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