* [PATCH v4 4/6] arm64: dts: qcom: shikra: Add pin configuration for mclks
From: Nihal Kumar Gupta @ 2026-06-15 8:33 UTC (permalink / raw)
To: Bryan O'Donoghue, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Robert Foss, Andi Shyti, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel, linux-i2c,
imx, linux-arm-kernel, Suresh Vankadara, Vikram Sharma,
Nihal Kumar Gupta
In-Reply-To: <20260615-shikra-camss-review-v4-0-bcb51081735b@oss.qualcomm.com>
Add pinctrl configuration for the four available camera master clocks.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 57732804a6c6a114a407a4a541a1cc7af7635ea2..16b547131e8b14541abc68ff7cda126ba777ad80 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -380,6 +380,34 @@ cci_i2c1_sleep: cci-i2c1-sleep-state {
bias-pull-down;
};
+ cam_mclk0_default: cam-mclk0-default-state {
+ pins = "gpio34";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk1_default: cam-mclk1-default-state {
+ pins = "gpio35";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk2_default: cam-mclk2-default-state {
+ pins = "gpio96";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk3_default: cam-mclk3-default-state {
+ pins = "gpio98";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
qup_uart0_default: qup-uart0-default-state {
pins = "gpio0", "gpio1";
function = "qup0_se0";
--
2.34.1
^ permalink raw reply related
* [PATCH v2 4/5] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk
From: Alim Akhtar @ 2026-06-15 8:52 UTC (permalink / raw)
To: krzk, peter.griffin, robh, conor+dt, linusw
Cc: linux-samsung-soc, linux-kernel, devicetree, linux-gpio,
hajun.sung, Alim Akhtar
In-Reply-To: <20260615085252.1964423-1-alim.akhtar@samsung.com>
Add initial devicetree support for Samsung smdk board using
Exynos8855 SoC.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm64/boot/dts/exynos/Makefile | 1 +
.../boot/dts/exynos/exynos8855-pinctrl.dtsi | 581 ++++++++++++++++++
.../arm64/boot/dts/exynos/exynos8855-smdk.dts | 32 +
arch/arm64/boot/dts/exynos/exynos8855.dtsi | 199 ++++++
4 files changed, 813 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos8855.dtsi
diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
index 76cc23acb9b2..8c48ce2e02e5 100644
--- a/arch/arm64/boot/dts/exynos/Makefile
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \
exynos7870-on7xelte.dtb \
exynos7885-jackpotlte.dtb \
exynos850-e850-96.dtb \
+ exynos8855-smdk.dtb \
exynos8895-dreamlte.dtb \
exynos9810-starlte.dtb \
exynos990-c1s.dtb \
diff --git a/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
new file mode 100644
index 000000000000..df69b2b3e96a
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
@@ -0,0 +1,581 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's S5E8855 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2023 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's S5E8855 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "exynos-pinctrl.h"
+
+&pinctrl_alive {
+ gpa0: gpa0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpa1: gpa1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpq0: gpq0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpq1: gpq1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpc0: gpc0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc1: gpc1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc2: gpc2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc3: gpc3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc4: gpc4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc5: gpc5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc6: gpc6-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc7: gpc7-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc8: gpc8-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc9: gpc9-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc10: gpc10-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc11: gpc11-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc12: gpc12-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc13: gpc13-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc14: gpc14-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpj0: gpj0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpj1: gpj1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpj2: gpj2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart0_pins: uart0-pins {
+ samsung,pins = "gpq0-0", "gpq0-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ };
+
+};
+
+&pinctrl_cmgp {
+ gpm0: gpm0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm1: gpm1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm2: gpm2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm3: gpm3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm4: gpm4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm5: gpm5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm6: gpm6-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm7: gpm7-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm8: gpm8-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm9: gpm9-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm10: gpm10-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm11: gpm11-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm12: gpm12-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm13: gpm13-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm14: gpm14-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm15: gpm15-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm16: gpm16-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm17: gpm17-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm18: gpm18-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm19: gpm19-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm20: gpm20-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm21: gpm21-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&pinctrl_hsi_ufs {
+ gpf3: gpf3-gpio-bank{
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_peric {
+ gpp0: gpp0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp1: gpp1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp2: gpp2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg0: gpg0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg1: gpg1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb0: gpb0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb1: gpb1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_pericmmc {
+ gpf2: gpf2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_usi {
+ gpp3: gpp3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp4: gpp4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg2: gpg2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg3: gpg3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts b/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
new file mode 100644
index 000000000000..f5132bcaa47c
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung Exynos8855 SMDK board device tree source
+ *
+ * Copyright (C) 2026 Samsung Electronics Co., Ltd.
+ *
+ * Device tree source file for WinLink's E850-96 board which is based on
+ * Samsung Exynos8855 SoC.
+ */
+
+/dts-v1/;
+
+#include "exynos8855.dtsi"
+
+/ {
+ model = "Samsung Exynos8855 SMDK board";
+ compatible = "samsung,exynos8855-smdk","samsung,exynos8855";
+
+ chosen {
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x80000000>;
+ };
+
+};
+
+&oscclk {
+ clock-frequency = <76800000>;
+};
+
diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
new file mode 100644
index 000000000000..d403f41bbecb
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung Exynos8855 SoC device tree source
+ *
+ * Copyright (C) 2023 Samsung Electronics Co., Ltd.
+ *
+ * Samsung Exynos8855 SoC device nodes are listed in this file.
+ * Exynos8855 based board files can include this file and provide
+ * values for board specific bindings.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "samsung,exynos8855";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ pinctrl0 = &pinctrl_alive;
+ pinctrl1 = &pinctrl_cmgp;
+ pinctrl2 = &pinctrl_hsi_ufs;
+ pinctrl3 = &pinctrl_peric;
+ pinctrl4 = &pinctrl_pericmmc;
+ pinctrl5 = &pinctrl_usi;
+ };
+
+ oscclk: clock-oscclk {
+ compatible = "fixed-clock";
+ clock-output-names = "oscclk";
+ #clock-cells = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x200>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x300>;
+ enable-method = "psci";
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x400>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x500>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x600>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x700>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x20000000>;
+
+ gic: interrupt-controller@10200000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x10200000 0x10000>,
+ <0x10240000 0x140000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_alive: pinctrl@11850000 {
+ compatible = "samsung,exynos8855-pinctrl";
+ reg = <0x11850000 0x1000>;
+
+ wakeup-interrupt-controller {
+ compatible = "samsung,exynos850-wakeup-eint",
+ "samsung,exynos7-wakeup-eint";
+ };
+ };
+
+ pinctrl_cmgp: pinctrl@12030000 {
+ compatible = "samsung,exynos8855-pinctrl";
+ reg = <0x12030000 0x1000>;
+ };
+
+ pinctrl_usi: pinctrl@15030000 {
+ compatible = "samsung,exynos8855-pinctrl";
+ reg = <0x15030000 0x1000>;
+ };
+
+ pinctrl_peric: pinctrl@15440000 {
+ compatible = "samsung,exynos8855-pinctrl";
+ reg = <0x15440000 0x1000>;
+ };
+
+ pinctrl_pericmmc: pinctrl@154f0000 {
+ compatible = "samsung,exynos8855-pinctrl";
+ reg = <0x154f0000 0x1000>;
+ };
+
+ pinctrl_hsi_ufs: pinctrl@17040000 {
+ compatible = "samsung,exynos8855-pinctrl";
+ reg = <0x17040000 0x1000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ /* Hypervisor Virtual Timer interrupt is not wired to GIC */
+ interrupts =
+ <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
+
+#include "exynos8855-pinctrl.dtsi"
--
2.34.1
^ permalink raw reply related
* [PATCH v4 3/6] arm64: dts: qcom: shikra: Add CCI definitions
From: Nihal Kumar Gupta @ 2026-06-15 8:33 UTC (permalink / raw)
To: Bryan O'Donoghue, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Robert Foss, Andi Shyti, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel, linux-i2c,
imx, linux-arm-kernel, Suresh Vankadara, Vikram Sharma,
Nihal Kumar Gupta
In-Reply-To: <20260615-shikra-camss-review-v4-0-bcb51081735b@oss.qualcomm.com>
Qualcomm Shikra SoC has one Camera Control Interface (CCI)
containing two I2C hosts.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 70 ++++++++++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index f0e827996609dab2c09834857a1bffd9560155a6..57732804a6c6a114a407a4a541a1cc7af7635ea2 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -348,6 +348,38 @@ tlmm: pinctrl@500000 {
gpio-ranges = <&tlmm 0 0 165>;
wakeup-parent = <&mpm>;
+ cci_i2c0_default: cci-i2c0-default-state {
+ /* SDA, SCL */
+ pins = "gpio36", "gpio37";
+ function = "cci_i2c0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci_i2c0_sleep: cci-i2c0-sleep-state {
+ /* SDA, SCL */
+ pins = "gpio36", "gpio37";
+ function = "cci_i2c0";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci_i2c1_default: cci-i2c1-default-state {
+ /* SDA, SCL */
+ pins = "gpio41", "gpio42";
+ function = "cci_i2c1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci_i2c1_sleep: cci-i2c1-sleep-state {
+ /* SDA, SCL */
+ pins = "gpio41", "gpio42";
+ function = "cci_i2c1";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
qup_uart0_default: qup-uart0-default-state {
pins = "gpio0", "gpio1";
function = "qup0_se0";
@@ -702,6 +734,44 @@ port@1 {
reg = <1>;
};
};
+
+ };
+
+ cci: cci@5c1b000 {
+ compatible = "qcom,shikra-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x05c1b000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING 0>;
+
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_0_CLK>;
+ clock-names = "ahb",
+ "cci";
+
+ power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
+
+ pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>;
+ pinctrl-1 = <&cci_i2c0_sleep &cci_i2c1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
qupv3_0: geniqup@4ac0000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 3/5] pinctrl: samsung: Add Exynos8855 pinctrl configuration
From: Alim Akhtar @ 2026-06-15 8:52 UTC (permalink / raw)
To: krzk, peter.griffin, robh, conor+dt, linusw
Cc: linux-samsung-soc, linux-kernel, devicetree, linux-gpio,
hajun.sung, Alim Akhtar
In-Reply-To: <20260615085252.1964423-1-alim.akhtar@samsung.com>
Add pinctrl configuration for Exynos8855. The bank type
macros are reused from Exynos850 SoC.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
.../pinctrl/samsung/pinctrl-exynos-arm64.c | 123 ++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
3 files changed, 126 insertions(+)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index fe9f92cb037e..db120ae4d847 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -943,6 +943,129 @@ const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = {
.num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl),
};
+/* pin banks of exynos8855 pin-controller 0 (ALIVE) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks0[] __initconst = {
+ /* Must start with EINTG banks, ordered by EINT group number. */
+ EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
+ EXYNOS850_PIN_BANK_EINTW(4, 0x020, "gpa1", 0x04),
+ EXYNOS850_PIN_BANK_EINTN(3, 0x040, "gpq0"),
+ EXYNOS850_PIN_BANK_EINTN(2, 0x060, "gpq1"),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpc0", 0x10),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpc1", 0x14),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpc2", 0x18),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpc3", 0x1c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpc4", 0x20),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpc5", 0x24),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpc6", 0x28),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpc7", 0x2c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpc8", 0x30),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x1a0, "gpc9", 0x34),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x1c0, "gpc10", 0x38),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x1e0, "gpc11", 0x3c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpc12", 0x40),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpc13", 0x44),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpc14", 0x48),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpj0", 0x4c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpj1", 0x50),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x2a0, "gpj2", 0x54),
+};
+
+/* pin banks of exynos8855 pin-controller 1 (CMGP) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks1[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTW(1, 0x00, "gpm0", 0x00),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x20, "gpm1", 0x04),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x40, "gpm2", 0x08),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x60, "gpm3", 0x0c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x80, "gpm4", 0x10),
+ EXYNOS850_PIN_BANK_EINTW(1, 0xa0, "gpm5", 0x14),
+ EXYNOS850_PIN_BANK_EINTW(1, 0xc0, "gpm6", 0x18),
+ EXYNOS850_PIN_BANK_EINTW(1, 0xe0, "gpm7", 0x1c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x1a0, "gpm13", 0x34),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4c),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50),
+ EXYNOS850_PIN_BANK_EINTW(1, 0x2a0, "gpm21", 0x54),
+};
+
+
+/* pin banks of exynos8855 pin-controller 2 (HSI UFS) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks2[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gpf3", 0x00),
+};
+
+/* pin banks of exynos8855 pin-controller 3 (PERIC) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks3[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTG(8, 0x0, "gpp0", 0x00),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpp1", 0x04),
+ EXYNOS850_PIN_BANK_EINTG(6, 0x40, "gpp2", 0x08),
+ EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpg0", 0x0c),
+ EXYNOS850_PIN_BANK_EINTG(3, 0x80, "gpg1", 0x10),
+ EXYNOS850_PIN_BANK_EINTG(6, 0xa0, "gpb0", 0x14),
+ EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpb1", 0x18),
+};
+
+/* pin banks of exynos8855 pin-controller 4 (PERICMMC) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks4[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpf2", 0x00),
+};
+
+/* pin banks of exynos8855 pin-controller 5 (USI) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks5[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTG(8, 0x00, "gpp3", 0x00),
+ EXYNOS850_PIN_BANK_EINTG(2, 0x20, "gpp4", 0x04),
+ EXYNOS850_PIN_BANK_EINTG(2, 0x40, "gpg2", 0x08),
+ EXYNOS850_PIN_BANK_EINTG(1, 0x60, "gpg3", 0x0c),
+};
+
+static const struct samsung_pin_ctrl exynos8855_pin_ctrl[] __initconst = {
+ {
+ /* pin-controller instance 0 ALIVE data */
+ .pin_banks = exynos8855_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks0),
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin-controller instance 1 CMGP data */
+ .pin_banks = exynos8855_pin_banks1,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks1),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin-controller instance 2 HSI UFS data */
+ .pin_banks = exynos8855_pin_banks2,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks2),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin-controller instance 3 PERIC data */
+ .pin_banks = exynos8855_pin_banks3,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks3),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin-controller instance 4 PERICMMC data */
+ .pin_banks = exynos8855_pin_banks4,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks4),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ }, {
+ /* pin-controller instance 5 USI data */
+ .pin_banks = exynos8855_pin_banks5,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks5),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ },
+};
+
+const struct samsung_pinctrl_of_match_data exynos8855_of_data __initconst = {
+ .ctrl = exynos8855_pin_ctrl,
+ .num_ctrl = ARRAY_SIZE(exynos8855_pin_ctrl),
+};
+
/* pin banks of exynos990 pin-controller 0 (ALIVE) */
static struct samsung_pin_bank_data exynos990_pin_banks0[] = {
/* Must start with EINTG banks, ordered by EINT group number. */
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 5ac6f6b02327..5ecc9ed4c44d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1500,6 +1500,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = &exynos7885_of_data },
{ .compatible = "samsung,exynos850-pinctrl",
.data = &exynos850_of_data },
+ { .compatible = "samsung,exynos8855-pinctrl",
+ .data = &exynos8855_of_data },
{ .compatible = "samsung,exynos8890-pinctrl",
.data = &exynos8890_of_data },
{ .compatible = "samsung,exynos8895-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 937600430a6e..bb02fb49b2af 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -396,6 +396,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
extern const struct samsung_pinctrl_of_match_data exynos7870_of_data;
extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
+extern const struct samsung_pinctrl_of_match_data exynos8855_of_data;
extern const struct samsung_pinctrl_of_match_data exynos8890_of_data;
extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
extern const struct samsung_pinctrl_of_match_data exynos9610_of_data;
--
2.34.1
^ permalink raw reply related
* [PATCH v4 2/6] arm64: dts: qcom: shikra: Add CAMSS node
From: Nihal Kumar Gupta @ 2026-06-15 8:33 UTC (permalink / raw)
To: Bryan O'Donoghue, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Robert Foss, Andi Shyti, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel, linux-i2c,
imx, linux-arm-kernel, Suresh Vankadara, Vikram Sharma,
Nihal Kumar Gupta
In-Reply-To: <20260615-shikra-camss-review-v4-0-bcb51081735b@oss.qualcomm.com>
Add the Camera Subsystem node. Shikra shares the same IP as QCM2290
with two CSIPHYs, two CSIDs and two VFEs, but does not include CDM
and OPE blocks, so only a single IOMMU context bank is needed.
Co-developed-by: Vikram Sharma <vikram.sharma@oss.qualcomm.com>
Signed-off-by: Vikram Sharma <vikram.sharma@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 100 +++++++++++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index a4334d99c1f35ee851ca8266ec37d4a200a07ee5..f0e827996609dab2c09834857a1bffd9560155a6 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -604,6 +604,106 @@ opp-384000000 {
};
};
+ camss: camss@5c11000 {
+ compatible = "qcom,shikra-camss", "qcom,qcm2290-camss";
+
+ reg = <0x0 0x05c11000 0x0 0x1000>,
+ <0x0 0x05c6e000 0x0 0x1000>,
+ <0x0 0x05c75000 0x0 0x1000>,
+ <0x0 0x05c52000 0x0 0x1000>,
+ <0x0 0x05c53000 0x0 0x1000>,
+ <0x0 0x05c66000 0x0 0x400>,
+ <0x0 0x05c68000 0x0 0x400>,
+ <0x0 0x05c6f000 0x0 0x4000>,
+ <0x0 0x05c76000 0x0 0x4000>;
+ reg-names = "top",
+ "csid0",
+ "csid1",
+ "csiphy0",
+ "csiphy1",
+ "csitpg0",
+ "csitpg1",
+ "vfe0",
+ "vfe1";
+
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMSS_AXI_CLK>,
+ <&gcc GCC_CAMSS_NRT_AXI_CLK>,
+ <&gcc GCC_CAMSS_RT_AXI_CLK>,
+ <&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
+ <&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
+ <&gcc GCC_CAMSS_CPHY_0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CPHY_1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_TFE_0_CLK>,
+ <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_TFE_1_CLK>,
+ <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>;
+ clock-names = "ahb",
+ "axi",
+ "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "csi0",
+ "csi1",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "top_ahb",
+ "vfe0",
+ "vfe0_cphy_rx",
+ "vfe1",
+ "vfe1_cphy_rx";
+
+ interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 212 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 309 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 211 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 213 IRQ_TYPE_EDGE_RISING 0>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csiphy0",
+ "csiphy1",
+ "csitpg0",
+ "csitpg1",
+ "vfe0",
+ "vfe1";
+
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>,
+ <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "ahb",
+ "hf_mnoc",
+ "sf_mnoc";
+
+ iommus = <&apps_smmu 0x400 0x0>;
+
+ power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
qupv3_0: geniqup@4ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x04ac0000 0x0 0x2000>;
--
2.34.1
^ permalink raw reply related
* [PATCH v2 2/5] dt-binding: pinctrl: samsung: Add exynos8855-pinctrl compatible
From: Alim Akhtar @ 2026-06-15 8:52 UTC (permalink / raw)
To: krzk, peter.griffin, robh, conor+dt, linusw
Cc: linux-samsung-soc, linux-kernel, devicetree, linux-gpio,
hajun.sung, Alim Akhtar
In-Reply-To: <20260615085252.1964423-1-alim.akhtar@samsung.com>
Document pin controller support on Exynos8855 SoC.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
index 7b006009ca0e..c4773701c92e 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
@@ -53,6 +53,7 @@ properties:
- samsung,exynos7870-pinctrl
- samsung,exynos7885-pinctrl
- samsung,exynos850-pinctrl
+ - samsung,exynos8855-pinctrl
- samsung,exynos8890-pinctrl
- samsung,exynos8895-pinctrl
- samsung,exynos9610-pinctrl
--
2.34.1
^ permalink raw reply related
* [PATCH v2 1/5] dt-binding: ARM: samsung: Add Samsung Exynos8855
From: Alim Akhtar @ 2026-06-15 8:52 UTC (permalink / raw)
To: krzk, peter.griffin, robh, conor+dt, linusw
Cc: linux-samsung-soc, linux-kernel, devicetree, linux-gpio,
hajun.sung, Alim Akhtar
In-Reply-To: <20260615085252.1964423-1-alim.akhtar@samsung.com>
Add Samsung Exynos8855 smdk board to documentation
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
.../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
index 753b3ba1b607..273464400477 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
@@ -235,6 +235,12 @@ properties:
- winlink,e850-96 # WinLink E850-96
- const: samsung,exynos850
+ - description: Exynos8855 based boards
+ items:
+ - enum:
+ - samsung,exynos8855-smdk # Samsung SMDK
+ - const: samsung,exynos8855
+
- description: Exynos8895 based boards
items:
- enum:
--
2.34.1
^ permalink raw reply related
* [PATCH v2 0/5] Add minimal Exynos8855 SoC support
From: Alim Akhtar @ 2026-06-15 8:52 UTC (permalink / raw)
To: krzk, peter.griffin, robh, conor+dt, linusw
Cc: linux-samsung-soc, linux-kernel, devicetree, linux-gpio,
hajun.sung, Alim Akhtar
In-Reply-To: <CGME20260615083410epcas5p162d288f0bb2431bdd3653011d7a72688@epcas5p1.samsung.com>
This series adds initial support for the Exynos8855 SoC and also
initial SMDK board support.
Exynos8855 is octa-core CPUs, a combination of Cortex-A720 and Cortex-A520,
arranged in 3 clusters. And other peripheral for mobile application.
This initial support consists of CPUs, pinctrl and related nodes
needed for initial kernel boot.
With these patches, kernel can boot using initramfs till file system mounts.
More platform support will be added in near future, clock driver to go next.
Chanegs since v1:
* Fixed some of the review comments by Sashiko [1]
* Dropped serial node, will be added once clock support is available
* Dropped wkup interrupt for CMGP block, will be added later
Link of v1:
https://lore.kernel.org/linux-samsung-soc/20260612163020.411761-1-alim.akhtar@samsung.com/
[1] https://sashiko.dev/#/patchset/20260612163020.411761-1-alim.akhtar@samsung.com?part=4
Alim Akhtar (5):
dt-binding: ARM: samsung: Add Samsung Exynos8855
dt-binding: pinctrl: samsung: Add exynos8855-pinctrl compatible
pinctrl: samsung: Add Exynos8855 pinctrl configuration
arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk
MAINTAINERS: Add entry for Samsung Exynos8855 SoC
.../bindings/arm/samsung/samsung-boards.yaml | 6 +
.../bindings/pinctrl/samsung,pinctrl.yaml | 1 +
MAINTAINERS | 7 +
arch/arm64/boot/dts/exynos/Makefile | 1 +
.../boot/dts/exynos/exynos8855-pinctrl.dtsi | 581 ++++++++++++++++++
.../arm64/boot/dts/exynos/exynos8855-smdk.dts | 32 +
arch/arm64/boot/dts/exynos/exynos8855.dtsi | 199 ++++++
.../pinctrl/samsung/pinctrl-exynos-arm64.c | 123 ++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
10 files changed, 953 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos8855.dtsi
base-commit: b99ae45861eccff1e1d8c7b05a13650be805d437
--
2.34.1
^ permalink raw reply
* [PATCH v4 1/6] dt-bindings: media: qcom: Add Shikra CAMSS compatible
From: Nihal Kumar Gupta @ 2026-06-15 8:33 UTC (permalink / raw)
To: Bryan O'Donoghue, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Robert Foss, Andi Shyti, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel, linux-i2c,
imx, linux-arm-kernel, Suresh Vankadara, Vikram Sharma,
Nihal Kumar Gupta, Krzysztof Kozlowski
In-Reply-To: <20260615-shikra-camss-review-v4-0-bcb51081735b@oss.qualcomm.com>
Shikra contains the same Camera Subsystem IP as QCM2290. Document the
platform-specific compatible string, using qcom,qcm2290-camss as
fallback.
Unlike QCM2290, Shikra omits the CDM and OPE blocks, requiring only a
single IOMMU context bank instead of four.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
.../devicetree/bindings/media/qcom,qcm2290-camss.yaml | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml
index 391d0f6f67ef5fdfea31dd3683477561516b1556..490a7f3a8c5ff9c624f46150ee651793811823de 100644
--- a/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml
@@ -14,7 +14,11 @@ description:
properties:
compatible:
- const: qcom,qcm2290-camss
+ oneOf:
+ - items:
+ - const: qcom,shikra-camss
+ - const: qcom,qcm2290-camss
+ - const: qcom,qcm2290-camss
reg:
maxItems: 9
@@ -76,7 +80,14 @@ properties:
- const: sf_mnoc
iommus:
- maxItems: 4
+ oneOf:
+ - items:
+ - description: S1 HLOS VFE non-protected (VFE only)
+ - items:
+ - description: S1 HLOS VFE non-protected
+ - description: S1 HLOS CDM non-protected
+ - description: S1 HLOS OPE read non-protected
+ - description: S1 HLOS OPE write non-protected
power-domains:
items:
--
2.34.1
^ permalink raw reply related
* [PATCH v4 0/6] Add CAMSS and IMX577 sensor support for Shikra EVK
From: Nihal Kumar Gupta @ 2026-06-15 8:33 UTC (permalink / raw)
To: Bryan O'Donoghue, Vladimir Zapolskiy, Loic Poulain,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Robert Foss, Andi Shyti, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel, linux-i2c,
imx, linux-arm-kernel, Suresh Vankadara, Vikram Sharma,
Nihal Kumar Gupta, Krzysztof Kozlowski
Shikra EVK is based on the Qualcomm Shikra SoC.
It lacks a camera sensor in its default configuration.
This series adds CAMSS driver support, CCI definitions and enables
the 22-pin IMX577 sensor via CSIPHY1 through device tree overlays.
We have tested IMX577 Sensor on CCI1 with following commands:
- media-ctl --reset
- media-ctl -d /dev/media0 -V '"imx577 1-001a":0[fmt:SRGGB10/4056x3040 field:none]'
- media-ctl -d /dev/media0 -V '"msm_csiphy1":0[fmt:SRGGB10/4056x3040]'
- media-ctl -d /dev/media0 -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]'
- media-ctl -d /dev/media0 -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]'
- media-ctl -d /dev/media0 -l '"msm_csiphy1":1->"msm_csid0":0[1]'
- media-ctl -d /dev/media0 -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
- yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0
Used following tools for the sanity check of these changes.
- make -j32 W=1
- checkpatch.pl
- make DT_CHECKER_FLAGS=-m W=1 DT_SCHEMA_FILES=i2c/qcom,i2c-cci.yaml dt_binding_check
- make DT_CHECKER_FLAGS=-m DT_SCHEMA_FILES=media/qcom,qcm2290-camss.yaml dt_binding_check W=1
- make CHECK_DTBS=y W=1 qcom/qrb2210-rb1-vision-mezzanine.dtb
- make CHECK_DTBS=1 W=1 qcom/shikra-cqm-cqs-evk-imx577-camera.dtb
- make CHECK_DTBS=1 W=1 qcom/shikra-iqs-evk-imx577-camera.dtb
- make CHECK_DTBS=y W=1 dtbs
The Shikra CAMSS binding patch does not depend on the rest of the series
and can go through the media tree on its own.
This patch series depends on patch series:
https://lore.kernel.org/all/20260527-shikra-dt-v4-0-b5ca1fa0b392@oss.qualcomm.com/
https://lore.kernel.org/all/20260608-shikra-gcc-rpmcc-clks-v5-0-94cefe092ee3@oss.qualcomm.com/
Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
---
Changes in v4:
- Fix data-lanes numbering to start from 1 in all endpoints (Vladimir)
Missed in last rev.
- Link to v3: https://lore.kernel.org/r/20260615-shikra-camss-review-v3-0-8183481f48d0@oss.qualcomm.com
Changes in v3:
- Drop dt-bindings: i2c: qcom-cci: Document Shikra compatible; already
picked by Andi Shyti into her i2c tree (now in linux-next as e3a8f8329397)
- Preserve blank line after compatible const in qcom,qcm2290-camss.yaml (Krzysztof)
- Add blank line between iommus and power-domains in CAMSS node (Vladimir)
- Move cam1_reset_default pinctrl state from board .dts files into the
mezzanine .dtso overlay files (Vladimir)
- Collect Reviewed-by tags
- Link to v2: https://lore.kernel.org/r/20260608-shikra-camss-review-v2-0-ca1936bf1219@oss.qualcomm.com
Changes in v2:
- Drop qcm2390_resources struct and CAMSS_2390 enum; use qcom,qcm2290-camss
as fallback compatible string since Shikra CAMSS is register-compatible
with QCM2290 (Loic, Bryan)
- Use oneOf in iommus to describe all valid SID combinations: VFE-only
(Shikra) and VFE+CDM+OPE read+OPE write (QCM2290/Agatti); add
per-entry descriptions naming each SID (Krzysztof, Bryan)
- Rename shikra-cqm-evk-imx577-camera overlay to
shikra-cqm-cqs-evk-imx577-camera, shared by both CQM and CQS EVK
boards which use the same PM4125 PMIC and camera supply rails (Bryan)
- Add reset-gpios pinctrl state for IMX577 sensor (gpio33, cam1-reset-default-state)
- Add comment in overlay DTS explaining absent regulators are powered
by the daughter board (Bryan)
- Collect Reviewed-by tags
- Add reset-gpios pinctrl state for IMX577 sensor.
- Link to v1: https://lore.kernel.org/r/20260526-shikra-camss-review-v1-0-645d2c8c75a7@qti.qualcomm.com
---
Nihal Kumar Gupta (6):
dt-bindings: media: qcom: Add Shikra CAMSS compatible
arm64: dts: qcom: shikra: Add CAMSS node
arm64: dts: qcom: shikra: Add CCI definitions
arm64: dts: qcom: shikra: Add pin configuration for mclks
arm64: dts: qcom: shikra-cqm-cqs-evk-imx577-camera: Add DT overlay
arm64: dts: qcom: shikra-iqs-evk-imx577-camera: Add DT overlay
.../bindings/media/qcom,qcm2290-camss.yaml | 15 +-
arch/arm64/boot/dts/qcom/Makefile | 8 +
.../dts/qcom/shikra-cqm-cqs-evk-imx577-camera.dtso | 79 ++++++++
.../dts/qcom/shikra-iqs-evk-imx577-camera.dtso | 79 ++++++++
arch/arm64/boot/dts/qcom/shikra.dtsi | 198 +++++++++++++++++++++
5 files changed, 377 insertions(+), 2 deletions(-)
---
base-commit: abe651837cb394f76d738a7a747322fca3bf17ba
change-id: 20260526-shikra-camss-review-cf6f66ac566b
prerequisite-change-id: 20260511-shikra-dt-d75d97454646:v4
prerequisite-patch-id: 3a689e8dda5fd2755b689d94d095806b3f2e6eed
prerequisite-patch-id: 2acc300a68ed8c5364fb5f2f7d28fc0d56ab07bf
prerequisite-patch-id: 2357cac636e019eaf14d6a493a1c72bca56fe405
prerequisite-patch-id: 2885f299e711582da312ca9d13983d296a3dd5dc
prerequisite-patch-id: 91af5f3c01e766a53ce8de69aa21847a2d6bbbf8
prerequisite-change-id: 20260429-shikra-gcc-rpmcc-clks-2094edfff3b0:v5
prerequisite-patch-id: 59bb0a7828e41f546f734f127d81da83c0adcda9
prerequisite-patch-id: 197da6bcb15cadc47869dba88c8020987b25c335
prerequisite-patch-id: 8ec9c1eb03f052ae232ed54117abed38672c23f6
prerequisite-patch-id: 350db4f4bcdfc0fad9ed57cd5b1723f85ad44f5d
Best regards,
--
Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v6 2/2] i2c: ls2x: Add clocks property parsing and adjust bus speed
From: Andi Shyti @ 2026-06-15 8:33 UTC (permalink / raw)
To: Huacai Chen
Cc: Hongliang Wang, Binbin Zhou, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Wolfram Sang, linux-i2c, devicetree, loongarch,
Huacai Chen, stable
In-Reply-To: <CAAhV-H5R9fPvUs7dvNrZAbXrGiWvE4YPkaca2nxnhgS3A+TVYw@mail.gmail.com>
...
> > >> Based on i2c bus reference clock(clock_a), i2c bus speed(clock_s)
> > >> and div, calculate the prcescale of i2c divider register. The
> > >> calculation formula is
> > >>
> > >> prcescale = (clock_a*10)/(div*clock_s)-1
> > >>
> > >> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
> > > I think Huacai has not reviewed this patch, his review was only
> > > for patch 1. Am I right?
> > >
> > > Andi
> > Sorry, it was my mistake, I will send a new version later.
> Why? I really gave some suggestions in previous versions and you accepted.
> If an explicitly R-b is needed for each one, then
> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Yes, no need to resend it. The R-b should be added only when it
is explicitly given; otherwise, I can't tell whether the reviewer
agrees with the changes.
Thanmks,
Andi
^ permalink raw reply
* [PATCH RESEND] dt-bindings: remoteproc: qcom,sm8550-pas: Add Qualcomm Maili ADSP and CDSP
From: Yijie Yang @ 2026-06-15 8:30 UTC (permalink / raw)
To: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam
Cc: linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
Yijie Yang
Document compatible strings for the ADSP and CDSP Peripheral Authentication
Services on the Qualcomm Maili SoC. Both are compatible with the Qualcomm
SM8550 PAS and can fallback to SM8550 except for one additional interrupt
("shutdown-ack"). For CDSP, similar to Kaanapali, "global_sync_mem" is
not managed by the kernel.
Assisted-by: Claude:claude-opus-4-6
Signed-off-by: Yijie Yang <yijie.yang@oss.qualcomm.com>
---
Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
index 1e4db0c9fcf9..ead7a7d68f59 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
@@ -31,12 +31,14 @@ properties:
- enum:
- qcom,glymur-adsp-pas
- qcom,kaanapali-adsp-pas
+ - qcom,maili-adsp-pas
- qcom,sm8750-adsp-pas
- const: qcom,sm8550-adsp-pas
- items:
- enum:
- qcom,glymur-cdsp-pas
- qcom,kaanapali-cdsp-pas
+ - qcom,maili-cdsp-pas
- const: qcom,sm8550-cdsp-pas
- items:
- const: qcom,sm8750-cdsp-pas
@@ -106,6 +108,8 @@ allOf:
- qcom,glymur-cdsp-pas
- qcom,kaanapali-adsp-pas
- qcom,kaanapali-cdsp-pas
+ - qcom,maili-adsp-pas
+ - qcom,maili-cdsp-pas
- qcom,sm8750-adsp-pas
then:
properties:
---
base-commit: 550604d6c9b9efc8d068aff94dc301694a7afdee
change-id: 20260522-remoteproc-9eca14b9a3ae
Best regards,
--
Yijie Yang <yijie.yang@oss.qualcomm.com>
--
Yijie Yang <yijie.yang@oss.qualcomm.com>
^ permalink raw reply related
* [PATCH RESEND] dt-bindings: interrupt-controller: qcom,pdc: Add Maili compatible string
From: Yijie Yang @ 2026-06-15 8:28 UTC (permalink / raw)
To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson
Cc: linux-arm-msm, linux-kernel, devicetree, Yijie Yang
Register qcom,maili-pdc as a supported compatible string for the
Qualcomm PDC interrupt controller binding.
Signed-off-by: Yijie Yang <yijie.yang@oss.qualcomm.com>
---
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
index 07a46c5457a4..8162a49d49a6 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
@@ -30,6 +30,7 @@ properties:
- qcom,glymur-pdc
- qcom,hawi-pdc
- qcom,kaanapali-pdc
+ - qcom,maili-pdc
- qcom,milos-pdc
- qcom,nord-pdc
- qcom,qcs615-pdc
---
base-commit: 550604d6c9b9efc8d068aff94dc301694a7afdee
change-id: 20260427-maili-pdc-71a488a96973
Best regards,
--
Yijie Yang <yijie.yang@oss.qualcomm.com>
--
Yijie Yang <yijie.yang@oss.qualcomm.com>
^ permalink raw reply related
* Re: [PATCH v4 2/6] drm/verisilicon: add register-level macros for DC8000
From: Icenowy Zheng @ 2026-06-15 8:24 UTC (permalink / raw)
To: Joey Lu, maarten.lankhorst, mripard, tzimmermann, airlied, simona,
robh, krzk+dt, conor+dt
Cc: ychuang3, schung, yclu4, dri-devel, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <20260615065003.76661-3-a0987203069@gmail.com>
在 2026-06-15一的 14:49 +0800，Joey Lu写道：
> Add register-level constants needed by the forthcoming DC8000
> (DCUltraLite)
> hardware ops:
>
> VSDC_DISP_IRQ_VSYNC(n) in vs_crtc_regs.h: bit mask for per-output
> VSYNC interrupt bits in DISP_IRQ_STA (0x147C) / DISP_IRQ_EN
> (0x1480),
> which are the IRQ registers used by DCUltraLite in place of the
> DC8200
> TOP_IRQ_ACK / TOP_IRQ_EN registers.
>
> VSDC_FB_CONFIG_ENABLE (bit 0), VSDC_FB_CONFIG_VALID (bit 3) and
> VSDC_FB_CONFIG_RESET (bit 4) in vs_primary_plane_regs.h: control
> bits
> in the FB_CONFIG register used by DCUltraLite for framebuffer
> enable
> and per-frame commit handshake.
Validated against DC8000 register list.
Reviewed-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
>
> No behaviour change for existing DC8200 platforms.
>
> Signed-off-by: Joey Lu <a0987203069@gmail.com>
> ---
> drivers/gpu/drm/verisilicon/vs_crtc_regs.h | 1 +
> drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/verisilicon/vs_crtc_regs.h
> b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h
> index c7930e817635..d4da22b08cd5 100644
> --- a/drivers/gpu/drm/verisilicon/vs_crtc_regs.h
> +++ b/drivers/gpu/drm/verisilicon/vs_crtc_regs.h
> @@ -54,6 +54,7 @@
> #define VSDC_DISP_GAMMA_DATA(n) (0x1460 +
> 0x4 * (n))
>
> #define VSDC_DISP_IRQ_STA 0x147C
> +#define VSDC_DISP_IRQ_VSYNC(n) BIT(n)
>
> #define VSDC_DISP_IRQ_EN 0x1480
>
> diff --git a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h
> b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h
> index cbb125c46b39..67d4b00f294e 100644
> --- a/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h
> +++ b/drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h
> @@ -16,6 +16,9 @@
> #define VSDC_FB_STRIDE(n) (0x1408 + 0x4 * (n))
>
> #define VSDC_FB_CONFIG(n) (0x1518 + 0x4 * (n))
> +#define VSDC_FB_CONFIG_ENABLE BIT(0)
> +#define VSDC_FB_CONFIG_VALID BIT(3)
> +#define VSDC_FB_CONFIG_RESET BIT(4)
> #define VSDC_FB_CONFIG_CLEAR_EN BIT(8)
> #define VSDC_FB_CONFIG_ROT_MASK GENMASK(13,
> 11)
> #define VSDC_FB_CONFIG_ROT(v) ((v) << 11)
^ permalink raw reply
* Re: [PATCH v4 2/2] drm/panel: Add panel driver for Chipone ICNA35XX based panels
From: Neil Armstrong @ 2026-06-15 8:20 UTC (permalink / raw)
To: webgeek1234, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: dri-devel, devicetree, linux-kernel, Teguh Sobirin
In-Reply-To: <20260607-icna35xx-v4-2-64de514add34@gmail.com>
On 6/7/26 22:11, Aaron Kling via B4 Relay wrote:
> From: Teguh Sobirin <teguh@sobir.in>
>
> This adds support for the ICNA3512 and ICNA3520 DDICs used in both the
> AYN Odin 2 Portal and Ayaneo Pocket DS top panel respectively and for
> for both the AYN Odin 3 and the AYN Thor top panel respectively.
>
> These all have unique compatibles because the panels themselves are
> likely unique hardware with only the ddic's and thus api and driver
> handling shared.
>
> Signed-off-by: Teguh Sobirin <teguh@sobir.in>
> Co-developed-by: Aaron Kling <webgeek1234@gmail.com>
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
> drivers/gpu/drm/panel/Kconfig | 11 +
> drivers/gpu/drm/panel/Makefile | 1 +
> drivers/gpu/drm/panel/panel-chipone-icna35xx.c | 422 +++++++++++++++++++++++++
> 3 files changed, 434 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> index 7450b27622a233..1368b5a0b6c912 100644
> --- a/drivers/gpu/drm/panel/Kconfig
> +++ b/drivers/gpu/drm/panel/Kconfig
> @@ -105,6 +105,17 @@ config DRM_PANEL_BOE_TV101WUM_LL2
> Say Y here if you want to support for BOE TV101WUM-LL2
> WUXGA PANEL DSI Video Mode panel
>
> +config DRM_PANEL_CHIPONE_ICNA35XX
> + tristate "Chipone ICNA35XX panel driver"
> + depends on OF
> + depends on DRM_MIPI_DSI
> + depends on BACKLIGHT_CLASS_DEVICE
> + select DRM_DISPLAY_HELPER
> + help
> + Say Y here if you want to enable support for the panels built
> + around the Chipone ICNA3512 and ICNA3520 display controllers,
> + such as some Tianma panels used in AYN Odin2 Portal and Thor.
> +
> config DRM_PANEL_CHIPWEALTH_CH13726A
> tristate "CHIPWEALTH CH13726A-based DSI panel"
> depends on OF
> diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> index c2c5cf81711633..d39a8f82fa8c06 100644
> --- a/drivers/gpu/drm/panel/Makefile
> +++ b/drivers/gpu/drm/panel/Makefile
> @@ -9,6 +9,7 @@ obj-$(CONFIG_DRM_PANEL_BOE_TD4320) += panel-boe-td4320.o
> obj-$(CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A) += panel-boe-th101mb31ig002-28a.o
> obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_LL2) += panel-boe-tv101wum-ll2.o
> obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
> +obj-$(CONFIG_DRM_PANEL_CHIPONE_ICNA35XX) += panel-chipone-icna35xx.o
> obj-$(CONFIG_DRM_PANEL_CHIPWEALTH_CH13726A) += panel-chipwealth-ch13726a.o
> obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o
> obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
> diff --git a/drivers/gpu/drm/panel/panel-chipone-icna35xx.c b/drivers/gpu/drm/panel/panel-chipone-icna35xx.c
> new file mode 100644
> index 00000000000000..86d096455caa1c
> --- /dev/null
> +++ b/drivers/gpu/drm/panel/panel-chipone-icna35xx.c
> @@ -0,0 +1,422 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Chipone ICNA35XX Driver IC panels driver
> + *
> + * Copyright (c) 2025 Teguh Sobirin <teguh@sobir.in>
> + */
> +
> +#include <linux/backlight.h>
> +#include <linux/delay.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_graph.h>
> +#include <linux/regulator/consumer.h>
> +
> +#include <video/mipi_display.h>
> +
> +#include <drm/display/drm_dsc.h>
> +#include <drm/display/drm_dsc_helper.h>
> +#include <drm/drm_connector.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_mipi_dsi.h>
> +#include <drm/drm_modes.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_probe_helper.h>
> +
> +struct panel_info {
> + struct drm_panel panel;
> + struct drm_connector *connector;
> + struct mipi_dsi_device *dsi;
> + struct panel_desc *desc;
> + enum drm_panel_orientation orientation;
> +
> + struct gpio_desc *reset_gpio;
> + struct regulator_bulk_data *supplies;
> +};
> +
> +struct panel_desc {
> + unsigned int width_mm;
> + unsigned int height_mm;
> +
> + unsigned int bpc;
> + unsigned int lanes;
> + unsigned long mode_flags;
> + enum mipi_dsi_pixel_format format;
> +
> + const struct drm_display_mode *modes;
> + unsigned int num_modes;
> + int (*init_sequence)(struct panel_info *pinfo);
> +
> + struct drm_dsc_config dsc;
> +};
> +
> +static const struct regulator_bulk_data panel_supplies[] = {
> + { .supply = "vdd" },
> + { .supply = "vddio" },
> + { .supply = "vci" },
> + { .supply = "disp" },
> + { .supply = "blvdd" },
> +};
> +
> +static inline struct panel_info *to_panel_info(struct drm_panel *panel)
> +{
> + return container_of(panel, struct panel_info, panel);
> +}
> +
> +static int icna3512_init_sequence(struct panel_info *pinfo)
> +{
> + struct mipi_dsi_multi_context dsi_ctx = { .dsi = pinfo->dsi };
> + struct drm_dsc_picture_parameter_set pps;
> +
> + pinfo->dsi->mode_flags |= MIPI_DSI_MODE_LPM;
> +
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9C, 0xA5, 0xA5);
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xFD, 0x5A, 0x5A);
> +
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x53, 0xE0);
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x35, 0x00);
> +
> + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
> +
> + mipi_dsi_msleep(&dsi_ctx, 120);
> +
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9F, 0x0F);
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xCE, 0x22);
> +
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9F, 0x01);
> +
> + /* 165 hz */
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x48, 0x20);
> +
> + drm_dsc_pps_payload_pack(&pps, &pinfo->desc->dsc);
> + mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps);
> +
> + mipi_dsi_msleep(&dsi_ctx, 20);
> +
> + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
> +
> + return dsi_ctx.accum_err;
> +}
> +
> +static int icna3520_init_sequence(struct panel_info *pinfo)
> +{
> + struct mipi_dsi_multi_context dsi_ctx = { .dsi = pinfo->dsi };
> + struct drm_dsc_picture_parameter_set pps;
> +
> + pinfo->dsi->mode_flags |= MIPI_DSI_MODE_LPM;
> +
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9C, 0xA5, 0xA5);
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xFD, 0x5A, 0x5A);
> +
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x53, 0xE0);
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x35, 0x00);
> +
> + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
> +
> + mipi_dsi_msleep(&dsi_ctx, 120);
> +
> + /* 120 hz */
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x48, 0x00);
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9F, 0x00);
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xB3,
> + 0x00, 0xD8, 0x00, 0x1C, 0x00, 0x4C);
> +
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9F, 0x01);
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xB2, 0x00);
> +
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x9F, 0x0D);
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xB2, 0x27);
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xB6, 0x03);
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xBB, 0x01);
> + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xB2, 0x24);
> +
> + drm_dsc_pps_payload_pack(&pps, &pinfo->desc->dsc);
> + mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps);
> +
> + mipi_dsi_msleep(&dsi_ctx, 20);
> +
> + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
> +
> + return dsi_ctx.accum_err;
> +}
> +
> +static const struct drm_display_mode odin2portal_modes[] = {
> + {
> + /* 165Hz */
> + .clock = (1080 + 98 + 1 + 23) * (1920 + 20 + 1 + 15) * 165 / 1000,
> + .hdisplay = 1080,
> + .hsync_start = 1080 + 98,
> + .hsync_end = 1080 + 98 + 1,
> + .htotal = 1080 + 98 + 1 + 23,
> + .vdisplay = 1920,
> + .vsync_start = 1920 + 20,
> + .vsync_end = 1920 + 20 + 1,
> + .vtotal = 1920 + 20 + 1 + 15,
> + }
> +};
> +
> +static const struct drm_display_mode thor_top_modes[] = {
> + {
> + /* 120Hz */
> + .clock = (1080 + 24 + 1 + 24) * (1920 + 28 + 1 + 28) * 120 / 1000,
> + .hdisplay = 1080,
> + .hsync_start = 1080 + 24,
> + .hsync_end = 1080 + 24 + 1,
> + .htotal = 1080 + 24 + 1 + 24,
> + .vdisplay = 1920,
> + .vsync_start = 1920 + 28,
> + .vsync_end = 1920 + 28 + 1,
> + .vtotal = 1920 + 28 + 1 + 28,
> + }
> +};
> +
> +static struct panel_desc odin2portal_desc = {
> + .modes = odin2portal_modes,
> + .num_modes = ARRAY_SIZE(odin2portal_modes),
> + .width_mm = 160,
> + .height_mm = 89,
> + .bpc = 8,
> + .lanes = 4,
> + .format = MIPI_DSI_FMT_RGB888,
> + .mode_flags = MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_CLOCK_NON_CONTINUOUS |
> + MIPI_DSI_MODE_LPM,
> + .init_sequence = icna3512_init_sequence,
> + .dsc = {
> + .dsc_version_major = 0x1,
> + .dsc_version_minor = 0x1,
> + .slice_height = 20,
> + .slice_width = 540,
> + .slice_count = 2,
> + .bits_per_component = 8,
> + .bits_per_pixel = 8 << 4,
> + .block_pred_enable = true,
> + },
> +};
> +
> +static struct panel_desc thor_top_desc = {
> + .modes = thor_top_modes,
> + .num_modes = ARRAY_SIZE(thor_top_modes),
> + .width_mm = 136,
> + .height_mm = 68,
> + .bpc = 8,
> + .lanes = 4,
> + .format = MIPI_DSI_FMT_RGB888,
> + .mode_flags = MIPI_DSI_MODE_NO_EOT_PACKET | MIPI_DSI_CLOCK_NON_CONTINUOUS |
> + MIPI_DSI_MODE_LPM,
> + .init_sequence = icna3520_init_sequence,
> + .dsc = {
> + .dsc_version_major = 0x1,
> + .dsc_version_minor = 0x1,
> + .slice_height = 12,
> + .slice_width = 540,
> + .slice_count = 2,
> + .bits_per_component = 8,
> + .bits_per_pixel = 8 << 4,
> + .block_pred_enable = true,
> + },
> +};
> +
> +static void icna35xx_reset(struct panel_info *pinfo)
> +{
> + gpiod_set_value_cansleep(pinfo->reset_gpio, 0);
> + usleep_range(20000, 21000);
> + gpiod_set_value_cansleep(pinfo->reset_gpio, 1);
> + usleep_range(20000, 21000);
> + gpiod_set_value_cansleep(pinfo->reset_gpio, 0);
> + usleep_range(20000, 21000);
> +}
> +
> +static int icna35xx_prepare(struct drm_panel *panel)
> +{
> + struct panel_info *pinfo = to_panel_info(panel);
> + int ret;
> +
> + ret = regulator_bulk_enable(ARRAY_SIZE(panel_supplies), pinfo->supplies);
> + if (ret < 0) {
> + dev_err(panel->dev, "failed to enable regulators: %d\n", ret);
> + return ret;
> + }
> +
> + icna35xx_reset(pinfo);
> +
> + ret = pinfo->desc->init_sequence(pinfo);
> + if (ret < 0) {
> + regulator_bulk_disable(ARRAY_SIZE(panel_supplies), pinfo->supplies);
> + dev_err(panel->dev, "failed to initialize panel: %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int icna35xx_disable(struct drm_panel *panel)
> +{
> + struct panel_info *pinfo = to_panel_info(panel);
> + struct mipi_dsi_multi_context dsi_ctx = { .dsi = pinfo->dsi };
> +
> + pinfo->dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
> +
> + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
> + mipi_dsi_msleep(&dsi_ctx, 50);
> + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
> + mipi_dsi_msleep(&dsi_ctx, 120);
> +
> + return dsi_ctx.accum_err;
> +}
> +
> +static int icna35xx_unprepare(struct drm_panel *panel)
> +{
> + struct panel_info *pinfo = to_panel_info(panel);
> +
> + gpiod_set_value_cansleep(pinfo->reset_gpio, 1);
> + regulator_bulk_disable(ARRAY_SIZE(panel_supplies), pinfo->supplies);
> +
> + return 0;
> +}
> +
> +static int icna35xx_get_modes(struct drm_panel *panel,
> + struct drm_connector *connector)
> +{
> + struct panel_info *pinfo = to_panel_info(panel);
> +
> + return drm_connector_helper_get_modes_fixed(connector, pinfo->desc->modes);
> +}
> +
> +static enum drm_panel_orientation icna35xx_get_orientation(struct drm_panel *panel)
> +{
> + struct panel_info *pinfo = to_panel_info(panel);
> +
> + return pinfo->orientation;
> +}
> +
> +static const struct drm_panel_funcs icna35xx_panel_funcs = {
> + .disable = icna35xx_disable,
> + .prepare = icna35xx_prepare,
> + .unprepare = icna35xx_unprepare,
> + .get_modes = icna35xx_get_modes,
> + .get_orientation = icna35xx_get_orientation,
> +};
> +
> +static int icna35xx_bl_update_status(struct backlight_device *bl)
> +{
> + struct mipi_dsi_device *dsi = bl_get_data(bl);
> + u16 brightness = backlight_get_brightness(bl);
> + int ret;
> +
> + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
> +
> + ret = mipi_dsi_dcs_set_display_brightness_large(dsi, brightness);
> +
> + dsi->mode_flags |= MIPI_DSI_MODE_LPM;
> +
> + return ret;
> +}
> +
> +static int icna35xx_bl_get_brightness(struct backlight_device *bl)
> +{
> + struct mipi_dsi_device *dsi = bl_get_data(bl);
> + u16 brightness;
> + int ret;
> +
> + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
> +
> + ret = mipi_dsi_dcs_get_display_brightness_large(dsi, &brightness);
> +
> + dsi->mode_flags |= MIPI_DSI_MODE_LPM;
> +
> + return ret < 0 ? ret : brightness;
> +}
> +
> +static const struct backlight_ops icna35xx_bl_ops = {
> + .update_status = icna35xx_bl_update_status,
> + .get_brightness = icna35xx_bl_get_brightness,
> +};
> +
> +static struct backlight_device *icna35xx_create_backlight(struct mipi_dsi_device *dsi)
> +{
> + struct device *dev = &dsi->dev;
> + const struct backlight_properties props = {
> + .type = BACKLIGHT_RAW,
> + .brightness = 4096,
> + .max_brightness = 4096,
> + };
> +
> + return devm_backlight_device_register(dev, dev_name(dev), dev, dsi,
> + &icna35xx_bl_ops, &props);
> +}
> +
> +static int icna35xx_probe(struct mipi_dsi_device *dsi)
> +{
> + struct device *dev = &dsi->dev;
> + struct panel_info *pinfo;
> + int ret;
> +
> + pinfo = devm_drm_panel_alloc(dev, __typeof(*pinfo), panel,
> + &icna35xx_panel_funcs,
> + DRM_MODE_CONNECTOR_DSI);
> + if (IS_ERR(pinfo))
> + return PTR_ERR(pinfo);
> +
> + ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(panel_supplies),
> + panel_supplies, &pinfo->supplies);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to get regulators\n");
> +
> + pinfo->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
> + if (IS_ERR(pinfo->reset_gpio))
> + return dev_err_probe(dev, PTR_ERR(pinfo->reset_gpio), "failed to get reset gpio\n");
> +
> + pinfo->desc = (struct panel_desc *)of_device_get_match_data(dev);
> + if (!pinfo->desc)
> + return -ENODEV;
> +
> + pinfo->dsi = dsi;
> + mipi_dsi_set_drvdata(dsi, pinfo);
> +
> + ret = of_drm_get_panel_orientation(dev->of_node, &pinfo->orientation);
> + if (ret < 0) {
> + dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, ret);
> + return ret;
> + }
> +
> + pinfo->panel.prepare_prev_first = true;
> +
> + pinfo->panel.backlight = icna35xx_create_backlight(dsi);
> + if (IS_ERR(pinfo->panel.backlight))
> + return dev_err_probe(dev, PTR_ERR(pinfo->panel.backlight),
> + "Failed to create backlight\n");
> +
> + ret = devm_drm_panel_add(dev, &pinfo->panel);
> + if (ret)
> + return ret;
> +
> + pinfo->dsi->lanes = pinfo->desc->lanes;
> + pinfo->dsi->format = pinfo->desc->format;
> + pinfo->dsi->mode_flags = pinfo->desc->mode_flags;
> + pinfo->dsi->dsc = &pinfo->desc->dsc;
> +
> + return devm_mipi_dsi_attach(dev, dsi);
> +}
> +
> +static const struct of_device_id icna35xx_of_match[] = {
> + { .compatible = "ayaneo,pocketds-panel-top", .data = &odin2portal_desc },
> + { .compatible = "ayntec,odin2portal-panel", .data = &odin2portal_desc },
> + { .compatible = "ayntec,odin3-panel", .data = &thor_top_desc },
> + { .compatible = "ayntec,thor-panel-top", .data = &thor_top_desc },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, icna35xx_of_match);
> +
> +static struct mipi_dsi_driver icna35xx_driver = {
> + .probe = icna35xx_probe,
> + .driver = {
> + .name = "panel-chipone-icna35xx",
> + .of_match_table = icna35xx_of_match,
> + },
> +};
> +module_mipi_dsi_driver(icna35xx_driver);
> +
> +MODULE_AUTHOR("Teguh Sobirin <teguh@sobir.in>");
> +MODULE_DESCRIPTION("DRM driver for Chipone ICNA35XX based MIPI DSI panels");
> +MODULE_LICENSE("GPL");
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
^ permalink raw reply
* Re: [PATCH v4 1/6] dt-bindings: display: verisilicon, dc: generalize for single-output variants
From: Icenowy Zheng @ 2026-06-15 8:19 UTC (permalink / raw)
To: Joey Lu, maarten.lankhorst, mripard, tzimmermann, airlied, simona,
robh, krzk+dt, conor+dt
Cc: ychuang3, schung, yclu4, dri-devel, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <20260615065003.76661-2-a0987203069@gmail.com>
在 2026-06-15一的 14:49 +0800，Joey Lu写道：
> The existing schema hard-codes the five-clock/three-reset/dual-port
> topology of the DC8200 IP block, preventing reuse for single-output
> variants such as the Verisilicon DCUltraLite used in the Nuvoton
> MA35D1
> SoC.
>
> Rework the schema so that variant-specific constraints are expressed
> via
> allOf/if blocks:
>
> - Add nuvoton,ma35d1-dcu to the SoC-specific compatible enum. The
> generic verisilicon,dc fallback remains the driver-binding string.
> - Move clock and reset items descriptions into the per-variant
> allOf/if
> blocks; keep only minItems/maxItems at the top level so the base
> schema
> accepts all variants.
> - Restore full items lists for clock-names and reset-names at the top
> level with minItems so the names are validated against the
> descriptions.
> - Keep ports in the global required list and keep
> additionalProperties: false.
> - Add an allOf/if block for thead,th1520-dc8200: five-clock (core,
> axi,
> ahb, pix0, pix1), three-reset (core, axi, ahb), required resets.
> - Add an allOf/if block for nuvoton,ma35d1-dcu: two-clock (core,
> pix0),
> one-reset (core), required resets.
>
> Signed-off-by: Joey Lu <a0987203069@gmail.com>
> ---
> .../bindings/display/verisilicon,dc.yaml | 80
> +++++++++++++++++--
> 1 file changed, 73 insertions(+), 7 deletions(-)
>
> diff --git
> a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> index 9dc35ab973f2..0c41286b8223 100644
> --- a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> @@ -17,6 +17,7 @@ properties:
> items:
> - enum:
> - thead,th1520-dc8200
> + - nuvoton,ma35d1-dcu
> - const: verisilicon,dc # DC IPs have discoverable ID/revision
> registers
>
> reg:
> @@ -26,14 +27,12 @@ properties:
> maxItems: 1
>
> clocks:
> - items:
> - - description: DC Core clock
> - - description: DMA AXI bus clock
> - - description: Configuration AHB bus clock
> - - description: Pixel clock of output 0
> - - description: Pixel clock of output 1
Clock descriptions should still be in the global part instead of the
per-compatible part.
In the per-compatible part, clock-names should be constraint for SoCs.
> + minItems: 2
> + maxItems: 5
>
> clock-names:
> + minItems: 2
> + maxItems: 5
> items:
> - const: core
> - const: axi
> @@ -42,12 +41,16 @@ properties:
> - const: pix1
>
> resets:
> + minItems: 1
> + maxItems: 3
> items:
> - description: DC Core reset
> - description: DMA AXI bus reset
> - description: Configuration AHB bus reset
>
> reset-names:
> + minItems: 1
> + maxItems: 3
> items:
> - const: core
> - const: axi
> @@ -59,7 +62,7 @@ properties:
> properties:
> port@0:
> $ref: /schemas/graph.yaml#/properties/port
> - description: The first output channel , endpoint 0 should be
> + description: The first output channel, endpoint 0 should be
If you really want to fix this, please make it a separated patch
instead of doing it here, for commit atomicity.
Thanks,
Icenowy
> used for DPI format output and endpoint 1 should be used
> for DP format output.
>
> @@ -77,6 +80,69 @@ required:
> - clock-names
> - ports
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: thead,th1520-dc8200
> + then:
> + properties:
> + clocks:
> + minItems: 5
> + maxItems: 5
> + items:
> + - description: DC Core clock
> + - description: DMA AXI bus clock
> + - description: Configuration AHB bus clock
> + - description: Pixel clock of output 0
> + - description: Pixel clock of output 1
> +
> + clock-names:
> + minItems: 5
> + maxItems: 5
> +
> + resets:
> + minItems: 3
> + maxItems: 3
> +
> + reset-names:
> + minItems: 3
> + maxItems: 3
> +
> + required:
> + - resets
> + - reset-names
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: nuvoton,ma35d1-dcu
> + then:
> + properties:
> + clocks:
> + minItems: 2
> + maxItems: 2
> + items:
> + - description: DC Core clock
> + - description: Pixel clock of output 0
> +
> + clock-names:
> + minItems: 2
> + maxItems: 2
> +
> + resets:
> + minItems: 1
> + maxItems: 1
> +
> + reset-names:
> + maxItems: 1
> +
> + required:
> + - resets
> + - reset-names
> +
> additionalProperties: false
>
> examples:
^ permalink raw reply
* Re: [PATCH V7 4/6] drm/panel: anbernic-td4310: Add RG Vita Pro panel
From: neil.armstrong @ 2026-06-15 8:18 UTC (permalink / raw)
To: Chris Morgan, linux-rockchip
Cc: devicetree, xsf, sre, simona, airlied, tzimmermann, mripard,
maarten.lankhorst, jesszhan0024, heiko, conor+dt, krzk+dt, robh,
Chris Morgan
In-Reply-To: <20260610144407.438846-5-macroalpha82@gmail.com>
On 6/10/26 16:44, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> The panel used by Anbernic in the RG Vita-Pro is a DSI panel based
> on the TD4310 controller IC. It measures approximately 5.5 inches
> diagonally and is 1080x1920 in resolution.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> ---
> drivers/gpu/drm/panel/Kconfig | 10 +
> drivers/gpu/drm/panel/Makefile | 1 +
> drivers/gpu/drm/panel/panel-anbernic-td4310.c | 257 ++++++++++++++++++
> 3 files changed, 268 insertions(+)
> create mode 100644 drivers/gpu/drm/panel/panel-anbernic-td4310.c
>
> diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> index d592f4f4b939..61dd00297ecc 100644
> --- a/drivers/gpu/drm/panel/Kconfig
> +++ b/drivers/gpu/drm/panel/Kconfig
> @@ -17,6 +17,16 @@ config DRM_PANEL_ABT_Y030XX067A
> Y030XX067A 320x480 3.0" panel as found in the YLM RG-280M, RG-300
> and RG-99 handheld gaming consoles.
>
> +config DRM_PANEL_ANBERNIC_TD4310
> + tristate "Anbernic TD4310 LCD panel"
> + depends on GPIOLIB && OF
> + depends on DRM_MIPI_DSI
> + depends on BACKLIGHT_CLASS_DEVICE
> + help
> + Say Y here to enable support for Anbernic designed panels with the
> + TD4310 panel controller such as the ones used on the Anbernic RG
> + Vita Pro.
> +
> config DRM_PANEL_ARM_VERSATILE
> tristate "ARM Versatile panel driver"
> depends on OF
> diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> index a4291dc3905b..9d8f70c9de3e 100644
> --- a/drivers/gpu/drm/panel/Makefile
> +++ b/drivers/gpu/drm/panel/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> obj-$(CONFIG_DRM_PANEL_ABT_Y030XX067A) += panel-abt-y030xx067a.o
> +obj-$(CONFIG_DRM_PANEL_ANBERNIC_TD4310) += panel-anbernic-td4310.o
> obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
> obj-$(CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596) += panel-asus-z00t-tm5p5-n35596.o
> obj-$(CONFIG_DRM_PANEL_AUO_A030JTN01) += panel-auo-a030jtn01.o
> diff --git a/drivers/gpu/drm/panel/panel-anbernic-td4310.c b/drivers/gpu/drm/panel/panel-anbernic-td4310.c
> new file mode 100644
> index 000000000000..9a1b4525423c
> --- /dev/null
> +++ b/drivers/gpu/drm/panel/panel-anbernic-td4310.c
> @@ -0,0 +1,257 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Driver for Anbernic panels with TD4310 panel controller.
> + *
> + * Copyright (C) 2026 Chris Morgan <macromorgan@hotmail.com>
> + *
> + */
> +
> +#include <linux/gpio/consumer.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/regulator/consumer.h>
> +
> +#include <drm/drm_mipi_dsi.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_probe_helper.h>
> +
> +#include <video/mipi_display.h>
> +
> +struct anbernic_panel_td4310_info {
> + const struct drm_display_mode *display_mode;
> + u16 width_mm;
> + u16 height_mm;
> + u32 bus_flags;
> + unsigned long mode_flags;
> + u32 format;
> + u32 lanes;
> + u16 prepare_delay;
> + u16 reset_delay;
> + u16 init_delay;
> + u16 enable_delay;
> + u16 disable_delay;
> + u16 unprepare_delay;
> +};
> +
> +struct anbernic_panel_td4310 {
> + struct device *dev;
> + struct mipi_dsi_device *dsi;
> + struct drm_panel panel;
> + const struct anbernic_panel_td4310_info *panel_info;
> + struct gpio_desc *reset_gpio;
> + struct gpio_desc *enable_gpio;
> + struct regulator *vdd;
> + enum drm_panel_orientation orientation;
> +};
> +
> +static inline struct anbernic_panel_td4310 *panel_to_anbernic_panel_td4310(struct drm_panel *panel)
> +{
> + return container_of(panel, struct anbernic_panel_td4310, panel);
> +}
> +
> +static int panel_anbernic_td4310_prepare(struct drm_panel *panel)
> +{
> + struct anbernic_panel_td4310 *ctx = panel_to_anbernic_panel_td4310(panel);
> + struct mipi_dsi_device *dsi = ctx->dsi;
> + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
> + int ret;
> +
> + ret = regulator_enable(ctx->vdd);
> + if (ret)
> + return ret;
> +
> + ret = gpiod_set_value_cansleep(ctx->enable_gpio, 1);
> + if (ret)
> + goto err_enable;
> +
> + if (ctx->panel_info->enable_delay)
> + mipi_dsi_msleep(&dsi_ctx, ctx->panel_info->enable_delay);
> +
> + ret = gpiod_set_value_cansleep(ctx->reset_gpio, 1);
> + if (ret)
> + goto err_reset;
> +
> + mipi_dsi_msleep(&dsi_ctx, 10);
> +
> + ret = gpiod_set_value_cansleep(ctx->reset_gpio, 0);
> + if (ret)
> + goto err_reset;
> +
> + if (ctx->panel_info->reset_delay)
> + mipi_dsi_msleep(&dsi_ctx, ctx->panel_info->reset_delay);
> +
> + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
> + mipi_dsi_msleep(&dsi_ctx, ctx->panel_info->prepare_delay);
> + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
> + mipi_dsi_msleep(&dsi_ctx, ctx->panel_info->prepare_delay);
> +
> + if (dsi_ctx.accum_err) {
> + ret = dsi_ctx.accum_err;
> + goto err_reset;
> + }
> +
> + return 0;
> +
> +err_reset:
> + gpiod_set_value_cansleep(ctx->enable_gpio, 0);
> +err_enable:
> + regulator_disable(ctx->vdd);
> + return ret;
> +}
> +
> +static int panel_anbernic_td4310_unprepare(struct drm_panel *panel)
> +{
> + struct anbernic_panel_td4310 *ctx = panel_to_anbernic_panel_td4310(panel);
> + struct mipi_dsi_device *dsi = ctx->dsi;
> + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
> +
> + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
> + mipi_dsi_msleep(&dsi_ctx, ctx->panel_info->unprepare_delay);
> + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
> + mipi_dsi_msleep(&dsi_ctx, ctx->panel_info->disable_delay);
> +
> + gpiod_set_value_cansleep(ctx->enable_gpio, 0);
> +
> + gpiod_set_value_cansleep(ctx->reset_gpio, 1);
> +
> + regulator_disable(ctx->vdd);
> +
> + return 0;
> +}
> +
> +static int panel_anbernic_td4310_get_mode(struct drm_panel *panel,
> + struct drm_connector *connector)
> +{
> + struct anbernic_panel_td4310 *ctx = panel_to_anbernic_panel_td4310(panel);
> + const struct anbernic_panel_td4310_info *panel_info = ctx->panel_info;
> +
> + connector->display_info.bpc = 8;
> + connector->display_info.width_mm = panel_info->width_mm;
> + connector->display_info.height_mm = panel_info->height_mm;
> + connector->display_info.bus_flags = panel_info->bus_flags;
> +
> + return drm_connector_helper_get_modes_fixed(connector, panel_info->display_mode);
> +}
> +
> +static enum drm_panel_orientation panel_anbernic_td4310_get_orientation(struct drm_panel *panel)
> +{
> + struct anbernic_panel_td4310 *ctx = panel_to_anbernic_panel_td4310(panel);
> +
> + return ctx->orientation;
> +}
> +
> +static const struct drm_panel_funcs panel_anbernic_td4310_funcs = {
> + .prepare = panel_anbernic_td4310_prepare,
> + .unprepare = panel_anbernic_td4310_unprepare,
> + .get_modes = panel_anbernic_td4310_get_mode,
> + .get_orientation = panel_anbernic_td4310_get_orientation,
> +};
> +
> +static int panel_anbernic_td4310_probe(struct mipi_dsi_device *dsi)
> +{
> + struct device *dev = &dsi->dev;
> + struct anbernic_panel_td4310 *ctx;
> + int ret;
> +
> + ctx = devm_drm_panel_alloc(dev, struct anbernic_panel_td4310, panel,
> + &panel_anbernic_td4310_funcs,
> + DRM_MODE_CONNECTOR_DSI);
> + if (IS_ERR(ctx))
> + return PTR_ERR(ctx);
> +
> + ctx->dev = dev;
> +
> + ctx->panel_info = of_device_get_match_data(dev);
> + if (!ctx->panel_info)
> + return -EINVAL;
> +
> + ret = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to get panel orientation\n");
> +
> + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
> + if (IS_ERR(ctx->reset_gpio))
> + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
> + "Cannot get reset gpio\n");
> +
> + ctx->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW);
> + if (IS_ERR(ctx->enable_gpio))
> + return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio),
> + "Cannot get enable gpio\n");
> +
> + ctx->vdd = devm_regulator_get(dev, "vdd");
> + if (IS_ERR(ctx->vdd))
> + return dev_err_probe(dev, PTR_ERR(ctx->vdd),
> + "Failed to request vdd regulator\n");
> +
> + ctx->dsi = dsi;
> + mipi_dsi_set_drvdata(dsi, ctx);
> +
> + dsi->lanes = ctx->panel_info->lanes;
> + dsi->format = ctx->panel_info->format;
> + dsi->mode_flags = ctx->panel_info->mode_flags;
> +
> + ret = drm_panel_of_backlight(&ctx->panel);
> + if (ret)
> + return ret;
> +
> + devm_drm_panel_add(dev, &ctx->panel);
> +
> + ret = devm_mipi_dsi_attach(dev, dsi);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to attach to DSI host\n");
> +
> + return 0;
> +}
> +
> +static const struct drm_display_mode anbernic_vitapro_mode = {
> + .clock = 140020,
> + .hdisplay = 1080,
> + .hsync_start = 1080 + 50,
> + .hsync_end = 1080 + 50 + 4,
> + .htotal = 1080 + 50 + 4 + 50,
> + .vdisplay = 1920,
> + .vsync_start = 1920 + 15,
> + .vsync_end = 1920 + 15 + 4,
> + .vtotal = 1920 + 15 + 4 + 32,
> + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
> +};
> +
> +static const struct anbernic_panel_td4310_info anbernic_vitapro_info = {
> + .display_mode = &anbernic_vitapro_mode,
> + .width_mm = 69,
> + .height_mm = 121,
> + .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
> + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
> + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET |
> + MIPI_DSI_CLOCK_NON_CONTINUOUS,
> + .format = MIPI_DSI_FMT_RGB888,
> + .lanes = 4,
> + .prepare_delay = 50,
> + .reset_delay = 220,
> + .enable_delay = 120,
> + .disable_delay = 50,
> + .unprepare_delay = 20,
> +};
> +
> +static const struct of_device_id panel_anbernic_td4310_of_match[] = {
> + {
> + .compatible = "anbernic,panel-vita-pro",
> + .data = &anbernic_vitapro_info,
> + },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, panel_anbernic_td4310_of_match);
> +
> +static struct mipi_dsi_driver anbernic_panel_td4310_driver = {
> + .driver = {
> + .name = "panel-anbernic-td4310",
> + .of_match_table = panel_anbernic_td4310_of_match,
> + },
> + .probe = panel_anbernic_td4310_probe,
> +};
> +module_mipi_dsi_driver(anbernic_panel_td4310_driver);
> +
> +MODULE_AUTHOR("Chris Morgan <macromorgan@hotmail.com>");
> +MODULE_DESCRIPTION("DRM driver for Anbernic TD4310 MIPI DSI panels");
> +MODULE_LICENSE("GPL");
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
^ permalink raw reply
* Re: [PATCH v3 1/4] drm: panel: Add LG LH609QH1 Panel with SW49410 controller
From: Neil Armstrong @ 2026-06-15 8:18 UTC (permalink / raw)
To: Paul Sajna, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
David Airlie, Simona Vetter, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thierry Reding, Sam Ravnborg, Jessica Zhang
Cc: linux-kernel, dri-devel, devicetree, David Heidelberg,
phone-devel, Amir Dahan
In-Reply-To: <20260614-judyln-panel-v3-1-07f4134441bd@postmarketos.org>
On 6/15/26 02:07, Paul Sajna wrote:
> From: Amir Dahan <system64fumo@tuta.io>
>
> Add panel driver used by LG G7 ThinQ (judyln)
>
> Signed-off-by: Amir Dahan <system64fumo@tuta.io>
> Co-developed-by: Paul Sajna <sajattack@postmarketos.org>
> Signed-off-by: Paul Sajna <sajattack@postmarketos.org>
> ---
> drivers/gpu/drm/panel/Kconfig | 15 +
> drivers/gpu/drm/panel/Makefile | 1 +
> drivers/gpu/drm/panel/panel-lg-sw49410.c | 528 +++++++++++++++++++++++++++++++
> 3 files changed, 544 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
> index 7450b27622a2..ecf6a45224d3 100644
> --- a/drivers/gpu/drm/panel/Kconfig
> +++ b/drivers/gpu/drm/panel/Kconfig
> @@ -498,6 +498,21 @@ config DRM_PANEL_LG_SW43408
> pixel. It provides a MIPI DSI interface to the host and has a
> built-in LED backlight.
>
> +config DRM_PANEL_LG_SW49410
> + tristate "LG SW49410 panel"
> + depends on OF
> + depends on DRM_MIPI_DSI
> + depends on BACKLIGHT_CLASS_DEVICE
> + select DRM_DISPLAY_DSC_HELPER
> + select DRM_DISPLAY_HELPER
> + help
> + Say Y here if you want to enable support for LG/SiliconWorks SW49410 controller
> + (found in LG G7 ThinQ).
> + The LH609QH1 panel has a 1440x3120@60Hz resolution and uses 24 bit RGB per
> + pixel. It provides a MIPI DSI interface to the host and has a
> + built-in LED backlight.
> + To compile this driver as a module, choose M here.
> +
> config DRM_PANEL_LXD_M9189A
> tristate "LXD M9189A MIPI-DSI LCD panel"
> depends on OF
> diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
> index c2c5cf817116..153970480269 100644
> --- a/drivers/gpu/drm/panel/Makefile
> +++ b/drivers/gpu/drm/panel/Makefile
> @@ -49,6 +49,7 @@ obj-$(CONFIG_DRM_PANEL_LG_LB035Q02) += panel-lg-lb035q02.o
> obj-$(CONFIG_DRM_PANEL_LG_LD070WX3) += panel-lg-ld070wx3.o
> obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
> obj-$(CONFIG_DRM_PANEL_LG_SW43408) += panel-lg-sw43408.o
> +obj-$(CONFIG_DRM_PANEL_LG_SW49410) += panel-lg-sw49410.o
> obj-$(CONFIG_DRM_PANEL_LXD_M9189A) += panel-lxd-m9189a.o
> obj-$(CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966) += panel-magnachip-d53e6ea8966.o
> obj-$(CONFIG_DRM_PANEL_MOTOROLA_MOT) += panel-motorola-mot.o
> diff --git a/drivers/gpu/drm/panel/panel-lg-sw49410.c b/drivers/gpu/drm/panel/panel-lg-sw49410.c
> new file mode 100644
> index 000000000000..02d1b85c3aff
> --- /dev/null
> +++ b/drivers/gpu/drm/panel/panel-lg-sw49410.c
> @@ -0,0 +1,528 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +// Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree:
> +// Copyright (c) 2025, The Linux Foundation. All rights reserved.
> +
> +#include <linux/backlight.h>
> +#include <linux/delay.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/regulator/consumer.h>
> +
> +#include <video/mipi_display.h>
> +
> +#include <drm/drm_mipi_dsi.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_probe_helper.h>
> +#include <drm/display/drm_dsc.h>
> +#include <drm/display/drm_dsc_helper.h>
> +
> +static const struct regulator_bulk_data sw49410_supplies[] = {
> + { .supply = "vsp"},
> + { .supply = "vsn"},
> +};
> +
> +
Spurious empty line
> +struct sw49410_panel {
> + struct drm_panel panel;
> + struct mipi_dsi_device *dsi;
> + struct drm_dsc_config dsc;
> +
> + struct regulator_bulk_data *supplies;
> +
> + struct gpio_desc *reset_gpio;
> +};
> +
> +static inline
> +struct sw49410_panel *to_sw49410_panel(struct drm_panel *panel)
> +{
> + return container_of(panel, struct sw49410_panel, panel);
> +}
> +
> +static void sw49410_panel_reset(struct sw49410_panel *ctx)
> +{
> + gpiod_set_value(ctx->reset_gpio, 0);
> + usleep_range(9000, 10000);
> + gpiod_set_value(ctx->reset_gpio, 1);
> + usleep_range(1000, 2000);
> + gpiod_set_value(ctx->reset_gpio, 0);
> + usleep_range(9000, 10000);
> +}
> +
> +static int sw49410_panel_program(struct sw49410_panel *ctx)
> +{
> + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
> + struct drm_dsc_picture_parameter_set pps;
> +
> +
Spurious empty line
> + mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
> + mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0x0000, 0x0c2f);
> + mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x00ff);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY,
> + 0x2c);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS,
> + 0x00);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x81);
> +
> + /* Manufacturer protection */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb0, 0xac);
> +
> + /* Source Control */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb3,
> + 0x04, 0x04, 0x28, 0x08, 0x5a, 0x12, 0x23,
> + 0x02);
> +
> + /* Gate & Mux Control */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4,
> + 0x11, 0x04, 0x02, 0x02, 0x02, 0x02, 0x02,
> + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xd0,
> + 0xe4, 0xe4, 0xe4, 0x93, 0x4e, 0x39, 0x0a,
> + 0x10, 0x18, 0x25, 0x24, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00);
> +
> + /* Sync Setup */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb5,
> + 0x2e, 0x0f, 0x10, 0xc0, 0x00, 0x10, 0xc0,
> + 0x00);
> +
> + /* Panel Setting */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6,
> + 0x03, 0x05, 0x0b, 0xb3, 0x30);
> +
> + /* Touch Timing Control */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb8,
> + 0x57, 0x02, 0x90, 0x40, 0x5d, 0xd0, 0x05,
> + 0x00, 0x00, 0x18, 0x22, 0x04, 0x01, 0x02,
> + 0x90, 0x40, 0x4c, 0xc0, 0x04, 0x00, 0x00,
> + 0x18, 0x22, 0x04, 0x01, 0x08, 0x00, 0x3a,
> + 0x86, 0x83, 0x00);
> +
> + /* Touch Source Setting */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb9,
> + 0x64, 0x64, 0x2a, 0x3f, 0xee);
> +
> + /* DSC Configuration */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba,
> + 0x3d, 0x1f, 0x01, 0xff, 0x01, 0x3c, 0x1f,
> + 0x01, 0xff, 0x01, 0x00);
> +
> + /* Low Rate Refresh Setting */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbc, 0x00, 0x00, 0x00, 0x90);
> +
> + /* Black Frame Setting */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbd, 0x00, 0x00);
> +
> + /* U2 Corner Down */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbf, 0x4f, 0x02);
> +
> + /* Internal Oscillator Setting */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc0,
> + 0x00, 0x04, 0x18, 0x07, 0x11, 0x11, 0x3c,
> + 0x00, 0x0a, 0x0a);
> +
> + /* Power Control1 */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc1,
> + 0x01, 0x00, 0xf0, 0xc2, 0xcf, 0x0c);
> +
> + /* Power Control2 */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2,
> + 0xcc, 0x44, 0x44, 0x20, 0x22, 0x26, 0x21,
> + 0x00);
> +
> + /* Power Control3 */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc3,
> + 0x92, 0x11, 0x09, 0x09, 0x11, 0xcc, 0x02,
> + 0x02, 0xa4, 0xa4, 0x02, 0xa2, 0x38, 0x28,
> + 0x14, 0x40, 0x38, 0xc0);
> +
> + /* Vcom Setting */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc4, 0x26, 0x00);
> +
> + /* Power Sequence Option Configuration */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc9,
> + 0x05, 0x5d, 0x03, 0x04, 0x00);
> +
> + /* Abrupt Power Off Control */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xca, 0x9b, 0x10);
> +
> + /* LFD Control */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcb,
> + 0xf3, 0x90, 0x3d, 0x30, 0xcc);
> +
> + /* Tail TFT Setting */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcc,
> + 0x00, 0x40, 0x50, 0x90, 0x41);
> +
> + /* U2 Option */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xce, 0x00, 0x00);
> +
> + /* Gamma */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd0,
> + 0x12, 0x05, 0x20, 0x1b, 0x2c, 0x28, 0x3f,
> + 0x3d, 0x4f, 0x4f, 0x66, 0x66, 0x6e, 0x6e,
> + 0x76, 0x76, 0x80, 0x80, 0x88, 0x88, 0x95,
> + 0x95, 0x3f, 0x3f, 0xa2, 0xa2, 0x94, 0x94,
> + 0x8b, 0x8b, 0x81, 0x81, 0x75, 0x75, 0x66,
> + 0x66, 0x47, 0x47, 0x2d, 0x2d, 0x00, 0x01,
> + 0x12, 0x05, 0x20, 0x1b, 0x2c, 0x28, 0x3f,
> + 0x3d, 0x4f, 0x4f, 0x66, 0x66, 0x6e, 0x6e,
> + 0x76, 0x76, 0x80, 0x80, 0x88, 0x88, 0x95,
> + 0x95, 0x3f, 0x3f, 0xa2, 0xa2, 0x94, 0x94,
> + 0x8b, 0x8b, 0x81, 0x81, 0x75, 0x75, 0x66,
> + 0x66, 0x47, 0x47, 0x2d, 0x2d, 0x00, 0x01,
> + 0x12, 0x05, 0x20, 0x1b, 0x2c, 0x28, 0x3f,
> + 0x3d, 0x4f, 0x4f, 0x66, 0x66, 0x6e, 0x6e,
> + 0x76, 0x76, 0x80, 0x80, 0x88, 0x88, 0x95,
> + 0x95, 0x3f, 0x3f, 0xa2, 0xa2, 0x94, 0x94,
> + 0x8b, 0x8b, 0x81, 0x81, 0x75, 0x75, 0x66,
> + 0x66, 0x47, 0x47, 0x2d, 0x2d, 0x00, 0x01,
> + 0x12, 0x05, 0x20, 0x1b, 0x2c, 0x28, 0x3f,
> + 0x3d, 0x4f, 0x4f, 0x66, 0x66, 0x6e, 0x6e,
> + 0x76, 0x76, 0x80, 0x80, 0x88, 0x88, 0x94,
> + 0x94, 0x3f, 0x3f, 0xa4, 0xa4, 0x95, 0x95,
> + 0x8b, 0x8b, 0x81, 0x81, 0x75, 0x75, 0x66,
> + 0x66, 0x47, 0x47, 0x2d, 0x2d, 0x00, 0x01);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd1,
> + 0x12, 0x05, 0x20, 0x1b, 0x2e, 0x29, 0x41,
> + 0x3f, 0x52, 0x52, 0x6a, 0x6a, 0x72, 0x72,
> + 0x7a, 0x7a, 0x84, 0x84, 0x8c, 0x8c, 0x9a,
> + 0x9a, 0x3f, 0x3f, 0x9b, 0x9b, 0x8d, 0x8d,
> + 0x84, 0x84, 0x7a, 0x7a, 0x6e, 0x6e, 0x5f,
> + 0x5f, 0x41, 0x41, 0x2a, 0x2a, 0x00, 0x01,
> + 0x12, 0x05, 0x20, 0x1b, 0x2e, 0x29, 0x41,
> + 0x3f, 0x52, 0x52, 0x6a, 0x6a, 0x72, 0x72,
> + 0x7a, 0x7a, 0x84, 0x84, 0x8c, 0x8c, 0x9a,
> + 0x9a, 0x3f, 0x3f, 0x9b, 0x9b, 0x8d, 0x8d,
> + 0x84, 0x84, 0x7a, 0x7a, 0x6e, 0x6e, 0x5f,
> + 0x5f, 0x41, 0x41, 0x2a, 0x2a, 0x00, 0x01,
> + 0x12, 0x05, 0x20, 0x1b, 0x2e, 0x29, 0x41,
> + 0x3f, 0x52, 0x52, 0x6a, 0x6a, 0x72, 0x72,
> + 0x7a, 0x7a, 0x84, 0x84, 0x8c, 0x8c, 0x9a,
> + 0x9a, 0x3f, 0x3f, 0x9b, 0x9b, 0x8d, 0x8d,
> + 0x84, 0x84, 0x7a, 0x7a, 0x6e, 0x6e, 0x5f,
> + 0x5f, 0x41, 0x41, 0x2a, 0x2a, 0x00, 0x01,
> + 0x12, 0x05, 0x20, 0x1b, 0x2e, 0x29, 0x41,
> + 0x3f, 0x52, 0x52, 0x6a, 0x6a, 0x72, 0x72,
> + 0x7a, 0x7a, 0x84, 0x84, 0x8c, 0x8c, 0x9a,
> + 0x9a, 0x3f, 0x3f, 0x9b, 0x9b, 0x8d, 0x8d,
> + 0x84, 0x84, 0x7a, 0x7a, 0x6e, 0x6e, 0x5f,
> + 0x5f, 0x41, 0x41, 0x2a, 0x2a, 0x00, 0x01);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd2,
> + 0x12, 0x05, 0x20, 0x1b, 0x2f, 0x2a, 0x43,
> + 0x41, 0x55, 0x55, 0x6e, 0x6e, 0x76, 0x76,
> + 0x7e, 0x7e, 0x88, 0x88, 0x90, 0x90, 0x9f,
> + 0x9f, 0x3f, 0x3f, 0x95, 0x95, 0x86, 0x86,
> + 0x7d, 0x7d, 0x74, 0x74, 0x68, 0x68, 0x59,
> + 0x59, 0x3c, 0x3c, 0x26, 0x26, 0x00, 0x01,
> + 0x12, 0x05, 0x20, 0x1b, 0x2f, 0x2a, 0x43,
> + 0x41, 0x55, 0x55, 0x6e, 0x6e, 0x76, 0x76,
> + 0x7e, 0x7e, 0x88, 0x88, 0x90, 0x90, 0x9f,
> + 0x9f, 0x3f, 0x3f, 0x95, 0x95, 0x86, 0x86,
> + 0x7d, 0x7d, 0x74, 0x74, 0x68, 0x68, 0x59,
> + 0x59, 0x3c, 0x3c, 0x26, 0x26, 0x00, 0x01,
> + 0x12, 0x05, 0x20, 0x1b, 0x2f, 0x2a, 0x43,
> + 0x41, 0x55, 0x55, 0x6e, 0x6e, 0x76, 0x76,
> + 0x7e, 0x7e, 0x88, 0x88, 0x90, 0x90, 0x9f,
> + 0x9f, 0x3f, 0x3f, 0x95, 0x95, 0x86, 0x86,
> + 0x7d, 0x7d, 0x74, 0x74, 0x68, 0x68, 0x59,
> + 0x59, 0x3c, 0x3c, 0x26, 0x26, 0x00, 0x01,
> + 0x12, 0x05, 0x20, 0x1b, 0x2f, 0x2a, 0x43,
> + 0x41, 0x55, 0x55, 0x6e, 0x6e, 0x76, 0x76,
> + 0x7e, 0x7e, 0x88, 0x88, 0x90, 0x90, 0x9f,
> + 0x9f, 0x3f, 0x3f, 0x95, 0x95, 0x86, 0x86,
> + 0x7d, 0x7d, 0x74, 0x74, 0x68, 0x68, 0x59,
> + 0x59, 0x3c, 0x3c, 0x26, 0x26, 0x00, 0x01);
> +
> + /* MPLUS Control */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd3, 0x12, 0x01, 0x00, 0x00);
> +
> + /* MPLUS Setting */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd4,
> + 0xdc, 0x5f, 0x9c, 0xbe, 0x39, 0x39, 0x39,
> + 0x47, 0x48, 0x48, 0x48, 0x3a, 0x00, 0x03,
> + 0x6d, 0x80, 0x00, 0x00, 0x8c, 0x66, 0x00,
> + 0x00, 0x8c, 0x66, 0x00, 0x00, 0x8c, 0x66,
> + 0x00, 0x0a, 0x48, 0x80, 0x00, 0x0a, 0x48,
> + 0x80, 0x00, 0x0a, 0x48, 0x80, 0x00, 0x0a,
> + 0x48, 0x80, 0x20, 0x0a, 0x14, 0x0a, 0x18,
> + 0x00, 0x1c, 0xcc, 0x23, 0x9e, 0x23, 0x9e,
> + 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x04,
> + 0x04, 0x01, 0x00, 0x02, 0x80, 0x00, 0x10,
> + 0x00, 0x10, 0x00, 0x10, 0x13, 0x9e, 0x13,
> + 0x9e, 0x13, 0x9e, 0x13, 0x9e, 0x05, 0x05,
> + 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x23,
> + 0x9e, 0xff, 0xff, 0x13, 0x33, 0x18, 0x00,
> + 0x16, 0x66, 0x10, 0x00, 0xff, 0x01, 0x00,
> + 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05,
> + 0x00, 0x06, 0x00, 0x07, 0x00, 0x08, 0x00,
> + 0x09, 0x00, 0x0a, 0x00, 0x0b, 0x00, 0x0c,
> + 0x00, 0x0d, 0x00, 0x0e, 0x00, 0x0f, 0x00,
> + 0x1b, 0x25, 0xdc, 0x18, 0x00, 0x20, 0x00,
> + 0x1c, 0xe1, 0x00, 0xff, 0xe0, 0xc8, 0xc8,
> + 0x41, 0x8f);
> +
> + /* Notch Up Gradation */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xad,
> + 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x06,
> + 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06,
> + 0x06, 0x06, 0x20, 0x40, 0x60, 0x90, 0xc0,
> + 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff);
> +
> + /* Notch Down Gradation */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xae,
> + 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x06,
> + 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06,
> + 0x06, 0x06, 0x20, 0x40, 0x60, 0x90, 0xc0,
> + 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xff);
> +
> + /* GIP Setting */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe5,
> + 0x0b, 0x0a, 0x0c, 0x00, 0x02, 0x04, 0x06,
> + 0x08, 0x0f, 0x1b, 0x02, 0x1a, 0x1a, 0x0b,
> + 0x0a, 0x0c, 0x01, 0x03, 0x05, 0x07, 0x09,
> + 0x10, 0x1b, 0x03, 0x1a, 0x1a);
> +
> + /* Mux Setting */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6,
> + 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
> + 0x18, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16,
> + 0x17, 0x18);
> +
> + /* Test1 */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xed,
> + 0x21, 0x49, 0x00, 0x00, 0x00, 0x00);
> +
> + /* BLU Control */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x81);
> +
> + /* Sharpness */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3,
> + 0x00, 0x01, 0x00, 0x0d, 0x00);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf4,
> + 0x00, 0x00, 0x40, 0x83, 0xc5, 0x00, 0x01,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb,
> + 0x20, 0x40, 0x60, 0x80, 0xa0, 0xc0, 0xe0,
> + 0x13, 0x18, 0x18, 0x18, 0x16, 0x0d, 0x0d,
> + 0x00, 0xc7, 0xcf, 0xd8, 0xe1, 0xea, 0xf3,
> + 0xf9, 0xff);
> +
> + /* Gamma Correction */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf5, 0x00);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf6,
> + 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
> + 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf7,
> + 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
> + 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf8,
> + 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
> + 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00);
> +
> + /* BLU PWM Control */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfc,
> + 0x13, 0x70, 0xd0, 0x26, 0x30, 0x7c, 0x02,
> + 0xff, 0x12, 0x22, 0x22, 0x10, 0x00);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_ENTER_NORMAL_MODE);
> + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
> + mipi_dsi_msleep(&dsi_ctx, 135);
> +
> + /* Black frame setting */
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbd, 0x01, 0x05);
> +
> + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
> + mipi_dsi_msleep(&dsi_ctx, 50);
> +
> + ctx->dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
> +
> + drm_dsc_pps_payload_pack(&pps, &ctx->dsc);
> +
> + ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM;
> +
> + mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps);
> +
> + mipi_dsi_compression_mode_ext_multi(&dsi_ctx, true, MIPI_DSI_COMPRESSION_DSC, 1);
> +
> + return dsi_ctx.accum_err;
> +}
> +
> +static int sw49410_panel_disable(struct drm_panel *panel)
> +{
> + struct sw49410_panel *ctx = to_sw49410_panel(panel);
> + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
> +
> + ctx->dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
> +
> + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
> + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
> + mipi_dsi_msleep(&dsi_ctx, 128);
> +
> + return dsi_ctx.accum_err;
> +}
> +
> +static int sw49410_panel_prepare(struct drm_panel *panel)
> +{
> + struct sw49410_panel *ctx = to_sw49410_panel(panel);
> + int ret;
> +
> + ret = regulator_bulk_enable(ARRAY_SIZE(sw49410_supplies), ctx->supplies);
> + if (ret < 0)
> + return ret;
> +
> + usleep_range(5000, 6000);
> +
> + sw49410_panel_reset(ctx);
> +
> + ret = sw49410_panel_program(ctx);
> + if (ret)
> + goto poweroff;
> +
> + return 0;
> +
> +poweroff:
> + gpiod_set_value(ctx->reset_gpio, 1);
> + regulator_bulk_disable(ARRAY_SIZE(sw49410_supplies), ctx->supplies);
> + return ret;
> +}
> +
> +static int sw49410_panel_unprepare(struct drm_panel *panel)
> +{
> + struct sw49410_panel *ctx = to_sw49410_panel(panel);
> +
> + gpiod_set_value(ctx->reset_gpio, 1);
> + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
> +
> + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
> + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
> + mipi_dsi_msleep(&dsi_ctx, 100);
> +
> + gpiod_set_value(ctx->reset_gpio, 1);
> +
> + regulator_bulk_disable(ARRAY_SIZE(sw49410_supplies), ctx->supplies);
> +
> + return dsi_ctx.accum_err;
> +}
> +
> +static const struct drm_display_mode sw49410_panel_mode = {
> + .clock = (1440 + 168 + 4 + 84) * (3120 + 2 + 18 + 18) * 60 / 1000,
> + .hdisplay = 1440,
> + .hsync_start = 1440 + 168,
> + .hsync_end = 1440 + 168 + 4,
> + .htotal = 1440 + 168 + 4 + 84,
> + .vdisplay = 3120,
> + .vsync_start = 3120 + 2,
> + .vsync_end = 3120 + 2 + 18,
> + .vtotal = 3120 + 2 + 18 + 18,
> + .width_mm = 65,
> + .height_mm = 140,
> + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
> +};
> +
> +static int sw49410_panel_get_modes(struct drm_panel *panel, struct drm_connector *connector)
> +{
> + return drm_connector_helper_get_modes_fixed(connector, &sw49410_panel_mode);
> +}
> +
> +static const struct drm_panel_funcs sw49410_panel_funcs = {
> + .disable = sw49410_panel_disable,
> + .prepare = sw49410_panel_prepare,
> + .unprepare = sw49410_panel_unprepare,
> + .get_modes = sw49410_panel_get_modes,
> +};
> +
> +static int sw49410_panel_probe(struct mipi_dsi_device *dsi)
> +{
> + struct device *dev = &dsi->dev;
> + struct sw49410_panel *ctx;
> + int ret;
> +
> + ctx = devm_drm_panel_alloc(&dsi->dev, __typeof(*ctx), panel,
> + &sw49410_panel_funcs, DRM_MODE_CONNECTOR_DSI);
> +
Spurious empty line
> + if (IS_ERR(ctx))
> + return PTR_ERR(ctx);
> +
> + ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(sw49410_supplies),
> + sw49410_supplies,
> + &ctx->supplies
> + );
Alignment is wrong, it should be:
ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(sw49410_supplies),
sw49410_supplies, &ctx->supplies);
> +
Spurious empty line
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to get regulators\n");
> +
> + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
> + if (IS_ERR(ctx->reset_gpio))
> + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
> + "Failed to get reset-gpios\n");
> +
> + ctx->dsi = dsi;
> + mipi_dsi_set_drvdata(dsi, ctx);
> +
> + dsi->lanes = 4;
> + dsi->format = MIPI_DSI_FMT_RGB888;
> + dsi->mode_flags = MIPI_DSI_MODE_VIDEO_BURST |
> + MIPI_DSI_CLOCK_NON_CONTINUOUS;
> +
> + ctx->panel.prepare_prev_first = true;
> +
> + ret = drm_panel_of_backlight(&ctx->panel);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to get backlight\n");
> +
> + drm_panel_add(&ctx->panel);
Use the devm variant
> +
> + /* This panel only supports DSC; unconditionally enable it */
> + dsi->dsc = &ctx->dsc;
> +
> + ctx->dsc.dsc_version_major = 1;
> + ctx->dsc.dsc_version_minor = 1;
> +
> + ctx->dsc.slice_height = 60;
> + ctx->dsc.slice_width = 720;
> +
> + WARN_ON(1440 % ctx->dsc.slice_width);
> + ctx->dsc.slice_count = 1440 / ctx->dsc.slice_width;
> + ctx->dsc.bits_per_component = 8;
> + ctx->dsc.bits_per_pixel = 8 << 4; /* 4 fractional bits */
> + ctx->dsc.block_pred_enable = true;
> +
> + return mipi_dsi_attach(dsi);
Use the devm variant
> +}
> +
> +static void sw49410_panel_remove(struct mipi_dsi_device *dsi)
> +{
> + struct sw49410_panel *ctx = mipi_dsi_get_drvdata(dsi);
> + int ret;
> +
> + ret = mipi_dsi_detach(dsi);
> + if (ret < 0)
> + dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
> +
> + drm_panel_remove(&ctx->panel);
> +}
Drop the remove after switching to the devm_ variants.
> +
> +static const struct of_device_id sw49410_of_match[] = {
> + { .compatible = "lg,sw49410" },
> + { .compatible = "lg,sw49410-lh609qh1" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, sw49410_of_match);
> +
> +static struct mipi_dsi_driver sw49410_panel_driver = {
> + .driver = {
> + .name = "panel-lg-sw49410",
> + .of_match_table = sw49410_of_match,
> + },
> + .probe = sw49410_panel_probe,
> + .remove = sw49410_panel_remove,
> +};
> +module_mipi_dsi_driver(sw49410_panel_driver);
> +
> +MODULE_AUTHOR("Amir Dahan <system64fumo@tuta.io>");
> +MODULE_DESCRIPTION("DRM driver for LG DSI Panel with SW49410 controller");
> +MODULE_LICENSE("GPL");
>
Thanks,
Neil
^ permalink raw reply
* Re: [PATCH 5/5] MAINTAINERS: Add entry for Samsung Exynos8855 SoC
From: Krzysztof Kozlowski @ 2026-06-15 8:16 UTC (permalink / raw)
To: Alim Akhtar, 'Linus Walleij'
Cc: peter.griffin, robh, conor+dt, linux-samsung-soc, linux-kernel,
devicetree, linux-gpio, hajun.sung
In-Reply-To: <0aa74645-d99d-4776-b3e6-e74fc0528f11@kernel.org>
On 15/06/2026 10:12, Krzysztof Kozlowski wrote:
> On 15/06/2026 10:04, Alim Akhtar wrote:
>> Thanks Linus for your review
>>
>>> -----Original Message-----
>>> From: Linus Walleij <linusw@kernel.org>
>>> Sent: Monday, June 15, 2026 12:51 PM
>>> To: Alim Akhtar <alim.akhtar@samsung.com>
>>> Cc: krzk@kernel.org; peter.griffin@linaro.org; robh@kernel.org;
>>> conor+dt@kernel.org; linux-samsung-soc@vger.kernel.org; linux-
>>> kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-
>>> gpio@vger.kernel.org; hajun.sung@samsung.com
>>> Subject: Re: [PATCH 5/5] MAINTAINERS: Add entry for Samsung Exynos8855
>>> SoC
>>>
>>> Hi Alim,
>>>
>>> On Fri, Jun 12, 2026 at 6:11 PM Alim Akhtar <alim.akhtar@samsung.com>
>>> wrote:
>>>
>>>> Add maintainers entry for the Samsung Exynos8855 SoC based platforms
>>>>
>>>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>>> (...)
>>>> +SAMSUNG EXYNOS8855 SoC SUPPORT
>>>> +M: Alim Akhtar <alim.akhtar@samsung.com>
>>>> +L: linux-arm-kernel@lists.infradead.org (moderated for non-
>>> subscribers)
>>>> +L: linux-samsung-soc@vger.kernel.org
>>>> +S: Maintained
>>>> +F: arch/arm64/boot/dts/exynos/exynos8855*
>>>
>>> If you really want to single out a single platform like this (and I don't even
>>> know if that is a good idea... how do you keep the big picture in mind?) you
>>> should probably want to also add a wildcard for all the
>>> 8855 device tree files.
>>>
>> I am also not sure, just followed what was done historically, other Exynos8855 file will get added once they
>> are posted for review, e.g. clock driver.
>> Let me discuss with Krzk during OSS (Mumbai) and see how do we handle this or any other better ways.
>>
>
> You are Alim already reviewer for entire Samsung, so not sure if this is
> beneficial but I also do not mind.
>
> For Exynos850 and Google GS101, these were added because folks wanted to
> be involved in these specific bits. In the past I was voting for per-DTS
> file maintainer entry and rejecting per-board maintainer entries. There
Lemme clarify: "voting for in-DTS file maintainer entry", so like we
have for DT bindings, which lists maintainers.
> was even get_maintainers.pl patch doing that. Unfortunately after many
> tries that patch eventually did not land and I got bored bringing it up,
> thus I agreed to earlier NXP approach for per-board or per-SoC maintainers.
>
> I would like to encourage more people doing meaningful reviews, so if
> having maintainers entry helps that, then I am in.
>
> Therefore I am fine with this patch as is.
>
> Best regards,
> Krzysztof
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v7 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle
From: Neeraj Soni @ 2026-06-15 8:16 UTC (permalink / raw)
To: Krzysztof Kozlowski, Kuldeep Singh, ulf.hansson, robh, krzk+dt,
conor+dt, andersson, konradybcio
Cc: linux-mmc, devicetree, linux-kernel, Abel Vesa, Abhinaba Rakshit
In-Reply-To: <432f3a3b-3d28-4130-9a9c-61be04eade1d@oss.qualcomm.com>
On 6/15/2026 10:15 AM, Krzysztof Kozlowski wrote:
> On 13/06/2026 07:21, Neeraj Soni wrote:
>>
>>
>> On 6/9/2026 5:19 PM, Krzysztof Kozlowski wrote:
>>> On 09/06/2026 10:18, Neeraj Soni wrote:
>>>>
>>>>
>>>> On 6/8/2026 11:40 AM, Kuldeep Singh wrote:
>>>>> On 08-06-2026 09:46, Neeraj Soni wrote:
>>>>>> Starting with sc7280(kodiak), the ICE will have its own device-tree node.
>>>>>> So add the qcom,ice property to reference it.
>>>>>>
>>>>>> To avoid double-modeling, when qcom,ice is present, disallow an embedded
>>>>>> ICE register region in the SDHCI node. Older SoCs without ICE remain
>>>>>> valid as no additional requirement is imposed.
>>>>>>
>>>>>> Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
>>>>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
>>>>>> Co-developed-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
>>>>>> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
>>>>>> Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
>>>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>>>>>> Link: https://lore.kernel.org/r/20260310113557.348502-2-neeraj.soni@oss.qualcomm.com
>>>>>> Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
>>>>>
>>>>> Link should go below "---" to specify previous discussions.
>>>>>
>>>>> Usually maintainers add link of patchset being merged here while merging
>>>>> changes in their tree but authors don't add it here.
>>>>>
>>>> Do not see any such restrictions here https://www.kernel.org/doc/html/latest/process/submitting-patches.html
>>>
>>> What do you provide that Link for? What does it bring?
>>>
>> Kuleep highlighted a concern with the usage of "Link:" tag. The link i
>> provided guides on posting patches to upstream linux. Wanted to highlight
>> what i folloed and I did not find any specific comment/line in the guide
>> which prohibits author to use "Link:" tag in trailer section. If there
>
> This is reversed logic. You need to provide reasons WHY it is worth, not
> just claim it is not disallowed. Adding 100 Links to whatever website is
> not disallowed, so you are going to add them?
>
Ack. I understand your point on Author's responsibility.
>> are guidelines otherwise please let me know and i will correct and post
>> new patch.
>
> The "Link:", not the URL itself. What does it bring? Linus made clear
> statement that you should not add links UNLESS you have a reason.
>
> So please share the reason. If you do not have, DO NOT ADD any "Link:".
>
Ack. The purpose was to only highlight what was reviewed but i understand
it was not necessary. I will fix and post v8.
> Best regards,
> Krzysztof
>
Regards
Neeraj
^ permalink raw reply
* Re: [PATCH 5/5] MAINTAINERS: Add entry for Samsung Exynos8855 SoC
From: Krzysztof Kozlowski @ 2026-06-15 8:12 UTC (permalink / raw)
To: Alim Akhtar, 'Linus Walleij'
Cc: peter.griffin, robh, conor+dt, linux-samsung-soc, linux-kernel,
devicetree, linux-gpio, hajun.sung
In-Reply-To: <007a01dcfc9d$aa94dd60$ffbe9820$@samsung.com>
On 15/06/2026 10:04, Alim Akhtar wrote:
> Thanks Linus for your review
>
>> -----Original Message-----
>> From: Linus Walleij <linusw@kernel.org>
>> Sent: Monday, June 15, 2026 12:51 PM
>> To: Alim Akhtar <alim.akhtar@samsung.com>
>> Cc: krzk@kernel.org; peter.griffin@linaro.org; robh@kernel.org;
>> conor+dt@kernel.org; linux-samsung-soc@vger.kernel.org; linux-
>> kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-
>> gpio@vger.kernel.org; hajun.sung@samsung.com
>> Subject: Re: [PATCH 5/5] MAINTAINERS: Add entry for Samsung Exynos8855
>> SoC
>>
>> Hi Alim,
>>
>> On Fri, Jun 12, 2026 at 6:11 PM Alim Akhtar <alim.akhtar@samsung.com>
>> wrote:
>>
>>> Add maintainers entry for the Samsung Exynos8855 SoC based platforms
>>>
>>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> (...)
>>> +SAMSUNG EXYNOS8855 SoC SUPPORT
>>> +M: Alim Akhtar <alim.akhtar@samsung.com>
>>> +L: linux-arm-kernel@lists.infradead.org (moderated for non-
>> subscribers)
>>> +L: linux-samsung-soc@vger.kernel.org
>>> +S: Maintained
>>> +F: arch/arm64/boot/dts/exynos/exynos8855*
>>
>> If you really want to single out a single platform like this (and I don't even
>> know if that is a good idea... how do you keep the big picture in mind?) you
>> should probably want to also add a wildcard for all the
>> 8855 device tree files.
>>
> I am also not sure, just followed what was done historically, other Exynos8855 file will get added once they
> are posted for review, e.g. clock driver.
> Let me discuss with Krzk during OSS (Mumbai) and see how do we handle this or any other better ways.
>
You are Alim already reviewer for entire Samsung, so not sure if this is
beneficial but I also do not mind.
For Exynos850 and Google GS101, these were added because folks wanted to
be involved in these specific bits. In the past I was voting for per-DTS
file maintainer entry and rejecting per-board maintainer entries. There
was even get_maintainers.pl patch doing that. Unfortunately after many
tries that patch eventually did not land and I got bored bringing it up,
thus I agreed to earlier NXP approach for per-board or per-SoC maintainers.
I would like to encourage more people doing meaningful reviews, so if
having maintainers entry helps that, then I am in.
Therefore I am fine with this patch as is.
Best regards,
Krzysztof
^ permalink raw reply
* RE: [PATCH 5/5] MAINTAINERS: Add entry for Samsung Exynos8855 SoC
From: Alim Akhtar @ 2026-06-15 8:04 UTC (permalink / raw)
To: 'Linus Walleij'
Cc: krzk, peter.griffin, robh, conor+dt, linux-samsung-soc,
linux-kernel, devicetree, linux-gpio, hajun.sung
In-Reply-To: <CAD++jL=mQUJCqVyqK746UdkZCsO+2oeO1MCQM4F-_pSOfpuQuA@mail.gmail.com>
Thanks Linus for your review
> -----Original Message-----
> From: Linus Walleij <linusw@kernel.org>
> Sent: Monday, June 15, 2026 12:51 PM
> To: Alim Akhtar <alim.akhtar@samsung.com>
> Cc: krzk@kernel.org; peter.griffin@linaro.org; robh@kernel.org;
> conor+dt@kernel.org; linux-samsung-soc@vger.kernel.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-
> gpio@vger.kernel.org; hajun.sung@samsung.com
> Subject: Re: [PATCH 5/5] MAINTAINERS: Add entry for Samsung Exynos8855
> SoC
>
> Hi Alim,
>
> On Fri, Jun 12, 2026 at 6:11 PM Alim Akhtar <alim.akhtar@samsung.com>
> wrote:
>
> > Add maintainers entry for the Samsung Exynos8855 SoC based platforms
> >
> > Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> (...)
> > +SAMSUNG EXYNOS8855 SoC SUPPORT
> > +M: Alim Akhtar <alim.akhtar@samsung.com>
> > +L: linux-arm-kernel@lists.infradead.org (moderated for non-
> subscribers)
> > +L: linux-samsung-soc@vger.kernel.org
> > +S: Maintained
> > +F: arch/arm64/boot/dts/exynos/exynos8855*
>
> If you really want to single out a single platform like this (and I don't even
> know if that is a good idea... how do you keep the big picture in mind?) you
> should probably want to also add a wildcard for all the
> 8855 device tree files.
>
I am also not sure, just followed what was done historically, other Exynos8855 file will get added once they
are posted for review, e.g. clock driver.
Let me discuss with Krzk during OSS (Mumbai) and see how do we handle this or any other better ways.
> Yours,
> Linus Walleij
^ permalink raw reply
* Re: [PATCH v11 4/6] arm64: dts: qcom: kodiak: Add OPP-table for ICE UFS and ICE eMMC nodes
From: Abhinaba Rakshit @ 2026-06-15 8:03 UTC (permalink / raw)
To: Kuldeep Singh
Cc: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neeraj Soni, Harshal Dev, linux-arm-msm, linux-kernel, linux-scsi,
linux-mmc, devicetree
In-Reply-To: <184dfbd2-4781-4dc2-9165-66b3617bde0e@oss.qualcomm.com>
On Thu, Jun 11, 2026 at 05:42:10PM +0530, Kuldeep Singh wrote:
> On 09-06-2026 03:17, Abhinaba Rakshit wrote:
> > Qualcomm Inline Crypto Engine (ICE) platform driver now, supports
> > an optional OPP-table.
> >
> > Add OPP-table for ICE UFS and ICE eMMC device nodes for Kodiak
> > platform.
>
> s/eMMC/sdhc
>
> >
> > Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/kodiak.dtsi | 42 ++++++++++++++++++++++++++++++++++++
> > 1 file changed, 42 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> > index ecf4790f3415c46781c8e790d7892a41300ee7a0..cd76da7e49d8c664df6a60b5c18418c4e97a3ba4 100644
> > --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
> > @@ -1087,6 +1087,27 @@ sdhc_ice: crypto@7c8000 {
> > clock-names = "core",
> > "iface";
> > power-domains = <&rpmhpd SC7280_CX>;
> > +
> > + operating-points-v2 = <&ice_mmc_opp_table>;
>
> To align with sdhc_ice(as label name), can we rename to ice_sdhc_opp_table?
Do you mean sdhc_ice_opp_table?
Abhinaba Rakshit
^ permalink raw reply
* Re: [PATCH 0/3] ARM: dts: stm32: lxa: change stdout-path baud rate from 9600 to 115200
From: Ahmad Fatoum @ 2026-06-15 7:53 UTC (permalink / raw)
To: David Laight
Cc: Alexandre Torgue, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Leonard Göhrs,
Marc Kleine-Budde, Alexandre Torgue, devicetree, linux-stm32,
linux-arm-kernel, linux-kernel, kernel
In-Reply-To: <20260612075342.6615d66c@pumpkin>
Hello David,
On 6/12/26 8:53 AM, David Laight wrote:
> On Thu, 11 Jun 2026 22:33:18 +0200
> Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
>
>> Hi David,
>>
>> On 6/11/26 21:43, David Laight wrote:
>>> On Thu, 11 Jun 2026 20:12:32 +0200
>>> Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
>>>
>>>> The LXA boards are the only STM32 boards that set stdout-path = &uart*
>>>> instead of explicitly specifying a baud rate.
>>>>
>>>> This would mean the default of 9600 is used, but it goes unnoticed when
>>>> booting normally as barebox fixes up a console= line that includes a
>>>> baud rate.
>>>>
>>>> When EFI booting GRUB however, GRUB will not pass along the console=
>>>> line and thus the board ends up with a 9600 baud Linux console,
>>>> confusing users.
>>>
>>> Is it possible to determine the current baud rate (by reading the hardware
>>> register) and default to that value.
>>> Then if grub has initialised the uart the kernel will use the same
>>> baud rate.
>>
>> I think so, yes. In addition to the register divider configuration, one
>> would need the input clock rate as well, but that's not a problem.
>>
>> Do you know if any drivers already do this?
>
> I've seen it done somewhere, certainly x86, but possibly NetBSD.
> That would have been preserving the baud rate set by the bios.
> You don't want the baud rate changing half way through the boot sequence.
I agree in general, but in this case here, the BIOS defaults to 115200:
https://github.com/linux-automation/meta-lxatac/blob/wrynose/meta-lxatac-bsp/recipes-bsp/barebox/files/lxatac/defconfig#L171
https://elixir.bootlin.com/barebox/v2026.06.0/source/common/console.c#L349
Cheers,
Ahmad
>
> David
>
>>
>> Nevertheless, I would like the LXA device trees changed, even if only
>> to align them with all other existing STM32 device trees.
>>
>> Cheers,
>> Ahmad
>>
>>
>>>
>>> David
>>>
>>>>
>>>> This series fixes this. As the device trees were added at different
>>>> times, they are fixed each in a separate commit with its own Fixes: tag.
>>>>
>>>> ---
>>>> Ahmad Fatoum (3):
>>>> ARM: dts: stm32: lxa-mc1: change stdout-path baud rate from 9600 to 115200
>>>> ARM: dts: stm32: lxa-tac: change stdout-path baud rate from 9600 to 115200
>>>> ARM: dts: stm32: fairytux2: change stdout-path baud rate from 9600 to 115200
>>>>
>>>> arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi | 2 +-
>>>> arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts | 2 +-
>>>> arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi | 2 +-
>>>> 3 files changed, 3 insertions(+), 3 deletions(-)
>>>> ---
>>>> base-commit: 4549871118cf616eecdd2d939f78e3b9e1dddc48
>>>> change-id: 20260611-lxa-stdout-path-baudrate-7cf454cdae07
>>>>
>>>> Best regards,
>>>> --
>>>> Ahmad Fatoum <a.fatoum@pengutronix.de>
>>>>
>>>>
>>>
>>>
>>
>>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* Re: [PATCH V1 1/2] arm64: dts: qcom: Add SD Card support for Shikra SoC
From: Monish Chunara @ 2026-06-15 7:39 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, Wesley Cheng,
Ulf Hansson, Kernel Team, linux-arm-msm, devicetree, linux-kernel,
linux-phy, linux-mmc, Nitin Rawat, Pradeep Pragallapati,
Komal Bajaj, Konrad Dybcio
In-Reply-To: <gq54nr2bzvvqkocphvkji7g7rhbsrngsno7gvsfl4nsfvakj2a@wsfsnohrnscm>
On Thu, Jun 04, 2026 at 04:49:59PM +0300, Dmitry Baryshkov wrote:
> On Thu, Jun 04, 2026 at 05:50:44PM +0530, Monish Chunara wrote:
> > Add support for SD card on Shikra SoC and enable the required pinctrl
> > configurations.
> >
> > Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/shikra.dtsi | 93 ++++++++++++++++++++++++++++
> > 1 file changed, 93 insertions(+)
> >
> > + clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> > + <&gcc GCC_SDCC2_APPS_CLK>,
> > + <&rpmcc RPM_SMD_XO_CLK_SRC>;
>
> Misaligned
ACK
>
> > + clock-names = "iface", "core", "xo";
>
> One perline
ACK
>
> > +
> > + qcom,dll-config = <0x0007442c>;
> > + qcom,ddr-config = <0x80040868>;
> > +
> > + iommus = <&apps_smmu 0x0a0 0x0>;
> > +
> > + interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG
> > + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
>
> Misaligned, make sure that ampersands are at the same column.
>
ACK, thanks for pointing out.
> > + <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
Regards,
Monish
^ permalink raw reply
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