* Re: [RFC 00/12] RFC: Devicetree-ACPI hybrid mode
From: Sudeep Holla @ 2026-06-27 14:12 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Hans de Goede, Sudeep Holla, Rafael J . Wysocki, Bjorn Andersson,
Konrad Dybcio, Srinivas Kandagatla, Krzysztof Kozlowski,
Dmitry Baryshkov, Bartosz Golaszewski, Abel Vesa, linux-arm-msm,
devicetree, linux-acpi
In-Reply-To: <obvpvyx3kmzcdc5nxmx4inlpiqugjxdgzfzmdxzfqqy4qqwt7l@y2zyrtso6yk4>
On Fri, Jun 26, 2026 at 11:57:47PM +0300, Dmitry Baryshkov wrote:
> On Fri, Jun 26, 2026 at 04:52:41PM +0100, Sudeep Holla wrote:
> > On Tue, Jun 23, 2026 at 04:52:13PM +0200, Hans de Goede wrote:
> > > Hi All,
> > >
> > > Currently as soon as the kernel boots with a populated DT provided then
> > > the arch/arm64 code sets acpi_disabled=1 and the complete ACPI subsystem
> > > gets disabled. On WoA Snapdragon laptops where the factory Windows OS
> > > actually boots using these tables this is not necessarily desirable.
> > >
> >
> > I am bit lost reading the very first statement here.
> >
> > Who is populating DT and why ? It seems that is the source of the problem.
> >
> > If windows can boot with ACPI tables, why is it causing issues for the
> > Linux kernel, any specifics?
>
> Windows uses a separate beast called PEP, which nobody wanted to
> implement for these platforms up to now. You can find a lot of ACPI
> dumps for these devices at [1].
>
Agreed and I assume that is the reason why we want DT.
> > IOW why is DT populated which creates the problem you are trying to address
> > here.
>
> Most of the laptops resemble other Qualcomm platforms, which use DT for
> hardware description. In some cases, it is the same platform being used
> for both mobile, IoT and laptops. It was more or less natural to reuse
> existing support.
>
Sure, just use DT then, why are we even talking about mixed/hybrid mode.
It gives no incentive to OEMs using PEP to get away from it and use
standard ACPI or improve if anything is missing.
So I don't like this idea of mixing at all. Use ACPI or DT, make up you
mind. You can't expect to get the best of both worlds if you are not improving
the missing parts in either of those. This is just a shortcut.
--
Regards,
Sudeep
^ permalink raw reply
* Re: [PATCH RFC v7 0/9] firmware: arm_scmi: vendors: Qualcomm Generic Vendor Extensions
From: Sudeep Holla @ 2026-06-27 14:13 UTC (permalink / raw)
To: Pragnesh Papaniya
Cc: Cristian Marussi, Sudeep Holla, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, MyungJoo Ham, Kyungmin Park,
Chanwoo Choi, Dmitry Osipenko, Thierry Reding, Jonathan Hunter,
Bjorn Andersson, Konrad Dybcio, Rajendra Nayak, Pankaj Patil,
linux-arm-msm, linux-kernel, arm-scmi, linux-arm-kernel,
devicetree, linux-pm, linux-tegra, Amir Vajid,
Ramakrishna Gottimukkula
In-Reply-To: <ea9d0c11-e110-4d13-b165-1548875ef9cd@oss.qualcomm.com>
On Thu, Jun 25, 2026 at 10:57:40AM +0530, Pragnesh Papaniya wrote:
>
>
> On 23-Jun-26 2:17 PM, Sudeep Holla wrote:
> > On Fri, Jun 19, 2026 at 06:01:23PM +0530, Pragnesh Papaniya wrote:
> >>
> >> On 16-Jun-26 1:57 PM, Sudeep Holla wrote:
> >>
> >>> Not sure if it was discussed in the previous versions or not, it would be
> >>> good if you can capture why some of bus scaling doesn't work with the existing
> >>> SCMI performance protocol and the monitors don't fit the MPAM mode.
> >>>
> >>> Please capture them in 1/9 as a motivation for this vendor protocol. It will
> >>> then help to understand it better as I am still struggling to. Sorry for that.
> >>
> >> Thanks for the input!
> >>
> >> SCMI perf protocol exports perf domains to kernel where kernel can set
> >> the frequency but here the scaling governor runs on the SCP while kernel
> >> just observes frequency changes made by remote governor.
> >
> > OK if it is sort of read-only w.r.t kernel, why not perf domain notifications
> > work to consume the change done by the SCMI platform.
> >
> > And why do you have set operations in the vendor protocol being proposed then.
> > It all looks like something just cooked up to make things work. I need
> > detailed reasoning as why the existing perf protocol can't work considering
> > all the existing notifications in place.
>
> Please do take another look at the documentation and driver changes to see
> how it all comes together, since it's apparent that we use SET operation for
> a ton of things. Taking another stab at explaining how the MEMLAT uses all
> the ops exposed by the vendor protocol.
>
Sure I will have a look at the documentation again and sorry if I missed
anything. But in general I would expect the document to be self-explanatory
and not having to look at the driver on how it is used to understand the
firmware interface. Please make sure of that if not already.
> We use the SET operation to pass on various tuneables (IPM CEIL, stall floors,
> write-back filter, freq-scale params, adaptive low/high freq, sample ms),
> the core-freq -> mem-freq map, and min/max clamps) required to run the
> MEMLAT algorithm on the SCP. You might ask why can't we have these values
> stored somewhere on the SCP itself?
Exactly, thanks for saving a round trip.
> We would like to but all of these are tuneable values, that can change for
> various boards for the same SoC.
>
Sure and where do these boards get these values from ? I assume device tree ?
If so, are the fixed and can be done once at boot ?
> The START/STOP operations are meant to start/stop the algorithm, in this case
> the bus scaling algorithm.
>
Yes you need to add more details on that algorithm. Can firmware take random
strings as input. I guess not. Please list the valid strings and explain them.
Filter invalid strings in the driver if only handful of values are valid.
> We use the GET operation to get the current frequency of memory that we
> are trying to scale. It can be also used to read back all the parameters
> that we are trying to set. Another thing to note is that exposing the current
> frequency to the userspace was something that the community wanted.
>
More fun, user ABI involved, so the firmware interface needs to be as clear
as possible.
> With all of ^^ in mind, re-using the perf protocol becomes impossible.
>
> https://lore.kernel.org/lkml/k4lpzxtrq3x6riyv6etxiobn7nbpczf2bp3m4oc752nhjknlit@uo53kbppzim7/
> https://lore.kernel.org/lkml/20241115003809epcms1p518df149458f3023d33ec6d87a315e8f6@epcms1p5/
>
It is good to capture summary of these old discussions if they are relevant.
> We'll add more call flow diagrams as part of the documentation for the next
> re-spin to make reviews a bit more easier.
>
Anything that improves and helps in understanding this is always welcome.
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH v2 0/3] Add support for Variscite DART-MX8M-MINI and Sonata board
From: Stefano Radaelli @ 2026-06-27 14:46 UTC (permalink / raw)
To: linux-kernel, devicetree, imx, linux-arm-kernel
Cc: pierluigi.p, Stefano Radaelli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shawn Guo, Daniel Baluta, Josua Mayer,
Dario Binacchi, Alexander Stein, Ernest Van Hoecke,
Maud Spierings, Francesco Dolcini, Hugo Villeneuve
This patch series adds support for the Variscite DART-MX8M-MINI
system on module and the Sonata carrier board.
The series includes:
- SOM device tree with on-module peripherals
- Sonata carrier board device tree with board-specific features
The implementation follows the standard SOM + carrier board pattern
where the SOM dtsi contains only peripherals mounted on the module,
while carrier-specific interfaces are enabled in the board dts.
v1->v2:
- Remove HDMI from commit message
- Fixed eth regulator
Stefano Radaelli (3):
dt-bindings: arm: fsl: add Variscite DART-MX8M-MINI Boards
arm64: dts: freescale: Add support for Variscite DART-MX8M-MINI
arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board
.../devicetree/bindings/arm/fsl.yaml | 6 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx8mm-var-dart-sonata.dts | 517 ++++++++++++++++
.../boot/dts/freescale/imx8mm-var-dart.dtsi | 558 ++++++++++++++++++
4 files changed, 1082 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi
base-commit: 23a7098c710673ce8f245af317903ae46325a694
--
2.47.3
^ permalink raw reply
* [PATCH v2 1/3] dt-bindings: arm: fsl: add Variscite DART-MX8M-MINI Boards
From: Stefano Radaelli @ 2026-06-27 14:46 UTC (permalink / raw)
To: linux-kernel, devicetree, imx, linux-arm-kernel
Cc: pierluigi.p, Stefano Radaelli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shawn Guo, Daniel Baluta, Josua Mayer,
Dario Binacchi, Alexander Stein, Ernest Van Hoecke,
Maud Spierings, Francesco Dolcini, Hugo Villeneuve,
Krzysztof Kozlowski
In-Reply-To: <cover.1782571383.git.stefano.r@variscite.com>
From: Stefano Radaelli <stefano.r@variscite.com>
Add DT compatible strings for Variscite DART-MX8MM SoM and Variscite
development carrier Board.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
v1->v2:
-
Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 86876311ec59..c942d3d06469 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1064,6 +1064,12 @@ properties:
- const: solidrun,imx8mm-sr-som
- const: fsl,imx8mm
+ - description: Variscite DART-MX8MM based boards
+ items:
+ - const: variscite,var-dart-mx8mm-sonata # Variscite DART-MX8MM on Sonata Development Board
+ - const: variscite,var-dart-mx8mm # Variscite DART-MX8M-MINI SOM
+ - const: fsl,imx8mm
+
- description: Variscite VAR-SOM-MX8MM based boards
items:
- const: variscite,var-som-mx8mm-symphony
--
2.47.3
^ permalink raw reply related
* [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX8M-MINI
From: Stefano Radaelli @ 2026-06-27 14:46 UTC (permalink / raw)
To: linux-kernel, devicetree, imx, linux-arm-kernel
Cc: pierluigi.p, Stefano Radaelli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shawn Guo, Daniel Baluta, Josua Mayer,
Dario Binacchi, Alexander Stein, Ernest Van Hoecke,
Maud Spierings, Francesco Dolcini, Hugo Villeneuve
In-Reply-To: <cover.1782571383.git.stefano.r@variscite.com>
From: Stefano Radaelli <stefano.r@variscite.com>
Add device tree support for the Variscite DART-MX8MM system on module.
This SOM is designed to be used with various carrier boards.
The module includes:
- NXP i.MX8M Mini MPU processor
- Up to 4GB of LPDDR4 memory
- Up to 128GB of eMMC storage memory
- Integrated 10/100/1000 Mbps Ethernet Transceiver
- Codec audio WM8904
- WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth
Only SOM-specific peripherals are enabled by default. Carrier board
specific interfaces are left disabled to be enabled in the respective
carrier board device trees.
Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
v1->v2:
- Fixed eth regulator
.../boot/dts/freescale/imx8mm-var-dart.dtsi | 558 ++++++++++++++++++
1 file changed, 558 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi
new file mode 100644
index 000000000000..2324063f8fd9
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi
@@ -0,0 +1,558 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Common dtsi for Variscite DART-MX8M-MINI
+ *
+ * Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/
+ *
+ * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Variscite DART-MX8M-MINI Module";
+ compatible = "variscite,var-dart-mx8mm", "fsl,imx8mm";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ reg_audio_supply: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "wm8904-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_eth_phy: regulator-eth-phy {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_eth_phy>;
+ regulator-name = "eth_phy_pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <20000>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_phy_vddio: regulator-phy-vddio {
+ compatible = "regulator-fixed";
+ regulator-name = "vddio-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ sound-wm8904 {
+ compatible = "simple-audio-card";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&codec_dai>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "wm8904-audio";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "IN2L", "Line In Jack",
+ "IN2R", "Line In Jack",
+ "IN1L", "Microphone Jack",
+ "IN1R", "Microphone Jack";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Line", "Line In Jack";
+
+ codec_dai: simple-audio-card,codec {
+ sound-dai = <&wm8904>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai3>;
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <10000>;
+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
+ <&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&fec1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_fec1>;
+ pinctrl-1 = <&pinctrl_fec1_sleep>;
+ /*
+ * The required RGMII TX and RX 2ns delays are implemented directly
+ * in hardware via passive delay elements on the SOM PCB.
+ * No delay configuration is needed in software via PHY driver.
+ */
+ phy-mode = "rgmii";
+ phy-handle = <ðphy0>;
+ phy-supply = <®_eth_phy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <100000>;
+ vddio-supply = <®_phy_vddio>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ buck3_reg: BUCK3 {
+ // BUCK5 in datasheet
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4_reg: BUCK4 {
+ // BUCK6 in datasheet
+ regulator-name = "buck4";
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ // BUCK7 in datasheet
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ // BUCK8 in datasheet
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ wm8904: audio-codec@1a {
+ compatible = "wlf,wm8904";
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+ clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
+ clock-names = "mclk";
+ AVDD-supply = <&ldo5_reg>;
+ CPVDD-supply = <&ldo5_reg>;
+ DBVDD-supply = <®_audio_supply>;
+ DCVDD-supply = <&ldo5_reg>;
+ MICVDD-supply = <&ldo5_reg>;
+ wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
+ "soft", "music";
+ /*
+ * Config registers per name, respectively:
+ * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
+ * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
+ * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
+ * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
+ * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
+ */
+ wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+ /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
+ /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
+ /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
+ /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
+ /* GPIO1 = DMIC_CLK, don't touch others */
+ wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+ };
+};
+
+&mu {
+ status = "okay";
+};
+
+&sai3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <1536000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+/* BT module */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
+ assigned-clocks = <&clk IMX8MM_CLK_UART4>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth_iw61x: bluetooth {
+ compatible = "nxp,88w8987-bt";
+ };
+};
+
+/* WIFI */
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>;
+ bus-width = <4>;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_bt: btgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0xc1
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc1
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ >;
+ };
+
+ pinctrl_fec1_sleep: fec1sleepgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
+ MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
+ MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
+ MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
+ MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
+ MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
+ MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
+ MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
+ MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
+ MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
+ MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
+ MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
+ MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
+ MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x100
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x140
+ >;
+ };
+
+ pinctrl_reg_eth_phy: regeth-phygrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6
+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
+ MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x140
+ MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x140
+ MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x140
+ MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+
+ pinctrl_wifi: wifigrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x140
+ MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0xc1
+ >;
+ };
+};
--
2.47.3
^ permalink raw reply related
* [PATCH v2 3/3] arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board
From: Stefano Radaelli @ 2026-06-27 14:46 UTC (permalink / raw)
To: linux-kernel, devicetree, imx, linux-arm-kernel
Cc: pierluigi.p, Stefano Radaelli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Shawn Guo, Daniel Baluta, Josua Mayer,
Dario Binacchi, Alexander Stein, Ernest Van Hoecke,
Maud Spierings, Francesco Dolcini, Hugo Villeneuve
In-Reply-To: <cover.1782571383.git.stefano.r@variscite.com>
From: Stefano Radaelli <stefano.r@variscite.com>
Add device tree support for the Variscite Sonata carrier board with the
DART-MX8M-MINI system on module.
The Sonata board includes
- uSD Card support
- USB ports and OTG
- Uart, SPI and I2C interfaces
- GPIO Expanders
- RTC module
- TPM module
- CAN peripherals
Link: https://variscite.com/carrier-boards/sonata-board/
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
v1->v2:
- Remove HDMI from commit message
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx8mm-var-dart-sonata.dts | 517 ++++++++++++++++++
2 files changed, 518 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 8ddaab127ab9..694c9aa32779 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-iv-306-d.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-mini-111.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-dart-sonata.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony-legacy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts
new file mode 100644
index 000000000000..93b0076987b8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts
@@ -0,0 +1,517 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Variscite Sonata carrier board for DART-MX8M-MINI
+ *
+ * Link: https://variscite.com/carrier-boards/sonata-board/
+ *
+ * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include "imx8mm-var-dart.dtsi"
+
+/ {
+ model = "Variscite DART-MX8M-MINI on Sonata-Board";
+ compatible = "variscite,var-dart-mx8mm-sonata",
+ "variscite,var-dart-mx8mm",
+ "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-home {
+ label = "Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ button-up {
+ label = "Up";
+ linux,code = <KEY_UP>;
+ gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ button-down {
+ label = "Down";
+ linux,code = <KEY_DOWN>;
+ gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ button-back {
+ label = "Back";
+ linux,code = <KEY_BACK>;
+ gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-emmc {
+ gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
+ label = "eMMC";
+ linux,default-trigger = "mmc2";
+ };
+ };
+
+ clk40m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <40000000>;
+ clock-output-names = "can_osc";
+ };
+
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vmmc_usdhc2>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
+ <&gpio1 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ /* Resistive touch controller */
+ ads7846: touchscreen@0 {
+ compatible = "ti,ads7846";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_restouch>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <1500000>;
+ pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ ti,x-min = /bits/ 16 <125>;
+ ti,x-max = /bits/ 16 <4008>;
+ ti,y-min = /bits/ 16 <282>;
+ ti,y-max = /bits/ 16 <3864>;
+ ti,x-plate-ohms = /bits/ 16 <180>;
+ ti,pressure-max = /bits/ 16 <255>;
+ ti,debounce-max = /bits/ 16 <10>;
+ ti,debounce-tol = /bits/ 16 <3>;
+ ti,debounce-rep = /bits/ 16 <1>;
+ ti,settle-delay-usec = /bits/ 16 <150>;
+ ti,keep-vref-on;
+ wakeup-source;
+ };
+
+ can0: can@1 {
+ compatible = "microchip,mcp251xfd";
+ reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can>;
+ clocks = <&clk40m>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ microchip,rx-int-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
+ðphy0 {
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_LAN;
+ linux,default-trigger = "netdev";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ linux,default-trigger = "netdev";
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pca9534: gpio@22 {
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ /* RGB_SEL */
+ lvds-brg-enable-hog {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "rgb_sel";
+ };
+ };
+
+ /* Capacitive touch controller */
+ ft5x06_ts: touchscreen@38 {
+ compatible = "edt,edt-ft5206";
+ reg = <0x38>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_captouch>;
+ reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ wakeup-source;
+ };
+
+ extcon_ptn5150: typec@3d {
+ compatible = "nxp,ptn5150";
+ reg = <0x3d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_extcon>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+
+ port {
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1337";
+ reg = <0x68>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_gpio>;
+ scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ pca6408_1: gpio@20 {
+ compatible = "nxp,pcal6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pca6408>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pca6408_2: gpio@21 {
+ compatible = "nxp,pcal6408";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ st33ktpm2xi2c: tpm@2e {
+ compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
+ reg = <0x2e>;
+ label = "tpm";
+ reset-gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ fsl,tx-deemph-gen1 = <0x2d>;
+ fsl,tx-deemph-gen2 = <0xf>;
+ clocks = <&pcie0_refclk>;
+ status = "okay";
+};
+
+&pcie0 {
+ reset-gpios = <&pca6408_2 3 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+ <&clk IMX8MM_CLK_PCIE1_AUX>;
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&clk IMX8MM_CLK_PCIE1_CTRL>;
+ assigned-clock-rates = <10000000>, <250000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+ <&clk IMX8MM_SYS_PLL2_250M>;
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm>;
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+&snvs_rtc {
+ status = "disabled";
+};
+
+/* Console */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ wakeup-source;
+ status = "okay";
+};
+
+/* Header */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* Header */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ disable-over-current;
+ status = "okay";
+};
+
+/* SD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_can: cangrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16
+ >;
+ };
+
+ pinctrl_captouch: captouchgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x13
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x13
+ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x13
+ >;
+ };
+
+ pinctrl_extcon: extcongrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
+ >;
+ };
+
+ pinctrl_gpio_leds: ledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c6
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4_gpio: i2c4-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
+ >;
+ };
+
+ pinctrl_pca6408: pca6408grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c6
+ >;
+ };
+
+ pinctrl_pwm: pwmgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
+ >;
+ };
+
+ pinctrl_vmmc_usdhc2: regvmmc-usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0xc1
+ >;
+ };
+
+ pinctrl_restouch: restouchgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
+ >;
+ };
+
+ pinctrl_rtc: rtcgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0xc1
+ >;
+ };
+};
--
2.47.3
^ permalink raw reply related
* Re: [PATCH v2 3/3] arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board
From: sashiko-bot @ 2026-06-27 14:57 UTC (permalink / raw)
To: Stefano Radaelli; +Cc: Frank.Li, devicetree, imx, robh, conor+dt
In-Reply-To: <e7fa5dc7f6f29bfc3f1b7b7e55cbec3758c28f14.1782571383.git.stefano.r@variscite.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The MCP251xFD CAN controller uses an active-low interrupt line that must be configured as level-triggered, but is configured as edge-triggered (`IRQ_TYPE_EDGE_FALLING`).
- [Low] The ads7846 touchscreen node uses deprecated properties.
- [Low] The pinmux `MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22` is configured as a GPIO in `pinctrl_ecspi1` but `GPIO4_IO22` is never used by `ecspi1` or any of its subnodes.
--
commit bb01573339283cd17f8253331852c339f7a84276
Author: Stefano Radaelli <stefano.r@variscite.com>
arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board
Add device tree support for the Variscite Sonata carrier board with the
DART-MX8M-MINI system on module. This adds support for peripherals including
uSD Card, USB, UART, SPI, I2C, RTC, TPM, and CAN interfaces.
Link: https://variscite.com/carrier-boards/sonata-board/
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts
> new file mode 100644
> index 0000000000000..93b0076987b82
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts
[ ... ]
> + /* Resistive touch controller */
> + ads7846: touchscreen@0 {
> + compatible = "ti,ads7846";
> + reg = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_restouch>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
> + spi-max-frequency = <1500000>;
> + pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
> + ti,x-min = /bits/ 16 <125>;
> + ti,x-max = /bits/ 16 <4008>;
> + ti,y-min = /bits/ 16 <282>;
> + ti,y-max = /bits/ 16 <3864>;
> + ti,x-plate-ohms = /bits/ 16 <180>;
> + ti,pressure-max = /bits/ 16 <255>;
> + ti,debounce-max = /bits/ 16 <10>;
[Severity: Low]
Are these specific ti,ads7846 properties deprecated in favor of generic
touchscreen properties? Using the standard generic bindings might avoid
device tree validation warnings.
> + ti,debounce-tol = /bits/ 16 <3>;
> + ti,debounce-rep = /bits/ 16 <1>;
> + ti,settle-delay-usec = /bits/ 16 <150>;
> + ti,keep-vref-on;
> + wakeup-source;
> + };
> +
> + can0: can@1 {
> + compatible = "microchip,mcp251xfd";
> + reg = <1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_can>;
> + clocks = <&clk40m>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
[Severity: High]
Does the mcp251xfd CAN controller require a level-triggered interrupt rather
than edge-triggered? If the device holds the INT pin low while internal
interrupts are pending, an edge-triggered setup might miss subsequent
interrupts if the line does not transition high to low again, potentially
stalling CAN communication.
[ ... ]
> + pinctrl_captouch: captouchgrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
> + >;
> + };
> +
> + pinctrl_ecspi1: ecspi1grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
> + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
> + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
> + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x13
> + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x13
> + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x13
[Severity: Low]
Is MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 used by ecspi1 or its subnodes? It
appears to be included in the pinctrl_ecspi1 group without being referenced
by the SPI interface, which could unnecessarily claim the pad or cause
conflicts.
> + >;
> + };
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1782571383.git.stefano.r@variscite.com?part=3
^ permalink raw reply
* Re: [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX8M-MINI
From: sashiko-bot @ 2026-06-27 15:00 UTC (permalink / raw)
To: Stefano Radaelli; +Cc: Frank.Li, imx, conor+dt, robh, devicetree
In-Reply-To: <17f248241982c2d421e83475d7e0f8b61ba50198.1782571383.git.stefano.r@variscite.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] Simultaneous assertion/deassertion of Wi-Fi power enable and reset pins in `wifi_pwrseq`, violating typical SDIO Wi-Fi power sequencing requirements.
- [Medium] Bluetooth GPIOs configured in `pinctrl_bt` are not assigned to or claimed by the Bluetooth device node, leaving them as unmanaged floating inputs.
- [Medium] WM8904 codec configuration contains contradictory settings blindly copied from binding examples, likely breaking microphone functionality.
--
commit 4642338fef518c3eba73b9681507dd2dd37ee845
Author: Stefano Radaelli <stefano.r@variscite.com>
arm64: dts: freescale: Add support for Variscite DART-MX8M-MINI
Add device tree support for the Variscite DART-MX8MM system on module.
This SOM is designed to be used with various carrier boards. Only
SOM-specific peripherals are enabled by default.
Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi
> new file mode 100644
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi
[ ... ]
> + sound-wm8904 {
> + compatible = "simple-audio-card";
> + simple-audio-card,bitclock-master = <&codec_dai>;
> + simple-audio-card,format = "i2s";
> + simple-audio-card,frame-master = <&codec_dai>;
> + simple-audio-card,mclk-fs = <256>;
> + simple-audio-card,name = "wm8904-audio";
> + simple-audio-card,routing =
> + "Headphone Jack", "HPOUTL",
> + "Headphone Jack", "HPOUTR",
> + "IN2L", "Line In Jack",
> + "IN2R", "Line In Jack",
> + "IN1L", "Microphone Jack",
> + "IN1R", "Microphone Jack";
[Severity: Medium]
Is this analog microphone routing missing a connection to MICBIAS?
The simple-audio-card,routing property routes the Microphone Jack to the
codec's analog inputs (IN1L/IN1R), but without a connection to the codec's
MICBIAS pin, the analog microphone will likely not receive the required bias
voltage to function.
> + simple-audio-card,widgets =
> + "Microphone", "Microphone Jack",
> + "Headphone", "Headphone Jack",
> + "Line", "Line In Jack";
[ ... ]
> + wifi_pwrseq: wifi-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + post-power-on-delay-ms = <100>;
> + power-off-delay-us = <10000>;
> + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
> + <&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
> + };
[Severity: Medium]
Does grouping both the power enable and reset pins in this single reset-gpios
array violate SDIO Wi-Fi power sequencing requirements?
The mmc-pwrseq-simple driver toggles all GPIOs in the reset-gpios array
simultaneously. During power-on, the Wi-Fi chip's power enable and reset lines
will be driven high at the exact same moment.
Standard Wi-Fi power sequencing typically requires the power supply to be
fully ramped and stable before the reset line is released.
[ ... ]
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + pinctrl-1 = <&pinctrl_i2c3_gpio>;
> + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + status = "okay";
> +
> + wm8904: audio-codec@1a {
> + compatible = "wlf,wm8904";
> + reg = <0x1a>;
[ ... ]
> + /* GPIO1 = DMIC_CLK, don't touch others */
> + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
> + };
> +};
[Severity: Medium]
Does this digital microphone clock configuration contradict the analog audio
routing defined above?
Configuring GPIO1 as a digital microphone clock appears to be a direct copy
from the wlf,wm8904 binding example, but it contradicts the analog routing for
the Microphone Jack to IN1L/IN1R.
This might expose unintended side-effects by driving a digital clock out of
GPIO1 when it's not needed for an analog microphone setup.
[ ... ]
> +/* BT module */
> +&uart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
> + assigned-clocks = <&clk IMX8MM_CLK_UART4>;
> + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
> + uart-has-rtscts;
> + status = "okay";
> +
> + bluetooth_iw61x: bluetooth {
> + compatible = "nxp,88w8987-bt";
> + };
> +};
[Severity: Medium]
Are the Bluetooth GPIOs defined in pinctrl_bt missing their assignments here?
The pinctrl_bt group defines GPIO2_IO6 and GPIO5_IO5 with floating pad
configurations (0xc1), and the parent uart4 node applies them. However,
because this bluetooth node doesn't map them to expected driver properties
(such as device-wakeup-gpios or host-wakeup-gpios), they are left as
unmanaged floating inputs.
If one of these acts as an enable or reset pin, floating inputs can cause
erratic behavior due to voltage drift.
> +/* WIFI */
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>;
> + bus-width = <4>;
> + keep-power-in-suspend;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + non-removable;
> + status = "okay";
> +};
[Severity: Medium]
Should this node include a vmmc-supply linking to a regulator for the Wi-Fi
power enable?
Modeling WIFI_PWR_EN as a regulator-fixed assigned to vmmc-supply in this
usdhc1 node, while leaving only WIFI_RESET in the mmc-pwrseq-simple node,
would ensure the power sequencing is handled correctly.
--
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1782571383.git.stefano.r@variscite.com?part=2
^ permalink raw reply
* Re: [PATCH v2 00/17] mod_devicetable.h: Split into per subsystem headers
From: Danilo Krummrich @ 2026-06-27 16:07 UTC (permalink / raw)
To: Uwe Kleine-König (The Capable Hub)
Cc: Linus Torvalds, Greg Kroah-Hartman, Mark Brown, Nathan Chancellor,
Nick Desaulniers, Bill Wendling, Justin Stitt, Raag Jadav,
Sohil Mehta, Dave Hansen, Rob Herring, Saravana Kannan,
Bjorn Helgaas, Rafael J. Wysocki, Len Brown, Andi Shyti,
linux-kernel, Yemike Abhilash Chandra, Mauro Carvalho Chehab,
linux-media, Nicolas Frattaroli, Liam Girdwood, Jaroslav Kysela,
Takashi Iwai, Heiko Stuebner, linux-rockchip, linux-sound,
linux-arm-kernel, driver-core, Jonathan Cameron, Dmitry Torokhov,
Bartosz Golaszewski, Pei Xiao, Shashank Balaji, Ben Horgan,
Johan Hovold, linux-usb, Nikita Kravets, Hans de Goede,
Ilpo Järvinen, platform-driver-x86, devicetree, linux-i2c,
Daniel Scally, Sakari Ailus, Minas Harutyunyan, Tianrui Zhao,
Bibo Mao, Huacai Chen, WANG Xuerui, kvm, loongarch
In-Reply-To: <cover.1782490566.git.u.kleine-koenig@baylibre.com>
On Fri Jun 26, 2026 at 8:00 PM CEST, Uwe Kleine-König (The Capable Hub) wrote:
> Uwe Kleine-König (The Capable Hub) (17):
> mod_devicetable.h: Split into per subsystem headers
> driver: core: Include headers for acpi_device_id and of_device_id for struct device_driver
> driver core: platform: Include header for struct platform_device_id
With the suggested rename,
Acked-by: Danilo Krummrich <dakr@kernel.org>
^ permalink raw reply
* [PATCH v3 0/6] Add minimal Exynos8855 SoC support
From: Alim Akhtar @ 2026-06-27 17:12 UTC (permalink / raw)
To: krzk, peter.griffin, robh, conor+dt, linusw
Cc: linux-samsung-soc, linux-kernel, devicetree, linux-gpio,
hajun.sung, Alim Akhtar
In-Reply-To: <CGME20260627165402epcas5p4481839961bdedebfa4d96a3517edaf2b@epcas5p4.samsung.com>
This series adds initial support for the Exynos8855 SoC and also
initial SMDK board support.
Exynos8855 is octa-core CPUs, a combination of Cortex-A720 and Cortex-A520,
arranged in 3 clusters. And other peripheral for mobile application.
This initial support consists of CPUs, pinctrl and related nodes
needed for initial kernel boot.
With these patches, kernel can boot using initramfs till file system mounts.
More platform support will be added in near future, clock driver to go next.
Changes since v2:
* Addressed review comments from Peter Griffin and Krzysztof.
* Updated uses of GS101 MACROS for pinctrl driver
* Documented wakeup interrupt binding
* Rebased on latest Linux-next
Chanegs since v1:
* Fixed some of the review comments by Sashiko [1]
* Dropped serial node, will be added once clock support is available
* Dropped wkup interrupt for CMGP block, will be added later
Link of v2:
https://lore.kernel.org/all/20260615085252.1964423-1-alim.akhtar@samsung.com/
Link of v1:
https://lore.kernel.org/linux-samsung-soc/20260612163020.411761-1-alim.akhtar@samsung.com/
[1] https://sashiko.dev/#/patchset/20260612163020.411761-1-alim.akhtar@samsung.com?part=4
Alim Akhtar (6):
dt-binding: ARM: samsung: Add Samsung Exynos8855
dt-binding: pinctrl: samsung: Add exynos8855-pinctrl compatible
pinctrl: samsung: Add Exynos8855 pinctrl configuration
dt-bindings: pinctrl: samsung: Add exynos8855-wakeup-eint compatible
arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk
MAINTAINERS: Add entry for Samsung Exynos8855 SoC
.../bindings/arm/samsung/samsung-boards.yaml | 6 +
.../samsung,pinctrl-wakeup-interrupt.yaml | 1 +
.../bindings/pinctrl/samsung,pinctrl.yaml | 1 +
MAINTAINERS | 7 +
arch/arm64/boot/dts/exynos/Makefile | 1 +
.../boot/dts/exynos/exynos8855-pinctrl.dtsi | 574 ++++++++++++++++++
.../arm64/boot/dts/exynos/exynos8855-smdk.dts | 32 +
arch/arm64/boot/dts/exynos/exynos8855.dtsi | 204 +++++++
.../pinctrl/samsung/pinctrl-exynos-arm64.c | 132 ++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
11 files changed, 961 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos8855.dtsi
base-commit: 3d5670d672ae08b8c534b7beed6f57c8b44e7b43
--
2.34.1
^ permalink raw reply
* [PATCH v3 2/6] dt-binding: pinctrl: samsung: Add exynos8855-pinctrl compatible
From: Alim Akhtar @ 2026-06-27 17:12 UTC (permalink / raw)
To: krzk, peter.griffin, robh, conor+dt, linusw
Cc: linux-samsung-soc, linux-kernel, devicetree, linux-gpio,
hajun.sung, Alim Akhtar
In-Reply-To: <20260627171228.2687857-1-alim.akhtar@samsung.com>
Document pin controller support on Exynos8855 SoC.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
index 7b006009ca0e..c4773701c92e 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
@@ -53,6 +53,7 @@ properties:
- samsung,exynos7870-pinctrl
- samsung,exynos7885-pinctrl
- samsung,exynos850-pinctrl
+ - samsung,exynos8855-pinctrl
- samsung,exynos8890-pinctrl
- samsung,exynos8895-pinctrl
- samsung,exynos9610-pinctrl
--
2.34.1
^ permalink raw reply related
* [PATCH v3 1/6] dt-binding: ARM: samsung: Add Samsung Exynos8855
From: Alim Akhtar @ 2026-06-27 17:12 UTC (permalink / raw)
To: krzk, peter.griffin, robh, conor+dt, linusw
Cc: linux-samsung-soc, linux-kernel, devicetree, linux-gpio,
hajun.sung, Alim Akhtar
In-Reply-To: <20260627171228.2687857-1-alim.akhtar@samsung.com>
Add Samsung Exynos8855 smdk board to documentation
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
.../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
index 753b3ba1b607..273464400477 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
@@ -235,6 +235,12 @@ properties:
- winlink,e850-96 # WinLink E850-96
- const: samsung,exynos850
+ - description: Exynos8855 based boards
+ items:
+ - enum:
+ - samsung,exynos8855-smdk # Samsung SMDK
+ - const: samsung,exynos8855
+
- description: Exynos8895 based boards
items:
- enum:
--
2.34.1
^ permalink raw reply related
* [PATCH v3 3/6] pinctrl: samsung: Add Exynos8855 pinctrl configuration
From: Alim Akhtar @ 2026-06-27 17:12 UTC (permalink / raw)
To: krzk, peter.griffin, robh, conor+dt, linusw
Cc: linux-samsung-soc, linux-kernel, devicetree, linux-gpio,
hajun.sung, Alim Akhtar
In-Reply-To: <20260627171228.2687857-1-alim.akhtar@samsung.com>
Add pinctrl configuration for Exynos8855. The bank type
macros are reused from EXYNOS850 and GS101 SoC.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
.../pinctrl/samsung/pinctrl-exynos-arm64.c | 132 ++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
3 files changed, 135 insertions(+)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index fe9f92cb037e..1aa977d2a1f8 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -943,6 +943,138 @@ const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = {
.num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl),
};
+/* pin banks of exynos8855 pin-controller 0 (ALIVE) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks0[] __initconst = {
+ GS101_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00, 0x00),
+ GS101_PIN_BANK_EINTW(4, 0x020, "gpa1", 0x04, 0x08),
+ EXYNOS850_PIN_BANK_EINTN(3, 0x040, "gpq0"),
+ EXYNOS850_PIN_BANK_EINTN(2, 0x060, "gpq1"),
+ GS101_PIN_BANK_EINTW(1, 0x080, "gpc0", 0x08, 0x10),
+ GS101_PIN_BANK_EINTW(1, 0x0a0, "gpc1", 0x0c, 0x14),
+ GS101_PIN_BANK_EINTW(1, 0x0c0, "gpc2", 0x10, 0x18),
+ GS101_PIN_BANK_EINTW(1, 0x0e0, "gpc3", 0x14, 0x1c),
+ GS101_PIN_BANK_EINTW(1, 0x100, "gpc4", 0x18, 0x20),
+ GS101_PIN_BANK_EINTW(1, 0x120, "gpc5", 0x1c, 0x24),
+ GS101_PIN_BANK_EINTW(1, 0x140, "gpc6", 0x20, 0x28),
+ GS101_PIN_BANK_EINTW(1, 0x160, "gpc7", 0x24, 0x2c),
+ GS101_PIN_BANK_EINTW(1, 0x180, "gpc8", 0x28, 0x30),
+ GS101_PIN_BANK_EINTW(1, 0x1a0, "gpc9", 0x2c, 0x34),
+ GS101_PIN_BANK_EINTW(1, 0x1c0, "gpc10", 0x30, 0x38),
+ GS101_PIN_BANK_EINTW(1, 0x1e0, "gpc11", 0x34, 0x3c),
+ GS101_PIN_BANK_EINTW(1, 0x200, "gpc12", 0x38, 0x40),
+ GS101_PIN_BANK_EINTW(1, 0x220, "gpc13", 0x3c, 0x44),
+ GS101_PIN_BANK_EINTW(1, 0x240, "gpc14", 0x40, 0x48),
+ GS101_PIN_BANK_EINTW(1, 0x260, "gpj0", 0x44, 0x4c),
+ GS101_PIN_BANK_EINTW(1, 0x280, "gpj1", 0x48, 0x50),
+ GS101_PIN_BANK_EINTW(1, 0x2a0, "gpj2", 0x4c, 0x54),
+};
+
+/* pin banks of exynos8855 pin-controller 1 (CMGP) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks1[] __initconst = {
+ GS101_PIN_BANK_EINTW(1, 0x00, "gpm0", 0x00, 0x00),
+ GS101_PIN_BANK_EINTW(1, 0x20, "gpm1", 0x04, 0x04),
+ GS101_PIN_BANK_EINTW(1, 0x40, "gpm2", 0x08, 0x08),
+ GS101_PIN_BANK_EINTW(1, 0x60, "gpm3", 0x0c, 0x0c),
+ GS101_PIN_BANK_EINTW(1, 0x80, "gpm4", 0x10, 0x10),
+ GS101_PIN_BANK_EINTW(1, 0xa0, "gpm5", 0x14, 0x14),
+ GS101_PIN_BANK_EINTW(1, 0xc0, "gpm6", 0x18, 0x18),
+ GS101_PIN_BANK_EINTW(1, 0xe0, "gpm7", 0x1c, 0x1c),
+ GS101_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20, 0x20),
+ GS101_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24, 0x24),
+ GS101_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28, 0x28),
+ GS101_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2c, 0x2c),
+ GS101_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30, 0x30),
+ GS101_PIN_BANK_EINTW(1, 0x1a0, "gpm13", 0x34, 0x34),
+ GS101_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38, 0x38),
+ GS101_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c, 0x3c),
+ GS101_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40, 0x40),
+ GS101_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44, 0x44),
+ GS101_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48, 0x48),
+ GS101_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4c, 0x4c),
+ GS101_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50, 0x50),
+ GS101_PIN_BANK_EINTW(1, 0x2a0, "gpm21", 0x54, 0x54),
+};
+
+/* pin banks of exynos8855 pin-controller 2 (HSI UFS) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks2[] __initconst = {
+ GS101_PIN_BANK_EINTG(2, 0x0, "gpf3", 0x00, 0x00),
+};
+
+/* pin banks of exynos8855 pin-controller 3 (PERIC) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks3[] __initconst = {
+ GS101_PIN_BANK_EINTG(8, 0x0, "gpp0", 0x00, 0x00),
+ GS101_PIN_BANK_EINTG(8, 0x20, "gpp1", 0x04, 0x08),
+ GS101_PIN_BANK_EINTG(6, 0x40, "gpp2", 0x08, 0x10),
+ GS101_PIN_BANK_EINTG(4, 0x60, "gpg0", 0x0c, 0x18),
+ GS101_PIN_BANK_EINTG(3, 0x80, "gpg1", 0x10, 0x1c),
+ GS101_PIN_BANK_EINTG(6, 0xa0, "gpb0", 0x14, 0x20),
+ GS101_PIN_BANK_EINTG(4, 0xc0, "gpb1", 0x18, 0x28),
+};
+
+/* pin banks of exynos8855 pin-controller 4 (PERICMMC) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks4[] __initconst = {
+ GS101_PIN_BANK_EINTG(7, 0x0, "gpf2", 0x00, 0x00),
+};
+
+/* pin banks of exynos8855 pin-controller 5 (USI) */
+static const struct samsung_pin_bank_data exynos8855_pin_banks5[] __initconst = {
+ GS101_PIN_BANK_EINTG(8, 0x00, "gpp3", 0x00, 0x00),
+ GS101_PIN_BANK_EINTG(2, 0x20, "gpp4", 0x04, 0x08),
+ GS101_PIN_BANK_EINTG(2, 0x40, "gpg2", 0x08, 0x0c),
+ GS101_PIN_BANK_EINTG(1, 0x60, "gpg3", 0x0c, 0x10),
+};
+
+static const struct samsung_pin_ctrl exynos8855_pin_ctrl[] __initconst = {
+ {
+ /* pin-controller instance 0 ALIVE data */
+ .pin_banks = exynos8855_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks0),
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .suspend = gs101_pinctrl_suspend,
+ .resume = gs101_pinctrl_resume,
+ }, {
+ /* pin-controller instance 1 CMGP data */
+ .pin_banks = exynos8855_pin_banks1,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks1),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = gs101_pinctrl_suspend,
+ .resume = gs101_pinctrl_resume,
+ }, {
+ /* pin-controller instance 2 HSI UFS data */
+ .pin_banks = exynos8855_pin_banks2,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks2),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = gs101_pinctrl_suspend,
+ .resume = gs101_pinctrl_resume,
+ }, {
+ /* pin-controller instance 3 PERIC data */
+ .pin_banks = exynos8855_pin_banks3,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks3),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = gs101_pinctrl_suspend,
+ .resume = gs101_pinctrl_resume,
+ }, {
+ /* pin-controller instance 4 PERICMMC data */
+ .pin_banks = exynos8855_pin_banks4,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks4),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = gs101_pinctrl_suspend,
+ .resume = gs101_pinctrl_resume,
+ }, {
+ /* pin-controller instance 5 USI data */
+ .pin_banks = exynos8855_pin_banks5,
+ .nr_banks = ARRAY_SIZE(exynos8855_pin_banks5),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = gs101_pinctrl_suspend,
+ .resume = gs101_pinctrl_resume,
+ },
+};
+
+const struct samsung_pinctrl_of_match_data exynos8855_of_data __initconst = {
+ .ctrl = exynos8855_pin_ctrl,
+ .num_ctrl = ARRAY_SIZE(exynos8855_pin_ctrl),
+};
+
/* pin banks of exynos990 pin-controller 0 (ALIVE) */
static struct samsung_pin_bank_data exynos990_pin_banks0[] = {
/* Must start with EINTG banks, ordered by EINT group number. */
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 5ac6f6b02327..5ecc9ed4c44d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1500,6 +1500,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = &exynos7885_of_data },
{ .compatible = "samsung,exynos850-pinctrl",
.data = &exynos850_of_data },
+ { .compatible = "samsung,exynos8855-pinctrl",
+ .data = &exynos8855_of_data },
{ .compatible = "samsung,exynos8890-pinctrl",
.data = &exynos8890_of_data },
{ .compatible = "samsung,exynos8895-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 937600430a6e..bb02fb49b2af 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -396,6 +396,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
extern const struct samsung_pinctrl_of_match_data exynos7870_of_data;
extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
+extern const struct samsung_pinctrl_of_match_data exynos8855_of_data;
extern const struct samsung_pinctrl_of_match_data exynos8890_of_data;
extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
extern const struct samsung_pinctrl_of_match_data exynos9610_of_data;
--
2.34.1
^ permalink raw reply related
* [PATCH v3 4/6] dt-bindings: pinctrl: samsung: Add exynos8855-wakeup-eint compatible
From: Alim Akhtar @ 2026-06-27 17:12 UTC (permalink / raw)
To: krzk, peter.griffin, robh, conor+dt, linusw
Cc: linux-samsung-soc, linux-kernel, devicetree, linux-gpio,
hajun.sung, Alim Akhtar
In-Reply-To: <20260627171228.2687857-1-alim.akhtar@samsung.com>
Add a dedicated compatible for the exynos8855-wakeup-eint node, which
is compatible with Exynos7 implementation.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
.../bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
index 2b88f25e80a6..802911e23aff 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
@@ -41,6 +41,7 @@ properties:
- samsung,exynos7870-wakeup-eint
- samsung,exynos7885-wakeup-eint
- samsung,exynos850-wakeup-eint
+ - samsung,exynos8855-wakeup-eint
- samsung,exynos8890-wakeup-eint
- samsung,exynos8895-wakeup-eint
- const: samsung,exynos7-wakeup-eint
--
2.34.1
^ permalink raw reply related
* [PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk
From: Alim Akhtar @ 2026-06-27 17:12 UTC (permalink / raw)
To: krzk, peter.griffin, robh, conor+dt, linusw
Cc: linux-samsung-soc, linux-kernel, devicetree, linux-gpio,
hajun.sung, Alim Akhtar
In-Reply-To: <20260627171228.2687857-1-alim.akhtar@samsung.com>
Add initial devicetree support for Samsung smdk board using
Exynos8855 SoC.
This SoC has Octa-core CPU with tri cluster architecture, a custom GPU
and a NPU supporting up to 14.7 TOPS apart from other supporting peripheral
and IPs.
Commercially this SoC is also known as Exynos1580 [1]
[1] https://semiconductor.samsung.com/processor/mobile-processor/exynos-1580/
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
arch/arm64/boot/dts/exynos/Makefile | 1 +
.../boot/dts/exynos/exynos8855-pinctrl.dtsi | 574 ++++++++++++++++++
.../arm64/boot/dts/exynos/exynos8855-smdk.dts | 32 +
arch/arm64/boot/dts/exynos/exynos8855.dtsi | 204 +++++++
4 files changed, 811 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos8855.dtsi
diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
index 76cc23acb9b2..8c48ce2e02e5 100644
--- a/arch/arm64/boot/dts/exynos/Makefile
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \
exynos7870-on7xelte.dtb \
exynos7885-jackpotlte.dtb \
exynos850-e850-96.dtb \
+ exynos8855-smdk.dtb \
exynos8895-dreamlte.dtb \
exynos9810-starlte.dtb \
exynos990-c1s.dtb \
diff --git a/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
new file mode 100644
index 000000000000..b65f1698cd74
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
@@ -0,0 +1,574 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's S5E8855 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2023 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's S5E8855 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "exynos-pinctrl.h"
+
+&pinctrl_alive {
+ gpa0: gpa0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpa1: gpa1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpq0: gpq0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpq1: gpq1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpc0: gpc0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc1: gpc1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc2: gpc2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc3: gpc3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc4: gpc4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc5: gpc5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc6: gpc6-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc7: gpc7-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc8: gpc8-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc9: gpc9-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc10: gpc10-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc11: gpc11-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc12: gpc12-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc13: gpc13-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpc14: gpc14-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpj0: gpj0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpj1: gpj1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpj2: gpj2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&pinctrl_cmgp {
+ gpm0: gpm0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm1: gpm1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm2: gpm2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm3: gpm3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm4: gpm4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm5: gpm5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm6: gpm6-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm7: gpm7-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm8: gpm8-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm9: gpm9-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm10: gpm10-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm11: gpm11-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm12: gpm12-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm13: gpm13-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm14: gpm14-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm15: gpm15-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm16: gpm16-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm17: gpm17-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm18: gpm18-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm19: gpm19-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm20: gpm20-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpm21: gpm21-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&pinctrl_hsi_ufs {
+ gpf3: gpf3-gpio-bank{
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_peric {
+ gpp0: gpp0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp1: gpp1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp2: gpp2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg0: gpg0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg1: gpg1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb0: gpb0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb1: gpb1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_pericmmc {
+ gpf2: gpf2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_usi {
+ gpp3: gpp3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp4: gpp4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg2: gpg2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg3: gpg3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts b/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
new file mode 100644
index 000000000000..792d52affc61
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung Exynos8855 SMDK board device tree source
+ *
+ * Copyright (C) 2023 Samsung Electronics Co., Ltd.
+ *
+ * Device tree source file for Samsung SMDK board which is based on
+ * Exynos8855 SoC.
+ */
+
+/dts-v1/;
+
+#include "exynos8855.dtsi"
+
+/ {
+ model = "Samsung Exynos8855 SMDK board";
+ compatible = "samsung,exynos8855-smdk","samsung,exynos8855";
+
+ chosen {
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x80000000>;
+ };
+
+};
+
+&oscclk {
+ clock-frequency = <76800000>;
+};
+
diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
new file mode 100644
index 000000000000..9d82fceb5130
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung Exynos8855 SoC device tree source
+ *
+ * Copyright (C) 2023 Samsung Electronics Co., Ltd.
+ *
+ * Samsung Exynos8855 SoC device nodes are listed in this file.
+ * Exynos8855 based board files can include this file and provide
+ * values for board specific bindings.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "samsung,exynos8855";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ pinctrl0 = &pinctrl_alive;
+ pinctrl1 = &pinctrl_cmgp;
+ pinctrl2 = &pinctrl_hsi_ufs;
+ pinctrl3 = &pinctrl_peric;
+ pinctrl4 = &pinctrl_pericmmc;
+ pinctrl5 = &pinctrl_usi;
+ };
+
+ oscclk: clock-oscclk {
+ compatible = "fixed-clock";
+ clock-output-names = "oscclk";
+ #clock-cells = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x200>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0x300>;
+ enable-method = "psci";
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x400>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x500>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x600>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0x700>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x20000000>;
+
+ gic: interrupt-controller@10200000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x10200000 0x10000>,
+ <0x10240000 0x140000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_alive: pinctrl@11850000 {
+ compatible = "samsung,exynos8855-pinctrl";
+ reg = <0x11850000 0x1000>;
+
+ wakeup-interrupt-controller {
+ compatible = "samsung,exynos8855-wakeup-eint",
+ "samsung,exynos7-wakeup-eint";
+ };
+ };
+
+ pinctrl_cmgp: pinctrl@12030000 {
+ compatible = "samsung,exynos8855-pinctrl";
+ reg = <0x12030000 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_usi: pinctrl@15030000 {
+ compatible = "samsung,exynos8855-pinctrl";
+ reg = <0x15030000 0x1000>;
+ interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_peric: pinctrl@15440000 {
+ compatible = "samsung,exynos8855-pinctrl";
+ reg = <0x15440000 0x1000>;
+ interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_pericmmc: pinctrl@154f0000 {
+ compatible = "samsung,exynos8855-pinctrl";
+ reg = <0x154f0000 0x1000>;
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_hsi_ufs: pinctrl@17040000 {
+ compatible = "samsung,exynos8855-pinctrl";
+ reg = <0x17040000 0x1000>;
+ interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ /* Hypervisor Virtual Timer interrupt is not wired to GIC */
+ interrupts =
+ <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "exynos8855-pinctrl.dtsi"
--
2.34.1
^ permalink raw reply related
* [PATCH v3 6/6] MAINTAINERS: Add entry for Samsung Exynos8855 SoC
From: Alim Akhtar @ 2026-06-27 17:12 UTC (permalink / raw)
To: krzk, peter.griffin, robh, conor+dt, linusw
Cc: linux-samsung-soc, linux-kernel, devicetree, linux-gpio,
hajun.sung, Alim Akhtar
In-Reply-To: <20260627171228.2687857-1-alim.akhtar@samsung.com>
Add maintainers entry for the Samsung Exynos8855 SoC based platforms
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1705eb823dd0..f6d9e03d3370 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23996,6 +23996,13 @@ F: arch/arm64/boot/dts/exynos/exynos850*
F: drivers/clk/samsung/clk-exynos850.c
F: include/dt-bindings/clock/exynos850.h
+SAMSUNG EXYNOS8855 SoC SUPPORT
+M: Alim Akhtar <alim.akhtar@samsung.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: linux-samsung-soc@vger.kernel.org
+S: Maintained
+F: arch/arm64/boot/dts/exynos/exynos8855*
+
SAMSUNG EXYNOS ACPM MAILBOX PROTOCOL
M: Tudor Ambarus <tudor.ambarus@linaro.org>
L: linux-kernel@vger.kernel.org
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v3 3/6] pinctrl: samsung: Add Exynos8855 pinctrl configuration
From: sashiko-bot @ 2026-06-27 17:04 UTC (permalink / raw)
To: Alim Akhtar; +Cc: devicetree, conor+dt, robh
In-Reply-To: <20260627171228.2687857-4-alim.akhtar@samsung.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Incorrect Wakeup Interrupt Initialization Callback for CMGP pin controller
--
commit 603cd3e67c5aa008772144faa081414df87774ab
Author: Alim Akhtar <alim.akhtar@samsung.com>
pinctrl: samsung: Add Exynos8855 pinctrl configuration
Add pinctrl configuration for Exynos8855. The bank type
macros are reused from EXYNOS850 and GS101 SoC.
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> index fe9f92cb037ea..1aa977d2a1f80 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
[ ... ]
> +static const struct samsung_pin_ctrl exynos8855_pin_ctrl[] __initconst = {
> + {
> + /* pin-controller instance 0 ALIVE data */
> + .pin_banks = exynos8855_pin_banks0,
> + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks0),
> + .eint_wkup_init = exynos_eint_wkup_init,
> + .suspend = gs101_pinctrl_suspend,
> + .resume = gs101_pinctrl_resume,
> + }, {
> + /* pin-controller instance 1 CMGP data */
> + .pin_banks = exynos8855_pin_banks1,
> + .nr_banks = ARRAY_SIZE(exynos8855_pin_banks1),
> + .eint_gpio_init = exynos_eint_gpio_init,
[Severity: High]
Does this incorrectly assign the GPIO interrupt initialization callback instead
of the wakeup interrupt initialization callback?
Looking at exynos8855_pin_banks1, the banks are defined using
GS101_PIN_BANK_EINTW, meaning they are marked as EINT_TYPE_WKUP.
If .eint_wkup_init is NULL and .eint_gpio_init is used, exynos_eint_gpio_init()
will skip these banks because they are marked as EINT_TYPE_WKUP.
Will this cause external wakeup interrupts on the CMGP pin controller to fail
since their IRQ domains are never initialized?
> + .suspend = gs101_pinctrl_suspend,
> + .resume = gs101_pinctrl_resume,
> + }, {
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260627171228.2687857-1-alim.akhtar@samsung.com?part=3
^ permalink raw reply
* Re: [PATCH v3 4/6] dt-bindings: pinctrl: samsung: Add exynos8855-wakeup-eint compatible
From: sashiko-bot @ 2026-06-27 17:05 UTC (permalink / raw)
To: Alim Akhtar; +Cc: robh, conor+dt, devicetree
In-Reply-To: <20260627171228.2687857-5-alim.akhtar@samsung.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Mismatched interrupt initialization callback for the Exynos8855 CMGP pin controller instance.
- [Medium] Missing schema constraint for 'samsung,exynos8855-wakeup-eint' in conditional blocks.
--
commit 6b2b84ce35194270a7205c775f4bf99caf377480
Author: Alim Akhtar <alim.akhtar@samsung.com>
dt-bindings: pinctrl: samsung: Add exynos8855-wakeup-eint compatible
Add a dedicated compatible for the exynos8855-wakeup-eint node, which
is compatible with Exynos7 implementation.
> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> index 2b88f25e80a6d..802911e23aff5 100644
> --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
> @@ -41,6 +41,7 @@ properties:
> - samsung,exynos7870-wakeup-eint
> - samsung,exynos7885-wakeup-eint
> - samsung,exynos850-wakeup-eint
> + - samsung,exynos8855-wakeup-eint
> - samsung,exynos8890-wakeup-eint
> - samsung,exynos8895-wakeup-eint
> - const: samsung,exynos7-wakeup-eint
[Severity: Medium]
Should samsung,exynos8855-wakeup-eint also be added to the allOf conditional
blocks to enforce the correct interrupt constraints?
Looking later in this file, this conditional block restricts the 'interrupts'
property to a single item for Exynos7 variants:
- if:
properties:
compatible:
oneOf:
- enum:
[ ... ]
- contains:
enum:
- samsung,exynos5433-wakeup-eint
- samsung,exynos7870-wakeup-eint
[ ... ]
Is the new Exynos8855 variant missing from this list, which would allow
invalid hardware descriptions to silently pass validation?
[Severity: High]
While looking at the related driver code for Exynos8855, is there a mismatched
interrupt initialization callback for the CMGP instance?
The exynos8855_pin_banks1 definition configures the banks as wake-up type
interrupts (EINTW), which require the wake-up initialization routine:
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c:exynos8855_pin_banks1[] {
GS101_PIN_BANK_EINTW(1, 0x00, "gpm0", 0x00, 0x00),
[ ... ]
};
But the CMGP instance exynos8855_pin_ctrl incorrectly assigns the GPIO init
callback instead of the required wake-up init callback:
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c:exynos8855_pin_ctrl[] {
[ ... ]
}, {
/* pin-controller instance 1 CMGP data */
.pin_banks = exynos8855_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos8855_pin_banks1),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = gs101_pinctrl_suspend,
[ ... ]
}
Does this cause the wake-up interrupt banks to be ignored?
During the driver probe process, the GPIO init function explicitly skips banks
that are not of type EINT_TYPE_GPIO. Because the wake-up init callback
(.eint_wkup_init) is missing, it seems no initialization runs for these banks
at all, leaving the external wake-up interrupts completely dead and their IRQ
domains uncreated.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260627171228.2687857-1-alim.akhtar@samsung.com?part=4
^ permalink raw reply
* Re: [PATCH v3 5/6] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk
From: sashiko-bot @ 2026-06-27 17:06 UTC (permalink / raw)
To: Alim Akhtar; +Cc: conor+dt, devicetree, robh
In-Reply-To: <20260627171228.2687857-6-alim.akhtar@samsung.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The pinctrl_cmgp controller and its first child bank gpm0 both claim the exact same GIC interrupt (SPI 114), and the driver configuration is fundamentally broken for CMGP interrupts.
- [Medium] The asymmetric big.LITTLE CPU topology (Cortex-A520 and Cortex-A720) is missing CPU capacity definitions.
--
commit 46c39da58bc865179bf89eb7be4c747cacdd7227
Author: Alim Akhtar <alim.akhtar@samsung.com>
arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk
This commit adds initial devicetree support for the Samsung SMDK board using
the Exynos8855 SoC. The SoC features an Octa-core CPU with a tri-cluster
architecture, a custom GPU, and an NPU supporting up to 14.7 TOPS.
Link: https://semiconductor.samsung.com/processor/mobile-processor/exynos-1580/
> diff --git a/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
> new file mode 100644
> index 0000000000000..b65f1698cd74a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi
[ ... ]
> +&pinctrl_cmgp {
> + gpm0: gpm0-gpio-bank {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> + };
[Severity: High]
Does this child bank gpm0 claim the exact same SPI 114 interrupt as its
parent pinctrl_cmgp node?
If the child explicitly requests SPI 114 here, it might create an IRQ
resource conflict with the parent.
[ ... ]
> diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
> new file mode 100644
> index 0000000000000..9d82fceb5130a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi
[ ... ]
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
[Severity: Medium]
Will the Energy Aware Scheduler function properly without the
capacity-dmips-mhz property defined here for the asymmetric Cortex-A520 and
Cortex-A720 nodes?
Without this property and lacking OPP tables, the scheduler might assume a
symmetric topology, which could cause it to schedule heavy tasks on the
small A520 cores or background tasks on the big A720 cores.
[ ... ]
> + pinctrl_cmgp: pinctrl@12030000 {
> + compatible = "samsung,exynos8855-pinctrl";
> + reg = <0x12030000 0x1000>;
> + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> + };
[Severity: High]
Could claiming GIC_SPI 114 here in the parent node lead to initialization
failures for CMGP interrupts?
The Exynos driver configures CMGP to use exynos_eint_gpio_init, which
expects a single demultiplexed IRQ on the parent. However, the gpm banks
are Wakeup EINTs with direct per-bank GIC interrupts (like the SPI 114
requested by gpm0).
Because exynos_eint_gpio_init skips EINT_TYPE_WKUP banks, the parent
successfully claims SPI 114 for a non-functional demux handler, blocking
gpm0. Any peripheral attempting to map an interrupt from a CMGP bank might
fail to probe. Should this instead have a wakeup-interrupt-controller
child node without claiming a parent interrupt?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260627171228.2687857-1-alim.akhtar@samsung.com?part=5
^ permalink raw reply
* [PATCH v2 0/2] Recognize Snapdragon SDM850
From: David Heidelberg via B4 Relay @ 2026-06-27 17:50 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, David Heidelberg
Useful for sdm850 devices in tree and also will be used by Comma AI comma three
Signed-off-by: David Heidelberg <david@ixit.cz>
---
Changes in v2:
- It's not SDA850, but classic SDM850. (Konrad)
- Add consumer of the define (socinfo). (Krzysztof)
- Link to v1: https://lore.kernel.org/r/20260623-sda850-v1-1-ddd8e62c85d8@ixit.cz
---
David Heidelberg (2):
dt-bindings: arm: qcom,ids: Add SoC ID for Snapdragon SDM 850
soc: qcom: socinfo: Add SoC ID for SDM850
drivers/soc/qcom/socinfo.c | 1 +
include/dt-bindings/arm/qcom,ids.h | 1 +
2 files changed, 2 insertions(+)
---
base-commit: 948efecf22e49aa4bf55bb73ec79a0ddcfd38571
change-id: 20260623-sda850-6b5c1e44662c
Best regards,
--
David Heidelberg <david@ixit.cz>
^ permalink raw reply
* [PATCH v2 2/2] soc: qcom: socinfo: Add SoC ID for SDM850
From: David Heidelberg via B4 Relay @ 2026-06-27 17:50 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, David Heidelberg
In-Reply-To: <20260627-sda850-v2-0-44bf46ade42e@ixit.cz>
From: David Heidelberg <david@ixit.cz>
Recognize the SDM850 SoC.
Signed-off-by: David Heidelberg <david@ixit.cz>
---
drivers/soc/qcom/socinfo.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
index af418adad7aaf..1836e226a2945 100644
--- a/drivers/soc/qcom/socinfo.c
+++ b/drivers/soc/qcom/socinfo.c
@@ -420,16 +420,17 @@ static const struct soc_id soc_id[] = {
{ qcom_board_id(SDM450) },
{ qcom_board_id(SM8150) },
{ qcom_board_id(SDA845) },
{ qcom_board_id(IPQ8072) },
{ qcom_board_id(IPQ8076) },
{ qcom_board_id(IPQ8078) },
{ qcom_board_id(SDM636) },
{ qcom_board_id(SDA636) },
+ { qcom_board_id(SDM850) },
{ qcom_board_id(SDM632) },
{ qcom_board_id(SDA632) },
{ qcom_board_id(SDA450) },
{ qcom_board_id(SDM439) },
{ qcom_board_id(SDM429) },
{ qcom_board_id(SM8250) },
{ qcom_board_id(SA8155) },
{ qcom_board_id(SDA439) },
--
2.53.0
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: arm: qcom,ids: Add SoC ID for Snapdragon SDM 850
From: David Heidelberg via B4 Relay @ 2026-06-27 17:50 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, David Heidelberg
In-Reply-To: <20260627-sda850-v2-0-44bf46ade42e@ixit.cz>
From: David Heidelberg <david@ixit.cz>
Add SoC ID for Qualcomm Snapdragon SDM850.
Signed-off-by: David Heidelberg <david@ixit.cz>
---
include/dt-bindings/arm/qcom,ids.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
index 1af73c0ad41cd..2cf433f61d5e7 100644
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -179,16 +179,17 @@
#define QCOM_ID_SDM450 338
#define QCOM_ID_SM8150 339
#define QCOM_ID_SDA845 341
#define QCOM_ID_IPQ8072 342
#define QCOM_ID_IPQ8076 343
#define QCOM_ID_IPQ8078 344
#define QCOM_ID_SDM636 345
#define QCOM_ID_SDA636 346
+#define QCOM_ID_SDM850 348
#define QCOM_ID_SDM632 349
#define QCOM_ID_SDA632 350
#define QCOM_ID_SDA450 351
#define QCOM_ID_SDM439 353
#define QCOM_ID_SDM429 354
#define QCOM_ID_SM8250 356
#define QCOM_ID_SA8155 362
#define QCOM_ID_SDA439 363
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v3 0/2] iio: magnetometer: add support for Melexis MLX90393
From: David Lechner @ 2026-06-27 18:30 UTC (permalink / raw)
To: Nikhil Gautam, linux-iio
Cc: jic23, nuno.sa, andy, u.kleine-koenig, robh, krzk+dt, conor+dt,
devicetree, linux-kernel
In-Reply-To: <20260627005843.7786-1-nikhilgtr@gmail.com>
On 6/26/26 7:58 PM, Nikhil Gautam wrote:
> Subject: [PATCH v3 0/2] iio: magnetometer: add support for Melexis MLX90393
>
It is best not to manually edit the emails before sending. Somehow the
subject ended up in the email body.
^ permalink raw reply
* Re: [PATCH v3 1/2] dt-bindings: iio: magnetometer: add Melexis MLX90393
From: David Lechner @ 2026-06-27 18:41 UTC (permalink / raw)
To: Nikhil Gautam, linux-iio
Cc: jic23, nuno.sa, andy, u.kleine-koenig, robh, krzk+dt, conor+dt,
devicetree, linux-kernel
In-Reply-To: <20260627005843.7786-2-nikhilgtr@gmail.com>
On 6/26/26 7:58 PM, Nikhil Gautam wrote:
> Add devicetree bindings for the Melexis MLX90393
> 3-axis magnetometer and temperature sensor.
>
> The device supports magnetic field and temperature
> measurements over I2C and SPI interfaces.
>
> This initial binding documents the I2C interface.
>
> Signed-off-by: Nikhil Gautam <nikhilgtr@gmail.com>
> ---
> .../iio/magnetometer/melexis,mlx90393.yaml | 54 +++++++++++++++++++
> MAINTAINERS | 6 +++
> 2 files changed, 60 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/magnetometer/melexis,mlx90393.yaml
>
> diff --git a/Documentation/devicetree/bindings/iio/magnetometer/melexis,mlx90393.yaml b/Documentation/devicetree/bindings/iio/magnetometer/melexis,mlx90393.yaml
> new file mode 100644
> index 000000000000..33ab0be66345
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/magnetometer/melexis,mlx90393.yaml
> @@ -0,0 +1,54 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/magnetometer/melexis,mlx90393.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Melexis MLX90393 magnetometer sensor
> +
> +maintainers:
> + - Nikhil Gautam <nikhilgtr@gmail.com>
> +
> +description:
> + Melexis MLX90393 3-axis magnetometer and temperature sensor.
> +
> +properties:
> + compatible:
> + const: melexis,mlx90393
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + trigger-gpios:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - vdd-supply
> + - vddio-supply
The supplies are required but are missing from the properties and the
example. Running `make dt_binding_check` before sending would have caught
this.
See: https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + i2c {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + magnetometer@c {
> + compatible = "melexis,mlx90393";
> + reg = <0x0c>;
> +
> + interrupt-parent = <&gpio>;
> + interrupts = <17 IRQ_TYPE_EDGE_RISING>;
> +
> + trigger-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a92290fffa16..469ae3f9aa0f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -15501,6 +15501,12 @@ F: Documentation/scsi/megaraid.rst
> F: drivers/scsi/megaraid.*
> F: drivers/scsi/megaraid/
>
> +MELEXIS MLX90393 MAGNETOMETER DRIVER
> +M: Nikhil Gautam <nikhilgtr@gmail.com>
> +L: linux-iio@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/iio/magnetometer/melexis,mlx90393.yaml
> +
> MELEXIS MLX90614 DRIVER
> M: Crt Mori <cmo@melexis.com>
> L: linux-iio@vger.kernel.org
^ permalink raw reply
* Re: [PATCH v2 2/3] arm64: dts: qcom: Add HP EliteBook X G2q 14 AI
From: t @ 2026-06-27 18:55 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Jason Pettit, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Akhil P Oommen, Mahadevan P, Sibi Sankar, Jingyi Wang,
Ananthu C V
In-Reply-To: <c6966f05-b1bb-4b71-8373-c90995ab4cc3@oss.qualcomm.com>
From: Jason Pettit <jason.pettit@oss.qualcomm.com>
On Fri, 26 Jun 2026 13:27:42 +0200, Konrad Dybcio wrote:
> If you remove these two nodes, the QMPPHY-as-DP-only should still
> function (it's the USB3 block that depends on the QMPPHY, not the
> other way around)
I boot-tested this. With &usb_2 and &usb_2_hsphy removed, dmesg still
shows the af64000 DP controller binding and /sys/class/drm shows the
HDMI-A-1 connector as connected, but nothing is displayed on the attached
monitor. With both nodes present, the monitor shows an image.
So removing them stops HDMI from working on this board.
The comment in v3 will be updated to read:
/* usb_2's combo PHY drives the HDMI bridge over DP; keep the dwc3 enabled. */
Thanks,
Jason
^ permalink raw reply
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