* [RFC PATCH 3/9] pmdomain/rockchip: cycle optional power-domain resets on power-on
From: Jiaxing Hu @ 2026-07-17 8:50 UTC (permalink / raw)
To: tomeu, heiko, robh, krzk+dt, conor+dt, joro, will, robin.murphy,
ulfh, p.zabel, ogabbay
Cc: dri-devel, linux-rockchip, iommu, linux-pm, devicetree,
linux-arm-kernel, linux-kernel, Jiaxing Hu
In-Reply-To: <20260717085220.3212274-1-gahing@gahingwoo.com>
Some power domains contain hardware bus interfaces that require an
explicit assert/deassert edge on their reset line after the domain
is powered on. The CRU preserves reset state across power cycles
(stays deasserted), so the hardware never sees the edge it needs to
initialize unless the driver pulses it explicitly.
Add an optional resets property to rockchip_pm_domain. When present,
the resets are asserted and deasserted (with a 10 µs hold) inside
rockchip_pd_power() after the idle bits are cleared and the
delay_us settling time has elapsed, but before any device in the
domain resumes. This ordering guarantees the bus is fully
initialized before any device driver accesses registers.
Signed-off-by: Jiaxing Hu <gahing@gahingwoo.com>
---
drivers/pmdomain/rockchip/pm-domains.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
index 1787f62ba..7a88a9149 100644
--- a/drivers/pmdomain/rockchip/pm-domains.c
+++ b/drivers/pmdomain/rockchip/pm-domains.c
@@ -18,6 +18,7 @@
#include <linux/of_address.h>
#include <linux/of_clk.h>
#include <linux/clk.h>
+#include <linux/reset.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/mfd/syscon.h>
@@ -102,6 +103,7 @@ struct rockchip_pm_domain {
struct clk_bulk_data *clks;
struct device_node *node;
struct regulator *supply;
+ struct reset_control *resets;
};
struct rockchip_pmu {
@@ -671,6 +673,12 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
if (pd->info->delay_us)
udelay(pd->info->delay_us);
+ if (pd->resets) {
+ reset_control_assert(pd->resets);
+ udelay(10);
+ reset_control_deassert(pd->resets);
+ }
+
rockchip_pmu_restore_qos(pd);
}
@@ -840,6 +848,14 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
if (error)
goto err_put_clocks;
+ pd->resets = of_reset_control_array_get_optional_exclusive(node);
+ if (IS_ERR(pd->resets)) {
+ error = PTR_ERR(pd->resets);
+ dev_err(pmu->dev, "%pOFn: failed to get resets: %d\n", node, error);
+ pd->resets = NULL;
+ goto err_unprepare_clocks;
+ }
+
pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
NULL);
@@ -910,6 +926,7 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
clk_bulk_unprepare(pd->num_clks, pd->clks);
err_put_clocks:
clk_bulk_put(pd->num_clks, pd->clks);
+ reset_control_put(pd->resets);
return error;
}
--
2.43.0
^ permalink raw reply related
* [RFC PATCH 2/9] pmdomain/rockchip: add optional per-domain power-on settle delay
From: Jiaxing Hu @ 2026-07-17 8:50 UTC (permalink / raw)
To: tomeu, heiko, robh, krzk+dt, conor+dt, joro, will, robin.murphy,
ulfh, p.zabel, ogabbay
Cc: dri-devel, linux-rockchip, iommu, linux-pm, devicetree,
linux-arm-kernel, linux-kernel, Jiaxing Hu
In-Reply-To: <20260717085220.3212274-1-gahing@gahingwoo.com>
The RK3576 NPU domains need a short settle time after the idle
request is released before the QoS registers behind the domain are
written: restoring QoS immediately after de-idle can raise an SError
on the register access while the NoC is still settling (observed on
ROCK 4D as a panic inside rockchip_pd_power() during NPU runtime-PM
cycling).
The vendor kernel handles this with a per-domain delay_us field
applied between the de-idle request and the QoS restore, carrying
15us for the RK3576 NPUTOP domain. Mirror that: add delay_us to
rockchip_domain_info, honor it in rockchip_pd_power() right before
rockchip_pmu_restore_qos(), and set 15us for NPUTOP, NPU0 and NPU1
(the two core domains power-cycle constantly under runtime PM and
showed the same symptom during bring-up). All other domains keep 0,
so nothing changes for them.
Signed-off-by: Jiaxing Hu <gahing@gahingwoo.com>
---
drivers/pmdomain/rockchip/pm-domains.c | 51 ++++++++++++++------------
1 file changed, 28 insertions(+), 23 deletions(-)
diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
index 490bbb1d1..1787f62ba 100644
--- a/drivers/pmdomain/rockchip/pm-domains.c
+++ b/drivers/pmdomain/rockchip/pm-domains.c
@@ -59,6 +59,7 @@ struct rockchip_domain_info {
u32 pwr_offset;
u32 mem_offset;
u32 req_offset;
+ u32 delay_us;
};
struct rockchip_pmu_info {
@@ -185,7 +186,7 @@ struct rockchip_pmu {
.need_regulator = regulator, \
}
-#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup) \
+#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, delay, wakeup) \
{ \
.name = _name, \
.pwr_offset = p_offset, \
@@ -200,6 +201,7 @@ struct rockchip_pmu {
.req_mask = (req), \
.idle_mask = (idle), \
.clk_ungate_mask = (g_mask), \
+ .delay_us = (delay), \
.ack_mask = (ack), \
.active_wakeup = wakeup, \
}
@@ -244,8 +246,8 @@ struct rockchip_pmu {
#define DOMAIN_RK3568(name, pwr, req, wakeup) \
DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
-#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
- DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup)
+#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, delay, wakeup) \
+ DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, delay, wakeup)
/*
* Dynamic Memory Controller may need to coordinate with us -- see
@@ -612,7 +614,6 @@ static int rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
return ret;
}
-
ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
is_on == on, 0, 10000);
if (ret) {
@@ -667,6 +668,9 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
if (ret < 0)
goto out;
+ if (pd->info->delay_us)
+ udelay(pd->info->delay_us);
+
rockchip_pmu_restore_qos(pd);
}
@@ -1286,25 +1290,26 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = {
};
static const struct rockchip_domain_info rk3576_pm_domains[] = {
- [RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, 0, false),
- [RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), BIT(2), false),
- [RK3576_PD_SDGMAC] = DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(7), 0x4, BIT(1), BIT(17), 0x6, false),
- [RK3576_PD_AUDIO] = DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8), 0x4, BIT(0), BIT(16), BIT(0), false),
- [RK3576_PD_PHP] = DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9), 0x0, BIT(15), BIT(15), BIT(15), false),
- [RK3576_PD_SUBPHP] = DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(10), 0x0, 0, 0, 0, false),
- [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, false),
- [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, false),
- [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, false),
- [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, true),
- [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), false),
- [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, false),
- [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), false),
- [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), false),
- [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), false),
- [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, false),
- [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, false),
- [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, false),
- [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
+ /* name p_offset pwr status r_status r_offset req idle g_mask delay wakeup */
+ [RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, 0, 0, false),
+ [RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), BIT(2), 0, false),
+ [RK3576_PD_SDGMAC] = DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(7), 0x4, BIT(1), BIT(17), 0x6, 0, false),
+ [RK3576_PD_AUDIO] = DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8), 0x4, BIT(0), BIT(16), BIT(0), 0, false),
+ [RK3576_PD_PHP] = DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9), 0x0, BIT(15), BIT(15), BIT(15), 0, false),
+ [RK3576_PD_SUBPHP] = DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(10), 0x0, 0, 0, 0, 0, false),
+ [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, 0, false),
+ [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, 0, false),
+ [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, 0, false),
+ [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, 0, true),
+ [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), 0, false),
+ [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, 0, false),
+ [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), 0, false),
+ [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), 0, false),
+ [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), 0, false),
+ [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, 15, false),
+ [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, 15, false),
+ [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, 15, false),
+ [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), 0, false),
};
static const struct rockchip_domain_info rk3588_pm_domains[] = {
--
2.43.0
^ permalink raw reply related
* [RFC PATCH 1/9] dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core
From: Jiaxing Hu @ 2026-07-17 8:50 UTC (permalink / raw)
To: tomeu, heiko, robh, krzk+dt, conor+dt, joro, will, robin.murphy,
ulfh, p.zabel, ogabbay
Cc: dri-devel, linux-rockchip, iommu, linux-pm, devicetree,
linux-arm-kernel, linux-kernel, Jiaxing Hu
In-Reply-To: <20260717085220.3212274-1-gahing@gahingwoo.com>
Document the RK3576 NPU core: add rockchip,rk3576-rknn-core to the
compatible enum and drop sram-supply from required (RK3576 has no NPU
SRAM supply).
Signed-off-by: Jiaxing Hu <gahing@gahingwoo.com>
---
.../devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
index caca2a490..d904db3bf 100644
--- a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
+++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
@@ -21,6 +21,7 @@ properties:
compatible:
enum:
+ - rockchip,rk3576-rknn-core
- rockchip,rk3588-rknn-core
reg:
@@ -75,7 +76,6 @@ required:
- resets
- reset-names
- npu-supply
- - sram-supply
additionalProperties: false
--
2.43.0
^ permalink raw reply related
* [RFC PATCH 0/9] accel/rocket: RK3576 NPU (RKNN) enablement
From: Jiaxing Hu @ 2026-07-17 8:50 UTC (permalink / raw)
To: tomeu, heiko, robh, krzk+dt, conor+dt, joro, will, robin.murphy,
ulfh, p.zabel, ogabbay
Cc: dri-devel, linux-rockchip, iommu, linux-pm, devicetree,
linux-arm-kernel, linux-kernel, Jiaxing Hu
This adds RK3576 NPU support to accel/rocket. RFC: the NPU brings up and
runs, but full inference is not correct yet, and I would rather get
feedback now than sit on it.
Tested on a Radxa ROCK 4D. The NPU probes, powers on, brings up its
IOMMUs, and runs jobs to completion (rocket + Mesa Teflon). Getting there
took a few fixes outside the driver too: a power-domain settle delay and
reset cycling (else a cold power-on throws an async SError), two rk_iommu
fixes for banks firmware leaves faulted, taking the full clock set on the
MMU nodes, and both NPU power domains on the core.
Not solved: only the first operation in a power session gives the right
answer. Every later one engages and DMAs its input, but the compute
output never lands, so the readback is the zero-point. I chased it
through the whole software surface (registers, IOMMU/TLB, cache,
power/clock/reset, dispatch) and it reproduces even with the driver
environment matched to the vendor's on the same kernel, so it looks to be
below software, in the fixed-function block. Traces available.
Two asks: review of the bring-up and the shared pmdomain/iommu changes;
and if anyone knows the RK3576 NPU internals, whether that
per-power-session arm can be driven from software at all.
The series is split by subsystem (binding, pmdomain, iommu, driver, DT).
The board DT keeps vdd_npu_s0 always-on for now; happy to switch to
proper runtime control if preferred.
I used Claude Opus 4.8 to help trim this series out of my debugging tree
and generate the diffs.
Jiaxing Hu (9):
dt-bindings: npu: rockchip: add rockchip,rk3576-rknn-core
pmdomain/rockchip: add optional per-domain power-on settle delay
pmdomain/rockchip: cycle optional power-domain resets on power-on
iommu/rockchip: skip orphaned-fault banks in rk_iommu_is_stall_active
iommu/rockchip: skip orphaned-fault banks in CMD_ENABLE_STALL dispatch
iommu/rockchip: take all DT clocks
accel/rocket: add RK3576 NPU (RKNN) support
arm64: dts: rockchip: rk3576: add NPU (RKNN) nodes
arm64: dts: rockchip: rk3576-rock-4d: enable NPU
.../npu/rockchip,rk3588-rknn-core.yaml | 2 +-
.../boot/dts/rockchip/rk3576-rock-4d.dts | 16 ++
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 78 ++++++++-
drivers/accel/rocket/rocket_core.c | 43 ++++-
drivers/accel/rocket/rocket_core.h | 22 ++-
drivers/accel/rocket/rocket_device.c | 4 +
drivers/accel/rocket/rocket_drv.c | 1 +
drivers/accel/rocket/rocket_job.c | 154 ++++++++++++++----
drivers/iommu/rockchip-iommu.c | 66 +++++---
drivers/pmdomain/rockchip/pm-domains.c | 68 +++++---
10 files changed, 367 insertions(+), 87 deletions(-)
--
2.43.0
^ permalink raw reply
* Re: [PATCH v6 4/4] arm64: dts: qcom: add SoCCP DT node for Glymur
From: Konrad Dybcio @ 2026-07-17 8:50 UTC (permalink / raw)
To: Ananthu C V, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Jingyi Wang,
Taniya Das, Maulik Shah, Abel Vesa, Qiang Yu, Sibi Sankar,
Pankaj Patil, Jishnu Prakash
Cc: linux-arm-msm, devicetree, linux-kernel, linux-remoteproc,
Krzysztof Kozlowski, Jyothi Kumar Seerapu, Raviteja Laggyshetty,
Dmitry Baryshkov
In-Reply-To: <20260709-glymur-soccp-v6-4-16f70227547d@oss.qualcomm.com>
On 7/10/26 8:39 AM, Ananthu C V wrote:
> From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>
> The SoC Control Processor (SoCCP) is a small RISC-V MCU that controls
> USB Type-C, battery charging, and various other functions on Qualcomm SoCs.
>
> Add the nodes required to enable SoCCP on Glymur/Mahua SoCs.
>
> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> Co-developed-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH v6 3/4] arm64: dts: qcom: fix SoCCP memory mappings for Glymur
From: Konrad Dybcio @ 2026-07-17 8:49 UTC (permalink / raw)
To: Ananthu C V, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Mathieu Poirier, Jingyi Wang,
Taniya Das, Maulik Shah, Abel Vesa, Qiang Yu, Sibi Sankar,
Pankaj Patil, Jishnu Prakash
Cc: linux-arm-msm, devicetree, linux-kernel, linux-remoteproc,
Krzysztof Kozlowski, Jyothi Kumar Seerapu, Raviteja Laggyshetty,
Dmitry Baryshkov
In-Reply-To: <20260709-glymur-soccp-v6-3-16f70227547d@oss.qualcomm.com>
On 7/10/26 8:39 AM, Ananthu C V wrote:
> The currently listed SoCCP and SoCCP DTB reserved memory regions
> don't align with the memory requested by the SoCCP Firmware. Fix
> this by updating the SoCCP/SoCCP DTB memory regions to reflect the
> memory region requirements of the SoCCP firmware, as described in
> the Glymur v21 memory map release.
>
> Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi")
> Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH v5 3/3] arm64: dts: qcom: add SoCCP DT node for Glymur
From: Ananthu C V @ 2026-07-17 8:46 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mathieu Poirier, linux-arm-msm, devicetree,
linux-kernel, linux-remoteproc, Sibi Sankar
In-Reply-To: <fe8f8696-d78c-4b80-8fb5-3978178533b7@oss.qualcomm.com>
Hi Konrad,
On Thu, Jul 16, 2026 at 04:49:24PM +0200, Konrad Dybcio wrote:
> On 7/7/26 12:12 PM, Ananthu C V wrote:
> > From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> >
> > The SoC Control Processor (SoCCP) is a small RISC-V MCU that controls
> > USB Type-C, battery charging, and various other functions on Qualcomm SoCs.
> >
> > Add the nodes required to enable SoCCP on Glymur/Mahua SoCs.
> >
> > Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> > Co-developed-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> > Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> > ---
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Thanks for the review. However there is a v6 of this series addressing few things
from this v5, and this patch also has changes. Please review the v6 instead.
v6 link: https://lore.kernel.org/all/20260709-glymur-soccp-v6-0-16f70227547d@oss.qualcomm.com/
> Konrad
Best,
Ananthu
^ permalink raw reply
* [PATCH v3 4/4] regulator: axp20x: add support for the AXP318W
From: Jerome Brunet @ 2026-07-17 8:44 UTC (permalink / raw)
To: Andre Przywara, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Liam Girdwood, Mark Brown
Cc: devicetree, linux-kernel, Jerome Brunet
In-Reply-To: <20260717-axp318-regulator-v3-0-779dc1b97dd4@baylibre.com>
From: Andre Przywara <andre.przywara@arm.com>
The X-Powers AXP318W is a typical PMIC from X-Powers, featuring nine
DC/DC converters and 28 LDOs, on the regulator side.
Describe the chip's voltage settings and switch registers, how the
voltages are encoded, and connect this to the MFD device via its
regulator ID.
We use just "318" for the internal identifiers, for easier typing and
less churn. If something else other than the "AXP318W" shows up, that's
an easy change, externally visible strings carry the additional letter
already.
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Co-developed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/regulator/axp20x-regulator.c | 298 +++++++++++++++++++++++++++++++++--
include/linux/mfd/axp20x.h | 44 ++++++
2 files changed, 333 insertions(+), 9 deletions(-)
diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
index da891415efc0..6f887250d640 100644
--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
@@ -138,6 +138,27 @@
#define AXP313A_DCDC_V_OUT_MASK GENMASK(6, 0)
#define AXP313A_LDO_V_OUT_MASK GENMASK(4, 0)
+#define AXP318_DCDC1_V_OUT_MASK GENMASK(4, 0)
+#define AXP318_DCDC2_V_OUT_MASK GENMASK(6, 0)
+#define AXP318_LDO_V_OUT_MASK GENMASK(4, 0)
+#define AXP318_ELDO_V_OUT_MASK GENMASK(5, 0)
+#define AXP318_THRESHOLD_VOLTAGE 1540000
+/*
+ * FIXME:
+ * Some LDOs of the AXP318 may be fed by different supplies and
+ * the documentation repeatedly warns that output voltage must
+ * be less than the supply, which is the case for any LDO really.
+ *
+ * The best way to let the framework handle this is to set the
+ * min_dropout_uV field. However the AXP318 documentation
+ * does not provide any information about this.
+ *
+ * Realistically, it can't be less than 1uV so use this
+ * for all LDOs until we know more.
+ */
+#define AXP318_LDO_MIN_DROPOUT 1 /* uV */
+
+
#define AXP717_DCDC1_NUM_VOLTAGES 88
#define AXP717_DCDC2_NUM_VOLTAGES 107
#define AXP717_DCDC3_NUM_VOLTAGES 103
@@ -371,8 +392,8 @@
.ops = &axp20x_ops, \
}
-#define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
- _vmask, _ereg, _emask) \
+#define AXP_DESC_EXT(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask, _ops, _bpreg, _bpmask, _dropout) \
[_family##_##_id] = { \
.name = (_match), \
.supply_name = (_supply), \
@@ -384,13 +405,32 @@
.owner = THIS_MODULE, \
.min_uV = (_min) * 1000, \
.uV_step = (_step) * 1000, \
+ .min_dropout_uV = (_dropout), \
.vsel_reg = (_vreg), \
.vsel_mask = (_vmask), \
.enable_reg = (_ereg), \
.enable_mask = (_emask), \
- .ops = &axp20x_ops, \
+ .bypass_reg = (_bpreg), \
+ .bypass_mask = (_bpmask), \
+ .ops = (_ops), \
}
+#define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask) \
+ AXP_DESC_EXT(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask, &axp20x_ops, 0, 0, 0)
+
+#define AXP_DESC_DO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask, _dropout) \
+ AXP_DESC_EXT(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask, &axp20x_ops, 0, 0, _dropout)
+
+#define AXP_DESC_BYPASS(_family, _id, _match, _supply, _min, _max, _step, _vreg,\
+ _vmask, _ereg, _emask, _bpreg, _bpmask, _dropout) \
+ AXP_DESC_EXT(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask, &axp20x_bypass_ops, _bpreg, \
+ _bpmask, _dropout)
+
#define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \
[_family##_##_id] = { \
.name = (_match), \
@@ -419,8 +459,9 @@
.ops = &axp20x_ops_fixed \
}
-#define AXP_DESC_RANGES_DELAY(_family, _id, _match, _supply, _ranges, _n_voltages, \
- _vreg, _vmask, _ereg, _emask, _ramp_delay) \
+#define AXP_DESC_RANGES_DELAY_OPS(_family, _id, _match, _supply, _ranges, \
+ _n_voltages, _vreg, _vmask, _ereg, _emask, \
+ _ramp_delay, _ops) \
[_family##_##_id] = { \
.name = (_match), \
.supply_name = (_supply), \
@@ -436,10 +477,23 @@
.enable_mask = (_emask), \
.linear_ranges = (_ranges), \
.n_linear_ranges = ARRAY_SIZE(_ranges), \
- .ramp_delay = (_ramp_delay), \
- .ops = &axp20x_ops_range, \
+ .ramp_delay = (_ramp_delay), \
+ .ops = (_ops), \
}
+#define AXP_DESC_RANGES_THRESHOLD(_family, _id, _match, _supply, _ranges, \
+ _n_voltages, _vreg, _vmask, _ereg, _emask) \
+ AXP_DESC_RANGES_DELAY_OPS(_family, _id, _match, _supply, _ranges, \
+ _n_voltages, _vreg, _vmask, _ereg, _emask, \
+ 0, &axp318_threshold_ops_range)
+
+#define AXP_DESC_RANGES_DELAY(_family, _id, _match, _supply, _ranges, \
+ _n_voltages, _vreg, _vmask, _ereg, _emask, \
+ _ramp_delay) \
+ AXP_DESC_RANGES_DELAY_OPS(_family, _id, _match, _supply, _ranges, \
+ _n_voltages, _vreg, _vmask, _ereg, _emask, \
+ _ramp_delay, &axp20x_ops_range)
+
#define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \
_vreg, _vmask, _ereg, _emask) \
AXP_DESC_RANGES_DELAY(_family, _id, _match, _supply, _ranges, \
@@ -567,6 +621,50 @@ static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev)
return regulator_enable_regmap(rdev);
};
+static int axp318_threshold_check(struct regulator_dev *rdev,
+ unsigned int sel)
+{
+ int old_sel, old_uV, new_uV, enabled;
+
+ /* Only applicable if the regulator is enabled */
+ enabled = rdev->desc->ops->is_enabled(rdev);
+ if (enabled <= 0)
+ return enabled;
+
+ old_sel = rdev->desc->ops->get_voltage_sel(rdev);
+ if (old_sel < 0)
+ return old_sel;
+
+ old_uV = rdev->desc->ops->list_voltage(rdev, old_sel);
+ if (old_uV < 0)
+ return old_uV;
+
+ new_uV = rdev->desc->ops->list_voltage(rdev, sel);
+ if (new_uV < 0)
+ return new_uV;
+
+ /* Crossing the threshold ? */
+ if ((old_uV <= AXP318_THRESHOLD_VOLTAGE
+ && new_uV > AXP318_THRESHOLD_VOLTAGE) ||
+ (new_uV <= AXP318_THRESHOLD_VOLTAGE
+ && old_uV > AXP318_THRESHOLD_VOLTAGE))
+ return -EBUSY;
+
+ return 0;
+}
+
+static int axp318_threshold_set_voltage_sel(struct regulator_dev *rdev,
+ unsigned int sel)
+{
+ int ret;
+
+ ret = axp318_threshold_check(rdev, sel);
+ if (ret < 0)
+ return ret;
+
+ return regulator_set_voltage_sel_regmap(rdev, sel);
+}
+
static const struct regulator_ops axp20x_ops_fixed = {
.list_voltage = regulator_list_voltage_linear,
};
@@ -580,6 +678,15 @@ static const struct regulator_ops axp20x_ops_range = {
.is_enabled = regulator_is_enabled_regmap,
};
+static const struct regulator_ops axp318_threshold_ops_range = {
+ .set_voltage_sel = axp318_threshold_set_voltage_sel,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .list_voltage = regulator_list_voltage_linear_range,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+};
+
static const struct regulator_ops axp20x_ops = {
.set_voltage_sel = regulator_set_voltage_sel_regmap,
.get_voltage_sel = regulator_get_voltage_sel_regmap,
@@ -590,6 +697,19 @@ static const struct regulator_ops axp20x_ops = {
.set_ramp_delay = axp20x_set_ramp_delay,
};
+static const struct regulator_ops axp20x_bypass_ops = {
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .list_voltage = regulator_list_voltage_linear,
+ .enable = axp20x_regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .set_ramp_delay = axp20x_set_ramp_delay,
+ .get_bypass = regulator_get_bypass_regmap,
+ .set_bypass = regulator_set_bypass_regmap,
+};
+
+
static const struct regulator_ops axp20x_ops_sw = {
.enable = regulator_enable_regmap,
.disable = regulator_disable_regmap,
@@ -765,6 +885,158 @@ static const struct regulator_desc axp313a_regulators[] = {
AXP_DESC_FIXED(AXP313A, RTC_LDO, "rtc-ldo", "vin1", 1800),
};
+static const struct linear_range axp318_dcdc2_ranges[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
+ REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),
+};
+
+static const struct linear_range axp318_dcdc6_ranges[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
+ REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),
+ REGULATOR_LINEAR_RANGE(1800000, 88, 118, 20000),
+ REGULATOR_LINEAR_RANGE(2440000, 119, 127, 40000),
+};
+
+static const struct linear_range axp318_dcdc7_ranges[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
+ REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000),
+};
+
+static const struct linear_range axp318_dcdc8_ranges[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
+ REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000),
+ REGULATOR_LINEAR_RANGE(1900000, 103, 118, 100000),
+};
+
+static const struct regulator_desc axp318_regulators[] = {
+ AXP_DESC(AXP318, DCDC1, "dcdc1", "vin19", 1000, 3400, 100,
+ AXP318_DCDC1_CONTROL, AXP318_DCDC1_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(0)),
+ AXP_DESC_RANGES(AXP318, DCDC2, "dcdc2", "vin23",
+ axp318_dcdc2_ranges, 88,
+ AXP318_DCDC2_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(1)),
+ AXP_DESC_RANGES(AXP318, DCDC3, "dcdc3", "vin23",
+ axp318_dcdc2_ranges, 88,
+ AXP318_DCDC3_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(2)),
+ AXP_DESC_RANGES(AXP318, DCDC4, "dcdc4", "vin45",
+ axp318_dcdc2_ranges, 88,
+ AXP318_DCDC4_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(3)),
+ AXP_DESC_RANGES(AXP318, DCDC5, "dcdc5", "vin45",
+ axp318_dcdc2_ranges, 88,
+ AXP318_DCDC5_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(4)),
+ AXP_DESC_RANGES_THRESHOLD(AXP318, DCDC6, "dcdc6", "vin678",
+ axp318_dcdc6_ranges, 128,
+ AXP318_DCDC6_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(5)),
+ AXP_DESC_RANGES_THRESHOLD(AXP318, DCDC7, "dcdc7", "vin678",
+ axp318_dcdc7_ranges, 103,
+ AXP318_DCDC7_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(6)),
+ AXP_DESC_RANGES_THRESHOLD(AXP318, DCDC8, "dcdc8", "vin678",
+ axp318_dcdc8_ranges, 119,
+ AXP318_DCDC8_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(7)),
+ AXP_DESC_RANGES_THRESHOLD(AXP318, DCDC9, "dcdc9", "vin19",
+ axp318_dcdc8_ranges, 119,
+ AXP318_DCDC9_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL2, BIT(0)),
+ AXP_DESC_SW(AXP318, SWOUT1, "swout1", NULL,
+ AXP318_DCDC_OUTPUT_CONTROL2, BIT(3)),
+ AXP_DESC_SW(AXP318, SWOUT2, "swout2", NULL,
+ AXP318_DCDC_OUTPUT_CONTROL2, BIT(4)),
+ AXP_DESC_DO(AXP318, ALDO1, "aldo1", "aldo156in", 500, 3400, 100,
+ AXP318_ALDO1_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(0), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ALDO2, "aldo2", "aldo234in", 500, 3400, 100,
+ AXP318_ALDO2_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(1), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ALDO3, "aldo3", "aldo234in", 500, 3400, 100,
+ AXP318_ALDO3_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(2), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ALDO4, "aldo4", "aldo234in", 500, 3400, 100,
+ AXP318_ALDO4_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(3), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ALDO5, "aldo5", "aldo156in", 500, 3400, 100,
+ AXP318_ALDO5_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(4), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ALDO6, "aldo6", "aldo156in", 500, 3400, 100,
+ AXP318_ALDO6_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(5), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, BLDO1, "bldo1", "bldoin", 500, 3400, 100,
+ AXP318_BLDO1_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(6), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, BLDO2, "bldo2", "bldoin", 500, 3400, 100,
+ AXP318_BLDO2_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(7), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, BLDO3, "bldo3", "bldoin", 500, 3400, 100,
+ AXP318_BLDO3_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(0), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, BLDO4, "bldo4", "bldoin", 500, 3400, 100,
+ AXP318_BLDO4_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(1), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, BLDO5, "bldo5", "bldoin", 500, 3400, 100,
+ AXP318_BLDO5_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(2), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, CLDO1, "cldo1", "cldoin", 500, 3400, 100,
+ AXP318_CLDO1_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(3), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, CLDO2, "cldo2", "cldoin", 500, 3400, 100,
+ AXP318_CLDO2_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(4), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, CLDO3, "cldo3", "cldoin", 500, 3400, 100,
+ AXP318_CLDO3_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(5), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, CLDO4, "cldo4", "cldoin", 500, 3400, 100,
+ AXP318_CLDO4_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(6), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, CLDO5, "cldo5", "cldoin", 500, 3400, 100,
+ AXP318_CLDO5_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(7), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, DLDO1, "dldo1", "dldoin", 500, 3400, 100,
+ AXP318_DLDO1_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(0), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, DLDO2, "dldo2", "dldoin", 500, 3400, 100,
+ AXP318_DLDO2_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(1), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, DLDO3, "dldo3", "dldoin", 500, 3400, 100,
+ AXP318_DLDO3_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(2), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, DLDO4, "dldo4", "dldoin", 500, 3400, 100,
+ AXP318_DLDO4_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(3), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, DLDO5, "dldo5", "dldoin", 500, 3400, 100,
+ AXP318_DLDO5_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(4), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, DLDO6, "dldo6", "dldoin", 500, 3400, 100,
+ AXP318_DLDO6_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(5), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ELDO1, "eldo1", "eldoin", 500, 1500, 25,
+ AXP318_ELDO1_CONTROL, AXP318_ELDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(6), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ELDO2, "eldo2", "eldoin", 500, 1500, 25,
+ AXP318_ELDO2_CONTROL, AXP318_ELDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(7), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ELDO3, "eldo3", "eldoin", 500, 1500, 25,
+ AXP318_ELDO3_CONTROL, AXP318_ELDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL4, BIT(0), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_BYPASS(AXP318, ELDO4, "eldo4", "eldoin", 500, 1500, 25,
+ AXP318_ELDO4_CONTROL, AXP318_ELDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL4, BIT(1),
+ AXP318_ELDO4_CONTROL, BIT(6), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_BYPASS(AXP318, ELDO5, "eldo5", "eldoin", 500, 1500, 25,
+ AXP318_ELDO5_CONTROL, AXP318_ELDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL4, BIT(2),
+ AXP318_ELDO5_CONTROL, BIT(6), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ELDO6, "eldo6", "eldoin", 500, 1500, 25,
+ AXP318_ELDO6_CONTROL, AXP318_ELDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL4, BIT(3), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_FIXED(AXP318, RTC_LDO, "rtc-ldo", "ips", 1800),
+};
+
static const struct linear_range axp717_dcdc1_ranges[] = {
REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),
@@ -1347,6 +1619,7 @@ static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
step = 150;
break;
case AXP313A_ID:
+ case AXP318_ID:
case AXP323_ID:
case AXP717_ID:
case AXP15060_ID:
@@ -1585,6 +1858,10 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
regulators = axp313a_regulators;
nregulators = AXP313A_REG_ID_MAX;
break;
+ case AXP318_ID:
+ regulators = axp318_regulators;
+ nregulators = AXP318_REG_ID_MAX;
+ break;
case AXP717_ID:
regulators = axp717_regulators;
nregulators = AXP717_REG_ID_MAX;
@@ -1651,7 +1928,9 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||
(regulators == axp803_regulators && i == AXP803_DC1SW) ||
(regulators == axp809_regulators && i == AXP809_DC1SW) ||
- (regulators == axp15060_regulators && i == AXP15060_SW)) {
+ (regulators == axp15060_regulators && i == AXP15060_SW) ||
+ (regulators == axp318_regulators && i == AXP318_SWOUT1) ||
+ (regulators == axp318_regulators && i == AXP318_SWOUT2)) {
new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
GFP_KERNEL);
if (!new_desc)
@@ -1709,7 +1988,8 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
*/
if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
(regulators == axp809_regulators && i == AXP809_DCDC1) ||
- (regulators == axp15060_regulators && i == AXP15060_DCDC1))
+ (regulators == axp15060_regulators && i == AXP15060_DCDC1) ||
+ (regulators == axp318_regulators && i == AXP318_DCDC1))
of_property_read_string(rdev->dev.of_node,
"regulator-name",
&dcdc1_name);
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
index c1f9dc06387a..89001990106e 100644
--- a/include/linux/mfd/axp20x.h
+++ b/include/linux/mfd/axp20x.h
@@ -562,6 +562,50 @@ enum {
AXP313A_REG_ID_MAX,
};
+enum {
+ AXP318_DCDC1 = 0,
+ AXP318_DCDC2,
+ AXP318_DCDC3,
+ AXP318_DCDC4,
+ AXP318_DCDC5,
+ AXP318_DCDC6,
+ AXP318_DCDC7,
+ AXP318_DCDC8,
+ AXP318_DCDC9,
+ AXP318_ALDO1,
+ AXP318_ALDO2,
+ AXP318_ALDO3,
+ AXP318_ALDO4,
+ AXP318_ALDO5,
+ AXP318_ALDO6,
+ AXP318_BLDO1,
+ AXP318_BLDO2,
+ AXP318_BLDO3,
+ AXP318_BLDO4,
+ AXP318_BLDO5,
+ AXP318_CLDO1,
+ AXP318_CLDO2,
+ AXP318_CLDO3,
+ AXP318_CLDO4,
+ AXP318_CLDO5,
+ AXP318_DLDO1,
+ AXP318_DLDO2,
+ AXP318_DLDO3,
+ AXP318_DLDO4,
+ AXP318_DLDO5,
+ AXP318_DLDO6,
+ AXP318_ELDO1,
+ AXP318_ELDO2,
+ AXP318_ELDO3,
+ AXP318_ELDO4,
+ AXP318_ELDO5,
+ AXP318_ELDO6,
+ AXP318_SWOUT1,
+ AXP318_SWOUT2,
+ AXP318_RTC_LDO,
+ AXP318_REG_ID_MAX,
+};
+
enum {
AXP717_DCDC1 = 0,
AXP717_DCDC2,
--
2.47.3
^ permalink raw reply related
* [PATCH v3 3/4] mfd: axp20x: constify axp313 and axp717 cells
From: Jerome Brunet @ 2026-07-17 8:44 UTC (permalink / raw)
To: Andre Przywara, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Liam Girdwood, Mark Brown
Cc: devicetree, linux-kernel, Jerome Brunet
In-Reply-To: <20260717-axp318-regulator-v3-0-779dc1b97dd4@baylibre.com>
mfd_cells array should generally be const and there does not seem to be
anything against it for the axp313 and axp717.
Constify the mfd_cells array for the axp313 and axp717 to be consitent
with the other supported chips
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/mfd/axp20x.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index c8aeebd01bbc..2bbe73afff43 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -1123,7 +1123,7 @@ static const struct mfd_cell axp152_cells[] = {
},
};
-static struct mfd_cell axp313a_cells[] = {
+static const struct mfd_cell axp313a_cells[] = {
/* AXP323 is sometimes paired with AXP717 as sub-PMIC */
MFD_CELL_BASIC("axp20x-regulator", NULL, NULL, 0, 1),
MFD_CELL_RES("axp313a-pek", axp313a_pek_resources),
@@ -1133,7 +1133,7 @@ static const struct mfd_cell axp318_cells[] = {
MFD_CELL_BASIC("axp20x-regulator", NULL, NULL, 0, 1),
};
-static struct mfd_cell axp717_cells[] = {
+static const struct mfd_cell axp717_cells[] = {
MFD_CELL_NAME("axp20x-regulator"),
MFD_CELL_RES("axp20x-pek", axp717_pek_resources),
MFD_CELL_OF("axp717-adc",
--
2.47.3
^ permalink raw reply related
* [PATCH v3 2/4] mfd: axp20x: Add support for AXP318W PMIC
From: Jerome Brunet @ 2026-07-17 8:44 UTC (permalink / raw)
To: Andre Przywara, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Liam Girdwood, Mark Brown
Cc: devicetree, linux-kernel, Jerome Brunet
In-Reply-To: <20260717-axp318-regulator-v3-0-779dc1b97dd4@baylibre.com>
From: Andre Przywara <andre.przywara@arm.com>
The AXP318W is a PMIC chip produced by X-Powers, it can be connected to
an I2C bus.
It has a large number of regulators: 9(!) DCDC buck converters, and 28
LDOs, also some ADCs, interrupts, and a power key.
Describe the regmap and the MFD bits, along with the registers exposed
via I2C only. This covers the regulator, interrupts and power key
devices for now.
Advertise the device using the new compatible string.
We use just "318" for the internal identifiers, for easier typing and
less churn, but use "318W" for anything externally visible. If something
else other than the "AXP318W" shows up, that's an easy change then.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/mfd/axp20x-i2c.c | 2 ++
drivers/mfd/axp20x.c | 78 +++++++++++++++++++++++++++++++++++++++++
include/linux/mfd/axp20x.h | 86 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 166 insertions(+)
diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c
index 5c93136f977e..4e4ebfc78525 100644
--- a/drivers/mfd/axp20x-i2c.c
+++ b/drivers/mfd/axp20x-i2c.c
@@ -65,6 +65,7 @@ static const struct of_device_id axp20x_i2c_of_match[] = {
{ .compatible = "x-powers,axp221", .data = (void *)AXP221_ID },
{ .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
{ .compatible = "x-powers,axp313a", .data = (void *)AXP313A_ID },
+ { .compatible = "x-powers,axp318w", .data = (void *)AXP318_ID },
{ .compatible = "x-powers,axp323", .data = (void *)AXP323_ID },
{ .compatible = "x-powers,axp717", .data = (void *)AXP717_ID },
{ .compatible = "x-powers,axp803", .data = (void *)AXP803_ID },
@@ -83,6 +84,7 @@ static const struct i2c_device_id axp20x_i2c_id[] = {
{ "axp221" },
{ "axp223" },
{ "axp313a" },
+ { "axp318w" },
{ "axp717" },
{ "axp803" },
{ "axp806" },
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 679364189ea5..c8aeebd01bbc 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -42,6 +42,7 @@ static const char * const axp20x_model_names[] = {
[AXP223_ID] = "AXP223",
[AXP288_ID] = "AXP288",
[AXP313A_ID] = "AXP313a",
+ [AXP318_ID] = "AXP318W",
[AXP323_ID] = "AXP323",
[AXP717_ID] = "AXP717",
[AXP803_ID] = "AXP803",
@@ -218,6 +219,31 @@ static const struct regmap_access_table axp313a_volatile_table = {
.n_yes_ranges = ARRAY_SIZE(axp313a_volatile_ranges),
};
+static const struct regmap_range axp318_writeable_ranges[] = {
+ regmap_reg_range(AXP318_DCDC_OUTPUT_CONTROL1, AXP318_IRQ_STATE4),
+ regmap_reg_range(AXP318_SHUTDOWN_CTRL, AXP318_TEMP_ADC_H_EN),
+ regmap_reg_range(AXP318_DIE_TEMP_ADC_H_EN, AXP318_DIE_TEMP_ADC_H_EN),
+ regmap_reg_range(AXP318_GPADC_H_EN, AXP318_GPADC_H_EN),
+ regmap_reg_range(AXP318_GPIO_CTRL, AXP318_WDOG_CTRL),
+};
+
+static const struct regmap_range axp318_volatile_ranges[] = {
+ regmap_reg_range(AXP318_IRQ_EN1, AXP318_IRQ_STATE4),
+ regmap_reg_range(AXP318_POWER_REASON, AXP318_SHUTDOWN_REASON),
+ regmap_reg_range(AXP318_TEMP_ADC_H_EN, AXP318_GPADC_L),
+ regmap_reg_range(AXP318_GPIO_INPUT, AXP318_GPIO_INPUT),
+};
+
+static const struct regmap_access_table axp318_writeable_table = {
+ .yes_ranges = axp318_writeable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(axp318_writeable_ranges),
+};
+
+static const struct regmap_access_table axp318_volatile_table = {
+ .yes_ranges = axp318_volatile_ranges,
+ .n_yes_ranges = ARRAY_SIZE(axp318_volatile_ranges),
+};
+
static const struct regmap_range axp717_writeable_ranges[] = {
regmap_reg_range(AXP717_PMU_FAULT, AXP717_MODULE_EN_CONTROL_1),
regmap_reg_range(AXP717_MIN_SYS_V_CONTROL, AXP717_BOOST_CONTROL),
@@ -447,6 +473,15 @@ static const struct regmap_config axp313a_regmap_config = {
.cache_type = REGCACHE_MAPLE,
};
+static const struct regmap_config axp318_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .wr_table = &axp318_writeable_table,
+ .volatile_table = &axp318_volatile_table,
+ .max_register = AXP318_WDOG_CTRL,
+ .cache_type = REGCACHE_MAPLE,
+};
+
static const struct regmap_config axp323_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
@@ -663,6 +698,28 @@ static const struct regmap_irq axp313a_regmap_irqs[] = {
INIT_REGMAP_IRQ(AXP313A, DIE_TEMP_HIGH, 0, 0),
};
+static const struct regmap_irq axp318_regmap_irqs[] = {
+ INIT_REGMAP_IRQ(AXP318, DCDC8_V_LOW, 0, 7),
+ INIT_REGMAP_IRQ(AXP318, DCDC7_V_LOW, 0, 6),
+ INIT_REGMAP_IRQ(AXP318, DCDC6_V_LOW, 0, 5),
+ INIT_REGMAP_IRQ(AXP318, DCDC5_V_LOW, 0, 4),
+ INIT_REGMAP_IRQ(AXP318, DCDC4_V_LOW, 0, 3),
+ INIT_REGMAP_IRQ(AXP318, DCDC3_V_LOW, 0, 2),
+ INIT_REGMAP_IRQ(AXP318, DCDC2_V_LOW, 0, 1),
+ INIT_REGMAP_IRQ(AXP318, DCDC1_V_LOW, 0, 0),
+ INIT_REGMAP_IRQ(AXP318, PEK_RIS_EDGE, 1, 6),
+ INIT_REGMAP_IRQ(AXP318, PEK_FAL_EDGE, 1, 5),
+ INIT_REGMAP_IRQ(AXP318, PEK_LONG, 1, 4),
+ INIT_REGMAP_IRQ(AXP318, PEK_SHORT, 1, 3),
+ INIT_REGMAP_IRQ(AXP318, DIE_TEMP_HIGH_LV2, 1, 2),
+ INIT_REGMAP_IRQ(AXP318, DIE_TEMP_HIGH_LV1, 1, 1),
+ INIT_REGMAP_IRQ(AXP318, DCDC9_V_LOW, 1, 0),
+ INIT_REGMAP_IRQ(AXP318, GPIO3_INPUT, 2, 6),
+ INIT_REGMAP_IRQ(AXP318, GPIO2_INPUT, 2, 5),
+ INIT_REGMAP_IRQ(AXP318, GPIO1_INPUT, 2, 4),
+ INIT_REGMAP_IRQ(AXP318, WDOG_EXPIRE, 3, 0),
+};
+
static const struct regmap_irq axp717_regmap_irqs[] = {
INIT_REGMAP_IRQ(AXP717, SOC_DROP_LVL2, 0, 7),
INIT_REGMAP_IRQ(AXP717, SOC_DROP_LVL1, 0, 6),
@@ -884,6 +941,17 @@ static const struct regmap_irq_chip axp313a_regmap_irq_chip = {
.num_regs = 1,
};
+static const struct regmap_irq_chip axp318_regmap_irq_chip = {
+ .name = "axp318w_irq_chip",
+ .status_base = AXP318_IRQ_STATE1,
+ .ack_base = AXP318_IRQ_STATE1,
+ .unmask_base = AXP318_IRQ_EN1,
+ .init_ack_masked = true,
+ .irqs = axp318_regmap_irqs,
+ .num_irqs = ARRAY_SIZE(axp318_regmap_irqs),
+ .num_regs = 4,
+};
+
static const struct regmap_irq_chip axp717_regmap_irq_chip = {
.name = "axp717_irq_chip",
.status_base = AXP717_IRQ0_STATE,
@@ -1061,6 +1129,10 @@ static struct mfd_cell axp313a_cells[] = {
MFD_CELL_RES("axp313a-pek", axp313a_pek_resources),
};
+static const struct mfd_cell axp318_cells[] = {
+ MFD_CELL_BASIC("axp20x-regulator", NULL, NULL, 0, 1),
+};
+
static struct mfd_cell axp717_cells[] = {
MFD_CELL_NAME("axp20x-regulator"),
MFD_CELL_RES("axp20x-pek", axp717_pek_resources),
@@ -1313,6 +1385,12 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
axp20x->regmap_cfg = &axp313a_regmap_config;
axp20x->regmap_irq_chip = &axp313a_regmap_irq_chip;
break;
+ case AXP318_ID:
+ axp20x->nr_cells = ARRAY_SIZE(axp318_cells);
+ axp20x->cells = axp318_cells;
+ axp20x->regmap_cfg = &axp318_regmap_config;
+ axp20x->regmap_irq_chip = &axp318_regmap_irq_chip;
+ break;
case AXP323_ID:
axp20x->nr_cells = ARRAY_SIZE(axp313a_cells);
axp20x->cells = axp313a_cells;
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
index b352661d99a1..c1f9dc06387a 100644
--- a/include/linux/mfd/axp20x.h
+++ b/include/linux/mfd/axp20x.h
@@ -19,6 +19,7 @@ enum axp20x_variants {
AXP223_ID,
AXP288_ID,
AXP313A_ID,
+ AXP318_ID,
AXP323_ID,
AXP717_ID,
AXP803_ID,
@@ -116,6 +117,69 @@ enum axp20x_variants {
#define AXP313A_IRQ_STATE 0x21
#define AXP323_DCDC_MODE_CTRL2 0x22
+#define AXP318_DCDC_OUTPUT_CONTROL1 0x10
+#define AXP318_DCDC_OUTPUT_CONTROL2 0x11
+#define AXP318_DCDC1_CONTROL 0x12
+#define AXP318_DCDC2_CONTROL 0x13
+#define AXP318_DCDC3_CONTROL 0x14
+#define AXP318_DCDC4_CONTROL 0x15
+#define AXP318_DCDC5_CONTROL 0x16
+#define AXP318_DCDC6_CONTROL 0x17
+#define AXP318_DCDC7_CONTROL 0x18
+#define AXP318_DCDC8_CONTROL 0x19
+#define AXP318_DCDC9_CONTROL 0x1a
+#define AXP318_LDO_OUTPUT_CONTROL1 0x20
+#define AXP318_LDO_OUTPUT_CONTROL2 0x21
+#define AXP318_LDO_OUTPUT_CONTROL3 0x22
+#define AXP318_LDO_OUTPUT_CONTROL4 0x23
+#define AXP318_ALDO1_CONTROL 0x24
+#define AXP318_ALDO2_CONTROL 0x25
+#define AXP318_ALDO3_CONTROL 0x26
+#define AXP318_ALDO4_CONTROL 0x27
+#define AXP318_ALDO5_CONTROL 0x28
+#define AXP318_ALDO6_CONTROL 0x29
+#define AXP318_BLDO1_CONTROL 0x2a
+#define AXP318_BLDO2_CONTROL 0x2b
+#define AXP318_BLDO3_CONTROL 0x2c
+#define AXP318_BLDO4_CONTROL 0x2d
+#define AXP318_BLDO5_CONTROL 0x2e
+#define AXP318_CLDO1_CONTROL 0x2f
+#define AXP318_CLDO2_CONTROL 0x30
+#define AXP318_CLDO3_CONTROL 0x31
+#define AXP318_CLDO4_CONTROL 0x32
+#define AXP318_CLDO5_CONTROL 0x33
+#define AXP318_DLDO1_CONTROL 0x34
+#define AXP318_DLDO2_CONTROL 0x35
+#define AXP318_DLDO3_CONTROL 0x36
+#define AXP318_DLDO4_CONTROL 0x37
+#define AXP318_DLDO5_CONTROL 0x38
+#define AXP318_DLDO6_CONTROL 0x39
+#define AXP318_ELDO1_CONTROL 0x3a
+#define AXP318_ELDO2_CONTROL 0x3b
+#define AXP318_ELDO3_CONTROL 0x3c
+#define AXP318_ELDO4_CONTROL 0x3d
+#define AXP318_ELDO5_CONTROL 0x3e
+#define AXP318_ELDO6_CONTROL 0x3f
+#define AXP318_IRQ_EN1 0x40
+#define AXP318_IRQ_EN2 0x41
+#define AXP318_IRQ_EN3 0x42
+#define AXP318_IRQ_EN4 0x43
+#define AXP318_IRQ_STATE1 0x48
+#define AXP318_IRQ_STATE2 0x49
+#define AXP318_IRQ_STATE3 0x4a
+#define AXP318_IRQ_STATE4 0x4b
+#define AXP318_POWER_REASON 0x50
+#define AXP318_SHUTDOWN_REASON 0x51
+#define AXP318_SHUTDOWN_CTRL 0x52
+#define AXP318_TEMP_ADC_H_EN 0x65
+#define AXP318_TEMP_ADC_L 0x66
+#define AXP318_DIE_TEMP_ADC_H_EN 0x67
+#define AXP318_GPADC_H_EN 0x69
+#define AXP318_GPADC_L 0x6a
+#define AXP318_GPIO_CTRL 0x70
+#define AXP318_GPIO_INPUT 0x71
+#define AXP318_WDOG_CTRL 0x77
+
#define AXP717_ON_INDICATE 0x00
#define AXP717_PMU_STATUS_2 0x01
#define AXP717_BC_DETECT 0x05
@@ -819,6 +883,28 @@ enum axp313a_irqs {
AXP313A_IRQ_PEK_RIS_EDGE,
};
+enum axp318_irqs {
+ AXP318_IRQ_DCDC1_V_LOW,
+ AXP318_IRQ_DCDC2_V_LOW,
+ AXP318_IRQ_DCDC3_V_LOW,
+ AXP318_IRQ_DCDC4_V_LOW,
+ AXP318_IRQ_DCDC5_V_LOW,
+ AXP318_IRQ_DCDC6_V_LOW,
+ AXP318_IRQ_DCDC7_V_LOW,
+ AXP318_IRQ_DCDC8_V_LOW,
+ AXP318_IRQ_DCDC9_V_LOW,
+ AXP318_IRQ_DIE_TEMP_HIGH_LV1,
+ AXP318_IRQ_DIE_TEMP_HIGH_LV2,
+ AXP318_IRQ_PEK_SHORT,
+ AXP318_IRQ_PEK_LONG,
+ AXP318_IRQ_PEK_FAL_EDGE,
+ AXP318_IRQ_PEK_RIS_EDGE,
+ AXP318_IRQ_GPIO1_INPUT = 20,
+ AXP318_IRQ_GPIO2_INPUT,
+ AXP318_IRQ_GPIO3_INPUT,
+ AXP318_IRQ_WDOG_EXPIRE = 24,
+};
+
enum axp717_irqs {
AXP717_IRQ_VBUS_FAULT,
AXP717_IRQ_VBUS_OVER_V,
--
2.47.3
^ permalink raw reply related
* [PATCH v3 1/4] dt-bindings: mfd: x-powers,axp152: Document AXP318W
From: Jerome Brunet @ 2026-07-17 8:44 UTC (permalink / raw)
To: Andre Przywara, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Liam Girdwood, Mark Brown
Cc: devicetree, linux-kernel, Conor Dooley, Jerome Brunet
In-Reply-To: <20260717-axp318-regulator-v3-0-779dc1b97dd4@baylibre.com>
From: Andre Przywara <andre.przywara@arm.com>
The X-Powers AXP318W is a PMIC used on some newer Allwinner devices.
Among a large number of both DCDC and LDO regulators it features the usual
ADC/IRQ/power key parts.
Like other recent PMICs, it lacks the DC/DC converter PWM frequency control
register, that rate is fixed here (1.5MHz on DCDC1, 3 MHz on the others).
Add the new compatible string, and add that to the list of PMICs without
the PWM frequency property.
Also add more input supply properties, for the split DCDC and ALDO
supplies.
The PMIC features *two* switched outputs, hanging of DCDC1, and the
manual calls them swout1 and swout2, so follow suit here and add those
names to the pattern for matching the node names.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
.../devicetree/bindings/mfd/x-powers,axp152.yaml | 28 +++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
index 45f015d63df1..95b3984fe0f9 100644
--- a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
+++ b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
@@ -83,6 +83,7 @@ allOf:
contains:
enum:
- x-powers,axp313a
+ - x-powers,axp318w
- x-powers,axp323
- x-powers,axp15060
- x-powers,axp717
@@ -102,6 +103,7 @@ properties:
- x-powers,axp221
- x-powers,axp223
- x-powers,axp313a
+ - x-powers,axp318w
- x-powers,axp323
- x-powers,axp717
- x-powers,axp803
@@ -156,10 +158,18 @@ properties:
description: >
DCDC1 power supply node, if present.
+ vin19-supply:
+ description: >
+ Combined DCDC1/DCDC9 power supply node, if present.
+
vin2-supply:
description: >
DCDC2 power supply node, if present.
+ vin23-supply:
+ description: >
+ Combined DCDC2/DCDC3 power supply node, if present.
+
vin3-supply:
description: >
DCDC3 power supply node, if present.
@@ -168,6 +178,10 @@ properties:
description: >
DCDC4 power supply node, if present.
+ vin45-supply:
+ description: >
+ Combined DCDC4/DCDC5 power supply node, if present.
+
vin5-supply:
description: >
DCDC5 power supply node, if present.
@@ -176,6 +190,10 @@ properties:
description: >
DCDC6 power supply node, if present.
+ vin678-supply:
+ description: >
+ Combined DCDC6/DCDC7/DCDC8 power supply node, if present.
+
vin7-supply:
description: >
DCDC7 power supply node, if present.
@@ -220,6 +238,14 @@ properties:
description: >
ALDO* power supply node, if present.
+ aldo156in-supply:
+ description: >
+ ALDO* power supply node, if present.
+
+ aldo234in-supply:
+ description: >
+ ALDO* power supply node, if present.
+
bldoin-supply:
description: >
BLDO* power supply node, if present.
@@ -277,7 +303,7 @@ properties:
Defines the work frequency of DC-DC in kHz.
patternProperties:
- "^(([a-f])?ldo[0-9]|dcdc[0-7a-e]|ldo(_|-)io(0|1)|(dc1)?sw|rtc(_|-)ldo|cpusldo|drivevbus|dc5ldo|boost)$":
+ "^(([a-f])?ldo[0-9]|dcdc[0-9a-e]|ldo(_|-)io(0|1)|(dc1)?sw|swout[1-9]|rtc(_|-)ldo|cpusldo|drivevbus|dc5ldo|boost)$":
$ref: /schemas/regulator/regulator.yaml#
type: object
unevaluatedProperties: false
--
2.47.3
^ permalink raw reply related
* [PATCH v3 0/4] regulator: Add X-Powers AXP318W PMIC support
From: Jerome Brunet @ 2026-07-17 8:44 UTC (permalink / raw)
To: Andre Przywara, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Liam Girdwood, Mark Brown
Cc: devicetree, linux-kernel, Conor Dooley, Jerome Brunet
This patch series adds support for the X-Powers AXP318W PMIC, which is
used recently on new boards with Allwinner SoCs (the A733).
The PMIC features 9 DCDC buck converters and 28 LDOs, plus the usual ADC,
interrupts, and power key components.
A datasheet can be found linked in this Wiki table:
https://linux-sunxi.org/AXP_PMICs
Patch 1 adds the compatible string to the binding document, and adds
the additional input supply properties.
Patch 2 is the MFD part, describing the regmap and all the interrupts.
So far we support the regulators, the ADC and other pieces will follow later.
Patch 3 follows up one of Sashiko recommendation regarding const data.
Patch 4 adds the voltage regulator rails, this part is crucial to enable
any board using this PMIC, as we depend on those rails even for basic
devices.
There was an unclosed topic regarding the handling of LDOs output
voltage being limited to input voltage being provided by the supply.
Chen-Yu noted the min_dropout_uV would be a good fit for that but
the actual minimal dropout value was unknown. I've arbitrarily picked
1uV because it is the minimum the framework supports. Realistically a low
dropout regulator is bound to have some dropout. This choice does the
trick for now and is certain be less restrictive than what it is in
reality.
If anyone has problems because the dropout is actually higher
* it is arguably an HW design error
* it is a good time to let us know what the actual dropout is
Changes in v3:
- Correct mess up v2 errors regarding ops and ids.
- Correctly propagate errors when checking axp318 threshold.
- Fix DT binding regex regarding dcdc max ids
- Add missing RTCLDO.
- Remove axp318 PEK MFD cell:
As pointed out by sashiko, the driver name did not match anything in the
pek driver. While the device does support some handling of the power
button, it does not seem to match the existing driver. Register 0x36
relates to DLDO3, not the power key, as expected by the misc driver.
Leave this out for now.
- Constify axp313 and axp717 mfd_cells array for consistency.
- Link to v2: https://patch.msgid.link/20260710-axp318-regulator-v2-0-ee5f1c56b49f@baylibre.com
Changes in v2:
- Droped _NUM_VOLTAGES macros
- Use min_dropout_uV to limit LDO voltage to supplies
- Add bypass mode for EDLO4/5
- Prevent crossing 1.54V threshold for DCDC6/7/8/9
- Link to v1: https://lore.kernel.org/r/20251021112013.2710903-1-andre.przywara@arm.com
---
Andre Przywara (3):
dt-bindings: mfd: x-powers,axp152: Document AXP318W
mfd: axp20x: Add support for AXP318W PMIC
regulator: axp20x: add support for the AXP318W
Jerome Brunet (1):
mfd: axp20x: constify axp313 and axp717 cells
.../devicetree/bindings/mfd/x-powers,axp152.yaml | 28 +-
drivers/mfd/axp20x-i2c.c | 2 +
drivers/mfd/axp20x.c | 82 +++++-
drivers/regulator/axp20x-regulator.c | 298 ++++++++++++++++++++-
include/linux/mfd/axp20x.h | 130 +++++++++
5 files changed, 528 insertions(+), 12 deletions(-)
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260710-axp318-regulator-43545ce3261f
Best regards,
--
Jerome
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: sram: Document qcom,shikra-imem compatible
From: Krzysztof Kozlowski @ 2026-07-17 8:44 UTC (permalink / raw)
To: Komal Bajaj
Cc: Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
devicetree, linux-kernel, Konrad Dybcio
In-Reply-To: <20260716-shikra-imem-binding-v2-1-2c3e2465d25a@oss.qualcomm.com>
On Thu, Jul 16, 2026 at 01:10:14PM +0530, Komal Bajaj wrote:
> Add compatible for Shikra SoC IMEM.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
> Changes in v2:
> - Rebased on top of linux-next
> - Collected Reviewed-By tag from Konrad
> - Link to v1: https://lore.kernel.org/r/20260430-shikra-imem-binding-v1-1-c6976239f90f@oss.qualcomm.com
> ---
> Documentation/devicetree/bindings/sram/sram.yaml | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 2/3] arm64: dts: qcom: fix SoCCP memory mappings for Glymur
From: Ananthu C V @ 2026-07-17 8:42 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mathieu Poirier, linux-arm-msm, devicetree,
linux-kernel, linux-remoteproc
In-Reply-To: <9e0ea6cf-ec91-4017-a14d-a1f7c4921f37@oss.qualcomm.com>
Hi Konrad,
On Thu, Jul 16, 2026 at 05:16:56PM +0200, Konrad Dybcio wrote:
> On 7/7/26 12:12 PM, Ananthu C V wrote:
> > The currently listed SoCCP and SoCCP DTB reserved memory regions
> > don't align with the memory requested by the SoCCP Firmware. Fix
> > this by updating the SoCCP/SoCCP DTB memory regions to reflect the
> > memory region requirements of the SoCCP firmware, as described in
> > the Glymur v21 memory map release.
> >
> > Signed-off-by: Ananthu C V <ananthu.cv@oss.qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > index 20b49af7298e..9ec7c256b80a 100644
> > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > @@ -602,13 +602,13 @@ spss_region_mem: spss@88a00000 {
> > no-map;
> > };
> >
> > - soccpdtb_mem: soccpdtb@892e0000 {
> > - reg = <0x0 0x892e0000 0x0 0x20000>;
> > + soccp_mem: soccp@88e00000 {
> > + reg = <0x0 0x88e00000 0x0 0x400000>;
> > no-map;
> > };
> >
> > - soccp_mem: soccp@89300000 {
> > - reg = <0x0 0x89300000 0x0 0x400000>;
> > + soccpdtb_mem: soccpdtb@89200000 {
> > + reg = <0x0 0x89200000 0x0 0x20000>;
> > no-map;
> > };
>
> The updated regions point to "SOCCP Boot [DTB]", whereas the old
> regions point to "SOCCP [DTB]". I'm assuming HLOS potentially loading
> FW to the boot regions is fine?
The reason why there are two seperate memory regions for SoCCP is because of
some Hyper-V limitations not allowing HLOS to reuse the memory regions from
pre-HLOS context for SoCCP. This is a windows specific issue. KVM is not
limited by this, so we are able to reuse the same memory regions loaded by
the bootloader in HLOS context as well, and do not require two seperate
memory regions.
> Konrad
Best,
Ananthu
^ permalink raw reply
* Re: [PATCH v4 2/2] iio: adc: add Axiado SARADC driver
From: Andy Shevchenko @ 2026-07-17 8:38 UTC (permalink / raw)
To: Petar Stepanovic
Cc: Akhila Kavi, Prasad Bolisetty, Jonathan Cameron, David Lechner,
Nuno Sá, Andy Shevchenko, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Harshit Shah, linux-iio, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <alnpMFK6_ZkdWlLi@ashevche-desk.local>
On Fri, Jul 17, 2026 at 11:35:01AM +0300, Andy Shevchenko wrote:
> On Thu, Jul 16, 2026 at 10:53:02PM -0700, Petar Stepanovic wrote:
...
> > +static void axiado_saradc_disable(void *data)
> > +{
> > + struct axiado_saradc *info = data;
> > +
> > + regmap_write(info->regmap, AX_SARADC_GLOBAL_CTRL_REG,
> > + AX_SARADC_GLOBAL_CTRL_PD);
> > +}
>
> Supply regmap instead of info and make this simpler
>
> static void axiado_saradc_disable(void *map)
> {
> regmap_write(map, AX_SARADC_GLOBAL_CTRL_REG, AX_SARADC_GLOBAL_CTRL_PD);
> }
>
> ...
>
> > + regval = FIELD_PREP(AX_SARADC_GLOBAL_CTRL_CH_EN_MASK,
> > + GENMASK(soc_data->num_channels - 1, 0)) |
> > + AX_SARADC_GLOBAL_CTRL_SAMPLE_16 |
> > + AX_SARADC_GLOBAL_CTRL_MODE_MANUAL |
> > + AX_SARADC_GLOBAL_CTRL_ENABLE;
>
> This is not used in the below call, move it closer to its user.
>
> > + ret = regmap_write(info->regmap, AX_SARADC_GLOBAL_CTRL_REG,
> > + AX_SARADC_GLOBAL_CTRL_PD);
>
> With
>
> struct regmap *map;
>
> at the top, this and other will be shorter and easier to follow.
> And I would dare to use a single line:
>
> ret = regmap_write(map, AX_SARADC_GLOBAL_CTRL_REG, AX_SARADC_GLOBAL_CTRL_PD);
Looking closer at this I think it's a leftover? Since it's an action that does
disable. This one should only enable chip, right?
> > + if (ret)
> > + return ret;
> > +
> > + ret = regmap_write(info->regmap, AX_SARADC_GLOBAL_CTRL_REG, regval);
> > + if (ret)
> > + return ret;
>
> > + ret = devm_add_action_or_reset(dev, axiado_saradc_disable, info);
>
> ret = devm_add_action_or_reset(dev, axiado_saradc_disable, map);
>
> > + if (ret)
> > + return ret;
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v3 1/8] dt-bindings: arm: Add Live Firmware Activation
From: Sudeep Holla @ 2026-07-17 8:38 UTC (permalink / raw)
To: Andre Przywara
Cc: Mark Rutland, Sudeep Holla, Lorenzo Pieralisi, Salman Nabi,
Vedashree Vidwans, Trilok Soni, Nirmoy Das, vsethi, Varun Wadekar,
linux-arm-kernel, linux-kernel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
In-Reply-To: <20260706134455.132091-2-andre.przywara@arm.com>
On Mon, Jul 06, 2026 at 03:44:41PM +0200, Andre Przywara wrote:
> The Arm Live Firmware Activation spec [1] describes updating firmware
> images during runtime, without requiring a reboot. Update images might
> be deployed out-of-band, for instance via a BMC, in this case the OS
> needs to be notified about the availability of a new image.
>
> Describe an interrupt that could be triggered by the platform, to notify
> about any changes.
>
> [1] https://developer.arm.com/documentation/den0147/latest/
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../devicetree/bindings/arm/arm,lfa.yaml | 45 +++++++++++++++++++
> 1 file changed, 45 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/arm,lfa.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/arm,lfa.yaml b/Documentation/devicetree/bindings/arm/arm,lfa.yaml
> new file mode 100644
> index 000000000000..ef8e250f2da7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/arm,lfa.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/arm,lfa.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Arm Live Firmware Activation (LFA)
> +
> +maintainers:
> + - Andre Przywara <andre.przywara@arm.com>
> + - Sudeep Holla <sudeep.holla@arm.com>
> +
> +description:
> + The Arm Live Firmware Activation (LFA) specification [1] describes a
> + firmware interface to activate an updated firmware at runtime, without
> + requiring a reboot. Updates might be supplied out-of-band, for instance
> + via a BMC, in which case the platform needs to notify an OS about pending
> + image updates.
What does the below described "interrupts" cover or doesn't cover? Both
in case of in-band and out-of-band. It is not very clear for me.
--
Regards,
Sudeep
^ permalink raw reply
* Re: [PATCH v3 1/2] dt-bindings: clock: qcom: Add Qualcomm Maili video clock controller
From: Krzysztof Kozlowski @ 2026-07-17 8:37 UTC (permalink / raw)
To: Jagadeesh Kona
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Taniya Das,
Jagadeesh Kona, linux-arm-msm, linux-clk, devicetree,
linux-kernel
In-Reply-To: <20260717-maili_videocc-v3-1-6656694b06a7@oss.qualcomm.com>
On Fri, Jul 17, 2026 at 09:44:44AM +0530, Jagadeesh Kona wrote:
> Add device tree bindings for the video clock controller on Qualcomm
> Maili SoC.
>
> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
> ---
> .../bindings/clock/qcom,sm8450-videocc.yaml | 2 +
> include/dt-bindings/clock/qcom,maili-videocc.h | 50 ++++++++++++++++++++++
> 2 files changed, 52 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 7/8] dt-bindings: usb: generic-xhci: add Axiado AX3005 xHCI variant
From: Krzysztof Kozlowski @ 2026-07-17 8:37 UTC (permalink / raw)
To: Swark Yang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah,
Linus Walleij, Bartosz Golaszewski, Jan Kotas, Michal Simek,
Andi Shyti, Przemysław Gaj, Alexandre Belloni, Frank Li,
Boris Brezillon, Greg Kroah-Hartman, Jiri Slaby, Mark Brown,
Mathias Nyman, devicetree, linux-arm-kernel, linux-kernel,
linux-gpio, linux-i2c, linux-i3c, linux-serial, linux-spi,
linux-usb
In-Reply-To: <20260716-upstream-axiado-ax3005-upstream-v3-7-c429095143ec@axiado.com>
On Thu, Jul 16, 2026 at 08:51:14PM -0700, Swark Yang wrote:
> Add binding for Axiado AX3005 xHCI controller. So far, no changes
> are known, so it can fall back to the generic-xhci compatible.
>
> Signed-off-by: Swark Yang <syang@axiado.com>
> ---
> Documentation/devicetree/bindings/usb/generic-xhci.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/generic-xhci.yaml b/Documentation/devicetree/bindings/usb/generic-xhci.yaml
> index 62678abd74b5..d7fb0301fe4c 100644
> --- a/Documentation/devicetree/bindings/usb/generic-xhci.yaml
> +++ b/Documentation/devicetree/bindings/usb/generic-xhci.yaml
> @@ -14,6 +14,10 @@ properties:
> oneOf:
> - description: Generic xHCI device
> const: generic-xhci
> + - description: Axiado AX3005 SoC xHCI controller
> + items:
> + - const: axiado,ax3005-xhci
Just add it to the enum in "Armada 37xx/8k SoCs" group while dropping
that description. Description anyway repeats the compatibles so is
completely redundant.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 6/8] dt-bindings: spi: dw-apb-ssi: add Axiado AX3005 SPI variant
From: Krzysztof Kozlowski @ 2026-07-17 8:35 UTC (permalink / raw)
To: Swark Yang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah,
Linus Walleij, Bartosz Golaszewski, Jan Kotas, Michal Simek,
Andi Shyti, Przemysław Gaj, Alexandre Belloni, Frank Li,
Boris Brezillon, Greg Kroah-Hartman, Jiri Slaby, Mark Brown,
Mathias Nyman, devicetree, linux-arm-kernel, linux-kernel,
linux-gpio, linux-i2c, linux-i3c, linux-serial, linux-spi,
linux-usb
In-Reply-To: <20260717-admirable-robust-adder-7aad70@quoll>
On 17/07/2026 10:34, Krzysztof Kozlowski wrote:
> On Thu, Jul 16, 2026 at 08:51:13PM -0700, Swark Yang wrote:
>> Add binding for Axiado AX3005 SPI controller. So far, no changes
>> are known, so it can fall back to the snps,dwc-ssi-1.01a compatible.
>>
>> Signed-off-by: Swark Yang <syang@axiado.com>
>> ---
>> Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> index 8ebebcebca16..7b16053d2244 100644
>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> @@ -41,6 +41,10 @@ properties:
>> enum:
>> - snps,dw-apb-ssi
>> - snps,dwc-ssi-1.01a
>> + - description: Axiado AX3005 SPI Controller
>
> Rather: Vendor controllers compatible with v1.01a
>
> and then place it after the group with "description: Vendor controllers which
> use snps,dw-apb-ssi as fallback".
>
Ah, and first entry should be enum, not const, so this list can grow.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v3 6/8] dt-bindings: spi: dw-apb-ssi: add Axiado AX3005 SPI variant
From: Krzysztof Kozlowski @ 2026-07-17 8:34 UTC (permalink / raw)
To: Swark Yang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah,
Linus Walleij, Bartosz Golaszewski, Jan Kotas, Michal Simek,
Andi Shyti, Przemysław Gaj, Alexandre Belloni, Frank Li,
Boris Brezillon, Greg Kroah-Hartman, Jiri Slaby, Mark Brown,
Mathias Nyman, devicetree, linux-arm-kernel, linux-kernel,
linux-gpio, linux-i2c, linux-i3c, linux-serial, linux-spi,
linux-usb
In-Reply-To: <20260716-upstream-axiado-ax3005-upstream-v3-6-c429095143ec@axiado.com>
On Thu, Jul 16, 2026 at 08:51:13PM -0700, Swark Yang wrote:
> Add binding for Axiado AX3005 SPI controller. So far, no changes
> are known, so it can fall back to the snps,dwc-ssi-1.01a compatible.
>
> Signed-off-by: Swark Yang <syang@axiado.com>
> ---
> Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index 8ebebcebca16..7b16053d2244 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -41,6 +41,10 @@ properties:
> enum:
> - snps,dw-apb-ssi
> - snps,dwc-ssi-1.01a
> + - description: Axiado AX3005 SPI Controller
Rather: Vendor controllers compatible with v1.01a
and then place it after the group with "description: Vendor controllers which
use snps,dw-apb-ssi as fallback".
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v4 2/2] iio: adc: add Axiado SARADC driver
From: Andy Shevchenko @ 2026-07-17 8:34 UTC (permalink / raw)
To: Petar Stepanovic
Cc: Akhila Kavi, Prasad Bolisetty, Jonathan Cameron, David Lechner,
Nuno Sá, Andy Shevchenko, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Harshit Shah, linux-iio, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260716-axiado-ax3000-ax3005-saradc-v4-2-810527a9d27f@axiado.com>
On Thu, Jul 16, 2026 at 10:53:02PM -0700, Petar Stepanovic wrote:
> Add support for the SARADC controller found on Axiado AX3000 and
> AX3005 SoCs.
>
> The driver supports single-shot voltage reads through the IIO
> subsystem. The number of available input channels is selected from
> the SoC match data, allowing AX3000 and AX3005 variants to use the
> same driver.
...
Please, follow IWYU principle.
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +#include <linux/clk.h>
> +#include <linux/cleanup.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
You can omit this since you have platform_device.h.
> +#include <linux/err.h>
> +#include <linux/io.h>
+ math.h
> +#include <linux/mod_devicetable.h>
No to this header in a new code, Uwe did some rework recently.
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/platform_device.h>
> +#include <linux/property.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
+ types.h // uXX
> +#include <linux/units.h>
...
> +/* Register offsets */
> +#define AX_SARADC_GLOBAL_CTRL_REG 0x0004
> +#define AX_SARADC_MANUAL_CTRL_REG 0x0008
> +#define AX_SARADC_DOUT_REG 0x001C
Be consistent, use tabs to indent values of the offsets.
...
> +/* GLOBAL_CTRL register values */
> +#define AX_SARADC_GLOBAL_CTRL_SAMPLE_16 \
> + FIELD_PREP(AX_SARADC_GLOBAL_CTRL_SAMPLE_MASK, 0)
> +
> +#define AX_SARADC_GLOBAL_CTRL_MODE_MANUAL \
> + FIELD_PREP(AX_SARADC_GLOBAL_CTRL_MODE_MASK, 1)
FIELD_PREP_CONST() in both cases.
...
> +#define AX_SARADC_MANUAL_CTRL_EN(ch) \
> + (AX_SARADC_MANUAL_CTRL_ENABLE | \
> + FIELD_PREP(AX_SARADC_MANUAL_CTRL_CH_SEL_MASK, ch))
Missing parentheses for ch. Also wrong indentation of the second line, missing
one space.
...
> +#define AX_RESOLUTION_BITS 10
> +#define AX_SARADC_CONV_CYCLES 13
> +#define AX_SARADC_CONV_DELAY_MARGIN_US 10
Again, be consistent, use tabs to indent values.
...
> +struct axiado_saradc {
> + struct regmap *regmap;
> + struct clk *clk;
Makes no sense to keep it here, your code takes the rate and uses that,
I do not see how clk is being used right now. Perhaps you have plans
for power management? But then add it when it's needed and being used.
> + struct mutex lock; /* Serializes ADC conversions. */
> + unsigned long clk_rate;
> + int vref_uV;
> +};
> +
> +static const struct regmap_config axiado_saradc_regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = AX_SARADC_DOUT_REG,
No cache?
> +};
> +
> +
Single blank line is enough.
...
> +static int axiado_saradc_conversion(struct axiado_saradc *info,
> + struct iio_chan_spec const *chan, int *val)
> +{
> + unsigned long usecs;
> + unsigned int regval;
> + int stop_ret;
> + int ret;
> +
> + guard(mutex)(&info->lock);
> +
> + /* Select the channel to be used and trigger conversion */
> + ret = regmap_write(info->regmap, AX_SARADC_MANUAL_CTRL_REG,
> + AX_SARADC_MANUAL_CTRL_EN(chan->channel));
> + if (ret)
> + return ret;
> +
> +
Ditto.
> + /* Hardware requires 13 conversion cycles at clk_rate */
> + usecs = DIV_ROUND_UP(AX_SARADC_CONV_CYCLES * USEC_PER_SEC,
> + info->clk_rate);
> + fsleep(usecs + AX_SARADC_CONV_DELAY_MARGIN_US);
> + ret = regmap_read(info->regmap, AX_SARADC_DOUT_REG, ®val);
> +
> + /* Stop manual conversion */
> + stop_ret = regmap_write(info->regmap, AX_SARADC_MANUAL_CTRL_REG, 0);
> +
> + if (ret)
> + return ret;
> + if (stop_ret)
> + return stop_ret;
Why do we care about stop error? Isn't it the best effort we can do?
> + *val = regval & GENMASK(AX_RESOLUTION_BITS - 1, 0);
Is device responding always in native endianess?
> + return 0;
> +}
...
> +static int axiado_saradc_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan, int *val,
> + int *val2, long mask)
Split logically:
static int axiado_saradc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
...
> +static void axiado_saradc_disable(void *data)
> +{
> + struct axiado_saradc *info = data;
> +
> + regmap_write(info->regmap, AX_SARADC_GLOBAL_CTRL_REG,
> + AX_SARADC_GLOBAL_CTRL_PD);
> +}
Supply regmap instead of info and make this simpler
static void axiado_saradc_disable(void *map)
{
regmap_write(map, AX_SARADC_GLOBAL_CTRL_REG, AX_SARADC_GLOBAL_CTRL_PD);
}
...
> + regval = FIELD_PREP(AX_SARADC_GLOBAL_CTRL_CH_EN_MASK,
> + GENMASK(soc_data->num_channels - 1, 0)) |
> + AX_SARADC_GLOBAL_CTRL_SAMPLE_16 |
> + AX_SARADC_GLOBAL_CTRL_MODE_MANUAL |
> + AX_SARADC_GLOBAL_CTRL_ENABLE;
This is not used in the below call, move it closer to its user.
> + ret = regmap_write(info->regmap, AX_SARADC_GLOBAL_CTRL_REG,
> + AX_SARADC_GLOBAL_CTRL_PD);
With
struct regmap *map;
at the top, this and other will be shorter and easier to follow.
And I would dare to use a single line:
ret = regmap_write(map, AX_SARADC_GLOBAL_CTRL_REG, AX_SARADC_GLOBAL_CTRL_PD);
> + if (ret)
> + return ret;
> +
> + ret = regmap_write(info->regmap, AX_SARADC_GLOBAL_CTRL_REG, regval);
> + if (ret)
> + return ret;
> + ret = devm_add_action_or_reset(dev, axiado_saradc_disable, info);
ret = devm_add_action_or_reset(dev, axiado_saradc_disable, map);
> + if (ret)
> + return ret;
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v3 2/8] dt-bindings: gpio: cdns: add Axiado AX3005 GPIO variant
From: Krzysztof Kozlowski @ 2026-07-17 8:33 UTC (permalink / raw)
To: Swark Yang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah,
Linus Walleij, Bartosz Golaszewski, Jan Kotas, Michal Simek,
Andi Shyti, Przemysław Gaj, Alexandre Belloni, Frank Li,
Boris Brezillon, Greg Kroah-Hartman, Jiri Slaby, Mark Brown,
Mathias Nyman, devicetree, linux-arm-kernel, linux-kernel,
linux-gpio, linux-i2c, linux-i3c, linux-serial, linux-spi,
linux-usb
In-Reply-To: <20260716-upstream-axiado-ax3005-upstream-v3-2-c429095143ec@axiado.com>
On Thu, Jul 16, 2026 at 08:51:09PM -0700, Swark Yang wrote:
> Add binding for Axiado AX3005 GPIO controller. So far, no changes
> are known, so it can fall back to the cdns,gpio-r1p02 compatible.
>
> Signed-off-by: Swark Yang <syang@axiado.com>
> ---
> Documentation/devicetree/bindings/gpio/cdns,gpio.yaml | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
> index a84d60b39459..7eacf5af6554 100644
> --- a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
> +++ b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
> @@ -14,8 +14,11 @@ properties:
> oneOf:
> - const: cdns,gpio-r1p02
> - items:
> - - enum:
This should stay enum which would also make your diff easier to read.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 10/16] usb: hub: Power on connected M.2 E-key connectors with power sequencing API
From: Chen-Yu Tsai @ 2026-07-17 8:32 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Bartosz Golaszewski, Greg Kroah-Hartman, Daniel Scally,
Heikki Krogerus, Sakari Ailus, Rafael J. Wysocki,
Danilo Krummrich, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Matthias Brugger, AngeloGioacchino Del Regno, Wei Deng,
linux-acpi, driver-core, linux-pm, linux-usb, devicetree,
linux-mediatek, linux-arm-kernel, linux-kernel,
Manivannan Sadhasivam, Alan Stern, Bartosz Golaszewski
In-Reply-To: <alkWE-bQ9gGIXIJj@ashevche-desk.local>
On Fri, Jul 17, 2026 at 1:34 AM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
>
> On Thu, Jul 16, 2026 at 06:02:38PM +0800, Chen-Yu Tsai wrote:
> > On Wed, Jul 15, 2026 at 9:25 PM Andy Shevchenko
> > <andriy.shevchenko@linux.intel.com> wrote:
> > > On Wed, Jul 15, 2026 at 04:53:40PM +0800, Chen-Yu Tsai wrote:
>
> ...
>
>
> > > > fwnode_handle_put(dev_fwnode(dev));
> > > > + /* usb_hub_create_port_device() could leave an error value */
> > > > + if (!IS_ERR(port_dev->pwrseq))
> > > > + pwrseq_put(port_dev->pwrseq);
> > >
> > > Hmm... I would rather make pwrseq_put() NULL and error pointer-aware, so
> > > it will be no-op in such cases. But I think Bart has his own opinion about
> > > this.
> > >
> > > > kfree(port_dev->req);
> > > > kfree(port_dev);
> > > > }
> > >
> > > > put_device(&port_dev->dev);
> > > > + hub->ports[port1 - 1] = NULL;
> > > > return retval;
> > > > }
>
> ...
>
> > > > int usb_hub_create_port_device(struct usb_hub *hub, int port1)
> > >
> > > > + port_dev->pwrseq = usb_hub_port_pwrseq_get(port_dev);
> > > > + if (IS_ERR(port_dev->pwrseq)) {
> > > > + retval = dev_err_probe(&port_dev->dev, PTR_ERR(port_dev->pwrseq),
> > > > + "failed to get power sequencing descriptor\n");
> > > > + goto err_put_kn;
> > >
> > > OTOH, how pwrseq can be non-NULL and at the same time port be created?
> >
> > I assume by non-NULL you mean returning an error?
> >
> > device_register(&port_dev->dev) is called some lines above this.
> >
> > usb_port is weird in that usb_hub_create_port_device() does a bunch
> > of stuff that is normally done in a driver's probe function. However
> > usb_port's driver is just a stub driver add for userspace compatibility
> > reasons. See commit d99f6b4130877 ("usb: rename usb_port device objects").
> >
> > So at this point the usb_port device has been added to the driver model.
> > Or we can just zero out port_dev->pwrseq instead? I guess that is cleaner
> > than having some weird check in the release function.
>
> So, why do we need to assign the error pointer to the field directly then?
> Make a local variable and assign it if and only if there is no error pointer
> in it. Would it work?
That's the next thing to do on my list. :)
ChenYu
^ permalink raw reply
* [PATCH v7 2/2] arm64: dts: ti: Add audio overlay for k3-j721s2-evm
From: Moteen Shah @ 2026-07-17 8:32 UTC (permalink / raw)
To: krzk+dt, robh, conor+dt, nm, vigneshr, kristo, mturquette, sboyd,
bmasney
Cc: devicetree, linux-arm-kernel, linux-kernel, u-kumar1,
gehariprasath, y-abhilashchandra, m-shah, sen
In-Reply-To: <20260717083201.1887640-1-m-shah@ti.com>
From: Jayesh Choudhary <j-choudhary@ti.com>
Add device tree overlay to enable analog audio support on J721S2-EVM
using PCM3168A codec connected to McASP4 serializers.
- Add audio_refclk1 clock node to k3-j721s2-main.dtsi
- Add nodes for sound-card, audio codec, I2C3 and McASP4
- Add pinmux for I2C3, McASP4, AUDIO_EXT_REFCLK1 and WKUP_GPIO_0
- Add GPIO expander (TCA6408) for codec control
- Add gpio-mux controller to route I2C3 lines
- Add GPIO hogs to route McASP serializers
- Set idle-state to 0 in mux0 and mux1 for McASP signal routing
- Disable main_mcan3 and main_mcan5 as they conflict with McASP4
signal routing via mux0 and mux1
Reviewed-by: Hari Prasath Gujulan Elango <gehariprasath@ti.com>
Reviewed-by: Sen Wang <sen@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Co-developed-by: Moteen Shah <m-shah@ti.com>
Signed-off-by: Moteen Shah <m-shah@ti.com>
---
arch/arm64/boot/dts/ti/Makefile | 4 +
.../boot/dts/ti/k3-j721s2-evm-audio.dtso | 157 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 9 +
3 files changed, 170 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-audio.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 371f9a043fe52..d9824e17085f4 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -180,6 +180,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo
k3-j721s2-evm-dtbs := k3-j721s2-common-proc-board.dtb k3-j721s2-evm-gesi-exp-board.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-audio.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-usb0-type-a.dtbo
@@ -320,6 +321,8 @@ k3-j721e-evm-pcie1-ep-dtbs := k3-j721e-common-proc-board.dtb \
k3-j721e-evm-pcie1-ep.dtbo
k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
+k3-j721s2-evm-audio-dtbs := k3-j721s2-common-proc-board.dtb \
+ k3-j721s2-evm-audio.dtbo
k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
k3-j721s2-evm-pcie1-ep.dtbo
k3-j721s2-evm-usb0-type-a-dtbs := k3-j721s2-common-proc-board.dtb \
@@ -396,6 +399,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-j721e-evm-pcie0-ep.dtb \
k3-j721e-evm-pcie1-ep.dtb \
k3-j721e-sk-csi2-dual-imx219.dtb \
+ k3-j721s2-evm-audio.dtb \
k3-j721s2-evm-pcie1-ep.dtb \
k3-j721s2-evm-usb0-type-a.dtb \
k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-audio.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-audio.dtso
new file mode 100644
index 0000000000000..ac5a827e1b750
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-audio.dtso
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree Overlay for J721S2 Audio Support
+ *
+ * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "k3-pinctrl.h"
+
+&{/} {
+ codec_audio: sound {
+ compatible = "ti,j7200-cpb-audio";
+ model = "j721s2-cpb";
+
+ ti,cpb-mcasp = <&mcasp4>;
+ ti,cpb-codec = <&pcm3168a_1>;
+
+ clocks = <&k3_clks 213 0>, <&k3_clks 213 1>,
+ <&k3_clks 157 299>, <&k3_clks 157 328>;
+ clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000",
+ "cpb-codec-scki", "cpb-codec-scki-48000";
+ };
+
+ i2c_mux: mux-controller-2 {
+ compatible = "gpio-mux";
+ #mux-state-cells = <1>;
+ mux-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_HIGH>;
+ idle-state = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c3_mux_pins_default>;
+ };
+};
+
+&main_pmx0 {
+ mcasp4_pins_default: mcasp4-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0c8, PIN_OUTPUT_PULLDOWN, 1) /* (AD28) MCASP4_ACLKX */
+ J721S2_IOPAD(0x06c, PIN_OUTPUT_PULLDOWN, 1) /* (V26) MCASP4_AFSX */
+ J721S2_IOPAD(0x068, PIN_INPUT_PULLDOWN, 1) /* (U28) MCASP4_AXR1 */
+ J721S2_IOPAD(0x0c4, PIN_OUTPUT_PULLDOWN, 1) /* (AB26) MCASP4_AXR2 */
+ J721S2_IOPAD(0x070, PIN_OUTPUT_PULLDOWN, 1) /* (R27) MCASP4_AXR3 */
+ >;
+ };
+
+ audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x078, PIN_OUTPUT, 1) /* (Y25) MCAN2_RX.AUDIO_EXT_REFCLK1 */
+ >;
+ };
+};
+
+&wkup_pmx2 {
+ main_i2c3_mux_pins_default: main-i2c3-mux-default-pins {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 7) /* (B27) WKUP_GPIO0_54 */
+ >;
+ };
+};
+
+&exp2 {
+ p09-hog {
+ /* P09 - MCASP/TRACE_MUX_S0 */
+ gpio-hog;
+ gpios = <9 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "MCASP/TRACE_MUX_S0";
+ };
+
+ p10-hog {
+ /* P10 - MCASP/TRACE_MUX_S1 */
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "MCASP/TRACE_MUX_S1";
+ };
+};
+
+&mux0 {
+ idle-state = <0>;
+};
+
+&mux1 {
+ idle-state = <0>;
+};
+
+&main_mcan3 {
+ /* Conflicts with McASP4 signal routing via mux0 */
+ status = "disabled";
+};
+
+&main_mcan5 {
+ /* Conflicts with McASP4 signal routing via mux1 */
+ status = "disabled";
+};
+
+&k3_clks {
+ /* Configure AUDIO_EXT_REFCLK1 pin as output */
+ pinctrl-names = "default";
+ pinctrl-0 = <&audio_ext_refclk1_pins_default>;
+};
+
+&main_i2c3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c3_pins_default>;
+ clock-frequency = <400000>;
+ mux-states = <&i2c_mux 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ exp3: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "CODEC_RSTZ", "CODEC_SPARE1",
+ "UB926_RESETN", "UB926_LOCK",
+ "UB926_PWR_SW_CNTRL", "UB926_TUNER_RESET",
+ "UB926_GPIO_SPARE";
+ };
+
+ pcm3168a_1: audio-codec@44 {
+ compatible = "ti,pcm3168a";
+ reg = <0x44>;
+ #sound-dai-cells = <1>;
+ reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
+ clocks = <&audio_refclk1>;
+ clock-names = "scki";
+ VDD1-supply = <&vsys_3v3>;
+ VDD2-supply = <&vsys_3v3>;
+ VCCAD1-supply = <&vsys_5v0>;
+ VCCAD2-supply = <&vsys_5v0>;
+ VCCDA1-supply = <&vsys_5v0>;
+ VCCDA2-supply = <&vsys_5v0>;
+ };
+};
+
+&mcasp4 {
+ status = "okay";
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcasp4_pins_default>;
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ auxclk-fs-ratio = <256>;
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 0 2 1 1
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ >;
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 1228ac5711bf0..36a01a06dd254 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -74,6 +74,15 @@ ehrpwm_tbclk: clock-controller@140 {
reg = <0x140 0x18>;
#clock-cells = <1>;
};
+
+ audio_refclk1: clock-controller@42e4 {
+ compatible = "ti,j721s2-audio-refclk", "ti,am62-audio-refclk";
+ reg = <0x42e4 0x4>;
+ clocks = <&k3_clks 157 299>;
+ assigned-clocks = <&k3_clks 157 299>;
+ assigned-clock-parents = <&k3_clks 157 328>;
+ #clock-cells = <0>;
+ };
};
main_ehrpwm0: pwm@3000000 {
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v3 5/8] dt-bindings: serial: cdns: add Axiado AX3005 UART variant
From: Krzysztof Kozlowski @ 2026-07-17 8:32 UTC (permalink / raw)
To: Swark Yang
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah,
Linus Walleij, Bartosz Golaszewski, Jan Kotas, Michal Simek,
Andi Shyti, Przemysław Gaj, Alexandre Belloni, Frank Li,
Boris Brezillon, Greg Kroah-Hartman, Jiri Slaby, Mark Brown,
Mathias Nyman, devicetree, linux-arm-kernel, linux-kernel,
linux-gpio, linux-i2c, linux-i3c, linux-serial, linux-spi,
linux-usb
In-Reply-To: <20260716-upstream-axiado-ax3005-upstream-v3-5-c429095143ec@axiado.com>
On Thu, Jul 16, 2026 at 08:51:12PM -0700, Swark Yang wrote:
> Add binding for Axiado AX3005 UART controller. So far, no changes
> are known, so it can fall back to the cdns,uart-r1p12 compatible.
>
> Signed-off-by: Swark Yang <syang@axiado.com>
> ---
> Documentation/devicetree/bindings/serial/cdns,uart.yaml | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
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