* [PATCH v3 2/2] arm64: dts: qcom: Add Xiaomi 11 Lite 5G NE
From: Oleksii Onchul @ 2026-07-17 13:22 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel, Oleksii Onchul, Konrad Dybcio
In-Reply-To: <20260717132218.27007-1-oleksiionchul@gmail.com>
Add initial support for the Xiaomi 11 Lite 5G NE, codenamed lisa.
The supported hardware includes regulators, UFS, USB, GPU, remote
processors, Wi-Fi, Bluetooth, touchscreen, flash LED, thermal sensors
and the hardware buttons.
Signed-off-by: Oleksii Onchul <oleksiionchul@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/sm7325-xiaomi-lisa.dts | 1108 +++++++++++++++++
2 files changed, 1109 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm7325-xiaomi-lisa.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index e05414290..c25ac4954 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -355,6 +355,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai-csot.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai-tianma.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-nothing-spacewar.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm7325-xiaomi-lisa.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-xiaomi-taoyao.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm7325-xiaomi-lisa.dts b/arch/arm64/boot/dts/qcom/sm7325-xiaomi-lisa.dts
new file mode 100644
index 000000000..28a19c96c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm7325-xiaomi-lisa.dts
@@ -0,0 +1,1108 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Jens Reidel <adrian@travitia.xyz>
+ * Copyright (c) 2026, Oleksii Onchul <oleksiionchul@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm8350b.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "sm7325.dtsi"
+#include "pm7325.dtsi"
+#include "pm8350b.dtsi" /* PM7325B */
+#include "pm8350c.dtsi" /* PM7350C */
+#include "pmk8350.dtsi" /* PMK7325 */
+
+/* The following reserved memory regions have different addresses or sizes */
+/delete-node/ &adsp_mem;
+/delete-node/ &adsp_rpc_remote_heap_mem;
+/delete-node/ &cdsp_mem;
+/delete-node/ &rmtfs_mem;
+
+/ {
+ model = "Xiaomi 11 Lite 5G NE";
+ compatible = "xiaomi,lisa", "qcom,sm7325";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart5;
+ serial1 = &uart7;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "serial0:115200n8";
+
+ framebuffer0: framebuffer {
+ compatible = "simple-framebuffer";
+ memory-region = <&framebuffer_mem>;
+ width = <1080>;
+ height = <2400>;
+ stride = <(1080 * 4)>;
+ format = "a8r8g8b8";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_default>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm7325-pmic-glink",
+ "qcom,qcm6490-pmic-glink",
+ "qcom,pmic-glink";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&fsa4480_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cdsp_secure_heap_mem: cdsp-secure-heap@81800000 {
+ reg = <0x0 0x81800000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ adsp_mem: adsp@86700000 {
+ reg = <0x0 0x86700000 0x0 0x4000000>;
+ no-map;
+ };
+
+ /* Mainline video_mem is downstream cvp_mem */
+ real_video_mem: video@8ad00000 {
+ reg = <0x0 0x8ad00000 0x0 0x500000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi@8b710000 {
+ reg = <0x0 0x8b710000 0x0 0xa000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@9c700000 {
+ reg = <0x0 0x9c700000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@9e500000 {
+ reg = <0x0 0x9e500000 0x0 0x800000>;
+ no-map;
+ };
+
+ ramoops@a9000000 {
+ compatible = "ramoops";
+ reg = <0x0 0xa9000000 0x0 0x200000>;
+ pmsg-size = <0x200000>;
+ ecc-size = <16>;
+ mem-type = <2>;
+ };
+
+ removed_mem: removed@c0000000 {
+ reg = <0x0 0xc0000000 0x0 0x5100000>;
+ no-map;
+ };
+
+ pil_trustedvm_mem: pil-trustedvm-region@d0800000 {
+ reg = <0x0 0xd0800000 0x0 0x76f7000>;
+ no-map;
+ };
+
+ qrtr_shmem: qrtr-shmem@d7ef7000 {
+ reg = <0x0 0xd7ef7000 0x0 0x9000>;
+ no-map;
+ };
+
+ neuron_block_0_mem: neuron-block@d7f00000 {
+ reg = <0x0 0xd7f00000 0x0 0x80000>;
+ no-map;
+ };
+
+ neuron_block_1_mem: neuron-block@d7f80000 {
+ reg = <0x0 0xd7f80000 0x0 0x80000>;
+ no-map;
+ };
+
+ framebuffer_mem: framebuffer@e1000000 {
+ reg = <0x0 0xe1000000 0x0 (1080 * 2400 * 4)>;
+ no-map;
+ };
+
+ rmtfs_mem: rmtfs@ef500000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0xef500000 0x0 0x280000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>,
+ <QCOM_SCM_VMID_NAV>;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ /* S2B is really ebi.lvl but it's there for supply map completeness sake. */
+ vreg_s2b_0p7: smpa3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s2b_0p7";
+
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <700000>;
+ regulator-always-on;
+ vin-supply = <&vph_pwr>;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm7325-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+
+ vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p952>;
+ vdd-l2-l7-supply = <&vreg_bob>;
+ vdd-l3-supply = <&vreg_s2b_0p7>;
+ vdd-l5-supply = <&vreg_s2b_0p7>;
+ vdd-l6-l9-l10-supply = <&vreg_s8b_1p256>;
+ vdd-l8-supply = <&vreg_s7b_0p952>;
+ vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p856>;
+ vdd-l13-supply = <&vreg_s7b_0p952>;
+ vdd-l14-l16-supply = <&vreg_s8b_1p256>;
+
+ /*
+ * S2, L4-L5 are ARCs:
+ * S2 - ebi.lvl,
+ * L4 - lmx.lvl,
+ * l5 - lcx.lvl.
+ *
+ * L10 are unused.
+ */
+
+ vdd19_pmu_rfa_i:
+ vreg_s1b_1p856: smps1 {
+ regulator-name = "vreg_s1b_1p856";
+ regulator-min-microvolt = <1840000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_s7b_0p952: smps7 {
+ regulator-name = "vreg_s7b_0p952";
+ regulator-min-microvolt = <535000>;
+ regulator-max-microvolt = <1120000>;
+ };
+
+ vdd13_pmu_rfa_i:
+ vreg_s8b_1p256: smps8 {
+ regulator-name = "vreg_s8b_1p256";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
+ };
+
+ vreg_l1b_0p912: ldo1 {
+ regulator-name = "vreg_l1b_0p912";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <925000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_a_usbhs_3p1:
+ vreg_l2b_3p072: ldo2 {
+ regulator-name = "vreg_l2b_3p072";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3b_0p6: ldo3 {
+ regulator-name = "vreg_l3b_0p6";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <910000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_a_dsi_0_1p2:
+ vdd_a_ufs_0_1p2:
+ vreg_l6b_1p2: ldo6 {
+ regulator-name = "vreg_l6b_1p2";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_2p96: ldo7 {
+ regulator-name = "vreg_l7b_2p96";
+ /* Constrained for UFS VCC, at least until UFS driver scales voltage */
+ regulator-min-microvolt = <2952000>;
+ regulator-max-microvolt = <2952000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_0p904: ldo8 {
+ regulator-name = "vreg_l8b_0p904";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_1p2: ldo9 {
+ regulator-name = "vreg_l9b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p776: ldo11 {
+ regulator-name = "vreg_l11b_1p776";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_0p8: ldo12 {
+ regulator-name = "vreg_l12b_0p8";
+ regulator-min-microvolt = <751000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_0p8: ldo13 {
+ regulator-name = "vreg_l13b_0p8";
+ regulator-min-microvolt = <530000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_1p2: ldo14 {
+ regulator-name = "vreg_l14b_1p2";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_0p88: ldo15 {
+ regulator-name = "vreg_l15b_0p88";
+ regulator-min-microvolt = <765000>;
+ regulator-max-microvolt = <1020000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_1p2: ldo16 {
+ regulator-name = "vreg_l16b_1p2";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_1p8: ldo17 {
+ regulator-name = "vreg_l17b_1p8";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b_1p8: ldo18 {
+ regulator-name = "vreg_l18b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l19b_1p8: ldo19 {
+ regulator-name = "vreg_l19b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8350c-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l12-supply = <&vreg_s1b_1p856>;
+ vdd-l2-l8-supply = <&vreg_s1b_1p856>;
+ vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
+ vdd-l6-l9-l11-supply = <&vreg_bob>;
+ vdd-l10-supply = <&vreg_s7b_0p952>;
+
+ vdd-bob-supply = <&vph_pwr>;
+
+ /*
+ * S2, S5, S7, S10 are ARCs:
+ * S2 - cx.lvl,
+ * S5 - mss.lvl,
+ * S7 - gfx.lvl,
+ * S10 - mx.lvl.
+ */
+
+ vreg_s1c_2p2: smps1 {
+ regulator-name = "vreg_s1c_2p2";
+ regulator-min-microvolt = <2190000>;
+ regulator-max-microvolt = <2210000>;
+ };
+
+ vreg_s9c_0p676: smps9 {
+ regulator-name = "vreg_s9c_0p676";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1170000>;
+ };
+
+ vdd_a_usbhs_1p8:
+ vdd_qfprom:
+ vreg_l1c_1p8: ldo1 {
+ regulator-name = "vreg_l1c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_1p8: ldo2 {
+ regulator-name = "vreg_l2c_1p8";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c_1p8_3p0: ldo4 {
+ regulator-name = "vreg_l4c_1p8_3p0";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5c_1p8_3p0: ldo5 {
+ regulator-name = "vreg_l5c_1p8_3p0";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p96: ldo6 {
+ regulator-name = "vreg_l6c_2p96";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-name = "vreg_l7c_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-name = "vreg_l8c_1p8";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ };
+
+ vreg_l9c_2p96: ldo9 {
+ regulator-name = "vreg_l9c_2p96";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_a_dsi_0_0p9:
+ vdd_a_dsi_0_pll_0p9:
+ vdd_a_ufs_0_core:
+ vdd_a_usbhs_core:
+ vreg_l10c_0p88: ldo10 {
+ regulator-name = "vreg_l10c_0p88";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_2p8: ldo11 {
+ regulator-name = "vreg_l11c_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12c_1p8: ldo12 {
+ regulator-name = "vreg_l12c_1p8";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13c_3p0: ldo13 {
+ regulator-name = "vreg_l13c_3p0";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_flash:
+ vdd_iris_rgb:
+ vdd_mic_bias:
+ vreg_bob: bob {
+ regulator-name = "vreg_bob";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+};
+
+&gcc {
+ protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
+ <GCC_MSS_CFG_AHB_CLK>,
+ <GCC_MSS_OFFLINE_AXI_CLK>,
+ <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
+ <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+ <GCC_MSS_SNOC_AXI_CLK>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_SEC_CTRL_CLK_SRC>,
+ <GCC_WPSS_AHB_BDG_MST_CLK>,
+ <GCC_WPSS_AHB_CLK>,
+ <GCC_WPSS_RSCP_CLK>;
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/sm7325/xiaomi/lisa/a660_zap.mbn";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+
+ pm8008: pmic@8 {
+ compatible = "qcom,pm8008";
+ reg = <0x8>;
+
+ interrupts-extended = <&tlmm 25 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&pm8350c_gpios 3 GPIO_ACTIVE_LOW>;
+
+ vdd-l1-l2-supply = <&vreg_s8b_1p256>;
+ vdd-l3-l4-supply = <&vreg_bob>;
+ vdd-l5-supply = <&vreg_s1b_1p856>;
+ vdd-l6-supply = <&vreg_bob>;
+ vdd-l7-supply = <&vreg_bob>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm8008_int_default>, <&pm8008_reset_n_default>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8008 0 0 2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ #thermal-sensor-cells = <0>;
+
+ regulators {
+ vreg_l1p: ldo1 {
+ regulator-name = "vreg_l1p";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l2p: ldo2 {
+ regulator-name = "vreg_l2p";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l3p: ldo3 {
+ regulator-name = "vreg_l3p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vreg_l4p: ldo4 {
+ regulator-name = "vreg_l4p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vreg_l5p: ldo5 {
+ regulator-name = "vreg_l5p";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ };
+
+ vreg_l6p: ldo6 {
+ regulator-name = "vreg_l6p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vreg_l7p: ldo7 {
+ regulator-name = "vreg_l7p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ };
+ };
+
+ fsa4480: typec-mux@42 {
+ compatible = "fcs,fsa4480";
+ reg = <0x42>;
+
+ vcc-supply = <&vreg_bob>;
+ mode-switch;
+ orientation-switch;
+
+ port {
+ fsa4480_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+
+ /* awinic,aw8624_haptic @ 5a */
+};
+
+&ipa {
+ firmware-name = "qcom/sm7325/xiaomi/lisa/ipa_fws.mbn";
+
+ status = "okay";
+};
+
+&pm7325_gpios {
+ volume_up_default: volume-up-default-state {
+ pins = "gpio6";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pm8350c_gpios {
+ pm8008_reset_n_default: pm8008-reset-n-default-state {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-pull-down;
+ };
+};
+
+&pm8350c_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <1>, <4>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <1280000>;
+ };
+};
+
+&pmk8350_adc_tm {
+ status = "okay";
+
+ /* PMK8350 */
+ xo-therm@0 {
+ reg = <0>;
+ io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ /* PM7325 */
+ quiet-therm@1 {
+ reg = <1>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ cam-flash-therm@2 {
+ reg = <2>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ sdm-skin-therm@3 {
+ reg = <3>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ wide-rfc-therm@4 {
+ reg = <4>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ 5g-pa-therm@5 {
+ reg = <5>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM5_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ 4g-pa-therm@6 {
+ reg = <6>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ /* PM8350B */
+ chg-skin-therm@7 {
+ reg = <7>;
+ io-channels = <&pmk8350_vadc PM8350B_ADC7_GPIO2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
+&pmk8350_rtc {
+ status = "okay";
+};
+
+&pmk8350_vadc {
+ /* PMK8350 */
+ channel@44 {
+ reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pmk8350_xo_therm";
+ };
+
+ /* PM7325 */
+ channel@144 {
+ reg = <PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_quiet_therm";
+ };
+
+ channel@145 {
+ reg = <PM7325_ADC7_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_cam_flash_therm";
+ };
+
+ channel@146 {
+ reg = <PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_sdm_skin_therm";
+ };
+
+ channel@147 {
+ reg = <PM7325_ADC7_AMUX_THM4_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_wide_rfc_therm";
+ };
+
+ channel@148 {
+ reg = <PM7325_ADC7_AMUX_THM5_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_5g_pa_therm";
+ };
+
+ channel@14c {
+ reg = <PM7325_ADC7_GPIO3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_4g_pa_therm";
+ };
+
+ /* PM8350B */
+ channel@34b {
+ reg = <PM8350B_ADC7_GPIO2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm8350b_chg_skin_therm";
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qfprom {
+ vcc-supply = <&vdd_qfprom>;
+};
+
+&qup_spi13_cs {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&qup_spi13_data_clk {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&qup_uart5_rx {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart5_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm7325/xiaomi/lisa/adsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm7325/xiaomi/lisa/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/sm7325/xiaomi/lisa/modem.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_wpss {
+ firmware-name = "qcom/sm7325/xiaomi/lisa/wpss.mbn";
+
+ status = "okay";
+};
+
+&spi13 {
+ status = "okay";
+
+ touchscreen@0 {
+ compatible = "goodix,gt9897";
+ reg = <0>;
+ spi-max-frequency = <6000000>;
+
+ interrupts-extended = <&tlmm 81 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&tlmm 105 GPIO_ACTIVE_LOW>;
+
+ avdd-supply = <&vreg_l7c_3p0>;
+ vddio-supply = <&vreg_l2c_1p8>;
+
+ pinctrl-0 = <&touchscreen_default>;
+ pinctrl-names = "default";
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <2400>;
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 2>, /* SMB1394 (SPMI) */
+ <48 4>, /* Presumably NFC SE */
+ <56 4>; /* Presumably fingerprint reader */
+
+ qup_uart7_sleep_cts: qup-uart7-sleep-cts-state {
+ pins = "gpio28";
+ function = "gpio";
+ /*
+ * Configure a bias-bus-hold on CTS to lower power
+ * usage when Bluetooth is turned off. Bus hold will
+ * maintain a low power state regardless of whether
+ * the Bluetooth module drives the pin in either
+ * direction or leaves the pin fully unpowered.
+ */
+ bias-bus-hold;
+ };
+
+ qup_uart7_sleep_rts: qup-uart7-sleep-rts-state {
+ pins = "gpio29";
+ function = "gpio";
+ /*
+ * Configure pull-down on RTS. As RTS is active low
+ * signal, pull it low to indicate the BT SoC that it
+ * can wakeup the system anytime from suspend state by
+ * pulling RX low (by sending wakeup bytes).
+ */
+ bias-pull-down;
+ };
+
+ qup_uart7_sleep_tx: qup-uart7-sleep-tx-state {
+ pins = "gpio30";
+ function = "gpio";
+ /*
+ * Configure pull-up on TX when it isn't actively driven
+ * to prevent BT SoC from receiving garbage during sleep.
+ */
+ bias-pull-up;
+ };
+
+ qup_uart7_sleep_rx: qup-uart7-sleep-rx-state {
+ pins = "gpio31";
+ function = "gpio";
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module
+ * is floating which may cause spurious wakeups.
+ */
+ bias-pull-up;
+ };
+
+ bluetooth_enable_default: bluetooth-enable-default-state {
+ pins = "gpio85";
+ function = "gpio";
+ output-low;
+ bias-disable;
+ };
+
+ sw_ctrl_default: sw-ctrl-default-state {
+ pins = "gpio86";
+ function = "gpio";
+ bias-pull-down;
+ };
+
+ touchscreen_default: touchscreen-default-state {
+ pins = "gpio81", "gpio105";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ pm8008_int_default: pm8008-int-default-state {
+ pins = "gpio25";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&uart5 {
+ compatible = "qcom,geni-debug-uart";
+
+ status = "okay";
+};
+
+&uart7 {
+ /delete-property/interrupts;
+ interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-1 = <&qup_uart7_sleep_cts>,
+ <&qup_uart7_sleep_rts>,
+ <&qup_uart7_sleep_tx>,
+ <&qup_uart7_sleep_rx>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+
+ bluetooth: bluetooth {
+ compatible = "qcom,wcn6750-bt";
+
+ pinctrl-0 = <&bluetooth_enable_default>, <&sw_ctrl_default>;
+ pinctrl-names = "default";
+
+ enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
+ swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>;
+
+ vddio-supply = <&vreg_l19b_1p8>;
+ vddaon-supply = <&vreg_s7b_0p952>;
+ vddbtcxmx-supply = <&vreg_s7b_0p952>;
+ vddrfacmn-supply = <&vreg_s7b_0p952>;
+ vddrfa0p8-supply = <&vreg_s7b_0p952>;
+ vddrfa1p2-supply = <&vdd13_pmu_rfa_i>;
+ vddrfa1p7-supply = <&vdd19_pmu_rfa_i>;
+ vddrfa2p2-supply = <&vreg_s1c_2p2>;
+ vddasd-supply = <&vreg_l11c_2p8>;
+ max-speed = <3200000>;
+
+ qcom,local-bd-address-broken;
+ };
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l7b_2p96>;
+ vcc-max-microamp = <800000>;
+ /*
+ * Technically l9b enables an eLDO (supplied by s1b) which then powers
+ * VCCQ2 of the UFS.
+ */
+ vccq-supply = <&vreg_l9b_1p2>;
+ vccq-max-microamp = <900000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vdd_a_ufs_0_core>;
+ vdda-pll-supply = <&vdd_a_ufs_0_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ qcom,select-utmi-as-pipe-clk;
+
+ maximum-speed = "high-speed";
+ phys = <&usb_1_hsphy>;
+ phy-names = "usb2-phy";
+
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&vdd_a_usbhs_core>;
+ vdda18-supply = <&vdd_a_usbhs_1p8>;
+ vdda33-supply = <&vdd_a_usbhs_3p1>;
+
+ status = "okay";
+};
+
+&venus {
+ firmware-name = "qcom/sm7325/xiaomi/lisa/vpu20_1v.mbn";
+
+ status = "okay";
+};
+
+&wifi {
+ status = "okay";
+};
--
2.55.0
^ permalink raw reply related
* [PATCH v3 1/2] dt-bindings: arm: qcom: Add Xiaomi 11 Lite 5G NE
From: Oleksii Onchul @ 2026-07-17 13:22 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel, Oleksii Onchul, Krzysztof Kozlowski
In-Reply-To: <20260717132218.27007-1-oleksiionchul@gmail.com>
Add the compatible for the Xiaomi 11 Lite 5G NE, codenamed lisa,
which is based on the Qualcomm SM7325 SoC.
Signed-off-by: Oleksii Onchul <oleksiionchul@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 0b4c17419..494d1425d 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -1080,6 +1080,7 @@ properties:
- enum:
- motorola,dubai
- nothing,spacewar
+ - xiaomi,lisa
- xiaomi,taoyao
- const: qcom,sm7325
--
2.55.0
^ permalink raw reply related
* [PATCH v3 0/2] arm64: dts: qcom: Add Xiaomi 11 Lite 5G NE
From: Oleksii Onchul @ 2026-07-17 13:22 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel, Oleksii Onchul
Add initial support for the Xiaomi 11 Lite 5G NE, codenamed lisa.
The supported hardware includes regulators, UFS, USB, GPU, remote
processors, Wi-Fi, Bluetooth, touchscreen, flash LED, thermal sensors
and the hardware buttons.
Link to v2: https://lore.kernel.org/all/20260714125806.310708-1-oleksiionchul@gmail.com/
Changes in v3:
- Keep a blank line before status properties.
- Use interrupts-extended for the touchscreen interrupt.
Changes in v2:
- Drop SD card support because card detection is not reliable yet.
- Constrain the UFS VCC rail to 2.952 V.
- Drop the unused FSA4480 interrupt.
- Add the touchscreen pinctrl state.
- Reference the reserved framebuffer through memory-region.
- Enable ramoops ECC and use decimal notation for mem-type.
- Allow the unused camera PMIC regulators to be disabled.
- Document all GPIO reserved ranges inline.
- Replace underscores in node names with hyphens.
- Drop the unverified USB limitation comment.
- Drop IPA properties now provided by kodiak.dtsi.
- Drop redundant USB role properties.
Oleksii Onchul (2):
dt-bindings: arm: qcom: Add Xiaomi 11 Lite 5G NE
arm64: dts: qcom: Add Xiaomi 11 Lite 5G NE
.../devicetree/bindings/arm/qcom.yaml | 1 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/sm7325-xiaomi-lisa.dts | 1108 +++++++++++++++++
3 files changed, 1110 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm7325-xiaomi-lisa.dts
base-commit: 1c553b3d0cfca9cac2186daea6e2f81808ce7d8b
--
2.55.0
^ permalink raw reply
* Re: [PATCH 4/4] arm64: dts: qcom: Add Glymur QCB
From: Konrad Dybcio @ 2026-07-17 13:24 UTC (permalink / raw)
To: Gopikrishna Garmidi, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Anvesh Jain P, Sibi Sankar,
Pankaj Patil
Cc: Rajendra Nayak, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260717-glymur-qcb-v1-4-aaf1cff84aab@oss.qualcomm.com>
On 7/17/26 1:54 PM, Gopikrishna Garmidi wrote:
> The Glymur QCB (Qualcomm Compute Board) is a Glymur-based board in an
> open form factor, aimed at compute bring-up and power/signal measurement
> rather than the closed enclosure of the CRD.
>
> Add its device tree. The board boots to a shell over the uart21 console
> with its root filesystem on NVMe. Enabled so far:
>
> - Board and sleep clocks
> - Volume up/down keys
> - PMIC RPMH regulators (banks 0 - 4) and the NVMe, WWAN and WCN rails
> - PCIe4/5/6 controllers and PHYs, with their PERST/WAKE/CLKREQ lines
> - WCN7850 WiFi on PCIe4 and Bluetooth on UART14
> - Embedded controller on I2C9
> - ADSP,CDSP and SoCCP remote processors
>
> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH 2/3] regulator: pfuze100: add set_suspend_disable for LDO ops
From: Mark Brown @ 2026-07-17 13:22 UTC (permalink / raw)
To: Joy Zou
Cc: Liam Girdwood, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Ye Li, Jacky Bai, Peng Fan, Dong Aisheng, linux-kernel,
devicetree, imx, linux-arm-kernel
In-Reply-To: <20260716-b4-regulator-pf01-v1-2-8c1519d54bd4@oss.nxp.com>
[-- Attachment #1: Type: text/plain, Size: 1200 bytes --]
On Thu, Jul 16, 2026 at 11:50:54AM +0800, Joy Zou wrote:
> Add set_suspend_disable callback to pfuze100_ldo_regulator_ops to
> support regulator-off-in-suspend DTS property for VGEN regulators.
> This allows unused LDO regulators to be properly disabled during
> system suspend, reducing power consumption.
> +static int pfuze100_set_suspend_disable(struct regulator_dev *rdev)
This looks to be only used for LDOs but is named like it applies to all
regulators the driver supports.
> +{
> + struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
> + int id = rdev_get_id(rdev);
> +
> + /*
> + * Set VGENxSTBY and clear VGENxLPWR so that the LDO output is
> + * disabled when the PMIC receives a STANDBY event.
> + * EN=1, LPWR=0, STBY=1 results in output Off when STANDBY is asserted.
> + */
> + return regmap_update_bits(pfuze100->regmap,
> + pfuze100->regulator_descs[id].stby_reg,
> + PFUZE100_VGENxSTBY | PFUZE100_VGENxLPWR,
> + PFUZE100_VGENxSTBY);
> +}
This is a fixed bit in the register, but I see other regulators have
_stby_mask configuration. Are you sure that all the LDOs in all the
regulators covered by this driver have this feature with this exact
control bit?
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* [PATCH v2 3/3] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Use common pinctrl
From: Luca Weiss @ 2026-07-17 13:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel, Luca Weiss
In-Reply-To: <20260717-kodiak-cam-mclk-v2-0-04451f1374bd@fairphone.com>
Since there's already a define for gpio67 (mclk3) in kodiak.dtsi, use
that instead of defining an extra pinctrl state. Also rename the suspend
state to match naming.
No functional change intended.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
.../boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso | 13 +++----------
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso
index b9e4a5214f70..aceafea45343 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso
@@ -51,8 +51,8 @@ camera@1a {
reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "suspend";
- pinctrl-0 = <&cam2_default>;
- pinctrl-1 = <&cam2_suspend>;
+ pinctrl-0 = <&cam_mclk3_default>;
+ pinctrl-1 = <&cam_mclk3_suspend>;
clocks = <&camcc CAM_CC_MCLK3_CLK>;
assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>;
@@ -73,14 +73,7 @@ imx577_ep: endpoint {
};
&tlmm {
- cam2_default: cam2-default-state {
- pins = "gpio67";
- function = "cam_mclk";
- drive-strength = <2>;
- bias-disable;
- };
-
- cam2_suspend: cam2-suspend-state {
+ cam_mclk3_suspend: cam-mclk3-suspend-state {
pins = "gpio67";
function = "cam_mclk";
drive-strength = <2>;
--
2.55.0
^ permalink raw reply related
* [PATCH v2 2/3] arm64: dts: qcom: kodiak: Add camera mclk pinctrl definitions
From: Luca Weiss @ 2026-07-17 13:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel, Luca Weiss, Konrad Dybcio, Vladimir Zapolskiy
In-Reply-To: <20260717-kodiak-cam-mclk-v2-0-04451f1374bd@fairphone.com>
On different boards the cameras are connected to different pins with the
cam_mclk function. Add the definitions so that mclk0-5 are covered.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index d5fc38fc10ed..13f1c205c07e 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -6521,6 +6521,27 @@ qup_uart15_rx: qup-uart15-rx-state {
function = "qup17";
};
+ cam_mclk0_default: cam-mclk0-default-state {
+ pins = "gpio64";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk1_default: cam-mclk1-default-state {
+ pins = "gpio65";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cam_mclk2_default: cam-mclk2-default-state {
+ pins = "gpio66";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
cam_mclk3_default: cam-mclk3-default-state {
pins = "gpio67";
function = "cam_mclk";
@@ -6528,6 +6549,13 @@ cam_mclk3_default: cam-mclk3-default-state {
bias-disable;
};
+ cam_mclk4_default: cam-mclk4-default-state {
+ pins = "gpio68";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
cci0_default: cci0-default-state {
pins = "gpio69", "gpio70";
function = "cci_i2c";
@@ -6594,6 +6622,13 @@ pcie0_clkreq_n: pcie0-clkreq-n-state {
function = "pcie0_clkreqn";
};
+ cam_mclk5_default: cam-mclk5-default-state {
+ pins = "gpio93";
+ function = "cam_mclk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
mi2s0_mclk: mi2s0-mclk-state {
pins = "gpio96";
function = "pri_mi2s";
--
2.55.0
^ permalink raw reply related
* [PATCH v2 1/3] arm64: dts: qcom: kodiak: Sort pinctrl subnodes by pins
From: Luca Weiss @ 2026-07-17 13:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel, Luca Weiss, Dmitry Baryshkov
In-Reply-To: <20260717-kodiak-cam-mclk-v2-0-04451f1374bd@fairphone.com>
As documented in the "Devicetree Sources (DTS) Coding Style" document,
pinctrl subnodes should be sorted by the pins property. Do this once for
kodiak.dtsi so that future additions can be added at the right places.
No functional change intended, verified with dtx_diff.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 1382 +++++++++++++++++-----------------
1 file changed, 691 insertions(+), 691 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 7e73348fe0d0..d5fc38fc10ed 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -5851,6 +5851,676 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+ pins = "gpio0", "gpio1";
+ function = "qup00";
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ pins = "gpio0", "gpio1", "gpio2";
+ function = "qup00";
+ };
+
+ qup_uart0_cts: qup-uart0-cts-state {
+ pins = "gpio0";
+ function = "qup00";
+ };
+
+ qup_uart0_rts: qup-uart0-rts-state {
+ pins = "gpio1";
+ function = "qup00";
+ };
+
+ qup_uart0_tx: qup-uart0-tx-state {
+ pins = "gpio2";
+ function = "qup00";
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio3";
+ function = "qup00";
+ };
+
+ qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
+ pins = "gpio3";
+ function = "gpio";
+ };
+
+ qup_uart0_rx: qup-uart0-rx-state {
+ pins = "gpio3";
+ function = "qup00";
+ };
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ pins = "gpio4", "gpio5";
+ function = "qup01";
+ };
+
+ qup_spi1_data_clk: qup-spi1-data-clk-state {
+ pins = "gpio4", "gpio5", "gpio6";
+ function = "qup01";
+ };
+
+ qup_uart1_cts: qup-uart1-cts-state {
+ pins = "gpio4";
+ function = "qup01";
+ };
+
+ qup_uart1_rts: qup-uart1-rts-state {
+ pins = "gpio5";
+ function = "qup01";
+ };
+
+ qup_uart1_tx: qup-uart1-tx-state {
+ pins = "gpio6";
+ function = "qup01";
+ };
+
+ qup_spi1_cs: qup-spi1-cs-state {
+ pins = "gpio7";
+ function = "qup01";
+ };
+
+ qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
+ pins = "gpio7";
+ function = "gpio";
+ };
+
+ qup_uart1_rx: qup-uart1-rx-state {
+ pins = "gpio7";
+ function = "qup01";
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+ pins = "gpio8", "gpio9";
+ function = "qup02";
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
+ pins = "gpio8", "gpio9", "gpio10";
+ function = "qup02";
+ };
+
+ qup_uart2_cts: qup-uart2-cts-state {
+ pins = "gpio8";
+ function = "qup02";
+ };
+
+ qup_uart2_rts: qup-uart2-rts-state {
+ pins = "gpio9";
+ function = "qup02";
+ };
+
+ qup_uart2_tx: qup-uart2-tx-state {
+ pins = "gpio10";
+ function = "qup02";
+ };
+
+ qup_spi2_cs: qup-spi2-cs-state {
+ pins = "gpio11";
+ function = "qup02";
+ };
+
+ qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
+ pins = "gpio11";
+ function = "gpio";
+ };
+
+ qup_uart2_rx: qup-uart2-rx-state {
+ pins = "gpio11";
+ function = "qup02";
+ };
+
+ qspi_data0: qspi-data0-state {
+ pins = "gpio12";
+ function = "qspi_data";
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ pins = "gpio12", "gpio13";
+ function = "qup03";
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk-state {
+ pins = "gpio12", "gpio13", "gpio14";
+ function = "qup03";
+ };
+
+ qup_uart3_cts: qup-uart3-cts-state {
+ pins = "gpio12";
+ function = "qup03";
+ };
+
+ qspi_data1: qspi-data1-state {
+ pins = "gpio13";
+ function = "qspi_data";
+ };
+
+ qup_uart3_rts: qup-uart3-rts-state {
+ pins = "gpio13";
+ function = "qup03";
+ };
+
+ qspi_clk: qspi-clk-state {
+ pins = "gpio14";
+ function = "qspi_clk";
+ };
+
+ qup_uart3_tx: qup-uart3-tx-state {
+ pins = "gpio14";
+ function = "qup03";
+ };
+
+ qspi_cs0: qspi-cs0-state {
+ pins = "gpio15";
+ function = "qspi_cs";
+ };
+
+ qup_spi3_cs: qup-spi3-cs-state {
+ pins = "gpio15";
+ function = "qup03";
+ };
+
+ qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
+ pins = "gpio15";
+ function = "gpio";
+ };
+
+ qup_uart3_rx: qup-uart3-rx-state {
+ pins = "gpio15";
+ function = "qup03";
+ };
+
+ qspi_data23: qspi-data23-state {
+ pins = "gpio16", "gpio17";
+ function = "qspi_data";
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+ pins = "gpio16", "gpio17";
+ function = "qup04";
+ };
+
+ qup_spi4_data_clk: qup-spi4-data-clk-state {
+ pins = "gpio16", "gpio17", "gpio18";
+ function = "qup04";
+ };
+
+ qup_uart4_cts: qup-uart4-cts-state {
+ pins = "gpio16";
+ function = "qup04";
+ };
+
+ qup_uart4_rts: qup-uart4-rts-state {
+ pins = "gpio17";
+ function = "qup04";
+ };
+
+ qup_uart4_tx: qup-uart4-tx-state {
+ pins = "gpio18";
+ function = "qup04";
+ };
+
+ qspi_cs1: qspi-cs1-state {
+ pins = "gpio19";
+ function = "qspi_cs";
+ };
+
+ qup_spi4_cs: qup-spi4-cs-state {
+ pins = "gpio19";
+ function = "qup04";
+ };
+
+ qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
+ pins = "gpio19";
+ function = "gpio";
+ };
+
+ qup_uart4_rx: qup-uart4-rx-state {
+ pins = "gpio19";
+ function = "qup04";
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+ pins = "gpio20", "gpio21";
+ function = "qup05";
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
+ pins = "gpio20", "gpio21", "gpio22";
+ function = "qup05";
+ };
+
+ qup_uart5_tx: qup-uart5-tx-state {
+ pins = "gpio22";
+ function = "qup05";
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio23";
+ function = "qup05";
+ };
+
+ qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
+ pins = "gpio23";
+ function = "gpio";
+ };
+
+ qup_uart5_rx: qup-uart5-rx-state {
+ pins = "gpio23";
+ function = "qup05";
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+ pins = "gpio24", "gpio25";
+ function = "qup06";
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
+ pins = "gpio24", "gpio25", "gpio26";
+ function = "qup06";
+ };
+
+ qup_uart6_cts: qup-uart6-cts-state {
+ pins = "gpio24";
+ function = "qup06";
+ };
+
+ qup_uart6_rts: qup-uart6-rts-state {
+ pins = "gpio25";
+ function = "qup06";
+ };
+
+ qup_uart6_tx: qup-uart6-tx-state {
+ pins = "gpio26";
+ function = "qup06";
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio27";
+ function = "qup06";
+ };
+
+ qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
+ pins = "gpio27";
+ function = "gpio";
+ };
+
+ qup_uart6_rx: qup-uart6-rx-state {
+ pins = "gpio27";
+ function = "qup06";
+ };
+
+ qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+ pins = "gpio28", "gpio29";
+ function = "qup07";
+ };
+
+ qup_spi7_data_clk: qup-spi7-data-clk-state {
+ pins = "gpio28", "gpio29", "gpio30";
+ function = "qup07";
+ };
+
+ qup_uart7_cts: qup-uart7-cts-state {
+ pins = "gpio28";
+ function = "qup07";
+ };
+
+ qup_uart7_rts: qup-uart7-rts-state {
+ pins = "gpio29";
+ function = "qup07";
+ };
+
+ qup_uart7_tx: qup-uart7-tx-state {
+ pins = "gpio30";
+ function = "qup07";
+ };
+
+ qup_spi7_cs: qup-spi7-cs-state {
+ pins = "gpio31";
+ function = "qup07";
+ };
+
+ qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
+ pins = "gpio31";
+ function = "gpio";
+ };
+
+ qup_uart7_rx: qup-uart7-rx-state {
+ pins = "gpio31";
+ function = "qup07";
+ };
+
+ qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+ pins = "gpio32", "gpio33";
+ function = "qup10";
+ };
+
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
+ pins = "gpio32", "gpio33", "gpio34";
+ function = "qup10";
+ };
+
+ qup_uart8_cts: qup-uart8-cts-state {
+ pins = "gpio32";
+ function = "qup10";
+ };
+
+ qup_uart8_rts: qup-uart8-rts-state {
+ pins = "gpio33";
+ function = "qup10";
+ };
+
+ qup_uart8_tx: qup-uart8-tx-state {
+ pins = "gpio34";
+ function = "qup10";
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ pins = "gpio35";
+ function = "qup10";
+ };
+
+ qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ qup_uart8_rx: qup-uart8-rx-state {
+ pins = "gpio35";
+ function = "qup10";
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+ pins = "gpio36", "gpio37";
+ function = "qup11";
+ };
+
+ qup_spi9_data_clk: qup-spi9-data-clk-state {
+ pins = "gpio36", "gpio37", "gpio38";
+ function = "qup11";
+ };
+
+ qup_uart9_cts: qup-uart9-cts-state {
+ pins = "gpio36";
+ function = "qup11";
+ };
+
+ qup_uart9_rts: qup-uart9-rts-state {
+ pins = "gpio37";
+ function = "qup11";
+ };
+
+ qup_uart9_tx: qup-uart9-tx-state {
+ pins = "gpio38";
+ function = "qup11";
+ };
+
+ qup_spi9_cs: qup-spi9-cs-state {
+ pins = "gpio39";
+ function = "qup11";
+ };
+
+ qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
+ pins = "gpio39";
+ function = "gpio";
+ };
+
+ qup_uart9_rx: qup-uart9-rx-state {
+ pins = "gpio39";
+ function = "qup11";
+ };
+
+ qup_i2c10_data_clk: qup-i2c10-data-clk-state {
+ pins = "gpio40", "gpio41";
+ function = "qup12";
+ };
+
+ qup_spi10_data_clk: qup-spi10-data-clk-state {
+ pins = "gpio40", "gpio41", "gpio42";
+ function = "qup12";
+ };
+
+ qup_uart10_cts: qup-uart10-cts-state {
+ pins = "gpio40";
+ function = "qup12";
+ };
+
+ qup_uart10_rts: qup-uart10-rts-state {
+ pins = "gpio41";
+ function = "qup12";
+ };
+
+ qup_uart10_tx: qup-uart10-tx-state {
+ pins = "gpio42";
+ function = "qup12";
+ };
+
+ qup_spi10_cs: qup-spi10-cs-state {
+ pins = "gpio43";
+ function = "qup12";
+ };
+
+ qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
+ pins = "gpio43";
+ function = "gpio";
+ };
+
+ qup_uart10_rx: qup-uart10-rx-state {
+ pins = "gpio43";
+ function = "qup12";
+ };
+
+ qup_i2c11_data_clk: qup-i2c11-data-clk-state {
+ pins = "gpio44", "gpio45";
+ function = "qup13";
+ };
+
+ qup_spi11_data_clk: qup-spi11-data-clk-state {
+ pins = "gpio44", "gpio45", "gpio46";
+ function = "qup13";
+ };
+
+ qup_uart11_cts: qup-uart11-cts-state {
+ pins = "gpio44";
+ function = "qup13";
+ };
+
+ qup_uart11_rts: qup-uart11-rts-state {
+ pins = "gpio45";
+ function = "qup13";
+ };
+
+ qup_uart11_tx: qup-uart11-tx-state {
+ pins = "gpio46";
+ function = "qup13";
+ };
+
+ dp_hot_plug_det: dp-hot-plug-det-state {
+ pins = "gpio47";
+ function = "dp_hot";
+ };
+
+ qup_spi11_cs: qup-spi11-cs-state {
+ pins = "gpio47";
+ function = "qup13";
+ };
+
+ qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
+ pins = "gpio47";
+ function = "gpio";
+ };
+
+ qup_uart11_rx: qup-uart11-rx-state {
+ pins = "gpio47";
+ function = "qup13";
+ };
+
+ qup_i2c12_data_clk: qup-i2c12-data-clk-state {
+ pins = "gpio48", "gpio49";
+ function = "qup14";
+ };
+
+ qup_spi12_data_clk: qup-spi12-data-clk-state {
+ pins = "gpio48", "gpio49", "gpio50";
+ function = "qup14";
+ };
+
+ qup_uart12_cts: qup-uart12-cts-state {
+ pins = "gpio48";
+ function = "qup14";
+ };
+
+ qup_uart12_rts: qup-uart12-rts-state {
+ pins = "gpio49";
+ function = "qup14";
+ };
+
+ qup_uart12_tx: qup-uart12-tx-state {
+ pins = "gpio50";
+ function = "qup14";
+ };
+
+ qup_spi12_cs: qup-spi12-cs-state {
+ pins = "gpio51";
+ function = "qup14";
+ };
+
+ qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
+ pins = "gpio51";
+ function = "gpio";
+ };
+
+ qup_uart12_rx: qup-uart12-rx-state {
+ pins = "gpio51";
+ function = "qup14";
+ };
+
+ qup_i2c13_data_clk: qup-i2c13-data-clk-state {
+ pins = "gpio52", "gpio53";
+ function = "qup15";
+ };
+
+ qup_spi13_data_clk: qup-spi13-data-clk-state {
+ pins = "gpio52", "gpio53", "gpio54";
+ function = "qup15";
+ };
+
+ qup_uart13_cts: qup-uart13-cts-state {
+ pins = "gpio52";
+ function = "qup15";
+ };
+
+ qup_uart13_rts: qup-uart13-rts-state {
+ pins = "gpio53";
+ function = "qup15";
+ };
+
+ qup_uart13_tx: qup-uart13-tx-state {
+ pins = "gpio54";
+ function = "qup15";
+ };
+
+ qup_spi13_cs: qup-spi13-cs-state {
+ pins = "gpio55";
+ function = "qup15";
+ };
+
+ qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
+ pins = "gpio55";
+ function = "gpio";
+ };
+
+ qup_uart13_rx: qup-uart13-rx-state {
+ pins = "gpio55";
+ function = "qup15";
+ };
+
+ qup_i2c14_data_clk: qup-i2c14-data-clk-state {
+ pins = "gpio56", "gpio57";
+ function = "qup16";
+ };
+
+ qup_spi14_data_clk: qup-spi14-data-clk-state {
+ pins = "gpio56", "gpio57", "gpio58";
+ function = "qup16";
+ };
+
+ qup_uart14_cts: qup-uart14-cts-state {
+ pins = "gpio56";
+ function = "qup16";
+ };
+
+ qup_uart14_rts: qup-uart14-rts-state {
+ pins = "gpio57";
+ function = "qup16";
+ };
+
+ qup_uart14_tx: qup-uart14-tx-state {
+ pins = "gpio58";
+ function = "qup16";
+ };
+
+ qup_spi14_cs: qup-spi14-cs-state {
+ pins = "gpio59";
+ function = "qup16";
+ };
+
+ qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
+ pins = "gpio59";
+ function = "gpio";
+ };
+
+ qup_uart14_rx: qup-uart14-rx-state {
+ pins = "gpio59";
+ function = "qup16";
+ };
+
+ edp_hot_plug_det: edp-hot-plug-det-state {
+ pins = "gpio60";
+ function = "edp_hot";
+ };
+
+ qup_i2c15_data_clk: qup-i2c15-data-clk-state {
+ pins = "gpio60", "gpio61";
+ function = "qup17";
+ };
+
+ qup_spi15_data_clk: qup-spi15-data-clk-state {
+ pins = "gpio60", "gpio61", "gpio62";
+ function = "qup17";
+ };
+
+ qup_uart15_cts: qup-uart15-cts-state {
+ pins = "gpio60";
+ function = "qup17";
+ };
+
+ qup_uart15_rts: qup-uart15-rts-state {
+ pins = "gpio61";
+ function = "qup17";
+ };
+
+ qup_uart15_tx: qup-uart15-tx-state {
+ pins = "gpio62";
+ function = "qup17";
+ };
+
+ qup_spi15_cs: qup-spi15-cs-state {
+ pins = "gpio63";
+ function = "qup17";
+ };
+
+ qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
+ pins = "gpio63";
+ function = "gpio";
+ };
+
+ qup_uart15_rx: qup-uart15-rx-state {
+ pins = "gpio63";
+ function = "qup17";
+ };
+
cam_mclk3_default: cam-mclk3-default-state {
pins = "gpio67";
function = "cam_mclk";
@@ -5914,24 +6584,14 @@ cci3_sleep: cci3-sleep-state {
bias-pull-down;
};
- dp_hot_plug_det: dp-hot-plug-det-state {
- pins = "gpio47";
- function = "dp_hot";
+ pcie1_clkreq_n: pcie1-clkreq-n-state {
+ pins = "gpio79";
+ function = "pcie1_clkreqn";
};
- edp_hot_plug_det: edp-hot-plug-det-state {
- pins = "gpio60";
- function = "edp_hot";
- };
-
- mi2s0_data0: mi2s0-data0-state {
- pins = "gpio98";
- function = "mi2s0_data0";
- };
-
- mi2s0_data1: mi2s0-data1-state {
- pins = "gpio99";
- function = "mi2s0_data1";
+ pcie0_clkreq_n: pcie0-clkreq-n-state {
+ pins = "gpio88";
+ function = "pcie0_clkreqn";
};
mi2s0_mclk: mi2s0-mclk-state {
@@ -5944,696 +6604,36 @@ mi2s0_sclk: mi2s0-sclk-state {
function = "mi2s0_sck";
};
+ mi2s0_data0: mi2s0-data0-state {
+ pins = "gpio98";
+ function = "mi2s0_data0";
+ };
+
+ mi2s0_data1: mi2s0-data1-state {
+ pins = "gpio99";
+ function = "mi2s0_data1";
+ };
+
mi2s0_ws: mi2s0-ws-state {
pins = "gpio100";
function = "mi2s0_ws";
};
- mi2s1_data0: mi2s1-data0-state {
- pins = "gpio107";
- function = "mi2s1_data0";
- };
-
mi2s1_sclk: mi2s1-sclk-state {
pins = "gpio106";
function = "mi2s1_sck";
};
+ mi2s1_data0: mi2s1-data0-state {
+ pins = "gpio107";
+ function = "mi2s1_data0";
+ };
+
mi2s1_ws: mi2s1-ws-state {
pins = "gpio108";
function = "mi2s1_ws";
};
- pcie0_clkreq_n: pcie0-clkreq-n-state {
- pins = "gpio88";
- function = "pcie0_clkreqn";
- };
-
- pcie1_clkreq_n: pcie1-clkreq-n-state {
- pins = "gpio79";
- function = "pcie1_clkreqn";
- };
-
- qspi_clk: qspi-clk-state {
- pins = "gpio14";
- function = "qspi_clk";
- };
-
- qspi_cs0: qspi-cs0-state {
- pins = "gpio15";
- function = "qspi_cs";
- };
-
- qspi_cs1: qspi-cs1-state {
- pins = "gpio19";
- function = "qspi_cs";
- };
-
- qspi_data0: qspi-data0-state {
- pins = "gpio12";
- function = "qspi_data";
- };
-
- qspi_data1: qspi-data1-state {
- pins = "gpio13";
- function = "qspi_data";
- };
-
- qspi_data23: qspi-data23-state {
- pins = "gpio16", "gpio17";
- function = "qspi_data";
- };
-
- qup_i2c0_data_clk: qup-i2c0-data-clk-state {
- pins = "gpio0", "gpio1";
- function = "qup00";
- };
-
- qup_i2c1_data_clk: qup-i2c1-data-clk-state {
- pins = "gpio4", "gpio5";
- function = "qup01";
- };
-
- qup_i2c2_data_clk: qup-i2c2-data-clk-state {
- pins = "gpio8", "gpio9";
- function = "qup02";
- };
-
- qup_i2c3_data_clk: qup-i2c3-data-clk-state {
- pins = "gpio12", "gpio13";
- function = "qup03";
- };
-
- qup_i2c4_data_clk: qup-i2c4-data-clk-state {
- pins = "gpio16", "gpio17";
- function = "qup04";
- };
-
- qup_i2c5_data_clk: qup-i2c5-data-clk-state {
- pins = "gpio20", "gpio21";
- function = "qup05";
- };
-
- qup_i2c6_data_clk: qup-i2c6-data-clk-state {
- pins = "gpio24", "gpio25";
- function = "qup06";
- };
-
- qup_i2c7_data_clk: qup-i2c7-data-clk-state {
- pins = "gpio28", "gpio29";
- function = "qup07";
- };
-
- qup_i2c8_data_clk: qup-i2c8-data-clk-state {
- pins = "gpio32", "gpio33";
- function = "qup10";
- };
-
- qup_i2c9_data_clk: qup-i2c9-data-clk-state {
- pins = "gpio36", "gpio37";
- function = "qup11";
- };
-
- qup_i2c10_data_clk: qup-i2c10-data-clk-state {
- pins = "gpio40", "gpio41";
- function = "qup12";
- };
-
- qup_i2c11_data_clk: qup-i2c11-data-clk-state {
- pins = "gpio44", "gpio45";
- function = "qup13";
- };
-
- qup_i2c12_data_clk: qup-i2c12-data-clk-state {
- pins = "gpio48", "gpio49";
- function = "qup14";
- };
-
- qup_i2c13_data_clk: qup-i2c13-data-clk-state {
- pins = "gpio52", "gpio53";
- function = "qup15";
- };
-
- qup_i2c14_data_clk: qup-i2c14-data-clk-state {
- pins = "gpio56", "gpio57";
- function = "qup16";
- };
-
- qup_i2c15_data_clk: qup-i2c15-data-clk-state {
- pins = "gpio60", "gpio61";
- function = "qup17";
- };
-
- qup_spi0_data_clk: qup-spi0-data-clk-state {
- pins = "gpio0", "gpio1", "gpio2";
- function = "qup00";
- };
-
- qup_spi0_cs: qup-spi0-cs-state {
- pins = "gpio3";
- function = "qup00";
- };
-
- qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
- pins = "gpio3";
- function = "gpio";
- };
-
- qup_spi1_data_clk: qup-spi1-data-clk-state {
- pins = "gpio4", "gpio5", "gpio6";
- function = "qup01";
- };
-
- qup_spi1_cs: qup-spi1-cs-state {
- pins = "gpio7";
- function = "qup01";
- };
-
- qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
- pins = "gpio7";
- function = "gpio";
- };
-
- qup_spi2_data_clk: qup-spi2-data-clk-state {
- pins = "gpio8", "gpio9", "gpio10";
- function = "qup02";
- };
-
- qup_spi2_cs: qup-spi2-cs-state {
- pins = "gpio11";
- function = "qup02";
- };
-
- qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
- pins = "gpio11";
- function = "gpio";
- };
-
- qup_spi3_data_clk: qup-spi3-data-clk-state {
- pins = "gpio12", "gpio13", "gpio14";
- function = "qup03";
- };
-
- qup_spi3_cs: qup-spi3-cs-state {
- pins = "gpio15";
- function = "qup03";
- };
-
- qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
- pins = "gpio15";
- function = "gpio";
- };
-
- qup_spi4_data_clk: qup-spi4-data-clk-state {
- pins = "gpio16", "gpio17", "gpio18";
- function = "qup04";
- };
-
- qup_spi4_cs: qup-spi4-cs-state {
- pins = "gpio19";
- function = "qup04";
- };
-
- qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
- pins = "gpio19";
- function = "gpio";
- };
-
- qup_spi5_data_clk: qup-spi5-data-clk-state {
- pins = "gpio20", "gpio21", "gpio22";
- function = "qup05";
- };
-
- qup_spi5_cs: qup-spi5-cs-state {
- pins = "gpio23";
- function = "qup05";
- };
-
- qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
- pins = "gpio23";
- function = "gpio";
- };
-
- qup_spi6_data_clk: qup-spi6-data-clk-state {
- pins = "gpio24", "gpio25", "gpio26";
- function = "qup06";
- };
-
- qup_spi6_cs: qup-spi6-cs-state {
- pins = "gpio27";
- function = "qup06";
- };
-
- qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
- pins = "gpio27";
- function = "gpio";
- };
-
- qup_spi7_data_clk: qup-spi7-data-clk-state {
- pins = "gpio28", "gpio29", "gpio30";
- function = "qup07";
- };
-
- qup_spi7_cs: qup-spi7-cs-state {
- pins = "gpio31";
- function = "qup07";
- };
-
- qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
- pins = "gpio31";
- function = "gpio";
- };
-
- qup_spi8_data_clk: qup-spi8-data-clk-state {
- pins = "gpio32", "gpio33", "gpio34";
- function = "qup10";
- };
-
- qup_spi8_cs: qup-spi8-cs-state {
- pins = "gpio35";
- function = "qup10";
- };
-
- qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
- pins = "gpio35";
- function = "gpio";
- };
-
- qup_spi9_data_clk: qup-spi9-data-clk-state {
- pins = "gpio36", "gpio37", "gpio38";
- function = "qup11";
- };
-
- qup_spi9_cs: qup-spi9-cs-state {
- pins = "gpio39";
- function = "qup11";
- };
-
- qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
- pins = "gpio39";
- function = "gpio";
- };
-
- qup_spi10_data_clk: qup-spi10-data-clk-state {
- pins = "gpio40", "gpio41", "gpio42";
- function = "qup12";
- };
-
- qup_spi10_cs: qup-spi10-cs-state {
- pins = "gpio43";
- function = "qup12";
- };
-
- qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
- pins = "gpio43";
- function = "gpio";
- };
-
- qup_spi11_data_clk: qup-spi11-data-clk-state {
- pins = "gpio44", "gpio45", "gpio46";
- function = "qup13";
- };
-
- qup_spi11_cs: qup-spi11-cs-state {
- pins = "gpio47";
- function = "qup13";
- };
-
- qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
- pins = "gpio47";
- function = "gpio";
- };
-
- qup_spi12_data_clk: qup-spi12-data-clk-state {
- pins = "gpio48", "gpio49", "gpio50";
- function = "qup14";
- };
-
- qup_spi12_cs: qup-spi12-cs-state {
- pins = "gpio51";
- function = "qup14";
- };
-
- qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
- pins = "gpio51";
- function = "gpio";
- };
-
- qup_spi13_data_clk: qup-spi13-data-clk-state {
- pins = "gpio52", "gpio53", "gpio54";
- function = "qup15";
- };
-
- qup_spi13_cs: qup-spi13-cs-state {
- pins = "gpio55";
- function = "qup15";
- };
-
- qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
- pins = "gpio55";
- function = "gpio";
- };
-
- qup_spi14_data_clk: qup-spi14-data-clk-state {
- pins = "gpio56", "gpio57", "gpio58";
- function = "qup16";
- };
-
- qup_spi14_cs: qup-spi14-cs-state {
- pins = "gpio59";
- function = "qup16";
- };
-
- qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
- pins = "gpio59";
- function = "gpio";
- };
-
- qup_spi15_data_clk: qup-spi15-data-clk-state {
- pins = "gpio60", "gpio61", "gpio62";
- function = "qup17";
- };
-
- qup_spi15_cs: qup-spi15-cs-state {
- pins = "gpio63";
- function = "qup17";
- };
-
- qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
- pins = "gpio63";
- function = "gpio";
- };
-
- qup_uart0_cts: qup-uart0-cts-state {
- pins = "gpio0";
- function = "qup00";
- };
-
- qup_uart0_rts: qup-uart0-rts-state {
- pins = "gpio1";
- function = "qup00";
- };
-
- qup_uart0_tx: qup-uart0-tx-state {
- pins = "gpio2";
- function = "qup00";
- };
-
- qup_uart0_rx: qup-uart0-rx-state {
- pins = "gpio3";
- function = "qup00";
- };
-
- qup_uart1_cts: qup-uart1-cts-state {
- pins = "gpio4";
- function = "qup01";
- };
-
- qup_uart1_rts: qup-uart1-rts-state {
- pins = "gpio5";
- function = "qup01";
- };
-
- qup_uart1_tx: qup-uart1-tx-state {
- pins = "gpio6";
- function = "qup01";
- };
-
- qup_uart1_rx: qup-uart1-rx-state {
- pins = "gpio7";
- function = "qup01";
- };
-
- qup_uart2_cts: qup-uart2-cts-state {
- pins = "gpio8";
- function = "qup02";
- };
-
- qup_uart2_rts: qup-uart2-rts-state {
- pins = "gpio9";
- function = "qup02";
- };
-
- qup_uart2_tx: qup-uart2-tx-state {
- pins = "gpio10";
- function = "qup02";
- };
-
- qup_uart2_rx: qup-uart2-rx-state {
- pins = "gpio11";
- function = "qup02";
- };
-
- qup_uart3_cts: qup-uart3-cts-state {
- pins = "gpio12";
- function = "qup03";
- };
-
- qup_uart3_rts: qup-uart3-rts-state {
- pins = "gpio13";
- function = "qup03";
- };
-
- qup_uart3_tx: qup-uart3-tx-state {
- pins = "gpio14";
- function = "qup03";
- };
-
- qup_uart3_rx: qup-uart3-rx-state {
- pins = "gpio15";
- function = "qup03";
- };
-
- qup_uart4_cts: qup-uart4-cts-state {
- pins = "gpio16";
- function = "qup04";
- };
-
- qup_uart4_rts: qup-uart4-rts-state {
- pins = "gpio17";
- function = "qup04";
- };
-
- qup_uart4_tx: qup-uart4-tx-state {
- pins = "gpio18";
- function = "qup04";
- };
-
- qup_uart4_rx: qup-uart4-rx-state {
- pins = "gpio19";
- function = "qup04";
- };
-
- qup_uart5_tx: qup-uart5-tx-state {
- pins = "gpio22";
- function = "qup05";
- };
-
- qup_uart5_rx: qup-uart5-rx-state {
- pins = "gpio23";
- function = "qup05";
- };
-
- qup_uart6_cts: qup-uart6-cts-state {
- pins = "gpio24";
- function = "qup06";
- };
-
- qup_uart6_rts: qup-uart6-rts-state {
- pins = "gpio25";
- function = "qup06";
- };
-
- qup_uart6_tx: qup-uart6-tx-state {
- pins = "gpio26";
- function = "qup06";
- };
-
- qup_uart6_rx: qup-uart6-rx-state {
- pins = "gpio27";
- function = "qup06";
- };
-
- qup_uart7_cts: qup-uart7-cts-state {
- pins = "gpio28";
- function = "qup07";
- };
-
- qup_uart7_rts: qup-uart7-rts-state {
- pins = "gpio29";
- function = "qup07";
- };
-
- qup_uart7_tx: qup-uart7-tx-state {
- pins = "gpio30";
- function = "qup07";
- };
-
- qup_uart7_rx: qup-uart7-rx-state {
- pins = "gpio31";
- function = "qup07";
- };
-
- qup_uart8_cts: qup-uart8-cts-state {
- pins = "gpio32";
- function = "qup10";
- };
-
- qup_uart8_rts: qup-uart8-rts-state {
- pins = "gpio33";
- function = "qup10";
- };
-
- qup_uart8_tx: qup-uart8-tx-state {
- pins = "gpio34";
- function = "qup10";
- };
-
- qup_uart8_rx: qup-uart8-rx-state {
- pins = "gpio35";
- function = "qup10";
- };
-
- qup_uart9_cts: qup-uart9-cts-state {
- pins = "gpio36";
- function = "qup11";
- };
-
- qup_uart9_rts: qup-uart9-rts-state {
- pins = "gpio37";
- function = "qup11";
- };
-
- qup_uart9_tx: qup-uart9-tx-state {
- pins = "gpio38";
- function = "qup11";
- };
-
- qup_uart9_rx: qup-uart9-rx-state {
- pins = "gpio39";
- function = "qup11";
- };
-
- qup_uart10_cts: qup-uart10-cts-state {
- pins = "gpio40";
- function = "qup12";
- };
-
- qup_uart10_rts: qup-uart10-rts-state {
- pins = "gpio41";
- function = "qup12";
- };
-
- qup_uart10_tx: qup-uart10-tx-state {
- pins = "gpio42";
- function = "qup12";
- };
-
- qup_uart10_rx: qup-uart10-rx-state {
- pins = "gpio43";
- function = "qup12";
- };
-
- qup_uart11_cts: qup-uart11-cts-state {
- pins = "gpio44";
- function = "qup13";
- };
-
- qup_uart11_rts: qup-uart11-rts-state {
- pins = "gpio45";
- function = "qup13";
- };
-
- qup_uart11_tx: qup-uart11-tx-state {
- pins = "gpio46";
- function = "qup13";
- };
-
- qup_uart11_rx: qup-uart11-rx-state {
- pins = "gpio47";
- function = "qup13";
- };
-
- qup_uart12_cts: qup-uart12-cts-state {
- pins = "gpio48";
- function = "qup14";
- };
-
- qup_uart12_rts: qup-uart12-rts-state {
- pins = "gpio49";
- function = "qup14";
- };
-
- qup_uart12_tx: qup-uart12-tx-state {
- pins = "gpio50";
- function = "qup14";
- };
-
- qup_uart12_rx: qup-uart12-rx-state {
- pins = "gpio51";
- function = "qup14";
- };
-
- qup_uart13_cts: qup-uart13-cts-state {
- pins = "gpio52";
- function = "qup15";
- };
-
- qup_uart13_rts: qup-uart13-rts-state {
- pins = "gpio53";
- function = "qup15";
- };
-
- qup_uart13_tx: qup-uart13-tx-state {
- pins = "gpio54";
- function = "qup15";
- };
-
- qup_uart13_rx: qup-uart13-rx-state {
- pins = "gpio55";
- function = "qup15";
- };
-
- qup_uart14_cts: qup-uart14-cts-state {
- pins = "gpio56";
- function = "qup16";
- };
-
- qup_uart14_rts: qup-uart14-rts-state {
- pins = "gpio57";
- function = "qup16";
- };
-
- qup_uart14_tx: qup-uart14-tx-state {
- pins = "gpio58";
- function = "qup16";
- };
-
- qup_uart14_rx: qup-uart14-rx-state {
- pins = "gpio59";
- function = "qup16";
- };
-
- qup_uart15_cts: qup-uart15-cts-state {
- pins = "gpio60";
- function = "qup17";
- };
-
- qup_uart15_rts: qup-uart15-rts-state {
- pins = "gpio61";
- function = "qup17";
- };
-
- qup_uart15_tx: qup-uart15-tx-state {
- pins = "gpio62";
- function = "qup17";
- };
-
- qup_uart15_rx: qup-uart15-rx-state {
- pins = "gpio63";
- function = "qup17";
- };
-
sdc1_clk: sdc1-clk-state {
pins = "sdc1_clk";
};
--
2.55.0
^ permalink raw reply related
* [PATCH v2 0/3] Sort kodiak pinctrl nodes & add camera mclk definitions
From: Luca Weiss @ 2026-07-17 13:19 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, devicetree,
linux-kernel, Luca Weiss, Dmitry Baryshkov, Konrad Dybcio,
Vladimir Zapolskiy
First patch is just cleanup with no functional change, the second patch
adds some camera mclk pinctrl definitions for preparation of adding more
cameras on different kodiak devices. Third patch adopts the new define
for qcs6490-rb3gen2-vision-mezzanine.dtso.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Changes in v2:
- Add patch to make qcs6490-rb3gen2-vision-mezzanine.dtso use the common
define (Konrad)
- Pick up tags
- Link to v1: https://patch.msgid.link/20260612-kodiak-cam-mclk-v1-0-fd294ff003a2@fairphone.com
---
Luca Weiss (3):
arm64: dts: qcom: kodiak: Sort pinctrl subnodes by pins
arm64: dts: qcom: kodiak: Add camera mclk pinctrl definitions
arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Use common pinctrl
arch/arm64/boot/dts/qcom/kodiak.dtsi | 1413 ++++++++++----------
.../dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso | 13 +-
2 files changed, 727 insertions(+), 699 deletions(-)
---
base-commit: 19827e7930a5511c68e12aac6e4522f3661a1709
change-id: 20260612-kodiak-cam-mclk-a7e87d5b1585
Best regards,
--
Luca Weiss <luca.weiss@fairphone.com>
^ permalink raw reply
* Re: [PATCH 1/3] ASoC: dt-bindings: cirrus,cs42l43: Add CS42L44 variant
From: Rob Herring (Arm) @ 2026-07-17 13:18 UTC (permalink / raw)
To: Charles Keepax
Cc: linux-sound, krzk+dt, mfd, conor+dt, linux-kernel, lgirdwood,
broonie, devicetree, lee, patches
In-Reply-To: <20260708140039.1993489-2-ckeepax@opensource.cirrus.com>
On Wed, 08 Jul 2026 15:00:37 +0100, Charles Keepax wrote:
> The cs42l44 is a cost optimised variant of cs42l43b.
>
> Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
> ---
> Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 1/4] dt-bindings: display: panel: samsung,atna33xc20: Add ATNA40HQ08-0
From: Konrad Dybcio @ 2026-07-17 13:06 UTC (permalink / raw)
To: Doug Anderson, Rob Herring
Cc: Neil Armstrong, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
dri-devel, devicetree, linux-kernel, linux-arm-msm
In-Reply-To: <CAD=FV=XBn78eOC_zG0S2U-W3whrVYEpghKF_WgX+3zpUJ82-5g@mail.gmail.com>
On 6/6/26 12:41 AM, Doug Anderson wrote:
> Hi,
>
> On Fri, Jun 5, 2026 at 10:14 AM Rob Herring <robh@kernel.org> wrote:
[...]
>> Well yes, people have a hard time using compatible strings that don't
>> sound generic. That's too bad for them.
>
> OK, so sounds like going forward I should NAK changes to this file and
> tell people to just use:
>
> compatible = "samsung,atna33xc20";
>
> ...to mean "Generic Samsung AMOLED panel with power sequencing that
> matches atna33xc20"
>
> Yes, it means that if we find quirks with a specific panel later, it
> could possibly be harder to work around them. However, since we have
> several ways to identify the panel (via EDID and via DDC) this seems
> fairly low risk. You can't perfectly predict the future anyway.
Are we going forward with this guidance? I have another laptop with
another ATNAxxx panel (ATNA60HR07-0) that I intend to submit a DT for
soon
Konrad
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: iio: adc: Add Nuvoton MA35D1 EADC
From: Rob Herring @ 2026-07-17 13:06 UTC (permalink / raw)
To: Chi-Wen Weng
Cc: Jonathan Cameron, jic23, krzk+dt, conor+dt, dlechner, nuno.sa,
andy, linux-arm-kernel, linux-iio, devicetree, linux-kernel,
cwweng
In-Reply-To: <8d757505-ea93-4dd4-a374-79f143f6f949@gmail.com>
On Thu, Jul 16, 2026 at 7:59 PM Chi-Wen Weng <cwweng.linux@gmail.com> wrote:
>
> Hi Jonathan,
>
> Thank you for the review.
>
> > Not sure this doc helps. What are these interrupts for?
> > The driver only uses one of them so why are there 4?
> >
> > May well need interrupt-names to allow gaps in the list to
> > work but hard to tell without more information.
>
> The hardware has four EADC interrupt outputs, ADINT0 to ADINT3. The
> conversion-complete source for each interrupt can be selected through
> the EADC interrupt source registers.
>
> However, this initial driver only uses sample module 0 and routes its
> end-of-conversion event to ADINT0. So the binding does not need to
> describe the unused interrupt outputs at this stage.
>
> I will simplify this in v3 and document only one interrupt entry for
> ADINT0. If support for the other ADINT lines is added later, the binding
> can be extended with interrupt-names at that point.
No, document what the h/w has, not what a driver currently uses. The
only exception I can think of here would be if only 1 interrupt pin is
usable on a given system. Then it would be just 1 interrupt with
interrupt-names to define which one is used.
Rob
^ permalink raw reply
* Re: [PATCH v9 13/14] arm64: dts: qcom: glymur: Add iris video node
From: Konrad Dybcio @ 2026-07-17 12:54 UTC (permalink / raw)
To: Vishnu Reddy, Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Dmitry Baryshkov, Mauro Carvalho Chehab,
Joerg Roedel (AMD), Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Stanimir Varbanov,
Bjorn Andersson, Konrad Dybcio
Cc: linux-kernel, linux-media, linux-arm-msm, iommu, devicetree
In-Reply-To: <20260715-glymur-v9-13-8cf2cbe12a07@oss.qualcomm.com>
On 7/15/26 4:10 PM, Vishnu Reddy wrote:
> Add iris video codec to glymur SoC, which comes with significantly
> different powering up sequence than previous platforms, thus different
> clocks and resets.
>
> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> # X2E94100 Asus Zenbook A16
[...]
> + /*
> + * IRIS firmware is signed by vendors, only
> + * enable on boards where the proper signed firmware
> + * is available.
> + */
I still find this comment not-very-useful
Konrad
^ permalink raw reply
* Re: [PATCH v3 01/11] arm64: dts: lx2160a: explicitly enable serdes_1 node
From: Ioana Ciornei @ 2026-07-17 12:49 UTC (permalink / raw)
To: sashiko-reviews; +Cc: Frank.Li, imx, robh, conor+dt, devicetree
In-Reply-To: <20260717122225.2D5BB1F000E9@smtp.kernel.org>
On Fri, Jul 17, 2026 at 12:22:24PM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] Incomplete device tree update: the patch claims to explicitly enable the `serdes_1` node in "all board DT files" to prepare for an SoC default change, but misses several LX2160A and LX2162A board files.
> --
>
> --- Patch [1]: [PATCH v3 01/11] arm64: dts: lx2160a: explicitly enable serdes_1 node ---
> commit d3826fcfc7d054169418a33dbec45e352c709bff
> Author: Ioana Ciornei <ioana.ciornei@nxp.com>
>
> arm64: dts: lx2160a: explicitly enable serdes_1 node
>
> This commit enables the serdes_1 node in board-specific device tree files.
> This change prepares for a subsequent update that will set the default
> status of the serdes_1 node to disabled in the main SoC device tree.
>
> > Explicitly enable the serdes_1 node in all board DT files. This is
> > needed in order to be able to change the default status of the node to
> > "disabled" from the SoC DT file.
>
> [Severity: High]
> Does this commit miss updating several other lx2160a and lx2162a board
> files?
>
> If the default status in the SoC device tree file is changed to disabled,
> it appears boards that rely on serdes_1 for high-speed IO (PCIe,
> networking, SATA) might be left without functional interfaces.
>
> Could the following board files also need the serdes_1 node enabled:
> - arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts
> - arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
> - arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
> - arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi
>
> Is there a reason these files were omitted from this patch?
This is not a valid concern.
The above listed board files were not updated because they are not
active users of the serdes_1 node (no MAC node is currently referencing
it), thus enabling it is not necessary.
Ioana
^ permalink raw reply
* Re: [PATCH v4 2/2] iio: adc: add MAX40080 current-sense amplifier driver
From: sashiko-bot @ 2026-07-17 12:48 UTC (permalink / raw)
To: Stefan Popa; +Cc: robh, conor+dt, devicetree
In-Reply-To: <20260717123852.1140893-3-stefan.popa@analog.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Uninitialized stack variable `tmp` is read and assigned to `*iv` on the error path in `max40080_read_iv`.
- [Medium] Unprotected read of `st->range` in `max40080_read_raw` races with concurrent modifications.
--
--- Patch [2]: [PATCH v4 2/2] iio: adc: add MAX40080 current-sense amplifier driver ---
commit b542cce161e1d593b12f173fe74a0a6612fdcb77
Author: Stefan Popa <stefan.popa@analog.com>
iio: adc: add MAX40080 current-sense amplifier driver
This commit adds a new driver for the Analog Devices MAX40080 bidirectional
current-sense amplifier. It exposes current and voltage channels via IIO and
allows configuring oversampling and input ranges through I2C.
diff --git a/drivers/iio/adc/max40080.c b/drivers/iio/adc/max40080.c
new file mode 100644
--- /dev/null
+++ b/drivers/iio/adc/max40080.c
[ ... ]
> +static int max40080_read_iv(struct max40080_state *st, u32 *iv)
> +{
> + struct i2c_client *client = st->client;
> + int ret, io_ret;
> + u32 tmp;
[ ... ]
> + ret = read_poll_timeout(max40080_read_iv_once, io_ret,
> + io_ret || (tmp & MAX40080_IV_VALID_MSK),
> + 1 * USEC_PER_MSEC, 50 * USEC_PER_MSEC,
> + false, st, &tmp);
> + /*
> + * Update *iv even on timeout — the caller checks ret first, but the
> + * last-read value (with valid bit still clear) can be useful for debug.
> + */
> + *iv = tmp;
[Severity: Medium]
If max40080_read_iv_once() fails on the first attempt and returns a negative
error code (like -EIO), read_poll_timeout() will short-circuit without
evaluating the right side of the condition.
Will this leave tmp uninitialized, resulting in uninitialized stack memory
being copied to *iv before the error is returned?
[ ... ]
> +static int max40080_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int *val, int *val2, long mask)
> +{
> + struct max40080_state *st = iio_priv(indio_dev);
> + unsigned int range;
> + int ret;
> +
> + switch (mask) {
[ ... ]
> + case IIO_CHAN_INFO_SCALE:
> + /*
> + * The selectable current-sense range is exposed through
> + * scale: each RANGE setting has its own precomputed
> + * mA-per-code value. Userspace picks the range by writing
> + * the matching scale.
> + */
> + switch (chan->type) {
> + case IIO_CURRENT:
> + range = st->range;
[Severity: Medium]
Since max40080_set_range() updates st->range while holding st->lock,
could reading it here without taking the lock cause a data race if a user
concurrently reads and writes the scale sysfs attribute?
> + *val = st->current_scale[range][0];
> + *val2 = st->current_scale[range][1];
> + return IIO_VAL_INT_PLUS_NANO;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260717123852.1140893-1-stefan.popa@analog.com?part=2
^ permalink raw reply
* Re: [PATCH 1/4] regulator: dt-bindings: Add Silergy SYR82X allowed modes
From: Mark Brown @ 2026-07-17 12:44 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Victor Krawiec, lgirdwood, robh, krzk+dt, conor+dt, linux-kernel,
devicetree
In-Reply-To: <94ce2136-3adc-40f5-946f-b56778f6343c@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 616 bytes --]
On Fri, Jul 17, 2026 at 02:31:51PM +0200, Krzysztof Kozlowski wrote:
> On 17/07/2026 14:02, Victor Krawiec wrote:
> > The underlying implementation in the driver (in fan53555_device_mode_map_setup() it the patch serie) is limited to SYR82X because it is the only hardware that I'm able to test. That's why the binding part was referring to this specific device.
> So you are adding constants for one device but used in the bindings and
> driver for other? Are they valid there?
It's one of these devices that's got a bunch of clones from various
manufacturers with minor differences and share a driver.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH v4 08/11] Bluetooth: hci_qca: Support QCA2066 on M.2 connector via pwrseq
From: Bartosz Golaszewski @ 2026-07-17 12:41 UTC (permalink / raw)
To: Loic Poulain
Cc: Bartosz Golaszewski, linux-pci, linux-pm, linux-kernel,
linux-arm-msm, linux-bluetooth, devicetree, Manivannan Sadhasivam,
Manivannan Sadhasivam, Marcel Holtmann, Luiz Augusto von Dentz,
Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
In-Reply-To: <CAFEp6-0HnYOboVWc3GUG5qMN_phP4ryJp=T=LgZs2ujyX1isMg@mail.gmail.com>
On Fri, 17 Jul 2026 14:32:27 +0200, Loic Poulain
<loic.poulain@oss.qualcomm.com> said:
> Hi Bartosz,
>
> On Fri, Jul 17, 2026 at 11:35 AM Bartosz Golaszewski <brgl@kernel.org> wrote:
>>
>> On Thu, 16 Jul 2026 18:18:25 +0200, Loic Poulain
>> <loic.poulain@oss.qualcomm.com> said:
>> > For QCA2066 (and other QCA chips) on M.2 connectors, the UART enable is
>> > controlled by the W_DISABLE2# signal managed by the pcie-m2 power sequencer
>> > rather than a dedicated BT enable GPIO.
>> >
>> > When the serdev controller has an OF graph (indicating it is connected to
>> > an M.2 connector), acquire the 'uart' pwrseq target from the connector's
>> > power sequencer and use it to control BT power instead of the bt-enable
>> > GPIO. This is factored out into qca_serdev_get_m2_pwrseq().
>> >
>> > Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
>> > Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
>> > ---
>> > drivers/bluetooth/hci_qca.c | 41 +++++++++++++++++++++++++++++++----------
>> > 1 file changed, 31 insertions(+), 10 deletions(-)
>> >
>> > diff --git a/drivers/bluetooth/hci_qca.c b/drivers/bluetooth/hci_qca.c
>> > index 25c4387136245fca25e375951f960d7240116781..22f6185a946ef04c45e41b2b34126e3f58d603ca 100644
>> > --- a/drivers/bluetooth/hci_qca.c
>> > +++ b/drivers/bluetooth/hci_qca.c
>> > @@ -1872,6 +1872,9 @@ static int qca_power_on(struct hci_dev *hdev)
>> > /* Controller needs time to bootup. */
>> > msleep(150);
>> > }
>> > +
>> > + if (qcadev->bt_power.pwrseq)
>> > + pwrseq_power_on(qcadev->bt_power.pwrseq);
>> > }
>> >
>> > clear_bit(QCA_BT_OFF, &qca->flags);
>> > @@ -2387,6 +2390,28 @@ static int qca_init_regulators(struct qca_power *qca,
>> > return 0;
>> > }
>> >
>> > +static void qca_serdev_put_pwrseq(void *data)
>> > +{
>> > + pwrseq_put(data);
>> > +}
>> > +
>> > +static int qca_serdev_get_m2_pwrseq(struct qca_serdev *qcadev)
>> > +{
>> > + struct serdev_device *serdev = qcadev->serdev_hu.serdev;
>> > + struct pwrseq_desc *pwrseq;
>> > +
>> > + if (!of_graph_is_present(dev_of_node(&serdev->ctrl->dev)))
>> > + return 0;
>> > +
>> > + pwrseq = pwrseq_get(&serdev->ctrl->dev, "uart");
>>
>> There's devm_pwrseq_get() you can use instead of scheduling your own action.
>
> The reason is discussed here:
> https://lore.kernel.org/all/20260716083141.GA4101439@google.com/
>
> We want the lifetime of the pwrseq descriptor to be tied to the serdev
> consumer device rather than the underlying serdev controller.
> Maybe a short comment explaining this relationship would be helpful.
>
Ah, subtle. Yeah a comment would be helpful.
Bart
^ permalink raw reply
* [PATCH v4 1/2] dt-bindings: iio: adc: add maxim,max40080
From: Stefan Popa @ 2026-07-17 12:38 UTC (permalink / raw)
To: linux-iio; +Cc: jic23, andriy.shevchenko, nuno.sa, devicetree, Stefan Popa
In-Reply-To: <20260717123852.1140893-1-stefan.popa@analog.com>
Add device tree bindings for the Maxim MAX40080 bidirectional
current-sense amplifier with a 12-bit ADC and an I2C/SMBus interface.
Signed-off-by: Stefan Popa <stefan.popa@analog.com>
---
.../bindings/iio/adc/maxim,max40080.yaml | 64 +++++++++++++++++++
MAINTAINERS | 8 +++
2 files changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/maxim,max40080.yaml
diff --git a/Documentation/devicetree/bindings/iio/adc/maxim,max40080.yaml b/Documentation/devicetree/bindings/iio/adc/maxim,max40080.yaml
new file mode 100644
index 0000000000000..3b367071b5d3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/maxim,max40080.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/maxim,max40080.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX40080 bidirectional current-sense amplifier
+
+maintainers:
+ - Ciprian Hegbeli <ciprian.hegbeli@analog.com>
+ - Stefan Popa <stefan.popa@analog.com>
+
+description: |
+ The MAX40080 is a high-precision, bidirectional current-sense amplifier with
+ an integrated 12-bit ADC and an I2C/SMBus interface. It measures the voltage
+ across an external shunt resistor and the input bus voltage, and stores the
+ results in an internal FIFO.
+
+ Datasheet:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/MAX40080.pdf
+
+properties:
+ compatible:
+ const: maxim,max40080
+
+ reg:
+ maxItems: 1
+
+ vdd-supply:
+ description: Power supply for the device.
+
+ interrupts:
+ maxItems: 1
+ description: ALERT output for overcurrent/undervoltage threshold events.
+
+ "#io-channel-cells":
+ const: 1
+
+ shunt-resistor-micro-ohms:
+ description:
+ Value of the current-sense shunt resistor connected between the IN+ and
+ IN- inputs. Used to scale the reported current.
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@20 {
+ compatible = "maxim,max40080";
+ reg = <0x20>;
+ vdd-supply = <&vdd_3v3>;
+ #io-channel-cells = <1>;
+ shunt-resistor-micro-ohms = <100000>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index e087673237636..9aa1bc9a65ac5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15513,6 +15513,14 @@ L: linux-iio@vger.kernel.org
S: Supported
F: drivers/iio/temperature/max30208.c
+MAXIM MAX40080 CURRENT SENSE AMPLIFIER DRIVER
+M: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
+M: Stefan Popa <stefan.popa@analog.com>
+L: linux-iio@vger.kernel.org
+S: Supported
+W: https://ez.analog.com/linux-software-drivers
+F: Documentation/devicetree/bindings/iio/adc/maxim,max40080.yaml
+
MAXIM MAX7360 KEYPAD LED MFD DRIVER
M: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com>
S: Maintained
--
2.53.0
^ permalink raw reply related
* [PATCH v4 2/2] iio: adc: add MAX40080 current-sense amplifier driver
From: Stefan Popa @ 2026-07-17 12:38 UTC (permalink / raw)
To: linux-iio
Cc: jic23, andriy.shevchenko, nuno.sa, devicetree, Stefan Popa,
Ciprian Hegbeli
In-Reply-To: <20260717123852.1140893-1-stefan.popa@analog.com>
The MAX40080 is a bidirectional current-sense amplifier with an
integrated 12-bit ADC and an I2C/SMBus interface. It measures the
voltage across an external shunt resistor and the input bus voltage,
storing the results in an internal FIFO.
No existing IIO driver covers this device or a register-compatible part.
The closest relatives target different silicon with incompatible register
maps and feature sets: max9611 is a unidirectional high-side sensor with a
die-temperature channel and MUX-selected gain and no FIFO/PEC, while
max34408 is an 8-bit multi-channel current monitor. The MAX40080 has a
device-specific register map with bidirectional 13-bit current, a 64-entry
FIFO, PEC, a single-measurement mode triggered by an SMBus Quick Command,
and two selectable input ranges, so it warrants its own driver.
Add a direct-mode IIO driver exposing the current and voltage channels
with raw and scale attributes, a configurable oversampling (digital
averaging) ratio, and PEC-protected register access. The two selectable
current-sense ranges are exposed through scale/scale_available; the
current scale is derived from the shunt-resistor-micro-ohms device-tree
property.
Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/MAX40080.pdf
Co-developed-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
Signed-off-by: Ciprian Hegbeli <ciprian.hegbeli@analog.com>
Signed-off-by: Stefan Popa <stefan.popa@analog.com>
---
MAINTAINERS | 1 +
drivers/iio/adc/Kconfig | 11 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/max40080.c | 636 +++++++++++++++++++++++++++++++++++++
4 files changed, 649 insertions(+)
create mode 100644 drivers/iio/adc/max40080.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 9aa1bc9a65ac5..f50c1e00e12bb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15520,6 +15520,7 @@ L: linux-iio@vger.kernel.org
S: Supported
W: https://ez.analog.com/linux-software-drivers
F: Documentation/devicetree/bindings/iio/adc/maxim,max40080.yaml
+F: drivers/iio/adc/max40080.c
MAXIM MAX7360 KEYPAD LED MFD DRIVER
M: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com>
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 58da8255525e4..b651c57bbc3f5 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -1041,6 +1041,17 @@ config MAX34408
To compile this driver as a module, choose M here: the module will be
called max34408.
+config MAX40080
+ tristate "Analog Devices MAX40080 Current Sense Amplifier"
+ depends on I2C
+ help
+ Say yes here to build support for the Analog Devices MAX40080
+ bidirectional current-sense amplifier with a 12-bit ADC and an I2C
+ interface.
+
+ To compile this driver as a module, choose M here: the module will be
+ called max40080.
+
config MAX77541_ADC
tristate "Analog Devices MAX77541 ADC driver"
depends on MFD_MAX77541
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 7cc8f9a12f763..e1953353c68a4 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -91,6 +91,7 @@ obj-$(CONFIG_MAX1241) += max1241.o
obj-$(CONFIG_MAX1363) += max1363.o
obj-$(CONFIG_MAX14001) += max14001.o
obj-$(CONFIG_MAX34408) += max34408.o
+obj-$(CONFIG_MAX40080) += max40080.o
obj-$(CONFIG_MAX77541_ADC) += max77541-adc.o
obj-$(CONFIG_MAX9611) += max9611.o
obj-$(CONFIG_MCP320X) += mcp320x.o
diff --git a/drivers/iio/adc/max40080.c b/drivers/iio/adc/max40080.c
new file mode 100644
index 0000000000000..9ffb4e9a009c1
--- /dev/null
+++ b/drivers/iio/adc/max40080.c
@@ -0,0 +1,636 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * MAX40080 Digital Current-Sense Amplifier driver
+ *
+ * Copyright 2026 Analog Devices, Inc.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/cleanup.h>
+#include <linux/i2c.h>
+#include <linux/iopoll.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/pm.h>
+#include <linux/property.h>
+#include <linux/time.h>
+#include <linux/types.h>
+#include <linux/unaligned.h>
+#include <linux/units.h>
+
+#include <linux/iio/iio.h>
+
+#define MAX40080_REG_CFG 0x00
+#define MAX40080_CFG_MODE_MSK GENMASK(2, 0)
+#define MAX40080_CFG_PEC_EN_MSK BIT(5)
+#define MAX40080_CFG_RANGE_MSK BIT(6)
+#define MAX40080_CFG_FILTER_MSK GENMASK(14, 12)
+
+#define MAX40080_REG_FIFO_CFG 0x0A
+#define MAX40080_FIFO_CFG_STORE_IV_MSK GENMASK(1, 0)
+
+#define MAX40080_REG_IV 0x10
+/* Current is a 13-bit two's-complement value (magnitude + sign bit). */
+#define MAX40080_IV_I_MSK GENMASK(12, 0)
+#define MAX40080_IV_I_SIGN_BIT 12
+#define MAX40080_IV_V_MAG_MSK GENMASK(27, 16)
+#define MAX40080_IV_VALID_MSK BIT(31)
+
+/* CFG.mode field values. */
+#define MAX40080_CFG_MODE_STDBY 0x00
+#define MAX40080_CFG_MODE_SINGLE 0x02 /* One conversion per Quick Command. */
+
+/* CFG.range field values. */
+#define MAX40080_CFG_RANGE_50mV 0
+#define MAX40080_CFG_RANGE_10mV 1
+
+/* FIFO_CFG.store_iv field values. */
+#define MAX40080_FIFO_CFG_STORE_I_V 0x02
+
+#define MAX40080_ADC_RES 4096
+#define MAX40080_INTER_VREF_mV 1250
+#define MAX40080_V_BUFF_GAIN 30
+#define MAX40080_CSA_50mV_GAIN 25
+#define MAX40080_CSA_10mV_GAIN 125
+
+/*
+ * The RANGE field (CFG bit 6) selects one of two current-sense full-scale
+ * ranges: +/-50 mV (gain 25 V/V) or +/-10 mV (gain 125 V/V).
+ */
+static const int max40080_csa_gain[] = {
+ [MAX40080_CFG_RANGE_50mV] = MAX40080_CSA_50mV_GAIN,
+ [MAX40080_CFG_RANGE_10mV] = MAX40080_CSA_10mV_GAIN,
+};
+
+struct max40080_state {
+ struct i2c_client *client;
+ /* Serializes read-modify-write access to the CFG register. */
+ struct mutex lock;
+ u32 shunt_resistor_uOhm;
+ /*
+ * Cached configuration, also used to restore the device on resume after
+ * a suspend that may have cut its power: the selected RANGE index and
+ * the oversampling ratio.
+ */
+ unsigned int range;
+ int oversampling_ratio;
+ /*
+ * Precomputed current scale (mA per code) for each RANGE setting, as
+ * {integer, nano} pairs for IIO_VAL_INT_PLUS_NANO. The range is
+ * selected by writing the corresponding scale.
+ */
+ int current_scale[ARRAY_SIZE(max40080_csa_gain)][2];
+ /* DMA-safe buffer for i2c_smbus_read_i2c_block_data(). */
+ u8 buf[4] ____cacheline_aligned;
+};
+
+static const int max40080_oversampling_avail[] = { 1, 8, 16, 32, 64, 128 };
+
+static int __max40080_update_bits(struct max40080_state *st, u8 reg,
+ u16 mask, u16 val)
+{
+ int tmp;
+
+ tmp = i2c_smbus_read_word_data(st->client, reg);
+ if (tmp < 0)
+ return tmp;
+
+ tmp = (tmp & ~mask) | (val & mask);
+
+ return i2c_smbus_write_word_data(st->client, reg, tmp);
+}
+
+/*
+ * A single measurement holds the matched current/voltage pair in one 32-bit
+ * word (MAX40080_REG_IV). Reading all four bytes in one transaction returns
+ * both from the same conversion; reading the separate current (0x0C) and
+ * voltage (0x0E) registers would decorrelate the two channels.
+ *
+ * Unlike the word accesses used elsewhere, this is a plain I2C block read: the
+ * SMBus layer does not append or verify a PEC byte for it even when PEC is
+ * otherwise enabled for the device, so this transfer is not PEC protected.
+ */
+static int max40080_read_iv_once(struct max40080_state *st, u32 *iv)
+{
+ int ret;
+
+ ret = i2c_smbus_read_i2c_block_data(st->client, MAX40080_REG_IV,
+ sizeof(st->buf), st->buf);
+ if (ret < 0)
+ return ret;
+ if (ret != sizeof(st->buf))
+ return -EIO;
+
+ *iv = get_unaligned_le32(st->buf);
+
+ return 0;
+}
+
+static int max40080_read_iv(struct max40080_state *st, u32 *iv)
+{
+ struct i2c_client *client = st->client;
+ int ret, io_ret;
+ u32 tmp;
+
+ guard(mutex)(&st->lock);
+
+ /*
+ * In single-measurement mode the device sits idle until it receives an
+ * SMBus Quick Command, then performs exactly one current and one voltage
+ * conversion and returns to idle. Triggering on demand this way (rather
+ * than running the FIFO continuously in active mode) means each read
+ * returns a fresh, coherent current/voltage pair instead of the oldest
+ * queued FIFO entry.
+ */
+ ret = i2c_smbus_xfer(client->adapter, client->addr, client->flags,
+ I2C_SMBUS_WRITE, 0, I2C_SMBUS_QUICK, NULL);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * Wait for the conversion to complete by polling the FIFO valid bit
+ * (or bail out on an I2C error). Polling the device's own status makes
+ * this independent of the actual conversion time, which varies with the
+ * oversampling ratio and the bus speed. The timeout is only a safety
+ * ceiling: the worst case is the maximum 128x averaging on both the
+ * current and voltage channels at the slowest 15 ksps base rate plus the
+ * inter-channel switching time, i.e. roughly 20 ms; 50 ms leaves ample
+ * margin.
+ */
+ ret = read_poll_timeout(max40080_read_iv_once, io_ret,
+ io_ret || (tmp & MAX40080_IV_VALID_MSK),
+ 1 * USEC_PER_MSEC, 50 * USEC_PER_MSEC,
+ false, st, &tmp);
+ /*
+ * Update *iv even on timeout — the caller checks ret first, but the
+ * last-read value (with valid bit still clear) can be useful for debug.
+ */
+ *iv = tmp;
+ if (ret)
+ return ret;
+
+ return io_ret;
+}
+
+static int max40080_get_current(struct max40080_state *st, int *val)
+{
+ u32 iv;
+ int ret;
+
+ ret = max40080_read_iv(st, &iv);
+ if (ret)
+ return ret;
+
+ *val = sign_extend32(FIELD_GET(MAX40080_IV_I_MSK, iv),
+ MAX40080_IV_I_SIGN_BIT);
+
+ return 0;
+}
+
+static int max40080_get_voltage(struct max40080_state *st, int *val)
+{
+ u32 iv;
+ int ret;
+
+ ret = max40080_read_iv(st, &iv);
+ if (ret)
+ return ret;
+
+ *val = FIELD_GET(MAX40080_IV_V_MAG_MSK, iv);
+
+ return 0;
+}
+
+static int max40080_set_range(struct max40080_state *st, unsigned int range)
+{
+ int ret;
+
+ guard(mutex)(&st->lock);
+
+ ret = __max40080_update_bits(st, MAX40080_REG_CFG, MAX40080_CFG_RANGE_MSK,
+ FIELD_PREP(MAX40080_CFG_RANGE_MSK, range));
+ if (ret)
+ return ret;
+
+ st->range = range;
+
+ return 0;
+}
+
+/*
+ * Precompute the current scale (mA per code) for each RANGE setting as
+ * {integer, nano} pairs. The shunt drop for a full-scale code is
+ * Vref[mV] / (ADC_RES * gain)
+ * and current = Vshunt / Rshunt, so with Rshunt in micro-ohms the scale in
+ * mA/code is
+ * Vref[mV] * NANO * MICRO / (ADC_RES * gain * Rshunt[uOhm])
+ * expressed as an integer part plus a nano fractional part.
+ */
+static void max40080_calc_current_scale(struct max40080_state *st)
+{
+ for (unsigned int i = 0; i < ARRAY_SIZE(max40080_csa_gain); i++) {
+ u64 numerator = 1ULL * MAX40080_INTER_VREF_mV * NANO * MICRO;
+ u64 denominator = 1ULL * MAX40080_ADC_RES * max40080_csa_gain[i] *
+ st->shunt_resistor_uOhm;
+ u64 tmp;
+ u32 rem;
+
+ tmp = div64_u64(numerator, denominator);
+ st->current_scale[i][0] = div_u64_rem(tmp, NANO, &rem);
+ st->current_scale[i][1] = rem;
+ }
+}
+
+/*
+ * The FILTER field selects digital averaging of N consecutive conversions
+ * (no averaging, 8, 16, 32, 64 or 128), which maps directly to the IIO
+ * oversampling ratio. Averaging reduces the effective output data rate by the
+ * same factor; the conversion rate itself is set by the separate ADC_RATE
+ * field.
+ */
+static int max40080_get_oversampling_ratio(struct max40080_state *st, int *val)
+{
+ u8 filter;
+ int tmp;
+
+ tmp = i2c_smbus_read_word_data(st->client, MAX40080_REG_CFG);
+ if (tmp < 0)
+ return tmp;
+
+ filter = FIELD_GET(MAX40080_CFG_FILTER_MSK, tmp);
+ if (filter >= ARRAY_SIZE(max40080_oversampling_avail))
+ return -EIO;
+
+ *val = max40080_oversampling_avail[filter];
+
+ return 0;
+}
+
+/*
+ * max40080_oversampling_avail[] is ordered so that its index is the FILTER
+ * field value (index 0 = no averaging, index 1 = 8x, ...). Return that index
+ * for an exact match, or -EINVAL for a value that is not on the list.
+ */
+static int max40080_oversampling_to_filter(int val)
+{
+ for (unsigned int i = 0; i < ARRAY_SIZE(max40080_oversampling_avail); i++) {
+ if (max40080_oversampling_avail[i] == val)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+static int max40080_set_oversampling_ratio(struct max40080_state *st, int val)
+{
+ int filter;
+ int ret;
+
+ filter = max40080_oversampling_to_filter(val);
+ if (filter < 0)
+ return filter;
+
+ guard(mutex)(&st->lock);
+
+ ret = __max40080_update_bits(st, MAX40080_REG_CFG, MAX40080_CFG_FILTER_MSK,
+ FIELD_PREP(MAX40080_CFG_FILTER_MSK, filter));
+ if (ret)
+ return ret;
+
+ st->oversampling_ratio = val;
+
+ return 0;
+}
+
+static int max40080_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2, long mask)
+{
+ struct max40080_state *st = iio_priv(indio_dev);
+ unsigned int range;
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ switch (chan->type) {
+ case IIO_CURRENT:
+ ret = max40080_get_current(st, val);
+ if (ret)
+ return ret;
+ return IIO_VAL_INT;
+ case IIO_VOLTAGE:
+ ret = max40080_get_voltage(st, val);
+ if (ret)
+ return ret;
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
+ case IIO_CHAN_INFO_SCALE:
+ /*
+ * The selectable current-sense range is exposed through
+ * scale: each RANGE setting has its own precomputed
+ * mA-per-code value. Userspace picks the range by writing
+ * the matching scale.
+ */
+ switch (chan->type) {
+ case IIO_CURRENT:
+ range = st->range;
+ *val = st->current_scale[range][0];
+ *val2 = st->current_scale[range][1];
+ return IIO_VAL_INT_PLUS_NANO;
+ case IIO_VOLTAGE:
+ /* voltage[mV] = raw * Vref[mV] * buffer_gain / ADC_RES */
+ *val = MAX40080_INTER_VREF_mV * MAX40080_V_BUFF_GAIN;
+ *val2 = MAX40080_ADC_RES;
+ return IIO_VAL_FRACTIONAL;
+ default:
+ return -EINVAL;
+ }
+ case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
+ ret = max40080_get_oversampling_ratio(st, val);
+ if (ret)
+ return ret;
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int max40080_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val, int val2, long mask)
+{
+ struct max40080_state *st = iio_priv(indio_dev);
+
+ switch (mask) {
+ case IIO_CHAN_INFO_SCALE:
+ /* Only the current channel has a selectable range/scale. */
+ if (chan->type != IIO_CURRENT)
+ return -EINVAL;
+
+ for (unsigned int i = 0; i < ARRAY_SIZE(max40080_csa_gain); i++) {
+ if (val == st->current_scale[i][0] &&
+ val2 == st->current_scale[i][1])
+ return max40080_set_range(st, i);
+ }
+
+ return -EINVAL;
+ case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
+ return max40080_set_oversampling_ratio(st, val);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int max40080_write_raw_get_fmt(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ long mask)
+{
+ switch (mask) {
+ case IIO_CHAN_INFO_SCALE:
+ return IIO_VAL_INT_PLUS_NANO;
+ default:
+ return IIO_VAL_INT;
+ }
+}
+
+static int max40080_read_avail(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ const int **vals, int *type, int *length,
+ long info)
+{
+ struct max40080_state *st = iio_priv(indio_dev);
+
+ switch (info) {
+ case IIO_CHAN_INFO_SCALE:
+ if (chan->type != IIO_CURRENT)
+ return -EINVAL;
+
+ *vals = (const int *)st->current_scale;
+ *length = ARRAY_SIZE(max40080_csa_gain) * 2;
+ *type = IIO_VAL_INT_PLUS_NANO;
+
+ return IIO_AVAIL_LIST;
+ case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
+ *vals = max40080_oversampling_avail;
+ *length = ARRAY_SIZE(max40080_oversampling_avail);
+ *type = IIO_VAL_INT;
+
+ return IIO_AVAIL_LIST;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int max40080_reg_access(struct iio_dev *indio_dev,
+ unsigned int reg,
+ unsigned int write_val,
+ unsigned int *read_val)
+{
+ struct max40080_state *st = iio_priv(indio_dev);
+ int val;
+
+ if (!read_val)
+ return i2c_smbus_write_word_data(st->client, reg, write_val);
+
+ val = i2c_smbus_read_word_data(st->client, reg);
+ if (val < 0)
+ return val;
+
+ *read_val = val;
+
+ return 0;
+}
+
+static const struct iio_info max40080_info = {
+ .read_raw = max40080_read_raw,
+ .write_raw = max40080_write_raw,
+ .write_raw_get_fmt = max40080_write_raw_get_fmt,
+ .read_avail = max40080_read_avail,
+ .debugfs_reg_access = &max40080_reg_access,
+};
+
+static const struct iio_chan_spec max40080_channels[] = {
+ {
+ .type = IIO_CURRENT,
+ .indexed = 1,
+ .channel = 0,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_SCALE),
+ .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE),
+ .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
+ .info_mask_shared_by_all_available =
+ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
+ },
+ {
+ .type = IIO_VOLTAGE,
+ .indexed = 1,
+ .channel = 0,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_SCALE),
+ .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
+ .info_mask_shared_by_all_available =
+ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
+ },
+};
+
+/*
+ * Configure (or, after a suspend that cut power, restore) the device from the
+ * cached state. The device powers up in standby with PEC enabled (CFG POR =
+ * 0x0060), so PEC is kept enabled throughout.
+ */
+static int max40080_init(struct max40080_state *st)
+{
+ u16 fifo_cfg, cfg;
+ int filter;
+ int ret;
+
+ filter = max40080_oversampling_to_filter(st->oversampling_ratio);
+ if (filter < 0)
+ return filter;
+
+ /*
+ * Put the device in standby before (re)configuring the FIFO: the FIFO
+ * configuration register can only be written while the device is not
+ * converting.
+ */
+ cfg = FIELD_PREP(MAX40080_CFG_MODE_MSK, MAX40080_CFG_MODE_STDBY) |
+ FIELD_PREP(MAX40080_CFG_PEC_EN_MSK, 1);
+ ret = i2c_smbus_write_word_data(st->client, MAX40080_REG_CFG, cfg);
+ if (ret)
+ return ret;
+
+ /* Store a matched current+voltage pair per conversion. */
+ fifo_cfg = FIELD_PREP(MAX40080_FIFO_CFG_STORE_IV_MSK, MAX40080_FIFO_CFG_STORE_I_V);
+ ret = i2c_smbus_write_word_data(st->client, MAX40080_REG_FIFO_CFG, fifo_cfg);
+ if (ret)
+ return ret;
+
+ /*
+ * Use single-measurement mode: the device stays idle and converts once
+ * per SMBus Quick Command (see max40080_trigger_measurement()), so each
+ * read returns a fresh sample rather than a queued FIFO entry.
+ */
+ cfg = FIELD_PREP(MAX40080_CFG_MODE_MSK, MAX40080_CFG_MODE_SINGLE) |
+ FIELD_PREP(MAX40080_CFG_PEC_EN_MSK, 1) |
+ FIELD_PREP(MAX40080_CFG_RANGE_MSK, st->range) |
+ FIELD_PREP(MAX40080_CFG_FILTER_MSK, filter);
+
+ return i2c_smbus_write_word_data(st->client, MAX40080_REG_CFG, cfg);
+}
+
+static int max40080_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ struct max40080_state *st;
+ struct iio_dev *indio_dev;
+ int ret;
+
+ /*
+ * The device powers up with PEC enabled (CFG POR = 0x0060) and rejects
+ * unprotected transactions, so PEC support is mandatory, along with word
+ * access, the I2C block read used for the current/voltage pair, and the
+ * Quick Command used to trigger a conversion.
+ */
+ if (!i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_WORD_DATA |
+ I2C_FUNC_SMBUS_I2C_BLOCK |
+ I2C_FUNC_SMBUS_QUICK |
+ I2C_FUNC_SMBUS_PEC))
+ return -EOPNOTSUPP;
+
+ client->flags |= I2C_CLIENT_PEC;
+
+ indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ i2c_set_clientdata(client, indio_dev);
+
+ st = iio_priv(indio_dev);
+ st->client = client;
+
+ ret = devm_mutex_init(dev, &st->lock);
+ if (ret)
+ return ret;
+
+ {
+ const char *propname = "shunt-resistor-micro-ohms";
+
+ if (device_property_present(dev, propname)) {
+ ret = device_property_read_u32(dev, propname,
+ &st->shunt_resistor_uOhm);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "can't read %s\n", propname);
+ if (!st->shunt_resistor_uOhm)
+ return dev_err_probe(dev, -EINVAL,
+ "%s must be non-zero\n", propname);
+ } else {
+ st->shunt_resistor_uOhm = 1 * MICRO;
+ }
+ }
+
+ max40080_calc_current_scale(st);
+
+ /* Defaults: 50 mV range (index 0), no averaging. */
+ st->range = 0;
+ st->oversampling_ratio = 1;
+
+ indio_dev->name = "max40080";
+ indio_dev->info = &max40080_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->channels = max40080_channels;
+ indio_dev->num_channels = ARRAY_SIZE(max40080_channels);
+
+ ret = max40080_init(st);
+ if (ret)
+ return ret;
+
+ return devm_iio_device_register(dev, indio_dev);
+}
+
+static int max40080_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct max40080_state *st = iio_priv(indio_dev);
+
+ /*
+ * A suspend may have cut power to the device, resetting it to its
+ * power-on defaults. Reprogram it from the cached configuration.
+ */
+ return max40080_init(st);
+}
+
+static DEFINE_SIMPLE_DEV_PM_OPS(max40080_pm_ops, NULL, max40080_resume);
+
+static const struct i2c_device_id max40080_i2c_ids[] = {
+ { .name = "max40080" },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, max40080_i2c_ids);
+
+static const struct of_device_id max40080_of_match[] = {
+ { .compatible = "maxim,max40080" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, max40080_of_match);
+
+static struct i2c_driver max40080_driver = {
+ .driver = {
+ .name = "max40080",
+ .of_match_table = max40080_of_match,
+ .pm = pm_sleep_ptr(&max40080_pm_ops),
+ },
+ .probe = max40080_probe,
+ .id_table = max40080_i2c_ids,
+};
+module_i2c_driver(max40080_driver);
+
+MODULE_AUTHOR("Ciprian Hegbeli <ciprian.hegbeli@analog.com>");
+MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
+MODULE_DESCRIPTION("Analog Devices MAX40080 current-sense amplifier driver");
+MODULE_LICENSE("GPL");
--
2.53.0
^ permalink raw reply related
* [PATCH v4 0/2] iio: adc: add MAX40080 current-sense amplifier driver
From: Stefan Popa @ 2026-07-17 12:38 UTC (permalink / raw)
To: linux-iio; +Cc: jic23, andriy.shevchenko, nuno.sa, devicetree, Stefan Popa
This series adds support for the Maxim MAX40080, a bidirectional
current-sense amplifier with an integrated 12-bit ADC and an I2C/SMBus
interface. It measures the voltage across an external shunt resistor and
the input bus voltage.
The driver operates in direct (INDIO_DIRECT_MODE) mode. Each raw read
triggers a single on-demand conversion (SMBus Quick Command) and reads
back the matched current/voltage pair, so results are always fresh. It
exposes the current and voltage channels with raw and scale attributes,
a configurable oversampling (digital averaging) ratio, and PEC-protected
register access. The two selectable current-sense ranges are exposed
through scale/scale_available; the current scale is derived from the
shunt-resistor-micro-ohms device-tree property.
Tested on hardware with four MAX40080 devices on an I2C bus.
Regarding regmap: it does not support SMBus PEC or Quick Command, both of
which are required by this device. The mlx90614 driver uses the same raw
i2c_smbus approach for similar reasons.
Changes in v4:
- Split MAINTAINERS between patches: binding file in patch 1, driver
file in patch 2 (Andy, Nuno, checkpatch)
- Use Datasheet: tag instead of Link: for datasheet URL (Andy)
- Remove blank line before Co-developed-by tag (Andy)
- Consistent comment style: capital first letter + period (Andy)
- Rename shunt_resistor_uohm to shunt_resistor_uOhm for SI convention (Andy)
- Inline trigger_measurement() into read_iv(), removing the helper (Nuno)
- Add DMA-safe buffer to struct with ____cacheline_aligned (Nuno)
- Rework read_iv: use local tmp variable, add comment explaining why
*iv is updated even on timeout (Andy)
- Refactor calc_current_scale: C99 loop variable, named numerator/denominator
variables with 1ULL * promotion trick (Andy)
- Use unsigned int for loop variable in oversampling_to_filter (Andy)
- Add propname variable to deduplicate "shunt-resistor-micro-ohms" string (Andy)
- Fix locking: rename to __max40080_update_bits (unlocked helper), hold
lock through cache update in set_range/set_oversampling_ratio (Nuno, Sashiko)
- Fix torn-read in read_raw: use local copy of st->range (Nuno)
- Return inline instead of breaks in read_raw switch cases (Nuno)
- Remove lock from resume function (Nuno)
Changes in v3:
- Remove mod_devicetable.h include (Andy, Uwe's rework)
- Use lowercase _mV suffix for unit defines: MAX40080_INTER_VREF_mV,
MAX40080_CSA_50mV_GAIN, MAX40080_CSA_10mV_GAIN (Andy)
- Remove MAX40080_NUM_RANGES macro, use ARRAY_SIZE() directly (Andy)
- Fix reversed xmas tree ordering in get_oversampling_ratio() (Andy)
- Split semantically different variable declarations in
set_oversampling_ratio() and max40080_init() (Andy)
- Join *val, *val2, long mask on same line in read_raw signature (Andy)
- Use const int * cast in read_avail (Andy)
- Join FIFO_CFG write onto single line in max40080_init() (Andy)
- Return i2c_smbus_write_word_data() directly at end of
max40080_init() (Andy)
- Use device_property_present() pattern for optional shunt-resistor
property (Andy)
- Make vdd-supply required in DT bindings (Conor)
- Restore i2c_set_clientdata() needed for PM resume (Sashiko)
- Add bounds check in get_oversampling_ratio() for hardware register
values outside expected range (Sashiko)
Changes in v2:
- Add vdd-supply and interrupts properties to the binding (David)
- Add types.h and time.h includes (Andy)
- Use USEC_PER_MSEC for poll timeout readability (Andy)
- Use 1 * MICRO for default shunt resistor (Andy)
- Rename field macros to include register name, e.g. MAX40080_CFG_MODE_MSK
(Jonathan, David)
- Add indexed defines for RANGE field values and use in gain array
(Jonathan)
- Use array lookup in get_oversampling_ratio instead of formula (Andy)
- Use switch statement for chan->type in read_raw (David)
- Simplify update_bits: one-liner RMW, return write directly (Andy)
- Add local client variable in trigger_measurement (Andy)
- Add braces to for loops and use C99 loop variables (Siratul, Andy)
- Flip if/else in reg_access, separate declaration from assignment (Andy)
- Add .name= in i2c_device_id (David, Siratul)
- Reorder declarations to reverse christmas tree (Siratul)
- Return directly from oversampling case in write_raw (Andy)
- Add blank lines before return in read_avail (Siratul)
- Add Co-developed-by tag for Ciprian (Andy)
- Use Link: tag for datasheet URL in commit message
Stefan Popa (2):
dt-bindings: iio: adc: add maxim,max40080
iio: adc: add MAX40080 current-sense amplifier driver
.../bindings/iio/adc/maxim,max40080.yaml | 64 ++
MAINTAINERS | 9 +
drivers/iio/adc/Kconfig | 11 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/max40080.c | 636 ++++++++++++++++++
5 files changed, 721 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/maxim,max40080.yaml
create mode 100644 drivers/iio/adc/max40080.c
--
2.53.0
^ permalink raw reply
* Re: (subset) [PATCH v7 0/2] dmaengine: arm-dma350: handle shared channel IRQ wiring on sky1
From: Vinod Koul @ 2026-07-17 12:35 UTC (permalink / raw)
To: peter.chen, fugang.duan, robh, krzk+dt, conor+dt, ychuang3,
schung, robin.murphy, Frank.Li, Jun Guo
Cc: dmaengine, devicetree, linux-kernel, cix-kernel-upstream,
linux-arm-kernel
In-Reply-To: <20260521072924.3000282-1-jun.guo@cixtech.com>
On Thu, 21 May 2026 15:29:22 +0800, Jun Guo wrote:
> This series updates DMA-350 support for the SKY1 integration where all
> DMA
> channel interrupt outputs are wired to the same GIC SPI.
>
> Patch 1 enables DMANSECCTRL.INTREN_ANYCHINTR in the driver so
> per-channel
> interrupt status is propagated even when channels share one parent IRQ
> line.
>
> [...]
Applied, thanks!
[1/2] dmaengine: arm-dma350: enable ANYCH interrupt for shared IRQ wiring
commit: 643c1e1ae3eb3cd9be31e83c2240e41849a6cb56
Best regards,
--
~Vinod
^ permalink raw reply
* Re: [PATCH v4 08/11] Bluetooth: hci_qca: Support QCA2066 on M.2 connector via pwrseq
From: Loic Poulain @ 2026-07-17 12:32 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: linux-pci, linux-pm, linux-kernel, linux-arm-msm, linux-bluetooth,
devicetree, Manivannan Sadhasivam, Manivannan Sadhasivam,
Marcel Holtmann, Luiz Augusto von Dentz, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <CAMRc=Mc3gt_uruVmUmqsOsvKX=52V4TBVC0hbo69KgjEGhch3A@mail.gmail.com>
Hi Bartosz,
On Fri, Jul 17, 2026 at 11:35 AM Bartosz Golaszewski <brgl@kernel.org> wrote:
>
> On Thu, 16 Jul 2026 18:18:25 +0200, Loic Poulain
> <loic.poulain@oss.qualcomm.com> said:
> > For QCA2066 (and other QCA chips) on M.2 connectors, the UART enable is
> > controlled by the W_DISABLE2# signal managed by the pcie-m2 power sequencer
> > rather than a dedicated BT enable GPIO.
> >
> > When the serdev controller has an OF graph (indicating it is connected to
> > an M.2 connector), acquire the 'uart' pwrseq target from the connector's
> > power sequencer and use it to control BT power instead of the bt-enable
> > GPIO. This is factored out into qca_serdev_get_m2_pwrseq().
> >
> > Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> > Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> > ---
> > drivers/bluetooth/hci_qca.c | 41 +++++++++++++++++++++++++++++++----------
> > 1 file changed, 31 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/bluetooth/hci_qca.c b/drivers/bluetooth/hci_qca.c
> > index 25c4387136245fca25e375951f960d7240116781..22f6185a946ef04c45e41b2b34126e3f58d603ca 100644
> > --- a/drivers/bluetooth/hci_qca.c
> > +++ b/drivers/bluetooth/hci_qca.c
> > @@ -1872,6 +1872,9 @@ static int qca_power_on(struct hci_dev *hdev)
> > /* Controller needs time to bootup. */
> > msleep(150);
> > }
> > +
> > + if (qcadev->bt_power.pwrseq)
> > + pwrseq_power_on(qcadev->bt_power.pwrseq);
> > }
> >
> > clear_bit(QCA_BT_OFF, &qca->flags);
> > @@ -2387,6 +2390,28 @@ static int qca_init_regulators(struct qca_power *qca,
> > return 0;
> > }
> >
> > +static void qca_serdev_put_pwrseq(void *data)
> > +{
> > + pwrseq_put(data);
> > +}
> > +
> > +static int qca_serdev_get_m2_pwrseq(struct qca_serdev *qcadev)
> > +{
> > + struct serdev_device *serdev = qcadev->serdev_hu.serdev;
> > + struct pwrseq_desc *pwrseq;
> > +
> > + if (!of_graph_is_present(dev_of_node(&serdev->ctrl->dev)))
> > + return 0;
> > +
> > + pwrseq = pwrseq_get(&serdev->ctrl->dev, "uart");
>
> There's devm_pwrseq_get() you can use instead of scheduling your own action.
The reason is discussed here:
https://lore.kernel.org/all/20260716083141.GA4101439@google.com/
We want the lifetime of the pwrseq descriptor to be tied to the serdev
consumer device rather than the underlying serdev controller.
Maybe a short comment explaining this relationship would be helpful.
Regards,
Loic
>
> > + if (IS_ERR(pwrseq))
> > + return PTR_ERR(pwrseq);
> > +
> > + qcadev->bt_power.pwrseq = pwrseq;
> > +
> > + return devm_add_action_or_reset(&serdev->dev, qca_serdev_put_pwrseq, pwrseq);
> > +}
> > +
> > static int qca_serdev_probe(struct serdev_device *serdev)
> > {
> > struct qca_serdev *qcadev;
> > @@ -2417,6 +2442,10 @@ static int qca_serdev_probe(struct serdev_device *serdev)
> > else
> > qcadev->btsoc_type = QCA_ROME;
> >
> > + err = qca_serdev_get_m2_pwrseq(qcadev);
> > + if (err)
> > + return err;
> > +
> > switch (qcadev->btsoc_type) {
> > case QCA_WCN3950:
> > case QCA_WCN3988:
> > @@ -2426,17 +2455,9 @@ static int qca_serdev_probe(struct serdev_device *serdev)
> > case QCA_WCN6750:
> > case QCA_WCN6855:
> > case QCA_WCN7850:
> > - /*
> > - * OF graph link is only present for BT devices attached through
> > - * the M.2 Key E connector.
> > - */
> > - if (of_graph_is_present(dev_of_node(&serdev->ctrl->dev))) {
> > - qcadev->bt_power.pwrseq = devm_pwrseq_get(&serdev->ctrl->dev,
> > - "uart");
> > - if (IS_ERR(qcadev->bt_power.pwrseq))
> > - return PTR_ERR(qcadev->bt_power.pwrseq);
> > + /* M.2 connector modules are powered by the pwrseq acquired above. */
> > + if (qcadev->bt_power.pwrseq)
> > break;
> > - }
> >
> > if (!device_property_present(&serdev->dev, "enable-gpios")) {
> > /*
> >
> > --
> > 2.34.1
> >
> >
>
> Bart
^ permalink raw reply
* Re: [PATCH 1/4] regulator: dt-bindings: Add Silergy SYR82X allowed modes
From: Krzysztof Kozlowski @ 2026-07-17 12:31 UTC (permalink / raw)
To: Victor Krawiec
Cc: lgirdwood, broonie, robh, krzk+dt, conor+dt, linux-kernel,
devicetree
In-Reply-To: <fd7d5b72-a400-435c-bbac-9e661d98e3c9@arturia.com>
On 17/07/2026 14:02, Victor Krawiec wrote:
> On 7/17/26 11:08, Krzysztof Kozlowski wrote:
>
>> On Wed, Jul 15, 2026 at 05:51:38PM +0200, Victor Krawiec wrote:
>>> Make the PWM mode configurable from devicetree. Some boards require forced
>>> PWM mode to keep the supply ripple within acceptable limits under light
>>> load conditions
>>>
>>> Indexes are starting from 1 to keep backward compatibility with existing
>>> device trees
>>>
>>> Signed-off-by: Victor Krawiec <victor.krawiec@arturia.com>
>>> ---
>>> .../dt-bindings/regulator/silergy,syr82x.h | 20 +++++++++++++++++++
>>> 1 file changed, 20 insertions(+)
>>> create mode 100644 include/dt-bindings/regulator/silergy,syr82x.h
>>>
>> This header should be mentioned in the binding in property description.
> Thank you for the review. I'll add it to the binding in the next iteration.
>>> diff --git a/include/dt-bindings/regulator/silergy,syr82x.h b/include/dt-bindings/regulator/silergy,syr82x.h
>>> new file mode 100644
>>> index 000000000000..6d4aa86bb5c1
>>> --- /dev/null
>>> +++ b/include/dt-bindings/regulator/silergy,syr82x.h
>> Some confusing name. How is your binding file called? This must be the
>> same.
>
> The binding file is named fcs,fan53555.yaml and handles several devices including the Silergy SYR82X which I was targeting in this patch serie. I will rename the header to have the same name as the binding file. Should I also rename the macros defined inside the header (SYR82X_REGULATOR_MODE_*) ?
>
> The underlying implementation in the driver (in fan53555_device_mode_map_setup() it the patch serie) is limited to SYR82X because it is the only hardware that I'm able to test. That's why the binding part was referring to this specific device.
>
So you are adding constants for one device but used in the bindings and
driver for other? Are they valid there?
The fcs,fan53555.yaml does not say that any modes are particularly valid.
Please wrap your replies.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v1 4/4] ARM: dts: imx7-colibri: Set LCDIF format
From: sashiko-bot @ 2026-07-17 12:30 UTC (permalink / raw)
To: Francesco Dolcini; +Cc: imx, robh, dri-devel, Frank.Li, conor+dt, devicetree
In-Reply-To: <20260717121847.488148-5-francesco@dolcini.it>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message body incorrectly refers to `colibri imx6ull` instead of `colibri imx7`.
--
--- Patch [4]: [PATCH v1 4/4] ARM: dts: imx7-colibri: Set LCDIF format ---
commit 9c45712860f8ad12db4bc3a18c8c4e7039c7f51b
Author: Francesco Dolcini <francesco.dolcini@toradex.com>
ARM: dts: imx7-colibri: Set LCDIF format
This commit updates the device tree for the Colibri i.MX7 to explicitly set
the LCDIF pixel format to rgb666 for its 18-bit width bus.
> The lcd DPI interface on colibri imx6ull uses a 18-bit width bus, set
> the interface-pix-fmt accordingly.
[Severity: Medium]
Is this description accurate for this patch? The subject and the modified
file (imx7-colibri.dtsi) both target the i.MX7 hardware, but the commit
message body mentions the colibri imx6ull. Should this text be updated to
refer to the i.MX7?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260717121847.488148-1-francesco@dolcini.it?part=4
^ permalink raw reply
* Re: [PATCH v1 1/4] dt-bindings: lcdif: Add interface pixel format
From: sashiko-bot @ 2026-07-17 12:28 UTC (permalink / raw)
To: Francesco Dolcini; +Cc: devicetree, robh, dri-devel, Frank.Li, conor+dt, imx
In-Reply-To: <20260717121847.488148-2-francesco@dolcini.it>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Introduction of the legacy, non-standard `interface-pix-fmt` property for a standard hardware concept (parallel bus width), violating modern DT principles.
--
--- Patch [1]: [PATCH v1 1/4] dt-bindings: lcdif: Add interface pixel format ---
commit 7225ea545d2ff50540972dd75d375b8ecea4f315
Author: Francesco Dolcini <francesco.dolcini@toradex.com>
dt-bindings: lcdif: Add interface pixel format
This commit updates the fsl,lcdif device tree binding to support the
interface-pix-fmt property. The property is used to describe the hardware's
parallel data bus transfer width to match board wiring and prevent shifted
colors.
> diff --git a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml
> index 2dd0411ec6516..209ee5a96e393 100644
> --- a/Documentation/devicetree/bindings/display/fsl,lcdif.yaml
> +++ b/Documentation/devicetree/bindings/display/fsl,lcdif.yaml
> @@ -58,6 +58,13 @@ properties:
> items:
> - const: rx
>
> + interface-pix-fmt:
> + $ref: /schemas/types.yaml#/definitions/string
> + enum:
> + - rgb24
> + - rgb565
> + - rgb666
[Severity: Low]
Is this introducing a legacy, non-standard property into the new schema ABI?
Standard devicetree guidelines usually prefer endpoint properties like
bus-width (defined in video-interfaces.yaml) to describe physical parallel
data line configurations, such as setting bus-width = <18> for RGB666.
If a custom property is strictly necessary here rather than using the standard
endpoint properties, does this require a vendor prefix like
fsl,interface-pix-fmt to comply with modern devicetree naming conventions?
> +
> interrupts:
> items:
> - description: LCDIF DMA interrupt
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260717121847.488148-1-francesco@dolcini.it?part=1
^ permalink raw reply
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