* Re: [PATCH v4 03/11] power: sequencing: Add pwrseq_is_controllable() API
From: Loic Poulain @ 2026-07-17 14:45 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: linux-pci, linux-pm, linux-kernel, linux-arm-msm, linux-bluetooth,
devicetree, Manivannan Sadhasivam, Manivannan Sadhasivam,
Marcel Holtmann, Luiz Augusto von Dentz, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <CAMRc=Md8mLgYRsLd-KhwVV8X9AcYbHf--RB_pf0xFBP_P_DvCQ@mail.gmail.com>
Hi Bartosz,
On Fri, Jul 17, 2026 at 11:29 AM Bartosz Golaszewski <brgl@kernel.org> wrote:
>
> On Thu, 16 Jul 2026 18:18:20 +0200, Loic Poulain
> <loic.poulain@oss.qualcomm.com> said:
> > On some boards a power sequencing target has no host-controllable enable
> > for its function, for instance when the enable line is not wired up to a
> > GPIO and is hardwired to an always-on level. The pcie-m2 "uart" target is
> > one such example: when the M.2 connector does not route the W_DISABLE2#
> > signal to a host GPIO, its enable/disable are no-ops and the consumer
> > cannot gate the Bluetooth function at all or exclusively.
> >
> > Add a generic pwrseq_is_controllable() helper. It reports whether the
> > target's final unit provides a host-controllable dedicated power actuator.
> > The target can implement a new optional is_controllable() callback,
> > reporting whether that actuator is effective on this target (for example
> > depending on GPIO presence). If the target does not provide the callback,
> > it is assumed to be controllable.
> >
> > Note this only describes the target's own enable actuator. It does not
> > imply that a power-off reaches an electrical OFF state, since a target may
> > have multiple consumers. It also does not mean that power is uncontrolled
> > for the target's dependencies: those may still be gated on their own. And
> > it does not restrict consumers from calling pwrseq_power_off() either,
> > which remains valid to drop this consumer's vote on the (possibly shared)
> > resources and dependencies of the target.
> >
> > Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> > ---
>
> Thanks, this looks good to me now. This series is a bit all over the place,
> what is the merge strategy?
Since the entire series ultimately depends/touch on the pwrseq topic,
the simplest approach may be to take it all through your pwrseq
branch, with the possible exception of the DTS patches (through
Bjorn)?
Regards,
Loic
^ permalink raw reply
* Re: [PATCH v4 1/5] dt-bindings: mfd: x-powers,axp152: Document AXP318W
From: sashiko-bot @ 2026-07-17 14:43 UTC (permalink / raw)
To: Jerome Brunet; +Cc: robh, conor+dt, devicetree
In-Reply-To: <20260717-axp318-regulator-v4-1-50aff97084dd@baylibre.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The `x-powers,axp318w` compatible string was omitted from the conditional block that exempts similar PMIC generations from strictly requiring the `interrupts` property.
- [Medium] The regex pattern for regulator nodes allows non-existent switched output nodes (`swout3` through `swout9`) to silently pass validation.
--
--- Patch [1]: [PATCH v4 1/5] dt-bindings: mfd: x-powers,axp152: Document AXP318W ---
commit 08577b06937ca6f13b4a7f204e7f0abb6042c44d
Author: Andre Przywara <andre.przywara@arm.com>
dt-bindings: mfd: x-powers,axp152: Document AXP318W
The X-Powers AXP318W is a PMIC used on some newer Allwinner devices.
This patch adds the new compatible string, updates the PWM frequency
property list, adds input supply properties, and updates the pattern
for matching switched outputs.
> diff --git a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
> index 45f015d63df16..95b3984fe0f96 100644
> --- a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
> +++ b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
> @@ -83,6 +83,7 @@ allOf:
> contains:
> enum:
> - x-powers,axp313a
> + - x-powers,axp318w
> - x-powers,axp323
[Severity: Medium]
Should x-powers,axp318w also be added to the earlier conditional block that
exempts PMICs from requiring the interrupts property?
There is another allOf block in this binding that forces interrupts to be
required for all devices except a few specific generations:
- if:
not:
properties:
compatible:
contains:
enum:
- x-powers,axp15060
- x-powers,axp305
- x-powers,axp313a
- x-powers,axp323
then:
required:
- interrupts
Since the AXP318W shares constraints with siblings like axp313a and axp323,
will omitting it from that exemption block cause valid device trees without
an interrupts property to erroneously fail validation?
[ ... ]
> @@ -277,7 +303,7 @@ properties:
> Defines the work frequency of DC-DC in kHz.
>
> patternProperties:
> - "^(([a-f])?ldo[0-9]|dcdc[0-7a-e]|ldo(_|-)io(0|1)|(dc1)?sw|rtc(_|-)ldo|cpusldo|drivevbus|dc5ldo|boost)$":
> + "^(([a-f])?ldo[0-9]|dcdc[0-9a-e]|ldo(_|-)io(0|1)|(dc1)?sw|swout[1-9]|rtc(_|-)ldo|cpusldo|drivevbus|dc5ldo|boost)$":
[Severity: Medium]
Could the swout[1-9] pattern allow invalid switched output nodes to silently
pass validation?
The commit message notes that the PMIC features exactly two switched outputs,
swout1 and swout2. Allowing swout[1-9] might let device trees with invalid
nodes or typos like swout3 pass schema validation incorrectly. Would a tighter
pattern like swout[1-2] be more appropriate here?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260717-axp318-regulator-v4-0-50aff97084dd@baylibre.com?part=1
^ permalink raw reply
* Re: [PATCH v9 2/4] clk: cix: add sky1 audss clock controller
From: Brian Masney @ 2026-07-17 14:30 UTC (permalink / raw)
To: Joakim Zhang
Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de,
cix-kernel-upstream, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <SEYPR06MB6226BD151ABBB192AEC53BA482C62@SEYPR06MB6226.apcprd06.prod.outlook.com>
On Fri, Jul 17, 2026 at 09:47:28AM +0000, Joakim Zhang wrote:
> > -----Original Message-----
> > > +static void sky1_audss_clk_remove(struct platform_device *pdev) {
> > > + struct device *dev = &pdev->dev;
> > > +
> > > + if (!pm_runtime_status_suspended(dev))
> > > + pm_runtime_force_suspend(dev);
> > > +
> > > + pm_runtime_disable(dev);
> >
> > I am fairly certain that remove() is called before the devm handlers are
> > invoked. The clocks will be shutdown, but there's a window where they are still
> > visible to consumers. I think you should use
> > devm_add_action_or_reset() so that the cleanup is called in the expected order.
> Agreed. remove() runs before devres_release_all(), so force_suspend() tears down the hardware while the OF clock provider is still visible. I'll move the runtime PM cleanup into a devm_add_action_or_reset() registered before the clocks/provider, and drop it from remove().
I don't know which email client you are using but you should fix your
client so that the text in your response wraps at 80 characters. Also
add a newline between what you are quoting and your response since it
also makes things much nicer to read in the archive.
Brian
^ permalink raw reply
* [PATCH v4 5/5] regulator: axp20x: add support for the AXP318W
From: Jerome Brunet @ 2026-07-17 14:31 UTC (permalink / raw)
To: Andre Przywara, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Liam Girdwood, Mark Brown
Cc: devicetree, linux-kernel, Jerome Brunet
In-Reply-To: <20260717-axp318-regulator-v4-0-50aff97084dd@baylibre.com>
From: Andre Przywara <andre.przywara@arm.com>
The X-Powers AXP318W is a typical PMIC from X-Powers, featuring nine
DC/DC converters and 28 LDOs, on the regulator side.
Describe the chip's voltage settings and switch registers, how the
voltages are encoded, and connect this to the MFD device via its
regulator ID.
We use just "318" for the internal identifiers, for easier typing and
less churn. If something else other than the "AXP318W" shows up, that's
an easy change, externally visible strings carry the additional letter
already.
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Co-developed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/regulator/axp20x-regulator.c | 326 ++++++++++++++++++++++++++++++++++-
include/linux/mfd/axp20x.h | 45 +++++
2 files changed, 362 insertions(+), 9 deletions(-)
diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
index da891415efc0..8f6d28a1f76f 100644
--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
@@ -138,6 +138,30 @@
#define AXP313A_DCDC_V_OUT_MASK GENMASK(6, 0)
#define AXP313A_LDO_V_OUT_MASK GENMASK(4, 0)
+#define AXP318_DCDC1_PFM_PWM_CTRL BIT(7)
+#define AXP318_DCDC23_POLYPHASE_CTRL BIT(6)
+#define AXP318_DCDC45_POLYPHASE_CTRL BIT(7)
+#define AXP318_DCDC1_V_OUT_MASK GENMASK(4, 0)
+#define AXP318_DCDC2_V_OUT_MASK GENMASK(6, 0)
+#define AXP318_LDO_V_OUT_MASK GENMASK(4, 0)
+#define AXP318_ELDO_V_OUT_MASK GENMASK(5, 0)
+#define AXP318_THRESHOLD_VOLTAGE 1540000
+/*
+ * FIXME:
+ * Some LDOs of the AXP318 may be fed by different supplies and
+ * the documentation repeatedly warns that output voltage must
+ * be less than the supply, which is the case for any LDO really.
+ *
+ * The best way to let the framework handle this is to set the
+ * min_dropout_uV field. However the AXP318 documentation
+ * does not provide any information about this.
+ *
+ * Realistically, it can't be less than 1uV so use this
+ * for all LDOs until we know more.
+ */
+#define AXP318_LDO_MIN_DROPOUT 1 /* uV */
+
+
#define AXP717_DCDC1_NUM_VOLTAGES 88
#define AXP717_DCDC2_NUM_VOLTAGES 107
#define AXP717_DCDC3_NUM_VOLTAGES 103
@@ -371,8 +395,8 @@
.ops = &axp20x_ops, \
}
-#define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
- _vmask, _ereg, _emask) \
+#define AXP_DESC_EXT(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask, _ops, _bpreg, _bpmask, _dropout) \
[_family##_##_id] = { \
.name = (_match), \
.supply_name = (_supply), \
@@ -384,13 +408,32 @@
.owner = THIS_MODULE, \
.min_uV = (_min) * 1000, \
.uV_step = (_step) * 1000, \
+ .min_dropout_uV = (_dropout), \
.vsel_reg = (_vreg), \
.vsel_mask = (_vmask), \
.enable_reg = (_ereg), \
.enable_mask = (_emask), \
- .ops = &axp20x_ops, \
+ .bypass_reg = (_bpreg), \
+ .bypass_mask = (_bpmask), \
+ .ops = (_ops), \
}
+#define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask) \
+ AXP_DESC_EXT(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask, &axp20x_ops, 0, 0, 0)
+
+#define AXP_DESC_DO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask, _dropout) \
+ AXP_DESC_EXT(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask, &axp20x_ops, 0, 0, _dropout)
+
+#define AXP_DESC_BYPASS(_family, _id, _match, _supply, _min, _max, _step, _vreg,\
+ _vmask, _ereg, _emask, _bpreg, _bpmask, _dropout) \
+ AXP_DESC_EXT(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask, &axp20x_bypass_ops, _bpreg, \
+ _bpmask, _dropout)
+
#define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \
[_family##_##_id] = { \
.name = (_match), \
@@ -419,8 +462,9 @@
.ops = &axp20x_ops_fixed \
}
-#define AXP_DESC_RANGES_DELAY(_family, _id, _match, _supply, _ranges, _n_voltages, \
- _vreg, _vmask, _ereg, _emask, _ramp_delay) \
+#define AXP_DESC_RANGES_DELAY_OPS(_family, _id, _match, _supply, _ranges, \
+ _n_voltages, _vreg, _vmask, _ereg, _emask, \
+ _ramp_delay, _ops) \
[_family##_##_id] = { \
.name = (_match), \
.supply_name = (_supply), \
@@ -436,10 +480,23 @@
.enable_mask = (_emask), \
.linear_ranges = (_ranges), \
.n_linear_ranges = ARRAY_SIZE(_ranges), \
- .ramp_delay = (_ramp_delay), \
- .ops = &axp20x_ops_range, \
+ .ramp_delay = (_ramp_delay), \
+ .ops = (_ops), \
}
+#define AXP_DESC_RANGES_THRESHOLD(_family, _id, _match, _supply, _ranges, \
+ _n_voltages, _vreg, _vmask, _ereg, _emask) \
+ AXP_DESC_RANGES_DELAY_OPS(_family, _id, _match, _supply, _ranges, \
+ _n_voltages, _vreg, _vmask, _ereg, _emask, \
+ 0, &axp318_threshold_ops_range)
+
+#define AXP_DESC_RANGES_DELAY(_family, _id, _match, _supply, _ranges, \
+ _n_voltages, _vreg, _vmask, _ereg, _emask, \
+ _ramp_delay) \
+ AXP_DESC_RANGES_DELAY_OPS(_family, _id, _match, _supply, _ranges, \
+ _n_voltages, _vreg, _vmask, _ereg, _emask, \
+ _ramp_delay, &axp20x_ops_range)
+
#define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \
_vreg, _vmask, _ereg, _emask) \
AXP_DESC_RANGES_DELAY(_family, _id, _match, _supply, _ranges, \
@@ -567,6 +624,50 @@ static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev)
return regulator_enable_regmap(rdev);
};
+static int axp318_threshold_check(struct regulator_dev *rdev,
+ unsigned int sel)
+{
+ int old_sel, old_uV, new_uV, enabled;
+
+ /* Only applicable if the regulator is enabled */
+ enabled = rdev->desc->ops->is_enabled(rdev);
+ if (enabled <= 0)
+ return enabled;
+
+ old_sel = rdev->desc->ops->get_voltage_sel(rdev);
+ if (old_sel < 0)
+ return old_sel;
+
+ old_uV = rdev->desc->ops->list_voltage(rdev, old_sel);
+ if (old_uV < 0)
+ return old_uV;
+
+ new_uV = rdev->desc->ops->list_voltage(rdev, sel);
+ if (new_uV < 0)
+ return new_uV;
+
+ /* Crossing the threshold ? */
+ if ((old_uV <= AXP318_THRESHOLD_VOLTAGE
+ && new_uV > AXP318_THRESHOLD_VOLTAGE) ||
+ (new_uV <= AXP318_THRESHOLD_VOLTAGE
+ && old_uV > AXP318_THRESHOLD_VOLTAGE))
+ return -EBUSY;
+
+ return 0;
+}
+
+static int axp318_threshold_set_voltage_sel(struct regulator_dev *rdev,
+ unsigned int sel)
+{
+ int ret;
+
+ ret = axp318_threshold_check(rdev, sel);
+ if (ret < 0)
+ return ret;
+
+ return regulator_set_voltage_sel_regmap(rdev, sel);
+}
+
static const struct regulator_ops axp20x_ops_fixed = {
.list_voltage = regulator_list_voltage_linear,
};
@@ -580,6 +681,15 @@ static const struct regulator_ops axp20x_ops_range = {
.is_enabled = regulator_is_enabled_regmap,
};
+static const struct regulator_ops axp318_threshold_ops_range = {
+ .set_voltage_sel = axp318_threshold_set_voltage_sel,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .list_voltage = regulator_list_voltage_linear_range,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+};
+
static const struct regulator_ops axp20x_ops = {
.set_voltage_sel = regulator_set_voltage_sel_regmap,
.get_voltage_sel = regulator_get_voltage_sel_regmap,
@@ -590,6 +700,19 @@ static const struct regulator_ops axp20x_ops = {
.set_ramp_delay = axp20x_set_ramp_delay,
};
+static const struct regulator_ops axp20x_bypass_ops = {
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .list_voltage = regulator_list_voltage_linear,
+ .enable = axp20x_regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .set_ramp_delay = axp20x_set_ramp_delay,
+ .get_bypass = regulator_get_bypass_regmap,
+ .set_bypass = regulator_set_bypass_regmap,
+};
+
+
static const struct regulator_ops axp20x_ops_sw = {
.enable = regulator_enable_regmap,
.disable = regulator_disable_regmap,
@@ -765,6 +888,158 @@ static const struct regulator_desc axp313a_regulators[] = {
AXP_DESC_FIXED(AXP313A, RTC_LDO, "rtc-ldo", "vin1", 1800),
};
+static const struct linear_range axp318_dcdc2_ranges[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
+ REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),
+};
+
+static const struct linear_range axp318_dcdc6_ranges[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
+ REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),
+ REGULATOR_LINEAR_RANGE(1800000, 88, 118, 20000),
+ REGULATOR_LINEAR_RANGE(2440000, 119, 127, 40000),
+};
+
+static const struct linear_range axp318_dcdc7_ranges[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
+ REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000),
+};
+
+static const struct linear_range axp318_dcdc8_ranges[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
+ REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000),
+ REGULATOR_LINEAR_RANGE(1900000, 103, 118, 100000),
+};
+
+static const struct regulator_desc axp318_regulators[] = {
+ AXP_DESC(AXP318, DCDC1, "dcdc1", "vin19", 1000, 3400, 100,
+ AXP318_DCDC1_CONTROL, AXP318_DCDC1_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(0)),
+ AXP_DESC_RANGES(AXP318, DCDC2, "dcdc2", "vin23",
+ axp318_dcdc2_ranges, 88,
+ AXP318_DCDC2_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(1)),
+ AXP_DESC_RANGES(AXP318, DCDC3, "dcdc3", "vin23",
+ axp318_dcdc2_ranges, 88,
+ AXP318_DCDC3_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(2)),
+ AXP_DESC_RANGES(AXP318, DCDC4, "dcdc4", "vin45",
+ axp318_dcdc2_ranges, 88,
+ AXP318_DCDC4_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(3)),
+ AXP_DESC_RANGES(AXP318, DCDC5, "dcdc5", "vin45",
+ axp318_dcdc2_ranges, 88,
+ AXP318_DCDC5_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(4)),
+ AXP_DESC_RANGES_THRESHOLD(AXP318, DCDC6, "dcdc6", "vin678",
+ axp318_dcdc6_ranges, 128,
+ AXP318_DCDC6_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(5)),
+ AXP_DESC_RANGES_THRESHOLD(AXP318, DCDC7, "dcdc7", "vin678",
+ axp318_dcdc7_ranges, 103,
+ AXP318_DCDC7_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(6)),
+ AXP_DESC_RANGES_THRESHOLD(AXP318, DCDC8, "dcdc8", "vin678",
+ axp318_dcdc8_ranges, 119,
+ AXP318_DCDC8_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL1, BIT(7)),
+ AXP_DESC_RANGES_THRESHOLD(AXP318, DCDC9, "dcdc9", "vin19",
+ axp318_dcdc8_ranges, 119,
+ AXP318_DCDC9_CONTROL, AXP318_DCDC2_V_OUT_MASK,
+ AXP318_DCDC_OUTPUT_CONTROL2, BIT(0)),
+ AXP_DESC_SW(AXP318, SWOUT1, "swout1", NULL,
+ AXP318_DCDC_OUTPUT_CONTROL2, BIT(3)),
+ AXP_DESC_SW(AXP318, SWOUT2, "swout2", NULL,
+ AXP318_DCDC_OUTPUT_CONTROL2, BIT(4)),
+ AXP_DESC_DO(AXP318, ALDO1, "aldo1", "aldo156in", 500, 3400, 100,
+ AXP318_ALDO1_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(0), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ALDO2, "aldo2", "aldo234in", 500, 3400, 100,
+ AXP318_ALDO2_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(1), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ALDO3, "aldo3", "aldo234in", 500, 3400, 100,
+ AXP318_ALDO3_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(2), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ALDO4, "aldo4", "aldo234in", 500, 3400, 100,
+ AXP318_ALDO4_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(3), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ALDO5, "aldo5", "aldo156in", 500, 3400, 100,
+ AXP318_ALDO5_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(4), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ALDO6, "aldo6", "aldo156in", 500, 3400, 100,
+ AXP318_ALDO6_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(5), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, BLDO1, "bldo1", "bldoin", 500, 3400, 100,
+ AXP318_BLDO1_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(6), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, BLDO2, "bldo2", "bldoin", 500, 3400, 100,
+ AXP318_BLDO2_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL1, BIT(7), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, BLDO3, "bldo3", "bldoin", 500, 3400, 100,
+ AXP318_BLDO3_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(0), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, BLDO4, "bldo4", "bldoin", 500, 3400, 100,
+ AXP318_BLDO4_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(1), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, BLDO5, "bldo5", "bldoin", 500, 3400, 100,
+ AXP318_BLDO5_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(2), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, CLDO1, "cldo1", "cldoin", 500, 3400, 100,
+ AXP318_CLDO1_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(3), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, CLDO2, "cldo2", "cldoin", 500, 3400, 100,
+ AXP318_CLDO2_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(4), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, CLDO3, "cldo3", "cldoin", 500, 3400, 100,
+ AXP318_CLDO3_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(5), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, CLDO4, "cldo4", "cldoin", 500, 3400, 100,
+ AXP318_CLDO4_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(6), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, CLDO5, "cldo5", "cldoin", 500, 3400, 100,
+ AXP318_CLDO5_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL2, BIT(7), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, DLDO1, "dldo1", "dldoin", 500, 3400, 100,
+ AXP318_DLDO1_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(0), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, DLDO2, "dldo2", "dldoin", 500, 3400, 100,
+ AXP318_DLDO2_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(1), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, DLDO3, "dldo3", "dldoin", 500, 3400, 100,
+ AXP318_DLDO3_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(2), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, DLDO4, "dldo4", "dldoin", 500, 3400, 100,
+ AXP318_DLDO4_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(3), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, DLDO5, "dldo5", "dldoin", 500, 3400, 100,
+ AXP318_DLDO5_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(4), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, DLDO6, "dldo6", "dldoin", 500, 3400, 100,
+ AXP318_DLDO6_CONTROL, AXP318_LDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(5), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ELDO1, "eldo1", "eldoin", 500, 1500, 25,
+ AXP318_ELDO1_CONTROL, AXP318_ELDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(6), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ELDO2, "eldo2", "eldoin", 500, 1500, 25,
+ AXP318_ELDO2_CONTROL, AXP318_ELDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL3, BIT(7), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ELDO3, "eldo3", "eldoin", 500, 1500, 25,
+ AXP318_ELDO3_CONTROL, AXP318_ELDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL4, BIT(0), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_BYPASS(AXP318, ELDO4, "eldo4", "eldoin", 500, 1500, 25,
+ AXP318_ELDO4_CONTROL, AXP318_ELDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL4, BIT(1),
+ AXP318_ELDO4_CONTROL, BIT(6), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_BYPASS(AXP318, ELDO5, "eldo5", "eldoin", 500, 1500, 25,
+ AXP318_ELDO5_CONTROL, AXP318_ELDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL4, BIT(2),
+ AXP318_ELDO5_CONTROL, BIT(6), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_DO(AXP318, ELDO6, "eldo6", "eldoin", 500, 1500, 25,
+ AXP318_ELDO6_CONTROL, AXP318_ELDO_V_OUT_MASK,
+ AXP318_LDO_OUTPUT_CONTROL4, BIT(3), AXP318_LDO_MIN_DROPOUT),
+ AXP_DESC_FIXED(AXP318, RTC_LDO, "rtc-ldo", "ips", 1800),
+};
+
static const struct linear_range axp717_dcdc1_ranges[] = {
REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),
REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),
@@ -1347,6 +1622,7 @@ static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
step = 150;
break;
case AXP313A_ID:
+ case AXP318_ID:
case AXP323_ID:
case AXP717_ID:
case AXP15060_ID:
@@ -1430,6 +1706,20 @@ static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 work
workmode <<= ffs(mask) - 1;
break;
+ case AXP318_ID:
+ /*
+ * Only DCDC1 has PWM control on the AXP318
+ * The other DCDCs control DVM through bit 7 of the related
+ * registers. Work mode could possibly extended to deal with
+ * this but it is not how it is documented at the moment
+ */
+ if (id != AXP318_DCDC1)
+ return -EINVAL;
+ reg = AXP318_DCDC1_CONTROL;
+ mask = AXP318_DCDC1_PFM_PWM_CTRL;
+ workmode <<= ffs(mask) - 1;
+ break;
+
case AXP806_ID:
/*
* AXP806 DCDC regulator IDs have the same range as AXP22X.
@@ -1543,6 +1833,17 @@ static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
}
break;
+ case AXP318_ID:
+ regmap_read(axp20x->regmap, AXP318_DCDC_CONTROL1, ®);
+
+ switch (id) {
+ case AXP318_DCDC3:
+ return !!(reg & AXP318_DCDC23_POLYPHASE_CTRL);
+ case AXP318_DCDC5:
+ return !!(reg & AXP318_DCDC45_POLYPHASE_CTRL);
+ }
+ break;
+
default:
return false;
}
@@ -1585,6 +1886,10 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
regulators = axp313a_regulators;
nregulators = AXP313A_REG_ID_MAX;
break;
+ case AXP318_ID:
+ regulators = axp318_regulators;
+ nregulators = AXP318_REG_ID_MAX;
+ break;
case AXP717_ID:
regulators = axp717_regulators;
nregulators = AXP717_REG_ID_MAX;
@@ -1651,7 +1956,9 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||
(regulators == axp803_regulators && i == AXP803_DC1SW) ||
(regulators == axp809_regulators && i == AXP809_DC1SW) ||
- (regulators == axp15060_regulators && i == AXP15060_SW)) {
+ (regulators == axp15060_regulators && i == AXP15060_SW) ||
+ (regulators == axp318_regulators && i == AXP318_SWOUT1) ||
+ (regulators == axp318_regulators && i == AXP318_SWOUT2)) {
new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
GFP_KERNEL);
if (!new_desc)
@@ -1709,7 +2016,8 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
*/
if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
(regulators == axp809_regulators && i == AXP809_DCDC1) ||
- (regulators == axp15060_regulators && i == AXP15060_DCDC1))
+ (regulators == axp15060_regulators && i == AXP15060_DCDC1) ||
+ (regulators == axp318_regulators && i == AXP318_DCDC1))
of_property_read_string(rdev->dev.of_node,
"regulator-name",
&dcdc1_name);
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
index c1f9dc06387a..10a959f362d3 100644
--- a/include/linux/mfd/axp20x.h
+++ b/include/linux/mfd/axp20x.h
@@ -128,6 +128,7 @@ enum axp20x_variants {
#define AXP318_DCDC7_CONTROL 0x18
#define AXP318_DCDC8_CONTROL 0x19
#define AXP318_DCDC9_CONTROL 0x1a
+#define AXP318_DCDC_CONTROL1 0x1b
#define AXP318_LDO_OUTPUT_CONTROL1 0x20
#define AXP318_LDO_OUTPUT_CONTROL2 0x21
#define AXP318_LDO_OUTPUT_CONTROL3 0x22
@@ -562,6 +563,50 @@ enum {
AXP313A_REG_ID_MAX,
};
+enum {
+ AXP318_DCDC1 = 0,
+ AXP318_DCDC2,
+ AXP318_DCDC3,
+ AXP318_DCDC4,
+ AXP318_DCDC5,
+ AXP318_DCDC6,
+ AXP318_DCDC7,
+ AXP318_DCDC8,
+ AXP318_DCDC9,
+ AXP318_ALDO1,
+ AXP318_ALDO2,
+ AXP318_ALDO3,
+ AXP318_ALDO4,
+ AXP318_ALDO5,
+ AXP318_ALDO6,
+ AXP318_BLDO1,
+ AXP318_BLDO2,
+ AXP318_BLDO3,
+ AXP318_BLDO4,
+ AXP318_BLDO5,
+ AXP318_CLDO1,
+ AXP318_CLDO2,
+ AXP318_CLDO3,
+ AXP318_CLDO4,
+ AXP318_CLDO5,
+ AXP318_DLDO1,
+ AXP318_DLDO2,
+ AXP318_DLDO3,
+ AXP318_DLDO4,
+ AXP318_DLDO5,
+ AXP318_DLDO6,
+ AXP318_ELDO1,
+ AXP318_ELDO2,
+ AXP318_ELDO3,
+ AXP318_ELDO4,
+ AXP318_ELDO5,
+ AXP318_ELDO6,
+ AXP318_SWOUT1,
+ AXP318_SWOUT2,
+ AXP318_RTC_LDO,
+ AXP318_REG_ID_MAX,
+};
+
enum {
AXP717_DCDC1 = 0,
AXP717_DCDC2,
--
2.47.3
^ permalink raw reply related
* [PATCH v4 4/5] mfd: axp20x-i2c: Fix i2c instantiation
From: Jerome Brunet @ 2026-07-17 14:31 UTC (permalink / raw)
To: Andre Przywara, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Liam Girdwood, Mark Brown
Cc: devicetree, linux-kernel, Sashiko, Jerome Brunet
In-Reply-To: <20260717-axp318-regulator-v4-0-50aff97084dd@baylibre.com>
Apparently this device never really supported i2c instantiation via
sysfs, because the driver does not even look at the i2c driver, which are
not set. It would only probe if the device matched through DT.
Fix that for correctness, even-though it is probably useless.
Add the missing AXP323 while at it.
Reported-by: Sashiko <sashiko-bot@kernel.org>
Closes: https://lore.kernel.org/r/20260717090209.2A09B1F000E9@smtp.kernel.org
Fixes: 41751b033aaa ("mfd: axp20x-i2c: Add i2c-ids to fix module auto-loading")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/mfd/axp20x-i2c.c | 26 ++++++++++++++------------
drivers/mfd/axp20x-rsb.c | 1 +
drivers/mfd/axp20x.c | 1 -
3 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c
index 4e4ebfc78525..64c212b76e5e 100644
--- a/drivers/mfd/axp20x-i2c.c
+++ b/drivers/mfd/axp20x-i2c.c
@@ -35,6 +35,7 @@ static int axp20x_i2c_probe(struct i2c_client *i2c)
axp20x->irq = i2c->irq;
dev_set_drvdata(axp20x->dev, axp20x);
+ axp20x->variant = (kernel_ulong_t)i2c_get_match_data(i2c);
ret = axp20x_match_device(axp20x);
if (ret)
return ret;
@@ -77,18 +78,19 @@ MODULE_DEVICE_TABLE(of, axp20x_i2c_of_match);
#endif
static const struct i2c_device_id axp20x_i2c_id[] = {
- { "axp152" },
- { "axp192" },
- { "axp202" },
- { "axp209" },
- { "axp221" },
- { "axp223" },
- { "axp313a" },
- { "axp318w" },
- { "axp717" },
- { "axp803" },
- { "axp806" },
- { "axp15060" },
+ { .name = "axp152", .driver_data = AXP152_ID },
+ { .name = "axp192", .driver_data = AXP192_ID },
+ { .name = "axp202", .driver_data = AXP202_ID },
+ { .name = "axp209", .driver_data = AXP209_ID },
+ { .name = "axp221", .driver_data = AXP221_ID },
+ { .name = "axp223", .driver_data = AXP223_ID },
+ { .name = "axp313a", .driver_data = AXP313A_ID },
+ { .name = "axp318w", .driver_data = AXP318_ID },
+ { .name = "axp323", .driver_data = AXP323_ID },
+ { .name = "axp717", .driver_data = AXP717_ID },
+ { .name = "axp803", .driver_data = AXP803_ID },
+ { .name = "axp806", .driver_data = AXP806_ID },
+ { .name = "axp15060", .driver_data = AXP15060_ID },
{ }
};
MODULE_DEVICE_TABLE(i2c, axp20x_i2c_id);
diff --git a/drivers/mfd/axp20x-rsb.c b/drivers/mfd/axp20x-rsb.c
index 059656f2a1bd..8fdc870c1fe4 100644
--- a/drivers/mfd/axp20x-rsb.c
+++ b/drivers/mfd/axp20x-rsb.c
@@ -35,6 +35,7 @@ static int axp20x_rsb_probe(struct sunxi_rsb_device *rdev)
axp20x->irq = rdev->irq;
dev_set_drvdata(&rdev->dev, axp20x);
+ axp20x->variant = (kernel_ulong_t)device_get_match_data(axp20x->dev);
ret = axp20x_match_device(axp20x);
if (ret)
return ret;
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 2bbe73afff43..25509e47bedc 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -1339,7 +1339,6 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
const struct mfd_cell *cells_no_irq = NULL;
int nr_cells_no_irq = 0;
- axp20x->variant = (long)device_get_match_data(dev);
switch (axp20x->variant) {
case AXP152_ID:
axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
--
2.47.3
^ permalink raw reply related
* [PATCH v4 3/5] mfd: axp20x: Constify axp313 and axp717 cells
From: Jerome Brunet @ 2026-07-17 14:31 UTC (permalink / raw)
To: Andre Przywara, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Liam Girdwood, Mark Brown
Cc: devicetree, linux-kernel, Jerome Brunet
In-Reply-To: <20260717-axp318-regulator-v4-0-50aff97084dd@baylibre.com>
mfd_cells array should generally be const and there does not seem to be
anything against it for the axp313 and axp717.
Constify the mfd_cells array for the axp313 and axp717 to be consitent
with the other supported chips
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/mfd/axp20x.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index c8aeebd01bbc..2bbe73afff43 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -1123,7 +1123,7 @@ static const struct mfd_cell axp152_cells[] = {
},
};
-static struct mfd_cell axp313a_cells[] = {
+static const struct mfd_cell axp313a_cells[] = {
/* AXP323 is sometimes paired with AXP717 as sub-PMIC */
MFD_CELL_BASIC("axp20x-regulator", NULL, NULL, 0, 1),
MFD_CELL_RES("axp313a-pek", axp313a_pek_resources),
@@ -1133,7 +1133,7 @@ static const struct mfd_cell axp318_cells[] = {
MFD_CELL_BASIC("axp20x-regulator", NULL, NULL, 0, 1),
};
-static struct mfd_cell axp717_cells[] = {
+static const struct mfd_cell axp717_cells[] = {
MFD_CELL_NAME("axp20x-regulator"),
MFD_CELL_RES("axp20x-pek", axp717_pek_resources),
MFD_CELL_OF("axp717-adc",
--
2.47.3
^ permalink raw reply related
* [PATCH v4 2/5] mfd: axp20x: Add support for AXP318W PMIC
From: Jerome Brunet @ 2026-07-17 14:31 UTC (permalink / raw)
To: Andre Przywara, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Liam Girdwood, Mark Brown
Cc: devicetree, linux-kernel, Jerome Brunet
In-Reply-To: <20260717-axp318-regulator-v4-0-50aff97084dd@baylibre.com>
From: Andre Przywara <andre.przywara@arm.com>
The AXP318W is a PMIC chip produced by X-Powers, it can be connected to
an I2C bus.
It has a large number of regulators: 9(!) DCDC buck converters, and 28
LDOs, also some ADCs, interrupts, and a power key.
Describe the regmap and the MFD bits, along with the registers exposed
via I2C only. This covers the regulators and interrupts for now.
Advertise the device using the new compatible string.
We use just "318" for the internal identifiers, for easier typing and
less churn, but use "318W" for anything externally visible. If something
else other than the "AXP318W" shows up, that's an easy change then.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/mfd/axp20x-i2c.c | 2 ++
drivers/mfd/axp20x.c | 78 +++++++++++++++++++++++++++++++++++++++++
include/linux/mfd/axp20x.h | 86 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 166 insertions(+)
diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c
index 5c93136f977e..4e4ebfc78525 100644
--- a/drivers/mfd/axp20x-i2c.c
+++ b/drivers/mfd/axp20x-i2c.c
@@ -65,6 +65,7 @@ static const struct of_device_id axp20x_i2c_of_match[] = {
{ .compatible = "x-powers,axp221", .data = (void *)AXP221_ID },
{ .compatible = "x-powers,axp223", .data = (void *)AXP223_ID },
{ .compatible = "x-powers,axp313a", .data = (void *)AXP313A_ID },
+ { .compatible = "x-powers,axp318w", .data = (void *)AXP318_ID },
{ .compatible = "x-powers,axp323", .data = (void *)AXP323_ID },
{ .compatible = "x-powers,axp717", .data = (void *)AXP717_ID },
{ .compatible = "x-powers,axp803", .data = (void *)AXP803_ID },
@@ -83,6 +84,7 @@ static const struct i2c_device_id axp20x_i2c_id[] = {
{ "axp221" },
{ "axp223" },
{ "axp313a" },
+ { "axp318w" },
{ "axp717" },
{ "axp803" },
{ "axp806" },
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 679364189ea5..c8aeebd01bbc 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -42,6 +42,7 @@ static const char * const axp20x_model_names[] = {
[AXP223_ID] = "AXP223",
[AXP288_ID] = "AXP288",
[AXP313A_ID] = "AXP313a",
+ [AXP318_ID] = "AXP318W",
[AXP323_ID] = "AXP323",
[AXP717_ID] = "AXP717",
[AXP803_ID] = "AXP803",
@@ -218,6 +219,31 @@ static const struct regmap_access_table axp313a_volatile_table = {
.n_yes_ranges = ARRAY_SIZE(axp313a_volatile_ranges),
};
+static const struct regmap_range axp318_writeable_ranges[] = {
+ regmap_reg_range(AXP318_DCDC_OUTPUT_CONTROL1, AXP318_IRQ_STATE4),
+ regmap_reg_range(AXP318_SHUTDOWN_CTRL, AXP318_TEMP_ADC_H_EN),
+ regmap_reg_range(AXP318_DIE_TEMP_ADC_H_EN, AXP318_DIE_TEMP_ADC_H_EN),
+ regmap_reg_range(AXP318_GPADC_H_EN, AXP318_GPADC_H_EN),
+ regmap_reg_range(AXP318_GPIO_CTRL, AXP318_WDOG_CTRL),
+};
+
+static const struct regmap_range axp318_volatile_ranges[] = {
+ regmap_reg_range(AXP318_IRQ_EN1, AXP318_IRQ_STATE4),
+ regmap_reg_range(AXP318_POWER_REASON, AXP318_SHUTDOWN_REASON),
+ regmap_reg_range(AXP318_TEMP_ADC_H_EN, AXP318_GPADC_L),
+ regmap_reg_range(AXP318_GPIO_INPUT, AXP318_GPIO_INPUT),
+};
+
+static const struct regmap_access_table axp318_writeable_table = {
+ .yes_ranges = axp318_writeable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(axp318_writeable_ranges),
+};
+
+static const struct regmap_access_table axp318_volatile_table = {
+ .yes_ranges = axp318_volatile_ranges,
+ .n_yes_ranges = ARRAY_SIZE(axp318_volatile_ranges),
+};
+
static const struct regmap_range axp717_writeable_ranges[] = {
regmap_reg_range(AXP717_PMU_FAULT, AXP717_MODULE_EN_CONTROL_1),
regmap_reg_range(AXP717_MIN_SYS_V_CONTROL, AXP717_BOOST_CONTROL),
@@ -447,6 +473,15 @@ static const struct regmap_config axp313a_regmap_config = {
.cache_type = REGCACHE_MAPLE,
};
+static const struct regmap_config axp318_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .wr_table = &axp318_writeable_table,
+ .volatile_table = &axp318_volatile_table,
+ .max_register = AXP318_WDOG_CTRL,
+ .cache_type = REGCACHE_MAPLE,
+};
+
static const struct regmap_config axp323_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
@@ -663,6 +698,28 @@ static const struct regmap_irq axp313a_regmap_irqs[] = {
INIT_REGMAP_IRQ(AXP313A, DIE_TEMP_HIGH, 0, 0),
};
+static const struct regmap_irq axp318_regmap_irqs[] = {
+ INIT_REGMAP_IRQ(AXP318, DCDC8_V_LOW, 0, 7),
+ INIT_REGMAP_IRQ(AXP318, DCDC7_V_LOW, 0, 6),
+ INIT_REGMAP_IRQ(AXP318, DCDC6_V_LOW, 0, 5),
+ INIT_REGMAP_IRQ(AXP318, DCDC5_V_LOW, 0, 4),
+ INIT_REGMAP_IRQ(AXP318, DCDC4_V_LOW, 0, 3),
+ INIT_REGMAP_IRQ(AXP318, DCDC3_V_LOW, 0, 2),
+ INIT_REGMAP_IRQ(AXP318, DCDC2_V_LOW, 0, 1),
+ INIT_REGMAP_IRQ(AXP318, DCDC1_V_LOW, 0, 0),
+ INIT_REGMAP_IRQ(AXP318, PEK_RIS_EDGE, 1, 6),
+ INIT_REGMAP_IRQ(AXP318, PEK_FAL_EDGE, 1, 5),
+ INIT_REGMAP_IRQ(AXP318, PEK_LONG, 1, 4),
+ INIT_REGMAP_IRQ(AXP318, PEK_SHORT, 1, 3),
+ INIT_REGMAP_IRQ(AXP318, DIE_TEMP_HIGH_LV2, 1, 2),
+ INIT_REGMAP_IRQ(AXP318, DIE_TEMP_HIGH_LV1, 1, 1),
+ INIT_REGMAP_IRQ(AXP318, DCDC9_V_LOW, 1, 0),
+ INIT_REGMAP_IRQ(AXP318, GPIO3_INPUT, 2, 6),
+ INIT_REGMAP_IRQ(AXP318, GPIO2_INPUT, 2, 5),
+ INIT_REGMAP_IRQ(AXP318, GPIO1_INPUT, 2, 4),
+ INIT_REGMAP_IRQ(AXP318, WDOG_EXPIRE, 3, 0),
+};
+
static const struct regmap_irq axp717_regmap_irqs[] = {
INIT_REGMAP_IRQ(AXP717, SOC_DROP_LVL2, 0, 7),
INIT_REGMAP_IRQ(AXP717, SOC_DROP_LVL1, 0, 6),
@@ -884,6 +941,17 @@ static const struct regmap_irq_chip axp313a_regmap_irq_chip = {
.num_regs = 1,
};
+static const struct regmap_irq_chip axp318_regmap_irq_chip = {
+ .name = "axp318w_irq_chip",
+ .status_base = AXP318_IRQ_STATE1,
+ .ack_base = AXP318_IRQ_STATE1,
+ .unmask_base = AXP318_IRQ_EN1,
+ .init_ack_masked = true,
+ .irqs = axp318_regmap_irqs,
+ .num_irqs = ARRAY_SIZE(axp318_regmap_irqs),
+ .num_regs = 4,
+};
+
static const struct regmap_irq_chip axp717_regmap_irq_chip = {
.name = "axp717_irq_chip",
.status_base = AXP717_IRQ0_STATE,
@@ -1061,6 +1129,10 @@ static struct mfd_cell axp313a_cells[] = {
MFD_CELL_RES("axp313a-pek", axp313a_pek_resources),
};
+static const struct mfd_cell axp318_cells[] = {
+ MFD_CELL_BASIC("axp20x-regulator", NULL, NULL, 0, 1),
+};
+
static struct mfd_cell axp717_cells[] = {
MFD_CELL_NAME("axp20x-regulator"),
MFD_CELL_RES("axp20x-pek", axp717_pek_resources),
@@ -1313,6 +1385,12 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
axp20x->regmap_cfg = &axp313a_regmap_config;
axp20x->regmap_irq_chip = &axp313a_regmap_irq_chip;
break;
+ case AXP318_ID:
+ axp20x->nr_cells = ARRAY_SIZE(axp318_cells);
+ axp20x->cells = axp318_cells;
+ axp20x->regmap_cfg = &axp318_regmap_config;
+ axp20x->regmap_irq_chip = &axp318_regmap_irq_chip;
+ break;
case AXP323_ID:
axp20x->nr_cells = ARRAY_SIZE(axp313a_cells);
axp20x->cells = axp313a_cells;
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
index b352661d99a1..c1f9dc06387a 100644
--- a/include/linux/mfd/axp20x.h
+++ b/include/linux/mfd/axp20x.h
@@ -19,6 +19,7 @@ enum axp20x_variants {
AXP223_ID,
AXP288_ID,
AXP313A_ID,
+ AXP318_ID,
AXP323_ID,
AXP717_ID,
AXP803_ID,
@@ -116,6 +117,69 @@ enum axp20x_variants {
#define AXP313A_IRQ_STATE 0x21
#define AXP323_DCDC_MODE_CTRL2 0x22
+#define AXP318_DCDC_OUTPUT_CONTROL1 0x10
+#define AXP318_DCDC_OUTPUT_CONTROL2 0x11
+#define AXP318_DCDC1_CONTROL 0x12
+#define AXP318_DCDC2_CONTROL 0x13
+#define AXP318_DCDC3_CONTROL 0x14
+#define AXP318_DCDC4_CONTROL 0x15
+#define AXP318_DCDC5_CONTROL 0x16
+#define AXP318_DCDC6_CONTROL 0x17
+#define AXP318_DCDC7_CONTROL 0x18
+#define AXP318_DCDC8_CONTROL 0x19
+#define AXP318_DCDC9_CONTROL 0x1a
+#define AXP318_LDO_OUTPUT_CONTROL1 0x20
+#define AXP318_LDO_OUTPUT_CONTROL2 0x21
+#define AXP318_LDO_OUTPUT_CONTROL3 0x22
+#define AXP318_LDO_OUTPUT_CONTROL4 0x23
+#define AXP318_ALDO1_CONTROL 0x24
+#define AXP318_ALDO2_CONTROL 0x25
+#define AXP318_ALDO3_CONTROL 0x26
+#define AXP318_ALDO4_CONTROL 0x27
+#define AXP318_ALDO5_CONTROL 0x28
+#define AXP318_ALDO6_CONTROL 0x29
+#define AXP318_BLDO1_CONTROL 0x2a
+#define AXP318_BLDO2_CONTROL 0x2b
+#define AXP318_BLDO3_CONTROL 0x2c
+#define AXP318_BLDO4_CONTROL 0x2d
+#define AXP318_BLDO5_CONTROL 0x2e
+#define AXP318_CLDO1_CONTROL 0x2f
+#define AXP318_CLDO2_CONTROL 0x30
+#define AXP318_CLDO3_CONTROL 0x31
+#define AXP318_CLDO4_CONTROL 0x32
+#define AXP318_CLDO5_CONTROL 0x33
+#define AXP318_DLDO1_CONTROL 0x34
+#define AXP318_DLDO2_CONTROL 0x35
+#define AXP318_DLDO3_CONTROL 0x36
+#define AXP318_DLDO4_CONTROL 0x37
+#define AXP318_DLDO5_CONTROL 0x38
+#define AXP318_DLDO6_CONTROL 0x39
+#define AXP318_ELDO1_CONTROL 0x3a
+#define AXP318_ELDO2_CONTROL 0x3b
+#define AXP318_ELDO3_CONTROL 0x3c
+#define AXP318_ELDO4_CONTROL 0x3d
+#define AXP318_ELDO5_CONTROL 0x3e
+#define AXP318_ELDO6_CONTROL 0x3f
+#define AXP318_IRQ_EN1 0x40
+#define AXP318_IRQ_EN2 0x41
+#define AXP318_IRQ_EN3 0x42
+#define AXP318_IRQ_EN4 0x43
+#define AXP318_IRQ_STATE1 0x48
+#define AXP318_IRQ_STATE2 0x49
+#define AXP318_IRQ_STATE3 0x4a
+#define AXP318_IRQ_STATE4 0x4b
+#define AXP318_POWER_REASON 0x50
+#define AXP318_SHUTDOWN_REASON 0x51
+#define AXP318_SHUTDOWN_CTRL 0x52
+#define AXP318_TEMP_ADC_H_EN 0x65
+#define AXP318_TEMP_ADC_L 0x66
+#define AXP318_DIE_TEMP_ADC_H_EN 0x67
+#define AXP318_GPADC_H_EN 0x69
+#define AXP318_GPADC_L 0x6a
+#define AXP318_GPIO_CTRL 0x70
+#define AXP318_GPIO_INPUT 0x71
+#define AXP318_WDOG_CTRL 0x77
+
#define AXP717_ON_INDICATE 0x00
#define AXP717_PMU_STATUS_2 0x01
#define AXP717_BC_DETECT 0x05
@@ -819,6 +883,28 @@ enum axp313a_irqs {
AXP313A_IRQ_PEK_RIS_EDGE,
};
+enum axp318_irqs {
+ AXP318_IRQ_DCDC1_V_LOW,
+ AXP318_IRQ_DCDC2_V_LOW,
+ AXP318_IRQ_DCDC3_V_LOW,
+ AXP318_IRQ_DCDC4_V_LOW,
+ AXP318_IRQ_DCDC5_V_LOW,
+ AXP318_IRQ_DCDC6_V_LOW,
+ AXP318_IRQ_DCDC7_V_LOW,
+ AXP318_IRQ_DCDC8_V_LOW,
+ AXP318_IRQ_DCDC9_V_LOW,
+ AXP318_IRQ_DIE_TEMP_HIGH_LV1,
+ AXP318_IRQ_DIE_TEMP_HIGH_LV2,
+ AXP318_IRQ_PEK_SHORT,
+ AXP318_IRQ_PEK_LONG,
+ AXP318_IRQ_PEK_FAL_EDGE,
+ AXP318_IRQ_PEK_RIS_EDGE,
+ AXP318_IRQ_GPIO1_INPUT = 20,
+ AXP318_IRQ_GPIO2_INPUT,
+ AXP318_IRQ_GPIO3_INPUT,
+ AXP318_IRQ_WDOG_EXPIRE = 24,
+};
+
enum axp717_irqs {
AXP717_IRQ_VBUS_FAULT,
AXP717_IRQ_VBUS_OVER_V,
--
2.47.3
^ permalink raw reply related
* [PATCH v4 1/5] dt-bindings: mfd: x-powers,axp152: Document AXP318W
From: Jerome Brunet @ 2026-07-17 14:31 UTC (permalink / raw)
To: Andre Przywara, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Liam Girdwood, Mark Brown
Cc: devicetree, linux-kernel, Conor Dooley, Jerome Brunet
In-Reply-To: <20260717-axp318-regulator-v4-0-50aff97084dd@baylibre.com>
From: Andre Przywara <andre.przywara@arm.com>
The X-Powers AXP318W is a PMIC used on some newer Allwinner devices.
Among a large number of both DCDC and LDO regulators it features the usual
ADC/IRQ/power key parts.
Like other recent PMICs, it lacks the DC/DC converter PWM frequency control
register, that rate is fixed here (1.5MHz on DCDC1, 3 MHz on the others).
Add the new compatible string, and add that to the list of PMICs without
the PWM frequency property.
Also add more input supply properties, for the split DCDC and ALDO
supplies.
The PMIC features *two* switched outputs, hanging of DCDC1, and the
manual calls them swout1 and swout2, so follow suit here and add those
names to the pattern for matching the node names.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
.../devicetree/bindings/mfd/x-powers,axp152.yaml | 28 +++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
index 45f015d63df1..95b3984fe0f9 100644
--- a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
+++ b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
@@ -83,6 +83,7 @@ allOf:
contains:
enum:
- x-powers,axp313a
+ - x-powers,axp318w
- x-powers,axp323
- x-powers,axp15060
- x-powers,axp717
@@ -102,6 +103,7 @@ properties:
- x-powers,axp221
- x-powers,axp223
- x-powers,axp313a
+ - x-powers,axp318w
- x-powers,axp323
- x-powers,axp717
- x-powers,axp803
@@ -156,10 +158,18 @@ properties:
description: >
DCDC1 power supply node, if present.
+ vin19-supply:
+ description: >
+ Combined DCDC1/DCDC9 power supply node, if present.
+
vin2-supply:
description: >
DCDC2 power supply node, if present.
+ vin23-supply:
+ description: >
+ Combined DCDC2/DCDC3 power supply node, if present.
+
vin3-supply:
description: >
DCDC3 power supply node, if present.
@@ -168,6 +178,10 @@ properties:
description: >
DCDC4 power supply node, if present.
+ vin45-supply:
+ description: >
+ Combined DCDC4/DCDC5 power supply node, if present.
+
vin5-supply:
description: >
DCDC5 power supply node, if present.
@@ -176,6 +190,10 @@ properties:
description: >
DCDC6 power supply node, if present.
+ vin678-supply:
+ description: >
+ Combined DCDC6/DCDC7/DCDC8 power supply node, if present.
+
vin7-supply:
description: >
DCDC7 power supply node, if present.
@@ -220,6 +238,14 @@ properties:
description: >
ALDO* power supply node, if present.
+ aldo156in-supply:
+ description: >
+ ALDO* power supply node, if present.
+
+ aldo234in-supply:
+ description: >
+ ALDO* power supply node, if present.
+
bldoin-supply:
description: >
BLDO* power supply node, if present.
@@ -277,7 +303,7 @@ properties:
Defines the work frequency of DC-DC in kHz.
patternProperties:
- "^(([a-f])?ldo[0-9]|dcdc[0-7a-e]|ldo(_|-)io(0|1)|(dc1)?sw|rtc(_|-)ldo|cpusldo|drivevbus|dc5ldo|boost)$":
+ "^(([a-f])?ldo[0-9]|dcdc[0-9a-e]|ldo(_|-)io(0|1)|(dc1)?sw|swout[1-9]|rtc(_|-)ldo|cpusldo|drivevbus|dc5ldo|boost)$":
$ref: /schemas/regulator/regulator.yaml#
type: object
unevaluatedProperties: false
--
2.47.3
^ permalink raw reply related
* [PATCH v4 0/5] regulator: Add X-Powers AXP318W PMIC support
From: Jerome Brunet @ 2026-07-17 14:31 UTC (permalink / raw)
To: Andre Przywara, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Liam Girdwood, Mark Brown
Cc: devicetree, linux-kernel, Conor Dooley, Jerome Brunet, Sashiko
This patch series adds support for the X-Powers AXP318W PMIC, which is
used recently on new boards with Allwinner SoCs (the A733).
The PMIC features 9 DCDC buck converters and 28 LDOs, plus the usual ADC,
interrupts, and power key components.
A datasheet can be found linked in this Wiki table:
https://linux-sunxi.org/AXP_PMICs
There was an unclosed topic regarding the handling of LDOs output
voltage being limited to input voltage being provided by the supply.
Chen-Yu noted the min_dropout_uV would be a good fit for that but
the actual minimal dropout value was unknown. I've arbitrarily picked
1uV because it is the minimum the framework supports. Realistically a low
dropout regulator is bound to have some dropout. This choice does the
trick for now and is certain be less restrictive than what it is in
reality.
If anyone has problems because the dropout is actually higher
* it is arguably an HW design error
* it is a good time to let us know what the actual dropout is
Changes in v4:
- Capitalize patch 3 title
- regulator: add support for workmode and poly-phase.
- i2c: fix probe through i2c sysfs
- Link to v3: https://patch.msgid.link/20260717-axp318-regulator-v3-0-779dc1b97dd4@baylibre.com
Changes in v3:
- Correct mess up v2 errors regarding ops and ids.
- Correctly propagate errors when checking axp318 threshold.
- Fix DT binding regex regarding dcdc max ids
- Add missing RTCLDO.
- Remove axp318 PEK MFD cell:
As pointed out by sashiko, the driver name did not match anything in the
pek driver. While the device does support some handling of the power
button, it does not seem to match the existing driver. Register 0x36
relates to DLDO3, not the power key, as expected by the misc driver.
Leave this out for now.
- Constify axp313 and axp717 mfd_cells array for consistency.
- Link to v2: https://patch.msgid.link/20260710-axp318-regulator-v2-0-ee5f1c56b49f@baylibre.com
Changes in v2:
- Droped _NUM_VOLTAGES macros
- Use min_dropout_uV to limit LDO voltage to supplies
- Add bypass mode for EDLO4/5
- Prevent crossing 1.54V threshold for DCDC6/7/8/9
- Link to v1: https://lore.kernel.org/r/20251021112013.2710903-1-andre.przywara@arm.com
---
Andre Przywara (3):
dt-bindings: mfd: x-powers,axp152: Document AXP318W
mfd: axp20x: Add support for AXP318W PMIC
regulator: axp20x: add support for the AXP318W
Jerome Brunet (2):
mfd: axp20x: Constify axp313 and axp717 cells
mfd: axp20x-i2c: Fix i2c instantiation
.../devicetree/bindings/mfd/x-powers,axp152.yaml | 28 +-
drivers/mfd/axp20x-i2c.c | 26 +-
drivers/mfd/axp20x-rsb.c | 1 +
drivers/mfd/axp20x.c | 83 +++++-
drivers/regulator/axp20x-regulator.c | 326 ++++++++++++++++++++-
include/linux/mfd/axp20x.h | 131 +++++++++
6 files changed, 571 insertions(+), 24 deletions(-)
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260710-axp318-regulator-43545ce3261f
Best regards,
--
Jerome
^ permalink raw reply
* Re: [PATCH 1/4] regulator: dt-bindings: Add Silergy SYR82X allowed modes
From: Victor Krawiec @ 2026-07-17 14:14 UTC (permalink / raw)
To: Mark Brown, Krzysztof Kozlowski
Cc: lgirdwood, robh, krzk+dt, conor+dt, linux-kernel, devicetree
In-Reply-To: <38adfbda-2cdb-49bb-84d4-aae0a6258f68@sirena.org.uk>
On 7/17/26 14:44, Mark Brown wrote:
> On Fri, Jul 17, 2026 at 02:31:51PM +0200, Krzysztof Kozlowski wrote:
>
>> So you are adding constants for one device but used in the bindings and
>> driver for other? Are they valid there?
>
> It's one of these devices that's got a bunch of clones from various
> manufacturers with minor differences and share a driver.
I checked the datasheets and all devices share the same 2 modes which
are Auto-PFM and Forced PWM mode.
Since devices are all clones and share the same modes the binding part
can be generic. I plan to rename the header and its macros to use
FAN53555 name and add this property to the binding:
regulator-initial-mode:
enum:
[ 1, 2 ]
description:
Defined in
include/dt-bindings/regulator/fcs,fan53555-regulator.h
However the implementation I made in the driver is currently
restricted to SYR82X. I could make it generic but I don't have access
to the other devices to test it.
Best regards
Victor
^ permalink raw reply
* Re: [PATCH v4 0/2] iio: adc: add MAX40080 current-sense amplifier driver
From: Siratul Islam @ 2026-07-17 14:03 UTC (permalink / raw)
To: Stefan Popa; +Cc: jic23, andriy.shevchenko, nuno.sa, devicetree, linux-iio
In-Reply-To: <20260717123852.1140893-1-stefan.popa@analog.com>
On Fri, 2026-07-17 at 15:38 +0300, Stefan Popa wrote:
> This series adds support for the Maxim MAX40080, a bidirectional
> current-sense amplifier with an integrated 12-bit ADC and an I2C/SMBus
> interface. It measures the voltage across an external shunt resistor and
> the input bus voltage.
>
> The driver operates in direct (INDIO_DIRECT_MODE) mode. Each raw read
> triggers a single on-demand conversion (SMBus Quick Command) and reads
> back the matched current/voltage pair, so results are always fresh. It
> exposes the current and voltage channels with raw and scale attributes,
> a configurable oversampling (digital averaging) ratio, and PEC-protected
> register access. The two selectable current-sense ranges are exposed
> through scale/scale_available; the current scale is derived from the
> shunt-resistor-micro-ohms device-tree property.
>
> Tested on hardware with four MAX40080 devices on an I2C bus.
>
> Regarding regmap: it does not support SMBus PEC or Quick Command, both of
> which are required by this device. The mlx90614 driver uses the same raw
> i2c_smbus approach for similar reasons.
>
> Changes in v4:
>
...
>
...
> --
> 2.53.0
Was it intentional to drop people from your Cc list who
were present / engaged in previous versions? Please try to keep it consistent.
Also, it helps to include the links to the previous versions.
--
Best regards,
Sirat
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: mfd: st,stmpe: add deprecated properties
From: Rob Herring (Arm) @ 2026-07-17 13:59 UTC (permalink / raw)
To: Frank.Li
Cc: linux-kernel, Alexandre Torgue, Maxime Coquelin, linux-arm-kernel,
linux-stm32, devicetree, Conor Dooley, Frank Li, Linus Walleij,
imx, Krzysztof Kozlowski, Sascha Hauer, Pengutronix Kernel Team,
Lee Jones, Fabio Estevam
In-Reply-To: <20260708-dts-stmpe-v1-1-1f51d15bb358@nxp.com>
On Wed, 08 Jul 2026 15:48:56 -0400, Frank.Li@oss.nxp.com wrote:
> From: Frank Li <Frank.Li@nxp.com>
>
> Add deprecated properties st,sample-time, st,sample-time, st,mod-12b and
> st,ref-sel. The both driver drivers/mfd/stmpe.c and
> drivers/input/touchscreen/stmpe-ts.c parse these information. Some dts
> put these properties under mfd, but some put these under child node
> sample_ts.
>
> Allow these properties put under sample_ts and mark as deprecated to fix
> below CHECK_DTBS warnings:
> arch/arm/boot/dts/nxp/imx/imx6q-novena.dtb: stmpe811@44 (st,stmpe811): touchscreen: Unevaluated properties are not allowed ('st,adc-freq', 'st,mod-12b', 'st,ref-sel', 'st,sample-time' were unexpected)
> from schema $id: http://devicetree.org/schemas/mfd/st,stmpe.yaml
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> .../devicetree/bindings/mfd/st,stmpe.yaml | 24 ++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v6 6/6] arm64: dts: qcom: Add device tree for Nord RRD board
From: Bartosz Golaszewski @ 2026-07-17 13:58 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bartosz Golaszewski, Deepti Jaggi, devicetree, linux-arm-msm,
linux-kernel, Bartosz Golaszewski, Shawn Guo, Bjorn Andersson
In-Reply-To: <b522c9b4-4944-4fb2-94f9-bd2553690901@oss.qualcomm.com>
On Thu, 16 Jul 2026 19:17:14 +0200, Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> said:
> On 7/16/26 4:26 PM, Shawn Guo wrote:
>> Add initial device tree for the Qualcomm Dragonwing IQ10 RRD (Robotics
>> Reference Design) board, which is built on Nord Embedded variant. Enable
>> the debug UART, UFS storage, PMICs, I2C and SPI.
>>
>> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
>> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
>> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
>> ---
>
> [...]
>
>> + /* PMIC A - Kobra_MM (PMM8650AU) - SID 0x0, Bus E0 */
>
> This comment is very useful
>
>> + regulators-0 {
>> + compatible = "qcom,pmm8654au-rpmh-regulators";
>> + qcom,pmic-id = "A_E0";
>> +
>> + /* LDO Regulators */
>
> This is much less so
>
> [...]
>
>> + vreg_l7a_1p2: ldo7 {
>> + regulator-name = "vreg_l7a_1p2";
>> + regulator-min-microvolt = <1200000>;
>> + regulator-max-microvolt = <1200000>;
>> + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + regulator-allow-set-load;
>
> You made a lot of the regulators always-/boot-on - are you sure about
> each one of them?
>
I double checked and for vreg_l3e_1p8 and vreg_l2i_1p2 we can drop the flags.
The first one feeds the efuse, the second UFS. The rest is fine.
Bart
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: display: imx: Add deprecated property display and display0
From: Rob Herring (Arm) @ 2026-07-17 13:58 UTC (permalink / raw)
To: Frank.Li
Cc: linux-arm-kernel, Alison Wang, vladimir.oltean, Simona Vetter,
Maxime Ripard, imx, Pengutronix Kernel Team, Frank Li,
ioana.ciornei, Krzysztof Kozlowski, Conor Dooley,
Maarten Lankhorst, devicetree, dri-devel, Stefan Agner,
linux-kernel, Thomas Zimmermann, Fabio Estevam, Sascha Hauer,
David Airlie
In-Reply-To: <20260708-ls-dts-display-v1-1-1986b2611895@nxp.com>
On Wed, 08 Jul 2026 15:39:51 -0400, Frank.Li@oss.nxp.com wrote:
> From: Frank Li <Frank.Li@nxp.com>
>
> Add deprecated property display and display0 to allow old platform lx1021a
> (>10 years) to put display timing under dcu node.
>
> Following patch rename display@0 to display0 and mode0 to timing0. Fix
> below CHECK_DTBS warnings:
> arch/arm/boot/dts/nxp/ls/ls1021a-iot.dtb: dcu@2ce0000 (fsl,ls1021a-dcu): 'display', 'display@0' do not match any of the regexes: '^pinctrl-[0-9]+$'
> from schema $id: http://devicetree.org/schemas/display/fsl,ls1021a-dcu.yaml
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> .../bindings/display/fsl,ls1021a-dcu.yaml | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: fsl,fpga-qixis: Add fsl,ls1021aqds-fpga compatible string
From: Rob Herring (Arm) @ 2026-07-17 13:57 UTC (permalink / raw)
To: Frank.Li
Cc: imx, Conor Dooley, linux-arm-kernel, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, vladimir.oltean, Krzysztof Kozlowski,
Fabio Estevam, devicetree, linux-kernel, Ioana Ciornei
In-Reply-To: <20260708-ls-fpga-v1-1-06c8a099b2a5@nxp.com>
On Wed, 08 Jul 2026 14:55:13 -0400, Frank.Li@oss.nxp.com wrote:
> From: Frank Li <Frank.Li@nxp.com>
>
> Add fsl,ls1021aqds-fpga compatible string for ls1021a qds's FPGA on board
> controller chips, which connect CFI interface.
>
> With following patches to fix below CHECK_DTBS warnings:
> arch/arm/boot/dts/nxp/ls/ls1021a-qds.dtb: memory-controller@1530000 (fsl,ifc): board-control@3,0: 'oneOf' conditional failed, one must be fixed:
> 'bank-width', 'device-width' do not match any of the regexes: '^gpio@[0-9a-f]+$', '^mdio-mux@[a-f0-9,]+$', '^pinctrl-[0-9]+$'
> /home/lizhi/source/linux-upstream-pci-ep-arm/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dtb: memory-controller@1530000 (fsl,ifc): board-control@3,0:compatible: 'oneOf' conditional failed, one must be fixed:
> ['simple-mfd'] is too short
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 2/4] dt-bindings: clock: qcom: Add Qualcomm Shikra AudioCoreCC and AudioCoreCSR
From: Rob Herring @ 2026-07-17 13:56 UTC (permalink / raw)
To: Imran Shaik
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Philipp Zabel, Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio,
Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
linux-kernel, devicetree
In-Reply-To: <20260708-shikra-audiocorecc-v2-2-b320d822cdd0@oss.qualcomm.com>
On Wed, Jul 08, 2026 at 11:55:06PM +0530, Imran Shaik wrote:
> Add device tree bindings for the Audio Core Clock Controller (AudioCoreCC)
> that provides clocks and Audio Core CSR that provides resets on Qualcomm
> Shikra SoC.
This should be 2 schema docs. They share very little.
>
> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
> ---
> .../bindings/clock/qcom,shikra-audiocorecc.yaml | 90 ++++++++++++++++++++++
> .../dt-bindings/clock/qcom,shikra-audiocorecc.h | 49 ++++++++++++
> 2 files changed, 139 insertions(+)
^ permalink raw reply
* Re: [PATCH v6 1/5] spi: dt-bindings: Add spi-device-addr peripheral property
From: Nuno Sá @ 2026-07-17 13:52 UTC (permalink / raw)
To: Mark Brown
Cc: Conor Dooley, Janani Sunil, Lars-Peter Clausen, Michael Hennerich,
Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Philipp Zabel,
Jonathan Corbet, Shuah Khan, Marius Cristea, Marcus Folkesson,
Kent Gustavsson, linux-iio, devicetree, linux-kernel, linux-doc,
Janani Sunil, linux-spi, Kent Gustavsson
In-Reply-To: <27746e91-ab2b-40a0-822b-6d3a8997cefc@sirena.org.uk>
On Fri, Jul 17, 2026 at 12:51:53PM +0100, Mark Brown wrote:
> On Thu, Jul 16, 2026 at 06:06:13PM +0100, Conor Dooley wrote:
> > On Thu, Jul 16, 2026 at 01:28:15PM +0100, Mark Brown wrote:
>
> > > Oh, isn't that just multi-pin chip selects then:
>
> > > https://patch.msgid.link/cover.1783729282.git.Jonathan.Santos@analog.com
>
> > No, I think that's something different.
>
> > In this case, there is one chip select that all instances of the device
> > share. Both the ADI and Microchip devices then use the upper bits of the
> > first/address byte during reads and write to access individual devices.
> > In the microchip case that I'm familiar with, what upper bits the device
> > responds to are set by fuses in the factory. They also share the same MOSI
> > and MISO.
>
> I'm struggling to identify a way in which this is functionally different
> to a multi-pin chip select.
>
> > The SPI core already supports two of these devices from Microchip, since
> > it just modifies the contents of tx_buf in a spi_transfer.
>
> When I said we'd have to modify the bitstream I was told that wasn't the
> case and this was just asserting more pins along with the "chip select".
Oh sorry,
Likely I was not clear. The part as some ID pins which are just
configuration! So they are two pins and depending on how they are set
(low/high) each chip can have four possible addresses! Now all of the chips
(to a max of 4) are connected to same CS of the controller so just one CS get's
asserted.
Of course the above will assert on all devices on that same CS but only
the one where the ID pins combo match the spi xfer high bits (part of
the address) will reply.
Hopefully the above makes it clear.
- Nuno Sá
^ permalink raw reply
* Re: [PATCH v6 2/3] pwm: rp1: Add RP1 PWM controller driver
From: Uwe Kleine-König @ 2026-07-17 13:49 UTC (permalink / raw)
To: Andrea della Porta
Cc: linux-pwm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Florian Fainelli, Broadcom internal kernel review list,
devicetree, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
Naushir Patuck, Stanimir Varbanov, mbrugger, Sean Young,
Julian Braha
In-Reply-To: <aln1D3E5QZULZ2U1@apocalypse>
[-- Attachment #1: Type: text/plain, Size: 3351 bytes --]
Hello Andrea,
On Fri, Jul 17, 2026 at 11:25:35AM +0200, Andrea della Porta wrote:
> On 11:18 Thu 16 Jul , Uwe Kleine-König wrote:
> > On Fri, Jul 03, 2026 at 07:05:25PM +0200, Andrea della Porta wrote:
> > > +static int rp1_pwm_round_waveform_tohw(struct pwm_chip *chip,
> > > + struct pwm_device *pwm,
> > > + const struct pwm_waveform *wf,
> > > + void *_wfhw)
> > > +{
> > > + struct rp1_pwm *rp1 = pwmchip_get_drvdata(chip);
> > > + u64 period_ticks, duty_ticks, offset_ticks;
> > > + struct rp1_pwm_waveform *wfhw = _wfhw;
> > > + u64 clk_rate = rp1->clk_rate;
> > > + int ret = 0;
> > > +
> > > + if (!wf->period_length_ns) {
> > > + wfhw->enabled = false;
> > > + wfhw->inverted_polarity = (pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED);
> >
> > pwm_get_polarity(pwm) looks wrong here for several reasons. 1st the
> > polarity is defined in *wf and should not depend on the current state,
> > 2nd for a disabled hardware the polarity doesn't matter anyhow, and 3rd
> > you should not call pwm API functions from the lowlevel driver (which
> > might interfere with subsystem locking).
>
> Ok, but in this case what the output of the disabled channel should be?
> If it was inverted before the disable, would it make sense to let the output
> be high? Or are we allowed to hard code a polarity value on disable?
Given that not all hardwares can drive the output of a disabled PWM to a
fixed level, a consumer that relies on a fixed inactive level output
must not disable the PWM. So it doesn't matter what you do on
wf->period_length_ns == 0, the only objective is to save power.
> > > + if (!wfhw->inverted_polarity) {
> > > + wf->duty_length_ns = DIV_ROUND_UP_ULL((u64)wfhw->duty_ticks * NSEC_PER_SEC,
> > > + (u32)clk_rate);
> > > + } else {
> > > + if (wfhw->duty_ticks > (u64)wfhw->period_ticks + 1) {
> > > + /* 100% duty cycle case */
> > > + ticks = 0;
> > > + } else {
> > > + ticks = (u64)wfhw->period_ticks + 1 - wfhw->duty_ticks;
> > > + }
> > > + wf->duty_length_ns = DIV_ROUND_UP_ULL(ticks * NSEC_PER_SEC, clk_rate);
> > > + wf->duty_offset_ns = wf->period_length_ns - wf->duty_length_ns;
> >
> > The duty_offset_ns calculation is wrong.
> >
> > Consider clk_rate = 3000000, period_ticks = 8, inverted_polarity = true and
> > duty_ticks = 4.
> >
> > Then you have:
> >
> > .period_length_ns = 2666.6666666666666 ns ~> 2667
> > .duty_length_ns = 1333.3333333333333 ns -> 1334
> > .duty_offset_ns = 1333.3333333333333 ns -> 1334
> >
> > but .period_length_ns - .duty_length_ns is 1333.
> >
> > To get this right, you have to calculate
> >
> > wf->duty_offset_ns = DIV_ROUND_UP_ULL((u64)(wfhw->period_ticks + 1 - ticks) * NSEC_PER_SEC, clk_rate);
>
> So it will end up as 'duty_length_ns + duty_offset_ns >
> period_length_ns', which is timing violation. Is it allowed (or even
> required) in the PWM subsystem?
Not all hardwares support that, but logically it makes sense. The active
phase of the output just crosses the period border. With duty_length_ns
+ duty_offset_ns < period_length_ns (and duty_offset > 0) it's the
inactive phase that crosses the period border, and there is no reason
why the active phase should be more special than the inactive one.
Best regards
Uwe
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^ permalink raw reply
* Re: [PATCH v2 05/15] arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec
From: Stefano Radaelli @ 2026-07-17 13:46 UTC (permalink / raw)
To: Frank Li; +Cc: sashiko-reviews, Frank.Li, imx, robh, devicetree, conor+dt
In-Reply-To: <ak1KYjOUWDy6po5j@SMW015318>
Hi Frank,
On Tue, Jul 07, 2026 at 01:50:10PM -0500, Frank Li wrote:
> >
> > Thanks for pointing this out.
> >
> > This audio routing is not new for this board. It follows the same WM8904
> > routing that we have been using on our other platforms for quite some
> > time, and we are not aware of any reported issues related to the
> > analogue microphone path.
> >
> > If adding an explicit route to MICBIAS is indeed required by the
> > codec driver, then this would not be specific to this board but would
> > potentially apply to all of our WM8904-based platforms.
> >
> > I'd prefer not to introduce this functional change as part of this DTS
> > alignment series without validating it across all affected platforms.
> > If needed, we can investigate the MICBIAS routing separately and
> > submit a dedicated fix covering all WM8904-based boards.
>
> Okay, thanks.
>
> Frank
>
> >
> > Thanks,
> > Stefano
Hi Frank,
Just for my understanding, is this patch series going to be applied or
are there any further changes you would like me to make?
Thank you,
Best Regards,
Stefano
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: iommu: ti,omap-iommu: Convert to DT schema
From: Rob Herring (Arm) @ 2026-07-17 13:46 UTC (permalink / raw)
To: Bhargav Joshi
Cc: m-chawdhry, Will Deacon, daniel.baluta, Krzysztof Kozlowski,
iommu, goledhruva, linux-kernel, devicetree, simona.toaca,
Joerg Roedel (AMD), Conor Dooley, Robin Murphy
In-Reply-To: <20260708-ti-omap-iommu-v2-1-612d4a6644ba@gmail.com>
On Wed, 08 Jul 2026 22:21:43 +0530, Bhargav Joshi wrote:
> Convert Texas Instruments OMAP2+ IOMMU from text to DT schema. Make the
> 'ti,hwmods' property optional and mark it deprecated as it is no longer
> used, it is kept to support legacy dtbs.
>
> Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
> ---
> Changes in v2:
> - Added maxItems:1 to ti,syscon-mmuconfig as property expects only one
> pair of phandle-args
> - Added deafult value 32 for ti,#tlb-entries
> - Link to v1: https://lore.kernel.org/r/20260708-ti-omap-iommu-v1-1-48cfc53aaa46@gmail.com
> ---
> .../devicetree/bindings/iommu/ti,omap-iommu.txt | 59 -----------
> .../devicetree/bindings/iommu/ti,omap-iommu.yaml | 114 +++++++++++++++++++++
> 2 files changed, 114 insertions(+), 59 deletions(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply
* [PATCH v2 2/2] arm64: dts: qcom: milos: add CPU OPP table with DDR & L3 bandwidths
From: Luca Weiss @ 2026-07-17 13:33 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Sibi Sankar, Bjorn Andersson, Konrad Dybcio, Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, linux-pm,
devicetree, linux-kernel, Luca Weiss, Konrad Dybcio
In-Reply-To: <20260717-milos-cpu-opp-v2-0-428813fafd52@fairphone.com>
Add the OSC L3 Cache controller node, interconnect entry for each CPU,
with 2 different paths (CPU to DDR, L3 Cache from CPU to DDR interface),
and add the OPP tables for each CPU clusters (cpu0-3, cpu4-6 & cpu7) to
permit scaling the DDR and L3 cache frequency by aggregating bandwidth
requests of all CPU core with reference to the current OPP they are
configured in by the LMH/EPSS hardware.
The effect is a proper caches & DDR frequency scaling when CPU cores
change frequency.
The OPP tables were built using the downstream memlat ddr & l3 tables
for each cluster type with the actual EPSS cpufreq LUT tables from
running devices. Note, that higher frequencies than SM7635 are available
on QCS6690, those have been added here as far as possible but may not be
fully complete. Additional OPPs may need to be added for that SoC.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/milos.dtsi | 344 ++++++++++++++++++++++++++++++++++++
1 file changed, 344 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index 8c9232988953..974afd7a582e 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,milos-rpmh.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
@@ -65,6 +66,13 @@ cpu0: cpu@0 {
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_0: l2-cache {
@@ -98,6 +106,13 @@ cpu1: cpu@100 {
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
};
@@ -118,6 +133,13 @@ cpu2: cpu@200 {
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_2: l2-cache {
@@ -145,6 +167,13 @@ cpu3: cpu@300 {
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
};
@@ -165,6 +194,13 @@ cpu4: cpu@400 {
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu4_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_4: l2-cache {
@@ -192,6 +228,13 @@ cpu5: cpu@500 {
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu4_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_5: l2-cache {
@@ -219,6 +262,13 @@ cpu6: cpu@600 {
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu4_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_6: l2-cache {
@@ -246,6 +296,13 @@ cpu7: cpu@700 {
qcom,freq-domain = <&cpufreq_hw 2>;
+ operating-points-v2 = <&cpu7_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
+
#cooling-cells = <2>;
l2_7: l2-cache {
@@ -394,6 +451,281 @@ memory@0 {
reg = <0 0 0 0>;
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-441600000 {
+ opp-hz = /bits/ 64 <441600000>;
+ opp-peak-kBps = <(547000 * 4) (364800 * 32)>;
+ };
+
+ opp-595200000 {
+ opp-hz = /bits/ 64 <595200000>;
+ opp-peak-kBps = <(547000 * 4) (556800 * 32)>;
+ };
+
+ opp-787200000 {
+ opp-hz = /bits/ 64 <787200000>;
+ opp-peak-kBps = <(547000 * 4) (710400 * 32)>;
+ };
+
+ opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-peak-kBps = <(547000 * 4) (806400 * 32)>;
+ };
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <(547000 * 4) (998400 * 32)>;
+ };
+
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-peak-kBps = <(547000 * 4) (998400 * 32)>;
+ };
+
+ opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-peak-kBps = <(768000 * 4) (1094400 * 32)>;
+ };
+
+ opp-1344000000 {
+ opp-hz = /bits/ 64 <1344000000>;
+ opp-peak-kBps = <(768000 * 4) (1209600 * 32)>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <(768000 * 4) (1363200 * 32)>;
+ };
+
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (1363200 * 32)>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (1497600 * 32)>;
+ };
+
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2054400000 {
+ opp-hz = /bits/ 64 <2054400000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (1804800 * 32)>;
+ };
+ };
+
+ cpu4_opp_table: opp-table-cpu4 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-peak-kBps = <(547000 * 4) (364800 * 32)>;
+ };
+
+ opp-633600000 {
+ opp-hz = /bits/ 64 <633600000>;
+ opp-peak-kBps = <(547000 * 4) (556800 * 32)>;
+ };
+
+ opp-787200000 {
+ opp-hz = /bits/ 64 <787200000>;
+ opp-peak-kBps = <(547000 * 4) (556800 * 32)>;
+ };
+
+ opp-940800000 {
+ opp-hz = /bits/ 64 <940800000>;
+ opp-peak-kBps = <(547000 * 4) (556800 * 32)>;
+ };
+
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 768000 */
+ opp-peak-kBps = <(768000 * 4) (710400 * 32)>;
+ };
+
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 768000 */
+ opp-peak-kBps = <(768000 * 4) (710400 * 32)>;
+ };
+
+ opp-1286400000 {
+ opp-hz = /bits/ 64 <1286400000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (902400 * 32)>;
+ };
+
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (1209600 * 32)>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (1209600 * 32)>;
+ };
+
+ opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 1555000 */
+ opp-peak-kBps = <(1555000 * 4) (1363200 * 32)>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <(1708000 * 4) (1363200 * 32)>;
+ };
+
+ opp-1824000000 {
+ opp-hz = /bits/ 64 <1824000000>;
+ opp-peak-kBps = <(1708000 * 4) (1497600 * 32)>;
+ };
+
+ opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 2092000 */
+ opp-peak-kBps = <(2092000 * 4) (1497600 * 32)>;
+ };
+
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 2092000 */
+ opp-peak-kBps = <(2092000 * 4) (1497600 * 32)>;
+ };
+
+ opp-2073600000 {
+ opp-hz = /bits/ 64 <2073600000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 2092000 */
+ opp-peak-kBps = <(2092000 * 4) (1497600 * 32)>;
+ };
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 2092000 */
+ opp-peak-kBps = <(2092000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2400000000 {
+ opp-hz = /bits/ 64 <2400000000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2707200000 {
+ opp-hz = /bits/ 64 <2707200000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1804800 * 32)>;
+ };
+ };
+
+ cpu7_opp_table: opp-table-cpu7 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-peak-kBps = <(547000 * 4) (364800 * 32)>;
+ };
+
+ opp-633600000 {
+ opp-hz = /bits/ 64 <633600000>;
+ opp-peak-kBps = <(547000 * 4) (556800 * 32)>;
+ };
+
+ opp-787200000 {
+ opp-hz = /bits/ 64 <787200000>;
+ opp-peak-kBps = <(547000 * 4) (806400 * 32)>;
+ };
+
+ opp-960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-peak-kBps = <(547000 * 4) (806400 * 32)>;
+ };
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 768000 */
+ opp-peak-kBps = <(768000 * 4) (998400 * 32)>;
+ };
+
+ opp-1209600000 {
+ opp-hz = /bits/ 64 <1209600000>;
+ /* TODO: ddr4 = 1017000, ddr5 = 768000 */
+ opp-peak-kBps = <(768000 * 4) (998400 * 32)>;
+ };
+
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-peak-kBps = <(1555000 * 4) (998400 * 32)>;
+ };
+
+ opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <(1555000 * 4) (1209600 * 32)>;
+ };
+
+ opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-peak-kBps = <(1708000 * 4) (1209600 * 32)>;
+ };
+
+ opp-1766400000 {
+ opp-hz = /bits/ 64 <1766400000>;
+ /* TODO: ddr4 = 1708000, ddr5 = 2092000 */
+ opp-peak-kBps = <(2092000 * 4) (1363200 * 32)>;
+ };
+
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ /* TODO: ddr4 = 2092000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1497600 * 32)>;
+ };
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ /* TODO: ddr4 = 2092000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1497600 * 32)>;
+ };
+
+ opp-2304000000 {
+ opp-hz = /bits/ 64 <2304000000>;
+ /* TODO: ddr4 = 2092000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2496000000 {
+ opp-hz = /bits/ 64 <2496000000>;
+ /* TODO: ddr4 = 2092000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2707200000 {
+ opp-hz = /bits/ 64 <2707200000>;
+ /* TODO: ddr4 = 2092000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1804800 * 32)>;
+ };
+
+ opp-2918400000 {
+ opp-hz = /bits/ 64 <2918400000>;
+ /* TODO: ddr4 = 2092000, ddr5 = 3196000 */
+ opp-peak-kBps = <(3196000 * 4) (1804800 * 32)>;
+ };
+ };
+
pmu-a520 {
compatible = "arm,cortex-a520-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
@@ -2639,6 +2971,18 @@ rpmhpd_opp_turbo_l1: opp-416 {
};
};
+ epss_l3: interconnect@17d90000 {
+ compatible = "qcom,milos-epss-l3", "qcom,epss-l3";
+ reg = <0x0 0x17d90000 0x0 0x1000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPLL0>;
+ clock-names = "xo",
+ "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@17d91000 {
compatible = "qcom,milos-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0x0 0x17d91000 0x0 0x1000>,
--
2.55.0
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: interconnect: OSM L3: Document Milos OSM L3 compatible
From: Luca Weiss @ 2026-07-17 13:33 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Sibi Sankar, Bjorn Andersson, Konrad Dybcio, Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, linux-pm,
devicetree, linux-kernel, Luca Weiss, Krzysztof Kozlowski
In-Reply-To: <20260717-milos-cpu-opp-v2-0-428813fafd52@fairphone.com>
Document the OSM L3 found in the Qualcomm Milos SoC.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index 41b9f758bf8b..17690ff34489 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -29,6 +29,7 @@ properties:
- items:
- enum:
- qcom,eliza-epss-l3
+ - qcom,milos-epss-l3
- qcom,sa8775p-epss-l3
- qcom,sc7280-epss-l3
- qcom,sc8280xp-epss-l3
--
2.55.0
^ permalink raw reply related
* [PATCH v2 0/2] Add Milos CPU OPP table for DDR & L3 bandwidth scaling
From: Luca Weiss @ 2026-07-17 13:33 UTC (permalink / raw)
To: Georgi Djakov, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Sibi Sankar, Bjorn Andersson, Konrad Dybcio, Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm, linux-pm,
devicetree, linux-kernel, Luca Weiss, Krzysztof Kozlowski,
Konrad Dybcio
Add a node for the OSM L3 on the Milos SoC and define the CPU OPP tables
to scale DDR & L3 bandwidths when CPU cores change frequency.
Tested with 7zip benchmark ("7z b") and membw [0] showing very close
results compared to disabling .sync_state and thus keeping all
interconnect bandwidths on maximum vote.
[0] https://github.com/doug65536/membw
Unfortunately there's no support upstream yet to have different
opp-peak-kBps values depending on whether the device is running on DDR4
or DDR5 RAM, which is where Milos should use different DDR votes. For
now the DDR5 values are used which are (usually) higher, but should
hopefully not cause any issues on devices with DDR4. TODO comments are
placed where they differ.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Changes in v2:
- Squash the three dts patches into one, some patches along would result
in performance degradation.
- Pick up tags
- Link to v1: https://patch.msgid.link/20260710-milos-cpu-opp-v1-0-ae7f4b09bc77@fairphone.com
---
Luca Weiss (2):
dt-bindings: interconnect: OSM L3: Document Milos OSM L3 compatible
arm64: dts: qcom: milos: add CPU OPP table with DDR & L3 bandwidths
.../bindings/interconnect/qcom,osm-l3.yaml | 1 +
arch/arm64/boot/dts/qcom/milos.dtsi | 344 +++++++++++++++++++++
2 files changed, 345 insertions(+)
---
base-commit: 4c45e14df2f4e77982ad70d6d8e3fe750edd4c37
change-id: 20260710-milos-cpu-opp-26fb6c36be60
Best regards,
--
Luca Weiss <luca.weiss@fairphone.com>
^ permalink raw reply
* Re: [PATCH 1/3] regulator: core: use system_freezable_wq for init complete work
From: Mark Brown @ 2026-07-17 13:30 UTC (permalink / raw)
To: Joy Zou
Cc: Liam Girdwood, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Ye Li, Jacky Bai, Peng Fan, Dong Aisheng, linux-kernel,
devicetree, imx, linux-arm-kernel
In-Reply-To: <20260716-b4-regulator-pf01-v1-1-8c1519d54bd4@oss.nxp.com>
[-- Attachment #1: Type: text/plain, Size: 987 bytes --]
On Thu, Jul 16, 2026 at 11:50:53AM +0800, Joy Zou wrote:
> schedule_delayed_work() uses system_wq, which is non-freezable, allowing
> regulator_init_complete_work to run concurrently with system suspend. This
> work fires ~30s after boot to disable unused regulators via I2C. When it
> races with PM suspend, the I2C adapter may already be suspended, triggering
> a -ESHUTDOWN warning dump.
> [ 33.707233] pc : __i2c_transfer+0x36c/0x3c8
> [ 33.707240] lr : __i2c_transfer+0x36c/0x3c8
> [ 33.707246] sp : ffff80008239ba50
> [ 33.707249] x29: ffff80008239ba50 x28: 0000000000000001 x27: 0000000000000000
Please think hard before including complete backtraces in upstream
reports, they are very large and contain almost no useful information
relative to their size so often obscure the relevant content in your
message. If part of the backtrace is usefully illustrative (it often is
for search engines if nothing else) then it's usually better to pull out
the relevant sections.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* [PATCH v3 2/2] arm64: dts: qcom: Add Xiaomi 11 Lite 5G NE
From: Oleksii Onchul @ 2026-07-17 13:22 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
devicetree, linux-kernel, Oleksii Onchul, Konrad Dybcio
In-Reply-To: <20260717132218.27007-1-oleksiionchul@gmail.com>
Add initial support for the Xiaomi 11 Lite 5G NE, codenamed lisa.
The supported hardware includes regulators, UFS, USB, GPU, remote
processors, Wi-Fi, Bluetooth, touchscreen, flash LED, thermal sensors
and the hardware buttons.
Signed-off-by: Oleksii Onchul <oleksiionchul@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/sm7325-xiaomi-lisa.dts | 1108 +++++++++++++++++
2 files changed, 1109 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm7325-xiaomi-lisa.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index e05414290..c25ac4954 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -355,6 +355,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai-csot.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai-tianma.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-nothing-spacewar.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm7325-xiaomi-lisa.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7325-xiaomi-taoyao.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm7325-xiaomi-lisa.dts b/arch/arm64/boot/dts/qcom/sm7325-xiaomi-lisa.dts
new file mode 100644
index 000000000..28a19c96c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm7325-xiaomi-lisa.dts
@@ -0,0 +1,1108 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Jens Reidel <adrian@travitia.xyz>
+ * Copyright (c) 2026, Oleksii Onchul <oleksiionchul@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm8350b.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "sm7325.dtsi"
+#include "pm7325.dtsi"
+#include "pm8350b.dtsi" /* PM7325B */
+#include "pm8350c.dtsi" /* PM7350C */
+#include "pmk8350.dtsi" /* PMK7325 */
+
+/* The following reserved memory regions have different addresses or sizes */
+/delete-node/ &adsp_mem;
+/delete-node/ &adsp_rpc_remote_heap_mem;
+/delete-node/ &cdsp_mem;
+/delete-node/ &rmtfs_mem;
+
+/ {
+ model = "Xiaomi 11 Lite 5G NE";
+ compatible = "xiaomi,lisa", "qcom,sm7325";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &uart5;
+ serial1 = &uart7;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "serial0:115200n8";
+
+ framebuffer0: framebuffer {
+ compatible = "simple-framebuffer";
+ memory-region = <&framebuffer_mem>;
+ width = <1080>;
+ height = <2400>;
+ stride = <(1080 * 4)>;
+ format = "a8r8g8b8";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_default>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm7325-pmic-glink",
+ "qcom,qcm6490-pmic-glink",
+ "qcom,pmic-glink";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pmic_glink_sbu: endpoint {
+ remote-endpoint = <&fsa4480_sbu_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cdsp_secure_heap_mem: cdsp-secure-heap@81800000 {
+ reg = <0x0 0x81800000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ adsp_mem: adsp@86700000 {
+ reg = <0x0 0x86700000 0x0 0x4000000>;
+ no-map;
+ };
+
+ /* Mainline video_mem is downstream cvp_mem */
+ real_video_mem: video@8ad00000 {
+ reg = <0x0 0x8ad00000 0x0 0x500000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi@8b710000 {
+ reg = <0x0 0x8b710000 0x0 0xa000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@9c700000 {
+ reg = <0x0 0x9c700000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@9e500000 {
+ reg = <0x0 0x9e500000 0x0 0x800000>;
+ no-map;
+ };
+
+ ramoops@a9000000 {
+ compatible = "ramoops";
+ reg = <0x0 0xa9000000 0x0 0x200000>;
+ pmsg-size = <0x200000>;
+ ecc-size = <16>;
+ mem-type = <2>;
+ };
+
+ removed_mem: removed@c0000000 {
+ reg = <0x0 0xc0000000 0x0 0x5100000>;
+ no-map;
+ };
+
+ pil_trustedvm_mem: pil-trustedvm-region@d0800000 {
+ reg = <0x0 0xd0800000 0x0 0x76f7000>;
+ no-map;
+ };
+
+ qrtr_shmem: qrtr-shmem@d7ef7000 {
+ reg = <0x0 0xd7ef7000 0x0 0x9000>;
+ no-map;
+ };
+
+ neuron_block_0_mem: neuron-block@d7f00000 {
+ reg = <0x0 0xd7f00000 0x0 0x80000>;
+ no-map;
+ };
+
+ neuron_block_1_mem: neuron-block@d7f80000 {
+ reg = <0x0 0xd7f80000 0x0 0x80000>;
+ no-map;
+ };
+
+ framebuffer_mem: framebuffer@e1000000 {
+ reg = <0x0 0xe1000000 0x0 (1080 * 2400 * 4)>;
+ no-map;
+ };
+
+ rmtfs_mem: rmtfs@ef500000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0xef500000 0x0 0x280000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>,
+ <QCOM_SCM_VMID_NAV>;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ /* S2B is really ebi.lvl but it's there for supply map completeness sake. */
+ vreg_s2b_0p7: smpa3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s2b_0p7";
+
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <700000>;
+ regulator-always-on;
+ vin-supply = <&vph_pwr>;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm7325-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+
+ vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p952>;
+ vdd-l2-l7-supply = <&vreg_bob>;
+ vdd-l3-supply = <&vreg_s2b_0p7>;
+ vdd-l5-supply = <&vreg_s2b_0p7>;
+ vdd-l6-l9-l10-supply = <&vreg_s8b_1p256>;
+ vdd-l8-supply = <&vreg_s7b_0p952>;
+ vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p856>;
+ vdd-l13-supply = <&vreg_s7b_0p952>;
+ vdd-l14-l16-supply = <&vreg_s8b_1p256>;
+
+ /*
+ * S2, L4-L5 are ARCs:
+ * S2 - ebi.lvl,
+ * L4 - lmx.lvl,
+ * l5 - lcx.lvl.
+ *
+ * L10 are unused.
+ */
+
+ vdd19_pmu_rfa_i:
+ vreg_s1b_1p856: smps1 {
+ regulator-name = "vreg_s1b_1p856";
+ regulator-min-microvolt = <1840000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_s7b_0p952: smps7 {
+ regulator-name = "vreg_s7b_0p952";
+ regulator-min-microvolt = <535000>;
+ regulator-max-microvolt = <1120000>;
+ };
+
+ vdd13_pmu_rfa_i:
+ vreg_s8b_1p256: smps8 {
+ regulator-name = "vreg_s8b_1p256";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
+ };
+
+ vreg_l1b_0p912: ldo1 {
+ regulator-name = "vreg_l1b_0p912";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <925000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_a_usbhs_3p1:
+ vreg_l2b_3p072: ldo2 {
+ regulator-name = "vreg_l2b_3p072";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3b_0p6: ldo3 {
+ regulator-name = "vreg_l3b_0p6";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <910000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_a_dsi_0_1p2:
+ vdd_a_ufs_0_1p2:
+ vreg_l6b_1p2: ldo6 {
+ regulator-name = "vreg_l6b_1p2";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_2p96: ldo7 {
+ regulator-name = "vreg_l7b_2p96";
+ /* Constrained for UFS VCC, at least until UFS driver scales voltage */
+ regulator-min-microvolt = <2952000>;
+ regulator-max-microvolt = <2952000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_0p904: ldo8 {
+ regulator-name = "vreg_l8b_0p904";
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_1p2: ldo9 {
+ regulator-name = "vreg_l9b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p776: ldo11 {
+ regulator-name = "vreg_l11b_1p776";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_0p8: ldo12 {
+ regulator-name = "vreg_l12b_0p8";
+ regulator-min-microvolt = <751000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_0p8: ldo13 {
+ regulator-name = "vreg_l13b_0p8";
+ regulator-min-microvolt = <530000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_1p2: ldo14 {
+ regulator-name = "vreg_l14b_1p2";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_0p88: ldo15 {
+ regulator-name = "vreg_l15b_0p88";
+ regulator-min-microvolt = <765000>;
+ regulator-max-microvolt = <1020000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_1p2: ldo16 {
+ regulator-name = "vreg_l16b_1p2";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_1p8: ldo17 {
+ regulator-name = "vreg_l17b_1p8";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b_1p8: ldo18 {
+ regulator-name = "vreg_l18b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l19b_1p8: ldo19 {
+ regulator-name = "vreg_l19b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8350c-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l12-supply = <&vreg_s1b_1p856>;
+ vdd-l2-l8-supply = <&vreg_s1b_1p856>;
+ vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
+ vdd-l6-l9-l11-supply = <&vreg_bob>;
+ vdd-l10-supply = <&vreg_s7b_0p952>;
+
+ vdd-bob-supply = <&vph_pwr>;
+
+ /*
+ * S2, S5, S7, S10 are ARCs:
+ * S2 - cx.lvl,
+ * S5 - mss.lvl,
+ * S7 - gfx.lvl,
+ * S10 - mx.lvl.
+ */
+
+ vreg_s1c_2p2: smps1 {
+ regulator-name = "vreg_s1c_2p2";
+ regulator-min-microvolt = <2190000>;
+ regulator-max-microvolt = <2210000>;
+ };
+
+ vreg_s9c_0p676: smps9 {
+ regulator-name = "vreg_s9c_0p676";
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1170000>;
+ };
+
+ vdd_a_usbhs_1p8:
+ vdd_qfprom:
+ vreg_l1c_1p8: ldo1 {
+ regulator-name = "vreg_l1c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_1p8: ldo2 {
+ regulator-name = "vreg_l2c_1p8";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c_1p8_3p0: ldo4 {
+ regulator-name = "vreg_l4c_1p8_3p0";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5c_1p8_3p0: ldo5 {
+ regulator-name = "vreg_l5c_1p8_3p0";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p96: ldo6 {
+ regulator-name = "vreg_l6c_2p96";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-name = "vreg_l7c_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-name = "vreg_l8c_1p8";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-always-on;
+ };
+
+ vreg_l9c_2p96: ldo9 {
+ regulator-name = "vreg_l9c_2p96";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_a_dsi_0_0p9:
+ vdd_a_dsi_0_pll_0p9:
+ vdd_a_ufs_0_core:
+ vdd_a_usbhs_core:
+ vreg_l10c_0p88: ldo10 {
+ regulator-name = "vreg_l10c_0p88";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_2p8: ldo11 {
+ regulator-name = "vreg_l11c_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12c_1p8: ldo12 {
+ regulator-name = "vreg_l12c_1p8";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13c_3p0: ldo13 {
+ regulator-name = "vreg_l13c_3p0";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_flash:
+ vdd_iris_rgb:
+ vdd_mic_bias:
+ vreg_bob: bob {
+ regulator-name = "vreg_bob";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+};
+
+&gcc {
+ protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
+ <GCC_MSS_CFG_AHB_CLK>,
+ <GCC_MSS_OFFLINE_AXI_CLK>,
+ <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
+ <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+ <GCC_MSS_SNOC_AXI_CLK>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_SEC_CTRL_CLK_SRC>,
+ <GCC_WPSS_AHB_BDG_MST_CLK>,
+ <GCC_WPSS_AHB_CLK>,
+ <GCC_WPSS_RSCP_CLK>;
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/sm7325/xiaomi/lisa/a660_zap.mbn";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+
+ pm8008: pmic@8 {
+ compatible = "qcom,pm8008";
+ reg = <0x8>;
+
+ interrupts-extended = <&tlmm 25 IRQ_TYPE_EDGE_RISING>;
+ reset-gpios = <&pm8350c_gpios 3 GPIO_ACTIVE_LOW>;
+
+ vdd-l1-l2-supply = <&vreg_s8b_1p256>;
+ vdd-l3-l4-supply = <&vreg_bob>;
+ vdd-l5-supply = <&vreg_s1b_1p856>;
+ vdd-l6-supply = <&vreg_bob>;
+ vdd-l7-supply = <&vreg_bob>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm8008_int_default>, <&pm8008_reset_n_default>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8008 0 0 2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ #thermal-sensor-cells = <0>;
+
+ regulators {
+ vreg_l1p: ldo1 {
+ regulator-name = "vreg_l1p";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l2p: ldo2 {
+ regulator-name = "vreg_l2p";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_l3p: ldo3 {
+ regulator-name = "vreg_l3p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vreg_l4p: ldo4 {
+ regulator-name = "vreg_l4p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vreg_l5p: ldo5 {
+ regulator-name = "vreg_l5p";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ };
+
+ vreg_l6p: ldo6 {
+ regulator-name = "vreg_l6p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ vreg_l7p: ldo7 {
+ regulator-name = "vreg_l7p";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ };
+ };
+
+ fsa4480: typec-mux@42 {
+ compatible = "fcs,fsa4480";
+ reg = <0x42>;
+
+ vcc-supply = <&vreg_bob>;
+ mode-switch;
+ orientation-switch;
+
+ port {
+ fsa4480_sbu_mux: endpoint {
+ remote-endpoint = <&pmic_glink_sbu>;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+
+ /* awinic,aw8624_haptic @ 5a */
+};
+
+&ipa {
+ firmware-name = "qcom/sm7325/xiaomi/lisa/ipa_fws.mbn";
+
+ status = "okay";
+};
+
+&pm7325_gpios {
+ volume_up_default: volume-up-default-state {
+ pins = "gpio6";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <1>;
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&pm8350c_gpios {
+ pm8008_reset_n_default: pm8008-reset-n-default-state {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ bias-pull-down;
+ };
+};
+
+&pm8350c_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <1>, <4>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <1280000>;
+ };
+};
+
+&pmk8350_adc_tm {
+ status = "okay";
+
+ /* PMK8350 */
+ xo-therm@0 {
+ reg = <0>;
+ io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ /* PM7325 */
+ quiet-therm@1 {
+ reg = <1>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ cam-flash-therm@2 {
+ reg = <2>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ sdm-skin-therm@3 {
+ reg = <3>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ wide-rfc-therm@4 {
+ reg = <4>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ 5g-pa-therm@5 {
+ reg = <5>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM5_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ 4g-pa-therm@6 {
+ reg = <6>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ /* PM8350B */
+ chg-skin-therm@7 {
+ reg = <7>;
+ io-channels = <&pmk8350_vadc PM8350B_ADC7_GPIO2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
+&pmk8350_rtc {
+ status = "okay";
+};
+
+&pmk8350_vadc {
+ /* PMK8350 */
+ channel@44 {
+ reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pmk8350_xo_therm";
+ };
+
+ /* PM7325 */
+ channel@144 {
+ reg = <PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_quiet_therm";
+ };
+
+ channel@145 {
+ reg = <PM7325_ADC7_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_cam_flash_therm";
+ };
+
+ channel@146 {
+ reg = <PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_sdm_skin_therm";
+ };
+
+ channel@147 {
+ reg = <PM7325_ADC7_AMUX_THM4_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_wide_rfc_therm";
+ };
+
+ channel@148 {
+ reg = <PM7325_ADC7_AMUX_THM5_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_5g_pa_therm";
+ };
+
+ channel@14c {
+ reg = <PM7325_ADC7_GPIO3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_4g_pa_therm";
+ };
+
+ /* PM8350B */
+ channel@34b {
+ reg = <PM8350B_ADC7_GPIO2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm8350b_chg_skin_therm";
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&qfprom {
+ vcc-supply = <&vdd_qfprom>;
+};
+
+&qup_spi13_cs {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&qup_spi13_data_clk {
+ drive-strength = <6>;
+ bias-disable;
+};
+
+&qup_uart5_rx {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart5_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm7325/xiaomi/lisa/adsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm7325/xiaomi/lisa/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/sm7325/xiaomi/lisa/modem.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_wpss {
+ firmware-name = "qcom/sm7325/xiaomi/lisa/wpss.mbn";
+
+ status = "okay";
+};
+
+&spi13 {
+ status = "okay";
+
+ touchscreen@0 {
+ compatible = "goodix,gt9897";
+ reg = <0>;
+ spi-max-frequency = <6000000>;
+
+ interrupts-extended = <&tlmm 81 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&tlmm 105 GPIO_ACTIVE_LOW>;
+
+ avdd-supply = <&vreg_l7c_3p0>;
+ vddio-supply = <&vreg_l2c_1p8>;
+
+ pinctrl-0 = <&touchscreen_default>;
+ pinctrl-names = "default";
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <2400>;
+ };
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 2>, /* SMB1394 (SPMI) */
+ <48 4>, /* Presumably NFC SE */
+ <56 4>; /* Presumably fingerprint reader */
+
+ qup_uart7_sleep_cts: qup-uart7-sleep-cts-state {
+ pins = "gpio28";
+ function = "gpio";
+ /*
+ * Configure a bias-bus-hold on CTS to lower power
+ * usage when Bluetooth is turned off. Bus hold will
+ * maintain a low power state regardless of whether
+ * the Bluetooth module drives the pin in either
+ * direction or leaves the pin fully unpowered.
+ */
+ bias-bus-hold;
+ };
+
+ qup_uart7_sleep_rts: qup-uart7-sleep-rts-state {
+ pins = "gpio29";
+ function = "gpio";
+ /*
+ * Configure pull-down on RTS. As RTS is active low
+ * signal, pull it low to indicate the BT SoC that it
+ * can wakeup the system anytime from suspend state by
+ * pulling RX low (by sending wakeup bytes).
+ */
+ bias-pull-down;
+ };
+
+ qup_uart7_sleep_tx: qup-uart7-sleep-tx-state {
+ pins = "gpio30";
+ function = "gpio";
+ /*
+ * Configure pull-up on TX when it isn't actively driven
+ * to prevent BT SoC from receiving garbage during sleep.
+ */
+ bias-pull-up;
+ };
+
+ qup_uart7_sleep_rx: qup-uart7-sleep-rx-state {
+ pins = "gpio31";
+ function = "gpio";
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module
+ * is floating which may cause spurious wakeups.
+ */
+ bias-pull-up;
+ };
+
+ bluetooth_enable_default: bluetooth-enable-default-state {
+ pins = "gpio85";
+ function = "gpio";
+ output-low;
+ bias-disable;
+ };
+
+ sw_ctrl_default: sw-ctrl-default-state {
+ pins = "gpio86";
+ function = "gpio";
+ bias-pull-down;
+ };
+
+ touchscreen_default: touchscreen-default-state {
+ pins = "gpio81", "gpio105";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ pm8008_int_default: pm8008-int-default-state {
+ pins = "gpio25";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&uart5 {
+ compatible = "qcom,geni-debug-uart";
+
+ status = "okay";
+};
+
+&uart7 {
+ /delete-property/interrupts;
+ interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-1 = <&qup_uart7_sleep_cts>,
+ <&qup_uart7_sleep_rts>,
+ <&qup_uart7_sleep_tx>,
+ <&qup_uart7_sleep_rx>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+
+ bluetooth: bluetooth {
+ compatible = "qcom,wcn6750-bt";
+
+ pinctrl-0 = <&bluetooth_enable_default>, <&sw_ctrl_default>;
+ pinctrl-names = "default";
+
+ enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
+ swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>;
+
+ vddio-supply = <&vreg_l19b_1p8>;
+ vddaon-supply = <&vreg_s7b_0p952>;
+ vddbtcxmx-supply = <&vreg_s7b_0p952>;
+ vddrfacmn-supply = <&vreg_s7b_0p952>;
+ vddrfa0p8-supply = <&vreg_s7b_0p952>;
+ vddrfa1p2-supply = <&vdd13_pmu_rfa_i>;
+ vddrfa1p7-supply = <&vdd19_pmu_rfa_i>;
+ vddrfa2p2-supply = <&vreg_s1c_2p2>;
+ vddasd-supply = <&vreg_l11c_2p8>;
+ max-speed = <3200000>;
+
+ qcom,local-bd-address-broken;
+ };
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l7b_2p96>;
+ vcc-max-microamp = <800000>;
+ /*
+ * Technically l9b enables an eLDO (supplied by s1b) which then powers
+ * VCCQ2 of the UFS.
+ */
+ vccq-supply = <&vreg_l9b_1p2>;
+ vccq-max-microamp = <900000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vdd_a_ufs_0_core>;
+ vdda-pll-supply = <&vdd_a_ufs_0_1p2>;
+
+ status = "okay";
+};
+
+&usb_1 {
+ qcom,select-utmi-as-pipe-clk;
+
+ maximum-speed = "high-speed";
+ phys = <&usb_1_hsphy>;
+ phy-names = "usb2-phy";
+
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&vdd_a_usbhs_core>;
+ vdda18-supply = <&vdd_a_usbhs_1p8>;
+ vdda33-supply = <&vdd_a_usbhs_3p1>;
+
+ status = "okay";
+};
+
+&venus {
+ firmware-name = "qcom/sm7325/xiaomi/lisa/vpu20_1v.mbn";
+
+ status = "okay";
+};
+
+&wifi {
+ status = "okay";
+};
--
2.55.0
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