* Re: [PATCH v2 1/1] dt-bindings: soc: imx-iomuxc-gpr: allow bridge@18 as child node
From: Frank Li @ 2026-07-18 14:12 UTC (permalink / raw)
To: Rob Herring (Arm)
Cc: Fabio Estevam, imx, linux-arm-kernel, Pengutronix Kernel Team,
Conor Dooley, Frank Li, linux-kernel, Krzysztof Kozlowski,
Sascha Hauer, Peng Fan, devicetree, Shawn Guo
In-Reply-To: <178432353778.2692844.15138095566024676604.robh@kernel.org>
On Fri, Jul 17, 2026 at 04:25:37PM -0500, Rob Herring (Arm) wrote:
>
> On Fri, 17 Jul 2026 16:15:17 -0400, Frank.Li@oss.nxp.com wrote:
> > From: Frank Li <Frank.Li@nxp.com>
> >
> > The legacy i.MX6SX (>15 year) SoC imx-iomuxc-gpr contains one LDB_CTRL
> > register. Allow the LVDS Display Bridge(LDB) child node under
> > imx-iomuxc-gpr.
> >
> > Fix below CHECK_DTBS warnings:
> > arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dtb: syscon@20e4000 (fsl,imx6sx-iomuxc-gpr): '#address-cells', '#size-cells', 'bridge@18' do not match any of the regexes: '^ipu[12]_csi[01]_mux$', '^pinctrl-[0-9]+$
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > change in v2
> > - remove status = "disabled" at example
> > ---
> > .../bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml | 58 +++++++++++++++++++
> > 1 file changed, 58 insertions(+)
> >
>
> My bot found errors running 'make dt_binding_check' on your patch:
I forget it is posted with other binding patch. please forget this one.
I will repost with whole serial.
Frank
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.example.dtb: syscon@20e4000 (fsl,imx6sx-iomuxc-gpr): bridge@18:reg: [[24, 4]] is too short
> from schema $id: http://devicetree.org/schemas/soc/imx/fsl,imx-iomuxc-gpr.yaml
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.example.dtb: bridge@18 (fsl,imx6sx-ldb): reg: [[24, 4]] is too short
> from schema $id: http://devicetree.org/schemas/display/bridge/fsl,ldb.yaml
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.kernel.org/project/devicetree/patch/20260717201519.844259-1-Frank.Li@oss.nxp.com
>
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
>
^ permalink raw reply
* Re: [PATCH v4 2/2] iio: adc: add Axiado SARADC driver
From: Uwe Kleine-König @ 2026-07-18 13:51 UTC (permalink / raw)
To: Petar Stepanovic
Cc: Akhila Kavi, Prasad Bolisetty, Jonathan Cameron, David Lechner,
Nuno Sá, Andy Shevchenko, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Harshit Shah, linux-iio, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260716-axiado-ax3000-ax3005-saradc-v4-2-810527a9d27f@axiado.com>
[-- Attachment #1: Type: text/plain, Size: 333 bytes --]
Hello,
On Thu, Jul 16, 2026 at 10:53:02PM -0700, Petar Stepanovic wrote:
> +#include <linux/mod_devicetable.h>
> [...]
> +#include <linux/platform_device.h>
Please don't explicitly include <linux/mod_devicetable.h>. I'm working
on removing that header and <linux/platform_device.h> already provides
of_device_id.
Best regards
Uwe
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH v2 2/2] mmc: core: Add MMC_CAP2_NO_SLEEP_CMD host capability
From: Ulf Hansson @ 2026-07-18 13:51 UTC (permalink / raw)
To: Kamal Dasu
Cc: Ulf Hansson, Florian Fainelli, Wolfram Sang, Oleksij Rempel,
Avri Altman, Pedro Demarchi Gomes, Erick Shepherd, Adrian Hunter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-mmc,
devicetree, linux-kernel
In-Reply-To: <20260717180536.1757204-3-kamal.dasu@broadcom.com>
On Fri, Jul 17, 2026 at 8:06 PM Kamal Dasu <kamal.dasu@broadcom.com> wrote:
>
> Some (e)MMC devices take longer to exit the SLEEP (CMD5) state than
> their advertised S_A_TIMEOUT allows for. On platforms where a boot
> ROM sends CMD0 and reads boot code from the card immediately on
> resume, a card still asleep at that point causes the ROM to treat
> it as fatal and reset.
>
> Add MMC_CAP2_NO_SLEEP_CMD, settable via the new "no-mmc-sleep" DT
> property, so affected hosts can tell mmc_card_can_sleep() to never
> put the card to sleep, regardless of ext_csd revision. This is a
> host-level capability rather than a card quirk so it also covers
> cards whose bug can't be identified by CID/ext_csd matching alone,
> and it is resolved before the card even exists, avoiding any
> ordering dependency on when a card-quirk table would be applied.
>
> Reported-by: Florian Fainelli <florian.fainelli@broadcom.com>
> Closes: https://lore.kernel.org/r/20260413180551.3683969-1-florian.fainelli@broadcom.com/
> Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
> ---
> Changes in v2:
> - Replaced the card-level MMC_QUIRK_BROKEN_SLEEP quirk (keyed off
> CID) with a host capability, MMC_CAP2_NO_SLEEP_CMD, set from the
> new "no-mmc-sleep" DT property, per Ulf's suggestion that this
> generalize beyond one device's CID.
> - Resolving the capability in mmc_of_parse(), before any card
> exists, also addresses Oleksij's concern that a quirk registered
> in mmc_blk_fixups[] (applied at mmc_block probe time) could lose
> a race against an earlier SLEEP/poweroff on an under-voltage
> path.
> - Added Reported-by/Closes tags crediting Florian for the original
> bug report.
>
> drivers/mmc/core/host.c | 2 ++
> drivers/mmc/core/mmc.c | 3 +++
> include/linux/mmc/host.h | 1 +
> 3 files changed, 6 insertions(+)
>
> diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
> index b7ce3137d452..3bc19645ea96 100644
> --- a/drivers/mmc/core/host.c
> +++ b/drivers/mmc/core/host.c
> @@ -400,6 +400,8 @@ int mmc_of_parse(struct mmc_host *host)
> if (device_property_read_bool(dev, "no-mmc-hs400"))
> host->caps2 &= ~(MMC_CAP2_HS400_1_8V | MMC_CAP2_HS400_1_2V |
> MMC_CAP2_HS400_ES);
> + if (device_property_read_bool(dev, "no-mmc-sleep"))
> + host->caps2 |= MMC_CAP2_NO_SLEEP_CMD;
>
> /* Must be after "non-removable" check */
> if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) {
> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
> index 05444ecf3909..5e80fa5c1a28 100644
> --- a/drivers/mmc/core/mmc.c
> +++ b/drivers/mmc/core/mmc.c
> @@ -1972,6 +1972,9 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
>
> static bool mmc_card_can_sleep(struct mmc_card *card)
> {
> + if (card->host->caps2 & MMC_CAP2_NO_SLEEP_CMD)
> + return false;
> +
No.
As I said several times by now, we should not just skip the sleep
command, but rather always keep the card powered on.
So, instead I suggest we look at adjusting the code in _mmc_suspend()
to cope with this.
> return card->ext_csd.rev >= 3;
> }
>
> diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
> index ba84f02c2a10..0447a8efed50 100644
> --- a/include/linux/mmc/host.h
> +++ b/include/linux/mmc/host.h
> @@ -463,6 +463,7 @@ struct mmc_host {
> #define MMC_CAP2_CRYPTO 0
> #endif
> #define MMC_CAP2_ALT_GPT_TEGRA (1 << 28) /* Host with eMMC that has GPT entry at a non-standard location */
> +#define MMC_CAP2_NO_SLEEP_CMD (1 << 29) /* Card can't reliably wake from CMD5 SLEEP */
>
> bool uhs2_sd_tran; /* UHS-II flag for SD_TRAN state */
> bool uhs2_app_cmd; /* UHS-II flag for APP command */
> --
> 2.34.1
>
Kind regards
Uffe
^ permalink raw reply
* Re: [PATCH v21 01/12] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC
From: sashiko-bot @ 2026-07-18 13:48 UTC (permalink / raw)
To: Biju; +Cc: conor+dt, robh, devicetree, wsa+renesas
In-Reply-To: <20260718133838.152905-2-biju.das.jz@bp.renesas.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The patch adds `reset-names` globally with `maxItems: 3` but fails to disable it for the `renesas,sdhi-r9a09g077` and `renesas,sdhi-r9a09g087` compatibles, erroneously allowing them to specify reset names despite having resets explicitly disabled.
--
--- Patch [1]: [PATCH v21 01/12] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC ---
commit ded5b3c418cd0dba150466076b0e30dd19fd0243
Author: Biju Das <biju.das.jz@bp.renesas.com>
dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC
Document the RZ/G3L (r9a08g046) SDHI controller. The RZ/G3L SDHI
controller is similar to RZ/G2L but has five clocks (core, clkh,
cd, aclkm, aclks) and three resets (rst, axim, axis), so update the
clocks/clock-names maximum to 5 and resets/reset-names maximum to 3.
> diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> index 4d66966ce2900..6d229a41a4b56 100644
> --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
[ ... ]
> @@ -116,7 +117,12 @@ properties:
> maxItems: 1
>
> resets:
> - maxItems: 1
> + minItems: 1
> + maxItems: 3
> +
> + reset-names:
> + minItems: 1
> + maxItems: 3
[Severity: Low]
Does adding reset-names globally allow it to be specified for the
renesas,sdhi-r9a09g077 and renesas,sdhi-r9a09g087 compatibles?
The existing schema has an allOf conditional block for these compatibles that
explicitly disables resets:
- if:
properties:
compatible:
contains:
enum:
- renesas,sdhi-r9a09g077
- renesas,sdhi-r9a09g087
then:
properties:
resets: false
Since resets are disabled for those hardware variants, shouldn't
reset-names: false also be added to that block to prevent a spurious
reset-names property from passing validation?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260718133838.152905-1-biju.das.jz@bp.renesas.com?part=1
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: mmc: Document no-mmc-sleep property
From: Ulf Hansson @ 2026-07-18 13:44 UTC (permalink / raw)
To: Kamal Dasu
Cc: Ulf Hansson, Florian Fainelli, Wolfram Sang, Oleksij Rempel,
Avri Altman, Pedro Demarchi Gomes, Erick Shepherd, Adrian Hunter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-mmc,
devicetree, linux-kernel
In-Reply-To: <20260717180536.1757204-2-kamal.dasu@broadcom.com>
On Fri, Jul 17, 2026 at 8:06 PM Kamal Dasu <kamal.dasu@broadcom.com> wrote:
>
> Some (e)MMC devices cannot reliably resume from the SLEEP (CMD5)
> state within their advertised S_A_TIMEOUT, which can be problematic
> on systems that resume from Suspend-to-DRAM by first pulling boot
> code from eMMC using hard wired logic that is not field updatable.
> Add a no-mmc-sleep flag property so affected boards can tell the
> mmc core to never put the card to sleep.
Please clarify what the FW is doing in the commit message so we can
better understand what is needed. Along the lines of the below.
Moreover, as stated for the cover letter; this is rather about keeping
the card powered on during system suspend, because of the behaviour in
the FW.
Moreover, because of the behaviour in the FW, the kernel still needs
to re-initialize the card at system resume.
In regards to the card advertising a wrong S_A_TIMEOUT, that is a
completely separate issue. If you want to fix that, we can for sure
use a card quirk - although that quirk should only override the sleep
timeout value that we use in the kernel - and not prevent the sleep
command.
>
> Signed-off-by: Kamal Dasu <kamal.dasu@broadcom.com>
> ---
> Changes in v2:
> - New patch. v1 used a card-level MMC_QUIRK_BROKEN_SLEEP quirk
> instead of a DT property; this documents the DT property backing
> the host capability added in patch 2, per Ulf's suggestion.
> - Reworded the rationale in the commit message and the binding
> description per Florian's review.
>
> .../devicetree/bindings/mmc/mmc-controller-common.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
> index 3d7195e9461c..11df0524530c 100644
> --- a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
> @@ -232,6 +232,14 @@ properties:
> description:
> All eMMC HS400 modes are not supported.
>
> + no-mmc-sleep:
This is a misleading name, please try to find a better one.
The property should say "because of FW, we need to keep power in
suspend but re-initialize it at resume".
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + The attached (e)MMC card cannot reliably resume from the SLEEP
> + (CMD5) state within its advertised S_A_TIMEOUT, so the
> + controller must not put it to sleep during suspend or power
> + off.
> +
Please rephrase this, along the lines of what I suggested above.
> dsr:
> description:
> Value the card Driver Stage Register (DSR) should be programmed
> --
> 2.34.1
>
Kind regards
Uffe
^ permalink raw reply
* [PATCH v21 01/12] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC
From: Biju @ 2026-07-18 13:38 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, Wolfram Sang, linux-mmc, devicetree, linux-kernel,
linux-renesas-soc, Prabhakar Mahadev Lad, Biju Das, Conor Dooley
In-Reply-To: <20260718133838.152905-1-biju.das.jz@bp.renesas.com>
From: Biju Das <biju.das.jz@bp.renesas.com>
Document the RZ/G3L (r9a08g046) SDHI controller. The RZ/G3L SDHI
controller is similar to RZ/G2L but has five clocks (core, clkh,
cd, aclkm, aclks) and three resets (rst, axim, axis), so update the
clocks/clock-names maximum to 5 and resets/reset-names maximum to 3.
It has an internal divider for all modes except HS400, and a 2048-bit
divider compared to 512 on others.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v20->v21:
* No change.
v19->v20:
* No change.
v18->v19:
* Updated commit description
* Updated clock and reset description with AXI master and AXI slave
* Added else condition for reset and reset-names.
* Renamed aclk->aclkm and reordered the axi clocks similar to resets.
* Retained the tag as the changes are trivial.
v17->v18:
* No change.
v1->v17:
* Collected tag.
---
.../devicetree/bindings/mmc/renesas,sdhi.yaml | 108 +++++++++++++-----
1 file changed, 81 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 4d66966ce290..6d229a41a4b5 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -18,6 +18,7 @@ properties:
- renesas,sdhi-r7s9210 # SH-Mobile AG5
- renesas,sdhi-r8a73a4 # R-Mobile APE6
- renesas,sdhi-r8a7740 # R-Mobile A1
+ - renesas,sdhi-r9a08g046 # RZ/G3L
- renesas,sdhi-r9a09g057 # RZ/V2H(P)
- renesas,sdhi-sh73a0 # R-Mobile APE6
- items:
@@ -86,11 +87,11 @@ properties:
clocks:
minItems: 1
- maxItems: 4
+ maxItems: 5
clock-names:
minItems: 1
- maxItems: 4
+ maxItems: 5
dmas:
minItems: 4
@@ -116,7 +117,12 @@ properties:
maxItems: 1
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 3
+
+ reset-names:
+ minItems: 1
+ maxItems: 3
pinctrl-0:
minItems: 1
@@ -155,60 +161,106 @@ allOf:
properties:
compatible:
contains:
- enum:
- - renesas,sdhi-r9a09g057
- - renesas,rzg2l-sdhi
+ const: renesas,sdhi-r9a08g046
then:
properties:
clocks:
items:
- description: IMCLK, SDHI channel main clock1.
- description: CLK_HS, SDHI channel High speed clock which operates
- 4 times that of SDHI channel main clock1.
+ 2 times that of SDHI channel main clock1.
- description: IMCLK2, SDHI channel main clock2. When this clock is
turned off, external SD card detection cannot be
detected.
- - description: ACLK, SDHI channel bus clock.
+ - description: IACLKM, SDHI channel AXI master bus clock.
+ - description: IACLKS, SDHI channel AXI slave bus clock.
clock-names:
items:
- const: core
- const: clkh
- const: cd
- - const: aclk
+ - const: aclkm
+ - const: aclks
+ resets:
+ items:
+ - description: rst, Core reset.
+ - description: axim, SDHI channel AXI master bus reset.
+ - description: axis, SDHI channel AXI slave bus reset.
+ reset-names:
+ items:
+ - const: rst
+ - const: axim
+ - const: axis
required:
- clock-names
- resets
+ - reset-names
else:
+ properties:
+ resets:
+ maxItems: 1
+ reset-names:
+ maxItems: 1
if:
properties:
compatible:
contains:
enum:
- - renesas,rcar-gen2-sdhi
- - renesas,rcar-gen3-sdhi
- - renesas,rcar-gen4-sdhi
+ - renesas,sdhi-r9a09g057
+ - renesas,rzg2l-sdhi
then:
properties:
clocks:
- minItems: 1
- maxItems: 3
- clock-names:
- minItems: 1
- uniqueItems: true
items:
- - const: core
- - enum: [ clkh, cd ]
- - const: cd
- else:
- properties:
- clocks:
- minItems: 1
- maxItems: 2
+ - description: IMCLK, SDHI channel main clock1.
+ - description: CLK_HS, SDHI channel High speed clock which operates
+ 4 times that of SDHI channel main clock1.
+ - description: IMCLK2, SDHI channel main clock2. When this clock is
+ turned off, external SD card detection cannot be
+ detected.
+ - description: ACLK, SDHI channel bus clock.
clock-names:
- minItems: 1
items:
- const: core
+ - const: clkh
- const: cd
+ - const: aclk
+ resets:
+ maxItems: 1
+ required:
+ - clock-names
+ - resets
+ else:
+ if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen2-sdhi
+ - renesas,rcar-gen3-sdhi
+ - renesas,rcar-gen4-sdhi
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 3
+ clock-names:
+ minItems: 1
+ uniqueItems: true
+ items:
+ - const: core
+ - enum: [ clkh, cd ]
+ - const: cd
+ else:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 2
+ clock-names:
+ minItems: 1
+ items:
+ - const: core
+ - const: cd
- if:
properties:
@@ -247,7 +299,9 @@ allOf:
properties:
compatible:
contains:
- const: renesas,sdhi-r9a09g057
+ enum:
+ - renesas,sdhi-r9a08g046
+ - renesas,sdhi-r9a09g057
then:
properties:
vqmmc-regulator:
--
2.43.0
^ permalink raw reply related
* [PATCH v21 00/12] Add Renesas RZ/G3L SD/eMMC support
From: Biju @ 2026-07-18 13:38 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Philipp Zabel, Magnus Damm
Cc: Biju Das, Wolfram Sang, linux-mmc, devicetree, linux-kernel,
linux-renesas-soc, Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Hi All,
RZ/G3L SoC has:
Channel 0 supports SD and eMMC (including HS400/HS400ES).
Channel 1 supports SD and eMMC (except for HS400).
Channel 2 supports SD.
The SoC supports a maximum frequency of 150 MHz. The SD0 interface does
not support IOVS and PWEN in the SDHI register (no internal regulator),
unlike SD1 and SD2. It has an internal divider for all modes except HS400.
It also has a 2048-bit divider compared to 512 on others. Moreover
RZ/G3L supports HS400 enhanced strobe mode.
This patch series support all Modes except HS400 ES mode.
Please see the test logs[1]
v20->v21:
* Dropped HS400 ES support due to file system corruption, will add this
mode later after investigation.
* Added support for make clock divider mask configurable
* Added clk_div_mask to RZ/G2L of_data.
* Added clk_div_mask to RZ/G3L of_data.
* Restored actual_clk calculation in renesas_sdhi_set_clock().
* Updated renesas_sdhi_set_clock() for RZ/G3L HS400 clock handling as
it supports only single clk divider value and other values are
prohibited.
* Updated commit description for patch#12.
v19->v20:
* Replaced the check mmd->clk_mask with mmc_data->clk_mask and moved
the code after assignment of variable mmd, this ensures assigning
the default values for non-DT platforms and DT platforms with no
device data.
* Replaced the check mmd->max_divider with mmc_data->max_divider and
moved the code after assignment of variable mmd, this ensures
assigning the default values for non-DT platforms and DT platforms with
no device data.
* Fixed the ordering of resets in suspend/resume paths.
* Added bitfield.h header file.
* Reworked on renesas_sdhi_set_clock() to handle the 11-bit divider
case and the 32-bit register write.
* Updated resume() with scoped PM runtime call.
* SD_CLK_CTRL clk enable turned off before updating SCC_CKSEL_DTSEL
register.
v18->v19:
* Updated commit description for patch#1,#2,#6,#8,#11 and #12
* Updated clock and reset description with AXI master and AXI slave
* Added else condition for reset and reset-names.
* Renamed aclk->aclkm and reordered the axi clocks similar to resets.
* Retained the tag got binding patch as the changes are trivial.
* Fixed the clk_mask for non-DT platforms.
* Fixed max-divider setting for non-DT platforms.
* Replaced the magic number '9' with ilog2 function in
renesas_sdhi_clk_enable().
* Dropped divider variable from struct renesas_sdhi.
* Updated renesas_sdhi_clk_update() to return rate for HS400 mode
and non HS400 mode(uses 1/2 internal divider).
* Updated handling for clk divider.
* Renamed TMIO_MMC_HWADJ2->TMIO_MMC_HWADJ to make it generic for
hardware tuning delays
* Dropped duplicate SH_MOBILE_SDHI_SCC_TMPPORT2 macro
* Updated suspend/resume with scoped runtime calls in suspend.
* Fixed extra space in HS400MODE2 comment block.
* Updated the comment HS400mode2->HS400MODE2.
* Dropped the updation of clk handling as it is taken care in
previous patches.
* HS400ES support is enabled based on of_data.
* Fixed the space in HS400ES comment block.
v17->v18:
* Collected tag
* Merged patch #4 and #5 and updated commit description
* Annotated the empty sentinel entries in the OF match tables with a
"Sentinel." comment for clarity.
* Retained the tag as it is a trivial cleanup.
* New patches drop struct renesas_sdhi_hw_info, instead using
renesas_sdhi_of_data and tmio_mmc_data.
* Dropped clk, pinctrl, SoC, and board dtsi from this patch series;
will send later.
v1->v17:
* Collected tag for binding patch.
* Resending the series as there is an issue with patch threading from
patch #14.
[1]:
Logs:
root@smarc-rzg3l:~# dmesg | grep mmc
[ 0.000000] Kernel command line: rw rootwait earlycon root=/dev/mmcblk0p2 net.ifnames=0
[ 1.954120] renesas_sdhi_internal_dmac 11c10000.mmc: mmc1 base at 0x0000000011c10000, max clock rate 150 MHz
[ 1.967729] renesas_sdhi_internal_dmac 11c00000.mmc: mmc0 base at 0x0000000011c00000, max clock rate 150 MHz
[ 1.978997] Waiting for root device /dev/mmcblk0p2...
[ 2.066736] mmc0: new HS400 MMC card at address 0001
[ 2.077061] mmcblk0: mmc0:0001 0IM20F 59.3 GiB
[ 2.095408] mmcblk0: p1 p2
[ 2.098917] mmcblk0boot0: mmc0:0001 0IM20F 31.5 MiB
[ 2.106696] mmcblk0boot1: mmc0:0001 0IM20F 31.5 MiB
[ 2.113966] mmcblk0rpmb: mmc0:0001 0IM20F 4.00 MiB, chardev (510:0)
[ 2.228334] EXT4-fs (mmcblk0p2): mounted filesystem d267a6b0-3e0c-48b1-865c-8801ab27f2c2 r/w with ordered data mode. Quota mode: none.
[ 2.483088] mmc1: new UHS-I speed SDR104 SDXC card at address 5048
[ 2.496361] mmcblk1: mmc1:5048 SN64G 59.5 GiB
[ 2.504683] mmcblk1: p1 p2
[ 4.455604] EXT4-fs (mmcblk0p2): re-mounted d267a6b0-3e0c-48b1-865c-8801ab27f2c2.
root@smarc-rzg3l:~# cat /sys/kernel/debug/mmc*/ios
clock: 150000000 Hz
actual clock: 150000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 10 (mmc HS400)
signal voltage: 1 (1.80 V)
driver type: 1 (driver type A)
clock: 150000000 Hz
actual clock: 150000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 6 (sd uhs SDR104)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)
root@smarc-rzg3l:~# echo "test" > /1.txt
root@smarc-rzg3l:~# mount -t auto /dev/mmcblk1p1 /media/
[ 287.682702] EXT4-fs (mmcblk1p1): mounted filesystem 6fb3211d-4e8e-4ab0-b0ab-e0d2451b9b98 r/w with ordered data mode. Quota mode: none.
root@smarc-rzg3l:~# echo "media" > /media/1.text
root@smarc-rzg3l:~# cat /media/1.text
media
s2ram:
root@smarc-rzg3l:~# echo mem > /sys/power/state
[ 333.723778] PM: suspend entry (deep)
[ 333.743368] Filesystems sync: 0.015 seconds
[ 333.754880] Freezing user space processes
[ 333.762770] Freezing user space processes completed (elapsed 0.003 seconds)
[ 333.769795] OOM killer disabled.
[ 333.773021] Freezing remaining freezable tasks
[ 333.778915] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
[ 333.786358] printk: Suspending console(s) (use no_console_suspend to debug)
NOTICE: BL2: v2.10.5(release):2.10.5/rzg3l_1.0.1_rc2
NOTICE: BL2: Built : 11:18:41, Jul 15 2026
INFO: BL2: Doing platform setup
INFO: Configuring TrustZone Controller
INFO: Total 3 regions set.
INFO: Configuring TrustZone Controller
INFO: Total 1 regions set.
INFO: Configuring TrustZone Controller
INFO: Total 1 regions set.
INFO: eMMC boot from partition 1
INFO: Loading image id=39 at address 0x44428
INFO: emmcdrv_block_len: len: 0x00001000
INFO: Load dst=0x44428 src=(p:1)0x260000(4864) len=0x1000(8)
INFO: Image id=39 loaded: 0x44428 - 0x45428
INFO: DDR: Retention Exit (Rev. 02.05)
NOTICE: BL2: SYS_LSI_MODE: 0x12051
NOTICE: BL2: SYS_LSI_DEVID: 0x87d9447
INFO: BL2: Skip loading image id 3
INFO: BL2: Skip loading image id 5
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0x44000000
INFO: SPSR = 0x3cd
[ 333.827014] renesas-gbeth 11c30000.ethernet eth0: Link is Down
[ 333.830869] Disabling non-boot CPUs ...
[ 333.833195] psci: CPU3 killed (polled 0 ms)
[ 333.837072] psci: CPU2 killed (polled 0 ms)
[ 333.840622] psci: CPU1 killed (polled 0 ms)
[ 333.842113] Enabling non-boot CPUs ...
[ 333.842381] Detected VIPT I-cache on CPU1
[ 333.842438] GICv3: CPU1: found redistributor 100 region 0:0x0000000012460000
[ 333.842484] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
[ 333.843494] CPU1 is up
[ 333.843644] Detected VIPT I-cache on CPU2
[ 333.843678] GICv3: CPU2: found redistributor 200 region 0:0x0000000012480000
[ 333.843708] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
[ 333.844560] CPU2 is up
[ 333.844714] Detected VIPT I-cache on CPU3
[ 333.844750] GICv3: CPU3: found redistributor 300 region 0:0x00000000124a0000
[ 333.844781] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
[ 333.845804] CPU3 is up
[ 333.873259] dwmac4: Master AXI performs fixed burst length
[ 333.873305] renesas-gbeth 11c30000.ethernet eth0: No Safety Features support found
[ 333.873349] renesas-gbeth 11c30000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported
[ 333.875449] renesas-gbeth 11c30000.ethernet eth0: configuring for phy/rgmii-id link mode
[ 333.892271] dwmac4: Master AXI performs fixed burst length
[ 333.892300] renesas-gbeth 11c40000.ethernet eth1: No Safety Features support found
[ 333.892329] renesas-gbeth 11c40000.ethernet eth1: IEEE 1588-2008 Advanced Timestamp supported
[ 333.894274] renesas-gbeth 11c40000.ethernet eth1: configuring for phy/rgmii-id link mode
[ 334.066618] OOM killer enabled.
[ 334.069768] Restarting tasks: Starting
[ 334.075337] Restarting tasks: Done
[ 334.079175] random: crng reseeded on system resumption
[ 334.084885] PM: suspend exit
root@smarc-rzg3l:~# [ 336.680010] renesas-gbeth 11c30000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
root@smarc-rzg3l:~# cat /1.txt
test
root@smarc-rzg3l:~# cat /media/1.text
media
root@smarc-rzg3l:~# cat /sys/kernel/debug/mmc*/ios
clock: 150000000 Hz
actual clock: 150000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 10 (mmc HS400)
signal voltage: 1 (1.80 V)
driver type: 1 (driver type A)
clock: 150000000 Hz
actual clock: 150000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 6 (sd uhs SDR104)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)
root@smarc-rzg3l:~#
s2idle:
root@smarc-rzg3l:~# echo freeze > /sys/power/state
[ 450.999169] PM: suspend entry (s2idle)
[ 451.017350] Filesystems sync: 0.013 seconds
[ 451.024258] Freezing user space processes
[ 451.028222] Freezing user space processes completed (elapsed 0.003 seconds)
[ 451.037188] OOM killer disabled.
[ 451.040460] Freezing remaining freezable tasks
[ 451.046419] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
[ 451.053881] printk: Suspending console(s) (use no_console_suspend to debug)
[ 451.095285] renesas-gbeth 11c30000.ethernet eth0: Link is Down
[ 453.419781] dwmac4: Master AXI performs fixed burst length
[ 453.419827] renesas-gbeth 11c30000.ethernet eth0: No Safety Features support found
[ 453.419869] renesas-gbeth 11c30000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported
[ 453.420959] renesas-gbeth 11c30000.ethernet eth0: configuring for phy/rgmii-id link mode
[ 453.437889] dwmac4: Master AXI performs fixed burst length
[ 453.437921] renesas-gbeth 11c40000.ethernet eth1: No Safety Features support found
[ 453.437952] renesas-gbeth 11c40000.ethernet eth1: IEEE 1588-2008 Advanced Timestamp supported
[ 453.439032] renesas-gbeth 11c40000.ethernet eth1: configuring for phy/rgmii-id link mode
[ 453.531484] OOM killer enabled.
[ 453.534640] Restarting tasks: Starting
[ 453.539474] Restarting tasks: Done
[ 453.543086] random: crng reseeded on system resumption
[ 453.548410] PM: suspend exit
root@smarc-rzg3l:~# [ 455.991868] renesas-gbeth 11c30000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
root@smarc-rzg3l:~# cat /1.txt
test
root@smarc-rzg3l:~# cat /media/1.text
media
root@smarc-rzg3l:~# cat /sys/kernel/debug/mmc*/ios
clock: 150000000 Hz
actual clock: 150000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 10 (mmc HS400)
signal voltage: 1 (1.80 V)
driver type: 1 (driver type A)
clock: 150000000 Hz
actual clock: 150000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 6 (sd uhs SDR104)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)
root@smarc-rzg3l:~#
SDIO Testing:
root@smarc-rzg3l:~# dmesg | grep mmc1
[ 1.750548] renesas_sdhi_internal_dmac 11c10000.mmc: mmc1 base at 0x0000000011c10000, max clock rate 150 MHz
[ 1.949973] mmc1: new UHS-I speed SDR50 SDIO card at address 0001
root@smarc-rzg3l:~# ping google.com
PING google.com (142.250.117.101): 56 data bytes
64 bytes from 142.250.117.101: seq=0 ttl=113 time=9.466 ms
64 bytes from 142.250.117.101: seq=1 ttl=113 time=13.376 ms
64 bytes from 142.250.117.101: seq=2 ttl=113 time=13.486 ms
3 packets transmitted, 3 packets received, 0% packet loss
round-trip min/avg/
Biju Das (12):
dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC
mmc: renesas_sdhi: Clean up whitespace and add OF table sentinels
mmc: renesas_sdhi: Add clk_mask field to support flexible clock
divider widths
mmc: renesas_sdhi: Add max_divider field to support SoC-specific clock
ranges
mmc: renesas_sdhi: Make clock divider mask configurable
mmc: renesas_sdhi: Add tuning delay support for RZ/G2L
mmc: renesas_sdhi: Add TMIO_MMC_INTERNAL_DIVIDER flag
mmc: renesas_sdhi: Add optional axis/axim reset controls
mmc: renesas_sdhi: Add RZ/G3L SDHI support
mmc: renesas_sdhi: Save and restore IOVS across suspend/resume
mmc: renesas_sdhi: Make HS400 OSEL bit configurable per SoC
mmc: renesas_sdhi: Add RZ/G3L HS400 support
.../devicetree/bindings/mmc/renesas,sdhi.yaml | 108 ++++++--
drivers/mmc/host/renesas_sdhi.h | 12 +-
drivers/mmc/host/renesas_sdhi_core.c | 232 ++++++++++++++----
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 78 +++++-
drivers/mmc/host/renesas_sdhi_sys_dmac.c | 14 +-
include/linux/platform_data/tmio.h | 16 ++
6 files changed, 375 insertions(+), 85 deletions(-)
--
2.43.0
^ permalink raw reply
* Re: [PATCH v2 0/2] mmc: core: Add a host capability to skip SLEEP for cards with a broken resume
From: Ulf Hansson @ 2026-07-18 13:32 UTC (permalink / raw)
To: Kamal Dasu
Cc: Ulf Hansson, Florian Fainelli, Wolfram Sang, Oleksij Rempel,
Avri Altman, Pedro Demarchi Gomes, Erick Shepherd, Adrian Hunter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-mmc,
devicetree, linux-kernel
In-Reply-To: <20260717180536.1757204-1-kamal.dasu@broadcom.com>
On Fri, Jul 17, 2026 at 8:06 PM Kamal Dasu <kamal.dasu@broadcom.com> wrote:
>
> This is v2 of Florian's original patch:
>
> Link: https://lore.kernel.org/r/20260413180551.3683969-1-florian.fainelli@broadcom.com/
>
> Background: the Kioxia 016G01 eMMC takes ~10ms to exit SLEEP (CMD5)
> instead of the ~1ms it advertises via S_A_TIMEOUT, which can be
> problematic on systems that resume from Suspend-to-DRAM by first
> pulling boot code from eMMC using hard wired logic that is not field
> updatable -- if the card is still asleep when that logic reads it, it
> resets the board. The device stays powered throughout suspend-to-
> DRAM (no software-controlled VCC/VCCQ regulator toggling on this
> path), and the CMD0-before-resume sequence follows the JEDEC boot
> spec, so this isn't something the kernel's resume ordering can fix
> on its own.
>
> v1 addressed this with a card-level MMC_QUIRK_BROKEN_SLEEP quirk
> keyed off the device CID. Ulf pointed out that a device-specific
> quirk doesn't generalize well and suggested a host capability bit
> instead, settable from DT (or derived from a compatible string),
> mirroring the existing no-sdio/no-sd/no-mmc properties. Oleksij
> separately noted that quirks registered in mmc_blk_fixups[] are only
> applied once the mmc_block driver probes, which is too late to avoid
> a race against an earlier SLEEP/poweroff triggered on an under-
> voltage path -- a host cap resolved in mmc_of_parse(), before any
> card exists, sidesteps that ordering problem entirely.
>
> This series implements that direction:
>
> - Patch 1 documents a new "no-mmc-sleep" DT flag property.
> - Patch 2 adds MMC_CAP2_NO_SLEEP_CMD, parses the DT property in
> mmc_of_parse(), and has mmc_card_can_sleep() honor it.
Hmm, this sounds like this is about skipping the sleep command, while
in fact what is needed is to keep the eMMC card powered on during
system suspend [1].
Moreover, during system resume, even if the card remains powered on,
the kernel still needs to do a re-initialization of the card, because
the FW has already used the eMMC before the kernel resumes.
If you could rephrase the description in the cover letter and its
header towards this, I would appreciate it as it would become more
clear what we need here.
>
> The actual board DT change (adding "no-mmc-sleep;" to the affected
> brcmstb eMMC controller node) will follow separately once this lands,
> since that DT lives outside of mainline.
>
> Changes in v2:
> - Dropped the card-quirk/CID-match approach entirely in favor of a
> host capability bit, per Ulf's suggestion.
> - Added a DT property ("no-mmc-sleep") to set that capability,
> following the no-sdio/no-sd/no-mmc precedent, per Ulf.
> - This also resolves Oleksij's concern about mmc_blk_fixups[]
> being applied too late to close the race on an early
> SLEEP/poweroff path, since the host cap is resolved in
> mmc_of_parse() before a card exists.
> - Reworded the rationale in patch 1's commit message and binding
> description per Florian's review.
> - Added a Reported-by/Closes tag crediting Florian for the
> original bug report.
>
> Kamal Dasu (2):
> dt-bindings: mmc: Document no-mmc-sleep property
> mmc: core: Add MMC_CAP2_NO_SLEEP_CMD host capability
>
> .../devicetree/bindings/mmc/mmc-controller-common.yaml | 8 ++++++++
> drivers/mmc/core/host.c | 2 ++
> drivers/mmc/core/mmc.c | 3 +++
> include/linux/mmc/host.h | 1 +
> 4 files changed, 14 insertions(+)
>
> --
> 2.34.1
>
Kind regards
Uffe
[1]
https://lore.kernel.org/all/CAPx+jO-RJYCwKLLYCPZw8nR0VLVJ+UXPotXwXXRHGvar04QyDg@mail.gmail.com/
^ permalink raw reply
* Re: [PATCH v6 02/16] clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe
From: sashiko-bot @ 2026-07-18 13:23 UTC (permalink / raw)
To: Imran Shaik; +Cc: devicetree, conor+dt, robh
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-2-62703e05ef0f@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Placing a voting register in the clk_cbcrs array misuses the CBCR API and introduces a fragile pattern.
--
--- Patch [2]: [PATCH v6 02/16] clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe ---
commit d7a7b99958c3ce75a0a25d8faec4383b5f406ac6
Author: Imran Shaik <imran.shaik@oss.qualcomm.com>
clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe
This commit drops the modeling of certain always-on QCM2290 GCC branch clocks
and instead uses the .clk_cbcr convention to keep them enabled from probe.
> diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c
> --- a/drivers/clk/qcom/gcc-qcm2290.c
> +++ b/drivers/clk/qcom/gcc-qcm2290.c
[ ... ]
> @@ -2943,6 +2845,15 @@ static struct gdsc *gcc_qcm2290_gdscs[] = {
> [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,
> };
>
> +static const u32 gcc_qcm2290_critical_cbcrs[] = {
> + 0x17008, /* GCC_CAMERA_AHB_CLK */
> + 0x17028, /* GCC_CAMERA_XO_CLK */
> + 0x1700c, /* GCC_DISP_AHB_CLK */
> + 0x1702c, /* GCC_DISP_XO_CLK */
> + 0x36004, /* GCC_GPU_CFG_AHB_CLK */
> + 0x79004, /* GCC_SYS_NOC_CPUSS_AHB_CLK */
[Severity: Low]
Does this code misuse the clk_cbcrs array? Register 0x79004 is a shared
voting register rather than a standard Clock Branch Control Register (CBCR).
Looking at how the API handles clk_cbcrs, the helper
qcom_branch_set_clk_en() unconditionally updates BIT(0) (the standard
CBCR enable bit).
While this functions correctly for GCC_SYS_NOC_CPUSS_AHB_CLK simply because
its voting mask happens to be exactly BIT(0), doesn't this introduce a
fragile pattern?
If this is copied for other voting clocks with different masks (such as
BIT(15)), won't it silently corrupt the voting register state and fail to
enable the intended clock?
> +};
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com?part=2
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: mmc: Add post-power-off-delay-ms property
From: Ulf Hansson @ 2026-07-18 13:15 UTC (permalink / raw)
To: Judith Mendez
Cc: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-mmc, devicetree, linux-kernel
In-Reply-To: <305cf4be-2f45-49b9-b933-05ac41092685@ti.com>
On Fri, Jul 17, 2026 at 7:40 PM Judith Mendez <jm@ti.com> wrote:
>
> Hi Ulf,
>
> On 7/17/26 5:21 AM, Ulf Hansson wrote:
> > On Fri, Jul 17, 2026 at 1:26 AM Judith Mendez <jm@ti.com> wrote:
> >>
> >> Add post-power-off-delay-ms property to MMC controller common.
> >>
> >> This property shall be used to specify delay if needed after
> >> deasserting power during MMC power cycles.
> >
> > Please clarify with some additional information from the cover-letter,
> > like "specify custom delays after MMC power off to work around
> > hardware issues such as slow RC circuites on MMC VDD rails."
> >
> >>
> >> Signed-off-by: Judith Mendez <jm@ti.com>
> >> ---
> >> .../devicetree/bindings/mmc/mmc-controller-common.yaml | 8 ++++++++
> >> 1 file changed, 8 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
> >> index 3d7195e9461c3..3ff68d32a308f 100644
> >> --- a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
> >> +++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml
> >> @@ -275,6 +275,14 @@ properties:
> >> not available.
> >> default: 10
> >>
> >> + post-power-off-delay-ms:
> >
> > For mmc-pwrseq-simple we already have "power-off-delay-us", perhaps
> > better to re-use that name instead.
>
> Besides having the same dt property name as mmc-pwrseq-simple what is
> the benefit of switching to power-off-delay-us?
Using ms as the unit is limiting and completely unnecessary. What is
some HW is fine with 300 us, for example.
>
> All values will have to be in us instead of ms and thus will look a bit
> less clean in code. If it is just a naming preference, I do prefer
> the current name in this version, please let me know if we can keep:
> post-power-off-delay-ms.
The code is a separate thing, this is the DT property for supporting
different HWs.
[...]
Kind regards
Uffe
^ permalink raw reply
* Re: [PATCH v6 06/16] clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs
From: sashiko-bot @ 2026-07-18 13:12 UTC (permalink / raw)
To: Imran Shaik; +Cc: conor+dt, devicetree, robh
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-6-62703e05ef0f@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Hardware context retention failure due to conflicting SW_RESET flag in GPU GX GDSC.
--
--- Patch [6]: [PATCH v6 06/16] clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs ---
commit 190ef1fdcc32df401791889048619af17ae2bf71
Author: Imran Shaik <imran.shaik@oss.qualcomm.com>
clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs
Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs on QCM2290 to retain
the register context across GDSC power collapse.
> diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c
> index 3b130f69bb938..8d397cadc86aa 100644
> --- a/drivers/clk/qcom/gpucc-qcm2290.c
> +++ b/drivers/clk/qcom/gpucc-qcm2290.c
[ ... ]
> @@ -313,7 +313,7 @@ static struct gdsc gpu_gx_gdsc = {
> },
> .parent = &gpu_cx_gdsc.pd,
> .pwrsts = PWRSTS_OFF_ON,
> - .flags = POLL_CFG_GDSCR | CLAMP_IO | AON_RESET | SW_RESET,
> + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR | CLAMP_IO | AON_RESET | SW_RESET,
[Severity: High]
Does adding RETAIN_FF_ENABLE here conflict with the existing SW_RESET flag?
During runtime PM resume of the gpu_gx_gdsc domain, the GDSC framework calls
gdsc_enable(). Since SW_RESET is present, gdsc_enable() will call
gdsc_assert_reset() to pulse the block controller reset.
Won't this hardware reset immediately erase the flip-flop state that
RETAIN_FF_ENABLE was intended to preserve across power collapse?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com?part=6
^ permalink raw reply
* Re: [PATCH v6 08/16] clk: qcom: gpucc-qcm2290: Drop pm_clk handling
From: sashiko-bot @ 2026-07-18 13:10 UTC (permalink / raw)
To: Imran Shaik; +Cc: conor+dt, devicetree, robh
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-8-62703e05ef0f@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] Probe function unconditionally returns 0 on the error path and logs a misleading copy-paste error message.
--
--- Patch [8]: [PATCH v6 08/16] clk: qcom: gpucc-qcm2290: Drop pm_clk handling ---
commit 01c8b0bd5cb4f5e13257da3723ae92aece05f86d
Author: Imran Shaik <imran.shaik@oss.qualcomm.com>
clk: qcom: gpucc-qcm2290: Drop pm_clk handling
This commit drops the pm_clk handling from the QCM2290 GPUCC driver since the
required GCC AHB clocks are kept always enabled by the GCC driver during probe.
> diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c
> index 4e97a02d942ad..f14b4620090ef 100644
> --- a/drivers/clk/qcom/gpucc-qcm2290.c
> +++ b/drivers/clk/qcom/gpucc-qcm2290.c
[ ... ]
> @@ -385,16 +384,6 @@ static int gpu_cc_qcm2290_probe(struct platform_device *pdev)
> if (ret)
> return ret;
>
> - ret = devm_pm_clk_create(&pdev->dev);
> - if (ret)
> - return ret;
> -
> - ret = pm_clk_add(&pdev->dev, NULL);
> - if (ret < 0) {
> - dev_err(&pdev->dev, "failed to acquire ahb clock\n");
> - return ret;
> - }
> -
> ret = pm_runtime_resume_and_get(&pdev->dev);
> if (ret)
> return ret;
[Severity: High]
This isn't a bug introduced by this patch, but while reviewing this function,
I noticed an issue further down in gpu_cc_qcm2290_probe():
ret = qcom_cc_really_probe(&pdev->dev, &gpu_cc_qcm2290_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register display clock controller\n");
goto out_pm_runtime_put;
}
out_pm_runtime_put:
pm_runtime_put_sync(&pdev->dev);
return 0;
Should the error path propagate ret instead of unconditionally returning 0?
This appears to silently ignore probe failures from qcom_cc_really_probe(),
which could leave the system in an inconsistent state.
Additionally, is the "display clock controller" mentioned in the error message
a copy-paste error?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com?part=8
^ permalink raw reply
* [PATCH v6 16/16] arm64: dts: qcom: shikra: Add support for DISPCC/GPUCC nodes
From: Imran Shaik @ 2026-07-18 12:56 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Loic Poulain,
Brian Masney, Dmitry Baryshkov
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Imran Shaik, Dmitry Baryshkov
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com>
Add support for Display clock controller and GPU clock controller nodes
on Qualcomm Shikra SoCs.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 4e5bc9e17c8ed8914733ac9fdc9b69128b40216e..2a131ae601a7040142da16e39dbe2f8563ef43ee 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -3,6 +3,8 @@
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
+#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
+#include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
@@ -640,6 +642,40 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
};
};
+ gpucc: clock-controller@5990000 {
+ compatible = "qcom,shikra-gpucc";
+ reg = <0x0 0x05990000 0x0 0x9000>;
+ clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ dispcc: clock-controller@5f00000 {
+ compatible = "qcom,shikra-dispcc", "qcom,qcm2290-dispcc";
+ reg = <0x0 0x05f00000 0x0 0x20000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+ <0>,
+ <0>;
+ clock-names = "bi_tcxo",
+ "bi_tcxo_ao",
+ "gcc_disp_gpll0_clk_src",
+ "gcc_disp_gpll0_div_clk_src",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk";
+ power-domains = <&rpmpd RPMPD_VDDCX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
sram@c11e000 {
compatible = "qcom,shikra-imem", "mmio-sram";
reg = <0x0 0x0c11e000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related
* [PATCH v6 15/16] clk: qcom: Add support for Qualcomm GPU Clock Controller on Shikra
From: Imran Shaik @ 2026-07-18 12:56 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Loic Poulain,
Brian Masney, Dmitry Baryshkov
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Imran Shaik, Konrad Dybcio,
Dmitry Baryshkov
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com>
The Qualcomm Shikra GPU clock controller is similar to QCM2290 GPUCC
hardware block, with minor differences. Hence add support for Shikra
GPUCC by extending the QCM2290 GPUCC driver.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
drivers/clk/qcom/gpucc-qcm2290.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c
index fc33d82bcfb6843307d002d67674253f0174cb4a..ece567c533e88527451eecfbcd52a52bd05a8ad3 100644
--- a/drivers/clk/qcom/gpucc-qcm2290.c
+++ b/drivers/clk/qcom/gpucc-qcm2290.c
@@ -133,6 +133,17 @@ static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
{ }
};
+static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src_shikra[] = {
+ F(355200000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0),
+ F(537600000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0),
+ F(672000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
+ F(844800000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
+ F(921600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
+ F(1017600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
+ F(1142400000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
+ { }
+};
+
static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
.cmd_rcgr = 0x101c,
.mnd_width = 0,
@@ -371,12 +382,16 @@ static const struct qcom_cc_desc gpu_cc_qcm2290_desc = {
static const struct of_device_id gpu_cc_qcm2290_match_table[] = {
{ .compatible = "qcom,qcm2290-gpucc" },
+ { .compatible = "qcom,shikra-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_qcm2290_match_table);
static int gpu_cc_qcm2290_probe(struct platform_device *pdev)
{
+ if (device_is_compatible(&pdev->dev, "qcom,shikra-gpucc"))
+ gpu_cc_gx_gfx3d_clk_src.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src_shikra;
+
return qcom_cc_probe(pdev, &gpu_cc_qcm2290_desc);
}
--
2.34.1
^ permalink raw reply related
* [PATCH v6 14/16] dt-bindings: clock: qcom: Add Qualcomm Shikra GPU clock controller
From: Imran Shaik @ 2026-07-18 12:56 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Loic Poulain,
Brian Masney, Dmitry Baryshkov
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Imran Shaik, Krzysztof Kozlowski
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com>
The Qualcomm Shikra GPU clock controller is similar to QCM2290 GPUCC
hardware block, with same set of clocks and minor other differences.
Hence reuse the QCM2290 header file for Shikra and document the
Qualcomm Shikra GPUCC compatible.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml
index bedbdabef67286afb6ce0a1ac53d1a9a15a01a92..ad2386190346cc10f53763e7c3b9fcb35fca8ed5 100644
--- a/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml
@@ -18,7 +18,9 @@ description: |
properties:
compatible:
- const: qcom,qcm2290-gpucc
+ enum:
+ - qcom,qcm2290-gpucc
+ - qcom,shikra-gpucc
reg:
maxItems: 1
--
2.34.1
^ permalink raw reply related
* [PATCH v6 13/16] dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller
From: Imran Shaik @ 2026-07-18 12:56 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Loic Poulain,
Brian Masney, Dmitry Baryshkov
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Imran Shaik, Krzysztof Kozlowski
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com>
The Qualcomm Shikra Display clock controller has clocks same as QCM2290.
Hence, add support to use the QCM2290 DISPCC compatible as fallback for
Shikra DISPCC.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml
index e9c2326adfd285444257b96f5adc68e27213281f..8d4f53c8a6cbf9ae89475381ef6ce6e7b61b006d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml
@@ -17,7 +17,13 @@ description: |
properties:
compatible:
- const: qcom,qcm2290-dispcc
+ oneOf:
+ - items:
+ - enum:
+ - qcom,shikra-dispcc
+ - const: qcom,qcm2290-dispcc
+ - enum:
+ - qcom,qcm2290-dispcc
clocks:
items:
--
2.34.1
^ permalink raw reply related
* [PATCH v6 12/16] arm64: dts: qcom: agatti: Add missing CX power domain to DISPCC
From: Imran Shaik @ 2026-07-18 12:56 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Loic Poulain,
Brian Masney, Dmitry Baryshkov
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Imran Shaik, Dmitry Baryshkov,
Konrad Dybcio
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com>
Add the missing power-domains property to associate DISPCC with CX rail.
This is to ensure the genpd performance state votes on the GDSC to get
propagated to the CX rail and to avoid the rail under-voltage conditions.
Fixes: a2b32096709d ("arm64: dts: qcom: qcm2290: Add display nodes")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/agatti.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi
index f0b6ae9b81528a848a75f6884f1b27137d780f07..590bd2432d85ba80891ed42df8afa317c869daa2 100644
--- a/arch/arm64/boot/dts/qcom/agatti.dtsi
+++ b/arch/arm64/boot/dts/qcom/agatti.dtsi
@@ -2197,6 +2197,7 @@ dispcc: clock-controller@5f00000 {
"gcc_disp_gpll0_div_clk_src",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk";
+ power-domains = <&rpmpd QCM2290_VDDCX>;
#power-domain-cells = <1>;
#clock-cells = <1>;
#reset-cells = <1>;
--
2.34.1
^ permalink raw reply related
* [PATCH v6 11/16] clk: qcom: gpucc-qcm2290: Park RCG's clk source at XO during disable
From: Imran Shaik @ 2026-07-18 12:56 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Loic Poulain,
Brian Masney, Dmitry Baryshkov
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Imran Shaik, Dmitry Baryshkov,
Konrad Dybcio
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com>
The RCG's clk src has to be parked at XO while disabling as per hardware
team's recommendation, hence use clk_rcg2_shared_ops to achieve the same.
Fixes: 8cab033628b1 ("clk: qcom: Add QCM2290 GPU clock controller driver")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
drivers/clk/qcom/gpucc-qcm2290.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c
index 78797b77d7c7ba053201064ace3963cf2bd5281f..fc33d82bcfb6843307d002d67674253f0174cb4a 100644
--- a/drivers/clk/qcom/gpucc-qcm2290.c
+++ b/drivers/clk/qcom/gpucc-qcm2290.c
@@ -144,7 +144,7 @@ static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
--
2.34.1
^ permalink raw reply related
* [PATCH v6 10/16] clk: qcom: gpucc-qcm2290: Keep the critical clocks always-on from probe
From: Imran Shaik @ 2026-07-18 12:56 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Loic Poulain,
Brian Masney, Dmitry Baryshkov
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Imran Shaik, Dmitry Baryshkov,
Konrad Dybcio
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com>
Drop modelling of gpu_cc_ahb_clk and keep it always enabled from probe
similar to other critical clocks, since marking it as CLK_IS_CRITICAL
causes the clock framework to invoke clk_pm_runtime_get() during prepare,
which prevents the associated power domains from collapsing.
Fixes: 8cab033628b1 ("clk: qcom: Add QCM2290 GPU clock controller driver")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
drivers/clk/qcom/gpucc-qcm2290.c | 16 +---------------
1 file changed, 1 insertion(+), 15 deletions(-)
diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c
index b19e8910931d85ceda079c2745eba37e18112955..78797b77d7c7ba053201064ace3963cf2bd5281f 100644
--- a/drivers/clk/qcom/gpucc-qcm2290.c
+++ b/drivers/clk/qcom/gpucc-qcm2290.c
@@ -148,20 +148,6 @@ static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
},
};
-static struct clk_branch gpu_cc_ahb_clk = {
- .halt_reg = 0x1078,
- .halt_check = BRANCH_HALT_DELAY,
- .clkr = {
- .enable_reg = 0x1078,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gpu_cc_ahb_clk",
- .flags = CLK_IS_CRITICAL,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT_DELAY,
@@ -324,7 +310,6 @@ static struct gdsc gpu_gx_gdsc = {
};
static struct clk_regmap *gpu_cc_qcm2290_clocks[] = {
- [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
@@ -353,6 +338,7 @@ static struct clk_alpha_pll *gpu_cc_qcm2290_plls[] = {
};
static const u32 gpu_cc_qcm2290_critical_cbcrs[] = {
+ 0x1078, /* GPU_CC_AHB_CLK */
0x1060, /* GPU_CC_GX_CXO_CLK */
};
--
2.34.1
^ permalink raw reply related
* [PATCH v6 09/16] clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model
From: Imran Shaik @ 2026-07-18 12:56 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Loic Poulain,
Brian Masney, Dmitry Baryshkov
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Imran Shaik, Dmitry Baryshkov,
Konrad Dybcio
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com>
Update the QCM2290 GPUCC driver to use the qcom_cc_probe() model by moving
the critical clocks handling and PLL configurations from probe to the
driver_data to align with the latest convention.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
drivers/clk/qcom/gpucc-qcm2290.c | 50 ++++++++++++++++------------------------
1 file changed, 20 insertions(+), 30 deletions(-)
diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c
index f14b4620090efea139316ad833e034536caa5199..b19e8910931d85ceda079c2745eba37e18112955 100644
--- a/drivers/clk/qcom/gpucc-qcm2290.c
+++ b/drivers/clk/qcom/gpucc-qcm2290.c
@@ -2,12 +2,12 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2024, Linaro Limited
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
@@ -19,6 +19,7 @@
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
+#include "common.h"
#include "gdsc.h"
#include "reset.h"
@@ -55,6 +56,7 @@ static const struct alpha_pll_config gpu_cc_pll0_config = {
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
+ .config = &gpu_cc_pll0_config,
.vco_table = huayra_vco,
.num_vco = ARRAY_SIZE(huayra_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290],
@@ -346,6 +348,14 @@ static struct gdsc *gpu_cc_qcm2290_gdscs[] = {
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
+static struct clk_alpha_pll *gpu_cc_qcm2290_plls[] = {
+ &gpu_cc_pll0,
+};
+
+static const u32 gpu_cc_qcm2290_critical_cbcrs[] = {
+ 0x1060, /* GPU_CC_GX_CXO_CLK */
+};
+
static const struct regmap_config gpu_cc_qcm2290_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -354,6 +364,12 @@ static const struct regmap_config gpu_cc_qcm2290_regmap_config = {
.fast_io = true,
};
+static const struct qcom_cc_driver_data gpu_cc_qcm2290_driver_data = {
+ .alpha_plls = gpu_cc_qcm2290_plls,
+ .num_alpha_plls = ARRAY_SIZE(gpu_cc_qcm2290_plls),
+ .clk_cbcrs = gpu_cc_qcm2290_critical_cbcrs,
+ .num_clk_cbcrs = ARRAY_SIZE(gpu_cc_qcm2290_critical_cbcrs),
+};
static const struct qcom_cc_desc gpu_cc_qcm2290_desc = {
.config = &gpu_cc_qcm2290_regmap_config,
@@ -363,6 +379,8 @@ static const struct qcom_cc_desc gpu_cc_qcm2290_desc = {
.num_resets = ARRAY_SIZE(gpu_cc_qcm2290_resets),
.gdscs = gpu_cc_qcm2290_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_qcm2290_gdscs),
+ .use_rpm = true,
+ .driver_data = &gpu_cc_qcm2290_driver_data,
};
static const struct of_device_id gpu_cc_qcm2290_match_table[] = {
@@ -373,35 +391,7 @@ MODULE_DEVICE_TABLE(of, gpu_cc_qcm2290_match_table);
static int gpu_cc_qcm2290_probe(struct platform_device *pdev)
{
- struct regmap *regmap;
- int ret;
-
- regmap = qcom_cc_map(pdev, &gpu_cc_qcm2290_desc);
- if (IS_ERR(regmap))
- return PTR_ERR(regmap);
-
- ret = devm_pm_runtime_enable(&pdev->dev);
- if (ret)
- return ret;
-
- ret = pm_runtime_resume_and_get(&pdev->dev);
- if (ret)
- return ret;
-
- clk_huayra_2290_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
-
- regmap_update_bits(regmap, 0x1060, BIT(0), BIT(0)); /* GPU_CC_GX_CXO_CLK */
-
- ret = qcom_cc_really_probe(&pdev->dev, &gpu_cc_qcm2290_desc, regmap);
- if (ret) {
- dev_err(&pdev->dev, "Failed to register display clock controller\n");
- goto out_pm_runtime_put;
- }
-
-out_pm_runtime_put:
- pm_runtime_put_sync(&pdev->dev);
-
- return 0;
+ return qcom_cc_probe(pdev, &gpu_cc_qcm2290_desc);
}
static struct platform_driver gpu_cc_qcm2290_driver = {
--
2.34.1
^ permalink raw reply related
* [PATCH v6 08/16] clk: qcom: gpucc-qcm2290: Drop pm_clk handling
From: Imran Shaik @ 2026-07-18 12:56 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Loic Poulain,
Brian Masney, Dmitry Baryshkov
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Imran Shaik, Dmitry Baryshkov,
Konrad Dybcio
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com>
Drop the pm_clk handling from QCM2290 GPUCC driver as the required GCC AHB
clocks are kept always enabled by the GCC driver during probe.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
drivers/clk/qcom/gpucc-qcm2290.c | 11 -----------
1 file changed, 11 deletions(-)
diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c
index 4e97a02d942ad23af561ec6ce1ba0a6f61bf5a69..f14b4620090efea139316ad833e034536caa5199 100644
--- a/drivers/clk/qcom/gpucc-qcm2290.c
+++ b/drivers/clk/qcom/gpucc-qcm2290.c
@@ -7,7 +7,6 @@
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/pm_clock.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
@@ -385,16 +384,6 @@ static int gpu_cc_qcm2290_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = devm_pm_clk_create(&pdev->dev);
- if (ret)
- return ret;
-
- ret = pm_clk_add(&pdev->dev, NULL);
- if (ret < 0) {
- dev_err(&pdev->dev, "failed to acquire ahb clock\n");
- return ret;
- }
-
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return ret;
--
2.34.1
^ permalink raw reply related
* [PATCH v6 07/16] clk: qcom: qcm2290: Update DISPCC and GPUCC GDSC *wait_val values
From: Imran Shaik @ 2026-07-18 12:56 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Loic Poulain,
Brian Masney, Dmitry Baryshkov
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Imran Shaik, Dmitry Baryshkov,
Konrad Dybcio
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com>
Update the QCM2290 DISPCC and GPUCC GDSC wait_val fields to match the
hardware default values. Incorrect settings can cause the GDSC FSM to
stuck, leading to power on/off failures.
Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290")
Fixes: 8cab033628b1 ("clk: qcom: Add QCM2290 GPU clock controller driver")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
drivers/clk/qcom/dispcc-qcm2290.c | 3 +++
drivers/clk/qcom/gpucc-qcm2290.c | 6 ++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
index 1b796698dff5abf50e57d90b92a6a429ee078e2a..d32fd3f8d7acda2b5beae6695a5606732d056a17 100644
--- a/drivers/clk/qcom/dispcc-qcm2290.c
+++ b/drivers/clk/qcom/dispcc-qcm2290.c
@@ -451,6 +451,9 @@ static const struct qcom_reset_map disp_cc_qcm2290_resets[] = {
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
.pd = {
.name = "mdss_gdsc",
},
diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c
index 8d397cadc86aaa1666e27c8c4185b9b3de13cf94..4e97a02d942ad23af561ec6ce1ba0a6f61bf5a69 100644
--- a/drivers/clk/qcom/gpucc-qcm2290.c
+++ b/drivers/clk/qcom/gpucc-qcm2290.c
@@ -296,6 +296,9 @@ static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
.pd = {
.name = "gpu_cx_gdsc",
},
@@ -308,6 +311,9 @@ static struct gdsc gpu_gx_gdsc = {
.clamp_io_ctrl = 0x1508,
.resets = (unsigned int []){ GPU_GX_BCR },
.reset_count = 1,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x2,
.pd = {
.name = "gpu_gx_gdsc",
},
--
2.34.1
^ permalink raw reply related
* [PATCH v6 06/16] clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs
From: Imran Shaik @ 2026-07-18 12:56 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Loic Poulain,
Brian Masney, Dmitry Baryshkov
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Imran Shaik, Konrad Dybcio
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com>
Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs on QCM2290 to retain
the register context across GDSC power collapse.
Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290")
Fixes: 8cab033628b1 ("clk: qcom: Add QCM2290 GPU clock controller driver")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
drivers/clk/qcom/dispcc-qcm2290.c | 2 +-
drivers/clk/qcom/gpucc-qcm2290.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
index 5f5bc5b1e09e2207466d2972ded91140ce8a6ecf..1b796698dff5abf50e57d90b92a6a429ee078e2a 100644
--- a/drivers/clk/qcom/dispcc-qcm2290.c
+++ b/drivers/clk/qcom/dispcc-qcm2290.c
@@ -455,7 +455,7 @@ static struct gdsc mdss_gdsc = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
- .flags = HW_CTRL | POLL_CFG_GDSCR,
+ .flags = HW_CTRL | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc *disp_cc_qcm2290_gdscs[] = {
diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c
index 3b130f69bb93898ce49654f2366851a7c1c94524..8d397cadc86aaa1666e27c8c4185b9b3de13cf94 100644
--- a/drivers/clk/qcom/gpucc-qcm2290.c
+++ b/drivers/clk/qcom/gpucc-qcm2290.c
@@ -300,7 +300,7 @@ static struct gdsc gpu_cx_gdsc = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
- .flags = VOTABLE,
+ .flags = RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
@@ -313,7 +313,7 @@ static struct gdsc gpu_gx_gdsc = {
},
.parent = &gpu_cx_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
- .flags = POLL_CFG_GDSCR | CLAMP_IO | AON_RESET | SW_RESET,
+ .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR | CLAMP_IO | AON_RESET | SW_RESET,
};
static struct clk_regmap *gpu_cc_qcm2290_clocks[] = {
--
2.34.1
^ permalink raw reply related
* [PATCH v6 05/16] clk: qcom: qcm2290: Set POLL_CFG_GDSCR flag for DISPCC and GPUCC GDSCs
From: Imran Shaik @ 2026-07-18 12:56 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Loic Poulain,
Brian Masney, Dmitry Baryshkov
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Imran Shaik, Konrad Dybcio
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com>
The Qualcomm QCM2290 SoC GDSCR status bit may not reflect the actual state
of the GDSC, instead the power on/off bits in CFG_GDSCR must be polled to
determine the GDSC state correctly. Set POLL_CFG_GDSCR flag for the QCM2290
MDSS GDSC and GPUCC GX GDSC to ensure the correct GDSC status. This is not
applicable for GPUCC CX GDSC, which relies on gds_hw_ctrl status.
Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290")
Fixes: 8cab033628b1 ("clk: qcom: Add QCM2290 GPU clock controller driver")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
drivers/clk/qcom/dispcc-qcm2290.c | 2 +-
drivers/clk/qcom/gpucc-qcm2290.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
index 2350ce7f46d9f6e395c87c7a00669b10e8bce3d3..5f5bc5b1e09e2207466d2972ded91140ce8a6ecf 100644
--- a/drivers/clk/qcom/dispcc-qcm2290.c
+++ b/drivers/clk/qcom/dispcc-qcm2290.c
@@ -455,7 +455,7 @@ static struct gdsc mdss_gdsc = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
- .flags = HW_CTRL,
+ .flags = HW_CTRL | POLL_CFG_GDSCR,
};
static struct gdsc *disp_cc_qcm2290_gdscs[] = {
diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c
index 66dea9d2a0e519dfc64d977ef107b5c875da3869..3b130f69bb93898ce49654f2366851a7c1c94524 100644
--- a/drivers/clk/qcom/gpucc-qcm2290.c
+++ b/drivers/clk/qcom/gpucc-qcm2290.c
@@ -313,7 +313,7 @@ static struct gdsc gpu_gx_gdsc = {
},
.parent = &gpu_cx_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
- .flags = CLAMP_IO | AON_RESET | SW_RESET,
+ .flags = POLL_CFG_GDSCR | CLAMP_IO | AON_RESET | SW_RESET,
};
static struct clk_regmap *gpu_cc_qcm2290_clocks[] = {
--
2.34.1
^ permalink raw reply related
* [PATCH v6 04/16] clk: qcom: dispcc-qcm2290: Enable runtime PM support
From: Imran Shaik @ 2026-07-18 12:56 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Konrad Dybcio, Loic Poulain,
Brian Masney, Dmitry Baryshkov
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
devicetree, linux-kernel, Imran Shaik
In-Reply-To: <20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com>
The QCM2290 DISPCC is now associated with a power domain (RPMPD_CX) to
propagate genpd performance state votes to the CX rail. Set use_rpm to
true so that a runtime PM reference is acquired and released around probe,
instead of leaving a permanent 'enable' vote on the power domain.
Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290")
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
drivers/clk/qcom/dispcc-qcm2290.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
index 50a0705128a37073a077b560d0c9e57544d54348..2350ce7f46d9f6e395c87c7a00669b10e8bce3d3 100644
--- a/drivers/clk/qcom/dispcc-qcm2290.c
+++ b/drivers/clk/qcom/dispcc-qcm2290.c
@@ -515,6 +515,7 @@ static const struct qcom_cc_desc disp_cc_qcm2290_desc = {
.num_gdscs = ARRAY_SIZE(disp_cc_qcm2290_gdscs),
.resets = disp_cc_qcm2290_resets,
.num_resets = ARRAY_SIZE(disp_cc_qcm2290_resets),
+ .use_rpm = true,
.driver_data = &disp_cc_qcm2290_driver_data,
};
--
2.34.1
^ permalink raw reply related
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