From: sashiko-bot@kernel.org
To: "Long Zhao" <longzhao@ambarella.com>
Cc: devicetree@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org,
linux-gpio@vger.kernel.org
Subject: Re: [PATCH 2/7] gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR
Date: Fri, 09 Oct 2026 11:27:15 +0000 [thread overview]
Message-ID: <sashiko-outbox-165371@kernel.org> (raw)
In-Reply-To: <20261009-cv75-gpio-v1-2-5836bd438423@ambarella.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] gpio: regmap: missing return value check for gpio_regmap_set in direction_output
--
commit 4dfbff55c3fbea74424f90710c5b76efb22f738e
Author: Long Zhao <longzhao@ambarella.com>
gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR
Some controllers ignore output writes while a line is still an input.
Add a behaviour flag so the output value is written after the direction
change. This is a legacy quirk. New hardware must not use it.
> diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c
> index 51b4d69b87403..0a44deae3d01e 100644
> --- a/drivers/gpio/gpio-regmap.c
> +++ b/drivers/gpio/gpio-regmap.c
[ ... ]
> @@ -271,9 +272,17 @@ static int gpio_regmap_direction_output(struct gpio_chip *chip,
> return ret;
> }
>
> - gpio_regmap_set(chip, offset, value);
> + if (!(gpio->quirks & GPIO_REGMAP_QUIRK_SET_AFTER_DIR))
> + gpio_regmap_set(chip, offset, value);
>
> - return gpio_regmap_set_direction(chip, offset, true);
> + ret = gpio_regmap_set_direction(chip, offset, true);
> + if (ret)
> + return ret;
> +
> + if (gpio->quirks & GPIO_REGMAP_QUIRK_SET_AFTER_DIR)
> + gpio_regmap_set(chip, offset, value);
> +
> + return 0;
> }
[Severity: Medium]
Does this code silently ignore hardware or bus errors?
If gpio_regmap_set() fails due to an underlying I2C/SPI bus timeout or NACK,
it returns a negative error code. However, the return value is dropped in the
newly added GPIO_REGMAP_QUIRK_SET_AFTER_DIR path, just as it is in the
pre-existing path.
Could this falsely signal to the gpiolib framework that the output pin was
successfully configured, leaving the hardware in an undefined state and
masking the error from consumers?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261009-cv75-gpio-v1-0-5836bd438423@ambarella.com?part=2
next prev parent reply other threads:[~2026-10-09 11:27 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 10:57 [PATCH 0/7] gpio: add Ambarella CV75 PL061 support Long Zhao via B4 Relay
2026-10-09 10:57 ` [PATCH 1/7] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-10-09 11:32 ` Krzysztof Kozlowski
2026-10-09 10:57 ` [PATCH 2/7] gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR Long Zhao via B4 Relay
2026-10-09 11:17 ` Michael Walle
2026-10-09 11:27 ` sashiko-bot [this message]
2026-10-09 10:57 ` [PATCH 3/7] gpio: pl061: convert register access to regmap Long Zhao via B4 Relay
2026-10-09 10:57 ` [PATCH 4/7] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Long Zhao via B4 Relay
2026-10-09 10:57 ` [PATCH 5/7] gpio: pl061: use cleanup helpers for locks Long Zhao via B4 Relay
2026-10-09 10:57 ` [PATCH 6/7] gpio: pl061: switch data path to gpio-regmap Long Zhao via B4 Relay
2026-10-09 11:50 ` sashiko-bot
2026-10-09 10:58 ` [PATCH 7/7] gpio: pl061: add Ambarella register-layout variant Long Zhao via B4 Relay
2026-10-09 12:03 ` sashiko-bot
2026-10-09 11:32 ` [PATCH 0/7] gpio: add Ambarella CV75 PL061 support Krzysztof Kozlowski
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