[PATCHv2 1/2] dt-bindings: arm: altera: document the Agilex27 platform

[PATCHv2 1/2] dt-bindings: arm: altera: document the Agilex27 platform

[Dinh Nguyen]

The Altera SoCFGPA Agilex72 platform will be rebranded as the Agilex27.

Add the "altr,socfpga-agilex27" and "altr,socfpga-agilex27-socdk" bindings
for the SoCFPGA Agilex27 platform.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: do not deprecate the agilex72 platform
---
 Documentation/devicetree/bindings/arm/altera.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
index 5fce1161210e7..f7058f00975c6 100644
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/arm/altera.yaml
@@ -99,6 +99,12 @@ properties:
               - intel,socfpga-agilex-socdk-emmc
           - const: intel,socfpga-agilex
 
+      - description: Agilex27 boards
+        items:
+          - enum:
+              - altr,socfpga-agilex27-socdk
+          - const: altr,socfpga-agilex27
+
       - description: Agilex3 boards
         items:
           - enum:
-- 
2.42.0.411.g813d9a9188

[PATCHv2 2/2] arm64: dts: altera: Add support for the Agilex27 platform

[Dinh Nguyen]

The Agilex72 platform is being rebranded to Agilex27. The Agilex27 is
exactly the same as the Agilex72. Add the base DTSI and the devkit's
DTS.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: leave the agilex72 files
---
 arch/arm64/boot/dts/altera/Makefile           |   1 +
 .../boot/dts/altera/socfpga_agilex27.dtsi     | 156 ++++++++++++++++++
 .../dts/altera/socfpga_agilex27_socdk.dts     |  27 +++
 3 files changed, 184 insertions(+)
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_agilex27.dtsi
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_agilex27_socdk.dts

diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile
index 8f41349103b80..14e260fb16f3b 100644
--- a/arch/arm64/boot/dts/altera/Makefile
+++ b/arch/arm64/boot/dts/altera/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
 				socfpga_agilex_socdk.dtb \
 				socfpga_agilex_socdk_emmc.dtb \
 				socfpga_agilex_socdk_nand.dtb \
+				socfpga_agilex27_socdk.dtb \
 				socfpga_agilex3_socdk.dtb \
 				socfpga_agilex5_socdk.dtb \
 				socfpga_agilex5_socdk_013b.dtb \
diff --git a/arch/arm64/boot/dts/altera/socfpga_agilex27.dtsi b/arch/arm64/boot/dts/altera/socfpga_agilex27.dtsi
new file mode 100644
index 0000000000000..369981fe85e38
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_agilex27.dtsi
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026, Altera Corporation
+ */
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "altr,socfpga-agilex27";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		atf_reserved: atf@80000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x80000000 0x0 0x100000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+
+		service_reserved: svcbuffer@80100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x80100000 0x0 0xf00000>;
+			alignment = <0x1000>;
+			no-map;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a520";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x0>;
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,cortex-a520";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x100>;
+		};
+
+		cpu2: cpu@200 {
+			compatible = "arm,cortex-a720";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x200>;
+		};
+
+		cpu3: cpu@300 {
+			compatible = "arm,cortex-a720";
+			device_type = "cpu";
+			enable-method = "psci";
+			reg = <0x300>;
+		};
+	};
+
+	clocks {
+		uart_clk: uart-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <125000000>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	intc: interrupt-controller@7000000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x7000000 0x0 0x10000>,
+		      <0x0 0x7080000 0x0 0x100000>;
+		ranges;
+		#interrupt-cells = <3>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		interrupt-controller;
+		#redistributor-regions = <1>;
+		redistributor-stride = <0x0 0x40000>;
+
+		its: msi-controller@7040000 {
+			compatible = "arm,gic-v3-its";
+			reg = <0x0 0x7040000 0x0 0x20000>;
+			msi-controller;
+			#msi-cells = <1>;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		ranges = <0 0 0 0xffffffff>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		interrupt-parent = <&intc>;
+
+		smmu: iommu@c100000 {
+			compatible = "arm,smmu-v3";
+			reg = <0x0c100000 0x30000>;
+			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eventq", "gerror", "priq";
+			dma-coherent;
+			#iommu-cells = <1>;
+		};
+
+		ocram: sram@0 {
+			compatible = "mmio-sram";
+			reg = <0x00000000 0x80000>;
+			ranges = <0 0 0x80000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
+		uart0: serial@9038000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x9038000 0x100>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+
+		uart1: serial@9039000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x9039000 0x100>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&uart_clk>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/altera/socfpga_agilex27_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_agilex27_socdk.dts
new file mode 100644
index 0000000000000..15d331cdeeb47
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_agilex27_socdk.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026, Altera Corporation
+ */
+#include "socfpga_agilex27.dtsi"
+
+/ {
+	model = "Altera SoCFPGA Agilex27 SoCDK";
+	compatible = "altr,socfpga-agilex27-socdk", "altr,socfpga-agilex27";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
-- 
2.42.0.411.g813d9a9188

Re: [PATCHv2 2/2] arm64: dts: altera: Add support for the Agilex27 platform

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] arm64: dts: altera: Missing VGIC maintenance interrupt in GICv3 node
- [Low] arm64: dts: altera: Unnecessary duplication of SoC DTSI file
- [Low] dt-bindings: arm: altera: Undocumented compatible strings for Agilex27
--

commit ef21748becf923e3ea0b9bb9bcd2a6ea73fa866e
Author: Dinh Nguyen <dinguyen@kernel.org>

    arm64: dts: altera: Add support for the Agilex27 platform
    
    The Agilex72 platform is being rebranded to Agilex27. The Agilex27 is
    exactly the same as the Agilex72. Add the base DTSI and the devkit's
    DTS.

diff --git a/arch/arm64/boot/dts/altera/socfpga_agilex27.dtsi b/arch/arm64/boot/dts/altera/socfpga_agilex27.dtsi
new file mode 100644
index 0000000000000..369981fe85e38
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_agilex27.dtsi
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026, Altera Corporation
+ */
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "altr,socfpga-agilex27";
+	#address-cells = <2>;
+	#size-cells = <2>;

[Severity: Low]
Since the commit message states that Agilex27 is exactly the same as
Agilex72, is it necessary to duplicate the entire SoC layout into a new
file? Could we include the existing socfpga_agilex72.dtsi or add this
compatible string directly to the Agilex72 device tree to avoid keeping the
two files in sync?

[Severity: Low]
Is this new compatible string documented in the corresponding devicetree
binding YAML files? Without it, running make dtbs_check will likely trigger
validation errors.

[ ... ]

> +	intc: interrupt-controller@7000000 {
> +		compatible = "arm,gic-v3";
> +		reg = <0x0 0x7000000 0x0 0x10000>,
> +		      <0x0 0x7080000 0x0 0x100000>;
> +		ranges;
> +		#interrupt-cells = <3>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		interrupt-controller;
> +		#redistributor-regions = <1>;
> +		redistributor-stride = <0x0 0x40000>;

[Severity: Medium]
Does this GICv3 node need the interrupts property for the VGIC maintenance
interrupt? 

Without it, KVM initialization via vgic_set_kvm_info() cannot proceed because
irq_of_parse_and_map() returns 0. Could this silently break KVM virtualization
support on this platform?

[ ... ]

diff --git a/arch/arm64/boot/dts/altera/socfpga_agilex27_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_agilex27_socdk.dts
new file mode 100644
index 0000000000000..15d331cdeeb47
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_agilex27_socdk.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026, Altera Corporation
+ */
+#include "socfpga_agilex27.dtsi"
+
+/ {
+	model = "Altera SoCFPGA Agilex27 SoCDK";
+	compatible = "altr,socfpga-agilex27-socdk", "altr,socfpga-agilex27";

[Severity: Low]
Is the altr,socfpga-agilex27-socdk board-level compatible string documented
in the devicetree bindings?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261015123700.2137706-2-dinguyen@kernel.org?part=1