* [RESEND PATCH 0/2] mfd: add Airoha AN8855 switch support @ 2026-10-21 11:34 Christian Marangi 2026-10-21 11:34 ` [RESEND PATCH 1/2] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Christian Marangi 2026-10-21 11:34 ` [RESEND PATCH 2/2] mfd: an8855: Add support for Airoha AN8855 Switch Christian Marangi 0 siblings, 2 replies; 6+ messages in thread From: Christian Marangi @ 2026-10-21 11:34 UTC (permalink / raw) To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Christian Marangi, mfd, devicetree, linux-kernel This is a subset only specific for MFD changes for Airoha AN8855 switch support. The old series with all the patches can be reached here [1] Changelog is included in the same link [1] https://lore.kernel.org/all/20261009161102.38961-1-ansuelsmth@gmail.com/ Christian Marangi (2): dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC mfd: an8855: Add support for Airoha AN8855 Switch .../bindings/mfd/airoha,an8855.yaml | 176 ++++++ drivers/mfd/Kconfig | 14 + drivers/mfd/Makefile | 1 + drivers/mfd/airoha-an8855.c | 579 ++++++++++++++++++ 4 files changed, 770 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an8855.yaml create mode 100644 drivers/mfd/airoha-an8855.c -- 2.55.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [RESEND PATCH 1/2] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC 2026-10-21 11:34 [RESEND PATCH 0/2] mfd: add Airoha AN8855 switch support Christian Marangi @ 2026-10-21 11:34 ` Christian Marangi 2026-10-21 11:46 ` sashiko-bot 2026-10-21 13:35 ` Rob Herring (Arm) 2026-10-21 11:34 ` [RESEND PATCH 2/2] mfd: an8855: Add support for Airoha AN8855 Switch Christian Marangi 1 sibling, 2 replies; 6+ messages in thread From: Christian Marangi @ 2026-10-21 11:34 UTC (permalink / raw) To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Christian Marangi, mfd, devicetree, linux-kernel Document support for Airoha AN8855 Switch SoC. This SoC expose various peripherals like an Ethernet Switch, a NVMEM provider and Ethernet PHYs. It does also support i2c and timers but those are not currently supported/used. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> --- .../bindings/mfd/airoha,an8855.yaml | 176 ++++++++++++++++++ 1 file changed, 176 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an8855.yaml diff --git a/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml new file mode 100644 index 000000000000..48127e956c96 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml @@ -0,0 +1,176 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/airoha,an8855.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN8855 Switch SoC + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + +description: > + Airoha AN8855 Switch is a SoC that expose various peripherals like an + Ethernet Switch, a NVMEM provider and Ethernet PHYs. + + It does also support i2c and timers but those are not currently + supported/used. + +properties: + compatible: + const: airoha,an8855 + + reg: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + efuse: + type: object + $ref: /schemas/nvmem/airoha,an8855-efuse.yaml + description: EFUSE exposed by the Airoha AN8855 SoC + + ethernet-switch: + type: object + $ref: /schemas/net/dsa/airoha,an8855-switch.yaml + description: Switch exposed by the Airoha AN8855 SoC + + mdio: + type: object + $ref: /schemas/net/mdio.yaml# + description: MDIO exposed by the Airoha AN8855 SoC + unevaluatedProperties: false + +required: + - compatible + - reg + - mdio + - ethernet-switch + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + soc@1 { + compatible = "airoha,an8855"; + reg = <1>; + + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + + efuse { + compatible = "airoha,an8855-efuse"; + + #nvmem-cell-cells = <0>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + shift_sel_port0_tx_a: shift-sel-port0-tx-a@c { + reg = <0xc 0x4>; + }; + + shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 { + reg = <0x10 0x4>; + }; + + shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 { + reg = <0x14 0x4>; + }; + + shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 { + reg = <0x18 0x4>; + }; + + shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c { + reg = <0x1c 0x4>; + }; + + shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 { + reg = <0x20 0x4>; + }; + + shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 { + reg = <0x24 0x4>; + }; + + shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 { + reg = <0x28 0x4>; + }; + }; + }; + + ethernet-switch { + compatible = "airoha,an8855-switch"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&internal_phy1>; + }; + + port@1 { + reg = <1>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&internal_phy2>; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + internal_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-idc0ff.0410", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + + nvmem-cells = <&shift_sel_port0_tx_a>, + <&shift_sel_port0_tx_b>, + <&shift_sel_port0_tx_c>, + <&shift_sel_port0_tx_d>; + nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d"; + }; + + internal_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-idc0ff.0410", + "ethernet-phy-ieee802.3-c22"; + reg = <2>; + + nvmem-cells = <&shift_sel_port1_tx_a>, + <&shift_sel_port1_tx_b>, + <&shift_sel_port1_tx_c>, + <&shift_sel_port1_tx_d>; + nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d"; + }; + }; + }; + }; -- 2.55.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [RESEND PATCH 1/2] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC 2026-10-21 11:34 ` [RESEND PATCH 1/2] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Christian Marangi @ 2026-10-21 11:46 ` sashiko-bot 2026-10-21 13:35 ` Rob Herring (Arm) 1 sibling, 0 replies; 6+ messages in thread From: sashiko-bot @ 2026-10-21 11:46 UTC (permalink / raw) To: Christian Marangi, mfd, devicetree; +Cc: robh, conor+dt, lee Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] dt-bindings: mfd: reference to missing schema airoha,an8855-switch.yaml -- commit 8973f67919d9fd3d92a5417e6a75e38e2eb9cc42 Author: Christian Marangi <ansuelsmth@gmail.com> dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC This commit adds the devicetree binding schema for the Airoha AN8855 switch multi-function device, including its efuse, ethernet-switch, and mdio subnodes. > diff --git a/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml > new file mode 100644 > index 0000000000000..48127e956c965 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml [ ... ] > + efuse: > + type: object > + $ref: /schemas/nvmem/airoha,an8855-efuse.yaml > + description: EFUSE exposed by the Airoha AN8855 SoC > + > + ethernet-switch: > + type: object > + $ref: /schemas/net/dsa/airoha,an8855-switch.yaml > + description: Switch exposed by the Airoha AN8855 SoC [Severity: Low] Does this break make dt_binding_check? In Documentation/devicetree/bindings/mfd/airoha,an8855.yaml, properties:ethernet-switch references /schemas/net/dsa/airoha,an8855-switch.yaml, and the examples section instantiates an ethernet-switch child node with: ethernet-switch { compatible = "airoha,an8855-switch"; However, Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml does not exist in the repository, causing dt-doc-validate, dt-mk-schema, and dt-validate to fail on the unresolved $ref and the undocumented airoha,an8855-switch compatible string. -- Sashiko AI review · https://sashiko.dev/#/patchset/20261021113419.283015-1-ansuelsmth@gmail.com?part=1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [RESEND PATCH 1/2] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC 2026-10-21 11:34 ` [RESEND PATCH 1/2] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Christian Marangi 2026-10-21 11:46 ` sashiko-bot @ 2026-10-21 13:35 ` Rob Herring (Arm) 1 sibling, 0 replies; 6+ messages in thread From: Rob Herring (Arm) @ 2026-10-21 13:35 UTC (permalink / raw) To: Christian Marangi Cc: Conor Dooley, Lee Jones, mfd, Krzysztof Kozlowski, devicetree, linux-kernel On Wed, 21 Oct 2026 13:34:16 +0200, Christian Marangi wrote: > Document support for Airoha AN8855 Switch SoC. This SoC expose various > peripherals like an Ethernet Switch, a NVMEM provider and Ethernet PHYs. > > It does also support i2c and timers but those are not currently > supported/used. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > Reviewed-by: Rob Herring (Arm) <robh@kernel.org> > --- > .../bindings/mfd/airoha,an8855.yaml | 176 ++++++++++++++++++ > 1 file changed, 176 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an8855.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml: Unresolvable reference: /schemas/net/dsa/airoha,an8855-switch.yaml Documentation/devicetree/bindings/mfd/airoha,an8855.example.dtb: soc@1 (airoha,an8855): ethernet-switch: False schema does not allow {'compatible': ['airoha,an8855-switch'], 'ports': {'#address-cells': 1, '#size-cells': 0, 'port@0': {'reg': [[0]], 'label': ['lan1'], 'phy-mode': ['internal'], 'phy-handle': [[1]]}, 'port@1': {'reg': [[1]], 'label': ['lan2'], 'phy-mode': ['internal'], 'phy-handle': [[2]]}, 'port@5': {'reg': [[5]], 'label': ['cpu'], 'ethernet': [[4294967295]], 'phy-mode': ['2500base-x'], 'fixed-link': {'speed': 2500, 'full-duplex': True, 'pause': True}}}} from schema $id: http://devicetree.org/schemas/mfd/airoha,an8855.yaml Documentation/devicetree/bindings/mfd/airoha,an8855.example.dtb: /example-0/mdio/soc@1/ethernet-switch: failed to match any schema with compatible: ['airoha,an8855-switch'] doc reference errors (make refcheckdocs): See https://patchwork.kernel.org/project/devicetree/patch/20261021113419.283015-2-ansuelsmth@gmail.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [RESEND PATCH 2/2] mfd: an8855: Add support for Airoha AN8855 Switch 2026-10-21 11:34 [RESEND PATCH 0/2] mfd: add Airoha AN8855 switch support Christian Marangi 2026-10-21 11:34 ` [RESEND PATCH 1/2] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Christian Marangi @ 2026-10-21 11:34 ` Christian Marangi 2026-10-21 12:00 ` sashiko-bot 1 sibling, 1 reply; 6+ messages in thread From: Christian Marangi @ 2026-10-21 11:34 UTC (permalink / raw) To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Christian Marangi, mfd, devicetree, linux-kernel Add support for Airoha AN8855 Switch that provide support for a DSA switch and a NVMEM provider. Also make use of the mdio-regmap driver and register a regmap for each internal PHY of the switch. This is needed to handle the double usage of the PHYs as both PHY and Switch accessor. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> --- drivers/mfd/Kconfig | 14 + drivers/mfd/Makefile | 1 + drivers/mfd/airoha-an8855.c | 579 ++++++++++++++++++++++++++++++++++++ 3 files changed, 594 insertions(+) create mode 100644 drivers/mfd/airoha-an8855.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 87ed55c155f0..653a81435b20 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -54,6 +54,20 @@ config MFD_ALTERA_SYSMGR using regmap_mmio accesses for ARM32 parts and SMC calls to EL3 for ARM64 parts. +config MFD_AIROHA_AN8855 + tristate "Airoha AN8855 Switch Core" + select MFD_CORE + select REGMAP + select PHYLIB + select MDIO_REGMAP + depends on NETDEVICES && OF + help + Support for the Airoha AN8855 Switch Core. This is an SoC + that provides various peripherals, to count, i2c, an Ethrnet + Switch, a CPU timer, GPIO, eFUSE. + + Currently it provides a DSA switch and a NVMEM provider. + config MFD_ACT8945A tristate "Active-semi ACT8945A" select MFD_CORE diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index f8101d2a9ce9..96bbe3fad736 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_MFD_88PM860X) += 88pm860x.o obj-$(CONFIG_MFD_88PM800) += 88pm800.o 88pm80x.o obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o obj-$(CONFIG_MFD_88PM886_PMIC) += 88pm886.o +obj-$(CONFIG_MFD_AIROHA_AN8855) += airoha-an8855.o obj-$(CONFIG_MFD_ACT8945A) += act8945a.o obj-$(CONFIG_MFD_SM501) += sm501.o obj-$(CONFIG_ARCH_BCM2835) += bcm2835-pm.o diff --git a/drivers/mfd/airoha-an8855.c b/drivers/mfd/airoha-an8855.c new file mode 100644 index 000000000000..6a270555db5c --- /dev/null +++ b/drivers/mfd/airoha-an8855.c @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Core driver for Airoha AN8855 Switch + * + * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com> + */ + +#include <linux/bitfield.h> +#include <linux/fwnode_mdio.h> +#include <linux/gpio/consumer.h> +#include <linux/mfd/core.h> +#include <linux/mdio.h> +#include <linux/mdio/mdio-regmap.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/phy.h> +#include <linux/regmap.h> + +/* Register for HW trap status */ +#define AN8855_HWTRAP 0x1000009c + +/* + * Register of the Switch ID + * (called Project ID in Documentation) + */ +#define AN8855_CREV 0x10005000 +#define AN8855_ID 0x8855 /* Switch ID */ + +/* Register for GPHY Power Down + * Used to Toggle the Gigabit PHY power and enable them. + */ +#define AN8855_RG_GPHY_AFE_PWD 0x1028c840 + +/* MII Registers */ +#define AN8855_PHY_SELECT_PAGE 0x1f +#define AN8855_PHY_PAGE GENMASK(2, 0) +#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0) +#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1) +#define AN8855_PHY_PAGE_EXTENDED_4 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4) + +/* MII Registers Page 4 */ +#define AN8855_PBUS_MODE 0x10 +#define AN8855_PBUS_MODE_ADDR_FIXED 0x0 +#define AN8855_PBUS_MODE_ADDR_INCR BIT(15) +#define AN8855_PBUS_WR_ADDR_HIGH 0x11 +#define AN8855_PBUS_WR_ADDR_LOW 0x12 +#define AN8855_PBUS_WR_DATA_HIGH 0x13 +#define AN8855_PBUS_WR_DATA_LOW 0x14 +#define AN8855_PBUS_RD_ADDR_HIGH 0x15 +#define AN8855_PBUS_RD_ADDR_LOW 0x16 +#define AN8855_PBUS_RD_DATA_HIGH 0x17 +#define AN8855_PBUS_RD_DATA_LOW 0x18 + +#define AN8855_MAX_PHY_PORT 5 + +struct an8855 { + struct mii_bus *bus; + struct mii_bus *phy_bus; + unsigned int switch_addr; + u16 current_page; +}; + +struct an8855_phy { + u8 addr; + struct an8855 *core; +}; + +struct an8855_phy_bus { + struct mii_bus *bus; + struct fwnode_handle *node; + u8 addr; +}; + +static const struct mfd_cell an8855_cells[] = { + MFD_CELL_OF("an8855-efuse", NULL, NULL, 0, 0, + "airoha,an8855-efuse"), + MFD_CELL_OF("an8855-switch", NULL, NULL, 0, 0, + "airoha,an8855-switch"), +}; + +static int an8855_mii_set_page(struct an8855 *ddata, u8 addr, + u8 page) __must_hold(&ddata->bus->mdio_lock) +{ + struct mii_bus *bus = ddata->bus; + int ret; + + ret = __mdiobus_write(bus, addr, AN8855_PHY_SELECT_PAGE, page); + if (ret) { + dev_err_ratelimited(&bus->dev, "failed to set mii page\n"); + return ret; + } + + /* Cache current page if next MII read/write is for Switch page */ + ddata->current_page = page; + return 0; +} + +static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg, + u32 *val) __must_hold(&bus->mdio_lock) +{ + int lo, hi, ret; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE, + AN8855_PBUS_MODE_ADDR_FIXED); + if (ret) + goto err; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH, + upper_16_bits(reg)); + if (ret) + goto err; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW, + lower_16_bits(reg)); + if (ret) + goto err; + + hi = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH); + if (hi < 0) { + ret = hi; + goto err; + } + + lo = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW); + if (lo < 0) { + ret = lo; + goto err; + } + + *val = ((u32)hi << 16) | lo; + + return 0; +err: + dev_err_ratelimited(&bus->dev, "failed to read register\n"); + return ret; +} + +/* + * Protect concurrent access to phy page if switch address also + * expose a PHY. + */ +static void an8855_regmap_lock(struct an8855 *ddata) +{ + if (ddata->phy_bus) + mutex_lock(&ddata->phy_bus->mdio_lock); + mutex_lock_nested(&ddata->bus->mdio_lock, MDIO_MUTEX_NESTED); +} + +static void an8855_regmap_unlock(struct an8855 *ddata) +{ + mutex_unlock(&ddata->bus->mdio_lock); + if (ddata->phy_bus) + mutex_unlock(&ddata->phy_bus->mdio_lock); +} + +static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val) +{ + struct an8855 *ddata = ctx; + struct mii_bus *bus = ddata->bus; + u16 addr = ddata->switch_addr; + int ret; + + an8855_regmap_lock(ddata); + ret = an8855_mii_set_page(ddata, addr, AN8855_PHY_PAGE_EXTENDED_4); + if (ret < 0) + goto exit; + + ret = an8855_mii_read32(bus, addr, reg, val); + +exit: + an8855_regmap_unlock(ddata); + + return ret < 0 ? ret : 0; +} + +static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg, + u32 val) __must_hold(&bus->mdio_lock) +{ + int ret; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE, + AN8855_PBUS_MODE_ADDR_FIXED); + if (ret) + goto err; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH, + upper_16_bits(reg)); + if (ret) + goto err; + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW, + lower_16_bits(reg)); + if (ret) + goto err; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH, + upper_16_bits(val)); + if (ret) + goto err; + + ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW, + lower_16_bits(val)); + if (ret) + goto err; + + return 0; +err: + dev_err_ratelimited(&bus->dev, + "failed to write an8855 register\n"); + return ret; +} + +static int an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val) +{ + struct an8855 *ddata = ctx; + struct mii_bus *bus = ddata->bus; + u16 addr = ddata->switch_addr; + int ret; + + an8855_regmap_lock(ddata); + ret = an8855_mii_set_page(ddata, addr, AN8855_PHY_PAGE_EXTENDED_4); + if (ret) + goto exit; + + ret = an8855_mii_write32(bus, addr, reg, val); + +exit: + an8855_regmap_unlock(ddata); + + return ret < 0 ? ret : 0; +} + +static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, + uint32_t write_val) +{ + struct an8855 *ddata = ctx; + struct mii_bus *bus = ddata->bus; + u16 addr = ddata->switch_addr; + u32 val; + int ret; + + an8855_regmap_lock(ddata); + ret = an8855_mii_set_page(ddata, addr, AN8855_PHY_PAGE_EXTENDED_4); + if (ret) + goto exit; + + ret = an8855_mii_read32(bus, addr, reg, &val); + if (ret < 0) + goto exit; + + val &= ~mask; + val |= write_val & mask; + ret = an8855_mii_write32(bus, addr, reg, val); + +exit: + an8855_regmap_unlock(ddata); + + return ret < 0 ? ret : 0; +} + +static const struct regmap_range an8855_readable_ranges[] = { + regmap_reg_range(0x10000000, 0x10000fff), /* SCU */ + regmap_reg_range(0x10001000, 0x10001fff), /* RBUS */ + regmap_reg_range(0x10002000, 0x10002fff), /* MCU */ + regmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */ + regmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */ + regmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */ + regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */ + regmap_reg_range(0x1000a100, 0x1000a1ff), /* General Purpose Timer */ + regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */ + regmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */ + regmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */ + regmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */ + regmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */ + regmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */ + regmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */ + regmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */ + regmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */ + regmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */ + regmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */ + regmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */ + regmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */ + regmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */ + regmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */ + regmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */ + regmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */ + regmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */ + regmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */ +}; + +static const struct regmap_access_table an8855_readable_table = { + .yes_ranges = an8855_readable_ranges, + .n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges), +}; + +static const struct regmap_config an8855_regmap_config = { + .name = "switch", + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0xbfffffff, + .reg_read = an8855_regmap_read, + .reg_write = an8855_regmap_write, + .reg_update_bits = an8855_regmap_update_bits, + .disable_locking = true, + .rd_table = &an8855_readable_table, +}; + +static int an8855_regmap_phy_reset_page(struct an8855 *ddata, + int phy) __must_hold(&ddata->bus->mdio_lock) +{ + /* Check PHY page only for addr shared with switch */ + if (phy != ddata->switch_addr) + return 0; + + /* Don't restore page if it's not set to Switch page */ + if (ddata->current_page != AN8855_PHY_PAGE_EXTENDED_4) + return 0; + + /* + * Restore page to 0, PHY might change page right after but that + * will be ignored as it won't be a switch page. + */ + return an8855_mii_set_page(ddata, phy, AN8855_PHY_PAGE_STANDARD); +} + +static int an8855_regmap_phy_read(void *ctx, uint32_t reg, uint32_t *val) +{ + struct an8855_phy *ddata = ctx; + struct an8855 *core_ddata; + u32 addr = ddata->addr; + struct mii_bus *bus; + int ret; + + core_ddata = ddata->core; + bus = core_ddata->bus; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + ret = an8855_regmap_phy_reset_page(core_ddata, addr); + if (ret) + goto exit; + + ret = __mdiobus_read(bus, addr, reg); + if (ret >= 0) + *val = ret; + +exit: + mutex_unlock(&bus->mdio_lock); + + return ret < 0 ? ret : 0; +} + +static int an8855_regmap_phy_write(void *ctx, uint32_t reg, uint32_t val) +{ + struct an8855_phy *ddata = ctx; + struct an8855 *core_ddata; + u32 addr = ddata->addr; + struct mii_bus *bus; + int ret; + + core_ddata = ddata->core; + bus = core_ddata->bus; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + ret = an8855_regmap_phy_reset_page(core_ddata, addr); + if (ret) + goto exit; + + ret = __mdiobus_write(bus, addr, reg, val); + +exit: + mutex_unlock(&bus->mdio_lock); + + return ret; +} + +static const struct regmap_config an8855_phy_regmap_config = { + .reg_bits = 16, + .val_bits = 16, + .reg_read = an8855_regmap_phy_read, + .reg_write = an8855_regmap_phy_write, + .disable_locking = true, + .max_register = 0x1f, +}; + +static int an8855_read_switch_id(struct device *dev, struct regmap *regmap) +{ + u32 id; + int ret; + + ret = regmap_read(regmap, AN8855_CREV, &id); + if (ret) + return ret; + + if (id != AN8855_ID) { + dev_err(dev, "Detected Switch ID %x but %x was expected\n", + id, AN8855_ID); + return -ENODEV; + } + + return 0; +} + +static int an8855_phy_bus_register(struct device *dev, struct an8855 *ddata, + struct device_node *phy_np, + struct an8855_phy_bus *phy_bus_info) +{ + struct mdio_regmap_config mrc = { }; + struct an8855_phy *phy_ddata; + struct regmap *regmap; + u32 addr, phy_offset; + struct mii_bus *bus; + int ret; + + ret = of_property_read_u32(phy_np, "reg", &addr); + if (ret) + return ret; + + phy_offset = addr - ddata->switch_addr; + if (phy_offset >= AN8855_MAX_PHY_PORT) + return -EINVAL; + + phy_ddata = devm_kzalloc(dev, sizeof(*phy_ddata), GFP_KERNEL); + if (!phy_ddata) + return -ENOMEM; + + phy_ddata->addr = addr; + phy_ddata->core = ddata; + + regmap = devm_regmap_init(dev, NULL, phy_ddata, &an8855_phy_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "phy%d regmap initialization failed\n", + addr); + + mrc.regmap = regmap; + mrc.parent = dev; + mrc.valid_addr = addr; + snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-phy%u", dev_name(dev), addr); + + bus = devm_mdio_regmap_register(dev, &mrc); + if (IS_ERR(bus)) + return PTR_ERR(bus); + + if (addr == ddata->switch_addr) + ddata->phy_bus = bus; + + phy_bus_info->bus = bus; + phy_bus_info->addr = addr; + phy_bus_info->node = fwnode_handle_get(of_fwnode_handle(phy_np)); + + return 0; +} + +static int an8855_mdio_register(struct device *dev, struct an8855 *ddata, + struct an8855_phy_bus *phy_bus_infos) +{ + struct device_node *mdio_np; + int ret = 0; + int i = 0; + + mdio_np = of_get_child_by_name(dev->of_node, "mdio"); + if (!mdio_np) + return -ENODEV; + + for_each_available_child_of_node_scoped(mdio_np, phy_np) { + if (i >= AN8855_MAX_PHY_PORT) { + ret = -EINVAL; + goto exit; + } + + ret = an8855_phy_bus_register(dev, ddata, phy_np, + &phy_bus_infos[i]); + if (ret) + goto exit; + + i++; + } + +exit: + of_node_put(mdio_np); + if (ret) { + while (i--) + fwnode_handle_put(phy_bus_infos[i].node); + + return ret; + } + + return i; +} + +static int an8855_probe(struct mdio_device *mdiodev) +{ + struct an8855_phy_bus phy_bus_infos[AN8855_MAX_PHY_PORT] = { }; + struct device *dev = &mdiodev->dev; + struct regmap *regmap; + struct an8855 *ddata; + int num_phys; + int i, ret; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + ddata->bus = mdiodev->bus; + ddata->switch_addr = mdiodev->addr; + /* No DMA for mdiobus, mute warning for DMA mask not set */ + dev->dma_mask = &dev->coherent_dma_mask; + + /* Register virtual MDIO for each PHY */ + num_phys = an8855_mdio_register(dev, ddata, phy_bus_infos); + if (num_phys < 0) + return num_phys; + + regmap = devm_regmap_init(dev, NULL, ddata, &an8855_regmap_config); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err_probe(dev, ret, "regmap initialization failed\n"); + goto err_put_fwnodes; + } + + /* Reset PHY page for switch address */ + mutex_lock_nested(&ddata->bus->mdio_lock, MDIO_MUTEX_NESTED); + ret = an8855_mii_set_page(ddata, ddata->switch_addr, + AN8855_PHY_PAGE_STANDARD); + mutex_unlock(&ddata->bus->mdio_lock); + if (ret) + goto err_put_fwnodes; + + ret = an8855_read_switch_id(dev, regmap); + if (ret) + goto err_put_fwnodes; + + /* Release global PHY power down */ + ret = regmap_write(regmap, AN8855_RG_GPHY_AFE_PWD, 0x0); + if (ret) + goto err_put_fwnodes; + + /* Register PHYs */ + for (i = 0; i < num_phys; i++) { + ret = fwnode_mdiobus_register_phy(phy_bus_infos[i].bus, + phy_bus_infos[i].node, + phy_bus_infos[i].addr); + fwnode_handle_put(phy_bus_infos[i].node); + phy_bus_infos[i].node = NULL; + + if (ret) + goto err_put_fwnodes; + } + + return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, an8855_cells, + ARRAY_SIZE(an8855_cells), NULL, 0, + NULL); + +err_put_fwnodes: + for (i = 0; i < num_phys; i++) + if (phy_bus_infos[i].node) + fwnode_handle_put(phy_bus_infos[i].node); + + return ret; +} + +static const struct of_device_id an8855_of_match[] = { + { .compatible = "airoha,an8855" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, an8855_of_match); + +static struct mdio_driver an8855_driver = { + .probe = an8855_probe, + .mdiodrv.driver = { + .name = "an8855", + .of_match_table = an8855_of_match, + }, +}; +mdio_module_driver(an8855_driver); + +MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>"); +MODULE_DESCRIPTION("Driver for Airoha AN8855"); +MODULE_LICENSE("GPL"); -- 2.55.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [RESEND PATCH 2/2] mfd: an8855: Add support for Airoha AN8855 Switch 2026-10-21 11:34 ` [RESEND PATCH 2/2] mfd: an8855: Add support for Airoha AN8855 Switch Christian Marangi @ 2026-10-21 12:00 ` sashiko-bot 0 siblings, 0 replies; 6+ messages in thread From: sashiko-bot @ 2026-10-21 12:00 UTC (permalink / raw) To: Christian Marangi, mfd, devicetree; +Cc: robh, conor+dt, lee Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: - [High] mfd: an8855: missing reset-gpios handling in an8855_probe() - [Medium] mfd: an8855: missing MFD_AIROHA_AN8855 dependency on NVMEM_AN8855_EFUSE - [Low] mfd: an8855: mixing __free() and goto cleanup in an8855_mdio_register() -- commit f927c03e4e8ef367f1a168337fd8954240810d42 Author: Christian Marangi <ansuelsmth@gmail.com> mfd: an8855: Add support for Airoha AN8855 Switch This commit adds the core driver for the Airoha an8855 switch, registering virtual mdio buses via mdio-regmap for the internal phys along with child devices for the nvmem efuse provider and dsa switch. > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig > index e4fd4572472f9..afbdcec0fce8f 100644 > --- a/drivers/mfd/Kconfig > +++ b/drivers/mfd/Kconfig > @@ -54,6 +54,20 @@ config MFD_ALTERA_SYSMGR > using regmap_mmio accesses for ARM32 parts and SMC calls to > EL3 for ARM64 parts. > > +config MFD_AIROHA_AN8855 > + tristate "Airoha AN8855 Switch Core" > + select MFD_CORE > + select REGMAP > + select PHYLIB > + select MDIO_REGMAP > + depends on NETDEVICES && OF > + help > + Support for the Airoha AN8855 Switch Core. This is an SoC > + that provides various peripherals, to count, i2c, an Ethrnet > + Switch, a CPU timer, GPIO, eFUSE. > + > + Currently it provides a DSA switch and a NVMEM provider. > + [Severity: Medium] Should drivers/nvmem/Kconfig also be updated so NVMEM_AN8855_EFUSE depends on MFD_AIROHA_AN8855 || COMPILE_TEST? When drivers/nvmem/an8855-efuse.c was added in commit e2258cfd9b98 ("nvmem: an8855: Add support for Airoha AN8855 Switch EFUSE"), NVMEM_AN8855_EFUSE had depends on MFD_AIROHA_AN8855 || COMPILE_TEST, which was later narrowed by commit 4796eaafd6a1 ("nvmem: an8855: drop an unused Kconfig symbol") to: drivers/nvmem/Kconfig: config NVMEM_AN8855_EFUSE tristate "Airoha AN8855 eFuse support" depends on COMPILE_TEST Without restoring MFD_AIROHA_AN8855 in that dependency, NVMEM_AN8855_EFUSE cannot be enabled in non-COMPILE_TEST builds for the an8855-efuse cell registered in an8855_cells. [ ... ] > diff --git a/drivers/mfd/airoha-an8855.c b/drivers/mfd/airoha-an8855.c > new file mode 100644 > index 0000000000000..6a270555db5cf > --- /dev/null > +++ b/drivers/mfd/airoha-an8855.c > @@ -0,0 +1,579 @@ [ ... ] > +static int an8855_mdio_register(struct device *dev, struct an8855 *ddata, > + struct an8855_phy_bus *phy_bus_infos) > +{ > + struct device_node *mdio_np; > + int ret = 0; > + int i = 0; > + > + mdio_np = of_get_child_by_name(dev->of_node, "mdio"); > + if (!mdio_np) > + return -ENODEV; > + > + for_each_available_child_of_node_scoped(mdio_np, phy_np) { > + if (i >= AN8855_MAX_PHY_PORT) { > + ret = -EINVAL; > + goto exit; > + } > + > + ret = an8855_phy_bus_register(dev, ddata, phy_np, > + &phy_bus_infos[i]); > + if (ret) > + goto exit; > + > + i++; > + } > + > +exit: > + of_node_put(mdio_np); [Severity: Low] Could mdio_np be declared with __free(device_node) or should the loop avoid mixing for_each_available_child_of_node_scoped() with goto cleanup labels? an8855_mdio_register() uses for_each_available_child_of_node_scoped(), which declares phy_np with __free(device_node), while also jumping to the exit label with goto to clean up mdio_np and phy_bus_infos[i].node, which goes against the cleanup helper guidelines in include/linux/cleanup.h against mixing __free() and goto in the same function. > + if (ret) { > + while (i--) > + fwnode_handle_put(phy_bus_infos[i].node); > + > + return ret; > + } > + > + return i; > +} > + > +static int an8855_probe(struct mdio_device *mdiodev) > +{ > + struct an8855_phy_bus phy_bus_infos[AN8855_MAX_PHY_PORT] = { }; > + struct device *dev = &mdiodev->dev; > + struct regmap *regmap; > + struct an8855 *ddata; > + int num_phys; > + int i, ret; > + > + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); > + if (!ddata) > + return -ENOMEM; > + > + ddata->bus = mdiodev->bus; > + ddata->switch_addr = mdiodev->addr; > + /* No DMA for mdiobus, mute warning for DMA mask not set */ > + dev->dma_mask = &dev->coherent_dma_mask; > + > + /* Register virtual MDIO for each PHY */ > + num_phys = an8855_mdio_register(dev, ddata, phy_bus_infos); > + if (num_phys < 0) > + return num_phys; > + > + regmap = devm_regmap_init(dev, NULL, ddata, &an8855_regmap_config); > + if (IS_ERR(regmap)) { > + ret = PTR_ERR(regmap); > + dev_err_probe(dev, ret, "regmap initialization failed\n"); > + goto err_put_fwnodes; > + } > + > + /* Reset PHY page for switch address */ > + mutex_lock_nested(&ddata->bus->mdio_lock, MDIO_MUTEX_NESTED); > + ret = an8855_mii_set_page(ddata, ddata->switch_addr, > + AN8855_PHY_PAGE_STANDARD); > + mutex_unlock(&ddata->bus->mdio_lock); > + if (ret) > + goto err_put_fwnodes; > + > + ret = an8855_read_switch_id(dev, regmap); > + if (ret) > + goto err_put_fwnodes; > + > + /* Release global PHY power down */ > + ret = regmap_write(regmap, AN8855_RG_GPHY_AFE_PWD, 0x0); > + if (ret) > + goto err_put_fwnodes; [Severity: High] How is reset-gpios deasserted before accessing the switch registers in an8855_probe()? Documentation/devicetree/bindings/mfd/airoha,an8855.yaml defines reset-gpios on the top-level airoha,an8855 node, and drivers/mfd/airoha-an8855.c includes linux/gpio/consumer.h, but an8855_probe() never requests or deasserts the reset gpio. Because airoha,an8855 is registered as a non-phy mdio_device without MDIO_DEVICE_FLAG_PHY, mdiobus_register_device() in drivers/net/phy/mdio_device.c skips mdio_device_register_reset(): if (mdiodev->flags & MDIO_DEVICE_FLAG_PHY) { err = mdio_device_register_reset(mdiodev); if (err) return err; /* Assert the reset signal */ mdio_device_reset(mdiodev, 1); } If reset-gpios is asserted at boot, won't an8855_mii_set_page() and an8855_read_switch_id() fail to read AN8855_ID over mdio and cause an8855_probe() to fail with -ENODEV? [ ... ] -- Sashiko AI review · https://sashiko.dev/#/patchset/20261021113419.283015-1-ansuelsmth@gmail.com?part=2 ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-10-21 13:35 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-10-21 11:34 [RESEND PATCH 0/2] mfd: add Airoha AN8855 switch support Christian Marangi 2026-10-21 11:34 ` [RESEND PATCH 1/2] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Christian Marangi 2026-10-21 11:46 ` sashiko-bot 2026-10-21 13:35 ` Rob Herring (Arm) 2026-10-21 11:34 ` [RESEND PATCH 2/2] mfd: an8855: Add support for Airoha AN8855 Switch Christian Marangi 2026-10-21 12:00 ` sashiko-bot
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