[PATCH] arm64: dts: qcom: sc8280xp: add missing Iris IOMMU SID

[PATCH] arm64: dts: qcom: sc8280xp: add missing Iris IOMMU SID

[Xilin Wu]

The Iris VPU on SC8280XP can issue memory transactions using stream ID
0x2a07. With only the 0x2a00 SID described in the IOMMU list, those
transactions are not attached to the Iris IOMMU domain and can trigger a
non-secure SMMU global fault during video decode.

This was observed while decoding H.264, where the faulting address fell
inside a DPB buffer mapped for the Iris device.

Add the missing 0x2a07 stream ID so both Iris access paths are mapped by
the SMMU.

Note that the issue was observed using Gen2 HFI firmware.

Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index d17475c3e66c..4ab01ef9ac05 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4268,7 +4268,8 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
 					     "video-mem";
 
 			operating-points-v2 = <&iris_opp_table>;
-			iommus = <&apps_smmu 0x2a00 0x400>;
+			iommus = <&apps_smmu 0x2a00 0x400>,
+				 <&apps_smmu 0x2a07 0x400>;
 			memory-region = <&pil_video_mem>;
 
 			status = "disabled";

---
base-commit: 151a134a4e6ec66f69db8750c66006f5207f7a9d
change-id: 20261030-sc8280xp-iris-iommu-aaf3fb5774c8

Best regards,
--  
Xilin Wu <sophon@radxa.com>

Re: [PATCH] arm64: dts: qcom: sc8280xp: add missing Iris IOMMU SID

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] arm64: dts: qcom: sc8280xp iris iommus exceeds sm8250-venus schema maxItems
--

commit 6441bb3f503ae341ba67b0bfcbe9378b5b24f71b
Author: Xilin Wu <sophon@radxa.com>

arm64: dts: qcom: sc8280xp: add missing Iris IOMMU SID

This commit adds the missing 0x2a07 IOMMU stream ID to the Iris VPU node
on SC8280XP so that both access paths are mapped by the SMMU during video
decode.

> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index d17475c3e66c9..4ab01ef9ac053 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -4268,7 +4268,8 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
>  					     "video-mem";
>  
>  			operating-points-v2 = <&iris_opp_table>;
> -			iommus = <&apps_smmu 0x2a00 0x400>;
> +			iommus = <&apps_smmu 0x2a00 0x400>,
> +				 <&apps_smmu 0x2a07 0x400>;

[Severity: Low]
Does Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml also
need an update for this change?

In arch/arm64/boot/dts/qcom/sc8280xp.dtsi, the iris (video-codec@aa00000)
node matches Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml:

  properties:
    compatible:
      oneOf:
        - const: qcom,sm8250-venus
        - items:
            - enum:
                - qcom,sc8280xp-iris
                - qcom,sm8350-iris
            - const: qcom,sm8250-venus
  ...
    iommus:
      maxItems: 1

Adding a second entry to iommus without updating maxItems in the binding
schema causes dtbs_check to fail on SC8280XP and SA8540P device trees.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261030-sc8280xp-iris-iommu-v1-1-1e3fb8562b3d@radxa.com?part=1