[PATCH 0/2] arm64: dts: allwinner: h6: Enable GPU and CPU DVFS on more boards

[PATCH 0/2] arm64: dts: allwinner: h6: Enable GPU and CPU DVFS on more boards

[Jernej Skrabec]

Most H6 boards don't use the GPU OPP table, and the Orange Pi One Plus
and Lite2 lack CPU DVFS as well, so their GPU and CPU run at a fixed
clock rate. This series enables both.

Jernej Skrabec (2):
  arm64: dts: allwinner: h6: Add GPU OPP table to all boards
  arm64: dts: allwinner: h6: orangepi: Enable CPU frequency scaling

 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 1 +
 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi  | 6 ++++++
 arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts   | 1 +
 arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi     | 1 +
 4 files changed, 9 insertions(+)


base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
-- 
2.43.0

[PATCH 1/2] arm64: dts: allwinner: h6: Add GPU OPP table to all boards

[Jernej Skrabec]

Only the Beelink GS1 and TaiQiCat A01 include the H6 GPU OPP table, so
the GPU on all other H6 boards runs at a fixed clock rate. Include it on
the remaining boards, so devfreq can scale the GPU clock for either
better performance or lower power consumption.

The table also works with a fixed GPU supply, as on Tanix boards.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 1 +
 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi  | 1 +
 arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts   | 1 +
 arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi     | 1 +
 4 files changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index dc7381c944c9..ce82aa265cfd 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -5,6 +5,7 @@
 
 #include "sun50i-h6.dtsi"
 #include "sun50i-h6-cpu-opp.dtsi"
+#include "sun50i-h6-gpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
index e34dbb992021..2948369cd659 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
@@ -5,6 +5,7 @@
 /dts-v1/;
 
 #include "sun50i-h6.dtsi"
+#include "sun50i-h6-gpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index fa7a765ee828..f4a5a2215ea2 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -5,6 +5,7 @@
 
 #include "sun50i-h6.dtsi"
 #include "sun50i-h6-cpu-opp.dtsi"
+#include "sun50i-h6-gpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
index bb7de37c0d58..f08077175549 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
@@ -5,6 +5,7 @@
 
 #include "sun50i-h6.dtsi"
 #include "sun50i-h6-cpu-opp.dtsi"
+#include "sun50i-h6-gpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
-- 
2.43.0

[PATCH 2/2] arm64: dts: allwinner: h6: orangepi: Enable CPU frequency scaling

[Jernej Skrabec]

The Orange Pi One Plus and Lite2 lack the CPU OPP table and CPU supply,
so the CPU never scales its frequency. Add both, like on Orange Pi 3.
OPPs above the regulator constraints stay unused.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
index 2948369cd659..b7351b1db97c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
@@ -5,6 +5,7 @@
 /dts-v1/;
 
 #include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
 #include "sun50i-h6-gpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
@@ -65,6 +66,10 @@ reg_vcc5v: vcc5v {
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdca>;
+};
+
 &de {
 	status = "okay";
 };
-- 
2.43.0

Re: [PATCH 1/2] arm64: dts: allwinner: h6: Add GPU OPP table to all boards

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] arm64: dts: allwinner: h6: missing regulator-ramp-delay on reg_dcdcc
--

commit ba32fa6c0b22c915eb543aebaebb44bdfbbd45e8
Author: Jernej Skrabec <jernej.skrabec@gmail.com>

arm64: dts: allwinner: h6: Add GPU OPP table to all boards

This commit includes sun50i-h6-gpu-opp.dtsi across the remaining Allwinner
H6 board device trees so that devfreq can scale the GPU clock rate and
voltage.

> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
> index e34dbb9920216..2948369cd659b 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
> @@ -5,6 +5,7 @@
>  /dts-v1/;
>  
>  #include "sun50i-h6.dtsi"
> +#include "sun50i-h6-gpu-opp.dtsi"

[Severity: Medium]
Should reg_dcdcc in sun50i-h6-orangepi.dtsi also specify
regulator-ramp-delay = <2500> when enabling the GPU OPP table here?

In arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi, &gpu uses
mali-supply = <&reg_dcdcc>, which is currently defined without a ramp delay:

	reg_dcdcc: dcdcc {
		regulator-enable-ramp-delay = <32000>;
		regulator-min-microvolt = <810000>;
		regulator-max-microvolt = <1080000>;
		regulator-name = "vdd-gpu";
	};

In drivers/regulator/axp20x-regulator.c, axp806_regulators defines DCDCC via
AXP_DESC_RANGES(), which leaves desc.ramp_delay as 0 and uses
axp20x_ops_range without a set_voltage_time or set_voltage_time_sel callback.

When Panfrost devfreq scales up the GPU OPP on OrangePi One Plus or OrangePi
Lite2, the call chain:

	_set_opp()
	  -> _generic_set_opp_regulator()
	  -> regulator_set_voltage_Unlocked()
	  -> _regulator_do_set_voltage()
	  -> _regulator_set_voltage_time()

checks rdev->constraints->ramp_delay and rdev->desc->ramp_delay. Because both
are 0, _regulator_set_voltage_time() returns 0 and _set_opp() immediately
raises CLK_GPU via opp_table->config_clks() before the AXP805 DCDCC buck
regulator output has ramped up to the target voltage.

All other AXP805-based H6 board device trees that include
sun50i-h6-gpu-opp.dtsi (sun50i-h6-beelink-gs1.dts, sun50i-h6-orangepi-3.dts,
sun50i-h6-pine-h64.dts, and sun50i-h6-taiqicat-a01.dts) set
regulator-ramp-delay = <2500> on reg_dcdcc (added in commits 67533f873ad7,
ebae33c3f6ce, and fe79ea577be8).

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261104184940.882833-1-jernej.skrabec@gmail.com?part=1

Re: [PATCH 2/2] arm64: dts: allwinner: h6: orangepi: Enable CPU frequency scaling

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] arm64: dts: allwinner: h6: missing regulator-ramp-delay in orangepi.dtsi
--

commit 756d3d30d1a6d15f42bf1d5d2b8437c122fdde4e
Author: Jernej Skrabec <jernej.skrabec@gmail.com>

arm64: dts: allwinner: h6: orangepi: Enable CPU frequency scaling

This commit includes sun50i-h6-cpu-opp.dtsi and sets cpu-supply on cpu0 to
reg_dcdca in sun50i-h6-orangepi.dtsi to enable CPU frequency scaling on the
Orange Pi One Plus and Lite2.

> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
> index 2948369cd659b..b7351b1db97c5 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
> @@ -5,6 +5,7 @@
>  /dts-v1/;
>  
>  #include "sun50i-h6.dtsi"
> +#include "sun50i-h6-cpu-opp.dtsi"
>  #include "sun50i-h6-gpu-opp.dtsi"
>  
>  #include <dt-bindings/gpio/gpio.h>
> @@ -65,6 +66,10 @@ reg_vcc5v: vcc5v {
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&reg_dcdca>;
> +};

[Severity: Medium]
Should reg_dcdca (and reg_dcdcc) in sun50i-h6-orangepi.dtsi also specify
regulator-ramp-delay = <2500>; now that voltage scaling is enabled on
reg_dcdca?

In sun50i-h6-orangepi.dtsi, reg_dcdca and reg_dcdcc currently omit
regulator-ramp-delay:

			reg_dcdca: dcdca {
				regulator-always-on;
				regulator-min-microvolt = <810000>;
				regulator-max-microvolt = <1080000>;
				regulator-name = "vdd-cpu";
			};

			reg_dcdcc: dcdcc {
				regulator-enable-ramp-delay = <32000>;
				regulator-min-microvolt = <810000>;
				regulator-max-microvolt = <1080000>;
				regulator-name = "vdd-gpu";
			};

In drivers/regulator/axp20x-regulator.c, the AXP806 DCDCA and DCDCC
descriptors are defined with AXP_DESC_RANGES(), which leaves desc->ramp_delay
at 0 and uses axp20x_ops_range without set_voltage_time or
set_voltage_time_sel callbacks.

When cpufreq-dt (or panfrost devfreq) scales up to a higher OPP via:

  dev_pm_opp_set_rate()
    -> _set_opp()
      -> _opp_config_regulator_single()
        -> _set_opp_voltage()
          -> regulator_set_voltage_triplet()
            -> _regulator_do_set_voltage()
              -> _regulator_set_voltage_time()

_regulator_set_voltage_time() checks:

	if (rdev->constraints->ramp_delay)
		ramp_delay = rdev->constraints->ramp_delay;
	else if (rdev->desc->ramp_delay)
		ramp_delay = rdev->desc->ramp_delay;

Without regulator-ramp-delay in the device tree, _regulator_set_voltage_time()
returns 0, so _regulator_do_set_voltage() skips waiting for the AXP805 buck
converter output voltage to ramp up before _opp_config_clk_single() calls
clk_set_rate() to switch the PLL to the higher frequency.

Other AXP805-based H6 board device trees (including sun50i-h6-orangepi-3.dts
in commit ebae33c3f6cee9, sun50i-h6-beelink-gs1.dts in commit 67533f873ad7e2,
sun50i-h6-pine-h64.dts in commit fe79ea577be81e, and
sun50i-h6-taiqicat-a01.dts) set regulator-ramp-delay = <2500>; on reg_dcdca
and reg_dcdcc.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261104184940.882833-1-jernej.skrabec@gmail.com?part=2