* [PATCH] arm64: versal: dts: Add PCIe reset IDs
@ 2026-11-12 8:43 Michal Simek
2026-11-12 8:56 ` sashiko-bot
0 siblings, 1 reply; 2+ messages in thread
From: Michal Simek @ 2026-11-12 8:43 UTC (permalink / raw)
To: linux-kernel, monstr, michal.simek, git
Cc: Sandeep Reddy Ghanapuram, Conor Dooley, Krzysztof Kozlowski,
Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/ZYNQ ARCHITECTURE
From: Sandeep Reddy Ghanapuram <sandeep.reddy-ghanapuram@amd.com>
Add VERSAL_RST_XAPE_0 through VERSAL_RST_XAPE_1 reset binding
definitions for CPM6 PCIe controllers. These IDs
will be used by the PM reset controller to manage PCIe resets.
Signed-off-by: Sandeep Reddy Ghanapuram <sandeep.reddy-ghanapuram@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h b/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h
index fe00f4a0ba65..f8189d1cbc12 100644
--- a/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h
+++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h
@@ -102,5 +102,7 @@
#define VERSAL_RST_XRAM (0xc30c05dU)
#define VERSAL_RST_AIE_ARRAY (0xc10405eU)
#define VERSAL_RST_AIE_SHIM (0xc10405fU)
+#define VERSAL_RST_XAPE0 (0xc410115U)
+#define VERSAL_RST_XAPE1 (0xc410116U)
#endif
---
--
2.43.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] arm64: versal: dts: Add PCIe reset IDs
2026-11-12 8:43 [PATCH] arm64: versal: dts: Add PCIe reset IDs Michal Simek
@ 2026-11-12 8:56 ` sashiko-bot
0 siblings, 0 replies; 2+ messages in thread
From: sashiko-bot @ 2026-11-12 8:56 UTC (permalink / raw)
To: Michal Simek
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, robh,
conor+dt
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] arm64: versal: dts: macro name mismatch between commit log and
header
--
commit a1880b29ae774d1de118295c96e2eedcfea5ec9e
Author: Sandeep Reddy Ghanapuram <sandeep.reddy-ghanapuram@amd.com>
arm64: versal: dts: Add PCIe reset IDs
This commit adds the XAPE0 and XAPE1 reset ID definitions for CPM6 PCIe
controllers to the Versal reset header.
> diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h b/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h
> index fe00f4a0ba65b..f8189d1cbc129 100644
> --- a/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h
> +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h
> @@ -102,5 +102,7 @@
> #define VERSAL_RST_XRAM (0xc30c05dU)
> #define VERSAL_RST_AIE_ARRAY (0xc10405eU)
> #define VERSAL_RST_AIE_SHIM (0xc10405fU)
> +#define VERSAL_RST_XAPE0 (0xc410115U)
> +#define VERSAL_RST_XAPE1 (0xc410116U)
[Severity: Low]
This isn't a bug, but the commit message says this adds VERSAL_RST_XAPE_0
and VERSAL_RST_XAPE_1, whereas the macros defined here omit the
underscore before the index (VERSAL_RST_XAPE0 and VERSAL_RST_XAPE1).
--
Sashiko AI review · https://sashiko.dev/#/patchset/b06d55abdb0671d9dc987057f44c989317e19680.1794473022.git.michal.simek@amd.com?part=1
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