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* [PATCH v2 1/2] arm64: dts: qcom: msm8937: Fix CPU4 thermal trip point type
@ 2026-11-12 12:00 Krzysztof Kozlowski
  2026-11-12 12:00 ` [PATCH v2 2/2] arm64: dts: qcom: sm8150: Fix missing wake-gpios in PCI Krzysztof Kozlowski
  0 siblings, 1 reply; 3+ messages in thread
From: Krzysztof Kozlowski @ 2026-11-12 12:00 UTC (permalink / raw)
  To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Dang Huynh,
	Barnabás Czémán, Dmitry Baryshkov, Bhupesh Sharma,
	linux-arm-msm, devicetree, linux-kernel
  Cc: Krzysztof Kozlowski, Sashiko, stable

CPU4 thermal zone, unlike the rest CPU5-7, has reversed types for
75 and 85 *C trips: the "passive", not "hot" should be used for alert
triggering cooling device.  Wrong types could cause missing thermal
throttling of CPU4.

Reported-by: Sashiko <sashiko-bot@kernel.org>
Closes: https://sashiko.dev/#/bug/linux-3ae74c01-648b-445f-9a65-114b2d3b2ac6
Fixes: a829f6f2e8a7 ("arm64: dts: qcom: Add initial support for MSM8937")
Cc: <stable@vger.kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/msm8937.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8937.dtsi b/arch/arm64/boot/dts/qcom/msm8937.dtsi
index 7de6447de48f..6729b39c3f2e 100644
--- a/arch/arm64/boot/dts/qcom/msm8937.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8937.dtsi
@@ -1942,13 +1942,13 @@ trips {
 				cpu4_alert0: trip-point0 {
 					temperature = <75000>;
 					hysteresis = <2000>;
-					type = "passive";
+					type = "hot";
 				};
 
 				cpu4_alert1: trip-point1 {
 					temperature = <85000>;
 					hysteresis = <2000>;
-					type = "hot";
+					type = "passive";
 				};
 
 				cpu4_crit: cpu-crit {
-- 
2.53.0


^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [PATCH v2 2/2] arm64: dts: qcom: sm8150: Fix missing wake-gpios in PCI
  2026-11-12 12:00 [PATCH v2 1/2] arm64: dts: qcom: msm8937: Fix CPU4 thermal trip point type Krzysztof Kozlowski
@ 2026-11-12 12:00 ` Krzysztof Kozlowski
  2026-11-12 12:08   ` sashiko-bot
  0 siblings, 1 reply; 3+ messages in thread
From: Krzysztof Kozlowski @ 2026-11-12 12:00 UTC (permalink / raw)
  To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Dang Huynh,
	Barnabás Czémán, Dmitry Baryshkov, Bhupesh Sharma,
	linux-arm-msm, devicetree, linux-kernel
  Cc: Krzysztof Kozlowski

Qualcomm PCI bindings do not allow an "enable-gpio" property.  Linux
drivers do not use it, either.  The pin matches slot wake-gpios, though.

Fixes: a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

---

Changes in v2:
1. Use wake-gpios instead
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 293fcbacff34..328e8be1638f 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -2019,8 +2019,6 @@ pcie1: pcie@1c08000 {
 
 			power-domains = <&gcc PCIE_1_GDSC>;
 
-			enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
-
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie1_default_state>;
 
@@ -2033,6 +2031,7 @@ pcie@0 {
 
 				phys = <&pcie1_phy>;
 				reset-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
+				wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
 
 				#address-cells = <3>;
 				#size-cells = <2>;
-- 
2.53.0


^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH v2 2/2] arm64: dts: qcom: sm8150: Fix missing wake-gpios in PCI
  2026-11-12 12:00 ` [PATCH v2 2/2] arm64: dts: qcom: sm8150: Fix missing wake-gpios in PCI Krzysztof Kozlowski
@ 2026-11-12 12:08   ` sashiko-bot
  0 siblings, 0 replies; 3+ messages in thread
From: sashiko-bot @ 2026-11-12 12:08 UTC (permalink / raw)
  To: Krzysztof Kozlowski, devicetree; +Cc: robh, conor+dt

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] arm64: dts: qcom: sm8150: pcie1 wake-gpios uses
  GPIO_ACTIVE_HIGH polarity
--

commit 809c46a66ec46c6ef99060dec4a500e026dc122f
Author: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

arm64: dts: qcom: sm8150: Fix missing wake-gpios in PCI

This commit replaces the unused enable-gpio property on pcie1 with a
wake-gpios property in its pcie@0 root port node.

> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index b9846b424a938..d667e38914519 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -2028,8 +2028,6 @@ pcie1: pcie@1c08000 {
>  
>  			power-domains = <&gcc PCIE_1_GDSC>;
>  
> -			enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
> -
>  			pinctrl-names = "default";
>  			pinctrl-0 = <&pcie1_default_state>;
>  
> @@ -2042,6 +2040,7 @@ pcie@0 {
>  
>  				phys = <&pcie1_phy>;
>  				reset-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
> +				wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;

[Severity: Medium]
Should wake-gpios use GPIO_ACTIVE_LOW here, matching pcie0 after commit
463d931d6a66 ("arm64: dts: qcom: sm8150: Fix PCIe WAKE# GPIO polarity")?

PCIe WAKE# is active-low and pcie1_default_state configures gpio104 with
bias-pull-up.  With GPIO_ACTIVE_HIGH, pci_configure_wake_irq() requests the
wake interrupt as IRQ_TYPE_LEVEL_HIGH, which triggers immediately while the
pulled-up WAKE# line is idle during suspend.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261112120030.99510-3-krzysztof.kozlowski@oss.qualcomm.com?part=2

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2026-11-12 12:08 UTC | newest]

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2026-11-12 12:00 [PATCH v2 1/2] arm64: dts: qcom: msm8937: Fix CPU4 thermal trip point type Krzysztof Kozlowski
2026-11-12 12:00 ` [PATCH v2 2/2] arm64: dts: qcom: sm8150: Fix missing wake-gpios in PCI Krzysztof Kozlowski
2026-11-12 12:08   ` sashiko-bot

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