[PATCH] arm64: dts: qcom: qcs6490-rb3gen2: Disable PCIe ASPM L1ss

[PATCH] arm64: dts: qcom: qcs6490-rb3gen2: Disable PCIe ASPM L1ss

[Sushrut Shree Trivedi]

On the QCS6490 RB3gen2 platform, there is no mechanism for the
PCIe endpoints connected to TC9563 switch to assert #CLKREQ and
initiate a L1ss exit on the upstream link between the PCIe1 RC and
TC9563 upstream port. Hence, once the upstream link enters L1ss
and the Renesas uPD720201 endpoint connected to the switch downstream
port tries to initiate an L1 exit, a link down is seen. This is
expected because the upstream link is still in L1ss and PCIe refclk
is cut-off.

To avoid this issue, disable ASPM L1ss on the upstream link of TC9563
switch to keep the PCIe refclk always on.

Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 909039816a21..df26c78e8a8a 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -891,6 +891,8 @@ pcie@0,0 {
 		pinctrl-0 = <&tc9563_resx_n>;
 		pinctrl-names = "default";
 
+		aspm-no-l1ss;
+
 		pcie1_switch0_dsp1: pcie@1,0 {
 			reg = <0x20800 0x0 0x0 0x0 0x0>;
 			#address-cells = <3>;

---
base-commit: 630059a5a632377b9b7b487baccde92b7ae1dd47
change-id: 20261112-rb3gen2_disable_l1ss-dee3d53fa53a

Best regards,
-- 
Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>

Re: [PATCH] arm64: dts: qcom: qcs6490-rb3gen2: Disable PCIe ASPM L1ss

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] arm64: dts: qcom: qcs6490-rb3gen2: missing Fixes trailer for
  TC9563 L1ss fix
--

commit 9d5417f567397369628afe2e5d17be0a24757085
Author: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>

> arm64: dts: qcom: qcs6490-rb3gen2: Disable PCIe ASPM L1ss
>
> On the QCS6490 RB3gen2 platform, there is no mechanism for the
> PCIe endpoints connected to TC9563 switch to assert #CLKREQ and
> initiate a L1ss exit on the upstream link between the PCIe1 RC and
> TC9563 upstream port. Hence, once the upstream link enters L1ss
> and the Renesas uPD720201 endpoint connected to the switch downstream
> port tries to initiate an L1 exit, a link down is seen. This is
> expected because the upstream link is still in L1ss and PCIe refclk
> is cut-off.
>
> To avoid this issue, disable ASPM L1ss on the upstream link of TC9563
> switch to keep the PCIe refclk always on.
>
> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>

[Severity: Low]
Since this fixes a PCIe link-down failure on the TC9563 switch upstream port,
should the commit message include a Fixes tag?

  Fixes: aa7b4bbcb3a1 ("arm64: dts: qcom: qcs6490-rb3gen2: Add TC9563 PCIe switch node")

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-rb3gen2_disable_l1ss-v1-1-aeefbf366595@oss.qualcomm.com?part=1