From: Mark Brown <broonie@kernel.org>
To: Marc Zyngier <maz@kernel.org>, Joey Gouly <joey.gouly@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Will Deacon <will@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
Oliver Upton <oupton@kernel.org>
Cc: Dave Martin <Dave.Martin@arm.com>, Fuad Tabba <tabba@google.com>,
Mark Rutland <mark.rutland@arm.com>,
Ben Horgan <ben.horgan@arm.com>,
Jean-Philippe Brucker <jpb@kernel.org>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Peter Maydell <peter.maydell@linaro.org>,
Eric Auger <eric.auger@redhat.com>,
Mark Brown <broonie@kernel.org>
Subject: [PATCH v12 15/29] KVM: arm64: Support SME control registers
Date: Thu, 09 Jul 2026 19:27:36 +0100 [thread overview]
Message-ID: <20260709-kvm-arm64-sme-v12-15-d0301d79ef58@kernel.org> (raw)
In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org>
SME is configured by the system registers SMCR_EL1 and SMCR_EL2, add
definitions and userspace access for them. These control the SME vector
length in a manner similar to that for SVE and also have feature enable
bits for SME2 and FA64. A subsequent patch will add management of them
for guests as part of the general floating point context switch, as is
done for the equivalent SVE registers.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/kvm_emulate.h | 15 +++++++++++++++
arch/arm64/include/asm/kvm_host.h | 2 ++
arch/arm64/include/asm/vncr_mapping.h | 1 +
arch/arm64/kvm/nested.c | 5 +++++
arch/arm64/kvm/sys_regs.c | 31 ++++++++++++++++++++++++++++++-
5 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
index 994afbf479fc..b5dc8a4c320a 100644
--- a/arch/arm64/include/asm/kvm_emulate.h
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -90,6 +90,15 @@ static inline void kvm_inject_nested_sve_trap(struct kvm_vcpu *vcpu)
kvm_inject_nested_sync(vcpu, esr);
}
+static inline void kvm_inject_nested_sme_trap(struct kvm_vcpu *vcpu,
+ u64 smtc)
+{
+ u64 esr = FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_SME) |
+ ESR_ELx_IL | smtc;
+
+ kvm_inject_nested_sync(vcpu, esr);
+}
+
#if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__)
static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
{
@@ -689,4 +698,10 @@ static inline void vcpu_set_hcrx(struct kvm_vcpu *vcpu)
vcpu->arch.hcrx_el2 |= HCRX_EL2_EnASR;
}
}
+
+static inline bool guest_hyp_sme_traps_enabled(const struct kvm_vcpu *vcpu)
+{
+ return __guest_hyp_cptr_xen_trap_enabled(vcpu, SMEN);
+}
+
#endif /* __ARM64_KVM_EMULATE_H__ */
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 858341eb1e8f..796b6e3a50f7 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -546,6 +546,7 @@ enum vcpu_sysreg {
MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */
CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */
ZCR_EL2, /* SVE Control Register (EL2) */
+ SMCR_EL2, /* SME Control Register (EL2) */
/* Any VNCR-capable reg goes after this point */
MARKER(__VNCR_START__),
@@ -554,6 +555,7 @@ enum vcpu_sysreg {
VNCR(ACTLR_EL1),/* Auxiliary Control Register */
VNCR(CPACR_EL1),/* Coprocessor Access Control */
VNCR(ZCR_EL1), /* SVE Control */
+ VNCR(SMCR_EL1), /* SME Control */
VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */
VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */
VNCR(TCR_EL1), /* Translation Control Register */
diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm/vncr_mapping.h
index 14366d35ce82..c3bf92ac52d4 100644
--- a/arch/arm64/include/asm/vncr_mapping.h
+++ b/arch/arm64/include/asm/vncr_mapping.h
@@ -44,6 +44,7 @@
#define VNCR_HDFGWTR_EL2 0x1D8
#define VNCR_ZCR_EL1 0x1E0
#define VNCR_HAFGRTR_EL2 0x1E8
+#define VNCR_SMCR_EL1 0x1F0
#define VNCR_TTBR0_EL1 0x200
#define VNCR_TTBR1_EL1 0x210
#define VNCR_FAR_EL1 0x220
diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
index fb54f6dad995..50e25ab9b604 100644
--- a/arch/arm64/kvm/nested.c
+++ b/arch/arm64/kvm/nested.c
@@ -1920,6 +1920,11 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
resx.res1 = ZCR_ELx_RES1;
set_sysreg_masks(kvm, ZCR_EL2, resx);
+ /* SMCR_EL2 - bits 8:4 are RAZ/WI so treat them as RES0 */
+ resx.res0 = SMCR_ELx_RES0 | GENMASK_ULL(8, 4);
+ resx.res1 = SMCR_ELx_RES1;
+ set_sysreg_masks(kvm, SMCR_EL2, resx);
+
out:
for (enum vcpu_sysreg sr = __SANITISED_REG_START__; sr < NR_SYS_REGS; sr++)
__vcpu_rmw_sys_reg(vcpu, sr, |=, 0);
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index ba8a3ed8f5ff..24bbe30c075a 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -121,6 +121,7 @@ static enum sr_loc_attr locate_direct_register(const struct kvm_vcpu *vcpu,
case ELR_EL1:
case SPSR_EL1:
case ZCR_EL1:
+ case SMCR_EL1:
case SCTLR2_EL1:
/*
* EL1 registers which have an ELx2 mapping are loaded if
@@ -241,6 +242,7 @@ static u64 read_sr_from_cpu(enum vcpu_sysreg reg)
case ELR_EL1: val = read_sysreg_s(SYS_ELR_EL12); break;
case SPSR_EL1: val = read_sysreg_s(SYS_SPSR_EL12); break;
case ZCR_EL1: val = read_sysreg_s(SYS_ZCR_EL12); break;
+ case SMCR_EL1: val = read_sysreg_s(SYS_SMCR_EL12); break;
case SCTLR2_EL1: val = read_sysreg_s(SYS_SCTLR2_EL12); break;
case TPIDR_EL0: val = read_sysreg_s(SYS_TPIDR_EL0); break;
case TPIDRRO_EL0: val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
@@ -279,6 +281,7 @@ static void write_sr_to_cpu(enum vcpu_sysreg reg, u64 val)
case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break;
case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break;
+ case SMCR_EL1: write_sysreg_s(val, SYS_SMCR_EL12); break;
case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break;
case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
@@ -2830,6 +2833,12 @@ static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu,
return __el2_visibility(vcpu, rd, sve_visibility);
}
+static unsigned int sme_el2_visibility(const struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *rd)
+{
+ return __el2_visibility(vcpu, rd, sme_visibility);
+}
+
static unsigned int vncr_el2_visibility(const struct kvm_vcpu *vcpu,
const struct sys_reg_desc *rd)
{
@@ -2872,6 +2881,23 @@ static bool access_zcr_el2(struct kvm_vcpu *vcpu,
return true;
}
+static bool access_smcr_el2(struct kvm_vcpu *vcpu,
+ struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ if (guest_hyp_sme_traps_enabled(vcpu)) {
+ kvm_inject_nested_sme_trap(vcpu, ESR_ELx_SME_ISS_SMTC_SME_DISABLED);
+ return false;
+ }
+
+ if (!p->is_write)
+ p->regval = __vcpu_sys_reg(vcpu, SMCR_EL2);
+ else
+ __vcpu_assign_sys_reg(vcpu, SMCR_EL2, p->regval);
+
+ return true;
+}
+
static bool access_gic_vtr(struct kvm_vcpu *vcpu,
struct sys_reg_params *p,
const struct sys_reg_desc *r)
@@ -3386,7 +3412,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
{ SYS_DESC(SYS_TRFCR_EL1), undef_access },
{ SYS_DESC(SYS_SMPRI_EL1), undef_access },
- { SYS_DESC(SYS_SMCR_EL1), undef_access },
+ { SYS_DESC(SYS_SMCR_EL1), NULL, reset_val, SMCR_EL1, 0, .visibility = sme_visibility },
{ SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
{ SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
{ SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
@@ -3754,6 +3780,9 @@ static const struct sys_reg_desc sys_reg_descs[] = {
EL2_REG_VNCR(HCRX_EL2, reset_val, 0),
+ EL2_REG_FILTERED(SMCR_EL2, access_smcr_el2, reset_val, 0,
+ sme_el2_visibility),
+
EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
--
2.47.3
next prev parent reply other threads:[~2026-07-09 18:41 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-09 18:27 [PATCH v12 00/29] KVM: arm64: Implement support for SME Mark Brown
2026-07-09 18:27 ` [PATCH v12 01/29] arm64/sysreg: Define full value read/modify/write helpers Mark Brown
2026-07-09 18:27 ` [PATCH v12 02/29] arm64/fpsimd: Update FA64 and ZT0 enables when loading SME state Mark Brown
2026-07-09 18:27 ` [PATCH v12 03/29] arm64/fpsimd: Decide to save ZT0 and streaming mode FFR at bind time Mark Brown
2026-07-09 18:27 ` [PATCH v12 04/29] arm64/sve: Factor virtualizable VL discovery out of SVE specific code Mark Brown
2026-07-09 18:27 ` [PATCH v12 05/29] arm64/fpsimd: Determine maximum virtualisable SME vector length Mark Brown
2026-07-09 18:27 ` [PATCH v12 06/29] KVM: arm64: Handle FEAT_IDST for guest accesses to hidden registers Mark Brown
2026-07-09 18:27 ` [PATCH v12 07/29] KVM: arm64: Pull ctxt_has_ helpers to start of sysreg-sr.h Mark Brown
2026-07-09 18:27 ` [PATCH v12 08/29] KVM: arm64: Rename SVE finalization constants to be more general Mark Brown
2026-07-09 18:27 ` [PATCH v12 09/29] KVM: arm64: Define internal features for SME Mark Brown
2026-07-09 18:27 ` [PATCH v12 10/29] KVM: arm64: Rename sve_state_reg_region Mark Brown
2026-07-09 18:27 ` [PATCH v12 11/29] KVM: arm64: Store vector lengths in an array Mark Brown
2026-07-09 18:27 ` [PATCH v12 12/29] KVM: arm64: Factor SVE code out of fpsimd_lazy_switch_to_host() Mark Brown
2026-07-09 18:27 ` [PATCH v12 13/29] KVM: arm64: Document the KVM ABI for SME Mark Brown
2026-07-09 18:27 ` [PATCH v12 14/29] KVM: arm64: Implement SME vector length configuration Mark Brown
2026-07-09 18:27 ` Mark Brown [this message]
2026-07-09 18:27 ` [PATCH v12 16/29] KVM: arm64: Support TPIDR2_EL0 Mark Brown
2026-07-09 18:27 ` [PATCH v12 17/29] KVM: arm64: Support SME identification registers for guests Mark Brown
2026-07-09 18:27 ` [PATCH v12 18/29] KVM: arm64: Support SME priority registers Mark Brown
2026-07-09 18:27 ` [PATCH v12 19/29] KVM: arm64: Support userspace access to streaming mode Z and P registers Mark Brown
2026-07-09 18:27 ` [PATCH v12 20/29] KVM: arm64: Flush register state on writes to SVCR.SM and SVCR.ZA Mark Brown
2026-07-09 18:27 ` [PATCH v12 21/29] KVM: arm64: Expose SME specific state to userspace Mark Brown
2026-07-09 18:27 ` [PATCH v12 22/29] KVM: arm64: Context switch SME state for guests Mark Brown
2026-07-09 18:27 ` [PATCH v12 23/29] KVM: arm64: Handle SME exceptions Mark Brown
2026-07-09 18:27 ` [PATCH v12 24/29] KVM: arm64: Expose SME to nested guests Mark Brown
2026-07-09 18:27 ` [PATCH v12 25/29] KVM: arm64: Provide interface for configuring and enabling SME for guests Mark Brown
2026-07-09 18:27 ` [PATCH v12 26/29] KVM: arm64: selftests: Remove spurious check for single bit safe values Mark Brown
2026-07-09 18:27 ` [PATCH v12 27/29] KVM: arm64: selftests: Skip impossible invalid value tests Mark Brown
2026-07-09 18:27 ` [PATCH v12 28/29] KVM: arm64: selftests: Add SME system registers to get-reg-list Mark Brown
2026-07-09 18:27 ` [PATCH v12 29/29] KVM: arm64: selftests: Add SME to set_id_regs test Mark Brown
2026-07-10 8:43 ` [PATCH v12 00/29] KVM: arm64: Implement support for SME Fuad Tabba
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