Re: [PATCH v4 05/14] iio: adc: Add AD7768 and AD7768-4 core support

[Janani Sunil <jananisunil.dev@gmail.com>]

On 8/22/26 19:30, David Lechner wrote:
>
> On 8/21/26 9:06 AM, Janani Sunil wrote:
>> Add core support for the AD7768 and AD7768-4 simultaneous sampling ADCs.
>> Configure supplies, clock and reset, use a custom regmap bus for the SPI
>> protocol, and parse the enabled channels and input buffer settings from
>> devicetree.
>>
>> Connect the converter to an IIO backend for buffered capture with CRC,
>> provide a fixed safe wideband sampling configuration and add runtime
>> power management.
>>
>> Signed-off-by: Janani Sunil <janani.sunil@analog.com>
>> ---
...
>> +static int ad7768_regmap_read(void *context, const void *reg_buf,
>> +			      size_t reg_size, void *val_buf, size_t val_size)
>> +{
>> +	struct ad7768_state *st = spi_get_drvdata(context);
>> +	struct spi_device *spi = context;
>> +	struct spi_transfer t[] = {
>> +		{
>> +			.tx_buf = &st->d16,
>> +			.len = sizeof(st->d16),
>> +			.cs_change = 1,
>> +		}, {
>> +			/*
>> +			 * Register responses are delayed by one CS frame. While
>> +			 * receiving the response to this read, the device also
>> +			 * decodes another command on SDI. Repeat the read
>> +			 * command to avoid sending an unspecified dummy
>> +			 * command.
> Could this have unintended concequences? E.g. register writes that have
> size-effects, like reset or clearing status registers.

Repeating the command cannot trigger reset or other write side effects. The device also does not have any read-to-clear registers.

Thanks,
Jan