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From: Yazen Ghannam <yazen.ghannam@amd.com>
To: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
Cc: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bp@suse.de" <bp@suse.de>,
	"tony.luck@intel.com" <tony.luck@intel.com>,
	"x86@kernel.org" <x86@kernel.org>
Subject: [v2,5/6] x86/MCE: Save MCA control bits that get set in hardware
Date: Thu, 11 Apr 2019 20:18:04 +0000	[thread overview]
Message-ID: <20190411201743.43195-6-Yazen.Ghannam@amd.com> (raw)

From: Yazen Ghannam <yazen.ghannam@amd.com>

The OS is expected to write all bits in MCA_CTL. However, only
implemented bits get set in the hardware.

Read back MCA_CTL so that the value in the hardware is saved and
reported through sysfs.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20190408141205.12376-6-Yazen.Ghannam@amd.com

v1->v2:
* No change.

 arch/x86/kernel/cpu/mce/core.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

-- 
2.17.1

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 0fe29140ecab..71662133c70c 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1565,10 +1565,13 @@ static void __mcheck_cpu_init_clear_banks(void)
 	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
 		struct mce_bank *b = &this_cpu_read(mce_banks)[i];
 
-		if (!b->init)
-			continue;
-		wrmsrl(msr_ops.ctl(i), b->ctl);
-		wrmsrl(msr_ops.status(i), 0);
+		if (b->init) {
+			wrmsrl(msr_ops.ctl(i), b->ctl);
+			wrmsrl(msr_ops.status(i), 0);
+		}
+
+		/* Save bits set in hardware. */
+		rdmsrl(msr_ops.ctl(i), b->ctl);
 	}
 }
 
@@ -2312,8 +2315,10 @@ static void mce_reenable_cpu(void)
 	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
 		struct mce_bank *b = &this_cpu_read(mce_banks)[i];
 
-		if (b->init)
+		if (b->init) {
 			wrmsrl(msr_ops.ctl(i), b->ctl);
+			rdmsrl(msr_ops.ctl(i), b->ctl);
+		}
 	}
 }
 

WARNING: multiple messages have this Message-ID (diff)
From: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
To: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
Cc: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bp@suse.de" <bp@suse.de>,
	"tony.luck@intel.com" <tony.luck@intel.com>,
	"x86@kernel.org" <x86@kernel.org>
Subject: [PATCH v2 5/6] x86/MCE: Save MCA control bits that get set in hardware
Date: Thu, 11 Apr 2019 20:18:04 +0000	[thread overview]
Message-ID: <20190411201743.43195-6-Yazen.Ghannam@amd.com> (raw)
Message-ID: <20190411201804.LK_Zw3IDjbo4K3xdayTPXp_ZFrhRVlJ4dzBxU-vmEMU@z> (raw)
In-Reply-To: <20190411201743.43195-1-Yazen.Ghannam@amd.com>

From: Yazen Ghannam <yazen.ghannam@amd.com>

The OS is expected to write all bits in MCA_CTL. However, only
implemented bits get set in the hardware.

Read back MCA_CTL so that the value in the hardware is saved and
reported through sysfs.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20190408141205.12376-6-Yazen.Ghannam@amd.com

v1->v2:
* No change.

 arch/x86/kernel/cpu/mce/core.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 0fe29140ecab..71662133c70c 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1565,10 +1565,13 @@ static void __mcheck_cpu_init_clear_banks(void)
 	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
 		struct mce_bank *b = &this_cpu_read(mce_banks)[i];
 
-		if (!b->init)
-			continue;
-		wrmsrl(msr_ops.ctl(i), b->ctl);
-		wrmsrl(msr_ops.status(i), 0);
+		if (b->init) {
+			wrmsrl(msr_ops.ctl(i), b->ctl);
+			wrmsrl(msr_ops.status(i), 0);
+		}
+
+		/* Save bits set in hardware. */
+		rdmsrl(msr_ops.ctl(i), b->ctl);
 	}
 }
 
@@ -2312,8 +2315,10 @@ static void mce_reenable_cpu(void)
 	for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
 		struct mce_bank *b = &this_cpu_read(mce_banks)[i];
 
-		if (b->init)
+		if (b->init) {
 			wrmsrl(msr_ops.ctl(i), b->ctl);
+			rdmsrl(msr_ops.ctl(i), b->ctl);
+		}
 	}
 }
 
-- 
2.17.1


         reply	other threads:[~2019-04-11 20:18 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-11 20:18 [PATCH v2 0/6] Handle MCA banks in a per_cpu way Ghannam, Yazen
2019-04-11 20:18 ` [v2,1/6] x86/MCE: Make struct mce_banks[] static Yazen Ghannam
2019-04-11 20:18   ` [PATCH v2 1/6] " Ghannam, Yazen
2019-04-11 20:18 ` [v2,2/6] x86/MCE: Handle MCA controls in a per_cpu way Yazen Ghannam
2019-04-11 20:18   ` [PATCH v2 2/6] " Ghannam, Yazen
2019-04-16 10:21   ` [v2,2/6] " Borislav Petkov
2019-04-16 10:21     ` [PATCH v2 2/6] " Borislav Petkov
2019-04-11 20:18 ` [v2,3/6] x86/MCE/AMD: Don't cache block addresses on SMCA systems Yazen Ghannam
2019-04-11 20:18   ` [PATCH v2 3/6] " Ghannam, Yazen
2019-04-16 13:44   ` [v2,3/6] " Borislav Petkov
2019-04-16 13:44     ` [PATCH v2 3/6] " Borislav Petkov
2019-04-11 20:18 ` [v2,4/6] x86/MCE: Make number of MCA banks per_cpu Yazen Ghannam
2019-04-11 20:18   ` [PATCH v2 4/6] " Ghannam, Yazen
2019-04-16 13:55   ` [v2,4/6] " Borislav Petkov
2019-04-16 13:55     ` [PATCH v2 4/6] " Borislav Petkov
2019-04-16 17:36   ` [v2,4/6] " Borislav Petkov
2019-04-16 17:36     ` [PATCH v2 4/6] " Borislav Petkov
2019-04-11 20:18 ` [v2,6/6] x86/MCE: Treat MCE bank as initialized if control bits set in hardware Yazen Ghannam
2019-04-11 20:18   ` [PATCH v2 6/6] " Ghannam, Yazen
2019-04-11 20:18 ` Yazen Ghannam [this message]
2019-04-11 20:18   ` [PATCH v2 5/6] x86/MCE: Save MCA control bits that get " Ghannam, Yazen

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