Re: [PATCH v4 4/4] x86/mce: Add CMCI storm switching support for Zhaoxin

[Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>]

On 2024/10/12 15:13, Zhuo, Qiuxu wrote:
> 
> 
> [这封邮件来自外部发件人 谨防风险]
> 
>> From: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
>> [...]
>> Subject: [PATCH v4 4/4] x86/mce: Add CMCI storm switching support for
>> Zhaoxin
>>
>> From: Lyle Li <LyleLi@zhaoxin.com>
>>
>> Zhaoxin CPUs support CMCI compatible with Intel, because Zhaoxin's UCR error
>> is not reported through CMCI, and in order to be compatible with intel's CMCI
>> code, so add Zhaoxin CMCI storm toggle to support the new CMCI storm
>> switching in mce/intel.c, mce/zhaoxin.c, mce/threshold.c, and mce/internal.h.
> 
> Could you tweak and simplify the commit message, like this:
> 
>      Zhaoxin CPUs support CMCI which is compatible with Intel, but their UCR errors are
>      not reported through CMCI like Intel's. To be compatible with Intel's CMCI code,
>      add Zhaoxin's specific CMCI storm toggle.
> 
>> [...]
>> diff --git a/arch/x86/kernel/cpu/mce/internal.h
>> b/arch/x86/kernel/cpu/mce/internal.h
>> index 836e56027..086b833c5 100644
>> --- a/arch/x86/kernel/cpu/mce/internal.h
>> +++ b/arch/x86/kernel/cpu/mce/internal.h
>> @@ -7,7 +7,7 @@
>>
>>   #include <linux/device.h>
>>   #include <asm/mce.h>
>> -
>> +#include <linux/spinlock.h>
> 
> Please sort the header files, like this:
> 
>      #include <linux/device.h>
>      #include <linux/spinlock.h>
> 
>      #include <asm/mce.h>
> 
> And keep a blank line here as it was.
> 
>>   enum severity_level {
>>        MCE_NO_SEVERITY,
>>        MCE_DEFERRED_SEVERITY,
>> @@ -334,11 +334,16 @@ static __always_inline u32 mca_msr_reg(int bank,
>> enum mca_msr reg)  }
> [...]
> 
> Other than that:
> 
>      Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>

Thank you for reviewing this patchset. v5 will be resent according to 
your suggestion.

Sincerely
TonyWWang-oc