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From: "Naik, Avadhut" <avadnaik@amd.com>
To: "Zhuo, Qiuxu" <qiuxu.zhuo@intel.com>,
	"x86@kernel.org" <x86@kernel.org>,
	"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
	"linux-trace-kernel@vger.kernel.org"
	<linux-trace-kernel@vger.kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bp@alien8.de" <bp@alien8.de>, "Luck, Tony" <tony.luck@intel.com>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"mingo@redhat.com" <mingo@redhat.com>,
	"rostedt@goodmis.org" <rostedt@goodmis.org>,
	"mchehab@kernel.org" <mchehab@kernel.org>,
	"yazen.ghannam@amd.com" <yazen.ghannam@amd.com>,
	"john.allen@amd.com" <john.allen@amd.com>,
	Avadhut Naik <avadhut.naik@amd.com>
Subject: [PATCH v6 3/5] x86/mce, EDAC/mce_amd: Add support for new MCA_SYND{1,2} registers
Date: Thu, 17 Oct 2024 16:49:21 -0500	[thread overview]
Message-ID: <8c71d83b-4dd2-4411-aac2-81284bf3a9df@amd.com> (raw)
In-Reply-To: <CY8PR11MB7134178B954B4DFFF6AEF81689472@CY8PR11MB7134.namprd11.prod.outlook.com>



On 10/17/2024 02:09, Zhuo, Qiuxu wrote:
>> From: Avadhut Naik <avadhut.naik@amd.com>
>> [...]
>> --- a/include/trace/events/mce.h
>> +++ b/include/trace/events/mce.h
>> @@ -43,6 +43,7 @@ TRACE_EVENT(mce_record,
>>  		__field(	u8,		bank		)
>>  		__field(	u8,		cpuvendor	)
>>  		__field(	u32,		microcode	)
>> +		__dynamic_array(u8, v_data, sizeof(err->vendor))
>>  	),
>>
>>  	TP_fast_assign(
>> @@ -65,9 +66,10 @@ TRACE_EVENT(mce_record,
>>  		__entry->bank		= err->m.bank;
>>  		__entry->cpuvendor	= err->m.cpuvendor;
>>  		__entry->microcode	= err->m.microcode;
>> +		memcpy(__get_dynamic_array(v_data), &err->vendor,
>> +sizeof(err->vendor));
>>  	),
>>
>> -	TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016Lx, IPID: %016Lx,
>> ADDR: %016Lx, MISC: %016Lx, SYND: %016Lx, RIP: %02x:<%016Lx>, TSC: %llx,
>> PPIN: %llx, vendor: %u, CPUID: %x, time: %llu, socket: %u, APIC: %x,
>> microcode: %x",
>> +	TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016llx, IPID: %016llx,
>> +ADDR: %016llx, MISC: %016llx, SYND: %016llx, RIP: %02x:<%016llx>, TSC:
>> +%llx, PPIN: %llx, vendor: %u, CPUID: %x, time: %llu, socket: %u, APIC:
>> +%x, microcode: %x, vendor data: %s",
>>  		__entry->cpu,
>>  		__entry->mcgcap, __entry->mcgstatus,
>>  		__entry->bank, __entry->status,
>> @@ -83,7 +85,8 @@ TRACE_EVENT(mce_record,
>>  		__entry->walltime,
>>  		__entry->socketid,
>>  		__entry->apicid,
>> -		__entry->microcode)
>> +		__entry->microcode,
>> +		__print_dynamic_array(v_data, 8))
> 
> What is the 2nd parameter '8' about? 
> 
> The 2nd parameter is about the element size. 
> The element type is 'u8', as defined above. 
> Therefore:
> 
>     __print_dynamic_array(v_data, sizeof(u8)))
>     
> -Qiuxu
> 
IIUC, the second parameter above determines how the dynamic
array is parsed and logged. The value of 8 means that the
array will be traversed with a u64 pointer i.e. data within
the array will be logged by the tracepoint in chunks of 8
bytes. Something like below:

vendor data: {0x3a726f7461636f4c,0x30434d305020,0x27000003fd}

This seems convenient since, AFAIK, MCA registers on x86-64
are of 8 bytes.

If we use sizeof(u8) (which equates to 1) above, then u8
pointer will be used for traversing the dynamic array and each
byte within the registers will be logged individually.
Something like below.

vendor data: {0x4c,0x6f,0x63,0x61,0x74,0x6f,0x72,0x3a,0x20,0x50,0x30,0x4d,0x43,0x30,0x0,0x0,0xfd,0x3,0x0,0x0,0x27,0x0,0x0,0x0}

Combined with endianness of the processor, this seems somewhat
inconvenient to decipher. Would you agree?

> [...]

-- 
Thanks,
Avadhut Naik

  reply	other threads:[~2024-10-17 21:49 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-16  6:36 [PATCH v6 0/5] MCE wrapper and support for new SMCA syndrome MSRs Avadhut Naik
2024-10-16  6:36 ` [PATCH v6 1/5] x86/mce: Add wrapper for struct mce to export vendor specific info Avadhut Naik
2024-10-17  6:02   ` Zhuo, Qiuxu
2024-10-17 18:09     ` Naik, Avadhut
2024-10-16  6:36 ` [PATCH v6 2/5] tracing: Add __print_dynamic_array() helper Avadhut Naik
2024-10-17  6:58   ` Zhuo, Qiuxu
2024-10-17 13:54     ` Steven Rostedt
2024-10-18  2:34       ` Zhuo, Qiuxu
2024-10-16  6:36 ` [PATCH v6 3/5] x86/mce, EDAC/mce_amd: Add support for new MCA_SYND{1,2} registers Avadhut Naik
2024-10-17  7:09   ` Zhuo, Qiuxu
2024-10-17 21:49     ` Naik, Avadhut [this message]
2024-10-18  2:24       ` Zhuo, Qiuxu
2024-10-18 15:28         ` Luck, Tony
2024-10-21  6:29           ` Naik, Avadhut
2024-10-16  6:36 ` [PATCH v6 4/5] x86/mce/apei: Handle variable register array size Avadhut Naik
2024-10-16  6:36 ` [PATCH v6 5/5] EDAC/mce_amd: Add support for FRU Text in MCA Avadhut Naik

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