From: Shiju Jose <shiju.jose@huawei.com>
To: Dave Jiang <dave.jiang@intel.com>,
Alison Schofield <alison.schofield@intel.com>
Cc: "linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
"dan.j.williams@intel.com" <dan.j.williams@intel.com>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
"dave@stgolabs.net" <dave@stgolabs.net>,
"vishal.l.verma@intel.com" <vishal.l.verma@intel.com>,
"ira.weiny@intel.com" <ira.weiny@intel.com>,
"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
"bp@alien8.de" <bp@alien8.de>,
"tony.luck@intel.com" <tony.luck@intel.com>,
"lenb@kernel.org" <lenb@kernel.org>,
"Yazen.Ghannam@amd.com" <Yazen.Ghannam@amd.com>,
"mchehab@kernel.org" <mchehab@kernel.org>,
"nifan.cxl@gmail.com" <nifan.cxl@gmail.com>,
Linuxarm <linuxarm@huawei.com>,
tanxiaofei <tanxiaofei@huawei.com>,
"Zengtao (B)" <prime.zeng@hisilicon.com>,
"Roberto Sassu" <roberto.sassu@huawei.com>,
"kangkang.shen@futurewei.com" <kangkang.shen@futurewei.com>,
wanghuiqiang <wanghuiqiang@huawei.com>
Subject: RE: [PATCH v5 7/8] cxl/edac: Add CXL memory device memory sparing control feature
Date: Mon, 19 May 2025 21:34:13 +0000 [thread overview]
Message-ID: <a4d67defc88a4c03b88a1a5e9c7f9954@huawei.com> (raw)
In-Reply-To: <43de25e8-cbce-43f5-931d-3b9edc3f45eb@intel.com>
>-----Original Message-----
>From: Dave Jiang <dave.jiang@intel.com>
>Sent: 19 May 2025 22:16
>To: Alison Schofield <alison.schofield@intel.com>; Shiju Jose
><shiju.jose@huawei.com>
>Cc: linux-cxl@vger.kernel.org; dan.j.williams@intel.com; Jonathan Cameron
><jonathan.cameron@huawei.com>; dave@stgolabs.net;
>vishal.l.verma@intel.com; ira.weiny@intel.com; linux-edac@vger.kernel.org;
>linux-doc@vger.kernel.org; bp@alien8.de; tony.luck@intel.com;
>lenb@kernel.org; Yazen.Ghannam@amd.com; mchehab@kernel.org;
>nifan.cxl@gmail.com; Linuxarm <linuxarm@huawei.com>; tanxiaofei
><tanxiaofei@huawei.com>; Zengtao (B) <prime.zeng@hisilicon.com>; Roberto
>Sassu <roberto.sassu@huawei.com>; kangkang.shen@futurewei.com;
>wanghuiqiang <wanghuiqiang@huawei.com>
>Subject: Re: [PATCH v5 7/8] cxl/edac: Add CXL memory device memory sparing
>control feature
>
>
>
>On 5/19/25 2:01 PM, Alison Schofield wrote:
>> On Thu, May 15, 2025 at 12:59:23PM +0100, shiju.jose@huawei.com wrote:
>>> From: Shiju Jose <shiju.jose@huawei.com>
>>>
>>
>> snip
>>
>>> diff --git a/drivers/cxl/core/edac.c b/drivers/cxl/core/edac.c index
>>> 489c9996bfbc..395d56457931 100644
>>> --- a/drivers/cxl/core/edac.c
>>> +++ b/drivers/cxl/core/edac.c
>>> @@ -21,7 +21,17 @@
>>> #include "core.h"
>>> #include "trace.h"
>>>
>>> -#define CXL_NR_EDAC_DEV_FEATURES 2
>>> +#define CXL_NR_EDAC_DEV_FEATURES 6
>>> +
>>> +static bool cxl_is_memdev_memory_online(const struct cxl_memdev
>>> +*cxlmd) {
>>> + struct cxl_port *port = cxlmd->endpoint;
>>> +
>>> + if (port && cxl_num_decoders_committed(port))
>>> + return true;
>>> +
>>> + return false;
>>> +}
>>>
>>
>> Looks like above fcn needs to be inside the below #ifdef.
>> Smatch is warning this when EDAC_SCRUB is off
This warning is with 'EDAC_MEM_REPAIR' is off.
>>
>> drivers/cxl/core/edac.c:27:13: warning: ‘cxl_is_memdev_memory_online’
>defined but not used [-Wunused-function]
>> 27 | static bool cxl_is_memdev_memory_online(const struct
>> cxl_memdev *cxlmd)
>>
>>
>>> #ifdef CONFIG_CXL_EDAC_SCRUB
>
>I think the function can be moved to above cxl_mem_perform_sparing() as that
>is the only function that calls it. I'll do that when I apply if there's nothing else
>major need to be changed.
Yes. Moving under "#ifdef CONFIG_CXL_EDAC_MEM_REPAIR" which is present
at the start of memory repair features, solved this warning.
Presently 'cxl_is_memdev_memory_online' is used in cxl_mem_perform_sparing() and
cxl_mem_perform_ppr() only though I thought it will be used in other parts of the CXL code.
>
>DJ
>
>
>>
>> snip to end.
>>
>
Thanks,
Shiju
next prev parent reply other threads:[~2025-05-19 21:34 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-15 11:59 [PATCH v5 0/8] cxl: support CXL memory RAS features shiju.jose
2025-05-15 11:59 ` [PATCH v5 1/8] EDAC: Update documentation for the CXL memory patrol scrub control feature shiju.jose
2025-05-15 17:18 ` Randy Dunlap
2025-05-15 11:59 ` [PATCH v5 2/8] cxl: Update prototype of function get_support_feature_info() shiju.jose
2025-05-15 11:59 ` [PATCH v5 3/8] cxl/edac: Add CXL memory device patrol scrub control feature shiju.jose
2025-05-20 2:02 ` Alison Schofield
2025-05-20 10:21 ` Jonathan Cameron
2025-05-20 23:44 ` Shiju Jose
2025-05-15 11:59 ` [PATCH v5 4/8] cxl/edac: Add CXL memory device ECS " shiju.jose
2025-05-15 11:59 ` [PATCH v5 5/8] cxl/edac: Add support for PERFORM_MAINTENANCE command shiju.jose
2025-05-15 11:59 ` [PATCH v5 6/8] cxl/edac: Support for finding memory operation attributes from the current boot shiju.jose
2025-05-20 4:31 ` Alison Schofield
2025-05-20 23:45 ` Shiju Jose
2025-05-15 11:59 ` [PATCH v5 7/8] cxl/edac: Add CXL memory device memory sparing control feature shiju.jose
2025-05-19 21:01 ` Alison Schofield
2025-05-19 21:15 ` Dave Jiang
2025-05-19 21:34 ` Shiju Jose [this message]
2025-05-15 11:59 ` [PATCH v5 8/8] cxl/edac: Add CXL memory device soft PPR " shiju.jose
2025-05-15 17:23 ` Randy Dunlap
2025-05-20 1:36 ` [PATCH v5 0/8] cxl: support CXL memory RAS features Alison Schofield
2025-05-20 23:44 ` Shiju Jose
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